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khvzakkhvzak
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v0.8.3+luau614
1 parent 2b8b9fe commit 8321407

14 files changed

+291
-94
lines changed

‎Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[package]
22
name = "luau0-src"
3-
version = "0.8.2+luau613"
3+
version = "0.8.3+luau614"
44
authors = ["Aleksandr Orlenko <[email protected]>"]
55
edition = "2021"
66
repository = "https://github.com/khvzak/luau-src-rs"

‎luau/Ast/src/Parser.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ LUAU_FASTINTVARIABLE(LuauParseErrorLimit, 100)
1818
// See docs/SyntaxChanges.md for an explanation.
1919
LUAU_FASTFLAG(LuauCheckedFunctionSyntax)
2020
LUAU_FASTFLAGVARIABLE(LuauReadWritePropertySyntax, false)
21+
LUAU_FASTFLAGVARIABLE(DebugLuauDeferredConstraintResolution, false)
2122

2223
namespace Luau
2324
{
@@ -1339,7 +1340,7 @@ AstType* Parser::parseTableType(bool inDeclarationContext)
13391340
AstTableAccess access = AstTableAccess::ReadWrite;
13401341
std::optional<Location> accessLocation;
13411342

1342-
if (FFlag::LuauReadWritePropertySyntax)
1343+
if (FFlag::LuauReadWritePropertySyntax || FFlag::DebugLuauDeferredConstraintResolution)
13431344
{
13441345
if (lexer.current().type == Lexeme::Name && lexer.lookahead().type != ':')
13451346
{

‎luau/CodeGen/include/Luau/AssemblyBuilderA64.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,6 @@ class AssemblyBuilderA64
211211
void placeSR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, int shift = 0, int N = 0);
212212
void placeSR2(const char* name, RegisterA64 dst, RegisterA64 src, uint8_t op, uint8_t op2 = 0);
213213
void placeR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, uint8_t op2);
214-
void placeR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t sizes, uint8_t op, uint8_t op2);
215214
void placeR1(const char* name, RegisterA64 dst, RegisterA64 src, uint32_t op);
216215
void placeI12(const char* name, RegisterA64 dst, RegisterA64 src1, int src2, uint8_t op);
217216
void placeI16(const char* name, RegisterA64 dst, int src, uint8_t op, int shift = 0);
@@ -230,6 +229,7 @@ class AssemblyBuilderA64
230229
void placeBM(const char* name, RegisterA64 dst, RegisterA64 src1, uint32_t src2, uint8_t op);
231230
void placeBFM(const char* name, RegisterA64 dst, RegisterA64 src1, int src2, uint8_t op, int immr, int imms);
232231
void placeER(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t op, int shift);
232+
void placeVR(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint16_t op, uint8_t op2);
233233

234234
void place(uint32_t word);
235235

‎luau/CodeGen/include/Luau/IrData.h

+5-1
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,11 @@ enum class IrCmd : uint8_t
304304

305305
// Converts a double number to a vector with the value in X/Y/Z
306306
// A: double
307-
NUM_TO_VECTOR,
307+
NUM_TO_VEC,
308+
309+
// Adds VECTOR type tag to a vector, preserving X/Y/Z components
310+
// A: TValue
311+
TAG_VECTOR,
308312

309313
// Adjust stack top (L->top) to point at 'B' TValues *after* the specified register
310314
// This is used to return multiple values

‎luau/CodeGen/include/Luau/IrUtils.h

+2-1
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,8 @@ inline bool hasResult(IrCmd cmd)
186186
case IrCmd::UINT_TO_NUM:
187187
case IrCmd::NUM_TO_INT:
188188
case IrCmd::NUM_TO_UINT:
189-
case IrCmd::NUM_TO_VECTOR:
189+
case IrCmd::NUM_TO_VEC:
190+
case IrCmd::TAG_VECTOR:
190191
case IrCmd::SUBSTITUTE:
191192
case IrCmd::INVOKE_FASTCALL:
192193
case IrCmd::BITAND_UINT:

‎luau/CodeGen/src/AssemblyBuilderA64.cpp

+65-27
Original file line numberDiff line numberDiff line change
@@ -63,13 +63,22 @@ AssemblyBuilderA64::~AssemblyBuilderA64()
6363

6464
void AssemblyBuilderA64::mov(RegisterA64 dst, RegisterA64 src)
6565
{
66-
CODEGEN_ASSERT(dst.kind == KindA64::w || dst.kind == KindA64::x || dst == sp);
67-
CODEGEN_ASSERT(dst.kind == src.kind || (dst.kind == KindA64::x && src == sp) || (dst == sp && src.kind == KindA64::x));
66+
if (dst.kind != KindA64::q)
67+
{
68+
CODEGEN_ASSERT(dst.kind == KindA64::w || dst.kind == KindA64::x || dst == sp);
69+
CODEGEN_ASSERT(dst.kind == src.kind || (dst.kind == KindA64::x && src == sp) || (dst == sp && src.kind == KindA64::x));
6870

69-
if (dst == sp || src == sp)
70-
placeR1("mov", dst, src, 0b00'100010'0'000000000000);
71+
if (dst == sp || src == sp)
72+
placeR1("mov", dst, src, 0b00'100010'0'000000000000);
73+
else
74+
placeSR2("mov", dst, src, 0b01'01010);
75+
}
7176
else
72-
placeSR2("mov", dst, src, 0b01'01010);
77+
{
78+
CODEGEN_ASSERT(dst.kind == src.kind);
79+
80+
placeR1("mov", dst, src, 0b10'01110'10'1'00000'00011'1 | (src.index << 6));
81+
}
7382
}
7483

7584
void AssemblyBuilderA64::mov(RegisterA64 dst, int src)
@@ -575,12 +584,18 @@ void AssemblyBuilderA64::fadd(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
575584

576585
placeR3("fadd", dst, src1, src2, 0b11110'01'1, 0b0010'10);
577586
}
578-
else
587+
else if (dst.kind == KindA64::s)
579588
{
580-
CODEGEN_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s);
589+
CODEGEN_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
581590

582591
placeR3("fadd", dst, src1, src2, 0b11110'00'1, 0b0010'10);
583592
}
593+
else
594+
{
595+
CODEGEN_ASSERT(dst.kind == KindA64::q && src1.kind == KindA64::q && src2.kind == KindA64::q);
596+
597+
placeVR("fadd", dst, src1, src2, 0b0'01110'0'0'1, 0b11010'1);
598+
}
584599
}
585600

586601
void AssemblyBuilderA64::fdiv(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2)
@@ -591,12 +606,18 @@ void AssemblyBuilderA64::fdiv(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
591606

592607
placeR3("fdiv", dst, src1, src2, 0b11110'01'1, 0b0001'10);
593608
}
594-
else
609+
else if (dst.kind == KindA64::s)
595610
{
596-
CODEGEN_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s);
611+
CODEGEN_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
597612

598613
placeR3("fdiv", dst, src1, src2, 0b11110'00'1, 0b0001'10);
599614
}
615+
else
616+
{
617+
CODEGEN_ASSERT(dst.kind == KindA64::q && src1.kind == KindA64::q && src2.kind == KindA64::q);
618+
619+
placeVR("fdiv", dst, src1, src2, 0b1'01110'00'1, 0b11111'1);
620+
}
600621
}
601622

602623
void AssemblyBuilderA64::fmul(RegisterA64 dst, RegisterA64 src1, RegisterA64 src2)
@@ -607,12 +628,18 @@ void AssemblyBuilderA64::fmul(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
607628

608629
placeR3("fmul", dst, src1, src2, 0b11110'01'1, 0b0000'10);
609630
}
610-
else
631+
else if (dst.kind == KindA64::s)
611632
{
612-
CODEGEN_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s);
633+
CODEGEN_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
613634

614635
placeR3("fmul", dst, src1, src2, 0b11110'00'1, 0b0000'10);
615636
}
637+
else
638+
{
639+
CODEGEN_ASSERT(dst.kind == KindA64::q && src1.kind == KindA64::q && src2.kind == KindA64::q);
640+
641+
placeVR("fmul", dst, src1, src2, 0b1'01110'00'1, 0b11011'1);
642+
}
616643
}
617644

618645
void AssemblyBuilderA64::fneg(RegisterA64 dst, RegisterA64 src)
@@ -623,12 +650,18 @@ void AssemblyBuilderA64::fneg(RegisterA64 dst, RegisterA64 src)
623650

624651
placeR1("fneg", dst, src, 0b000'11110'01'1'0000'10'10000);
625652
}
626-
else
653+
else if (dst.kind == KindA64::s)
627654
{
628-
CODEGEN_ASSERT(dst.kind == KindA64::s && src.kind == KindA64::s);
655+
CODEGEN_ASSERT(src.kind == KindA64::s);
629656

630657
placeR1("fneg", dst, src, 0b000'11110'00'1'0000'10'10000);
631658
}
659+
else
660+
{
661+
CODEGEN_ASSERT(dst.kind == KindA64::q && src.kind == KindA64::q);
662+
663+
placeR1("fneg", dst, src, 0b011'01110'1'0'10000'01111'10);
664+
}
632665
}
633666

634667
void AssemblyBuilderA64::fsqrt(RegisterA64 dst, RegisterA64 src)
@@ -646,12 +679,18 @@ void AssemblyBuilderA64::fsub(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
646679

647680
placeR3("fsub", dst, src1, src2, 0b11110'01'1, 0b0011'10);
648681
}
649-
else
682+
else if (dst.kind == KindA64::s)
650683
{
651-
CODEGEN_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s);
684+
CODEGEN_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
652685

653686
placeR3("fsub", dst, src1, src2, 0b11110'00'1, 0b0011'10);
654687
}
688+
else
689+
{
690+
CODEGEN_ASSERT(dst.kind == KindA64::q && src1.kind == KindA64::q && src2.kind == KindA64::q);
691+
692+
placeVR("fsub", dst, src1, src2, 0b0'01110'10'1, 0b11010'1);
693+
}
655694
}
656695

657696
void AssemblyBuilderA64::ins_4s(RegisterA64 dst, RegisterA64 src, uint8_t index)
@@ -952,18 +991,6 @@ void AssemblyBuilderA64::placeR3(const char* name, RegisterA64 dst, RegisterA64
952991
commit();
953992
}
954993

955-
void AssemblyBuilderA64::placeR3(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint8_t sizes, uint8_t op, uint8_t op2)
956-
{
957-
if (logText)
958-
log(name, dst, src1, src2);
959-
960-
CODEGEN_ASSERT(dst.kind == KindA64::w || dst.kind == KindA64::x || dst.kind == KindA64::d || dst.kind == KindA64::q);
961-
CODEGEN_ASSERT(dst.kind == src1.kind && dst.kind == src2.kind);
962-
963-
place(dst.index | (src1.index << 5) | (op2 << 10) | (src2.index << 16) | (op << 21) | (sizes << 29));
964-
commit();
965-
}
966-
967994
void AssemblyBuilderA64::placeR1(const char* name, RegisterA64 dst, RegisterA64 src, uint32_t op)
968995
{
969996
if (logText)
@@ -1226,6 +1253,17 @@ void AssemblyBuilderA64::placeER(const char* name, RegisterA64 dst, RegisterA64
12261253
commit();
12271254
}
12281255

1256+
void AssemblyBuilderA64::placeVR(const char* name, RegisterA64 dst, RegisterA64 src1, RegisterA64 src2, uint16_t op, uint8_t op2)
1257+
{
1258+
if (logText)
1259+
logAppend(" %-12sv%d.4s,v%d.4s,v%d.4s\n", name, dst.index, src1.index, src2.index);
1260+
1261+
CODEGEN_ASSERT(dst.kind == KindA64::q && dst.kind == src1.kind && dst.kind == src2.kind);
1262+
1263+
place(dst.index | (src1.index << 5) | (op2 << 10) | (src2.index << 16) | (op << 21) | (1 << 30));
1264+
commit();
1265+
}
1266+
12291267
void AssemblyBuilderA64::place(uint32_t word)
12301268
{
12311269
CODEGEN_ASSERT(codePos < codeEnd);

‎luau/CodeGen/src/CodeGen.cpp

+1-3
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,6 @@ LUAU_FASTINTVARIABLE(CodegenHeuristicsBlockLimit, 32'768) // 32 K
5757
// Current value is based on some member variables being limited to 16 bits
5858
LUAU_FASTINTVARIABLE(CodegenHeuristicsBlockInstructionLimit, 65'536) // 64 K
5959

60-
LUAU_FASTFLAGVARIABLE(DisableNativeCodegenIfBreakpointIsSet, false)
61-
6260
namespace Luau
6361
{
6462
namespace CodeGen
@@ -302,7 +300,7 @@ void create(lua_State* L, AllocationCallback* allocationCallback, void* allocati
302300
ecb->close = onCloseState;
303301
ecb->destroy = onDestroyFunction;
304302
ecb->enter = onEnter;
305-
ecb->disable = FFlag::DisableNativeCodegenIfBreakpointIsSet ? onDisable : nullptr;
303+
ecb->disable = onDisable;
306304
}
307305

308306
void create(lua_State* L)

‎luau/CodeGen/src/IrDump.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -205,8 +205,10 @@ const char* getCmdName(IrCmd cmd)
205205
return "NUM_TO_INT";
206206
case IrCmd::NUM_TO_UINT:
207207
return "NUM_TO_UINT";
208-
case IrCmd::NUM_TO_VECTOR:
209-
return "NUM_TO_VECTOR";
208+
case IrCmd::NUM_TO_VEC:
209+
return "NUM_TO_VEC";
210+
case IrCmd::TAG_VECTOR:
211+
return "TAG_VECTOR";
210212
case IrCmd::ADJUST_STACK_TO_REG:
211213
return "ADJUST_STACK_TO_REG";
212214
case IrCmd::ADJUST_STACK_TO_TOP:

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