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su.c
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/******************************************************************************\
* Project: MSP Simulation Layer for Scalar Unit Operations *
* Authors: Iconoclast *
* Release: 2018.03.17 *
* License: CC0 Public Domain Dedication *
* *
* To the extent possible under law, the author(s) have dedicated all copyright *
* and related and neighboring rights to this software to the public domain *
* worldwide. This software is distributed without any warranty. *
* *
* You should have received a copy of the CC0 Public Domain Dedication along *
* with this software. *
* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
\******************************************************************************/
#include "su.h"
/*
* including modular interface structure to access configuration settings...
* Some of the parallel timing features require perfect timing or configs.
*/
#include "module.h"
/* cycles stuff */
#include "cycle.h"
long long int cycle;
/* Emulate timings */
/* memcpy() and memset() in SP DMA */
#include <string.h>
u32 inst_word;
u32 SR[NUMBER_OF_SCALAR_REGISTERS];
typedef VECTOR_OPERATION(*p_vector_func)(v16, v16);
extern OSTask_type task_type;
pu8 DRAM;
pu8 DMEM;
pu8 IMEM;
unsigned long su_max_address = 0x007FFFFFul;
NOINLINE void res_S(void)
{
message("RESERVED.");
return;
}
void set_PC(unsigned int address)
{
temp_PC = 0x04001000 + FIT_IMEM(address);
#ifndef EMULATE_STATIC_PC
stage = 1;
#endif
return;
}
pu32 CR[NUMBER_OF_CP0_REGISTERS];
u8 conf[32];
inline static void printhlelist(int reg)
{
if (task_type == 1 && CFG_DBG_LOG_GFX) {
if (reg == 25) {
printf("gfx: %08X %08X\n", SR[25], SR[24]);
}
}
if (task_type == 2 && CFG_DBG_LOG_SFX) {
if (reg == 25) {
printf("sfx: %08X %08X\n", SR[25], SR[24]);
}
}
}
int MF_SP_STATUS_TIMEOUT;
void SP_CP0_MF(unsigned int rt, unsigned int rd)
{
SR[rt] = *(CR[rd %= NUMBER_OF_CP0_REGISTERS]);
SR[zero] = 0x00000000;
if (rd == 0x7) {
if (CFG_MEND_SEMAPHORE_LOCK == 0)
return;
GET_RCP_REG(SP_SEMAPHORE_REG) = 0x00000001;
GET_RCP_REG(SP_STATUS_REG) |= SP_STATUS_HALT; /* temporary hack */
return;
}
#ifdef WAIT_FOR_CPU_HOST
if (rd == 0x4) {
MFC0_count[rt] += 1;
GET_RCP_REG(SP_STATUS_REG) |= (MFC0_count[rt] >= MF_SP_STATUS_TIMEOUT);
}
#endif
return;
}
static void MT_DMA_CACHE(unsigned int rt)
{
*CR[0x0] = SR[rt] & 0xFFFFFFF8ul; /* & 0x00001FF8 */
return; /* Reserved upper bits are ignored during DMA R/W. */
}
static void MT_DMA_DRAM(unsigned int rt)
{
*CR[0x1] = SR[rt] & 0xFFFFFFF8ul; /* & 0x00FFFFF8 */
return; /* Let the reserved bits get sent, but the pointer is 24-bit. */
}
static void MT_DMA_READ_LENGTH(unsigned int rt)
{
*CR[0x2] = SR[rt] | 07;
SP_DMA_READ();
return;
}
static void MT_DMA_WRITE_LENGTH(unsigned int rt)
{
*CR[0x3] = SR[rt] | 07;
SP_DMA_WRITE();
return;
}
static void MT_SP_STATUS(unsigned int rt)
{
pu32 MI_INTR_REG;
pu32 SP_STATUS_REG;
if (SR[rt] & 0xFE000040)
message("MTC0\nSP_STATUS"); /* bits we don't know what to do with */
SP_STATUS_REG = GET_RSP_INFO(SP_STATUS_REG);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000001) << 0);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000004) << 1);
/* DMA_BUSY, DMA_FULL, IO_FULL: No feature exists to clear these. */
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000020) << 5);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000080) << 6);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000200) << 7);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00000800) << 8);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00002000) << 9);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00008000) << 10);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00020000) << 11);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00080000) << 12);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00200000) << 13);
*SP_STATUS_REG &= ~(!!(SR[rt] & 0x00800000) << 14);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00000002) << 0);
/* No feature exists to set BROKE: (!!1 << 1) */
/* DMA_BUSY, DMA_FULL, IO_FULL: No feature exists to set these. */
*SP_STATUS_REG |= (!!(SR[rt] & 0x00000040) << 5);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00000100) << 6);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00000400) << 7); /* yield request? */
*SP_STATUS_REG |= (!!(SR[rt] & 0x00001000) << 8); /* yielded? */
*SP_STATUS_REG |= (!!(SR[rt] & 0x00004000) << 9); /* task done? */
*SP_STATUS_REG |= (!!(SR[rt] & 0x00010000) << 10);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00040000) << 11);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00100000) << 12);
*SP_STATUS_REG |= (!!(SR[rt] & 0x00400000) << 13);
*SP_STATUS_REG |= (!!(SR[rt] & 0x01000000) << 14);
MI_INTR_REG = GET_RSP_INFO(MI_INTR_REG);
*MI_INTR_REG &= ~((SR[rt] & 0x00000008) >> 3); /* SP_CLR_INTR */
*MI_INTR_REG |= ((SR[rt] & 0x00000010) >> 4); /* SP_SET_INTR */
*SP_STATUS_REG |= (SR[rt] & 0x00000010) >> 4; /* int set halt */
return;
}
static void MT_SP_RESERVED(unsigned int rt)
{
const u32 source = SR[rt] & 0x00000000ul; /* forced (zilmar, dox) */
GET_RCP_REG(SP_SEMAPHORE_REG) = source;
return;
}
static void MT_CMD_START(unsigned int rt)
{
const u32 source = SR[rt] & 0xFFFFFFF8ul; /* Funnelcube demo by marshallh */
if (GET_RCP_REG(DPC_BUFBUSY_REG)) /* lock hazards not implemented */
message("MTC0\nCMD_START");
GET_RCP_REG(DPC_END_REG)
= GET_RCP_REG(DPC_CURRENT_REG)
= GET_RCP_REG(DPC_START_REG)
= source;
return;
}
static void MT_CMD_END(unsigned int rt)
{
if (GET_RCP_REG(DPC_BUFBUSY_REG))
message("MTC0\nCMD_END"); /* This is just CA-related. */
GET_RCP_REG(DPC_END_REG) = SR[rt] & 0xFFFFFFF8ul;
GBI_phase();
return;
}
static void MT_CMD_STATUS(unsigned int rt)
{
pu32 DPC_STATUS_REG;
if (SR[rt] & 0xFFFFFD80ul) /* unsupported or reserved bits */
message("MTC0\nCMD_STATUS");
DPC_STATUS_REG = GET_RSP_INFO(DPC_STATUS_REG);
*DPC_STATUS_REG &= ~(!!(SR[rt] & 0x00000001) << 0);
*DPC_STATUS_REG |= (!!(SR[rt] & 0x00000002) << 0);
*DPC_STATUS_REG &= ~(!!(SR[rt] & 0x00000004) << 1);
*DPC_STATUS_REG |= (!!(SR[rt] & 0x00000008) << 1);
*DPC_STATUS_REG &= ~(!!(SR[rt] & 0x00000010) << 2);
*DPC_STATUS_REG |= (!!(SR[rt] & 0x00000020) << 2);
/* Some NUS-CIC-6105 SP tasks try to clear some DPC cycle timers. */
GET_RCP_REG(DPC_TMEM_REG) &= !(SR[rt] & 0x00000040) ? ~0u : 0u;
/* GET_RCP_REG(DPC_PIPEBUSY_REG) &= !(SR[rt] & 0x00000080) ? ~0u : 0u; */
/* GET_RCP_REG(DPC_BUFBUSY_REG) &= !(SR[rt] & 0x00000100) ? ~0u : 0u; */
GET_RCP_REG(DPC_CLOCK_REG) &= !(SR[rt] & 0x00000200) ? ~0u : 0u;
return;
}
static void MT_CMD_CLOCK(unsigned int rt)
{
message("MTC0\nCMD_CLOCK"); /* read-only?? */
GET_RCP_REG(DPC_CLOCK_REG) = SR[rt];
return; /* Appendix says this is RW; elsewhere it says R. */
}
static void MT_READ_ONLY(unsigned int rt)
{
static char write_to_read_only[] = "Invalid MTC0 from SR[00].";
write_to_read_only[21] = '0' + (unsigned char)rt/10;
write_to_read_only[22] = '0' + (unsigned char)rt%10;
message(write_to_read_only);
return;
}
static void (*SP_CP0_MT[NUMBER_OF_CP0_REGISTERS])(unsigned int) = {
MT_DMA_CACHE ,MT_DMA_DRAM ,MT_DMA_READ_LENGTH ,MT_DMA_WRITE_LENGTH,
MT_SP_STATUS ,MT_READ_ONLY ,MT_READ_ONLY ,MT_SP_RESERVED,
MT_CMD_START ,MT_CMD_END ,MT_READ_ONLY ,MT_CMD_STATUS,
MT_CMD_CLOCK ,MT_READ_ONLY ,MT_READ_ONLY ,MT_READ_ONLY
};
void SP_DMA_READ(void)
{
unsigned int offC, offD; /* SP cache and dynamic DMA pointers */
register unsigned int length;
register unsigned int count;
register unsigned int skip;
length = (GET_RCP_REG(SP_RD_LEN_REG) & 0x00000FFFul) >> 0;
count = (GET_RCP_REG(SP_RD_LEN_REG) & 0x000FF000ul) >> 12;
skip = (GET_RCP_REG(SP_RD_LEN_REG) & 0xFFF00000ul) >> 20;
#ifdef _DEBUG
length |= 07; /* already corrected by mtc0 */
#endif
++length;
++count;
skip += length;
do {
register unsigned int i;
i = 0;
--count;
do {
offC = (count*length + *CR[0x0] + i) & 0x00001FF8ul;
offD = (count*skip + *CR[0x1] + i) & 0x00FFFFF8ul;
i += 0x008;
if (offD > su_max_address) {
memset(DMEM + offC, 0x00, 8);
continue;
}
memcpy(DMEM + offC, DRAM + offD, 8);
} while (i < length);
} while (count);
if ((*CR[0x0] & 0x1000) ^ (offC & 0x1000))
message("DMA over the DMEM-to-IMEM gap.");
GET_RCP_REG(SP_DMA_BUSY_REG) = 0x00000000;
GET_RCP_REG(SP_STATUS_REG) &= ~SP_STATUS_DMA_BUSY;
return;
}
void SP_DMA_WRITE(void)
{
unsigned int offC, offD; /* SP cache and dynamic DMA pointers */
register unsigned int length;
register unsigned int count;
register unsigned int skip;
length = (GET_RCP_REG(SP_WR_LEN_REG) & 0x00000FFFul) >> 0;
count = (GET_RCP_REG(SP_WR_LEN_REG) & 0x000FF000ul) >> 12;
skip = (GET_RCP_REG(SP_WR_LEN_REG) & 0xFFF00000ul) >> 20;
#ifdef _DEBUG
length |= 07; /* already corrected by mtc0 */
#endif
++length;
++count;
skip += length;
do {
register unsigned int i;
i = 0;
--count;
do {
offC = (count*length + *CR[0x0] + i) & 0x00001FF8ul;
offD = (count*skip + *CR[0x1] + i) & 0x00FFFFF8ul;
i += 0x000008;
if (offD > su_max_address)
continue;
memcpy(DRAM + offD, DMEM + offC, 8);
} while (i < length);
} while (count);
if ((*CR[0x0] & 0x1000) ^ (offC & 0x1000))
message("DMA over the DMEM-to-IMEM gap.");
GET_RCP_REG(SP_DMA_BUSY_REG) = 0x00000000;
GET_RCP_REG(SP_STATUS_REG) &= ~SP_STATUS_DMA_BUSY;
return;
}
/*** scalar, R4000 control flow manipulation ***/
PROFILE_MODE void J(u32 inst)
{
set_PC(4 * inst);
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void JAL(u32 inst, u32 PC)
{
SR[ra] = FIT_IMEM(PC + LINK_OFF);
set_PC(4 * inst);
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE int BEQ(u32 inst, u32 PC)
{
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
if (!(SR[rs] == SR[rt]))
return 0;
set_PC(PC + 4*inst + SLOT_OFF);
return 1;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE int BNE(u32 inst, u32 PC)
{
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
if (!(SR[rs] != SR[rt]))
return 0;
set_PC(PC + 4*inst + SLOT_OFF);
return 1;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE int BLEZ(u32 inst, u32 PC)
{
const unsigned int rs = (inst >> 21) % (1 << 5);
if (!((s32)SR[rs] <= 0))
return 0;
set_PC(PC + 4*inst + SLOT_OFF);
return 1;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE int BGTZ(u32 inst, u32 PC)
{
const unsigned int rs = (inst >> 21) % (1 << 5);
if (!((s32)SR[rs] > 0))
return 0;
set_PC(PC + 4*inst + SLOT_OFF);
return 1;
cycle += CYCLES_SU_COMMON;
}
/*** scalar, R4000 bit-wise logical operations ***/
PROFILE_MODE void ANDI(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = SR[rs] & immediate;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void ORI(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = SR[rs] | immediate;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void XORI(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = SR[rs] ^ immediate;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void LUI(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = (u32)immediate << 16; /* or: SR[rt] = 0; SR[rt]31..16 = imm; */
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
/*** scalar, R4000 arithmetic operations ***/
PROFILE_MODE void ADDIU(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
printhlelist(rt);
SR[rt] = SR[rs] + (s16)(immediate);
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void SLTI(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = ((s32)(SR[rs]) < (s32)SIGNED_IMM16(immediate)) ? 1 : 0;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void SLTIU(u32 inst)
{
const u16 immediate = (u16)(inst & 0x0000FFFFu);
const unsigned int rs = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
SR[rt] = ((u32)(SR[rs]) < (u32)SIGNED_IMM16(immediate)) ? 1 : 0;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
/*** scalar, R4000 memory loads and stores ***/
PROFILE_MODE void LB(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
SR[rt] = DMEM[BES(addr) & 0x00000FFFul];
SR[rt] = (s8)SR[rt];
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void LH(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
SR[rt] = 0x00000000
| DMEM[BES(addr + 0) & 0x00000FFFul] << 8
| DMEM[BES(addr + 1) & 0x00000FFFul] << 0
;
SR[rt] = (s16)SR[rt];
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void LW(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
printhlelist(rt);
addr = SR[base] + offset;
SR_B(rt, 0) = DMEM[BES(addr + 0) & 0x00000FFFul];
SR_B(rt, 1) = DMEM[BES(addr + 1) & 0x00000FFFul];
SR_B(rt, 2) = DMEM[BES(addr + 2) & 0x00000FFFul];
SR_B(rt, 3) = DMEM[BES(addr + 3) & 0x00000FFFul];
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void LBU(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
SR[rt] = DMEM[BES(addr) & 0x00000FFFul];
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void LHU(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
SR[rt] = 0x00000000
| DMEM[BES(addr + 0) & 0x00000FFFul] << 8
| DMEM[BES(addr + 1) & 0x00000FFFul] << 0
;
SR[zero] = 0x00000000;
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void SB(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
DMEM[BES(addr) & 0x00000FFFul] = (u8)(SR[rt] & 0xFFu);
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void SH(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
DMEM[BES(addr + 0) & 0x00000FFFul] = SR_B(rt, 2);
DMEM[BES(addr + 1) & 0x00000FFFul] = SR_B(rt, 3);
cycle += CYCLES_SU_COMMON;
}
PROFILE_MODE void SW(u32 inst)
{
u32 addr;
const s16 offset = (s16)(inst & 0x0000FFFFul);
const unsigned int base = (inst >> 21) % (1 << 5);
const unsigned int rt = (inst >> 16) % (1 << 5);
addr = SR[base] + offset;
DMEM[BES(addr + 0) & 0x00000FFFul] = SR_B(rt, 0);
DMEM[BES(addr + 1) & 0x00000FFFul] = SR_B(rt, 1);
DMEM[BES(addr + 2) & 0x00000FFFul] = SR_B(rt, 2);
DMEM[BES(addr + 3) & 0x00000FFFul] = SR_B(rt, 3);
cycle += CYCLES_SU_COMMON;
}
/*** scalar, coprocessor operations (vector unit) ***/
u16 rwR_VCE(void)
{ /* never saw a game try to read VCE out to a scalar GPR yet */
register u16 ret_slot;
ret_slot = 0x00 | (u16)get_VCE();
return (ret_slot);
}
void rwW_VCE(u16 vce)
{ /* never saw a game try to write VCE using a scalar GPR yet */
register int i;
vce = 0x00 | (vce & 0xFF);
for (i = 0; i < 8; i++)
cf_vce[i] = (vce >> i) & 1;
return;
}
static u16 (*R_VCF[4])(void) = {
get_VCO,get_VCC,rwR_VCE,rwR_VCE,
};
static void (*W_VCF[4])(u16) = {
set_VCO,set_VCC,rwW_VCE,rwW_VCE,
};
void MFC2(unsigned int rt, unsigned int vs, unsigned int e)
{
SR_B(rt, 2) = VR_B(vs, e);
e = (e + 0x1) & 0xF;
SR_B(rt, 3) = VR_B(vs, e);
SR[rt] = (s16)(SR[rt]);
SR[zero] = 0x00000000;
return;
}
void MTC2(unsigned int rt, unsigned int vd, unsigned int e)
{
VR_B(vd, e+0x0) = SR_B(rt, 2);
VR_B(vd, e+0x1) = SR_B(rt, 3);
return; /* If element == 0xF, it does not matter; loads do not wrap over. */
}
void CFC2(unsigned int rt, unsigned int rd)
{
SR[rt] = (s16)R_VCF[rd & 3]();
SR[zero] = 0x00000000;
return;
}
void CTC2(unsigned int rt, unsigned int rd)
{
W_VCF[rd & 3](SR[rt] & 0x0000FFFF);
return;
}
/*** scalar, coprocessor operations (vector unit, scalar cache transfers) ***/
void LBV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
const unsigned int e = element;
addr = (SR[base] + 1*offset) & 0x00000FFF;
VR_B(vt, e) = DMEM[BES(addr)];
cycle += CYCLES_SU_COMMON;
return;
}
void LSV(unsigned vt, unsigned element, signed offset, unsigned base)
{
signed int correction;
register u32 addr;
const unsigned int e = element;
if (e & 0x1) {
message("LSV\nIllegal element.");
return;
}
addr = (SR[base] + 2*offset) & 0x00000FFF;
correction = (signed)(addr % 0x004);
if (correction == 0x003) {
message("LSV\nWeird addr.");
return;
}
correction = (correction - 1) * HES(0x000);
VR_S(vt, e) = *(pi16)(DMEM + addr - correction);
cycle += CYCLES_SU_COMMON;
return;
}
void LLV(unsigned vt, unsigned element, signed offset, unsigned base)
{
signed int correction;
register u32 addr;
const unsigned int e = element;
if (e & 0x1) {
message("LLV\nOdd element.");
return;
} /* Illegal (but still even) elements are used by Boss Game Studios. */
addr = (SR[base] + 4*offset) & 0x00000FFF;
if (addr & 0x00000001) {
VR_A(vt, e+0x0) = DMEM[BES(addr)];
addr = (addr + 0x00000001) & 0x00000FFF;
VR_U(vt, e+0x1) = DMEM[BES(addr)];
addr = (addr + 0x00000001) & 0x00000FFF;
VR_A(vt, e+0x2) = DMEM[BES(addr)];
addr = (addr + 0x00000001) & 0x00000FFF;
VR_U(vt, e+0x3) = DMEM[BES(addr)];
return;
} /* branch very unlikely: "Star Wars: Battle for Naboo" unaligned addr */
correction = HES(0x000)*(addr%0x004 - 1);
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr - correction);
addr = (addr + 0x00000002) & 0x00000FFF; /* F3DLX 1.23: addr%4 is 0x002. */
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + correction);
cycle += CYCLES_SU_COMMON;
return;
}
void LDV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
const unsigned int e = element;
if (e & 0x1) {
message("LDV\nOdd element.");
return;
} /* Illegal (but still even) elements are used by Boss Game Studios. */
addr = (SR[base] + 8*offset) & 0x00000FFF;
switch (addr & 07) {
case 00:
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr + HES(0x000));
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + HES(0x002));
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + HES(0x004));
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr + HES(0x006));
break;
case 01: /* standard ABI ucodes (unlike e.g. MusyX w/ even addresses) */
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr + 0x000);
VR_A(vt, e+0x2) = DMEM[addr + 0x002 - BES(0x000)];
VR_U(vt, e+0x3) = DMEM[addr + 0x003 + BES(0x000)];
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + 0x004);
VR_A(vt, e+0x6) = DMEM[addr + 0x006 - BES(0x000)];
addr += 0x007 + BES(00);
addr &= 0x00000FFF;
VR_U(vt, e+0x7) = DMEM[addr];
break;
case 02:
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr + 0x000 - HES(0x000));
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + 0x002 + HES(0x000));
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + 0x004 - HES(0x000));
addr += 0x006 + HES(00);
addr &= 0x00000FFF;
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr);
break;
case 03: /* standard ABI ucodes (unlike e.g. MusyX w/ even addresses) */
VR_A(vt, e+0x0) = DMEM[addr + 0x000 - BES(0x000)];
VR_U(vt, e+0x1) = DMEM[addr + 0x001 + BES(0x000)];
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + 0x002);
VR_A(vt, e+0x4) = DMEM[addr + 0x004 - BES(0x000)];
addr += 0x005 + BES(00);
addr &= 0x00000FFF;
VR_U(vt, e+0x5) = DMEM[addr];
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr + 0x001 - BES(0x000));
break;
case 04:
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr + HES(0x000));
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + HES(0x002));
addr += 0x004 + WES(00);
addr &= 0x00000FFF;
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + HES(0x000));
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr + HES(0x002));
break;
case 05: /* standard ABI ucodes (unlike e.g. MusyX w/ even addresses) */
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr + 0x000);
VR_A(vt, e+0x2) = DMEM[addr + 0x002 - BES(0x000)];
addr += 0x003;
addr &= 0x00000FFF;
VR_U(vt, e+0x3) = DMEM[addr + BES(0x000)];
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + 0x001);
VR_A(vt, e+0x6) = DMEM[addr + BES(0x003)];
VR_U(vt, e+0x7) = DMEM[addr + BES(0x004)];
break;
case 06:
VR_S(vt, e+0x0) = *(pi16)(DMEM + addr - HES(0x000));
addr += 0x002;
addr &= 0x00000FFF;
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + HES(0x000));
VR_S(vt, e+0x4) = *(pi16)(DMEM + addr + HES(0x002));
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr + HES(0x004));
break;
case 07: /* standard ABI ucodes (unlike e.g. MusyX w/ even addresses) */
VR_A(vt, e+0x0) = DMEM[addr - BES(0x000)];
addr += 0x001;
addr &= 0x00000FFF;
VR_U(vt, e+0x1) = DMEM[addr + BES(0x000)];
VR_S(vt, e+0x2) = *(pi16)(DMEM + addr + 0x001);
VR_A(vt, e+0x4) = DMEM[addr + BES(0x003)];
VR_U(vt, e+0x5) = DMEM[addr + BES(0x004)];
VR_S(vt, e+0x6) = *(pi16)(DMEM + addr + 0x005);
break;
}
cycle += CYCLES_SU_COMMON;
return;
}
void SBV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
const unsigned int e = element;
addr = (SR[base] + 1*offset) & 0x00000FFF;
DMEM[BES(addr)] = VR_B(vt, e);
cycle += CYCLES_SU_COMMON;
return;
}
void SSV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
const unsigned int e = element;
addr = (SR[base] + 2*offset) & 0x00000FFF;
DMEM[BES(addr)] = VR_B(vt, (e + 0x0));
addr = (addr + 0x00000001) & 0x00000FFF;
DMEM[BES(addr)] = VR_B(vt, (e + 0x1) & 0xF);
cycle += CYCLES_SU_COMMON;
return;
}
void SLV(unsigned vt, unsigned element, signed offset, unsigned base)
{
signed int correction;
register u32 addr;
const unsigned int e = element;
if ((e & 0x1) || e > 0xC) {
message("SLV\nIllegal element.");
return;
} /* must support illegal even elements in F3DEX2 */
addr = (SR[base] + 4*offset) & 0x00000FFF;
if (addr & 0x00000001) {
message("SLV\nOdd addr.");
return;
}
correction = HES(0x000)*(addr%0x004 - 1);
*(pi16)(DMEM + addr - correction) = VR_S(vt, e+0x0);
addr = (addr + 0x00000002) & 0x00000FFF; /* F3DLX 0.95: "Mario Kart 64" */
*(pi16)(DMEM + addr + correction) = VR_S(vt, e+0x2);
cycle += CYCLES_SU_COMMON;
return;
}
void SDV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
const unsigned int e = element;
addr = (SR[base] + 8*offset) & 0x00000FFF;
if (e > 0x8 || (e & 0x1)) {
register unsigned int i;
#if (VR_STATIC_WRAPAROUND == 1)
vector_copy(VR[vt] + N, VR[vt]);
for (i = 0; i < 8; i++)
DMEM[BES(addr++ & 0x00000FFF)] = VR_B(vt, e + i);
#else
for (i = 0; i < 8; i++)
DMEM[BES(addr++ & 0x00000FFF)] = VR_B(vt, (e+i)&0xF);
#endif
cycle += CYCLES_SU_COMMON;
return;
} /* Illegal elements with Boss Game Studios publications. */
switch (addr & 07) {
case 00:
*(pi16)(DMEM + addr + HES(0x000)) = VR_S(vt, e+0x0);
*(pi16)(DMEM + addr + HES(0x002)) = VR_S(vt, e+0x2);
*(pi16)(DMEM + addr + HES(0x004)) = VR_S(vt, e+0x4);
*(pi16)(DMEM + addr + HES(0x006)) = VR_S(vt, e+0x6);
break;
case 01: /* "Tetrisphere" audio ucode */
*(pi16)(DMEM + addr + 0x000) = VR_S(vt, e+0x0);
DMEM[addr + 0x002 - BES(0x000)] = VR_A(vt, e+0x2);
DMEM[addr + 0x003 + BES(0x000)] = VR_U(vt, e+0x3);
*(pi16)(DMEM + addr + 0x004) = VR_S(vt, e+0x4);
DMEM[addr + 0x006 - BES(0x000)] = VR_A(vt, e+0x6);
addr += 0x007 + BES(0x000);
addr &= 0x00000FFF;
DMEM[addr] = VR_U(vt, e+0x7);
break;
case 02:
*(pi16)(DMEM + addr + 0x000 - HES(0x000)) = VR_S(vt, e+0x0);
*(pi16)(DMEM + addr + 0x002 + HES(0x000)) = VR_S(vt, e+0x2);
*(pi16)(DMEM + addr + 0x004 - HES(0x000)) = VR_S(vt, e+0x4);
addr += 0x006 + HES(0x000);
addr &= 0x00000FFF;
*(pi16)(DMEM + addr) = VR_S(vt, e+0x6);
break;
case 03: /* "Tetrisphere" audio ucode */
DMEM[addr + 0x000 - BES(0x000)] = VR_A(vt, e+0x0);
DMEM[addr + 0x001 + BES(0x000)] = VR_U(vt, e+0x1);
*(pi16)(DMEM + addr + 0x002) = VR_S(vt, e+0x2);
DMEM[addr + 0x004 - BES(0x000)] = VR_A(vt, e+0x4);
addr += 0x005 + BES(0x000);
addr &= 0x00000FFF;
DMEM[addr] = VR_U(vt, e+0x5);
*(pi16)(DMEM + addr + 0x001 - BES(0x000)) = VR_S(vt, 0x6);
break;
case 04:
*(pi16)(DMEM + addr + HES(0x000)) = VR_S(vt, e+0x0);
*(pi16)(DMEM + addr + HES(0x002)) = VR_S(vt, e+0x2);
addr = (addr + 0x004) & 0x00000FFF;
*(pi16)(DMEM + addr + HES(0x000)) = VR_S(vt, e+0x4);
*(pi16)(DMEM + addr + HES(0x002)) = VR_S(vt, e+0x6);
break;
case 05: /* "Tetrisphere" audio ucode */
*(pi16)(DMEM + addr + 0x000) = VR_S(vt, e+0x0);
DMEM[addr + 0x002 - BES(0x000)] = VR_A(vt, e+0x2);
addr = (addr + 0x003) & 0x00000FFF;
DMEM[addr + BES(0x000)] = VR_U(vt, e+0x3);
*(pi16)(DMEM + addr + 0x001) = VR_S(vt, e+0x4);
DMEM[addr + BES(0x003)] = VR_A(vt, e+0x6);
DMEM[addr + BES(0x004)] = VR_U(vt, e+0x7);
break;
case 06:
*(pi16)(DMEM + addr - HES(0x000)) = VR_S(vt, e+0x0);
addr = (addr + 0x002) & 0x00000FFF;
*(pi16)(DMEM + addr + HES(0x000)) = VR_S(vt, e+0x2);
*(pi16)(DMEM + addr + HES(0x002)) = VR_S(vt, e+0x4);
*(pi16)(DMEM + addr + HES(0x004)) = VR_S(vt, e+0x6);
break;
case 07: /* "Tetrisphere" audio ucode */
DMEM[addr - BES(0x000)] = VR_A(vt, e+0x0);
addr = (addr + 0x001) & 0x00000FFF;
DMEM[addr + BES(0x000)] = VR_U(vt, e+0x1);
*(pi16)(DMEM + addr + 0x001) = VR_S(vt, e+0x2);
DMEM[addr + BES(0x003)] = VR_A(vt, e+0x4);
DMEM[addr + BES(0x004)] = VR_U(vt, e+0x5);
*(pi16)(DMEM + addr + 0x005) = VR_S(vt, e+0x6);
break;
}
cycle += CYCLES_SU_COMMON;
return;
}
NOINLINE void
res_lsw(unsigned vt, unsigned element, signed offset, unsigned base)
{
message("Reserved vector unit transfer operation.");
if (vt != element + base || offset != 0) /* unused parameters */
return;
return;
}
/*
* Group II vector loads and stores:
* PV and UV (As of RCP implementation, XV and ZV are reserved opcodes.)
*/
void LPV(unsigned vt, unsigned element, signed offset, unsigned base)
{
register u32 addr;
register int b;
const unsigned int e = element;
if (e != 0x0) {
message("LPV\nIllegal element.");
return;
}
addr = (SR[base] + 8*offset) & 0x00000FFF;
b = addr & 07;
addr &= ~07;
switch (b) {
case 00:
VR[vt][07] = DMEM[addr + BES(0x007)] << 8;
VR[vt][06] = DMEM[addr + BES(0x006)] << 8;
VR[vt][05] = DMEM[addr + BES(0x005)] << 8;
VR[vt][04] = DMEM[addr + BES(0x004)] << 8;
VR[vt][03] = DMEM[addr + BES(0x003)] << 8;
VR[vt][02] = DMEM[addr + BES(0x002)] << 8;
VR[vt][01] = DMEM[addr + BES(0x001)] << 8;
VR[vt][00] = DMEM[addr + BES(0x000)] << 8;
break;
case 01: /* F3DZEX 2.08J "Doubutsu no Mori" (Animal Forest) CPU CFB */
VR[vt][00] = DMEM[addr + BES(0x001)] << 8;
VR[vt][01] = DMEM[addr + BES(0x002)] << 8;
VR[vt][02] = DMEM[addr + BES(0x003)] << 8;
VR[vt][03] = DMEM[addr + BES(0x004)] << 8;
VR[vt][04] = DMEM[addr + BES(0x005)] << 8;
VR[vt][05] = DMEM[addr + BES(0x006)] << 8;
VR[vt][06] = DMEM[addr + BES(0x007)] << 8;
addr += BES(0x008);
addr &= 0x00000FFF;
VR[vt][07] = DMEM[addr] << 8;
break;
case 02: /* F3DZEX 2.08J "Doubutsu no Mori" (Animal Forest) CPU CFB */
VR[vt][00] = DMEM[addr + BES(0x002)] << 8;
VR[vt][01] = DMEM[addr + BES(0x003)] << 8;
VR[vt][02] = DMEM[addr + BES(0x004)] << 8;
VR[vt][03] = DMEM[addr + BES(0x005)] << 8;
VR[vt][04] = DMEM[addr + BES(0x006)] << 8;
VR[vt][05] = DMEM[addr + BES(0x007)] << 8;
addr += 0x008;
addr &= 0x00000FFF;
VR[vt][06] = DMEM[addr + BES(0x000)] << 8;
VR[vt][07] = DMEM[addr + BES(0x001)] << 8;
break;
case 03: /* F3DZEX 2.08J "Doubutsu no Mori" (Animal Forest) CPU CFB */
VR[vt][00] = DMEM[addr + BES(0x003)] << 8;
VR[vt][01] = DMEM[addr + BES(0x004)] << 8;
VR[vt][02] = DMEM[addr + BES(0x005)] << 8;
VR[vt][03] = DMEM[addr + BES(0x006)] << 8;
VR[vt][04] = DMEM[addr + BES(0x007)] << 8;
addr += 0x008;
addr &= 0x00000FFF;
VR[vt][05] = DMEM[addr + BES(0x000)] << 8;
VR[vt][06] = DMEM[addr + BES(0x001)] << 8;
VR[vt][07] = DMEM[addr + BES(0x002)] << 8;
break;
case 04: /* "Resident Evil 2" in-game 3-D, F3DLX 2.08--"WWF No Mercy" */
VR[vt][00] = DMEM[addr + BES(0x004)] << 8;
VR[vt][01] = DMEM[addr + BES(0x005)] << 8;
VR[vt][02] = DMEM[addr + BES(0x006)] << 8;
VR[vt][03] = DMEM[addr + BES(0x007)] << 8;
addr += 0x008;
addr &= 0x00000FFF;
VR[vt][04] = DMEM[addr + BES(0x000)] << 8;
VR[vt][05] = DMEM[addr + BES(0x001)] << 8;
VR[vt][06] = DMEM[addr + BES(0x002)] << 8;
VR[vt][07] = DMEM[addr + BES(0x003)] << 8;
break;
case 05: /* F3DZEX 2.08J "Doubutsu no Mori" (Animal Forest) CPU CFB */
VR[vt][00] = DMEM[addr + BES(0x005)] << 8;
VR[vt][01] = DMEM[addr + BES(0x006)] << 8;
VR[vt][02] = DMEM[addr + BES(0x007)] << 8;
addr += 0x008;
addr &= 0x00000FFF;
VR[vt][03] = DMEM[addr + BES(0x000)] << 8;
VR[vt][04] = DMEM[addr + BES(0x001)] << 8;
VR[vt][05] = DMEM[addr + BES(0x002)] << 8;
VR[vt][06] = DMEM[addr + BES(0x003)] << 8;
VR[vt][07] = DMEM[addr + BES(0x004)] << 8;
break;
case 06: /* F3DZEX 2.08J "Doubutsu no Mori" (Animal Forest) CPU CFB */
VR[vt][00] = DMEM[addr + BES(0x006)] << 8;
VR[vt][01] = DMEM[addr + BES(0x007)] << 8;
addr += 0x008;
addr &= 0x00000FFF;
VR[vt][02] = DMEM[addr + BES(0x000)] << 8;
VR[vt][03] = DMEM[addr + BES(0x001)] << 8;
VR[vt][04] = DMEM[addr + BES(0x002)] << 8;