VSDSquadron-Research-Internship-Program

Explore VSDSquadron's internship repository for VLSI embedded systems using VSDSquadron Mini. Access tutorials, templates, tools, and projects for a comprehensive understanding.

TASK 1: RISC-V TOOL CHAIN

Install RISC-V GNU ToolChain

Compiling the C Program:

The sum of Numbers from 1 to n

Step 1: cd

step 2: gedit sum_1ton.c (save file name as .c)

step 3: Compilling -> gcc sum_1ton.c

step 4: Running -> ./a.out sum_1ton.c

At final Output is printed.

#include <stdio.h>
int main() 
{
    int i, n = 5, sum = 0;

    for (i = 0; i <= n; ++i)
    {
        sum += i;
    }

    printf("Sum of %d numbers is %d\n", n, sum);

    return 0;
}

Use the following commands for compiling in the RISC V Compiler:

Step 1:

riscv64-unknown-elf-gcc -O1 -mabi=lp64 march=rv64i -o sum_1ton.o sum_1ton.c

Use the following commands to open the assembly-level instruction:

step 2: Go to a new tab

riscv64-unknown-elf-objdump -d sum_1ton.c

Step 3: To make it less

riscv64-unknown-elf-objdump -d sum_1ton.c | less

Search for the main use--> /main and press n

now replace O1 to Ofast

To find the number of instruction

start address of present sequence - start address of next sequence

TASK 2: RISC-V INSTRUCTION SET

RISC-V

RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. It is designed to be royalty-free and open-source, allowing anyone to use and contribute to the architecture without any licensing fees or restrictions.

INSTRUCTIONS FORMAT IN RISC-V

Sure, I'd be happy to provide an overview of the topics you've listed related to RISC-V instruction formats and architecture.

General-Purpose Register and PC:
- RISC-V has 32 general-purpose 64-bit registers, named x0 to x31.
- x0 is a hardwired zero register, which cannot be written to.
- x1 is the return address register (also known as the link register).
- x2 is the stack pointer register.
- The program counter (PC) register holds the address of the currently executing instruction.
RISC-V Base Instruction Formats: RISC-V defines six base instruction formats:
- I-type
- U-type
- R-type
- J-type
- B-type
- S-type (a subclass of I-type)
I-type Instruction Format:
- I-type instructions include load, immediate, and shift instructions.
- The format is opcode rd, rs1, immediate.
- The immediate value is a 12-bit signed integer.
U-type Instruction Format:
- U-type instructions include upper-immediate instructions.
- The format is opcode rd, immediate.
- The immediate value is a 20-bit unsigned integer.
R-type Instruction Format:
- R-type instructions include arithmetic, logical, and control-transfer instructions.
- The format is opcode rd, rs1, rs2.
J-type Instruction Format:
- J-type instructions include jump instructions.
- The format is opcode rd, immediate.
- The immediate value is a 20-bit signed integer.
B-type Instruction Format:
- B-type instructions include conditional branch instructions.
- The format is opcode rs1, rs2, immediate.
- The immediate value is a 12-bit signed integer.
Load and Store Instructions:
- Load instructions (load, lw, ld) transfer data from memory to registers.
- Store instructions (store, sw, sd) transfer data from registers to memory.
- These instructions use the I-type format.
Address Alignment:
- RISC-V requires aligned memory accesses for load and store instructions.
- For 32-bit and 64-bit loads and stores, the address must be aligned to a 4-byte and 8-byte boundary, respectively.
- Unaligned memory accesses can be emulated in software if necessary.
Handle Overflow Situations:
- RISC-V does not have dedicated overflow detection instructions.
- Overflow can be detected by checking the carry or sign bits of the result.
- Specific instructions like addiw and subw can be used to perform 32-bit signed integer arithmetic with overflow detection.
- Software can also implement overflow checking through conditional branches.
Command: ADD r6, r2, r1
- Instruction Type: R-type
- Instruction Format: 0000000 00001 00010 000 00110 0110011
Command: SUB r7, r1, r2
- Instruction Type: R-type
- Instruction Format: 0100000 00010 00001 000 00111 0110011
Command: AND r8, r1, r3
- Instruction Type: R-type
- Instruction Format: 0000000 00011 00001 111 01000 0110011
Command: OR r9, r2, r5
- Instruction Type: R-type
- Instruction Format: 0000000 00101 00010 110 01001 0110011
Command: XOR r10, r1, r4
- Instruction Type: R-type
- Instruction Format: 0000000 00100 00001 100 01010 0110011
Command: SLT r11, r2, r4
- Instruction Type: R-type
- Instruction Format: 0000000 00100 00010 010 01011 0110011
Command: ADDI r12, r4, 5
- Instruction Type: I-type
- Instruction Format: 000000000101 00100 000 01100 0010011
Command: SW r3, r1, 2
- Instruction Type: S-type
- Instruction Format: 0000000 00001 00011 010 00010 0100011
Command: SRL r16, r14, r2
- Instruction Type: R-type
- Instruction Format: 0000000 00010 01110 101 10000 0110011
Command: BNE r0, r1, 20
- Instruction Type: B-type
- Instruction Format: 0000000 00001 00000 001 10100 1100011
Command: BEQ r0, r0, 15
- Instruction Type: B-type
- Instruction Format: 0000000 00000 00000 000 01111 1100011
Command: LW r13, r1, 2
- Instruction Type: I-type
- Instruction Format: 000000000010 00001 010 01101 0000011
Command: SLL r15, r1, r2
- Instruction Type: R-type
- Instruction Format: 0000000 00010 00001 001 01111 0110011

TASK 3: RISC-V Verilog Functional Simulation

Steps for RISCV Functional Simulations:

Install iverilog and GTKWave:

sudo apt install iverilog

sudo apt install gtkwave

step 1: create a new dir in a folder as

mkdir mrb

step 2: create files the Verilog files code and testbench using touch

file named as rv32i.v and rv32i_tb.v

Step 3: To run and simulate the Verilog code

iverilog -o rv32i rv32i.v rv32i_tb.v

./rv32i

Step 4:To simulate in GTKWave

gtkwave rv32i.vcd

OUTPUT:

Here's the given information in a table format:

Operation	Standard RISCV ISA	Hardcoded ISA
ADD	R6, R2, R1	32'h00110333
		32'h02208300
SUB	R7, R1, R2	32'h402083b3
		32'h02209380
AND	R8, R1, R3	32'h0030f433
		32'h0230a400
OR	R9, R2, R5	32'h005164b3
		32'h02513480
XOR	R10, R1, R4	32'h0040c533
		32'h0240c500
SLT	R1, R2, R4	32'h0045a0b3
		32'h02415580
ADDI	R12, R4, 5	32'h004120b3
		32'h00520600
BEQ	R0, R0, 15	32'h00000f63
		32'h00f00002
SW	R3, R1, 2	32'h0030a123
		32'h00209181
LW	R13, R1, 2	32'h0020a683
		32'h00208681
SRL	R16, R14, R2	32'h0030a123
		32'h00271803
SLL	R15, R1, R2	32'h002097b3
		32'h00208783

Each operation with its corresponding standard RISCV ISA format and hardcoded ISA format.

1. ADD: `ADD R6, R2 ,R1`

Output is 1+2 = 3

32- bit instruction for ADD R6, R2 ,R1 is 0220833

For Example:

Breakdown and how it maps to the 32-bit instruction format in RISCV:

The instruction ADD R6, R2, R1 is encoded in the RISCV ISA as 0x0220833.

In the RISCV ISA, the ADD instruction format is as follows:

funct7 | rs2 | rs1 | funct3 | rd | opcode

Each field is described as:

funct7: 7 bits
rs2: 5 bits
rs1: 5 bits
funct3: 3 bits
rd: 5 bits
opcode: 7 bits

For ADD R6, R2, R1, we need to fill in these fields:

funct7 = 0000000 (for ADD)
rs2 = R1 (register 1 in binary: 00001)
rs1 = R2 (register 2 in binary: 00010)
funct3 = 000 (for ADD)
rd = R6 (register 6 in binary: 00110)
opcode = 0110011 (for R-type instructions)

Putting these together:

funct7 | rs2  | rs1  | funct3 | rd   | opcode
0000000 | 00001 | 00010 | 000   | 00110 | 0110011

In binary: 0000000 00001 00010 000 00110 0110011

Converting each field to hexadecimal:

funct7 = 0000000 = 0x00
rs2 = 00001 = 0x01
rs1 = 00010 = 0x02
funct3 = 000 = 0x0
rd = 00110 = 0x06
opcode = 0110011 = 0x33

Combining these into a single 32-bit instruction:

0000000 00001 00010 000 00110 0110011

In hexadecimal, this is: 0x00208333

Given in the hardcoded format:

Opcode: 0x33
funct3: 0x0
funct7: 0x0
rd: 0x6
rs1: 0x2
rs2: 0x1

So, the 32-bit instruction for ADD R6, R2, R1 in RISCV ISA is 0x00208333.

2. SUB: SUB R7, R1 ,R2

Output is 1-2 = -1 or 0XFFFFFFFF

32- bit instruction for SUB R7, R1 ,R2 is 0220833

3. AND: AND R8, R1, R3

Output is 3 & 1 = 1 or 0X00000001

32 - bit instruction for AND R8, R1, R3 is 0230A400.

4.OR: OR R9, R2, R5

Output is 2|5 = 7

32- bit instruction for OR R9, R2, R5 is 02513480

5. XOR: XOR R10, R1, R4

Output is 1 (0001) ^ 4 (0100) = 5 (0101)

32 - bit instruction for XOR R10, R1, R4 is 0240C500.

6. SLT: SLT R1, R2, R4

Output is = comparing the value 2 with 4 , so 2 < 4 = 1

32- bit instruction for SLT R1, R2, R4 is 02415580.

7. ADDI: ADDI R12, R4, 5

Output is value 4 is stored in register with an value, 4+5=9

32- bit instruction for ADDI R12, R4, 5 is 00520600.

8. BEQ: BEQ R0, R0, 15

Output is BEQ checks the values stored in both registers, both the reg. are equal, and it increments the PC by 15. So, 10 + 15= 25 or 0x00000019.

32- bit instruction for BEQ R0, R0, 15 is 00F0002.

9. BNE: BNE R0, R1, 20

Output BNE checks the values stored in both registers, both the reg. not equal, and it increments the PC by 20. So, 26 + 20 =46 or 0X0000001A.

32 - bit instruction for BNE R0, R1, 20 is 00210700.

10. SLL: SLL R15, R1, R2

Output (0001) << 2 = 0100 or 4.

32 - bit instruction for SLL R15, R1, R2 is 00210700

TASK 4: PROJECT

AUTOMATED SMS CALLS USING VSDSQUADRON MINI and SIM800L MODULE

VSDSQUADRON MINI and SIM800L Pin Connections

VSDSQUADRON MINI Pin Description:

5V: Power supply pin that provides 5V to the connected module.
GND: Ground pin for common ground reference.
PA10: General-purpose I/O pin, used as the TX (Transmit) pin for UART communication.
PA9: General-purpose I/O pin, used as the RX (Receive) pin for UART communication.

SIM800L Pin Description:

VCC: Power input pin for the SIM800L module, typically requires 3.7-4.2V but is connected to the 5V pin of VSDSQUADRON MINI in this case.
GND: Ground pin, connected to the common ground.
TXD: Transmit pin for UART communication, connected to PA10 of the VSDSQUADRON MINI.
RXD: Receive pin for UART communication, connected to PA9 of the VSDSQUADRON MINI.

Code Implementation:

The provided code initializes the VSDSQUADRON MINI microcontroller and communicates with the SIM800L GSM module to send an SMS.

Includes and Defines:
- #include <ch32v00x.h>: Includes the header file for the VSDSQUADRON MINI microcontroller.
- #include <debug.h>: Includes the debug header for debugging purposes.
- #define SIM800L_UART USART1: Defines the UART port used for communication with the SIM800L.
- #define SIM800L_BAUDRATE 9600: Defines the baud rate for UART communication.
Delay Functions:
- void Delay_Init(void): Initializes delay functions (implementation needed if required).
- void Delay_Ms(uint32_t n): Delays for n milliseconds by executing a loop.
USART Initialization and Communication Functions:
- void USART_Printf_Init(uint32_t baudrate): Initializes the USART peripheral with the specified baud rate.
- void USART_SendString(USART_TypeDef* USARTx, char* str): Sends a string over the specified USART.
Setup Function:
- Initializes the system clock and delay functions.
- Configures the USART for communication with the SIM800L.
- Sends AT commands to the SIM800L to send an SMS to the specified phone number.
Main Function:
- Calls the setup() function and enters an infinite loop.

Connections Summary:

+-----------------+      +----------+
| VSDSQUADRON MINI|      | SIM800L  |
|                 |      |          |
|              5V |------| VCC      |
|             GND |------| GND      |
|             PA10|------| TXD      |
|             PA9 |------| RXD      |
+-----------------+      +----------+

Usage:

Connect the pins of the VSDSQUADRON MINI to the SIM800L as described.
Enter the phone number to which the SMS or call.
Compile and upload the code to the VSDSQUADRON MINI microcontroller.

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README.md

README.md

VSDSquadron-Research-Internship-Program

RISC-V

INSTRUCTIONS FORMAT IN RISC-V

Steps for RISCV Functional Simulations:

OUTPUT:

1. ADD: `ADD R6, R2 ,R1`

Breakdown and how it maps to the 32-bit instruction format in RISCV:

2. SUB: SUB R7, R1 ,R2

3. AND: AND R8, R1, R3

4.OR: OR R9, R2, R5

5. XOR: XOR R10, R1, R4

6. SLT: SLT R1, R2, R4

7. ADDI: ADDI R12, R4, 5

8. BEQ: BEQ R0, R0, 15

9. BNE: BNE R0, R1, 20

10. SLL: SLL R15, R1, R2

AUTOMATED SMS CALLS USING VSDSQUADRON MINI and SIM800L MODULE

VSDSQUADRON MINI and SIM800L Pin Connections

VSDSQUADRON MINI Pin Description:

SIM800L Pin Description:

Code Implementation:

Connections Summary:

Usage:

Files

README.md

Latest commit

History

README.md

File metadata and controls

VSDSquadron-Research-Internship-Program

RISC-V

INSTRUCTIONS FORMAT IN RISC-V

Steps for RISCV Functional Simulations:

OUTPUT:

1. ADD: ADD R6, R2 ,R1

Breakdown and how it maps to the 32-bit instruction format in RISCV:

2. SUB: SUB R7, R1 ,R2

3. AND: AND R8, R1, R3

4.OR: OR R9, R2, R5

5. XOR: XOR R10, R1, R4

6. SLT: SLT R1, R2, R4

7. ADDI: ADDI R12, R4, 5

8. BEQ: BEQ R0, R0, 15

9. BNE: BNE R0, R1, 20

10. SLL: SLL R15, R1, R2

AUTOMATED SMS CALLS USING VSDSQUADRON MINI and SIM800L MODULE

VSDSQUADRON MINI and SIM800L Pin Connections

VSDSQUADRON MINI Pin Description:

SIM800L Pin Description:

Code Implementation:

Connections Summary:

Usage:

1. ADD: `ADD R6, R2 ,R1`