This repository contains the code and documentation for ECE 5745 Tutorial 5 on the Synopsys/Cadence ASIC tools. This tutorial discusses the various views that make-up a standard-cell library and then illustrates how to use the Synopsys/Cadence ASIC tools to map an RTL design down to these standard cells and ultimately silicon. The tutorial discusses the key tools used for synthesis, place-and-route, and power analysis. This tutorial requires entering commands manually for each of the tools to enable students to gain a better understanding of the detailed steps involved in this process. The next tutorial will illustrate how this process can be automated to facilitate rapid design-space exploration. This tutorial assumes you have already completed the tutorials on Linux, Git, PyMTL, and Verilog.
You can find the actual tutorial document in the repo here:
Or online here: