From 7f31c3480aca45055b7e7ec411b488ea3919d8a1 Mon Sep 17 00:00:00 2001 From: Nascs Fang Date: Wed, 24 Apr 2024 15:22:59 +0800 Subject: [PATCH] rockchip: extracted from waveshare35 public section Signed-off-by: Nascs Fang Co-authored-by: ZHANG Yuntian --- .../arm64/boot/dts/rockchip/overlays/Makefile | 5 +- .../overlays/rk3399-spi1-waveshare35.dts | 66 ++++--------------- .../overlays/rk3399-spi1-waveshare35b.dts | 36 ++++++++++ .../rk3568-spi3-m0-cs0-waveshare35.dts | 55 ++++------------ .../rk3568-spi3-m1-cs0-waveshare35.dts | 52 ++++----------- .../rk3568-spi3-m1-cs0-waveshare35b.dts | 25 +++++++ .../rk3588-spi0-m1-cs0-waveshare35.dts | 56 +++++----------- .../rk3588-spi0-m1-cs0-waveshare35b.dts | 25 +++++++ .../rockchip/overlays/waveshare35-lcd.dtsi | 47 +++++++++++++ 9 files changed, 192 insertions(+), 175 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35b.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35b.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35b.dts create mode 100644 arch/arm64/boot/dts/rockchip/overlays/waveshare35-lcd.dtsi diff --git a/arch/arm64/boot/dts/rockchip/overlays/Makefile b/arch/arm64/boot/dts/rockchip/overlays/Makefile index f98724d9..eb26e65d 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_CLK_RK3399) += \ rk3399-spi1-mcp2515-8mhz.dtbo \ rk3399-spi1-spidev.dtbo \ rk3399-spi1-waveshare35.dtbo \ + rk3399-spi1-waveshare35b.dtbo \ rk3399-spi2-enc28j60.dtbo \ rk3399-spi2-jedec-nor.dtbo \ rk3399-spi2-sc16is752.dtbo \ @@ -220,12 +221,13 @@ dtb-$(CONFIG_CLK_RK3568) += \ rk3568-spi3-m0-cs0-mcp2515.dtbo \ rk3568-spi3-m0-cs0-spidev.dtbo \ rk3568-spi3-m0-cs0-waveshare35.dtbo \ - rk3568-spi3-m1-cs0-waveshare35.dtbo \ rk3568-spi3-m0-cs1-spidev.dtbo \ rk3568-spi3-m1-cs0-enc28j60.dtbo \ rk3568-spi3-m1-cs0-mcp2515-gpio4_d1.dtbo \ rk3568-spi3-m1-cs0-mcp2515.dtbo \ rk3568-spi3-m1-cs0-spidev.dtbo \ + rk3568-spi3-m1-cs0-waveshare35.dtbo \ + rk3568-spi3-m1-cs0-waveshare35b.dtbo \ rk3568-spi3-m1-cs1-spidev.dtbo \ rk3568-uart0.dtbo \ rk3568-uart1-m1-full.dtbo \ @@ -379,6 +381,7 @@ dtb-$(CONFIG_CLK_RK3588) += \ rk3588-spi0-m1-cs0-mcp2515-8mhz.dtbo \ rk3588-spi0-m1-cs0-spidev.dtbo \ rk3588-spi0-m1-cs0-waveshare35.dtbo \ + rk3588-spi0-m1-cs0-waveshare35b.dtbo \ rk3588-spi0-m1-cs1-spidev.dtbo \ rk3588-spi0-m2-cs0-mcp2515-8mhz.dtbo \ rk3588-spi0-m2-cs0-spidev.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35.dts index 281d10cb..baaad63c 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35.dts @@ -1,69 +1,31 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include +#define DISPLAY_SPI spi1 +#include "waveshare35-lcd.dtsi" / { metadata { - title = "Enable Waveshare 3.5 inch Display on SPI1"; + title = "Enable Waveshare 3.5inch RPi LCD (C) on SPI1"; compatible = "rockchip,rk3399"; category = "misc"; exclusive = "GPIO1_B0", "GPIO1_A7", "GPIO1_B1", "GPIO1_B2", "GPIO4_D2", "GPIO4_D4", "GPIO4_D5" ; - description = "Enable Waveshare 3.5 inch Display on SPI1."; - }; -}; - -&pinctrl { - ili9486_pins { - ili9486_pins: ili9486-pins { - rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; + description = "Enable Waveshare 3.5inch RPi LCD (C) on SPI1."; }; }; -&spi1 { - status = "okay"; - max-freq = <48000000>; - #address-cells = <1>; - #size-cells = <0>; +&DISPLAY_SPI { num-cs = <2>; cs-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH &gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi1_clk &spi1_rx &spi1_tx>; +}; - ili9486@0 { - compatible = "ilitek,ili9486"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&ili9486_pins>; - spi-max-frequency = <15000000>; - txbuflen = <32768>; - rotate = <90>; - bgr = <0>; - fps = <30>; - buswidth = <8>; - regwidth = <16>; - reset-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; - debug = <0>; - }; +&ili9486 { + reset-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +}; - ads7846@1 { - compatible = "ti,ads7846"; - status = "okay"; - reg = <1>; - id = <1>; - spi-max-frequency = <2000000>; - interrupts = ; - interrupt-parent = <&gpio4>; - pendown-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - ti,x-plate-ohms = /bits/ 16 <60>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy = <0>; - vcc-supply = <&vcc5v0_sys>; - }; +&ads7846 { + interrupts = ; + interrupt-parent = <&gpio4>; + pendown-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35b.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35b.dts new file mode 100644 index 00000000..2d2b13c9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3399-spi1-waveshare35b.dts @@ -0,0 +1,36 @@ +#include "rk3399-spi1-waveshare35.dts" + +/ { + metadata { + title = "Enable Waveshare 3.5inch RPi LCD (B) on SPI1 (No Touch Support)"; + exclusive = "GPIO1_B0", "GPIO1_A7", "GPIO1_B1", "GPIO1_B2", "GPIO4_D4", "GPIO4_D5" ; + description = "Enable Waveshare 3.5inch RPi LCD (B) on SPI1 (No Touch Support).\nDue to hardware conflict, touch is not available when using with ROCK 4."; + }; +}; + +&DISPLAY_SPI { + /delete-property/ num-cs; + /delete-property/ cs-gpios; + pinctrl-0 = <&spi1_clk &spi1_cs0 &spi1_rx &spi1_tx>; +}; + +&ili9486 { + init = <0x10000b0 0x0 + 0x1000011 + 0x20000ff + 0x1000021 + 0x100003a 0x55 + 0x10000c2 0x33 + 0x10000c5 0x0 0x1e 0x80 + 0x1000036 0x28 + 0x10000b1 0xb0 + 0x10000e0 0x0 0x13 0x18 0x4 0xf 0x6 0x3a 0x56 0x4d 0x3 0xa 0x6 0x30 0x3e 0xf + 0x10000e1 0x0 0x13 0x18 0x1 0x11 0x6 0x38 0x34 0x4d 0x6 0xd 0xb 0x31 0x37 0xf + 0x1000011 + 0x20000ff + 0x1000029>; +}; + +&ads7846 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m0-cs0-waveshare35.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m0-cs0-waveshare35.dts index dc7cb2c7..9a4a60a7 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m0-cs0-waveshare35.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m0-cs0-waveshare35.dts @@ -1,56 +1,29 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include +#define DISPLAY_SPI spi3 +#include "waveshare35-lcd.dtsi" / { metadata { - title = "Enable Waveshare 3.5 inch Display on SPI3"; + title = "Enable Waveshare 3.5inch RPi LCD (C) on SPI3"; compatible = "radxa,cm3-io", "radxa,cm3-rpi-cm4-io"; category = "misc"; exclusive = "GPIO4_A6", "GPIO3_C6", "GPIO3_D3", "GPIO0_C7", "GPIO4_B0", "GPIO4_B2", "GPIO4_B3"; - description = "Enable Waveshare 3.5 inch Display on SPI3."; + description = "Enable Waveshare 3.5inch RPi LCD (C) on SPI3."; }; }; -&spi3 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&DISPLAY_SPI { pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi3m0_cs0 &spi3m0_pins>; pinctrl-1 = <&spi3m0_cs0 &spi3m0_pins_hs>; - max-freq = <16000000>; +}; - ili9486@0 { - compatible = "ilitek,ili9486"; - reg = <0>; - spi-max-frequency = <16000000>; - txbuflen = <32768>; - rotate = <90>; - bgr = <0>; - fps = <30>; - buswidth = <8>; - regwidth = <16>; - reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; - debug = <0>; - }; +&ili9486 { + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; +}; - ads7846@1 { - compatible = "ti,ads7846"; - status = "okay"; - reg = <1>; - id = <1>; - spi-max-frequency = <2000000>; - interrupts = ; - interrupt-parent = <&gpio0>; - pendown-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - ti,x-plate-ohms = /bits/ 16 <60>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy = <0>; - vcc-supply = <&vcc5v0_sys>; - }; +&ads7846 { + interrupts = ; + interrupt-parent = <&gpio0>; + pendown-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35.dts index 25391191..8fe166b7 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35.dts @@ -1,9 +1,5 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include +#define DISPLAY_SPI spi3 +#include "waveshare35-lcd.dtsi" / { metadata { @@ -15,45 +11,21 @@ }; }; -&spi3 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&DISPLAY_SPI { pinctrl-names = "default", "high_speed"; pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; pinctrl-1 = <&spi3m1_cs1 &spi3m1_pins_hs>; - max-freq = <16000000>; +}; - ili9486@0 { - compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486"; - reg = <0>; - spi-max-frequency = <16000000>; - txbuflen = <32768>; - rotate = <90>; - bgr = <0>; - fps = <30>; - buswidth = <8>; - regwidth = <16>; - reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; - debug = <0>; - }; +&ili9486 { + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; +}; - ads7846@1 { - compatible = "ti,ads7846"; - status = "okay"; - reg = <1>; - id = <1>; - spi-max-frequency = <2000000>; - interrupts = ; - interrupt-parent = <&gpio3>; - pendown-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; - ti,x-plate-ohms = /bits/ 16 <60>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy = <0>; - ti,invert-y = <1>; - vcc-supply = <&vcc5v0_sys>; - }; +&ads7846 { + interrupts = ; + interrupt-parent = <&gpio3>; + pendown-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; }; &hdmi { diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35b.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35b.dts new file mode 100644 index 00000000..2baaaaa0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-waveshare35b.dts @@ -0,0 +1,25 @@ +#include "rk3568-spi3-m1-cs0-waveshare35.dts" + +/ { + metadata { + title = "Enable Waveshare 3.5inch RPi LCD (B) on SPI3-M1"; + description = "Enable Waveshare 3.5inch RPi LCD (B) on SPI3-M1.\nHDMI CEC function will be turned off when this overlay is enabled."; + }; +}; + +&ili9486 { + init = <0x10000b0 0x0 + 0x1000011 + 0x20000ff + 0x1000021 + 0x100003a 0x55 + 0x10000c2 0x33 + 0x10000c5 0x0 0x1e 0x80 + 0x1000036 0x28 + 0x10000b1 0xb0 + 0x10000e0 0x0 0x13 0x18 0x4 0xf 0x6 0x3a 0x56 0x4d 0x3 0xa 0x6 0x30 0x3e 0xf + 0x10000e1 0x0 0x13 0x18 0x1 0x11 0x6 0x38 0x34 0x4d 0x6 0xd 0xb 0x31 0x37 0xf + 0x1000011 + 0x20000ff + 0x1000029>; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35.dts index 49a3cd7a..f7e98a80 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35.dts +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35.dts @@ -1,55 +1,29 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include +#define DISPLAY_SPI spi0 +#include "waveshare35-lcd.dtsi" / { metadata { - title = "Enable Waveshare 3.5 inch Display on SPI0"; + title = "Enable Waveshare 3.5inch RPi LCD (C) on SPI0-M0"; compatible = "radxa,cm5-io"; category = "misc"; exclusive = "GPIO1_B1", "GPIO1_D5", "GPIO4_A0", "GPIO4_A1", "GPIO4_A2", "GPIO4_A6", "GPIO4_B2" ; - description = "Enable Waveshare 3.5 inch Display on SPI0."; + description = "Enable Waveshare 3.5inch RPi LCD (C) on SPI0-M0.\nTouch is temporarily unavailable."; }; }; -&spi0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; +&DISPLAY_SPI { pinctrl-names = "default"; pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>; - max-freq = <16000000>; +}; - ili9486@0 { - compatible = "ilitek,ili9486"; - reg = <0>; - spi-max-frequency = <16000000>; - txbuflen = <32768>; - rotate = <90>; - bgr = <0>; - fps = <30>; - buswidth = <8>; - regwidth = <16>; - reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; // GPIO1_B1 - dc-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; // GPIO1_D5 - debug = <0>; - }; +&ili9486 { + reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; // GPIO1_B1 + dc-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; // GPIO1_D5 +}; - ads7846@1 { - compatible = "ti,ads7846"; - status = "okay"; - reg = <1>; - id = <1>; - spi-max-frequency = <2000000>; - interrupt-parent = <&gpio4>; - interrupts = ; - pendown-gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; - ti,x-plate-ohms = /bits/ 16 <60>; - ti,pressure-max = /bits/ 16 <255>; - ti,swap-xy = <0>; - vcc-supply = <&vcc5v0_sys>; - }; +&ads7846 { + status = "disabled"; + interrupt-parent = <&gpio4>; + interrupts = ; + pendown-gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35b.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35b.dts new file mode 100644 index 00000000..20cab1e7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3588-spi0-m1-cs0-waveshare35b.dts @@ -0,0 +1,25 @@ +#include "rk3588-spi0-m1-cs0-waveshare35.dts" + +/ { + metadata { + title = "Enable Waveshare 3.5 inch Display (B) on SPI0-M0"; + description = "Enable Waveshare 3.5 inch Display (B) on SPI0-M0.\nTouch is temporarily unavailable."; + }; +}; + +&ili9486 { + init = <0x10000b0 0x0 + 0x1000011 + 0x20000ff + 0x1000021 + 0x100003a 0x55 + 0x10000c2 0x33 + 0x10000c5 0x0 0x1e 0x80 + 0x1000036 0x28 + 0x10000b1 0xb0 + 0x10000e0 0x0 0x13 0x18 0x4 0xf 0x6 0x3a 0x56 0x4d 0x3 0xa 0x6 0x30 0x3e 0xf + 0x10000e1 0x0 0x13 0x18 0x1 0x11 0x6 0x38 0x34 0x4d 0x6 0xd 0xb 0x31 0x37 0xf + 0x1000011 + 0x20000ff + 0x1000029>; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/waveshare35-lcd.dtsi b/arch/arm64/boot/dts/rockchip/overlays/waveshare35-lcd.dtsi new file mode 100644 index 00000000..fff26b99 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/waveshare35-lcd.dtsi @@ -0,0 +1,47 @@ +#ifndef __WAVESHARE35_LCD_DTSI__ +#define __WAVESHARE35_LCD_DTSI__ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +#ifndef DISPLAY_SPI +#error "DISPLAY_SPI is undefined." +#endif + +&DISPLAY_SPI { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ili9486: ili9486@0 { + compatible = "ilitek,ili9486"; + reg = <0>; + spi-max-frequency = <16000000>; + txbuflen = <32768>; + rotate = <90>; + bgr = <0>; + fps = <30>; + buswidth = <8>; + regwidth = <16>; + debug = <0>; + }; + + ads7846: ads7846@1 { + compatible = "ti,ads7846"; + status = "okay"; + reg = <1>; + id = <1>; + spi-max-frequency = <2000000>; + ti,x-plate-ohms = /bits/ 16 <60>; + ti,pressure-max = /bits/ 16 <255>; + ti,swap-xy = <0>; + ti,invert-y = <1>; + vcc-supply = <&vcc5v0_sys>; + }; +}; + +#endif // __WAVESHARE35_LCD_DTSI__