diff --git a/arch/arm64/boot/dts/rockchip/overlays/Makefile b/arch/arm64/boot/dts/rockchip/overlays/Makefile index 86ca72e6..b3b5b96a 100644 --- a/arch/arm64/boot/dts/rockchip/overlays/Makefile +++ b/arch/arm64/boot/dts/rockchip/overlays/Makefile @@ -178,6 +178,7 @@ dtb-$(CONFIG_CLK_RK3568) += \ rk3568-can0-m0.dtbo \ rk3568-can1-m0.dtbo \ rk3568-can1-m1.dtbo \ + rk3568-dht11-gpio3-a5.dtbo \ rk3568-disable-fiq-debugger.dtbo \ rk3568-dwc3-host.dtbo \ rk3568-dwc3-otg.dtbo \ @@ -198,8 +199,22 @@ dtb-$(CONFIG_CLK_RK3568) += \ rk3568-i2c2-m0-pca9555.dtbo \ rk3568-i2c2-m0.dtbo \ rk3568-i2c2-m1.dtbo \ + rk3568-i2c3-m0-jc42.dtbo \ + rk3568-i2c3-m0-mcp980x.dtbo \ + rk3568-i2c3-m0-sc16is750.dtbo \ rk3568-i2c3-m0.dtbo \ rk3568-i2c3-m1.dtbo \ + rk3568-i2c4-m0-bme280.dtbo \ + rk3568-i2c4-m0-bme680.dtbo \ + rk3568-i2c4-m0-bmp280.dtbo \ + rk3568-i2c4-m0-bmp380.dtbo \ + rk3568-i2c4-m0-htu21.dtbo \ + rk3568-i2c4-m0-lm75.dtbo \ + rk3568-i2c4-m0-pcf8574.dtbo \ + rk3568-i2c4-m0-pcf8575.dtbo \ + rk3568-i2c4-m0-sht41.dtbo \ + rk3568-i2c4-m0-si7020.dtbo \ + rk3568-i2c4-m0-tmp102.dtbo \ rk3568-i2c4-m0.dtbo \ rk3568-i2c5-m0.dtbo \ rk3568-npu-disable.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-dht11-gpio3-a5.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-dht11-gpio3-a5.dts new file mode 100644 index 00000000..f16729be --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-dht11-gpio3-a5.dts @@ -0,0 +1,34 @@ +/dts-v1/; +/plugin/; + +#include +#include + +/ { + metadata { + title = "Enable DHT11 on GPIO3_A5"; + compatible = "radxa,rock-3c", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO3_A5"; + description = "Enable DHT11 on GPIO3_A5. +On Radxa NX5 IO this is pin 40."; + }; +}; + +&{/} { + dht11: dht11@0 { + compatible = "dht11"; + pinctrl-names = "default"; + pinctrl-0 = <&dht11_pin>; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&pinctrl { + dht11 { + dht11_pin: dht11-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-jc42.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-jc42.dts new file mode 100644 index 00000000..90c186bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-jc42.dts @@ -0,0 +1,11 @@ +#include "rk3568-i2c3-m0.dts" + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + mcp980x: mcp980x@18 { + compatible = "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-mcp980x.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-mcp980x.dts new file mode 100644 index 00000000..d2b13a78 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-mcp980x.dts @@ -0,0 +1,11 @@ +#include "rk3568-i2c3-m0.dts" + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + mcp980x: mcp980x@18 { + compatible = "maxim,mcp980x"; + reg = <0x18>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-sc16is750.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-sc16is750.dts new file mode 100644 index 00000000..67191574 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c3-m0-sc16is750.dts @@ -0,0 +1,24 @@ +#include "rk3568-i2c3-m0.dts" + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + sc16is750: sc16is750@48 { + compatible = "nxp,sc16is750"; + reg = <0x48>; + clocks = <&sc16is750_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; + pinctrl-0 = <&int_pins>; + pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + i2c-max-frequency = <400000>; + }; +}; + + +&{/} { + +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme280.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme280.dts new file mode 100644 index 00000000..26a156dc --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme280.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable BME280 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable BME280 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + bme280: bme280@76 { + compatible = "bme280"; + reg = <0x76>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme680.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme680.dts new file mode 100644 index 00000000..862cdc00 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bme680.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable BME680 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable BME680 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + bme680: bme680@76 { + compatible = "bme680"; + reg = <0x76>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp280.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp280.dts new file mode 100644 index 00000000..281c63da --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp280.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable BMP280 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable BMP280 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + bmp280: bmp280@76 { + compatible = "bosch,bmp280"; + reg = <0x76>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp380.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp380.dts new file mode 100644 index 00000000..363bc497 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-bmp380.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable BMP380 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable BMP380 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + bmp380: bmp380@76 { + compatible = "bosch,bmp380"; + reg = <0x76>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-htu21.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-htu21.dts new file mode 100644 index 00000000..131848d7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-htu21.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable HTU21 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable HTU21 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + htu21: htu21@76 { + compatible = "meas,htu21"; + reg = <0x40>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-lm75.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-lm75.dts new file mode 100644 index 00000000..07f1d11b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-lm75.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable LM75 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable LM75 on I2C4-M0 . +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + lm75: lm75@48 { + compatible = "st,stlm75"; + reg = <0x48>; + vs-supply = <&vcc3v3_sys>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8574.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8574.dts new file mode 100644 index 00000000..4eb464b9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8574.dts @@ -0,0 +1,38 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable PCF8574 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable PCF8574 on I2C4-M0 . +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + pcf8574: pcf8574@20 { + compatible = "nxp,pcf8574"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8575.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8575.dts new file mode 100644 index 00000000..7c0352c5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-pcf8575.dts @@ -0,0 +1,38 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include + +/ { + metadata { + title = "Enable PCF8575 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable PCF8575 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28, INT=3. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28, INT=3"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + pcf8575: pcf8575@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + #gpio-controller; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = ; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-sht41.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-sht41.dts new file mode 100644 index 00000000..d83483f4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-sht41.dts @@ -0,0 +1,35 @@ + + +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SHT41 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable SHT41 on I2C4-M0. +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + sht41: sht41@76 { + compatible = "sensirion,sht4x"; + reg = <0x40>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-si7020.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-si7020.dts new file mode 100644 index 00000000..6b21f099 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-si7020.dts @@ -0,0 +1,32 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable SI7020 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable SI7020 on I2C4-M0 . +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + si7020@40 { + compatible = "si7020"; + reg = <0x40>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-tmp102.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-tmp102.dts new file mode 100644 index 00000000..86be69ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-i2c4-m0-tmp102.dts @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + metadata { + title = "Enable TMP102 on I2C4-M0"; + compatible = "radxa,rock-3c", "radxa,cm3-io", "radxa,cm3-rpi-cm4-io", "radxa,cm3s-io", "radxa,radxa-cm3-sodimm-io", "radxa,e23", "radxa,zero3"; + category = "misc"; + exclusive = "GPIO4_B2", "GPIO4_B3"; + description = "Enable TMP102 on I2C4-M0 . +On Radxa ROCK 3C this is SDA pin 27 and SCL pin 28. +On Radxa CM3 IO this is SDA pin 19 and SCL pin 23. +On Radxa CM3 RPI CM4 IO this SDA pin 19 and SCL pin 23. +On Radxa CM3S IO this is SDA pin 19 and SCL pin 23. +On Radxa E23 this is SDA pin 19 and SCL pin 23.. +On Radxa ZERO 3 this is SDA pin 27 and SCL pin 28"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + #thermal-sensor-cells = <0>; + status = "okay"; + }; +};