From d4d8b5a829f21482dca2e1b67526e396e20ccd11 Mon Sep 17 00:00:00 2001
From: Nascs Fang <nascs@radxa.com>
Date: Wed, 18 Sep 2024 17:48:38 +0800
Subject: [PATCH] feat: add st7735 for 3c/zero3

Signed-off-by: Nascs Fang <nascs@radxa.com>
---
 .../arm64/boot/dts/rockchip/overlays/Makefile |  1 +
 .../overlays/rk3568-spi3-m1-cs0-st7735.dts    | 35 ++++++++++++++++++
 .../boot/dts/rockchip/overlays/st7789v.dtsi   | 37 +++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-st7735.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/overlays/st7789v.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/overlays/Makefile b/arch/arm64/boot/dts/rockchip/overlays/Makefile
index 1613d571..d3ef5bbe 100644
--- a/arch/arm64/boot/dts/rockchip/overlays/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlays/Makefile
@@ -241,6 +241,7 @@ dtb-$(CONFIG_CLK_RK3568) += \
 	rk3568-spi3-m1-cs0-mcp2515-gpio4_d1.dtbo \
 	rk3568-spi3-m1-cs0-mcp2515.dtbo \
 	rk3568-spi3-m1-cs0-spidev.dtbo \
+	rk3568-spi3-m1-cs0-st7735.dtbo \
 	rk3568-spi3-m1-cs0-w5500.dtbo \
 	rk3568-spi3-m1-cs0-waveshare35.dtbo \
 	rk3568-spi3-m1-cs0-waveshare35b.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-st7735.dts b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-st7735.dts
new file mode 100644
index 00000000..e00a2047
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/rk3568-spi3-m1-cs0-st7735.dts
@@ -0,0 +1,35 @@
+#define DISPLAY_SPI spi3
+#include "st7789v.dtsi"
+
+/ {
+	metadata {
+		title = "Enable ST7789V LCD on SPI3-M1";
+		compatible = "radxa,rock-3c", "radxa,zero3";
+		category = "display";
+		exclusive = "GPIO4_A6", "GPIO4_C6", "GPIO3_C1", "GPIO3_B2", "GPIO3_A1", "GPIO4_D1", "GPIO4_B2", "GPIO4_B3";
+		description = "Enable ST7789V LCD on SPI3-M1.
+HDMI CEC function will be turned off when this overlay is enabled.";
+	};
+};
+
+&DISPLAY_SPI {
+	pinctrl-names = "default", "high_speed";
+	pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>;
+	pinctrl-1 = <&spi3m1_cs1 &spi3m1_pins_hs>;
+};
+
+&ili9486 {
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+	dc-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+};
+
+&ads7846 {
+	interrupts = <RK_PA1 IRQ_TYPE_EDGE_FALLING>;
+	interrupt-parent = <&gpio3>;
+	pendown-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmitx_scl &hdmitx_sda>; 
+};
diff --git a/arch/arm64/boot/dts/rockchip/overlays/st7789v.dtsi b/arch/arm64/boot/dts/rockchip/overlays/st7789v.dtsi
new file mode 100644
index 00000000..bc654bf7
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlays/st7789v.dtsi
@@ -0,0 +1,37 @@
+#ifndef __WAVESHARE35_LCD_DTSI__
+#define __WAVESHARE35_LCD_DTSI__
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+/plugin/;
+
+#ifndef DISPLAY_SPI
+#error "DISPLAY_SPI is undefined."
+#endif
+
+&DISPLAY_SPI {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	st7789: st7789@0 {
+		 compatible = "sitronix,st7789v";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+		txbuflen = <32768>;
+		rotate = <90>;
+		bgr = <0>;
+		fps = <60>;
+        width = <135>;
+        height = <240>;
+		buswidth = <8>;
+		regwidth = <16>;
+		debug = <0>;
+	};
+
+};
+
+#endif // __WAVESHARE35_LCD_DTSI__