diff --git a/_config.yml b/_config.yml index d69e3a8..4788b16 100644 --- a/_config.yml +++ b/_config.yml @@ -105,18 +105,18 @@ color_scheme: nil callouts_level: quiet # or loud callouts: highlight: - color: calloutsyellow + color: calloutshighlight important: - title: Important + title: ⚠️ Important color: calloutspink new: - title: New + title: 🔎 New color: calloutsgreen note: - title: Note + title: 📝 Note color: calloutsblue warning: - title: Warning + title: ☢️ Warning color: calloutsred plugins: diff --git a/_sass/color_schemes/dark.scss b/_sass/color_schemes/dark.scss index bcce4ae..89c1168 100644 --- a/_sass/color_schemes/dark.scss +++ b/_sass/color_schemes/dark.scss @@ -43,7 +43,7 @@ $calloutsteal-300: #11c5fc; $calloutspink-000: #f9c8da; $calloutspink-100: #f599b9; $calloutspink-200: #f389af; -$calloutspink-300: #ed4b83; +$calloutspink-300: #ec729d; $calloutsgreen-000: #cde9b6; $calloutsgreen-100: #b1dd8c; @@ -53,18 +53,23 @@ $calloutsgreen-300: #8bcd54; $calloutsred-000: #ffbdb6; $calloutsred-100: #ff8f83; $calloutsred-200: #ff6251; -$calloutsred-300: #ff351f; +$calloutsred-300: #ff8c7f; $calloutsyellow-000: #fee49c; $calloutsyellow-100: #fed86d; $calloutsyellow-200: #fecb3e; $calloutsyellow-300: #fbb901; +$calloutshighlight-000: #fee49c; +$calloutshighlight-100: #fed86d; +$calloutshighlight-200: #fecb3e; +$calloutshighlight-300: #fbb901; + $calloutsblue-000: #e3c7f7; $calloutsblue-100: #ca94f0; $calloutsblue-200: #d783ff; -$calloutsblue-300: #c855ff; +$calloutsblue-300: #f1d4ff; figure.highlight::before { diff --git a/_sass/support/_variables.scss b/_sass/support/_variables.scss index fdbd67a..c408901 100644 --- a/_sass/support/_variables.scss +++ b/_sass/support/_variables.scss @@ -101,6 +101,12 @@ $calloutsyellow-100: #fadf50; $calloutsyellow-200: #f7d12e; $calloutsyellow-300: #e7af06; +$calloutshighlight-000: #d7d7d7; +$calloutshighlight-100: #be9cfe9d; +$calloutshighlight-200: #be9cfe61; +$calloutshighlight-300: #803cfd; + + $calloutsblue-000: #7253ed; $calloutsblue-100: #5e41d0; $calloutsblue-200: #4e26af; diff --git a/docs/Hardware/a_basics-of-info.md b/docs/Hardware/a_basics-of-info.md index 5699b3b..ecdbeb3 100644 --- a/docs/Hardware/a_basics-of-info.md +++ b/docs/Hardware/a_basics-of-info.md @@ -20,41 +20,39 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here. ](https://youtu.be/IicB30kA3pY) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -1. **Understand the Foundation of Digital Devices:** - - Learn the basic concept of encoding information using electrical signals. - - Understand how bits represent data in electronic devices and their role in computation. - -2. **Explore Number Systems and Encoding:** - - Gain proficiency in converting between binary, decimal, octal, and hexadecimal number systems. - - Comprehend the use of prefixes and suffixes in different number systems to indicate bases. - -3. **Master 2's Complement for Signed Numbers:** - - Understand how 2's complement is used to represent signed integers in binary form. - - Learn the process of converting positive numbers to their negative counterparts using 2's complement. - -4. **Grasp Various Encoding Techniques:** - - Recognize fixed length length encoding methods. - - Understand character encoding standards like ASCII and Unicode and their significance in data representation. - -5. **Comprehend the Significance of Bytes in Digital Storage:** - - Learn why bytes are used as the standard unit of digital information and storage. - - Understand how data storage capacities are measured and reported in terms of bytes. - -6. **Calculate Information Quantity Based on Probability:** - - Understand the relationship between the probability of an event and the amount of information it provides. - - Learn how to compute the information content of events using logarithmic measures. - -7. **Apply Knowledge to Practical Digital System Design:** - - Explore the historical context and evolution of digital devices from mechanical systems to modern electronic computers. - - Understand the practical constraints in early computing, such as cost and size, and how they influenced design decisions. - -8. **Lay the Groundwork for Building General-Purpose Computers:** - - Begin the process of learning how to design and build a general-purpose programmable machine. - - Understand the transition from specific-purpose devices to general-purpose computing platforms. - -These objectives aim to equip students with a comprehensive understanding of digital systems from the ground up, preparing them to engage in more advanced studies and applications in computer science and engineering. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand the Foundation of Digital Devices:** +> - Learn the basic concept of encoding information using electrical signals. +> - Understand how bits represent data in electronic devices and their role in computation. +> 2. **Explore Number Systems and Encoding:** +> - Gain proficiency in converting between binary, decimal, octal, and hexadecimal number systems. +> - Comprehend the use of prefixes and suffixes in different number systems to indicate bases. +> 3. **Master 2's Complement for Signed Numbers:** +> - Understand how 2's complement is used to represent signed integers in binary form. +> - Learn the process of converting positive numbers to their negative counterparts using 2's complement. +> 4. **Grasp Various Encoding Techniques:** +> - Recognize fixed length length encoding methods. +> - Understand character encoding standards like ASCII and Unicode and their significance in data representation. +> 5. **Comprehend the Significance of Bytes in Digital Storage:** +> - Learn why bytes are used as the standard unit of digital information and storage. +> - Understand how data storage capacities are measured and reported in terms of bytes. +> 6. **Calculate Information Quantity Based on Probability:** +> - Understand the relationship between the probability of an event and the amount of information it provides. +> - Learn how to compute the information content of events using logarithmic measures. +> 7. **Understand Basic Logic Gates and Their Role in Digital Circuits**: +> - Learn the functions and operations of basic logic gates: AND, OR, XOR, BUFFER and NOT. +> - Recognize how these gates can be combined to perform simple digital operations. +> - Appreciate the importance of logic gates in translating theoretical binary operations into practical applications within computing hardware. +> 8. **Apply Knowledge to Practical Digital System Design:** +> - Explore the historical context and evolution of digital devices from mechanical systems to modern electronic computers. +> - Understand the practical constraints in early computing, such as cost and size, and how they influenced design decisions. +> 9. **Lay the Groundwork for Building General-Purpose Computers:** +> - Begin the process of learning how to design and build a general-purpose programmable machine. +> - Understand the transition from specific-purpose devices to general-purpose computing platforms. +> +> These objectives aim to equip students with a comprehensive understanding of digital systems from the ground up, preparing them to engage in more advanced studies and applications in computer science and engineering. ## [Overview](https://www.youtube.com/watch?v=IicB30kA3pY&list=PLklpDKpv-EBj1agIq4vB1iB6ahMT8_2A_&index=1&t=0s) @@ -198,9 +196,221 @@ Our system usually report storage amount (disk space, RAM, etc) in terms of **by The prefix "Giga" means $$10^9$$ in International Unit of Systems (SI), however when you plug in a 1GB RAM, your system might report it as 0.93GB instead. This is because in computing, *Giga* means $$1024^3 = 2^{30}$$ bytes exactly instead of $$10^9$$ bytes because we operate in **base** 2 instead of base 10 in SI. To avoid this confusion, there exist another set of prefixes: Kib, Mib, and Gib to denote $$1024$$ bytes, $$1024^2$$ bytes, and $$1024^3$$ bytes in digital systems. +## Introduction to Logic Gates + +{:.new-title} +> Logic Gates +> +> Logic gates are **basic** electronic devices that perform Boolean logic operations, taking binary inputs (0s and 1s) and producing a single binary output. They form building blocks of digital circuits They are implemented using **physical** components such as **transistors** and **diodes** to process digital information in computing hardware. We'll focus on the theory of logic gates first, while the details of transistors and hardware implementation will be covered later. + + +In the previous section, we learn how information is represented using **binary** form, characterized by sequences of 0s and 1s. These binary digits do more than just represent numerical values; they are fundamental to the operational logic of computers. + +Each binary digit forms the basis for decision-making processes within digital circuits, where these 0s and 1s are interpreted not just as numbers but as discrete states—off or on, `false` or `true`. This binary decision-making is implemented through the use of logic gates, which manipulate these bits to perform all kinds of computational tasks, from basic arithmetic to complex algorithmic executions. + +{:.note} +Understanding binary digits paves the way for understanding how computers **process** information, **make** decisions, and ultimately **execute** tasks. + +### Basic Boolean Logic Operations + +Boolean operations form the core of digital logic, using simple rules to determine outputs from binary inputs. These operations are critical for understanding how logic gates manipulate data to perform computations. Below are the basic Boolean operations that are pivotal in digital electronics: + +1. **AND**: Returns true if all the inputs are true. +2. **OR**: Returns true if at least one of the inputs is true. +3. **NOT**: Returns the opposite of the input value. +4. **BUFFER**: Passes the input directly to the output without any modification. +5. **XOR** (Exclusive OR): Returns true if an odd number of inputs are true. + +Each of these operations corresponds to a specific type of logic gate that we will explore next, demonstrating how theoretical Boolean logic is applied practically in hardware design. + +### Basic Types of Logic Gates + +Every logic gate has one output terminal (Z). The number of input terminal can vary from `1` to `N`. + +#### AND Gate +**Function**: Produces an output of `1` only if all its inputs are `1`. +**Input Terminals**: 2 or more. + +**Truth Table**: + +A | B| Z +---------|----------|--------- +0 | 0 | 0 +0 | 1 | 0 +1 | 0 | 0 +1 | 1 | 1 + +**Digital Hardware Symbol**: + + +**Practical application in programming**: in a while loop, an `AND` gate can be used to ensure that the loop continues to iterate only as long as all specified conditions remain true, + +```cpp +while (conditionA && conditionB) { + // execute code +} +``` + +#### OR Gate +**Function**: Produces an output of `1` only if at least one of its inputs is `1`. +**Input Terminals**: 2 or more. + +**Truth Table**: + +A | B| Z +---------|----------|--------- +0 | 0 | 0 +0 | 1 | 1 +1 | 0 | 1 +1 | 1 | 1 + +**Digital Hardware Symbol**: + + +**Practical application in programming**: used to ensure that a certain block of code executes if any of the specified conditions are true, + +```cpp +if (condition1 || condition2) { + // execute code +} +``` + +#### XOR Gate +**Function**: Produces an output of `1` when an odd number of inputs are `1`. +**Input Terminals**: 2 or more. + +**Truth Table**: + +A | B| Z +---------|----------|--------- +0 | 0 | 0 +0 | 1 | 1 +1 | 0 | 1 +1 | 1 | 0 + +**Digital Hardware Symbol**: + + +**Practical application in programming**: useful when you need to check for conditions that must be mutually exclusive, like scenarios such as setting toggles where one option disables the other, + +```cpp +if (condition1 ^ condition2) { + // execute code if exactly one condition is true +} +``` + +#### NOT Gate (Inverter) +**Function**: Produces an output that is the inverse of the input. +**Input Terminals**: exactly 1. + +**Truth Table**: + +A | Z +---------|---------- +0 | 1 +1 | 0 + +**Digital Hardware Symbol**: + + +**Practical application in programming**: an if statement where you want to execute code only if a condition is not met, + +```cpp +if (!condition) { + // execute code if the condition is false +} +``` + +#### BUFFER Gate +**Function**: Outputs exactly what it receives as input; it acts as a repeater. +**Input Terminals**: exactly 1. + +**Truth Table**: + +A | Z +---------|---------- +0 | 0 +1 | 1 + +**Digital Hardware Symbol**: + + +**Practical application**: Not obvious in programming, but A buffer gate in digital hardware level serves as a signal **strengthener**, essentially passing the input it receives directly to its output without alteration, but often with increased drive capability. This means it helps in maintaining the integrity of the signal through physically long circuits or across components that might degrade the signal due to resistance or other factors. + +### Combining Logic Gates + +Understanding how these gates work individually is just the beginning. The next step is to see how they **combine** to perform **complex** operations and make decisions within digital circuits (and ultimately how to make a **general purpose computers** from billions of these gates). This knowledge is not only pivotal for building hardware but also enhances our ability to design efficient, **programmable** systems. + +For example, let's build a two-bit **comparator** that determines if one binary number $$A$$ is **greater** than another $$B$$ (only checking for greater than, *not* less than). Each binary number consists of two bits: $$A_1A_0$$, and $$B_1B_0$$. The comparator will produce a one bit output indicating whether $$A\geB$$. If you were to write a **program** for this, you would write something like this: + +```py +def is_a_greater_than_b(A1, A0, B1, B0): + # Check the most significant bits first + if A1 and not B1: + return True + elif A1 == B1: + # If most significant bits are equal, check the least significant bits + if A0 and not B0: + return True + else: + return False + else: + return False + +# Example usage: +# Let's assume A = 10 (binary) and B = 01 (binary) +# A1 = 1, A0 = 0, B1 = 0, B0 = 1 +result = is_a_greater_than_b(1, 0, 0, 1) +print("Is A > B?", result) +``` + +The logic of the function implemented in Python above can be translated into a **hardware design** using logic gates, which form the basis of a hardware comparator unit. In hardware, the function's operations—comparing bits and determining the result based on their values—would be implemented using a combination of basic logic gates such as AND, OR, NOT, and XOR gates. Here's a hardware design that implements `is_a_greater_than_b` function above: + + + + +**Breakdown** + +1. **Comparing Most Significant Bits (MSBs)**: + - **AND Gate**: Used to check if \( A1 \) is 1 and \( B1 \) is 0 directly, mapping to `A1 and not B1`. + - This result can directly influence the output if \( A \) is greater, bypassing the need to check the least significant bits (LSBs). + +2. **Equality Check**: + - **XNOR Gate**: Typically, you might use an XNOR gate to compare \( A1 \) and \( B1 \) to check for equality because XNOR outputs true when both inputs are equal. This can control whether to proceed to compare the LSBs. + +3. **Comparing Least Significant Bits (LSBs)**: + - **AND Gate**: Similar to the MSB comparison, another AND gate can be used for `A0 and not B0` to check the condition when the MSBs are equal. + +4. **Overall Logic**: + - **OR Gate**: If \( A1 > B1 \) or (if equal and \( A0 > B0 \)), then \( A > B \). This can be implemented by feeding the outputs of the respective AND gates to an OR gate, whose output would then represent \( A > B \). + +5. **Final Output**: + - The outputs of these gates would typically be connected to form the logic needed for the comparator. For \( A = B \), the output from an XNOR gate (checking both bits pairs) could be used directly, and for \( A < B \), you could mirror the \( A > B \) logic by swapping inputs. + +### Example of Practical Application +In practical applications, such hardware comparators are used in sorting algorithms implemented in hardware, digital signal processing for real-time decision making, and anywhere within a digital system where two binary values need to be **compared** quickly and efficiently without the overhead of software computation. + +For instance: **automatic focus adjustment in digital cameras** +- Multiple hardware comparators can be used to compare the sharpness levels (converted into binary values) of different focus settings in real-time. +- Each comparator evaluates pairs of sharpness values to determine which focus setting produces a clearer, sharper image. +- The use of hardware comparators allows this decision process to be almost instantaneous, which is essential for photography where lighting and scene conditions can change rapidly. + +## Abstraction: A General Purpose Computer + +Logic gates form the bedrock upon which general-purpose computers are built, translating fundamental digital principles into versatile computing capabilities. By implementing basic operations like AND, OR, and NOT at the hardware level, these gates enable computers to perform complex calculations and decision-making processes efficiently. + +{:.important} +This foundational hardware logic allows developers to abstract away from the physical electronics to focus on software development. + +In practical terms, this means that *instead* of manually constructing circuits in a lab for specific tasks, programmers can write flexible and sophisticated Python code that the computer interprets and executes using its underlying logic gate-driven architecture. Thus, the intricate arrangement of logic gates in a computer's hardware directly empowers the high-level programming and software applications that drive modern technology, seamlessly bridging the gap between electronic design and software functionality. + ## [Information and uncertainty](https://www.youtube.com/watch?v=IicB30kA3pY&list=PLklpDKpv-EBj1agIq4vB1iB6ahMT8_2A_&index=1&t=1761s) +After exploring the fundamental operations performed by logic gates, it's crucial to **understand** how these elements contribute to the broader context of information processing in computing systems. + +{:.highlight} +Information theory, which quantifies the amount of information in messages or events based on their probability, provides a mathematical foundation for many aspects of computer science, including data compression, error detection, and cryptography. The amount of information held by an **event** is **inversely proportional to** the probability $$p$$ of that event happening, @@ -246,7 +456,9 @@ With the formula above, `N=8`, `M=3`, therefore: $$\begin{aligned} I_{8\rightarrow 3}(X) = \log_2 \left( \frac{8}{3} \right) = 1.42 \text{ bits} \end{aligned}$$ - + +{:.important} +It is important to consider how the certainty or predictability of an event (or data set) **influences** how we can encode, transmit, and store it. The concepts of entropy and the logarithmic measure of information provide the theoretical underpinnings for many practical applications in computer science. Head to [appendix](#practical-relevance-of-information-theory) for relevant practical examples if you're interested. ## [Summary](https://www.youtube.com/watch?v=IicB30kA3pY&list=PLklpDKpv-EBj1agIq4vB1iB6ahMT8_2A_&index=1&t=2094s) @@ -280,8 +492,8 @@ Finally, you might be wondering why are we *counting the number of bits* require As said in the introduction, the **goal** of this course is to learn how to build a general-purpose digital device (computers). We begin the first half of our learning journey by trying to **create** a digital device (not for general purpose yet) that's for a **specific purpose,** for example: -* a *simple* device that can perform 1-bit addition *(Mini Hardware Project)*, -* a *simple* device that can perform basic logic computation: addition, subtraction, bitshift, boolean operation *(SW Lab 3: ALU)*, +* a *simple* device that can perform N-bit addition *(Lab 1: Combinational Logic With FPGA)*, +* a *simple* device that can perform basic logic computation: addition, subtraction, bitshift, boolean operation *(Lab 3 & 4: ALU)*, * a *simple* electronic game device that can take input from players, compute it, and determine the winner *(1D Project)* @@ -321,5 +533,30 @@ We will consider all things necessary to create this programmable device that ca {:.note} "Computers" include any device: your laptops, desktops, and smartphones, etc for which you can install and run various kinds of software. +# Appendix + +## Practical Relevance of Information Theory +Expanding the practical relevance of information theory, let's further explore how the foundational principles link to the applications of logic gates and their broader impacts on technology and digital systems. + +#### Error Detection and Correction: +The principles of information theory are crucial in the design of error-correcting codes. These codes are fundamental for communication systems, where they ensure that data is transmitted accurately over noisy channels. Logic gates are integral in constructing these codes; for instance, XOR gates are often used in parity checks, which are a basic form of error detection. Engineers design circuits that automatically correct errors in data transmission, enhancing reliability in everything from satellite communications to internet traffic. + +#### Data Compression: +Information theory provides the mathematical underpinnings for data compression techniques, which are essential for managing large datasets, streaming video, and optimizing storage. Compression algorithms, like Huffman coding or Lempel-Ziv, rely on the probabilities of data occurrences to reduce the number of bits required to represent the data. Logic gates in hardware accelerators perform these algorithms rapidly, supporting real-time data compression which is crucial for streaming services and telecommunication. + +#### Optimizing Data Storage and Retrieval: +In the context of databases and memory systems, the 'information content' or entropy of data determines the most efficient ways to store and retrieve it. For example, databases use indexing mechanisms, which are optimized based on the expected frequency of query terms, directly applying principles from information theory. Logic gates are used to design the circuits in SSDs and RAM that manage data access and storage, ensuring quick retrieval and efficient space usage. + +#### Digital Signal Processing (DSP): +Digital signal processors use various algorithms to manipulate signals such as audio, video, and other data inputs in real time. Information theory guides DSP algorithms to filter out noise and enhance signal integrity. Logic gates are employed in DSP chips to execute these algorithms efficiently, enabling applications like noise-canceling headphones and high-definition television. + +#### Network Routing and Management: +Information theory also informs network routing algorithms that manage the flow of data across computer networks. Routing protocols use probabilities and information metrics to make decisions about the best paths for data packets to travel, optimizing network performance and reliability. The hardware that drives these decisions uses complex arrays of logic gates to process routing information dynamically. + +#### Cryptography: +Cryptography relies heavily on information theory to secure data. Understanding the entropy of systems and their data helps in designing secure encryption protocols, where logic gates play a role in the actual encryption and decryption processes. For instance, XOR gates are a basic component in many encryption algorithms, including stream ciphers. + +### Conclusion +By linking the theoretical aspects of information theory with practical applications through logic gates, we see a direct impact on numerous technologies. These applications not only demonstrate the practical utility of theoretical knowledge but also underscore the importance of digital logic design in modern computing and electronic communication. This expansion into the practical relevance of information theory and logic gates reveals their profound interconnectedness and the pivotal role they play in the technological advancements that define our digital age. diff --git a/docs/Hardware/b_digitalabstraction.md b/docs/Hardware/b_digitalabstraction.md index 4afb6d6..c006fb9 100644 --- a/docs/Hardware/b_digitalabstraction.md +++ b/docs/Hardware/b_digitalabstraction.md @@ -23,41 +23,35 @@ Singapore University of Technology and Design [You can find the lecture video here. ](https://youtu.be/xkVIr8jrtX0) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -1. **Understand Digital Abstraction:** - - Learn how digital circuits encode information using voltage levels to represent binary values. - - Understand the concept of digital abstraction for transforming continuous analog signals into discrete digital values. - -2. **Recognize the Role of Semiconductor Devices:** - - Comprehend the role of MOSFETs in generating voltage levels for digital bits. - - Discuss the advantages of using semiconductors for digital encoding and the challenges posed by external disturbances. - -3. **Apply the Static Discipline in Digital Systems:** - - Understand the static discipline as a contract ensuring predictable behavior in digital systems. - - Learn how the static discipline guarantees that valid inputs lead to valid outputs, ensuring system reliability. - -4. **Explore Combinational Digital Systems:** - - Define combinational devices and systems, detailing their properties and operational criteria. - - Differentiate between combinational and sequential logic devices, emphasizing the memory-less nature of combinational systems. - -5. **Voltage Encoding and Noise Margin:** - - Master the concept of using voltage levels to encode binary data, including defining thresholds for '0' and '1'. - - Understand the importance of noise margins in maintaining signal integrity across digital devices. - -6. **Examine Voltage Specifications and Their Impact:** - - Learn about the specifications for valid voltage levels and how they are used to prevent errors due to noise. - - Discuss how noise margins are established to enhance the robustness of digital systems against external disturbances. - -7. **Utilize Voltage Transfer Characteristic (VTC) Functions:** - - Analyze the Voltage Transfer Characteristic function to determine the behavior of digital systems under various input conditions. - - Evaluate the VTC to ensure that digital devices comply with the static discipline and effectively handle noise. - -8. **Prepare for Practical Applications:** - - Integrate the theoretical knowledge of voltage levels, static discipline, and combinational logic into designing and evaluating digital circuits. - - Prepare for advanced topics in digital systems design, including the use of MOSFETs to build logic gates and more complex combinational circuits. - -These objectives aim to equip students with a solid foundation in digital systems, emphasizing the translation of theoretical concepts into practical applications in digital electronics and circuit design. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Digital Abstraction:** +> - Learn how digital circuits encode information using voltage levels to represent binary values. +> - Understand the concept of digital abstraction for transforming continuous analog signals into discrete digital values. +> 2. **Recognize the Role of Semiconductor Devices:** +> - Comprehend the role of MOSFETs in generating voltage levels for digital bits. +> - Discuss the advantages of using semiconductors for digital encoding and the challenges posed by external disturbances. +> 3. **Apply the Static Discipline in Digital Systems:** +> - Understand the static discipline as a contract ensuring predictable behavior in digital systems. +> - Learn how the static discipline guarantees that valid inputs lead to valid outputs, ensuring system reliability. +> 4. **Explore Combinational Digital Systems:** +> - Define combinational devices and systems, detailing their properties and operational criteria. +> - Differentiate between combinational and sequential logic devices, emphasizing the memory-less nature of combinational systems. +> 5. **Voltage Encoding and Noise Margin:** +> - Master the concept of using voltage levels to encode binary data, including defining thresholds for '0' and '1'. +> - Understand the importance of noise margins in maintaining signal integrity across digital devices. +> 6. **Examine Voltage Specifications and Their Impact:** +> - Learn about the specifications for valid voltage levels and how they are used to prevent errors due to noise. +> - Discuss how noise margins are established to enhance the robustness of digital systems against external disturbances. +> 7. **Utilize Voltage Transfer Characteristic (VTC) Functions:** +> - Analyze the Voltage Transfer Characteristic function to determine the behavior of digital systems under various input conditions. +> - Evaluate the VTC to ensure that digital devices comply with the static discipline and effectively handle noise. +> 8. **Prepare for Practical Applications:** +> - Integrate the theoretical knowledge of voltage levels, static discipline, and combinational logic into designing and evaluating digital circuits. +> - Prepare for advanced topics in digital systems design, including the use of MOSFETs to build logic gates and more complex combinational circuits. +> +> These objectives aim to equip students with a solid foundation in digital systems, emphasizing the translation of theoretical concepts into practical applications in digital electronics and circuit design. ## [Overview](https://www.youtube.com/watch?v=xkVIr8jrtX0&t=0s) @@ -88,6 +82,10 @@ A combinational device is a specific type of digital device that has the followi 3. A **functional specification** that details the value of each output for each possible **combination** of inputs (can be illustrated in terms of truth table / boolean expression) 4. A **timing specification** consisting of an upper bound required propagation time for the device to compute the specified output values given a set of valid and stable input value(s) +{:.note} +You have seen this in our previous chapter: the $$A>B$$ 2-bit comparator device is a **combinational device**, consisted of pure logic gates and behave like a pure function. + + Later on you will learn another type of digital logic devices called the **sequential** logic device, whose output depends not only on the present input but also on the history of the inputs, hence having a *memory*. A **set** of interconnected circuit elements is **combinational** and can be labeled as a **combinational digital system** if and only if: @@ -107,11 +105,13 @@ Anything that is between the low and high threshold value is called the invalid The values of operating voltage in practice is commonly set to be 0.3V for low voltage and 3.3V for high voltage. ## [The Static Discipline](https://www.youtube.com/watch?v=xkVIr8jrtX0&t=634s) -The static discipline is one of the **contracts** bound for all logical elements making up a digital system. The static discipline is stated as follows: +The static discipline is one of the **contracts** bound for all logical elements making up a digital system. -{: .important} -**A digital system must be able to produce a valid output (for the next device connected at its output terminal) according to its specification if it is given a valid input.** +{: .important-title} +> The Static Discipline +> +> A digital system **must** be able to produce a valid output (for the next device connected at its output terminal) according to its specification if it is given a valid input. This contract **guarantees** the behavior for each processing block in a system, so that a set of such interconnected devices may work properly (are able to pass and compute valid information at the end of the chain of connections). This is necessary so that the system has a **predictable behavior.** @@ -120,12 +120,10 @@ Therefore, one can say that **a combinational logic device always obeys the stat However this doesn't mean that the opposite is true. -{:.important} -A device receiving invalid input doesn't necessarily produce invalid output. The output from a combinational logic device given invalid input remains unpredictable. Remember, for your Mini Hardware Project, include a pulldown resistor at each input to ensure a valid 0 when the switch is open. Without a pulldown resistor, an input left unconnected (open wire) leads to invalid input, which results in uncertain or random output. Essentially, the behavior of a combinational device with invalid input is indeterminate and cannot be precisely defined or assured—it might or might not yield a valid output. - +A device receiving invalid input does not necessarily produce invalid output. The output from a combinational logic device given invalid input remains *unpredictable*. - - +{:.note} +An unconnected terminal or a dangling wire in a digital circuit is not considered a valid low digital signal. In digital electronics, each signal line or terminal must have a definite state: high (1), low (0), or sometimes a high-impedance state. ## [Voltage Specifications and Noise Margin](https://www.youtube.com/watch?v=xkVIr8jrtX0&t=488s) diff --git a/docs/Hardware/c_cmostechnology.md b/docs/Hardware/c_cmostechnology.md index 2f18aa8..61f5ab0 100644 --- a/docs/Hardware/c_cmostechnology.md +++ b/docs/Hardware/c_cmostechnology.md @@ -21,38 +21,32 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here. ](https://youtu.be/JqgZcV_1IU4)You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - - -1. **Understand the Properties of Combinational Logic Devices:** - - Learn the ideal characteristics of a combinational logic device including noise tolerance, power dissipation, and functional reliability. - - Comprehend the significance of noise margins and their relationship to the gain of the Voltage Transfer Characteristic (VTC). - -2. **Explore the Basics of MOSFETs:** - - Understand the structure and operation of Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs). - - Identify the roles of the gate, drain, source, and body in MOSFET operation. - -3. **Differentiate Between NFET and PFET:** - - Compare the characteristics and functions of N-type and P-type FETs. - - Learn how NFETs and PFETs are used to implement different logic functions based on their configuration and voltage levels. - -4. **Learn CMOS Technology for Logic Devices:** - - Understand how Complementary MOS (CMOS) technology utilizes both NFETs and PFETs to create efficient logic circuits. - - Explore the concept of pull-up and pull-down networks within CMOS circuits. - -5. **Analyze the CMOS Complementary Recipe:** - - Study the complementary nature of pull-up and pull-down circuits in CMOS technology to prevent short circuits and ensure stable logic states. - - Apply the complementary MOS circuitry to understand basic logic gates like NAND and NOR. - -6. **Master Logic Gate Fundamentals:** - - Identify different types of logic gates and their operations. - - Understand how logic gates are implemented using CMOS technology to fulfill specific logic functions. - -7. **Discuss Timing Specifications in Combinational Logic Devices:** - - Learn about propagation delay and contamination delay as critical timing specifications in digital circuits. - - Understand how these delays impact the performance and reliability of logic circuits. - -These objectives aim to provide students with a comprehensive understanding of the basic building blocks of digital electronics, focusing on MOSFETs and their application in combinational logic devices through CMOS technology. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand the Properties of Combinational Logic Devices:** +> - Learn the ideal characteristics of a combinational logic device including noise tolerance, power dissipation, and functional reliability. +> - Comprehend the significance of noise margins and their relationship to the gain of the Voltage Transfer Characteristic (VTC). +> 2. **Explore the Basics of MOSFETs:** +> - Understand the structure and operation of Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs). +> - Identify the roles of the gate, drain, source, and body in MOSFET operation. +> 3. **Differentiate Between NFET and PFET:** +> - Compare the characteristics and functions of N-type and P-type FETs. +> - Learn how NFETs and PFETs are used to implement different logic functions based on their configuration and voltage levels. +> 4. **Learn CMOS Technology for Logic Devices:** +> - Understand how Complementary MOS (CMOS) technology utilizes both NFETs and PFETs to create efficient logic circuits. +> - Explore the concept of pull-up and pull-down networks within CMOS circuits. +> 5. **Analyze the CMOS Complementary Recipe:** +> - Study the complementary nature of pull-up and pull-down circuits in CMOS technology to prevent short circuits and ensure stable logic states. +> - Apply the complementary MOS circuitry to understand basic logic gates like NAND and NOR. +> 6. **Master Logic Gate Fundamentals:** +> - Identify different types of logic gates and their operations. +> - Understand how logic gates are implemented using CMOS technology to fulfill specific logic functions. +> 7. **Discuss Timing Specifications in Combinational Logic Devices:** +> - Learn about propagation delay and contamination delay as critical timing specifications in digital circuits. +> - Understand how these delays impact the performance and reliability of logic circuits. +> +> These objectives aim to provide students with a comprehensive understanding of the basic building blocks of digital electronics, focusing on MOSFETs and their application in combinational logic devices through CMOS technology. ## [Overview](https://www.youtube.com/watch?v=JqgZcV_1IU4&t=0s) diff --git a/docs/Hardware/d_logicsynthesis.md b/docs/Hardware/d_logicsynthesis.md index 178457b..8f14445 100644 --- a/docs/Hardware/d_logicsynthesis.md +++ b/docs/Hardware/d_logicsynthesis.md @@ -21,41 +21,35 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/yXBAy432vT8) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Learning Objectives - -1. **Understand Combinational Logic Devices:** - - Learn how combinational logic devices synthesize logic to produce specific outputs based on given inputs, adhering to functional specifications or truth tables. - - Explore how functional specifications are expressed through truth tables for different logic gates like NAND and AND. - -2. **Explore Multi-input Logic Gates:** - - Understand the concept of multi-input gates and recognize the computational possibilities and limitations of different gate types. - - Comprehend that the number of possible logic gates increases exponentially with the number of inputs. - -3. **Apply Sum of Products Method:** - - Learn to convert truth tables into Boolean expressions using the sum of products method. - - Understand the process of creating combinational logic expressions that align with specified truth tables. - -4. **Synthesize Logic Using Basic Gates:** - - Master the use of basic logic gates (INV, AND, OR) to synthesize any given Boolean expression. - - Explore straightforward logic synthesis to build complex combinational devices from basic components. - -5. **Utilize Boolean Algebra for Logic Minimization:** - - Apply Boolean algebra properties to manipulate and simplify Boolean expressions. - - Explore various Boolean algebra rules and their applications in reducing logic complexity. - -6. **Implement Universal Gates:** - - Recognize NAND and NOR gates as universal gates capable of implementing any Boolean function. - - Learn to construct basic logic functions using only NAND or NOR gates. - -7. **Understand Special Combinational Logic Devices:** - - Examine the functionality and application of multiplexers and demultiplexers in digital circuits. - - Learn how multiplexers can implement any Boolean function by selecting among multiple inputs. - -8. **Investigate the Use of ROMs for Hardcoding Logic:** - - Explore the use of Read-Only Memories (ROMs) to permanently encode specific logic functions. - - Understand the physical layout and logic implications of using ROMs in digital circuit design. - -These objectives are designed to provide students with a thorough understanding of how combinational logic devices are conceptualized, designed, and implemented in digital electronics, fostering a foundation for more complex system designs. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Combinational Logic Devices:** +> - Learn how combinational logic devices synthesize logic to produce specific outputs based on given inputs, adhering to functional specifications or truth tables. +> - Explore how functional specifications are expressed through truth tables for different logic gates like NAND and AND. +> 2. **Explore Multi-input Logic Gates:** +> - Understand the concept of multi-input gates and recognize the computational possibilities and limitations of different gate types. +> - Comprehend that the number of possible logic gates increases exponentially with the number of inputs. +> 3. **Apply Sum of Products Method:** +> - Learn to convert truth tables into Boolean expressions using the sum of products method. +> - Understand the process of creating combinational logic expressions that align with specified truth tables. +> 4. **Synthesize Logic Using Basic Gates:** +> - Master the use of basic logic gates (INV, AND, OR) to synthesize any given Boolean expression. +> - Explore straightforward logic synthesis to build complex combinational devices from basic components. +> 5. **Utilize Boolean Algebra for Logic Minimization:** +> - Apply Boolean algebra properties to manipulate and simplify Boolean expressions. +> - Explore various Boolean algebra rules and their applications in reducing logic complexity. +> 6. **Implement Universal Gates:** +> - Recognize NAND and NOR gates as universal gates capable of implementing any Boolean function. +> - Learn to construct basic logic functions using only NAND or NOR gates. +> 7. **Understand Special Combinational Logic Devices:** +> - Examine the functionality and application of multiplexers and demultiplexers in digital circuits. +> - Learn how multiplexers can implement any Boolean function by selecting among multiple inputs. +> 8. **Investigate the Use of ROMs for Hardcoding Logic:** +> - Explore the use of Read-Only Memories (ROMs) to permanently encode specific logic functions. +> - Understand the physical layout and logic implications of using ROMs in digital circuit design. +> +> These objectives are designed to provide students with a thorough understanding of how combinational logic devices are conceptualized, designed, and implemented in digital electronics, fostering a foundation for more complex system designs. ## [Overview](https://www.youtube.com/watch?v=yXBAy432vT8&t=0s) The purpose of creating combinational devices is to **synthesise logic**, meaning that we create a device that is able to give a certain combination of output given a certain combination input. In other words, a device that adheres to a truth table, i.e: its *functional specification.* diff --git a/docs/Hardware/e_sequentiallogic.md b/docs/Hardware/e_sequentiallogic.md index 0139b3d..96b7aac 100644 --- a/docs/Hardware/e_sequentiallogic.md +++ b/docs/Hardware/e_sequentiallogic.md @@ -21,45 +21,38 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/HlizelEp4Yc) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -1. **Distinguish Sequential and Combinational Logic Devices** - - Understand the functional differences between sequential and combinational logic devices. - - Explore the role of memory elements in sequential devices which allow them to store and reference past inputs. - -2. **Explore Memory Devices: D Flip-Flops and D-Latches** - - Learn about the structure and operational modes (write and memory modes) of D Flip-Flops and D-Latches. - - Examine how these memory devices integrate with combinational logic to form sequential logic circuits. - -3. **Identify the Role of the Clock Signal** - - Recognize the critical role of the clock (CLK) signal in managing the behavior of sequential logic devices. - - Understand how the CLK signal ensures synchronization of inputs for reliable operation. - -4. **Understand Edge-Triggered D Flip-Flops** - - Explore the design and functionalities of Edge-Triggered D Flip-Flops, focusing on master and slave latch configurations. - - Learn the importance of clock signal inversion and its impact on the operational dynamics of D Flip-Flops. - -5. **Comprehend Dynamic Discipline Requirements** - - Understand the necessity of setup time (\(T_{setup}\)) and hold time (\(T_{hold}\)) to prevent the storage of invalid information. - - Recognize how adhering to dynamic discipline ensures the reliability of sequential circuits. - -6. **Analyze Timing Constraints in Sequential Circuits** - - Grasp the importance of critical timing constraints (\(t_1\) and \(t_2\)) between sequential logic devices. - - Study how these constraints ensure stable and valid outputs throughout clock cycles. - -7. **Discuss Synchronization Challenges of External Inputs** - - Address the difficulties in synchronizing external inputs with the clock in sequential circuits. - - Examine potential issues arising from violations of the dynamic discipline. - -8. **Recognize the Metastable State in Sequential Logic Devices** - - Identify what a metastable state is and the conditions that lead to its occurrence in sequential logic devices. - - Evaluate the consequences and impacts on circuit functionality when a device enters a metastable state. - -9. **Evaluate Methods to Minimize Metastability** - - Analyze strategies to reduce the likelihood of a device entering a metastable state. - - Consider the trade-offs involved in these strategies, such as cost, responsiveness, and device size. - -The aim of these learning objectives is to thoroughly understand sequential and combinational logic devices, focusing on their differences, integration of memory elements, operational synchronization, and challenges in maintaining reliable and efficient functionality. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Distinguish Sequential and Combinational Logic Devices** +> - Understand the functional differences between sequential and combinational logic devices. +> - Explore the role of memory elements in sequential devices which allow them to store and reference past inputs. +> 2. **Explore Memory Devices: D Flip-Flops and D-Latches** +> - Learn about the structure and operational modes (write and memory modes) of D Flip-Flops and D-Latches. +> - Examine how these memory devices integrate with combinational logic to form sequential logic circuits. +> 3. **Identify the Role of the Clock Signal** +> - Recognize the critical role of the clock (CLK) signal in managing the behavior of sequential logic devices. +> - Understand how the CLK signal ensures synchronization of inputs for reliable operation. +> 4. **Understand Edge-Triggered D Flip-Flops** +> - Explore the design and functionalities of Edge-Triggered D Flip-Flops, focusing on master and slave latch configurations. +> - Learn the importance of clock signal inversion and its impact on the operational dynamics of D Flip-Flops. +> 5. **Comprehend Dynamic Discipline Requirements** +> - Understand the necessity of setup time (\(T_{setup}\)) and hold time (\(T_{hold}\)) to prevent the storage of invalid information. +> - Recognize how adhering to dynamic discipline ensures the reliability of sequential circuits. +> 6. **Analyze Timing Constraints in Sequential Circuits** +> - Grasp the importance of critical timing constraints (\(t_1\) and \(t_2\)) between sequential logic devices. +> - Study how these constraints ensure stable and valid outputs throughout clock cycles. +> 7. **Discuss Synchronization Challenges of External Inputs** +> - Address the difficulties in synchronizing external inputs with the clock in sequential circuits. +> - Examine potential issues arising from violations of the dynamic discipline. +> 8. **Recognize the Metastable State in Sequential Logic Devices** +> - Identify what a metastable state is and the conditions that lead to its occurrence in sequential logic devices. +> - Evaluate the consequences and impacts on circuit functionality when a device enters a metastable state. +> 9. **Evaluate Methods to Minimize Metastability** +> - Analyze strategies to reduce the likelihood of a device entering a metastable state. +> - Consider the trade-offs involved in these strategies, such as cost, responsiveness, and device size. +> +> The aim of these learning objectives is to thoroughly understand sequential and combinational logic devices, focusing on their differences, integration of memory elements, operational synchronization, and challenges in maintaining reliable and efficient functionality. ## [Overview](https://www.youtube.com/watch?v=HlizelEp4Yc&t=0s) diff --git a/docs/Hardware/f_fsm.md b/docs/Hardware/f_fsm.md index 0d82c20..99c66ed 100644 --- a/docs/Hardware/f_fsm.md +++ b/docs/Hardware/f_fsm.md @@ -21,36 +21,31 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/efLcdpqlAyI) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -- **Understand the Concept of Finite State Machines (FSMs):** - - Define a finite state machine (FSM) and its components: states, inputs, outputs, transitions, and outputs rules. - - Recognize the practical applications of FSMs in everyday devices like traffic lights and electronic locks. - -- **Differentiate Between Moore and Mealy Machines:** - - Identify the structural differences between Moore and Mealy FSMs. - - Analyze how outputs are determined in both Moore and Mealy machines based on state and input. - -- **Develop State Machine Diagrams and Truth Tables:** - - Create state machine diagrams and corresponding truth tables for digital lock mechanisms. - - Learn how to encode states for a given number of required bits. - -- **Build and Analyze FSMs:** - - Transform state machine descriptions into Boolean equations. - - Construct FSMs using different digital components like flip-flops and combinational logic units. - -- **Compare and Contrast Moore and Mealy Machines:** - - Discuss the advantages and disadvantages of Moore and Mealy machines in terms of state requirements and response times. - -- **Enumerate and Reduce FSMs:** - - Understand the concept of state equivalence and reduction to minimize the number of states in an FSM. - - Calculate the number of possible FSMs based on given bits for states, inputs, and outputs. - -- **Discuss FSM Limitations:** - - Recognize the limitations of FSMs in computing tasks that require arbitrarily many states. - - Prepare for the introduction to Turing machines as a more capable model of computation. - -The aim of these learning objectives is to master the fundamentals of finite state machines (FSMs), distinguishing between Moore and Mealy types, and to apply this knowledge in building, analyzing, and optimizing FSMs for various digital applications, while also preparing for advanced computational models like Turing machines. +{:.highlight-title} +> Detailed Learning Objectives +> +> - **Understand the Concept of Finite State Machines (FSMs):** +> - Define a finite state machine (FSM) and its components: states, inputs, outputs, transitions, and outputs rules. +> - Recognize the practical applications of FSMs in everyday devices like traffic lights and electronic locks. +> - **Differentiate Between Moore and Mealy Machines:** +> - Identify the structural differences between Moore and Mealy FSMs. +> - Analyze how outputs are determined in both Moore and Mealy machines based on state and input. +> - **Develop State Machine Diagrams and Truth Tables:** +> - Create state machine diagrams and corresponding truth tables for digital lock mechanisms. +> - Learn how to encode states for a given number of required bits. +> - **Build and Analyze FSMs:** +> - Transform state machine descriptions into Boolean equations. +> - Construct FSMs using different digital components like flip-flops and combinational logic units. +> - **Compare and Contrast Moore and Mealy Machines:** +> - Discuss the advantages and disadvantages of Moore and Mealy machines in terms of state requirements and response times. +> - **Enumerate and Reduce FSMs:** +> - Understand the concept of state equivalence and reduction to minimize the number of states in an FSM. +> - Calculate the number of possible FSMs based on given bits for states, inputs, and outputs. +> - **Discuss FSM Limitations:** +> - Recognize the limitations of FSMs in computing tasks that require arbitrarily many states. +> - Prepare for the introduction to Turing machines as a more capable model of computation. +> +> The aim of these learning objectives is to master the fundamentals of finite state machines (FSMs), distinguishing between Moore and Mealy types, and to apply this knowledge in building, analyzing, and optimizing FSMs for various digital applications, while also preparing for advanced computational models like Turing machines. ## [Overview](https://www.youtube.com/watch?v=efLcdpqlAyI&t=0s) diff --git a/docs/Hardware/g_turingmachine.md b/docs/Hardware/g_turingmachine.md index 712c4fe..5b9bc8f 100644 --- a/docs/Hardware/g_turingmachine.md +++ b/docs/Hardware/g_turingmachine.md @@ -22,38 +22,32 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/cmfDBAiogA0) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -1. **Recognize the Limitations of Finite State Machines (FSMs)** - - Understand that FSMs are limited by their lack of memory beyond the current state, making them unable to solve problems requiring knowledge of state visitation history, such as detecting palindromes or checking balanced parentheses. - -2. **Describe the Concept and Functionality of Turing Machines** - - Learn about the Turing Machine as a mathematical model capable of performing computations that FSMs cannot, including handling infinitely long inputs via its tape mechanism. - -3. **Explain the Basic Operation of a Turing Machine** - - Understand how a Turing Machine reads, writes, and manipulates data on an infinitely long tape using a set of defined states and transitions. - -4. **Illustrate the Process of Operating a Turing Machine** - - Describe the step-by-step process of how a Turing Machine moves through its tape, processes data, and utilizes its halt and start states effectively. - -5. **Analyze Specific Examples of Turing Machine Applications** - - Examine detailed examples such as an Increment Machine and a Coin Counter Machine to see how Turing Machines handle complex computations and scenarios beyond the capability of FSMs. - -6. **Understand the Concept of a Universal Turing Machine** - - Learn how a Universal Turing Machine simulates any other Turing Machine, representing the theoretical foundation for modern general-purpose computers. - -7. **Explore Church’s Thesis and Computable Functions** - - Discuss the implications of Church's Thesis regarding the capabilities of Turing Machines and the definition of computable functions. - -8. **Identify Examples of Uncomputable Functions** - - Recognize functions that cannot be computed by any algorithm, illustrating the limits of computational theory. - -9. **Appreciate the Impact of Turing Machines on Computer Science** - - Reflect on how the development of Turing Machines and their universal capabilities have revolutionized approaches to computational tasks and machine design. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Recognize the Limitations of Finite State Machines (FSMs)** +> - Understand that FSMs are limited by their lack of memory beyond the current state, making them unable to solve problems requiring knowledge of state visitation history, such as detecting palindromes or checking balanced parentheses. +> 2. **Describe the Concept and Functionality of Turing Machines** +> - Learn about the Turing Machine as a mathematical model capable of performing computations that FSMs cannot, including handling infinitely long inputs via its tape mechanism. +> 3. **Explain the Basic Operation of a Turing Machine** +> - Understand how a Turing Machine reads, writes, and manipulates data on an infinitely long tape using a set of defined states and transitions. +> 4. **Illustrate the Process of Operating a Turing Machine** +> - Describe the step-by-step process of how a Turing Machine moves through its tape, processes data, and utilizes its halt and start states effectively. +> 5. **Analyze Specific Examples of Turing Machine Applications** +> - Examine detailed examples such as an Increment Machine and a Coin Counter Machine to see how Turing Machines handle complex computations and scenarios beyond the capability of FSMs. +> 6. **Understand the Concept of a Universal Turing Machine** +> - Learn how a Universal Turing Machine simulates any other Turing Machine, representing the theoretical foundation for modern general-purpose computers. +> 7. **Explore Church’s Thesis and Computable Functions** +> - Discuss the implications of Church's Thesis regarding the capabilities of Turing Machines and the definition of computable functions. +> 8. **Identify Examples of Uncomputable Functions** +> - Recognize functions that cannot be computed by any algorithm, illustrating the limits of computational theory. +> 9. **Appreciate the Impact of Turing Machines on Computer Science** +> - Reflect on how the development of Turing Machines and their universal capabilities have revolutionized approaches to computational tasks and machine design. +> 10. **Summarize the Principle of Programmability in Computing** +> - Conclude with the significance of the programmable nature of computers, facilitated by the conceptual framework provided by Turing Machines and their ability to emulate an infinite set of instructions. +> +> These learning objectives equip students with a deep understanding of computational models, particularly focusing on the capabilities and limitations of Finite State Machines and Turing Machines, thereby providing a solid foundation in theoretical computer science that underpins modern computing technologies and concepts. -10. **Summarize the Principle of Programmability in Computing** - - Conclude with the significance of the programmable nature of computers, facilitated by the conceptual framework provided by Turing Machines and their ability to emulate an infinite set of instructions. - ## [Overview](https://www.youtube.com/watch?v=cmfDBAiogA0&t=0s) A Finite State Machine does not keep track of the number of states it *visited*, it is only aware of the current state *it is in*. Therefore it is unable to solve problems like detecting palindrome or checking balanced parenthesis. There is no way to tell whether you have visited a state for the first time, or for the $$n^{th}$$ time. diff --git a/docs/Hardware/h_instructionset.md b/docs/Hardware/h_instructionset.md index 4039b82..4e154ad 100644 --- a/docs/Hardware/h_instructionset.md +++ b/docs/Hardware/h_instructionset.md @@ -21,40 +21,31 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/h1KGzAbJH4Q) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - - -1. **Define a Basic Programmable Machine** - - Understand the requirements for a machine to be programmable, including expandable memory, a rich repertoire of operations, and the ability to execute newly generated programs. - -2. **Explore the Concept of a Datapath** - - Learn about datapaths, which consist of combinational devices, registers, and buses, and their role in processing inputs to produce outputs within a machine. - -3. **Identify the Role of Control Signals in Machine Operations** - - Recognize how control signals influence the behavior of circuits in a programmable machine, allowing for varied operations across different time steps. - -4. **Examine the Functionality of Control FSM Units** - - Analyze how different Control FSM (Finite State Machine) units can alter a machine's operations, making it programmable through variable control signal sequences. - -5. **Discuss the Constraints of Simple Programmable Machines** - - Consider the limitations of basic programmable machines in terms of storage capacity, operation diversity, and self-programming capabilities. - -6. **Describe the Von Neumann Architecture** - - Understand the structure and components of the Von Neumann architecture, including the CPU, memory unit, and input/output mechanisms, and how they integrate via data/address buses. - -7. **Detail the CPU’s Components and Functions** - - Explore the internal structure of a CPU, including its data path, control unit, ALU, and internal storage, and how these components interact to execute instructions. - -8. **Examine the Memory Unit’s Role and Functions** - - Learn about the functionality of memory units in storing data and instructions, how data is organized and accessed, and the concept of byte-addressable memory. - -9. **Understand Instruction Set Architectures** - - Grasp the importance of an ISA in defining the operations a CPU can perform, and how it facilitates the programming of a computer to perform a wide range of tasks. - -10. **Translate Between High-Level Languages and Machine Language** - - Explore the process of translating high-level programming languages into assembly and then into machine language, emphasizing the role of compilers and interpreters. - -These objectives guide students through understanding the foundational concepts of programmable machines, their architectural designs, and the transformation of high-level programming constructs into executable machine code. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Define a Basic Programmable Machine** +> - Understand the requirements for a machine to be programmable, including expandable memory, a rich repertoire of operations, and the ability to execute newly generated programs. +> 2. **Explore the Concept of a Datapath** +> - Learn about datapaths, which consist of combinational devices, registers, and buses, and their role in processing inputs to produce outputs within a machine. +> 3. **Identify the Role of Control Signals in Machine Operations** +> - Recognize how control signals influence the behavior of circuits in a programmable machine, allowing for varied operations across different time steps. +> 4. **Examine the Functionality of Control FSM Units** +> - Analyze how different Control FSM (Finite State Machine) units can alter a machine's operations, making it programmable through variable control signal sequences. +> 5. **Discuss the Constraints of Simple Programmable Machines** +> - Consider the limitations of basic programmable machines in terms of storage capacity, operation diversity, and self-programming capabilities. +> 6. **Describe the Von Neumann Architecture** +> - Understand the structure and components of the Von Neumann architecture, including the CPU, memory unit, and input/output mechanisms, and how they integrate via data/address buses. +> 7. **Detail the CPU’s Components and Functions** +> - Explore the internal structure of a CPU, including its data path, control unit, ALU, and internal storage, and how these components interact to execute instructions. +> 8. **Examine the Memory Unit’s Role and Functions** +> - Learn about the functionality of memory units in storing data and instructions, how data is organized and accessed, and the concept of byte-addressable memory. +> 9. **Understand Instruction Set Architectures** +> - Grasp the importance of an ISA in defining the operations a CPU can perform, and how it facilitates the programming of a computer to perform a wide range of tasks. +> 10. **Translate Between High-Level Languages and Machine Language** +> - Explore the process of translating high-level programming languages into assembly and then into machine language, emphasizing the role of compilers and interpreters. +> +> These objectives guide students through understanding the foundational concepts of programmable machines, their architectural designs, and the transformation of high-level programming constructs into executable machine code. ## [Overview](https://www.youtube.com/watch?v=h1KGzAbJH4Q&t=0s) To create a programmable control system suitable for *general* purposes (like the Universal Turing Machine), we need to define a set of instructions for that system, such that it is able to support a rich repertoire of operations. diff --git a/docs/Hardware/i_betacpu.md b/docs/Hardware/i_betacpu.md index d93d6b2..a688e0f 100644 --- a/docs/Hardware/i_betacpu.md +++ b/docs/Hardware/i_betacpu.md @@ -21,33 +21,27 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/4T9MR8BSzt0) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - -1. **Understand Control Logic and CPU Instruction Handling** - - Learn how the Control Logic unit decodes the OPCODE of instructions and outputs appropriate control signals to manipulate the datapath for executing various instructions. - -2. **Examine the Instruction Fetch and Decode Process** - - Explore how the CPU fetches and decodes instructions during each clock cycle, focusing on the computation of instruction addresses and the decoding of OPCODEs. - -3. **Analyze the Detailed Anatomy of the $$\beta$$ CPU** - - Study the components of the $$\beta$$ CPU, including the Program Counter (PC), Register Files (REGFILE), Arithmetic Logic Unit (ALU), and Control Unit (CU), and their interconnections. - -4. **Understand Memory Interaction in the CPU** - - Investigate how instructions interact with memory, specifically how data is loaded and stored between the CPU's registers and the physical memory unit. - -5. **Explore the Control Transfer in CPU Operations** - - Delve into instructions that involve control transfer such as conditional branches and jumps, and understand how they modify the flow of execution within the CPU. - -6. **Familiarize with the $$\beta$$ Instruction Set** - - Gain knowledge of the specific instructions under the $$\beta$$ ISA, their formats, and how they are executed within the CPU's datapath. - -7. **Recognize the Role of the Control Unit in Instruction Execution** - - Identify how the Control Unit's signals direct the CPU's datapath to execute instructions correctly based on the decoded instruction type. - -8. **Assess CPU Performance with Benchmarks** - - Learn how to evaluate CPU performance using metrics such as MIPS (Million Instructions Per Second) and understand the implications of CPI (Clocks Per Instruction) on performance assessment. - -These objectives help students grasp the intricate details of how a CPU interprets and executes instructions based on a predefined instruction set architecture, using the $$\beta$$ CPU as a model system. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Control Logic and CPU Instruction Handling** +> - Learn how the Control Logic unit decodes the OPCODE of instructions and outputs appropriate control signals to manipulate the datapath for executing various instructions. +> 2. **Examine the Instruction Fetch and Decode Process** +> - Explore how the CPU fetches and decodes instructions during each clock cycle, focusing on the computation of instruction addresses and the decoding of OPCODEs. +> 3. **Analyze the Detailed Anatomy of the $$\beta$$ CPU** +> - Study the components of the $$\beta$$ CPU, including the Program Counter (PC), Register Files (REGFILE), Arithmetic Logic Unit (ALU), and Control Unit (CU), and their interconnections. +> 4. **Understand Memory Interaction in the CPU** +> - Investigate how instructions interact with memory, specifically how data is loaded and stored between the CPU's registers and the physical memory unit. +> 5. **Explore the Control Transfer in CPU Operations** +> - Delve into instructions that involve control transfer such as conditional branches and jumps, and understand how they modify the flow of execution within the CPU. +> 6. **Familiarize with the $$\beta$$ Instruction Set** +> - Gain knowledge of the specific instructions under the $$\beta$$ ISA, their formats, and how they are executed within the CPU's datapath. +> 7. **Recognize the Role of the Control Unit in Instruction Execution** +> - Identify how the Control Unit's signals direct the CPU's datapath to execute instructions correctly based on the decoded instruction type. +> 8. **Assess CPU Performance with Benchmarks** +> - Learn how to evaluate CPU performance using metrics such as MIPS (Million Instructions Per Second) and understand the implications of CPI (Clocks Per Instruction) on performance assessment. +> +> These objectives help students grasp the intricate details of how a CPU interprets and executes instructions based on a predefined instruction set architecture, using the $$\beta$$ CPU as a model system. ## [Overview](https://www.youtube.com/watch?v=4T9MR8BSzt0&t=0s) diff --git a/docs/Hardware/images/cs-2025-A>B.drawio.png b/docs/Hardware/images/cs-2025-A>B.drawio.png new file mode 100644 index 0000000..276c897 Binary files /dev/null and b/docs/Hardware/images/cs-2025-A>B.drawio.png differ diff --git a/docs/Hardware/images/cs-2025-BUFFER.drawio.png b/docs/Hardware/images/cs-2025-BUFFER.drawio.png new file mode 100644 index 0000000..debb6b5 Binary files /dev/null and b/docs/Hardware/images/cs-2025-BUFFER.drawio.png differ diff --git a/docs/Hardware/images/cs-2025-NOT.drawio.png b/docs/Hardware/images/cs-2025-NOT.drawio.png new file mode 100644 index 0000000..6b13188 Binary files /dev/null and b/docs/Hardware/images/cs-2025-NOT.drawio.png differ diff --git a/docs/Hardware/images/cs-2025-OR.drawio.png b/docs/Hardware/images/cs-2025-OR.drawio.png new file mode 100644 index 0000000..eb6e2a2 Binary files /dev/null and b/docs/Hardware/images/cs-2025-OR.drawio.png differ diff --git a/docs/Hardware/images/cs-2025-XOR.drawio.png b/docs/Hardware/images/cs-2025-XOR.drawio.png new file mode 100644 index 0000000..b404d6d Binary files /dev/null and b/docs/Hardware/images/cs-2025-XOR.drawio.png differ diff --git a/docs/Hardware/images/cs-2025.drawio.png b/docs/Hardware/images/cs-2025.drawio.png new file mode 100644 index 0000000..5cf44bb Binary files /dev/null and b/docs/Hardware/images/cs-2025.drawio.png differ diff --git a/docs/Labs/index.md b/docs/Labs/index.md index a46799c..fd685a4 100644 --- a/docs/Labs/index.md +++ b/docs/Labs/index.md @@ -8,13 +8,13 @@ nav_order: 21 # 50.002 Lab {: .no_toc} -The first lab session of the week will be about our [Mini Hardware Project](https://natalieagus.github.io/50002/lab/mhp) (1D Project Part 1). -In week 2 onwards, there are 5 mandatory labs for 50.002: -1. [Lab 1: CMOS 3% (Week 2)](https://natalieagus.github.io/50002/lab/lab1) -2. [Lab 2: Adder 1% (Week 3)](https://natalieagus.github.io/50002/lab/lab2) -3. [Lab 3: ALU 3% (Week 4)](https://natalieagus.github.io/50002/lab/lab3-part1), [Week 5](https://natalieagus.github.io/50002/lab/lab3-part2) -4. [Lab 4: Beta 4% (Week 9)](https://natalieagus.github.io/50002/lab/lab4-part1), [Week 10](https://natalieagus.github.io/50002/lab/lab4-part2) -5. [Lab 5: Assembly 2% (Week 11)](https://natalieagus.github.io/50002/lab/lab5) +There are 6 mandatory labs for 50.002: +1. [Lab 0: Digital Abstraction](tbc) +2. [Lab 1: Combinational Logic with FPGA](tbc) +3. [Lab 2: Sequential Logic with FPGA](tbc) +4. Lab 3: ALU [Part 1](https://natalieagus.github.io/50002/lab/lab3-part1), [Part 2](https://natalieagus.github.io/50002/lab/lab3-part2) +5. Lab 4: Beta CPU [Part 1](https://natalieagus.github.io/50002/lab/lab4-part1), [Part 2](https://natalieagus.github.io/50002/lab/lab4-part2) +6. [Lab 5: Assembly](https://natalieagus.github.io/50002/lab/lab5) -All lab sessions are conducted **in person**. Please check myPortal to obtain your lab schedule. \ No newline at end of file +Consult your course handout for exact due dates and assessment weightage. \ No newline at end of file diff --git a/docs/Software/i_betacpudiagnostics.md b/docs/Software/i_betacpudiagnostics.md index 0ef04df..f2608c7 100644 --- a/docs/Software/i_betacpudiagnostics.md +++ b/docs/Software/i_betacpudiagnostics.md @@ -20,26 +20,23 @@ Singapore University of Technology and Design # Beta CPU Diagnostics {: .no_toc} -## Detailed Learning Objectives - - -1. **Understand Interrupt Handling in Beta CPU** - - Learn about the role and types of interrupts in the Beta CPU, including synchronous (software-driven) and asynchronous (hardware-driven) interrupts. - - Examine how interrupts are sampled and processed within the CPU's control system to ensure timely and correct response to external and internal events. - -2. **Diagnose Faults in the CPU Datapath** - - Develop skills in identifying and diagnosing faults within the Beta CPU's datapath using diagnostic software tools. - - Understand how to use simple test programs to isolate and identify specific faulty components within the CPU. - -3. **Implement Fixes for Faulty Datapaths** - - Explore strategies for making code adjustments and changes to bypass or correct faulty components within the Beta CPU's architecture. - - Gain practical experience in altering CPU behavior through modifications in the control logic to handle specific types of errors or malfunctions. - -4. **Enhance Knowledge of Beta CPU's Operational Details** - - Deepen understanding of how the Beta CPU processes and executes instructions by studying its control signals and datapath activity during normal operation and under fault conditions. - - Learn how different parts of the CPU interact during the execution of various types of instructions, focusing on the implications of these interactions for fault diagnosis and correction. - -These objectives aim to equip students with the ability to not only understand the inner workings of the Beta CPU but also to effectively address and resolve issues that may arise during its operation, especially those related to the CPU's datapath and control mechanisms. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Interrupt Handling in Beta CPU** +> - Learn about the role and types of interrupts in the Beta CPU, including synchronous (software-driven) and asynchronous (hardware-driven) interrupts. +> - Examine how interrupts are sampled and processed within the CPU's control system to ensure timely and correct response to external and internal events. +> 2. **Diagnose Faults in the CPU Datapath** +> - Develop skills in identifying and diagnosing faults within the Beta CPU's datapath using diagnostic software tools. +> - Understand how to use simple test programs to isolate and identify specific faulty components within the CPU. +> 3. **Implement Fixes for Faulty Datapaths** +> - Explore strategies for making code adjustments and changes to bypass or correct faulty components within the Beta CPU's architecture. +> - Gain practical experience in altering CPU behavior through modifications in the control logic to handle specific types of errors or malfunctions. +> 4. **Enhance Knowledge of Beta CPU's Operational Details** +> - Deepen understanding of how the Beta CPU processes and executes instructions by studying its control signals and datapath activity during normal operation and under fault conditions. +> - Learn how different parts of the CPU interact during the execution of various types of instructions, focusing on the implications of these interactions for fault diagnosis and correction. +> +> These objectives aim to equip students with the ability to not only understand the inner workings of the Beta CPU but also to effectively address and resolve issues that may arise during its operation, especially those related to the CPU's datapath and control mechanisms. In this chapter, we'll focus on understanding and fixing problems in the Beta CPU, specifically looking at its datapath. We'll learn how to find out which datapath might be faulty using simple testing software to spot these issues, and figure out what code changes can help when parts of the system aren't working correctly. Our goal is about getting to know the Beta CPU datapath better and being able to fix it whenever possible. We will also learn how to handle **interrupts** in Beta datapath. diff --git a/docs/Software/j_assemblersandcompilers.md b/docs/Software/j_assemblersandcompilers.md index 88ef1db..c33b351 100644 --- a/docs/Software/j_assemblersandcompilers.md +++ b/docs/Software/j_assemblersandcompilers.md @@ -21,35 +21,29 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/Hhq3RhZcngQ) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Learning Objectives - - -1. **Understand the Concept of Abstraction in Software Engineering** - - Learn the definition and importance of abstraction in software engineering and computer science. - - Understand how abstraction helps in managing complexity by hiding unnecessary details and allowing focus on higher-level problems. - -2. **Explore Software Tools for Abstraction** - - Examine different tools and software that provide layers of abstraction in computing, including assemblers, compilers, and interpreters. - - Understand the role of operating systems and applications in abstracting resource management, security details, and other underlying complexities. - -3. **Learn About Language Abstraction Levels** - - Study the progression from machine language to high-level programming languages through assembly language, and how each level abstracts the complexity of the underlying hardware. - - Discover how language constructs like subroutines, modules, and polymorphism further abstract programming tasks. - -4. **Understand Assemblers and Their Role in Programming** - - Define what an assembler is and how it functions as a primitive compiler to translate assembly language into machine language. - - Learn about UASM and its role in providing a symbolic representation for the Beta assembly language. - - -5. **Differentiate Between Interpreters and Compilers** - - Compare and contrast interpreters and compilers in terms of how they execute high-level languages. - - Understand the trade-offs between these tools in terms of execution speed, error detection, and ease of debugging. - -6. **Translate High-Level Constructs to Machine Language** - - Practice translating high-level language constructs, such as variable declarations, arrays, conditionals, and loops, into Beta machine language. - - Explore the strategies for optimizing the translation process to reduce instruction count and memory operations. - -These objectives aim to equip students with a deep understanding of how software abstraction layers work to simplify programming and enhance the usability of computing systems. Students will gain practical skills in using assemblers and understanding the transformation of high-level constructs into executable machine code. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand the Concept of Abstraction in Software Engineering** +> - Learn the definition and importance of abstraction in software engineering and computer science. +> - Understand how abstraction helps in managing complexity by hiding unnecessary details and allowing focus on higher-level problems. +> 2. **Explore Software Tools for Abstraction** +> - Examine different tools and software that provide layers of abstraction in computing, including assemblers, compilers, and interpreters. +> - Understand the role of operating systems and applications in abstracting resource management, security details, and other underlying complexities. +> 3. **Learn About Language Abstraction Levels** +> - Study the progression from machine language to high-level programming languages through assembly language, and how each level abstracts the complexity of the underlying hardware. +> - Discover how language constructs like subroutines, modules, and polymorphism further abstract programming tasks. +> 4. **Understand Assemblers and Their Role in Programming** +> - Define what an assembler is and how it functions as a primitive compiler to translate assembly language into machine language. +> - Learn about UASM and its role in providing a symbolic representation for the Beta assembly language. +> 5. **Differentiate Between Interpreters and Compilers** +> - Compare and contrast interpreters and compilers in terms of how they execute high-level languages. +> - Understand the trade-offs between these tools in terms of execution speed, error detection, and ease of debugging. +> 6. **Translate High-Level Constructs to Machine Language** +> - Practice translating high-level language constructs, such as variable declarations, arrays, conditionals, and loops, into Beta machine language. +> - Explore the strategies for optimizing the translation process to reduce instruction count and memory operations. +> +> These objectives aim to equip students with a deep understanding of how software abstraction layers work to simplify programming and enhance the usability of computing systems. Students will gain practical skills in using assemblers and understanding the transformation of high-level constructs into executable machine code. ## [Overview](https://www.youtube.com/watch?v=Hhq3RhZcngQ&t=49s) The goal of this chapter is to help us understand how to improve the programmability of the $$\beta$$ (or any ISA in general). The $$\beta$$ machine language is encoded into 32-bit instructions each. diff --git a/docs/Software/k_stackandprocedures.md b/docs/Software/k_stackandprocedures.md index f541028..2afba6e 100644 --- a/docs/Software/k_stackandprocedures.md +++ b/docs/Software/k_stackandprocedures.md @@ -20,42 +20,35 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/u4TETujaNuk) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Learning Objectives - - -1. **Understand Function Calls and Reusability** - - Learn why functions are essential for code reusability and organization. - - Understand the basic structure and operation of functions, including passing parameters, returning values, and the call and return mechanism. - -2. **Explore the Procedure Linkage and Stack Mechanism** - - Study the procedure linkage concept to manage function calls and returns efficiently. - - Understand the role of the stack in function calls, particularly in managing local variables, parameters, and return addresses. - -3. **Learn About Stack Operations** - - Understand how to use stack operations like PUSH and POP to manage function call contexts. - - Learn the importance of the stack pointer (SP), base pointer (BP), and linkage pointer (LP) in function execution. - -4. **Procedure Linkage Convention** - - Explore the detailed procedure linkage convention, which dictates how functions should manage calling and returning from functions. - - Learn the sequence of operations a function caller and callee must perform to ensure the correct execution flow and state preservation. - -5. **Stack Frame Management** - - Understand how to allocate and deallocate stack frames to manage local variables and function arguments. - - Study the impact of stack frame management on function calls, including nested calls and recursion. - -6. **Implement Functions with Multiple Arguments** - - Learn how to handle functions with multiple arguments using the stack. - - Understand the sequence of stacking arguments in reverse order and cleaning up the stack after function execution. - -7. **Debug and Manage Function Calls** - - Use debugging tools and techniques to inspect the call stack and understand function execution states. - - Learn about common pitfalls in function implementation, such as dangling references and stack mismanagement. - -8. **Advanced Topics in Procedure Linkage** - - Explore advanced concepts like nested functions and non-local variables, and how they affect procedure linkage. - - Discuss the limitations of C and C++ in handling complex function structures compared to languages like Python. - -These objectives aim to equip students with a comprehensive understanding of how functions are implemented at a low level, using the stack for memory management during function calls and returns. Students will also learn about the conventions and best practices in designing and debugging functions to write robust and maintainable code. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Function Calls and Reusability** +> - Learn why functions are essential for code reusability and organization. +> - Understand the basic structure and operation of functions, including passing parameters, returning values, and the call and return mechanism. +> 2. **Explore the Procedure Linkage and Stack Mechanism** +> - Study the procedure linkage concept to manage function calls and returns efficiently. +> - Understand the role of the stack in function calls, particularly in managing local variables, parameters, and return addresses. +> 3. **Learn About Stack Operations** +> - Understand how to use stack operations like PUSH and POP to manage function call contexts. +> - Learn the importance of the stack pointer (SP), base pointer (BP), and linkage pointer (LP) in function execution. +> 4. **Procedure Linkage Convention** +> - Explore the detailed procedure linkage convention, which dictates how functions should manage calling and returning from functions. +> - Learn the sequence of operations a function caller and callee must perform to ensure the correct execution flow and state preservation. +> 5. **Stack Frame Management** +> - Understand how to allocate and deallocate stack frames to manage local variables and function arguments. +> - Study the impact of stack frame management on function calls, including nested calls and recursion. +> 6. **Implement Functions with Multiple Arguments** +> - Learn how to handle functions with multiple arguments using the stack. +> - Understand the sequence of stacking arguments in reverse order and cleaning up the stack after function execution. +> 7. **Debug and Manage Function Calls** +> - Use debugging tools and techniques to inspect the call stack and understand function execution states. +> - Learn about common pitfalls in function implementation, such as dangling references and stack mismanagement. +> 8. **Advanced Topics in Procedure Linkage** +> - Explore advanced concepts like nested functions and non-local variables, and how they affect procedure linkage. +> - Discuss the limitations of C and C++ in handling complex function structures compared to languages like Python. +> +> These objectives aim to equip students with a comprehensive understanding of how functions are implemented at a low level, using the stack for memory management during function calls and returns. Students will also learn about the conventions and best practices in designing and debugging functions to write robust and maintainable code. ## [Overview](https://www.youtube.com/watch?v=u4TETujaNuk&t=0s) diff --git a/docs/Software/l_memoryhierarchy.md b/docs/Software/l_memoryhierarchy.md index d30cfae..41be397 100644 --- a/docs/Software/l_memoryhierarchy.md +++ b/docs/Software/l_memoryhierarchy.md @@ -20,51 +20,42 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/m5_u3sQ9bXo) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Learning Objectives - - -1. **Overview of Memory in Computing Systems** - - Explains the role of the REGFILE and external Memory Units in the $$\beta$$ CPU architecture. - - Discusses the limitations of a 32-bit address space, which can address up to 4GB of memory. - -2. **Memory Technologies: SRAM and DRAM** - - Introduces Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) as two primary technologies for creating memory cells. - - Describes the construction and operation of SRAM and DRAM, including the processes of reading from and writing to these memory types. - - Highlights the volatility of these memory types and the need for power to retain data. - -3. **SRAM vs DRAM Characteristics** - - Outlines the differences in cost, speed, and capacity between SRAM and DRAM. - - Provides a detailed explanation of how data is accessed and managed in both SRAM and DRAM cells. - -4. **Application of Memory Technologies** - - Discusses the practical use of SRAM and DRAM in modern computing, particularly in the context of consumer-grade PCs and CPU caches. - - Explains the role of the cache in enhancing processing speed by storing frequently accessed data closer to the CPU. - -5. **Understanding Disk Storage** - - Examines the mechanics of hard disk drives (HDDs) and their structure, including tracks, sectors, and the function of the read/write head. - - Explains the non-volatile nature of disk storage and its implications for data retrieval and storage. - -6. **The Memory Hierarchy Concept** - - Introduces the idea of a memory hierarchy to achieve an optimal balance between speed, cost, and capacity. - - Describes the roles of various storage types within this hierarchy, including registers, cache, main memory (RAM), and disk storage. - -7. **Locality of Reference** - - Discusses the principle of locality of reference, which predicts that certain memory locations are more likely to be accessed repeatedly over short periods. - - Explains how this principle supports the effective use of cache memory. - -8. **Cache Operation and Management** - - Details the operation of cache memory, including the concepts of cache hits and misses. - - Describes the processes involved when the cache does not contain requested data, including fetching data from main memory or disk. - -9. **Cache Design Types: Fully Associative and Direct Mapped** - - Compares fully associative and direct mapped cache designs. - - Discusses the advantages and challenges associated with each design, including speed, cost, flexibility, and contention issues. - -10. **Summary and Further Learning** - - Concludes with a summary of the key points discussed in the chapter. - - Points to additional resources and videos for extended learning on the topics covered. - -These notes are designed to give students a thorough understanding of the critical components and concepts related to memory technologies in computing systems, emphasizing the practical applications and the importance of memory hierarchy in achieving efficient computing operations. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Overview of Memory in Computing Systems** +> - Explains the role of the REGFILE and external Memory Units in the $$\beta$$ CPU architecture. +> - Discusses the limitations of a 32-bit address space, which can address up to 4GB of memory. +> 2. **Memory Technologies: SRAM and DRAM** +> - Introduces Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) as two primary technologies for creating memory cells. +> - Describes the construction and operation of SRAM and DRAM, including the processes of reading from and writing to these memory types. +> - Highlights the volatility of these memory types and the need for power to retain data. +> 3. **SRAM vs DRAM Characteristics** +> - Outlines the differences in cost, speed, and capacity between SRAM and DRAM. +> - Provides a detailed explanation of how data is accessed and managed in both SRAM and DRAM cells. +> 4. **Application of Memory Technologies** +> - Discusses the practical use of SRAM and DRAM in modern computing, particularly in the context of consumer-grade PCs and CPU caches. +> - Explains the role of the cache in enhancing processing speed by storing frequently accessed data closer to the CPU. +> 5. **Understanding Disk Storage** +> - Examines the mechanics of hard disk drives (HDDs) and their structure, including tracks, sectors, and the function of the read/write head. +> - Explains the non-volatile nature of disk storage and its implications for data retrieval and storage. +> 6. **The Memory Hierarchy Concept** +> - Introduces the idea of a memory hierarchy to achieve an optimal balance between speed, cost, and capacity. +> - Describes the roles of various storage types within this hierarchy, including registers, cache, main memory (RAM), and disk storage. +> 7. **Locality of Reference** +> - Discusses the principle of locality of reference, which predicts that certain memory locations are more likely to be accessed repeatedly over short periods. +> - Explains how this principle supports the effective use of cache memory. +> 8. **Cache Operation and Management** +> - Details the operation of cache memory, including the concepts of cache hits and misses. +> - Describes the processes involved when the cache does not contain requested data, including fetching data from main memory or disk. +> 9. **Cache Design Types: Fully Associative and Direct Mapped** +> - Compares fully associative and direct mapped cache designs. +> - Discusses the advantages and challenges associated with each design, including speed, cost, flexibility, and contention issues. +> 10. **Summary and Further Learning** +> - Concludes with a summary of the key points discussed in the chapter. +> - Points to additional resources and videos for extended learning on the topics covered. +> +> These notes are designed to give students a thorough understanding of the critical components and concepts related to memory technologies in computing systems, emphasizing the practical applications and the importance of memory hierarchy in achieving efficient computing operations. ## [Overview](https://www.youtube.com/watch?v=m5_u3sQ9bXo&t=0s) diff --git a/docs/Software/m_cacheissues.md b/docs/Software/m_cacheissues.md index 1d25725..400acb3 100644 --- a/docs/Software/m_cacheissues.md +++ b/docs/Software/m_cacheissues.md @@ -20,37 +20,38 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/2OARjqLK4io) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Learning Objectives - -1. **Understand Cache Memory and Its Role** - - Describe the function of cache in reducing CPU access time to memory. - - Identify the types of cache (L1, L2, L3) and understand their general function without detailed architectural differences. -2. **Learn Cache Design Parameters** - - Explain the significance of cache size, block size, associativity, and read/write/replacement policies in cache design. - - Analyze how each parameter affects cache performance and cost. -3. **Differentiate Cache Types: DM and FA** - - Compare and contrast Direct Mapped (DM) and Fully Associative (FA) caches. - - Discuss the pros and cons of each type concerning performance, cost, and risk of contention. -4. **Explore Associativity in Caches** - - Define what associativity is in the context of caches and its importance in reducing contention. - - Understand N-Way Set Associative Cache as a hybrid approach between DM and FA caches. -5. **Dive into Cache Replacement Policies** - - Examine common replacement strategies like Least Recently Used (LRU), Least Recently Replaced (LRR), and Random replacement. - - Discuss the hardware overhead and application scenarios for each replacement policy. -6. **Investigate Cache Write Policies** - - Understand different write policies including Write-Through, Write-Back, and Write-Behind. - - Evaluate the trade-offs and complexities associated with each write policy. -7. **Study Cache Block Size Considerations** - - Analyze the impact of block size on cache efficiency and performance. - - Explain the trade-offs between fetching large blocks (pros) and the risk of fetching unused words (cons). -8. **Learn About Cache Helper Bits** - - Understand the function of helper bits like Valid, Dirty, and LRU bits in cache operations. - - Discuss the storage requirements and implications of each type of helper bit on cache design. -9. **Cache Performance Metrics and Benchmarking** - - Learn how to measure cache performance using HIT and MISS rates. - - Use benchmarks to determine the effectiveness of different cache configurations and replacement policies. - -These learning objectives are designed to guide students through understanding cache memory, its design considerations, and operational strategies in a computer system architecture course. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand Cache Memory and Its Role** +> - Describe the function of cache in reducing CPU access time to memory. +> - Identify the types of cache (L1, L2, L3) and understand their general function without detailed architectural differences. +> 2. **Learn Cache Design Parameters** +> - Explain the significance of cache size, block size, associativity, and read/write/replacement policies in cache design. +> - Analyze how each parameter affects cache performance and cost. +> 3. **Differentiate Cache Types: DM and FA** +> - Compare and contrast Direct Mapped (DM) and Fully Associative (FA) caches. +> - Discuss the pros and cons of each type concerning performance, cost, and risk of contention. +> 4. **Explore Associativity in Caches** +> - Define what associativity is in the context of caches and its importance in reducing contention. +> - Understand N-Way Set Associative Cache as a hybrid approach between DM and FA caches. +> 5. **Dive into Cache Replacement Policies** +> - Examine common replacement strategies like Least Recently Used (LRU), Least Recently Replaced (LRR), and Random replacement. +> - Discuss the hardware overhead and application scenarios for each replacement policy. +> 6. **Investigate Cache Write Policies** +> - Understand different write policies including Write-Through, Write-Back, and Write-Behind. +> - Evaluate the trade-offs and complexities associated with each write policy. +> 7. **Study Cache Block Size Considerations** +> - Analyze the impact of block size on cache efficiency and performance. +> - Explain the trade-offs between fetching large blocks (pros) and the risk of fetching unused words (cons). +> 8. **Learn About Cache Helper Bits** +> - Understand the function of helper bits like Valid, Dirty, and LRU bits in cache operations. +> - Discuss the storage requirements and implications of each type of helper bit on cache design. +> 9. **Cache Performance Metrics and Benchmarking** +> - Learn how to measure cache performance using HIT and MISS rates. +> - Use benchmarks to determine the effectiveness of different cache configurations and replacement policies. +> +> These learning objectives are designed to guide students through understanding cache memory, its design considerations, and operational strategies in a computer system architecture course. ## [Overview](https://www.youtube.com/watch?v=2OARjqLK4io&t=0s) diff --git a/docs/Software/n_virtualmemory.md b/docs/Software/n_virtualmemory.md index 83efda5..8bc2641 100644 --- a/docs/Software/n_virtualmemory.md +++ b/docs/Software/n_virtualmemory.md @@ -20,32 +20,29 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/19wS4GC6mbQ) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives -1. **Understand the Concept of Memory in Computing Systems** - - Explain the differences between a program and a process in terms of memory usage. - - Describe how executable instructions and stack allocations influence process memory structure. - -2. **Examine the Role and Functionality of Virtual Memory** - - Define virtual memory and discuss its significance in modern computing. - - Explore how virtual memory enables the illusion of a large memory space on systems with limited physical memory. - -3. **Learn About Memory Paging and Page Management** - - Understand the concept of paging as a method to manage memory efficiently. - - Describe the structure of a page and how it facilitates efficient data transfer between memory and storage. - -4. **Investigate the Process of Address Translation Using the MMU** - - Explain the role of the Memory Management Unit (MMU) in translating virtual addresses to physical addresses. - - Identify the components of the MMU and their functions in the context of address translation. - -5. **Explore the Mechanisms of Demand Paging** - - Define demand paging and discuss its role in memory management. - - Analyze the process of handling page faults and the criteria for replacing pages in memory. - -6. **Context Switching in Operating Systems** - - Discuss the concept of context switching and its importance in multitasking environments. - - Explain how the operating system manages multiple processes through context switching. - -These learning objectives aim to equip students with a comprehensive understanding of how virtual memory and related concepts function within computer systems, emphasizing their role in managing limited physical resources effectively. +{:.highlight-title} +> Detailed Learning Objectives +> +> 1. **Understand the Concept of Memory in Computing Systems** +> - Explain the differences between a program and a process in terms of memory usage. +> - Describe how executable instructions and stack allocations influence process memory structure. +> 2. **Examine the Role and Functionality of Virtual Memory** +> - Define virtual memory and discuss its significance in modern computing. +> - Explore how virtual memory enables the illusion of a large memory space on systems with limited physical memory. +> 3. **Learn About Memory Paging and Page Management** +> - Understand the concept of paging as a method to manage memory efficiently. +> - Describe the structure of a page and how it facilitates efficient data transfer between memory and storage. +> 4. **Investigate the Process of Address Translation Using the MMU** +> - Explain the role of the Memory Management Unit (MMU) in translating virtual addresses to physical addresses. +> - Identify the components of the MMU and their functions in the context of address translation. +> 5. **Explore the Mechanisms of Demand Paging** +> - Define demand paging and discuss its role in memory management. +> - Analyze the process of handling page faults and the criteria for replacing pages in memory. +> 6. **Context Switching in Operating Systems** +> - Discuss the concept of context switching and its importance in multitasking environments. +> - Explain how the operating system manages multiple processes through context switching. +> +> These learning objectives aim to equip students with a comprehensive understanding of how virtual memory and related concepts function within computer systems, emphasizing their role in managing limited physical resources effectively. ## [Overview](https://www.youtube.com/watch?v=19wS4GC6mbQ&t=0s) diff --git a/docs/Software/o_virtualmachine.md b/docs/Software/o_virtualmachine.md index f3068ce..e9294b2 100644 --- a/docs/Software/o_virtualmachine.md +++ b/docs/Software/o_virtualmachine.md @@ -20,38 +20,32 @@ Singapore University of Technology and Design {: .no_toc} [You can find the lecture video here.](https://youtu.be/4pizOgCT11k) You can also **click** on each header to bring you to the section of the video covering the subtopic. -## Detailed Learning Objectives - - -- **Understand the Concept of a Virtual Processor** - - Explain the operational model where each process perceives itself as operating on a dedicated machine. - - Discuss how this abstraction benefits multitasking and resource management. - -- **Describe the Role of the Operating System Kernel** - - Detail the OS kernel's role in process management and resource allocation. - - Highlight the kernel's responsibilities in maintaining system security and process isolation. - -- **Explain Process Context and Isolation** - - Define the components that make up a process context and their importance in the OS. - - Explain how the OS uses process context to maintain each process in isolation from others. - -- **Identify the Mechanisms Supporting Dual Mode Operation** - - Describe the functions and importance of Kernel and User modes in operating systems. - - Discuss how these modes prevent unauthorized access and ensure system stability. - -- **Detail OS Multiplexing and Context Switching Techniques** - - Explore how operating systems share hardware resources among processes. - - Describe the role of context switching and how asynchronous interrupts facilitate this process. - -- **Explore Hardware Requirements for OS Multiplexing** - - Analyze the essential hardware features that support OS multiplexing. - - Discuss the mechanisms like interrupts and dual mode operation that ensure efficient process management. - -- **Understand Synchronous and Asynchronous Interrupts** - - Differentiate between synchronous and asynchronous interrupts and their roles in system operations. - - Describe how these interrupts interact with the OS to handle program execution and error management. - -These learning objectives are designed to give a comprehensive understanding of how virtual machines function within operating systems, emphasizing the essential roles of the OS kernel and necessary hardware support. +{:.highlight-title} +> Detailed Learning Objectives +> +> - **Understand the Concept of a Virtual Processor** +> - Explain the operational model where each process perceives itself as operating on a dedicated machine. +> - Discuss how this abstraction benefits multitasking and resource management. +> - **Describe the Role of the Operating System Kernel** +> - Detail the OS kernel's role in process management and resource allocation. +> - Highlight the kernel's responsibilities in maintaining system security and process isolation. +> - **Explain Process Context and Isolation** +> - Define the components that make up a process context and their importance in the OS. +> - Explain how the OS uses process context to maintain each process in isolation from others. +> - **Identify the Mechanisms Supporting Dual Mode Operation** +> - Describe the functions and importance of Kernel and User modes in operating systems. +> - Discuss how these modes prevent unauthorized access and ensure system stability. +> - **Detail OS Multiplexing and Context Switching Techniques** +> - Explore how operating systems share hardware resources among processes. +> - Describe the role of context switching and how asynchronous interrupts facilitate this process. +> - **Explore Hardware Requirements for OS Multiplexing** +> - Analyze the essential hardware features that support OS multiplexing. +> - Discuss the mechanisms like interrupts and dual mode operation that ensure efficient process management. +> - **Understand Synchronous and Asynchronous Interrupts** +> - Differentiate between synchronous and asynchronous interrupts and their roles in system operations. +> - Describe how these interrupts interact with the OS to handle program execution and error management. +> +> These learning objectives are designed to give a comprehensive understanding of how virtual machines function within operating systems, emphasizing the essential roles of the OS kernel and necessary hardware support. ## [Overview](https://www.youtube.com/watch?v=4pizOgCT11k&t=0s) diff --git a/docs/Software/p_asyncio.md b/docs/Software/p_asyncio.md index 6439965..17b5ac8 100644 --- a/docs/Software/p_asyncio.md +++ b/docs/Software/p_asyncio.md @@ -20,38 +20,32 @@ Singapore University of Technology and Design {: .no_toc} There's no pre-recorded video for this chapter as the file that was uploaded on YouTube was corrupted (no sound). Please attend the class instead as this chapter is very short and simple anyway. It is a precursor to what you'll learn in Term 5. -## Detailed Learning Objectives - - -- **Comprehend the Role of the Operating System Kernel in Multitasking** - - Understand how the OS Kernel enables multitasking through rapid context switching. - - Explain the concept of processes running in isolated virtual machines. - -- **Identify the Functionality of I/O Devices in Relation to the CPU** - - Describe how I/O devices operate asynchronously and independently of the CPU. - - Recognize the slower operation speeds of I/O devices compared to the CPU. - -- **Understand I/O Request Handling by the Operating System** - - Learn how I/O requests are handled asynchronously by the OS Kernel. - - Explore the process of handling I/O requests through supervisor calls and interrupts. - -- **Explore the Mechanism of Supervisor Calls (SVC)** - - Explain the SVC instruction and its role in facilitating process requests for Kernel services. - - Analyze the execution flow from SVC invocation to service routine execution. - -- **Examine Asynchronous Input Handling** - - Discuss how the OS Kernel manages asynchronous inputs from various I/O devices. - - Understand the implementation and operation of an interrupt-driven system for I/O handling. - -- **Study Real-Time I/O Handling and Its Challenges** - - Explore the concept of latency and deadlines in real-time I/O request handling. - - Discuss the strategies to manage multiple interrupt requests effectively. - -- **Determine the Impact of Interrupt Load on System Performance** - - Calculate the effective interrupt load and its impact on CPU performance. - - Analyze scenarios where high interrupt loads might affect system responsiveness and process execution. - -These objectives are designed to provide a detailed understanding of how an operating system manages I/O devices and processes, emphasizing the kernel's role in multitasking and real-time system responsiveness. +{:.highlight-title} +> Detailed Learning Objectives +> +> - **Comprehend the Role of the Operating System Kernel in Multitasking** +> - Understand how the OS Kernel enables multitasking through rapid context switching. +> - Explain the concept of processes running in isolated virtual machines. +> - **Identify the Functionality of I/O Devices in Relation to the CPU** +> - Describe how I/O devices operate asynchronously and independently of the CPU. +> - Recognize the slower operation speeds of I/O devices compared to the CPU. +> - **Understand I/O Request Handling by the Operating System** +> - Learn how I/O requests are handled asynchronously by the OS Kernel. +> - Explore the process of handling I/O requests through supervisor calls and interrupts. +> - **Explore the Mechanism of Supervisor Calls (SVC)** +> - Explain the SVC instruction and its role in facilitating process requests for Kernel services. +> - Analyze the execution flow from SVC invocation to service routine execution. +> - **Examine Asynchronous Input Handling** +> - Discuss how the OS Kernel manages asynchronous inputs from various I/O devices. +> - Understand the implementation and operation of an interrupt-driven system for I/O handling. +> - **Study Real-Time I/O Handling and Its Challenges** +> - Explore the concept of latency and deadlines in real-time I/O request handling. +> - Discuss the strategies to manage multiple interrupt requests effectively. +> - **Determine the Impact of Interrupt Load on System Performance** +> - Calculate the effective interrupt load and its impact on CPU performance. +> - Analyze scenarios where high interrupt loads might affect system responsiveness and process execution. +> +> These objectives are designed to provide a detailed understanding of how an operating system manages I/O devices and processes, emphasizing the kernel's role in multitasking and real-time system responsiveness. ## Overview