From 6ddbece8ac0760fdaa7e4f1fdbae35b2cca769f6 Mon Sep 17 00:00:00 2001 From: Natalie Agus Date: Fri, 15 Mar 2024 13:41:19 +0800 Subject: [PATCH] feat: add details on lab 4 checkoff --- docs/Labs/lab4-part1.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/Labs/lab4-part1.md b/docs/Labs/lab4-part1.md index adebb8e..d27fe5b 100644 --- a/docs/Labs/lab4-part1.md +++ b/docs/Labs/lab4-part1.md @@ -32,7 +32,7 @@ git clone https://github.com/natalieagus/beta-starter.git Then, you shall **paste** the implementation of your 32-bit ALU unit created in Lab 3: ALU. Be sure to include **all** files required by your `alu.luc`. {: .important} -Since there's only 1 FPGA per group, you need to work through this lab as a 1D group during class and **obtain checkoff as a group** by the end of the Lab next week. However each person must still submit the lab questionnaire **individually**. For the checkoff next week, only group members who are present gain the marks (unless valid LOA). +Since there's only 1 FPGA per group, you need to work through this lab as a 1D group during class and **obtain checkoff as a group** by the end of the Lab next week. However each person must still submit the lab questionnaire **individually**. For the checkoff next week, only group members who are present gain the marks (unless valid LOA).> You are not required to submit your code for this lab, only to show your implementation to your TA and instructors by the end of the Lab next week. Simply head to eDimension and do the lab **questionnaire** by the stipulated due date. @@ -567,7 +567,7 @@ Finally, observe that the last 16 bits of `pcsel_out` (the next PC value) still Now we need to test it by giving it a simple starter code (well, should've tested each and every component up above, but we don't have enough time in class). {: .highlight} -Paste the following simple driver code inside `instruction_rom.luc`, under `const INSTRUCTIONS`, replacing the existing instruction. +Paste the following simple driver code inside `instruction_rom.luc`, under `const INSTRUCTIONS`, replacing the existing instruction. You will need this for your Checkoff for this lab (due lab time, Week 10). ```verilog 32h7BE3FFFB, // 0x010 BNE(R3, main, R31) @@ -626,7 +626,7 @@ Finally, when you reach the fifth instruction at address `0x10` (`BNE`), confirm ### Checkoff -As stated in the beginning of this document, you need to complete all the above and demonstrate a working Beta CPU by the end of next week's lab. You can checkoff as a group. Only group members who are present gain the marks (unless valid LOA). +As stated in the beginning of this document, you need to complete all the above tasks and demonstrate a working Beta CPU using the "better test instructions" above by the end of next week's lab. You can checkoff as a group. Only group members who are present gain the marks (unless valid LOA). {: .new-title} > Checkoff