From a57054ce86b848eb6225ff1a63cb9f0924acdd84 Mon Sep 17 00:00:00 2001 From: natalieagus Date: Tue, 19 Mar 2024 22:17:00 +0800 Subject: [PATCH] style: update lab4-part1.md --- docs/Labs/lab4-part1.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Labs/lab4-part1.md b/docs/Labs/lab4-part1.md index aed37c0..e728bef 100644 --- a/docs/Labs/lab4-part1.md +++ b/docs/Labs/lab4-part1.md @@ -32,7 +32,7 @@ git clone https://github.com/natalieagus/beta-starter.git Then, you shall **paste** the implementation of your 32-bit ALU unit created in Lab 3: ALU. Be sure to include **all** files required by your `alu.luc`. {: .important} -Since there's only 1 FPGA per group, you need to work through this lab as a 1D group during class and **obtain checkoff as a group** by the end of the Lab next week. However each person must still submit the lab questionnaire **individually**. For the checkoff next week, only group members who are present gain the marks (unless valid LOA).> +Since there's only 1 FPGA per group, you need to work through this lab as a 1D group during class and **obtain checkoff as a group** by the end of the Lab next week. However each person must still submit the lab questionnaire **individually**. For the checkoff next week, only group members who are present gain the marks (unless valid LOA). You are not required to submit your code for this lab, only to show your implementation to your TA and instructors by the end of the Lab next week. Simply head to eDimension and do the lab **questionnaire** by the stipulated due date.