diff --git a/docs/FPGA/debugging.md b/docs/FPGA/Lucid V1/debugging.md similarity index 97% rename from docs/FPGA/debugging.md rename to docs/FPGA/Lucid V1/debugging.md index 7cc5011..0d49c25 100644 --- a/docs/FPGA/debugging.md +++ b/docs/FPGA/Lucid V1/debugging.md @@ -1,9 +1,10 @@ --- layout: default -permalink: /fpga/debugging +permalink: /fpga/lucid-v1/debugging title: Debugging for the Frantic description: Getting familiar with Alchitry Lab's debug feature -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA nav_order: 6 --- diff --git a/docs/FPGA/fpga_1.md b/docs/FPGA/Lucid V1/fpga_1.md similarity index 99% rename from docs/FPGA/fpga_1.md rename to docs/FPGA/Lucid V1/fpga_1.md index f4685d5..4214f61 100644 --- a/docs/FPGA/fpga_1.md +++ b/docs/FPGA/Lucid V1/fpga_1.md @@ -3,7 +3,8 @@ layout: default permalink: /fpga/fpga_1 title: FPGA Tutorial for Babies description: Getting Started with FPGA Part 1 - Combinational Logic -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA nav_order: 1 --- diff --git a/docs/FPGA/fpga_2.md b/docs/FPGA/Lucid V1/fpga_2.md similarity index 99% rename from docs/FPGA/fpga_2.md rename to docs/FPGA/Lucid V1/fpga_2.md index 635ed43..60f701c 100644 --- a/docs/FPGA/fpga_2.md +++ b/docs/FPGA/Lucid V1/fpga_2.md @@ -3,7 +3,8 @@ layout: default permalink: /fpga/fpga_2 title: FPGA Tutorial for Toddlers description: Getting Started with FPGA Part 2 - Sequential Logic and FSM -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA nav_order: 2 --- diff --git a/docs/FPGA/fpga_3.md b/docs/FPGA/Lucid V1/fpga_3.md similarity index 99% rename from docs/FPGA/fpga_3.md rename to docs/FPGA/Lucid V1/fpga_3.md index 932e0a7..dbacfb8 100644 --- a/docs/FPGA/fpga_3.md +++ b/docs/FPGA/Lucid V1/fpga_3.md @@ -3,7 +3,8 @@ layout: default permalink: /fpga/fpga_3 title: FPGA Tutorial for Children description: Getting Started with FPGA Part 3 - Reset and I/O -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA nav_order: 3 --- diff --git a/docs/FPGA/fpga_4.md b/docs/FPGA/Lucid V1/fpga_4.md similarity index 99% rename from docs/FPGA/fpga_4.md rename to docs/FPGA/Lucid V1/fpga_4.md index 50fafcf..3818db3 100644 --- a/docs/FPGA/fpga_4.md +++ b/docs/FPGA/Lucid V1/fpga_4.md @@ -3,7 +3,9 @@ layout: default permalink: /fpga/fpga_4 title: Building the Beta with FPGA description: Getting Good with FPGA - Building Beta CPU -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA +nav_exclude: true nav_order: 4 --- diff --git a/docs/FPGA/Lucid V1/index.md b/docs/FPGA/Lucid V1/index.md new file mode 100644 index 0000000..2b77e24 --- /dev/null +++ b/docs/FPGA/Lucid V1/index.md @@ -0,0 +1,8 @@ +--- +layout: default +title: Lucid V1 +permalink: /fpga/lucid-v1/intro +has_children: true +parent: FPGA +nav_order: 1 +--- \ No newline at end of file diff --git a/docs/FPGA/programmable_machine.md b/docs/FPGA/Lucid V1/programmable_machine.md similarity index 98% rename from docs/FPGA/programmable_machine.md rename to docs/FPGA/Lucid V1/programmable_machine.md index 5f471e3..72df395 100644 --- a/docs/FPGA/programmable_machine.md +++ b/docs/FPGA/Lucid V1/programmable_machine.md @@ -3,7 +3,8 @@ layout: default permalink: /fpga/programmable_machine title: Designing a Programmable Datapath description: This document shows an example on how you can create a programmable data path for a simple game idea that might be useful for your 1D project. -parent: FPGA +parent: Lucid V1 +grand_parent: FPGA nav_order: 5 --- * TOC @@ -19,7 +20,7 @@ Singapore University of Technology and Design # Designing a Programmable Datapath {: .no_toc} -For your 1D project, you are required to build an electronic game prototype that utilizes a **16-bit ALU**. You can do this by first designing a programmable datapath and the control logic (FSM) for your game, and finally implement on your FPGA. +For your 1D project (pre 2025), you are required to build an electronic game prototype that utilizes a **16-bit ALU**. You can do this by first designing a programmable datapath and the control logic (FSM) for your game, and finally implement on your FPGA. This document shows an example on how you can create a programmable data path for a simple game idea called the **Counter Game**. [The complete code can be found in this repository if you'd like to dive straight to it](https://github.com/natalieagus/counter-game). Otherwise, read along. @@ -88,7 +89,7 @@ As stated above, if you were to use a large 7-segment display then purchase some It is recommended that you follow a generic simplified **custom** $$\beta$$-like structure (without the PC and RAM unless you want to design a generic instruction set): 1. You have a **REGFILE** system, where it stores a bunch of registers inside that's addressable. It's up to you to define how many combinational read ports and how many sequential write ports. -2. **Combinational Logic Unit:** **You must utilize a 16-bit ALU, so you have no choice on this.** Therefore this makes your datapath to be a 16-bit architecture by default. <> +2. **Combinational Logic Unit:** **You must utilize a 16-bit ALU (pre 2025), so you have no choice on this.** Therefore this makes your datapath to be a 16-bit architecture by default. <> 3. You have a **Control Unit**, which is simply an FSM that gives out different control signals at various time step. It is imperative that ALL sequential parts that requires CLK is fed with the **SAME default Alchitry CLK at 100MHz.** You can create other submodules to be plugged into your datapath to act as frequency divider (slowing down the clock cycle) but DO NOT MESS with the CLK for the REGFILE and FSM **unless you are a very experienced FPGA developer.** <> diff --git a/docs/FPGA/fpga_applesilicon.md b/docs/FPGA/Lucid V2/fpga_applesilicon.md similarity index 98% rename from docs/FPGA/fpga_applesilicon.md rename to docs/FPGA/Lucid V2/fpga_applesilicon.md index 7ee486c..d88eb8a 100644 --- a/docs/FPGA/fpga_applesilicon.md +++ b/docs/FPGA/Lucid V2/fpga_applesilicon.md @@ -3,8 +3,9 @@ layout: default permalink: /fpga/fpga_applesilicon title: Running Vivado on Apple Silicon mac description: This document gives a brief overview of how you can run Vivado on Apple Silicon mac with UTM -parent: FPGA -nav_order: 7 +parent: Lucid V2 +grand_parent: FPGA +nav_order: 10 --- * TOC {:toc} diff --git a/docs/FPGA/Lucid V2/index.md b/docs/FPGA/Lucid V2/index.md new file mode 100644 index 0000000..5302758 --- /dev/null +++ b/docs/FPGA/Lucid V2/index.md @@ -0,0 +1,8 @@ +--- +layout: default +title: Lucid V2 +permalink: /fpga/lucid-v2/intro +has_children: true +nav_order: 2 +parent: FPGA +--- \ No newline at end of file diff --git a/docs/Labs/lab1-old.md b/docs/Labs/lab1-old.md index f0e8f0c..33dc129 100644 --- a/docs/Labs/lab1-old.md +++ b/docs/Labs/lab1-old.md @@ -5,6 +5,7 @@ title: (old) Lab 1 - CMOS description: Lab 1 handout covering topics from Digital Abstraction, CMOS Technology, and Logic Synthesis parent: Labs nav_order: 101 +nav_exclude: true --- * TOC diff --git a/docs/Labs/lab2-old.md b/docs/Labs/lab2-old.md index 4a3156b..4168f1a 100644 --- a/docs/Labs/lab2-old.md +++ b/docs/Labs/lab2-old.md @@ -5,6 +5,7 @@ title: (old) Lab 2 - Adder description: Lab 2 handout covering topics from CMOS Technology and Logic Synthesis parent: Labs nav_order: 103 +nav_exclude: true --- * TOC diff --git a/docs/Labs/lab3-jsim.md b/docs/Labs/lab3-jsim.md index 587f5f3..3da2670 100644 --- a/docs/Labs/lab3-jsim.md +++ b/docs/Labs/lab3-jsim.md @@ -5,6 +5,7 @@ title: (old) Lab 3 - Arithmetic Logic Unit with JSIM description: Lab 3 handout covering topics from Logic Synthesis, and Designing an Instruction Set parent: Labs nav_order: 106 +nav_exclude: true --- * TOC diff --git a/docs/Labs/lab3-part1.md b/docs/Labs/lab3-part1.md index 60ce7cd..4efeadc 100644 --- a/docs/Labs/lab3-part1.md +++ b/docs/Labs/lab3-part1.md @@ -53,7 +53,7 @@ You are NOT allowed to use ** ## Part 1 Introduction -In this lab, we will build a 32-bit **arithmetic and logic unit (ALU)** for the Beta processor. You will need this for your 1D Project Checkoff 1, just that you will need to **modify** it to be a **16-bit ALU**. It should be a minor change for you to adapt the ALU for your 1D project (simply change in size). We will stick with 32-bit ALU in this Lab because we will need it for the next lab when we make the 32-bit Beta CPU taught in the lectures. +In this lab, we will build a 32-bit **arithmetic and logic unit (ALU)** for the Beta processor. You will need this for your 1D Project Checkoff 1 **and** Lab 4 (Building the Beta). {: .new-title} > Arithmetic Logic Unit (ALU) diff --git a/docs/Labs/lab4-jsim.md b/docs/Labs/lab4-jsim.md index 46676a7..068f790 100644 --- a/docs/Labs/lab4-jsim.md +++ b/docs/Labs/lab4-jsim.md @@ -5,6 +5,7 @@ title: (old) Lab 4 - Beta Processor with JSIM description: Lab 4 handout covering topics from Beta Datapath parent: Labs nav_order: 109 +nav_exclude: true --- * TOC diff --git a/docs/Labs/mhp.md b/docs/Labs/mhp.md index 147a645..eab3dbe 100644 --- a/docs/Labs/mhp.md +++ b/docs/Labs/mhp.md @@ -5,6 +5,7 @@ title: (old) 1D Part 1 - MHP description: MHP Handout as part of 1D project parent: Labs nav_order: 100 +nav_exclude: true --- * TOC