readme.rst

VHDL libraries

Clocking

Clocking contains some comprehensive clock-related operations like:

• Sampling asynchronous data,
• Clock-domain crossing,
• Intra-domain operations,
• Clock distribution buffers,
• Abstract PLL instantiation (one input / one output) with automatic parameter calculation.

All these blocks come with proper timing constraints applied automatically to get the intended behavior.

I/O

Io library is mostly constituted of packages defining explicit record datatypes of various IO modes (opendrain, directed, tri-stated, differential). It also features usual IO blocks like DDR, some basic serdes (10 bit), IO delays.

Hardware-dependent

Even if most models try to use inference and refrains using vendor-specific libraries, some parts are still vendor-specific. Hardware-dependant library contains:

• Access to internal built-in oscillators of FPGAs,
• Access to internal built-in reset of FPGAs,
• Access to User-defined DRs of FPGAs JTAG TAPs.

NSL tries to model common abstract components above these.

Generic utilities

Math utilities:

• General arithmetic helpers,
• Fixed-point type and operators.

Data manipulation libary:

• Bytestream manipulation byte-based generic types: byte_string (vector of bytes), byte_stream (dynamically allocated byte_string),
• Generic PRBS generation framework,
• Generic CRC calculation and checking framework,
• Endianness management and conversion functions.

Memory building blocks

Memory blocks are all in relevant library

• RAMs (One port, two ports, two ports with different aspect ratios),
• ROMs (One port, two ports, specialized to hold fixed point constants),
• FIFOs,
• LIFOs,
• Look-up tables.

Industry standard buses

Industry standard buses are usually quite flexible in their configuration. NSL abstracts the details and gives the opportunity to have generic implementation for a given protocol.

• AMBA family of protocols:
  • AXI4-MM (lite and full featured),
  • AXI4-Stream,
  • APB (version 2 to 4).
• Wishbone.

Custom On-chip communication framework

Bnoc is a set of 8-bit wide data streaming infrastructure models, with various features depending on the needs.

Serial protocol adapters

• JTAG, SWD, I2C, SPI, ChipCon debug protocol, WS2812, UART, SMI (MDIO).
• I2C chip drivers for abstract usage
  • GPIO extender transactors,
  • PLL initializers,
  • DAC drivers,
  • LED drivers.

Fast IO protocols

• MII/RMII/GMII to Fifo bridges,
• FT245 Synchronous Fifo interface transactor,
• 8b/10b,
• 10b serdeses with automatic realignment.

High level communication stacks

• USB2 Full/High-speed Device implementation,
• Ethernet/IPv4/UDP implementation.

Multimedia interfaces

DVI and HDMI transmitters, including HDMI Data Island encapsulation (audio transport and other metadata). Allows flexible and arbitrary image format generation.

SPDIF and I2S input/output, including flexible clock source, clock recovery.

User-interface infrastructure

• Led management, color abstraction, PWM LED drivers, WS2812 drivers, RGB24 and RGB8 abstractions.
• Input button debouncers.
• Rotary/linear encoder input frameworks.

Simulation helpers library

Simulation library contains either helpers for test-benches:

• feeding a fifo from a file,
• comparing fifo contents with a file,
  • driving reset and clocks in a test-bench context.