From f560a840034d95ad4d083bf5f1aa0e55026a2c35 Mon Sep 17 00:00:00 2001
From: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Date: Wed, 13 Nov 2024 10:04:29 +0100
Subject: [PATCH] [nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration

Configure SDP MSPI pins to switch their control to VPR core

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
---
 drivers/pinctrl/pinctrl_nrf.c                 | 28 +++++++++++++++++++
 .../zephyr/dt-bindings/pinctrl/nrf-pinctrl.h  | 22 +++++++++++++++
 modules/hal_nordic/nrfx/nrfe_config.h         |  2 ++
 3 files changed, 52 insertions(+)

diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c
index 1e80de8fe67..dc466dd7342 100644
--- a/drivers/pinctrl/pinctrl_nrf.c
+++ b/drivers/pinctrl/pinctrl_nrf.c
@@ -94,6 +94,15 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
 #endif
 
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || defined(CONFIG_MSPI_NRFE)
+#define NRF_PSEL_SDP_MSPI(reg, pin)                                                                \
+	((NRF_GPIO_Type *)reg)->PIN_CNF[pin] =                                                     \
+		((((NRF_GPIO_Type *)reg)->PIN_CNF[pin] & ~GPIO_PIN_CNF_CTRLSEL_Msk) |              \
+		 (NRF_GPIO_PIN_SEL_VPR << GPIO_PIN_CNF_CTRLSEL_Pos));
+#endif
+#endif
+
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
@@ -347,6 +356,25 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_CONNECT;
 			break;
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_can) */
+#if defined(CONFIG_SOC_NRF54L15_CPUAPP)
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
+		case NRF_FUN_SDP_MSPI_CS0:
+		case NRF_FUN_SDP_MSPI_CS1:
+		case NRF_FUN_SDP_MSPI_SCK:
+		case NRF_FUN_SDP_MSPI_DQ0:
+		case NRF_FUN_SDP_MSPI_DQ1:
+		case NRF_FUN_SDP_MSPI_DQ2:
+		case NRF_FUN_SDP_MSPI_DQ3:
+		case NRF_FUN_SDP_MSPI_DQ4:
+		case NRF_FUN_SDP_MSPI_DQ5:
+		case NRF_FUN_SDP_MSPI_DQ6:
+		case NRF_FUN_SDP_MSPI_DQ7:
+			NRF_PSEL_SDP_MSPI(reg, psel);
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) */
+#endif /* CONFIG_SOC_NRF54L15_CPUAPP */
 		default:
 			return -ENOTSUP;
 		}
diff --git a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
index 4611baef95c..aab00563bbe 100644
--- a/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
@@ -162,6 +162,28 @@
 #define NRF_FUN_CAN_TX 46U
 /** CAN RX */
 #define NRF_FUN_CAN_RX 47U
+/** SDP_MSPI CK */
+#define NRF_FUN_SDP_MSPI_SCK 48U
+/** SDP_MSPI DQ0 */
+#define NRF_FUN_SDP_MSPI_DQ0 49U
+/** SDP_MSPI DQ1 */
+#define NRF_FUN_SDP_MSPI_DQ1 50U
+/** SDP_MSPI DQ2 */
+#define NRF_FUN_SDP_MSPI_DQ2 51U
+/** SDP_MSPI DQ3 */
+#define NRF_FUN_SDP_MSPI_DQ3 52U
+/** SDP_MSPI DQ4 */
+#define NRF_FUN_SDP_MSPI_DQ4 53U
+/** SDP_MSPI DQ5 */
+#define NRF_FUN_SDP_MSPI_DQ5 54U
+/** SDP_MSPI DQ6 */
+#define NRF_FUN_SDP_MSPI_DQ6 55U
+/** SDP_MSPI DQ7 */
+#define NRF_FUN_SDP_MSPI_DQ7 56U
+/** SDP_MSPI CS0 */
+#define NRF_FUN_SDP_MSPI_CS0 57U
+/** SDP_MSPI CS1 */
+#define NRF_FUN_SDP_MSPI_CS1 58U
 
 /** @} */
 
diff --git a/modules/hal_nordic/nrfx/nrfe_config.h b/modules/hal_nordic/nrfx/nrfe_config.h
index c85d22a14a3..6373b3212d8 100644
--- a/modules/hal_nordic/nrfx/nrfe_config.h
+++ b/modules/hal_nordic/nrfx/nrfe_config.h
@@ -9,6 +9,8 @@
 
 #ifdef CONFIG_GPIO_NRFE
 #include <drivers/gpio/nrfe_gpio.h>
+#elif CONFIG_MSPI_NRFE
+#include <drivers/mspi/nrfe_mspi.h>
 #else
 #error "NRFE config header included, even though no SW-define IO device is enabled."
 #endif