adding language verilog #490 (#789)

* adding language verilog #490 * Update languages.yaml straighter lines look better Co-authored-by: Ossama Hjaji <[email protected]> * more v straightening and updated chip value Co-authored-by: Ossama Hjaji <[email protected]>
o2sh · Oct 3, 2022 · 3c3c1b4 · 3c3c1b4
1 parent ac5d5dd
commit 3c3c1b4
Showing 1 changed file with 28 additions and 0 deletions.
diff --git a/languages.yaml b/languages.yaml
@@ -2347,6 +2347,34 @@ Vala:
       - magenta
       - white
     chip: '#A56DE2'
+Verilog:
+  type: programming
+  ascii: |
+    {0}        _.._    _.._    _.._       
+    {0}        _.._    _.._    _.._       
+    {0}        _.._    _.._    _.._       
+    {0}     _......................._     
+    {0}    _.{1}-----             -----{0}._    
+    {0}_..._.{1} ---               --- {0}._..._
+    {0}_..._.{1}  ---             ---  {0}._..._
+    {0}    _.{1}   ---           ---   {0}._    
+    {0}    _.{1}    ---         ---    {0}._    
+    {0}_..._.{1}     ---       ---     {0}._..._
+    {0}_..._.{1}      ---     ---      {0}._..._
+    {0}    _.{1}       ---   ---       {0}._    
+    {0}    _.{1}        --- ---        {0}._    
+    {0}_..._.{1}         -----         {0}._..._
+    {0}_..._.{1}          ---          {0}._..._
+    {0}    _.{1}           -           {0}._    
+    {0}     _......................._     
+    {0}        _.._    _.._    _.._         
+    {0}        _.._    _.._    _.._         
+    {0}        _.._    _.._    _.._     
+  colors:
+    ansi:
+      - white
+      - magenta
+    chip: '#b2b7f8'
 Vhdl:
   type: programming
   ascii: |