adding language systemverilog #490 (#797)

o2sh · Oct 6, 2022 · 8f27c93 · 8f27c93
1 parent c7b032e
commit 8f27c93
Showing 1 changed file with 28 additions and 0 deletions.
diff --git a/languages.yaml b/languages.yaml
@@ -2195,6 +2195,34 @@ Swift:
       - '#FC3224'
       - '#FD2822'
     chip: '#F05138'
+SystemVerilog:
+  type: programming
+  ascii: |
+    {0}   _.._    _.._    _.._    _.._
+    {0}   _.._    _.._    _.._    _.._
+    {0}  ...............................
+    {0} .              ----             . 
+    {0} .         --------------        . 
+    {0} .       ----       ---------    . 
+    {0} .     ---                -----  . 
+    {0} .    -    #####  #     #  ----- . 
+    {0} .        #     # #     #        . 
+    {0} .        #       #     #        . 
+    {0} .         #####  #     #        . 
+    {0} .              #  #   #         . 
+    {0} .        #     #   # #          . 
+    {0} . -----   #####     #      -    . 
+    {0} .  -----                ---     . 
+    {0} .    ---------       ----       . 
+    {0} .        --------------         . 
+    {0} .             ----              . 
+    {0}  ...............................
+    {0}   _.._    _.._    _.._    _.._
+    {0}   _.._    _.._    _.._    _.._
+  colors:
+    ansi:
+      - white
+    chip: '#DAE1C2'
 Tcl:
   type: programming
   ascii: |