diff --git a/edalize/modelsim.py b/edalize/modelsim.py
index a75fbe937..eb3326dde 100644
--- a/edalize/modelsim.py
+++ b/edalize/modelsim.py
@@ -111,6 +111,17 @@ def _write_build_rtl_tcl_file(self, tcl_main):
                 if f.file_type.startswith("systemVerilogSource"):
                     args += ['-sv']
                 args += vlog_include_dirs
+            # XXX: C/CPP DPI sources can also be passed to vlog
+            # workaround until we have proper DPI support
+            # (https://github.com/olofk/fusesoc/issues/311).
+            elif f.file_type.startswith("cSource") or \
+                 f.file_type.startswith("cppSource"):
+                cmd = 'vlog'
+                if f.file_type.startswith("cppSource"):
+                    args = ['-ccflags -x c++' ]
+                args += ['-ccflags "-I'+d.replace('\\','/')+'"' for d in incdirs]
+                args += self.tool_options.get('vlog_options', [])
+            # XXX
             elif f.file_type.startswith("vhdlSource"):
                 cmd = 'vcom'
                 if f.file_type.endswith("-87"):