From bb8f79490e9d3d573284fee386ab5f55c719dd40 Mon Sep 17 00:00:00 2001 From: TG Date: Mon, 8 Mar 2021 13:37:41 +0100 Subject: [PATCH] Modelsim: Handle cSource/cppSource and header files with modelsim Source files can be compiled by passing them to `vlog`. Header files search path is also passed using the `-I` option. TODO: All incdirs (RTL and DPI) are passed to `vlog` which could be too much. This is done because DPI support in Fusesoc is not yet finalized. See https://github.com/olofk/fusesoc/issues/311 --- edalize/modelsim.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/edalize/modelsim.py b/edalize/modelsim.py index a75fbe937..eb3326dde 100644 --- a/edalize/modelsim.py +++ b/edalize/modelsim.py @@ -111,6 +111,17 @@ def _write_build_rtl_tcl_file(self, tcl_main): if f.file_type.startswith("systemVerilogSource"): args += ['-sv'] args += vlog_include_dirs + # XXX: C/CPP DPI sources can also be passed to vlog + # workaround until we have proper DPI support + # (https://github.com/olofk/fusesoc/issues/311). + elif f.file_type.startswith("cSource") or \ + f.file_type.startswith("cppSource"): + cmd = 'vlog' + if f.file_type.startswith("cppSource"): + args = ['-ccflags -x c++' ] + args += ['-ccflags "-I'+d.replace('\\','/')+'"' for d in incdirs] + args += self.tool_options.get('vlog_options', []) + # XXX elif f.file_type.startswith("vhdlSource"): cmd = 'vcom' if f.file_type.endswith("-87"):