2022 Fall | Computer Architecture Individual Homework HW1 - Simple calculator with Jupiter RISC-V simulator HW2 - Fibonacci sequence and inorder traversal with Jupiter RISC-V simulator HW3 - RISC-V Single-cycle CPU Implemented with Verilog Individual Lab Lab1 - RISC-V Pipelined CPU Implemented with Verilog Lab2 - RISC-V Pipelined CPU with 2-bit Branch Predictor