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Builtin optimisation enhancement #22

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7 of 8 tasks
MaryBennett opened this issue Feb 20, 2023 · 2 comments
Open
7 of 8 tasks

Builtin optimisation enhancement #22

MaryBennett opened this issue Feb 20, 2023 · 2 comments
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enhancement New feature or request

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@MaryBennett
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MaryBennett commented Feb 20, 2023 •
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The CORE-V builtins can be enhanced by expanding the rtl for each instruction. This would allow gcc to pattern match to these builtins.
More testing with a simulator would be required.

Added, untested with simulator:

  • XCVmac
  • XCValu
  • XCVelw
  • XCVbi
  • XCVmem
  • XCVbitmanip
  • XCVsimd
  • XCVhwlp
@NandniJamnadas NandniJamnadas added the enhancement New feature or request label May 5, 2023
@MaryBennett
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This is required for upstreaming

@yulong18
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I and @zhixiao-zhang will focuse on the implementation of XCVsimd.

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@MaryBennett @yulong18 @NandniJamnadas