Check riscv-arch-test test against our coverpoints

[jordancarlin]

I began this process and with a rough script get about little over 50% coverage for most of our covergroups. Many of the coverpoints that it misses are arbitrary though (like max minus 2). Ideally we would go through and modify this to only check the coverpoints that really matter. The basic script is included below as a starting point:

#!/usr/bin/env python3

import os


reports = [["f",["arch64f", "arch64f_fma", "arch64f_divsqrt"]],
          ["d",["arch64d", "arch64d_fma", "arch64d_divsqrt"]],
          ["zfh", ["arch64zfh", "arch64zfh_fma", "arch64zfh_divsqrt"]],
          ["zfa", ["arch64zfaf", "arch64zfad"]],
          ["i", ["arch64i"]], 
          ["priv", ["arch64priv"]],
          ["zca", ["arch64c"]],
          ["m", ["arch64m"]],
          ["zcb", ["arch64zcb"]], 
          # ["zifencei", ["arch64zifencei"]],
          ["zicond", ["arch64zicond"]],
          ["zaamo", ["arch64a_amo"]],
          ["zbkb", ["arch64zbkb"]],
          ["zbkc", ["arch64zbkc"]],
          ["zbkx", ["arch64zbkx"]],
          ["zknd", ["arch64zknd"]],
          ["zkne", ["arch64zkne"]],
          ["zknh", ["arch64zknh"]],
          ["zba", ["arch64zba"]],
          ["zbb", ["arch64zbb"]],
          ["zbc", ["arch64zbc"]],
          ["zbs", ["arch64zbs"]]]

os.makedirs("coverage-reports", exist_ok=True)
cleanCmd = "rm -f sim/questa/fcov_ucdb/*"
reportCmd = "make -C addins/cvw-arch-verif merge"
for suite in reports:
  os.system(cleanCmd)
  mvCmd = f"mv addins/cvw-arch-verif/work coverage-reports/{suite[0]}-report"
  for test in suite[1]:
    runCmd = f"wsim --fcov rv64gc {test} &> sim/questa/logs/{suite[0]}-{test}.log"
    print(f"Running {test}")
    os.system(runCmd)
  print(f"Generating report for {suite[0]}")
  os.system(reportCmd)
  os.system(mvCmd)

[jordancarlin]

General coverage holes in riscv-arch-test that this has already discovered:

• Many riscv-arch-test instructions are not exercised with all 1s as one of the sources
• RV64W instructions are not exercised with 2^32-1 as one of the sources, which is probably an important corner for these instructions.
• Shifts are scarcely tested for shift amounts >= XLEN
• Floating-point tests don’t use -1 as one of the corners
• Floating-point tests don’t exercise static round modes, only dynamic modes controlled through the frm csr (such as fadd f1, f2, f3, rtz)
• Not much NaN-boxing testing for floats in larger-precision registers (F in D, Zfh in F or D)
• Zfa for Zfh doesn’t exist yet