From 73d62f3f0cd4cb3fb6975d4223bf44b35a0e1479 Mon Sep 17 00:00:00 2001 From: Evgeniy Naydanov Date: Tue, 31 Oct 2023 21:13:46 +0300 Subject: [PATCH] target: clarify usage of `coreid` By definition in `target/target.h`, `coreid` is not a unique identifier of a target -- it can be the same for targets on different TAPs. Change-Id: Ifce78da55fffe28dd8b6b06ecae7d8c4e305c0a2 Signed-off-by: Evgeniy Naydanov Reviewed-on: https://review.openocd.org/c/openocd/+/7997 Tested-by: jenkins Reviewed-by: Marek Vrbka Reviewed-by: Antonio Borneo --- src/target/armv8_cache.c | 2 +- src/target/cortex_a.c | 19 ++++++++----------- src/target/espressif/esp_xtensa_smp.c | 2 +- src/target/mips_m4k.c | 6 +++--- src/target/smp.c | 3 +++ src/target/xtensa/xtensa.c | 2 +- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c index 98f4b3f04c..66d4e00801 100644 --- a/src/target/armv8_cache.c +++ b/src/target/armv8_cache.c @@ -243,7 +243,7 @@ static int armv8_flush_all_data(struct target *target) foreach_smp_target(head, target->smp_targets) { struct target *curr = head->target; if (curr->state == TARGET_HALTED) { - LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid); + LOG_TARGET_INFO(curr, "Wait flushing data l1."); retval = _armv8_flush_all_data(curr); } } diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index ba3349d09a..7fa0c4e8b7 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -2989,29 +2989,29 @@ static int cortex_a_examine_first(struct target *target) armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGPRSR 0x%" PRIx32, dbg_osreg); if ((dbg_osreg & PRSR_POWERUP_STATUS) == 0) { - LOG_ERROR("target->coreid %" PRId32 " powered down!", target->coreid); + LOG_TARGET_ERROR(target, "powered down!"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } if (dbg_osreg & PRSR_STICKY_RESET_STATUS) - LOG_DEBUG("target->coreid %" PRId32 " was reset!", target->coreid); + LOG_TARGET_DEBUG(target, "was reset!"); /* Read DBGOSLSR and check if OSLK is implemented */ retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLSR, &dbg_osreg); if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %" PRId32 " DBGOSLSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_TARGET_DEBUG(target, "DBGOSLSR 0x%" PRIx32, dbg_osreg); /* check if OS Lock is implemented */ if ((dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM0 || (dbg_osreg & OSLSR_OSLM) == OSLSR_OSLM1) { /* check if OS Lock is set */ if (dbg_osreg & OSLSR_OSLK) { - LOG_DEBUG("target->coreid %" PRId32 " OSLock set! Trying to unlock", target->coreid); + LOG_TARGET_DEBUG(target, "OSLock set! Trying to unlock"); retval = mem_ap_write_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_OSLAR, @@ -3022,8 +3022,7 @@ static int cortex_a_examine_first(struct target *target) /* if we fail to access the register or cannot reset the OSLK bit, bail out */ if (retval != ERROR_OK || (dbg_osreg & OSLSR_OSLK) != 0) { - LOG_ERROR("target->coreid %" PRId32 " OSLock sticky, core not powered?", - target->coreid); + LOG_TARGET_ERROR(target, "OSLock sticky, core not powered?"); target->state = TARGET_UNKNOWN; /* TARGET_NO_POWER? */ return ERROR_TARGET_INIT_FAILED; } @@ -3036,13 +3035,11 @@ static int cortex_a_examine_first(struct target *target) return retval; if (dbg_idpfr1 & 0x000000f0) { - LOG_DEBUG("target->coreid %" PRId32 " has security extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has security extensions"); armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT; } if (dbg_idpfr1 & 0x0000f000) { - LOG_DEBUG("target->coreid %" PRId32 " has virtualization extensions", - target->coreid); + LOG_TARGET_DEBUG(target, "has virtualization extensions"); /* * overwrite and simplify the checks. * virtualization extensions require implementation of security extension diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c index 1d70be9e3c..bc4d8a21ad 100644 --- a/src/target/espressif/esp_xtensa_smp.c +++ b/src/target/espressif/esp_xtensa_smp.c @@ -746,7 +746,7 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump) struct target *curr; foreach_smp_target(head, target->smp_targets) { curr = head->target; - LOG_INFO("CPU%d:", curr->coreid); + LOG_TARGET_INFO(curr, ":"); int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do, target_to_xtensa(curr)); if (ret != ERROR_OK) diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 0a06bb1604..ad98089614 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -142,7 +142,7 @@ static int mips_m4k_halt_smp(struct target *target) ret = mips_m4k_halt(curr); if (ret != ERROR_OK) { - LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid); + LOG_TARGET_ERROR(curr, "halt failed."); retval = ret; } } @@ -412,8 +412,8 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han handle_breakpoints, 0); if (ret != ERROR_OK) { - LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32, - curr->coreid, address); + LOG_TARGET_ERROR(curr, "failed to resume at address: 0x%" PRIx32, + address); retval = ret; } } diff --git a/src/target/smp.c b/src/target/smp.c index effc63f521..50b19d01a0 100644 --- a/src/target/smp.c +++ b/src/target/smp.c @@ -132,6 +132,9 @@ COMMAND_HANDLER(handle_smp_gdb_command) { struct target *target = get_current_target(CMD_CTX); int retval = ERROR_OK; + + LOG_WARNING(DEPRECATED_MSG); + if (!list_empty(target->smp_targets)) { if (CMD_ARGC == 1) { int coreid = 0; diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c index e862fe165a..85dce0614c 100644 --- a/src/target/xtensa/xtensa.c +++ b/src/target/xtensa/xtensa.c @@ -822,7 +822,7 @@ int xtensa_examine(struct target *target) struct xtensa *xtensa = target_to_xtensa(target); unsigned int cmd = PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_COREWAKEUP(xtensa); - LOG_DEBUG("coreid = %d", target->coreid); + LOG_TARGET_DEBUG(target, ""); if (xtensa->core_config->core_type == XT_UNDEF) { LOG_ERROR("XTensa core not configured; is xtensa-core-openocd.cfg missing?");