coming from a c++ HLS background

[muzafferkal]

Hi,
Is there good intro to calyx tutorial which shows the scheduling capabilities of calyx?

[rachitnigam]

Hi Kal! Nice to hear from you again. Calyx currently does not do any HLS-esque scheduling since Calyx programs already explicitly mention the exact resources that they use. There is some work in CIRCT to generate statically scheduled pipelines from high-level programs and emit Calyx code. You can take a look at some of the tests to see what kind of high-level code in CIRCT can be converted into static pipelines in Calyx and run them by building the CIRCT tools. CIRCT can emit Calyx programs which can be lowered into Verilog by the compiler in this repository.

Longer term, we're working on a dataflow operator that expresses unscheduled programs to give Calyx more flexibility in scheduling programs.

[sampsyo]

Hi, @muzafferkal—good to run into you. 😃 Any chance you could elaborate on what you mean by "Python-based RTL stitching"? I'd be curious about what "stitching" entails in terms of requirements…

[muzafferkal]

Hi Adrian,
Nice to see you here.
By stitching I mean generating a top-level module from (S)Verilog leaf nodes, guided by a connectivity list. Basically a way to parse a verilog file, extract interfaces, parameters etc. and then let me connect them easily to spit out a top level with some ports propagated, some internally connected, generating errors for unconnected wires, mismatch parameters etc. If it also helps me to some simple coding it would be nice.
One example is Magma (ala chisel but in python)

[sampsyo]

Ah, neato. Calyx might be helpful if you wanted to build more complicated architectures that use blobs of functionality implementing in Verilog, but I'm not sure it's the right thing for automatically wiring up a Verilog-first codebase. Magma actually seems really useful for that… you'd have to implement the "automatic wiring" stuff yourself, but presumably they have a way to import Verilog signatures that would help?

[muzafferkal]

Actually my real goal is to establish a flow to do what you suggest. Automatically might be overstated. I'm perfectly happy with adding the connectivity but I need some help to make sure the connectivity is OK ie port directions/widths match, parameter settings are consistent etc.
I'll definitely add Calyx to the investigation to see how I can use it.
One question is, do you know if anyone has done any AXI interface work in Calyx? My first prototype will be a a simple AXI DMA to integrate with my Catapult HLS RTL.

[sampsyo]

Well cool—in that case it's not a crazy fit!

1. For wrapping Verilog in Calyx interfaces, see the way that the standard library does it. For example, here's the Calyx signature for sqrt, and here's the conformant Verilog implementation.
2. For AXI interfaces, we have an AXI wrapper generator specifically for use with Xilinx FPGAs and their accompanying XRT host driver. There are some detailed design docs available. Not sure if this fits the bill for your use case, though.