CC65 volatile (RIA memory port) handling bug

[patrick-flynn]

Hi there,

I have the following passage in one of my demos (RW0 is an alias for RIA.rw0, RIA.step0 is 1, RIA.addr0 is sensible):

            cm1m1 = RW0;
            cm10 = RW0;
            cm1p1 = RW0;

The generated assembly code is

000665r 1               ;
000665r 1               ; cm1m1 = RW0;
000665r 1               ;
000665r 1  AD E4 FF     L0033:	lda     $FFE4
000668r 1  8D rr rr     	sta     _cm1m1
00066Br 1               ;
00066Br 1               ; cm10 = RW0;
00066Br 1               ;
00066Br 1  8D rr rr     	sta     _cm10
00066Er 1               ;
00066Er 1               ; cm1p1 = RW0;
00066Er 1               ;
00066Er 1  AD E4 FF     	lda     $FFE4
000671r 1  8D rr rr     	sta     _cm1p1

which is wrong, as RW0 is not read anew for the second assignment. The variables cm1m1, etc. are normally in the zero page but I moved them out to see if it would change things. Nope.

Optimization is on by default in the RP6502 kit; when I disable it with a #pragma, the code is correct but has a pointless "LDX #$00" in front of each statement that accesses the RIA.

I'm going to look into the LLVM-MOS template but would prefer to stick with cc65 if possible. The cc65 documentation indicates that volatile is accepted but basically ignored in C source code. You can put the volatile attribute on inline assembly language but I'm not ready to do that. Appreciate any tips. --PF

[rumbledethumps]

You can try disabling specific optimizer steps using --disable-opt. Other than that, if you want to stick with cc65 then I think you need to submit this issue there.

[patrick-flynn]

Thanks!