Specify Top Module for Pure VHDL Design Exclusively During Design Ela…

…boration (#1672) * revert PR 1670 * fix CI * C++ code formating
os-fpga · Aug 14, 2024 · bd02fde · bd02fde
1 parent 12f14d8
commit bd02fde
Showing 1 changed file with 15 additions and 6 deletions.
diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp
@@ -1461,12 +1461,21 @@ std::string CompilerOpenFPGA::GhdlDesignParsingCommmands() {
       verilogcmd += "read_verilog " + includes + verilogFiles + "\n";
     }
   }
-  fileList =
-      "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit "
-      "--PREFIX=" +
-      prefixPackagePath.string() + " " + searchPath + lang + " " + fileList +
-      " -e " + ProjManager()->DesignTopModule() + " " + designLibraries + "\n";
-  fileList += verilogcmd;
+  if (!verilogFiles.empty()) {
+    fileList =
+        "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys "
+        "-fexplicit --PREFIX=" +
+        prefixPackagePath.string() + " " + searchPath + lang + " " + fileList +
+        " -e " + designLibraries + "\n";
+    fileList += verilogcmd;
+  } else {
+    fileList =
+        "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys "
+        "-fexplicit --PREFIX=" +
+        prefixPackagePath.string() + " " + searchPath + lang + " " + fileList +
+        " -e " + ProjManager()->DesignTopModule() + " " + designLibraries +
+        "\n";
+  }
 
   return fileList;
 }