From c0a4f235c3ce0f918455851467e0920a227945a8 Mon Sep 17 00:00:00 2001 From: Zaid Tahir Date: Thu, 31 Aug 2023 00:17:12 -0400 Subject: [PATCH] Final changes made for the draft PR review --- src/DesignQuery/DesignQuery.cpp | 348 ++++++++---------- .../main_sdtgen_cpp_nlohman_lib_v5 | Bin 647560 -> 647560 bytes .../main_sdtgen_cpp_nlohman_lib_v5.cpp | 51 ++- .../output_sdtgen_cpp_nlohman_lib_v5.sdt | 23 +- .../sdtgen_cpp_nlohman_lib_v5.cpp | 29 +- .../sdtgen_cpp_nlohman_lib_v5.h | 30 +- .../tcl_script_for_sdt_generation/output.sdt | 26 +- .../tcl_script_for_sdt_generation/sdtgen.tcl | 55 ++- ...tgen_cpp_nlohman_lib_v6.cpp => sdtgen.cpp} | 35 +- .../{sdtgen_cpp_nlohman_lib_v6.h => sdtgen.h} | 35 +- tests/Testcases/DesignQuery/gbox_top.tcl | 12 +- .../DesignQuery/test_parse_design_data.tcl | 10 +- third_party/gtkwave | 2 +- 13 files changed, 405 insertions(+), 251 deletions(-) rename src/DesignQuery/{sdtgen_cpp_nlohman_lib_v6.cpp => sdtgen.cpp} (99%) rename src/DesignQuery/{sdtgen_cpp_nlohman_lib_v6.h => sdtgen.h} (96%) diff --git a/src/DesignQuery/DesignQuery.cpp b/src/DesignQuery/DesignQuery.cpp index a2ffe3f31..6be28d677 100644 --- a/src/DesignQuery/DesignQuery.cpp +++ b/src/DesignQuery/DesignQuery.cpp @@ -50,13 +50,15 @@ along with this program. If not, see . #include "Utils/FileUtils.h" #include "Utils/ProcessUtils.h" #include "Utils/StringUtils.h" -#include "sdtgen_cpp_nlohman_lib_v6.h" +#include "sdtgen.h" extern FOEDAG::Session* GlobalSession; using namespace FOEDAG; using Time = std::chrono::high_resolution_clock; using ms = std::chrono::milliseconds; -using json = nlohmann::json; +using json_sdt = nlohmann::json; +using json = nlohmann::ordered_json; + int SdtCpuInstSubNode::total_instances; int SdtCpuClusterInstSubNode::total_instances; @@ -71,7 +73,7 @@ std::filesystem::path DesignQuery::GetProjDir() const { std::filesystem::path DesignQuery::GetHierInfoPath() const { std::filesystem::path dir = GetProjDir(); - std::filesystem::path hier_info = "hier_info.json"; + std::filesystem::path hier_info = "./tests/Testcases/DesignQuery/hier_info.json"; return dir / hier_info; } @@ -174,7 +176,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get cpus node from JSON file int result = get_cpus_node(data, cpus_node_obj, verbose_flag_global); @@ -185,9 +187,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -282,7 +301,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get cpus cluster node from JSON file int result = @@ -294,9 +313,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -393,7 +429,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get memory node from JSON file int result = get_memory_node(data, memory_node_obj, verbose_flag_global); @@ -404,9 +440,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -501,7 +554,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get soc node from JSON file int result = get_soc_node(data, soc_node_obj, verbose_flag_global); @@ -512,9 +565,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -606,7 +676,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get root metadata from JSON file int result = @@ -618,9 +688,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -733,7 +820,7 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { inputFile.close(); // get meta-data of all SDT nodes from JSON file - json data = json::parse(data_file); + json_sdt data = json_sdt::parse(data_file); // get rootmetadata node from JSON file int result = @@ -758,9 +845,26 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; @@ -820,33 +924,33 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { interp->registerCmd("sdt_gen_system_device_tree", sdt_gen_system_device_tree, this, 0); - // auto get_file_ids = [](void* clientData, Tcl_Interp* interp, int argc, - // const char* argv[]) -> int { - // DesignQuery* design_query = (DesignQuery*)clientData; - // Compiler* compiler = design_query->GetCompiler(); - // bool status = true; - - // if (!design_query->LoadHierInfo()) { - // status = false; - // } else { - // json& hier_info = design_query->getHierJson(); - // json file_ids_obj = hier_info["fileIDs"]; - // if (!file_ids_obj.is_object()) { - // status = false; - // } else { - // std::string ret = ""; - // for (auto it = file_ids_obj.begin(); it != file_ids_obj.end(); it++) - // { - // ret += " "; - // ret += it.key(); - // } - // compiler->TclInterp()->setResult(ret); - // } - // } - - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("get_file_ids", get_file_ids, this, 0); + auto get_file_ids = [](void* clientData, Tcl_Interp* interp, int argc, + const char* argv[]) -> int { + DesignQuery* design_query = (DesignQuery*)clientData; + Compiler* compiler = design_query->GetCompiler(); + bool status = true; + + if (!design_query->LoadHierInfo()) { + status = false; + } else { + json& hier_info = design_query->getHierJson(); + json file_ids_obj = hier_info["fileIDs"]; + if (!file_ids_obj.is_object()) { + status = false; + } else { + std::string ret = ""; + for (auto it = file_ids_obj.begin(); it != file_ids_obj.end(); it++) + { + ret += " "; + ret += it.key(); + } + compiler->TclInterp()->setResult(ret); + } + } + + return (status) ? TCL_OK : TCL_ERROR; + }; + interp->registerCmd("get_file_ids", get_file_ids, this, 0); auto get_modules = [](void* clientData, Tcl_Interp* interp, int argc, const char* argv[]) -> int { @@ -884,141 +988,5 @@ bool DesignQuery::RegisterCommands(TclInterpreter* interp, bool batchMode) { }; interp->registerCmd("get_ports", get_ports, this, 0); - // // first SDT API function implementation - // // get dict of all SDT nodes from JSON file - // auto sdt_get_sdt_nodes_dict_from_json = [](void* clientData, Tcl_Interp* - // interp, int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); - // // argv[0] is the main function name which in this case is - // "sdt_get_sdt_nodes_dict_from_json" - // std::string ret = cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_get_sdt_nodes_dict_from_json", - // sdt_get_sdt_nodes_dict_from_json, this, 0); - - // // SDT API function implementation - // // get cpus node meta-data - // auto sdt_get_cpus = [](void* clientData, Tcl_Interp* interp, int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_get_cpus", sdt_get_cpus, this, 0); - - // // SDT API function implementation - // // get cpu-clusters node meta-data - // auto sdt_get_cpus_clusters = [](void* clientData, Tcl_Interp* interp, int - // argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_get_cpus_clusters", sdt_get_cpus_clusters, this, - // 0); - - // // SDT API function implementation - // // get memory nodes meta-data - // auto sdt_get_memory_nodes = [](void* clientData, Tcl_Interp* interp, int - // argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_get_memory_nodes", sdt_get_memory_nodes, this, 0); - - // // SDT API function implementation - // // get soc user-logic meta-data (ips) - // auto sdt_get_soc = [](void* clientData, Tcl_Interp* interp, int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_get_soc", sdt_get_soc, this, 0); - - // // SDT API function implementation - // // generating/writing cpus node - // auto sdt_gen_cpu_node = [](void* clientData, Tcl_Interp* interp, int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_gen_cpu_node", sdt_gen_cpu_node, this, 0); - - // // SDT API function implementation - // // generating/writing cpus_cluster node - // auto sdt_gen_cpu_cluster_node = [](void* clientData, Tcl_Interp* interp, - // int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_gen_cpu_cluster_node", sdt_gen_cpu_cluster_node, - // this, 0); - - // // SDT API function implementation - // // generating/writing memory node - // auto sdt_gen_memory_nodes = [](void* clientData, Tcl_Interp* interp, int - // argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_gen_memory_nodes", sdt_gen_memory_nodes, this, 0); - - // // SDT API function implementation - // // generating/Wrtiting user-logic under SOC sdt node - // auto sdt_gen_soc_node = [](void* clientData, Tcl_Interp* interp, int argc, - // const char* argv[]) -> int { - // // TODO: Implement this API - // DesignQuery* design_query = (DesignQuery*)clientData; // typecasting - // pointer Compiler* compiler = design_query->GetCompiler(); bool status = - // true; std::string cmd_name = std::string(argv[0]); std::string ret = - // cmd_name + "__NOT__YET__IMPLEMENTED__"; - // compiler->TclInterp()->setResult(ret); - // return (status) ? TCL_OK : TCL_ERROR; - // }; - // interp->registerCmd("sdt_gen_soc_node", sdt_gen_soc_node, this, 0); - return true; } diff --git a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5 b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5 index dac2395f82d5be589a548f063b5456bfcf54258b..82bcecd1f7e036940799ba9518dc6ebd4a7fa12e 100755 GIT binary patch delta 57320 zcmce>qL@B4k+_aEQ;JRaL~?e}_*YpuQZzIIogg(q7rJlQJ4 zNvO6-Fp&OB-IO^%XfM>=V#rQ&I8zp@-WY4oO)1Xq)#FF&LF23Jh+KPU?t`aGG84t4 z%^G#o>8GYvVs=&8zXk?D9W%$b9I5IkcmMI9-8!?Y{~=e~rMzs_Ua(6swUGWD!2X@d z{!PQb-81i6q_t_VTr_Z5bjxK?ev$WQt=47H374cwJCnvS&67TLjBIT9ReL&Yeh<96#$h2IMQmf_)CCRxfQpTM&O?kfQkl>uT zaq|U1=$kotYnV#tm2z);BcWI3r|lP2M)p#?%hJ&Hy^-R3sY&L`T@C`qy>*(E%9M5H z9UgAUN~vZo=Q_PdN?5wL&?ED5`k#Veml?hHf?#CJJ)OJ=PxVupo~@c0oDnUUcGcCi zMCWE^JK0T zU5fP)XQ5rntRsu@Z{?iMf>nxL&M~2F%D0?U!76jb(P)*>CZ$HM1O6S5YcI6UT#$Rg zux6+-GM1qjnd?T)d5jy`EaBsut7eWlvsDn(nc92|lzB?n`9^|y=A!c#Rf0+8h)V&2 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zwpu#c!2eRt6wQimobj?%qFR}UO;op$G^Dh}Hb$nIm(+`GD8M@8X i_rNw8-#+x3p+}54_K4i8%;l!TQkL)C-ahn`;Qs@>#zCL} diff --git a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5.cpp b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5.cpp index c4e3c5c16..8d9cb49d5 100644 --- a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5.cpp +++ b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/main_sdtgen_cpp_nlohman_lib_v5.cpp @@ -1,8 +1,28 @@ +/** + + * @file main_sdtgen_cpp_nlohman_lib_v5.cpp + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team -//********************************************************************************************************************************** -// JSON to SDT cpp script written by ZaidTahir, for questions please email: -// zaid.butt.tahir@gmail.com or zaidt@bu.edu ************** -// ********************************************************************************************************************************* + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ #include @@ -111,9 +131,26 @@ int main(int, char*[]) { outfile << "/*\n \ *\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n*/\n\n"; + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n*/\n\n"; outfile << "/dts-v1/;\n\n" << "/ {\n"; diff --git a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/output_sdtgen_cpp_nlohman_lib_v5.sdt b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/output_sdtgen_cpp_nlohman_lib_v5.sdt index 663554e6c..ec6421285 100644 --- a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/output_sdtgen_cpp_nlohman_lib_v5.sdt +++ b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/output_sdtgen_cpp_nlohman_lib_v5.sdt @@ -1,8 +1,25 @@ /* * - *Copyright (c) 2023 Rapid Silicon - *SPDX-License-Identifier: rs-eula - *JSON to SDT cpp script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team + + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ /dts-v1/; diff --git a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.cpp b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.cpp index 1cbbbb37b..7cd6bb6a1 100644 --- a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.cpp +++ b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.cpp @@ -1,8 +1,29 @@ +/** + + * @file sdtgen_cpp_nlohman_lib_v5.cpp + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team + + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ -//********************************************************************************************************************************** -// JSON to SDT cpp script written by ZaidTahir, for questions please email: -// zaid.butt.tahir@gmail.com or zaidt@bu.edu ************** -// ********************************************************************************************************************************* #include "sdtgen_cpp_nlohman_lib_v5.h" #include diff --git a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.h b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.h index 4eb3cacdc..68d69fbee 100644 --- a/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.h +++ b/src/DesignQuery/scripts/cpp_script_for_sdt_generation/sdtgen_cpp_nlohman_lib_v5.h @@ -1,8 +1,28 @@ - -//********************************************************************************************************************************** -// JSON to SDT cpp script written by ZaidTahir, for questions please email: -// zaid.butt.tahir@gmail.com or zaidt@bu.edu ************** -// ********************************************************************************************************************************* +/** + + * @file sdtgen_cpp_nlohman_lib_v5.h + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team + + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ #ifndef MY_CLASS_H // include guard #define MY_CLASS_H diff --git a/src/DesignQuery/scripts/tcl_script_for_sdt_generation/output.sdt b/src/DesignQuery/scripts/tcl_script_for_sdt_generation/output.sdt index beeb149bf..93f6e7062 100644 --- a/src/DesignQuery/scripts/tcl_script_for_sdt_generation/output.sdt +++ b/src/DesignQuery/scripts/tcl_script_for_sdt_generation/output.sdt @@ -1,8 +1,26 @@ /* - *Copyright (c) 2023 Rapid Silicon - *SPDX-License-Identifier: rs-eula - *JSON to SDT TCL script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu - */ + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team + + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ /dts-v1/; diff --git a/src/DesignQuery/scripts/tcl_script_for_sdt_generation/sdtgen.tcl b/src/DesignQuery/scripts/tcl_script_for_sdt_generation/sdtgen.tcl index 272fea9eb..4e9fab842 100644 --- a/src/DesignQuery/scripts/tcl_script_for_sdt_generation/sdtgen.tcl +++ b/src/DesignQuery/scripts/tcl_script_for_sdt_generation/sdtgen.tcl @@ -1,3 +1,29 @@ +# /** + +# * @file main_sdtgen_cpp_nlohman_lib_v5.cpp +# * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) +# * @date 2023-08-30 +# * @copyright Copyright 2021 The Foedag team + +# * GPL License + +# * Copyright (c) 2021 The Open-Source FPGA Foundation + +# * This program is free software: you can redistribute it and/or modify +# * it under the terms of the GNU General Public License as published by +# * the Free Software Foundation, either version 3 of the License, or +# * (at your option) any later version. + +# * This program is distributed in the hope that it will be useful, +# * but WITHOUT ANY WARRANTY; without even the implied warranty of +# * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# * GNU General Public License for more details. + +# * You should have received a copy of the GNU General Public License +# * along with this program. If not, see . + +# */ + #!/usr/bin/tclsh package require json package require Tcl 8.5 @@ -9,10 +35,6 @@ if {$::tcl_version < 8.5} { package require dict } -########################################################################################################################################## -########## JSON to SDT TCL script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu ############ -########################################################################################################################################## - # Use this command to run this script: # "tclsh sdtgen_v6.tcl -o output_v6.sdt -f" # All functionality moved to procs in tcl script version5 @@ -416,10 +438,27 @@ proc get_board_info {} { proc gen_copyright_header {} { set copyrightString "/*\n \ - *Copyright (c) 2023 Rapid Silicon\n \ - *SPDX-License-Identifier: rs-eula\n \ - *JSON to SDT TCL script written by ZaidTahir, for questions please email: zaid.butt.tahir@gmail.com or zaidt@bu.edu\n \ - */\n\n" + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt)\n \ + * @date 2023-08-30\n \ + * @copyright Copyright 2021 The Foedag team\n \ + \n \ + * GPL License\n \ + \n \ + * Copyright (c) 2021 The Open-Source FPGA Foundation\n \ + \n \ + * This program is free software: you can redistribute it and/or modify\n \ + * it under the terms of the GNU General Public License as published by\n \ + * the Free Software Foundation, either version 3 of the License, or\n \ + * (at your option) any later version.\n \ + \n \ + * This program is distributed in the hope that it will be useful,\n \ + * but WITHOUT ANY WARRANTY; without even the implied warranty of\n \ + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n \ + * GNU General Public License for more details.\n \ + \n \ + * You should have received a copy of the GNU General Public License\n \ + * along with this program. If not, see . \n\ + \n*/\n\n" return $copyrightString } diff --git a/src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.cpp b/src/DesignQuery/sdtgen.cpp similarity index 99% rename from src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.cpp rename to src/DesignQuery/sdtgen.cpp index ee17775d1..9ad5f982b 100644 --- a/src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.cpp +++ b/src/DesignQuery/sdtgen.cpp @@ -1,17 +1,34 @@ +/** + + * @file sdtgen.cpp + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team -//********************************************************************************************************************************** -// JSON to SDT cpp script written by ZaidTahir, for questions please email: -// zaid.butt.tahir@gmail.com or zaidt@bu.edu ************** -// ********************************************************************************************************************************* + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ #include -// #include + #include "nlohmann_json/json.hpp" -// #include "json.hpp" -// #include "json/single_include/nlohmann/json.hpp" -// #include -#include "sdtgen_cpp_nlohman_lib_v6.h" +#include "sdtgen.h" using namespace std; diff --git a/src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.h b/src/DesignQuery/sdtgen.h similarity index 96% rename from src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.h rename to src/DesignQuery/sdtgen.h index 52dd9b898..8cd915d36 100644 --- a/src/DesignQuery/sdtgen_cpp_nlohman_lib_v6.h +++ b/src/DesignQuery/sdtgen.h @@ -1,20 +1,35 @@ +/** + + * @file sdtgen.h + * @author Zaid Tahir (zaid.butt.tahir@gmail.com or zaidt@bu.edu or https://github.com/zaidtahirbutt) + * @date 2023-08-30 + * @copyright Copyright 2021 The Foedag team -//********************************************************************************************************************************** -// JSON to SDT cpp script written by ZaidTahir, for questions please email: -// zaid.butt.tahir@gmail.com or zaidt@bu.edu ************** -// ********************************************************************************************************************************* + * GPL License + + * Copyright (c) 2021 The Open-Source FPGA Foundation + + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + +*/ #ifndef MY_CLASS_H // include guard #define MY_CLASS_H #include -// #include -#include "nlohmann_json/json.hpp" -// #include "json.hpp" -// #include "json/single_include/nlohmann/json.hpp" -// #include -// using json = nlohmann::json; +#include "nlohmann_json/json.hpp" using namespace std; diff --git a/tests/Testcases/DesignQuery/gbox_top.tcl b/tests/Testcases/DesignQuery/gbox_top.tcl index 81c37aa1e..3c0ebb6bc 100644 --- a/tests/Testcases/DesignQuery/gbox_top.tcl +++ b/tests/Testcases/DesignQuery/gbox_top.tcl @@ -1,17 +1,19 @@ # puts [ test_device_modeling_tcl ] # puts [ exec date ] +# puts [ get_file_ids ] # works now after adding additional code + # use "verbose" with tcl command to display debugging information for the sdt generating cpp library "sdtgen_cpp_nlohman_lib_v6" -# puts [ sdt_gen_cpus_node verbose ] +# # puts [ sdt_gen_cpus_node verbose ] puts [ sdt_gen_cpus_node ] -# # puts [ sdt_gen_cpus_cluster_node verbose ] +# puts [ sdt_gen_cpus_cluster_node verbose ] puts [ sdt_gen_cpus_cluster_node ] -# # puts [ sdt_gen_memory_node verbose ] +# puts [ sdt_gen_memory_node verbose ] puts [ sdt_gen_memory_node ] -# # puts [ sdt_gen_soc_node verbose ] +# puts [ sdt_gen_soc_node verbose ] puts [ sdt_gen_soc_node ] -# # puts [ sdt_gen_root_metadata_node verbose ] +# # # puts [ sdt_gen_root_metadata_node verbose ] puts [ sdt_gen_root_metadata_node ] # puts [ sdt_gen_system_device_tree verbose ] puts [ sdt_gen_system_device_tree ] diff --git a/tests/Testcases/DesignQuery/test_parse_design_data.tcl b/tests/Testcases/DesignQuery/test_parse_design_data.tcl index 7a67327ce..cb5522ed6 100644 --- a/tests/Testcases/DesignQuery/test_parse_design_data.tcl +++ b/tests/Testcases/DesignQuery/test_parse_design_data.tcl @@ -25,10 +25,10 @@ set_top_module top synth # Test get_file_ids and error out if the correct file ids weren't captured from the dummy data in hier_info.json -# set ids [get_file_ids] -# if { ![string compare $ids "1 10 11 12 2 3 4 5 6 7 8 9"] } { -# puts "TEST FAILED: get_file_ids should have generated 1 10 11 12 2 3 4 5 6 7 8 9" -# exit 1 -# } +set ids [get_file_ids] +if { ![string compare $ids "1 10 11 12 2 3 4 5 6 7 8 9"] } { + puts "TEST FAILED: get_file_ids should have generated 1 10 11 12 2 3 4 5 6 7 8 9" + exit 1 +} exit 0 diff --git a/third_party/gtkwave b/third_party/gtkwave index 994b1ab2f..17b83eabf 160000 --- a/third_party/gtkwave +++ b/third_party/gtkwave @@ -1 +1 @@ -Subproject commit 994b1ab2fbd5941638f4fbd66301217ea8f984de +Subproject commit 17b83eabfb36a02dde2f5317f823294455a44f69