From 1ae8f84d86eaa4a1c0a9078ee8c58a4e3bc13545 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Wed, 31 Jul 2024 15:47:02 -0700 Subject: [PATCH 01/14] Update unit test --- .../golden/model_config.negative.ppdb.json | 68 +-- .../ModelConfig/golden/model_config.ppdb.json | 86 ++-- .../model_config_io_bitstream.detail.bit | 420 +++++++++--------- ...el_config_io_bitstream.negative.detail.bit | 252 +++++------ .../model_config_netlist.negative.ppdb.json | 230 ++++++---- .../model_config_netlist.ppdb.json | 177 ++++---- 6 files changed, 650 insertions(+), 583 deletions(-) diff --git a/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json b/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json index c69510b0e..15f1519ef 100644 --- a/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json +++ b/tests/unittest/ModelConfig/golden/model_config.negative.ppdb.json @@ -244,11 +244,11 @@ " Rule I_DDR", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_clk_out)", + " Module: O_BUFT ($obuf$top.$obuf_clk_out)", " Object: clk_out", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_SERDES_CLK (o_serdes_clk)", " Object: clk_out", @@ -259,17 +259,17 @@ " Rule O_SERDES_CLK.DDR_MODE", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_dinoutosc)", + " Module: O_BUFT ($obuf$top.$obuf_dinoutosc)", " Object: dinoutosc", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_dout00)", + " Module: O_BUFT ($obuf$top.$obuf_dout00)", " Object: dout00", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr00)", " Object: dout00", @@ -277,11 +277,11 @@ " Rule O_DDR", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_dout01)", + " Module: O_BUFT ($obuf$top.$obuf_dout01)", " Object: dout01", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr01)", " Object: dout01", @@ -289,11 +289,11 @@ " Rule O_DDR", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_dout11)", + " Module: O_BUFT ($obuf$top.$obuf_dout11)", " Object: dout11", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr11)", " Object: dout11", @@ -301,11 +301,11 @@ " Rule O_DDR", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_dout12)", + " Module: O_BUFT ($obuf$top.$obuf_dout12)", " Object: dout12", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_DDR (o_ddr12)", " Object: dout12", @@ -1539,7 +1539,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out", "linked_object" : "clk_out", "linked_objects" : { @@ -1549,7 +1549,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1600,7 +1600,7 @@ "CLOCK_PHASE" : "270", "DATA_RATE" : "SDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1613,7 +1613,7 @@ "__validation_msg__" : "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out_osc", "linked_object" : "clk_out_osc", "linked_objects" : { @@ -1665,7 +1665,7 @@ "CLOCK_PHASE" : "180", "DATA_RATE" : "DDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1679,7 +1679,7 @@ "__validation_msg__" : "Fail:internal_error" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dinoutosc", "linked_object" : "dinoutosc", "linked_objects" : { @@ -1689,7 +1689,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1713,7 +1713,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout00", "linked_object" : "dout00", "linked_objects" : { @@ -1723,7 +1723,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1769,7 +1769,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1782,7 +1782,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout01", "linked_object" : "dout01", "linked_objects" : { @@ -1792,7 +1792,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1838,7 +1838,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1851,7 +1851,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout10", "linked_object" : "dout10", "linked_objects" : { @@ -1901,7 +1901,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1914,7 +1914,7 @@ "__validation_msg__" : "Invalidated because other instance in the chain is invalid" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout11", "linked_object" : "dout11", "linked_objects" : { @@ -1924,7 +1924,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1970,7 +1970,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1983,7 +1983,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout12", "linked_object" : "dout12", "linked_objects" : { @@ -1993,7 +1993,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -2039,7 +2039,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -2052,7 +2052,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout20", "linked_object" : "dout20", "linked_objects" : { diff --git a/tests/unittest/ModelConfig/golden/model_config.ppdb.json b/tests/unittest/ModelConfig/golden/model_config.ppdb.json index 74d6bc374..d68d63a1e 100644 --- a/tests/unittest/ModelConfig/golden/model_config.ppdb.json +++ b/tests/unittest/ModelConfig/golden/model_config.ppdb.json @@ -181,11 +181,11 @@ " Property", " Rule I_BUF.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_clk_out)", + " Module: O_BUFT ($obuf$top.$obuf_clk_out)", " Object: clk_out", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_SERDES_CLK (o_serdes_clk)", " Object: clk_out", @@ -196,47 +196,47 @@ " Rule O_SERDES_CLK.DDR_MODE", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_delay_tap)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap)", " Object: delay_tap[0]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_delay_tap_1)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap_1)", " Object: delay_tap[1]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_delay_tap_2)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap_2)", " Object: delay_tap[2]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_delay_tap_3)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap_3)", " Object: delay_tap[3]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_delay_tap_4)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap_4)", " Object: delay_tap[4]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_delay_tap_5)", + " Module: O_BUFT ($obuf$top.$obuf_delay_tap_5)", " Object: delay_tap[5]", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_dout)", + " Module: O_BUFT ($obuf$top.$obuf_dout)", " Object: dout", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Match", " Module: O_DELAY (o_delay)", " Object: dout", @@ -244,17 +244,17 @@ " Rule O_DELAY", " Match", " Property", - " Module: O_BUF ($obuf$top.$obuf_dout_clk2)", + " Module: O_BUFT ($obuf$top.$obuf_dout_clk2)", " Object: dout_clk2", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", - " Module: O_BUF ($obuf$top.$obuf_dout_serdes)", + " Module: O_BUFT ($obuf$top.$obuf_dout_serdes)", " Object: dout_serdes", " Parameter", " Property", - " Rule O_BUF.IOSTANDARD", + " Rule O_BUFT.IOSTANDARD", " Mismatch", " Module: O_SERDES (o_serdes)", " Object: dout_serdes", @@ -1011,7 +1011,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out", "linked_object" : "clk_out", "linked_objects" : { @@ -1021,7 +1021,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1072,7 +1072,7 @@ "CLOCK_PHASE" : "270", "DATA_RATE" : "SDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1085,7 +1085,7 @@ "__validation_msg__" : "Pass:__check_data_rate_parameter__,__check_clock_phase_parameter__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap", "linked_object" : "delay_tap[0]", "linked_objects" : { @@ -1095,7 +1095,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1119,7 +1119,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_1", "linked_object" : "delay_tap[1]", "linked_objects" : { @@ -1129,7 +1129,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1153,7 +1153,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_2", "linked_object" : "delay_tap[2]", "linked_objects" : { @@ -1163,7 +1163,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1187,7 +1187,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_3", "linked_object" : "delay_tap[3]", "linked_objects" : { @@ -1197,7 +1197,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1221,7 +1221,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_4", "linked_object" : "delay_tap[4]", "linked_objects" : { @@ -1231,7 +1231,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1255,7 +1255,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_5", "linked_object" : "delay_tap[5]", "linked_objects" : { @@ -1265,7 +1265,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1289,7 +1289,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout", "linked_object" : "dout", "linked_objects" : { @@ -1301,7 +1301,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==LVCMOS_18_HR" + "O_BUFT" : "IOSTANDARD==LVCMOS_18_HR" } ] } @@ -1351,7 +1351,7 @@ "parameters" : { "DELAY" : "60" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1364,7 +1364,7 @@ "__validation_msg__" : "" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout_clk2", "linked_object" : "dout_clk2", "linked_objects" : { @@ -1374,7 +1374,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1398,7 +1398,7 @@ "__validation_msg__" : "Pass:__pin_is_valid__,__check_pin_resource__" }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout_serdes", "linked_object" : "dout_serdes", "linked_objects" : { @@ -1408,7 +1408,7 @@ }, "config_attributes" : [ { - "O_BUF" : "IOSTANDARD==DEFAULT" + "O_BUFT" : "IOSTANDARD==DEFAULT" } ] } @@ -1462,7 +1462,7 @@ "DATA_RATE" : "DDR", "WIDTH" : "4" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit index 7970c7547..acde36940 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.detail.bit @@ -1877,28 +1877,28 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_1 [HR_5_2_1P] MC - Addr: 0x00000CC8, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_0 [HR_5_1_0N] Attributes: - RATE - Addr: 0x00000CCC, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00000CD0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000CD1, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000CD2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00000CD3, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00000CD5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00000CD6, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00000CCC, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00000CD0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000CD1, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000CD2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00000CD3, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00000CD5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00000CD6, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00000CD8, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00000CDE, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00000CE0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00000CE1, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00000CE7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00000CE9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00000CEA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00000CEB, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00000CEC, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00000CED, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00000CEE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00000CEF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00000CF0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00000CF1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00000CF2, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00000CDE, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00000CE0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00000CE1, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00000CE7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00000CE9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00000CEA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00000CEB, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00000CEC, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00000CED, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00000CEE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00000CEF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00000CF0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00000CF1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00000CF2, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_clk2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_0 [HR_5_0_0P] Attributes: RATE - Addr: 0x00000CF6, Size: 4, Value: (0x00000003) 3 { $ibuf$top.$ibuf_din_clk2 [I_BUF] [I_BUF:IOSTANDARD==DEFAULT] } @@ -4804,28 +4804,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_3 [HR_1_7_3N] MC - Addr: 0x00002121, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_3 [HR_1_6_3P] Attributes: - RATE - Addr: 0x00002125, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - MASTER_SLAVE - Addr: 0x00002129, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - PEER_IS_ON - Addr: 0x0000212A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_CLOCK_IO - Addr: 0x0000212B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_DDR_MODE - Addr: 0x0000212C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_BYPASS - Addr: 0x0000212E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_CLK_PHASE - Addr: 0x0000212F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } + RATE - Addr: 0x00002125, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + MASTER_SLAVE - Addr: 0x00002129, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + PEER_IS_ON - Addr: 0x0000212A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_CLOCK_IO - Addr: 0x0000212B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_DDR_MODE - Addr: 0x0000212C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_BYPASS - Addr: 0x0000212E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_CLK_PHASE - Addr: 0x0000212F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } TX_DLY - Addr: 0x00002131, Size: 6, Value: (0x0000003C) 60 { o_delay [O_DELAY] [TX_DLY:60] } - RX_DDR_MODE - Addr: 0x00002137, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_BYPASS - Addr: 0x00002139, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_DLY - Addr: 0x0000213A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_DPA_MODE - Addr: 0x00002140, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_MIPI_MODE - Addr: 0x00002142, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - TX_MODE - Addr: 0x00002143, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_MODE - Addr: 0x00002144, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - RX_CLOCK_IO - Addr: 0x00002145, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - DFEN - Addr: 0x00002146, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - SR - Addr: 0x00002147, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - PE - Addr: 0x00002148, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - PUD - Addr: 0x00002149, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - DFODTEN - Addr: 0x0000214A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } - MC - Addr: 0x0000214B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUF] [O_BUF:IOSTANDARD==LVCMOS_18_HR] } + RX_DDR_MODE - Addr: 0x00002137, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_BYPASS - Addr: 0x00002139, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_DLY - Addr: 0x0000213A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_DPA_MODE - Addr: 0x00002140, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_MIPI_MODE - Addr: 0x00002142, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + TX_MODE - Addr: 0x00002143, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_MODE - Addr: 0x00002144, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + RX_CLOCK_IO - Addr: 0x00002145, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + DFEN - Addr: 0x00002146, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + SR - Addr: 0x00002147, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + PE - Addr: 0x00002148, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + PUD - Addr: 0x00002149, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + DFODTEN - Addr: 0x0000214A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } + MC - Addr: 0x0000214B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout [O_BUFT] [O_BUFT:IOSTANDARD==LVCMOS_18_HR] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_2 [HR_1_5_2N] Attributes: RATE - Addr: 0x0000214F, Size: 4, Value: (0x00000000) 0 @@ -5188,28 +5188,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_15 [HR_2_31_15N] MC - Addr: 0x000023C1, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_15 [HR_2_30_15P] Attributes: - RATE - Addr: 0x000023C5, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x000023C9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000023CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000023CB, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x000023CC, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x000023CE, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x000023CF, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x000023C5, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x000023C9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000023CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000023CB, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x000023CC, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x000023CE, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x000023CF, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x000023D1, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x000023D7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x000023D9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x000023DA, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x000023E0, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x000023E2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x000023E3, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x000023E4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000023E5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x000023E6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x000023E7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x000023E8, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x000023E9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x000023EA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x000023EB, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x000023D7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x000023D9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x000023DA, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x000023E0, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x000023E2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x000023E3, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x000023E4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000023E5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x000023E6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x000023E7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x000023E8, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x000023E9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x000023EA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x000023EB, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_5 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_14 [HR_2_29_14N] Attributes: RATE - Addr: 0x000023EF, Size: 4, Value: (0x00000000) 0 @@ -5236,28 +5236,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_14 [HR_2_29_14N] MC - Addr: 0x00002415, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_14 [HR_2_28_14P] Attributes: - RATE - Addr: 0x00002419, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x0000241D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000241E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000241F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002420, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00002422, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00002423, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00002419, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x0000241D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000241E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000241F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002420, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00002422, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00002423, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002425, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000242B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x0000242D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000242E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002434, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00002436, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00002437, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002438, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002439, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000243A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000243B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x0000243C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x0000243D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000243E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000243F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000242B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x0000242D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000242E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002434, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00002436, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00002437, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002438, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002439, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x0000243A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000243B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x0000243C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x0000243D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000243E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000243F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_4 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_13 [HR_2_27_13N] Attributes: RATE - Addr: 0x00002443, Size: 4, Value: (0x00000000) 0 @@ -5284,28 +5284,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_13 [HR_2_27_13N] MC - Addr: 0x00002469, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_13 [HR_2_26_13P] Attributes: - RATE - Addr: 0x0000246D, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00002471, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002472, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002473, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002474, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00002476, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00002477, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x0000246D, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00002471, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002472, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002473, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002474, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00002476, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00002477, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002479, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000247F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002481, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00002482, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002488, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x0000248A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x0000248B, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x0000248C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000248D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000248E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000248F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00002490, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00002491, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00002492, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00002493, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000247F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002481, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00002482, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002488, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x0000248A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x0000248B, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x0000248C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000248D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x0000248E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000248F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00002490, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00002491, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00002492, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00002493, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_3 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_12 [HR_2_25_12N] Attributes: RATE - Addr: 0x00002497, Size: 4, Value: (0x00000000) 0 @@ -5332,28 +5332,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_12 [HR_2_25_12N] MC - Addr: 0x000024BD, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_12 [HR_2_24_12P] Attributes: - RATE - Addr: 0x000024C1, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x000024C5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000024C6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000024C7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x000024C8, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x000024CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x000024CB, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x000024C1, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x000024C5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000024C6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000024C7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x000024C8, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x000024CA, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x000024CB, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x000024CD, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x000024D3, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x000024D5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x000024D6, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x000024DC, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x000024DE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x000024DF, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x000024E0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000024E1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x000024E2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x000024E3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x000024E4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x000024E5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x000024E6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x000024E7, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x000024D3, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x000024D5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x000024D6, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x000024DC, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x000024DE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x000024DF, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x000024E0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000024E1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x000024E2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x000024E3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x000024E4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x000024E5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x000024E6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x000024E7, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_2 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_11 [HR_2_23_11N] Attributes: RATE - Addr: 0x000024EB, Size: 4, Value: (0x00000000) 0 @@ -5380,28 +5380,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_11 [HR_2_23_11N] MC - Addr: 0x00002511, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] Attributes: - RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002521, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00002527, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002529, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000252A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002530, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00002532, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00002533, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002534, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002535, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00002536, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00002537, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00002538, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00002539, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000253A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000253B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00002527, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002529, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000252A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002530, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00002532, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00002533, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002534, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002535, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00002536, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00002537, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00002538, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00002539, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000253A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000253B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap_1 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_10 [HR_2_21_10N] Attributes: RATE - Addr: 0x0000253F, Size: 4, Value: (0x00000000) 0 @@ -5428,28 +5428,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_10 [HR_2_21_10N] MC - Addr: 0x00002565, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_10 [HR_2_20_10P] Attributes: - RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00002573, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00002569, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x0000256D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000256E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000256F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002570, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x00002572, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00002573, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002575, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000257B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x0000257D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000257E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002584, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00002586, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00002587, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002588, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002589, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000258A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000258B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x0000258C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x0000258D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000258E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000258F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000257B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x0000257D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000257E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002584, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00002586, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00002587, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002588, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002589, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x0000258A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000258B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x0000258C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x0000258D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000258E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000258F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_delay_tap [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_9 [HR_2_CC_19_9N] Attributes: RATE - Addr: 0x00002593, Size: 4, Value: (0x00000000) 0 @@ -5812,28 +5812,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_2 [HR_2_5_2N] MC - Addr: 0x00002805, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_2 [HR_2_4_2P] Attributes: - RATE - Addr: 0x00002809, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x0000280D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000280E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000280F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002810, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } - TX_BYPASS - Addr: 0x00002812, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00002813, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } + RATE - Addr: 0x00002809, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x0000280D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000280E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000280F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002810, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } + TX_BYPASS - Addr: 0x00002812, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00002813, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } TX_DLY - Addr: 0x00002815, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000281B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x0000281D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000281E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002824, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00002826, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00002827, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002828, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002829, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000282A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000282B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x0000282C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x0000282D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000282E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000282F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000281B, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x0000281D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000281E, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002824, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00002826, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00002827, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002828, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002829, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x0000282A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000282B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x0000282C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x0000282D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000282E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000282F, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [HR_2_3_1N] Attributes: RATE - Addr: 0x00002833, Size: 4, Value: (0x00000000) 0 @@ -5860,28 +5860,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_1 [HR_2_3_1N] MC - Addr: 0x00002859, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_1 [HR_2_2_1P] Attributes: - RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000004) 4 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [RATE:4] } - MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [PEER_IS_ON:PEER_on] } - TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [O_SERDES:DDR_MODE==DDR] } - TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [TX_BYPASS:TX_gear_on] } - TX_CLK_PHASE - Addr: 0x00002867, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x0000285D, Size: 4, Value: (0x00000004) 4 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [RATE:4] } + MASTER_SLAVE - Addr: 0x00002861, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002862, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [PEER_IS_ON:PEER_on] } + TX_CLOCK_IO - Addr: 0x00002863, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002864, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [O_SERDES:DDR_MODE==DDR] } + TX_BYPASS - Addr: 0x00002866, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes [O_SERDES] [TX_BYPASS:TX_gear_on] } + TX_CLK_PHASE - Addr: 0x00002867, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002869, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x0000286F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002871, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00002872, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002878, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x0000287A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x0000287B, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x0000287C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x0000287D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x0000287E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x0000287F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00002880, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00002881, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00002882, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00002883, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x0000286F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002871, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00002872, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002878, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x0000287A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x0000287B, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x0000287C, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x0000287D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x0000287E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x0000287F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00002880, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00002881, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00002882, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00002883, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout_serdes [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_0 [HR_2_1_0N] Attributes: RATE - Addr: 0x00002887, Size: 4, Value: (0x00000000) 0 diff --git a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit index 247b04087..459603e67 100644 --- a/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit +++ b/tests/unittest/ModelConfig/golden/model_config_io_bitstream.negative.detail.bit @@ -1805,28 +1805,28 @@ Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_2 [HR_5_5_2N] MC - Addr: 0x00000C4A, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_A_2 [HR_5_4_2P] Attributes: - RATE - Addr: 0x00000C4E, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00000C52, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00000C53, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00000C54, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00000C55, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr11 [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00000C57, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00000C58, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00000C4E, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00000C52, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00000C53, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00000C54, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00000C55, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr11 [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00000C57, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00000C58, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00000C5A, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00000C60, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00000C62, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00000C63, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00000C69, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00000C6B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00000C6C, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00000C6D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00000C6E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00000C6F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00000C70, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00000C71, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00000C72, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00000C73, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00000C74, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00000C60, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00000C62, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00000C63, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00000C69, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00000C6B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00000C6C, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00000C6D, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00000C6E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00000C6F, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00000C70, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00000C71, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00000C72, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00000C73, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00000C74, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout11 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VR.u_HV_GBOX_BK1_B_1 [HR_5_3_1N] Attributes: RATE - Addr: 0x00000C78, Size: 4, Value: (0x00000000) 0 @@ -3323,28 +3323,28 @@ Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_11 [HP_1_23_11N] MC - Addr: 0x000016AC, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_A_11 [HP_1_22_11P] Attributes: - RATE - Addr: 0x000016B0, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x000016B4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x000016B5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x000016B6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x000016B7, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr00 [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x000016B9, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x000016BA, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x000016B0, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x000016B4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x000016B5, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x000016B6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x000016B7, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr00 [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x000016B9, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x000016BA, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x000016BC, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x000016C2, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x000016C4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x000016C5, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x000016CB, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x000016CD, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x000016CE, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x000016CF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x000016D0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x000016D1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x000016D2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x000016D3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x000016D4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x000016D5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x000016D6, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x000016C2, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x000016C4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x000016C5, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x000016CB, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x000016CD, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x000016CE, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x000016CF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x000016D0, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x000016D1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x000016D2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x000016D3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x000016D4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x000016D5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x000016D6, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout00 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HP_40X2.u_HP_GBOX_BK0_B_10 [HP_1_21_10N] Attributes: RATE - Addr: 0x000016DA, Size: 4, Value: (0x00000000) 0 @@ -4324,28 +4324,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_13 [HR_1_27_13N] MC - Addr: 0x00001DD9, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_13 [HR_1_26_13P] Attributes: - RATE - Addr: 0x00001DDD, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00001DE1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001DE2, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001DE3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00001DE4, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr12 [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00001DE6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00001DE7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00001DDD, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00001DE1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001DE2, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001DE3, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00001DE4, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr12 [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00001DE6, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00001DE7, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001DE9, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00001DEF, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00001DF1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00001DF2, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00001DF8, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00001DFA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00001DFB, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00001DFC, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001DFD, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00001DFE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00001DFF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00001E00, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00001E01, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00001E02, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00001E03, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00001DEF, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00001DF1, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00001DF2, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00001DF8, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00001DFA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00001DFB, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00001DFC, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001DFD, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00001DFE, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00001DFF, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00001E00, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00001E01, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00001E02, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00001E03, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout12 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_12 [HR_1_25_12N] Attributes: RATE - Addr: 0x00001E07, Size: 4, Value: (0x00000000) 0 @@ -4420,28 +4420,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_11 [HR_1_23_11N] MC - Addr: 0x00001E81, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_A_11 [HR_1_22_11P] Attributes: - RATE - Addr: 0x00001E85, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00001E89, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00001E8A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00001E8B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00001E8C, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_ddr01 [O_DDR] [O_DDR:MODE==DDR] } - TX_BYPASS - Addr: 0x00001E8E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x00001E8F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00001E85, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00001E89, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00001E8A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00001E8B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00001E8C, Size: 2, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_ddr01 [O_DDR] [O_DDR:MODE==DDR] } + TX_BYPASS - Addr: 0x00001E8E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x00001E8F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00001E91, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00001E97, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00001E99, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00001E9A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00001EA0, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00001EA2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00001EA3, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00001EA4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00001EA5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00001EA6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00001EA7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00001EA8, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00001EA9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00001EAA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00001EAB, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00001E97, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00001E99, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00001E9A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00001EA0, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00001EA2, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00001EA3, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00001EA4, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00001EA5, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00001EA6, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00001EA7, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00001EA8, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00001EA9, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00001EAA, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00001EAB, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dout01 [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK0_B_10 [HR_1_21_10N] Attributes: RATE - Addr: 0x00001EAF, Size: 4, Value: (0x00000000) 0 @@ -5380,28 +5380,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_11 [HR_2_23_11N] MC - Addr: 0x00002511, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_11 [HR_2_22_11P] Attributes: - RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RATE - Addr: 0x00002515, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00002519, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x0000251A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x0000251B, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x0000251C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_BYPASS - Addr: 0x0000251E, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x0000251F, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } TX_DLY - Addr: 0x00002521, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00002527, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002529, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x0000252A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x00002530, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x00002532, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x00002533, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002534, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002535, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00002536, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00002537, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00002538, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00002539, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x0000253A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x0000253B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00002527, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002529, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x0000252A, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x00002530, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x00002532, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x00002533, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002534, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002535, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00002536, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00002537, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00002538, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00002539, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x0000253A, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x0000253B, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_dinoutosc [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_10 [HR_2_21_10N] Attributes: RATE - Addr: 0x0000253F, Size: 4, Value: (0x00000000) 0 @@ -5716,28 +5716,28 @@ Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_4 [HR_2_9_4N] MC - Addr: 0x0000275D, Size: 4, Value: (0x00000000) 0 Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_A_4 [HR_2_8_4P] Attributes: - RATE - Addr: 0x00002761, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MASTER_SLAVE - Addr: 0x00002765, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PEER_IS_ON - Addr: 0x00002766, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLOCK_IO - Addr: 0x00002767, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_DDR_MODE - Addr: 0x00002768, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } - TX_BYPASS - Addr: 0x0000276A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_CLK_PHASE - Addr: 0x0000276B, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } + RATE - Addr: 0x00002761, Size: 4, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MASTER_SLAVE - Addr: 0x00002765, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PEER_IS_ON - Addr: 0x00002766, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLOCK_IO - Addr: 0x00002767, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_DDR_MODE - Addr: 0x00002768, Size: 2, Value: (0x00000002) 2 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [O_SERDES_CLK:DDR_MODE==SDR] } + TX_BYPASS - Addr: 0x0000276A, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_CLK_PHASE - Addr: 0x0000276B, Size: 2, Value: (0x00000003) 3 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT], o_serdes_clk [O_SERDES_CLK] [TX_CLK_PHASE:TX_phase_270] } TX_DLY - Addr: 0x0000276D, Size: 6, Value: (0x00000000) 0 - RX_DDR_MODE - Addr: 0x00002773, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_BYPASS - Addr: 0x00002775, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DLY - Addr: 0x00002776, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_DPA_MODE - Addr: 0x0000277C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MIPI_MODE - Addr: 0x0000277E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - TX_MODE - Addr: 0x0000277F, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_MODE - Addr: 0x00002780, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - RX_CLOCK_IO - Addr: 0x00002781, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFEN - Addr: 0x00002782, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - SR - Addr: 0x00002783, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PE - Addr: 0x00002784, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - PUD - Addr: 0x00002785, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - DFODTEN - Addr: 0x00002786, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } - MC - Addr: 0x00002787, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUF] [O_BUF:IOSTANDARD==DEFAULT] } + RX_DDR_MODE - Addr: 0x00002773, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_BYPASS - Addr: 0x00002775, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DLY - Addr: 0x00002776, Size: 6, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_DPA_MODE - Addr: 0x0000277C, Size: 2, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MIPI_MODE - Addr: 0x0000277E, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + TX_MODE - Addr: 0x0000277F, Size: 1, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_MODE - Addr: 0x00002780, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + RX_CLOCK_IO - Addr: 0x00002781, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFEN - Addr: 0x00002782, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + SR - Addr: 0x00002783, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PE - Addr: 0x00002784, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + PUD - Addr: 0x00002785, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + DFODTEN - Addr: 0x00002786, Size: 1, Value: (0x00000000) 0 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } + MC - Addr: 0x00002787, Size: 4, Value: (0x00000001) 1 { $obuf$top.$obuf_clk_out [O_BUFT] [O_BUFT:IOSTANDARD==DEFAULT] } Block u_GBOX_HV_40X2_VL.u_HV_GBOX_BK1_B_3 [HR_2_7_3N] Attributes: RATE - Addr: 0x0000278B, Size: 4, Value: (0x00000000) 0 diff --git a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json index a2478dcc9..eac7dde58 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.negative.ppdb.json @@ -91,31 +91,31 @@ " Cell port \\I is connected to input port \\dinosc4", " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_clk_out", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_clk_out", " Cell port \\O is connected to output port \\clk_out", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_clk_out_osc", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_clk_out_osc", " Cell port \\O is connected to output port \\clk_out_osc", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dinoutosc", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dinoutosc", " Cell port \\O is connected to output port \\dinoutosc", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout00", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout00", " Cell port \\O is connected to output port \\dout00", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout01", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout01", " Cell port \\O is connected to output port \\dout01", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout10", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout10", " Cell port \\O is connected to output port \\dout10", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout11", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout11", " Cell port \\O is connected to output port \\dout11", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout12", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout12", " Cell port \\O is connected to output port \\dout12", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout20", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout20", " Cell port \\O is connected to output port \\dout20", " Data Width: 1", " Get important connection of cell \\BOOT_CLOCK \\boot_clock", @@ -270,24 +270,24 @@ " Trace \\I_DELAY --> \\I_SERDES", " Trace \\O_BUF --> \\O_DELAY", " Trace \\O_BUF --> \\O_DDR", - " Try \\O_BUF $obuf$top.$obuf_dout00 out connection: $obuf_dout00 -> \\o_ddr00", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Trace \\O_BUFT --> \\O_DDR", + " Try \\O_BUFT $obuf$top.$obuf_dout00 out connection: $obuf_dout00 -> \\o_ddr00", " Connected \\o_ddr00", " Data Width: 2", - " Try \\O_BUF $obuf$top.$obuf_dout01 out connection: $obuf_dout01 -> \\o_ddr01", + " Try \\O_BUFT $obuf$top.$obuf_dout01 out connection: $obuf_dout01 -> \\o_ddr01", " Connected \\o_ddr01", " Data Width: 2", - " Try \\O_BUF $obuf$top.$obuf_dout10 out connection: $obuf_dout10 -> \\o_ddr10", + " Try \\O_BUFT $obuf$top.$obuf_dout10 out connection: $obuf_dout10 -> \\o_ddr10", " Connected \\o_ddr10", " Data Width: 2", - " Try \\O_BUF $obuf$top.$obuf_dout11 out connection: $obuf_dout11 -> \\o_ddr11", + " Try \\O_BUFT $obuf$top.$obuf_dout11 out connection: $obuf_dout11 -> \\o_ddr11", " Connected \\o_ddr11", " Data Width: 2", - " Try \\O_BUF $obuf$top.$obuf_dout12 out connection: $obuf_dout12 -> \\o_ddr12", + " Try \\O_BUFT $obuf$top.$obuf_dout12 out connection: $obuf_dout12 -> \\o_ddr12", " Connected \\o_ddr12", " Data Width: 2", - " Trace \\O_BUF --> \\O_SERDES", - " Trace \\O_BUFT --> \\O_DELAY", - " Trace \\O_BUFT --> \\O_DDR", " Trace \\O_BUFT --> \\O_SERDES", " Trace \\O_BUF_DS --> \\O_DELAY", " Trace \\O_BUF_DS --> \\O_DDR", @@ -301,17 +301,17 @@ " Trace \\O_DELAY --> \\O_DDR", " Trace \\O_DELAY --> \\O_SERDES", " Trace \\O_BUF --> \\O_SERDES_CLK", - " Try \\O_BUF $obuf$top.$obuf_clk_out out connection: $obuf_clk_out -> \\o_serdes_clk", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Try \\O_BUFT $obuf$top.$obuf_clk_out out connection: $obuf_clk_out -> \\o_serdes_clk", " Connected \\o_serdes_clk", " Parameter \\CLOCK_PHASE: 270", " Parameter \\DATA_RATE: \"SDR\"", " Data Width: -2", - " Try \\O_BUF $obuf$top.$obuf_clk_out_osc out connection: $obuf_clk_out_osc -> \\o_serdes_clk_osc", + " Try \\O_BUFT $obuf$top.$obuf_clk_out_osc out connection: $obuf_clk_out_osc -> \\o_serdes_clk_osc", " Connected \\o_serdes_clk_osc", " Parameter \\CLOCK_PHASE: 180", " Parameter \\DATA_RATE: \"DDR\"", " Data Width: -2", - " Trace \\O_BUFT --> \\O_SERDES_CLK", " Trace \\O_BUF_DS --> \\O_SERDES_CLK", " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", " Trace fabric clock buffer", @@ -351,22 +351,22 @@ " Does not meet core_clk checking criteria. Not sending to fabric", " Connected to cell \\O_DDR \\o_ddr00", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\PLL \\pll00: clock port \\CLK_OUT, net \\pll00_clk1", " Connected to cell \\I_DDR \\i_ddr01", " Which is a primitive", " Does not meet core_clk checking criteria. Not sending to fabric", " Connected to cell \\O_DDR \\o_ddr01", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\PLL \\pll00: clock port \\CLK_OUT_DIV2, net \\pll00_clk2", - " Connected to cell \\DFFRE $abc$277$auto$blifparse.cc:377:parse_blif$278", + " Connected to cell \\DFFRE $abc$277$auto_278", " Which is not a IO primitive. Send to fabric", " Module \\PLL \\pll00: clock port \\CLK_OUT_DIV3, net \\pll00_clk3", - " Connected to cell \\DFFRE $abc$270$auto$blifparse.cc:377:parse_blif$271", + " Connected to cell \\DFFRE $abc$270$auto_271", " Which is not a IO primitive. Send to fabric", " Module \\PLL \\pll00: clock port \\CLK_OUT_DIV4, net \\pll00_clk4", - " Connected to cell \\DFFRE $abc$263$auto$blifparse.cc:377:parse_blif$264", + " Connected to cell \\DFFRE $abc$263$auto_264", " Which is not a IO primitive. Send to fabric", " Module \\CLK_BUF \\clk_buf10: clock port \\O, net \\clkbuf10", " Connected to cell \\I_DDR \\i_ddr10", @@ -380,9 +380,9 @@ " Does not meet core_clk checking criteria. Not sending to fabric", " Connected to cell \\O_DDR \\o_ddr10", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\CLK_BUF $clkbuf$top.$ibuf_clk20: clock port \\O, net $clk_buf_$ibuf_clk20", - " Connected to cell \\DFFRE $abc$284$auto$blifparse.cc:377:parse_blif$285", + " Connected to cell \\DFFRE $abc$284$auto_285", " Which is not a IO primitive. Send to fabric", " Module \\BOOT_CLOCK \\boot_clock: clock port \\O, net \\osc", " Connected to cell \\O_SERDES_CLK \\o_serdes_clk_osc", @@ -433,7 +433,7 @@ " Does not meet core_clk checking criteria. Not sending to fabric", " Connected to cell \\O_DDR \\o_ddr3x", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\CLK_BUF \\clk_buf40: clock port \\O, net \\clkbuf40", " Connected to cell \\O_SERDES_CLK \\o_serdes_clk", " Which is a primitive", @@ -455,15 +455,15 @@ " IN | dinosc2 * I_BUF |-> I_DDR * |", " IN | dinosc3 * I_BUF |-> I_DDR * |", " IN | dinosc4 * I_BUF |-> I_DDR * |", - " OUT | * O_SERDES_CLK |-> O_BUF * clk_out |", - " OUT | * O_SERDES_CLK |-> O_BUF * clk_out_osc |", - " OUT | * O_BUF * dinoutosc |", - " OUT | * O_DDR |-> O_BUF * dout00 |", - " OUT | * O_DDR |-> O_BUF * dout01 |", - " OUT | * O_DDR |-> O_BUF * dout10 |", - " OUT | * O_DDR |-> O_BUF * dout11 |", - " OUT | * O_DDR |-> O_BUF * dout12 |", - " OUT | * O_BUF * dout20 |", + " OUT | * O_SERDES_CLK |-> O_BUFT * clk_out |", + " OUT | * O_SERDES_CLK |-> O_BUFT * clk_out_osc |", + " OUT | * O_BUFT * dinoutosc |", + " OUT | * O_DDR |-> O_BUFT * dout00 |", + " OUT | * O_DDR |-> O_BUFT * dout01 |", + " OUT | * O_DDR |-> O_BUFT * dout10 |", + " OUT | * O_DDR |-> O_BUFT * dout11 |", + " OUT | * O_DDR |-> O_BUFT * dout12 |", + " OUT | * O_BUFT * dout20 |", " IN | BOOT_CLOCK#0 * BOOT_CLOCK |-> PLL * |", " IN | * |-> PLL * |", " IN | * |-> PLL * |", @@ -508,15 +508,15 @@ " Determine data signals", " Pin object=clk00, location: HP_1_CC_18_9P", " Data signal from object clk00", - " Failure reason: Object clk00 is primitive \\PLL but data signal is not defined", + " Fail reason: Object clk00 is primitive \\PLL but data signal is not defined", " Pin object=clk10, location: HR_1_CC_18_9P", " Data signal from object clk10", - " Module=I_BUF Linked-object=clk10 Port=O Net=$flatten$auto$rs_design_edit.cc:1153:execute$805.$ibuf_clk10 - Not found", - " Failure reason: Clock data from object clk10 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk10 Port=O Net=$flatten$auto_814.$ibuf_clk10 - Not found", + " Fail reason: Clock data from object clk10 port O is not routed to fabric", " Pin object=clk20, location: HP_1_CC_38_19P", " Data signal from object clk20", - " Module=I_BUF Linked-object=clk20 Port=O Net=$flatten$auto$rs_design_edit.cc:1153:execute$805.$ibuf_clk20 - Not found", - " Failure reason: Clock data from object clk20 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk20 Port=O Net=$flatten$auto_814.$ibuf_clk20 - Not found", + " Fail reason: Clock data from object clk20 port O is not routed to fabric", " Pin object=din00, location: HP_1_20_10P", " Data signal from object din00", " Module=I_DDR Linked-object=din00 Port=Q Net=din_iddr00[0] - Found", @@ -557,21 +557,21 @@ " Module=I_DDR Linked-object=dinosc4 Port=Q Net=din_iddr_osc4[1] - Found", " Pin object=clk_out, location: HR_2_8_4P", " Data signal from object clk_out", - " Failure reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", + " Fail reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=clk_out_osc, location: HR_2_9_4N", " Data signal from object clk_out_osc", - " Failure reason: Object clk_out_osc is primitive \\O_SERDES_CLK but data signal is not defined", + " Fail reason: Object clk_out_osc is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=dinoutosc, location: HR_2_22_11P", " Data signal from object dinoutosc", - " Module=O_BUF Linked-object=dinoutosc Port=I Net=$obuf_dinoutosc - Found", + " Module=O_BUFT Linked-object=dinoutosc Port=I Net=$obuf_dinoutosc - Found", " Pin object=dout00, location: HP_1_22_11P", " Data signal from object dout00", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$793 - Found", - " Module=O_DDR Linked-object=dout00 Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$794 - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$auto_802 - Found", + " Module=O_DDR Linked-object=dout00 Port=D Net=$auto_803 - Found", " Pin object=dout01, location: HR_1_22_11P", " Data signal from object dout01", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$795 - Found", - " Module=O_DDR Linked-object=dout01 Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$796 - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$auto_804 - Found", + " Module=O_DDR Linked-object=dout01 Port=D Net=$auto_805 - Found", " Pin object=dout10, location: ", " Pin location is not assigned", " Pin object=dout11, location: HR_5_4_2P", @@ -586,14 +586,14 @@ " Pin location is not assigned", " Pin object=clk30, location: HR_1_CC_38_19P", " Data signal from object clk30", - " Failure reason: Object clk30 is primitive \\PLL but data signal is not defined", + " Fail reason: Object clk30 is primitive \\PLL but data signal is not defined", " Pin object=clk31, location: HR_3_CC_38_19P", " Data signal from object clk31", - " Failure reason: Object clk31 is primitive \\PLL but data signal is not defined", + " Fail reason: Object clk31 is primitive \\PLL but data signal is not defined", " Pin object=clk40, location: HR_2_CC_38_19P", " Data signal from object clk40", - " Module=I_BUF Linked-object=clk40 Port=O Net=$auto$rs_design_edit.cc:1153:execute$805.ibuf40 - Not found", - " Failure reason: Clock data from object clk40 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk40 Port=O Net=$auto_814.ibuf40 - Not found", + " Fail reason: Clock data from object clk40 port O is not routed to fabric", " Pin object=din30_n, location: HR_2_1_0N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=din30_p, location: HR_2_0_0P", @@ -615,98 +615,144 @@ " Determine internal control signals", " Module=I_BUF LinkedObject=clk00 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=clk00 Location=HP_1_CC_18_9P Port=LOCK Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object clk00 wrapped-instance port LOCK", + " Skip reason: User design does not utilize linked-object clk00 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk00 Location=HP_1_CC_18_9P Port=PLL_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=clk10 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=clk20 Location=HP_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=din00 Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din00 Location=HP_1_20_10P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din00 Location=HP_1_20_10P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=din01 Location=HR_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din01 Location=HR_1_20_10P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din01 Location=HR_1_20_10P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=din10 Location= Port=EN Signal=in:f2g_in_en_{A|B}", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_DDR LinkedObject=din10 Location= Port=E Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_DDR LinkedObject=din10 Location= Port=R Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF LinkedObject=din11 Location=HR_5_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din11 Location=HR_5_2_1P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din11 Location=HR_5_2_1P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=din12 Location=HR_1_24_12P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din12 Location=HR_1_24_12P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din12 Location=HR_1_24_12P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=din20 Location= Port=EN Signal=in:f2g_in_en_{A|B}", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF LinkedObject=dinosc0 Location=HR_2_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc0 Location=HR_2_20_10P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc0 Location=HR_2_20_10P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=dinosc1 Location=HR_5_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc1 Location=HR_5_20_10P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc1 Location=HR_5_20_10P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=dinosc2 Location= Port=EN Signal=in:f2g_in_en_{A|B}", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_DDR LinkedObject=dinosc2 Location= Port=E Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_DDR LinkedObject=dinosc2 Location= Port=R Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF LinkedObject=dinosc3 Location=HR_5_22_11P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc3 Location=HR_5_22_11P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc3 Location=HR_5_22_11P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=dinosc4 Location=HR_1_30_15P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=dinosc4 Location=HR_1_30_15P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=dinosc4 Location=HR_1_30_15P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT LinkedObject=clk_out Location=HR_2_8_4P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_8_4P Port=CLK_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_8_4P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", + " Skip reason: User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", + " Module=O_BUFT LinkedObject=clk_out_osc Location=HR_2_9_4N Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_SERDES_CLK LinkedObject=clk_out_osc Location=HR_2_9_4N Port=CLK_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out_osc Location=HR_2_9_4N Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object clk_out_osc wrapped-instance port PLL_LOCK", + " Skip reason: User design does not utilize linked-object clk_out_osc wrapped-instance port PLL_LOCK", + " Module=O_BUFT LinkedObject=dinoutosc Location=HR_2_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dout00 Location=HP_1_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout00 Location=HP_1_22_11P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout00 Location=HP_1_22_11P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT LinkedObject=dout01 Location=HR_1_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout01 Location=HR_1_22_11P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout01 Location=HR_1_22_11P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT LinkedObject=dout10 Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", " Module=O_DDR LinkedObject=dout10 Location= Port=E Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=O_DDR LinkedObject=dout10 Location= Port=R Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", + " Module=O_BUFT LinkedObject=dout11 Location=HR_5_4_2P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout11 Location=HR_5_4_2P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout11 Location=HR_5_4_2P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT LinkedObject=dout12 Location=HR_1_26_13P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DDR LinkedObject=dout12 Location=HR_1_26_13P Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout12 Location=HR_1_26_13P Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", + " Module=O_BUFT LinkedObject=dout20 Location= Port=T Signal=in:f2g_tx_oe_{A|B}", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=LOCK Signal=out:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=LOCK Signal=out:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=LOCK Signal=out:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF LinkedObject=clk30 Location=HR_1_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", - " User design does not utilize linked-object clk30 wrapped-instance port EN", + " Skip reason: User design does not utilize linked-object clk30 wrapped-instance port EN", " Module=PLL LinkedObject=clk30 Location=HR_1_CC_38_19P Port=LOCK Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object clk30 wrapped-instance port LOCK", + " Skip reason: User design does not utilize linked-object clk30 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk30 Location=HR_1_CC_38_19P Port=PLL_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=clk31 Location=HR_3_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", - " User design does not utilize linked-object clk31 wrapped-instance port EN", + " Skip reason: User design does not utilize linked-object clk31 wrapped-instance port EN", " Module=PLL LinkedObject=clk31 Location=HR_3_CC_38_19P Port=LOCK Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object clk31 wrapped-instance port LOCK", + " Skip reason: User design does not utilize linked-object clk31 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk31 Location=HR_3_CC_38_19P Port=PLL_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=clk40 Location=HR_2_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", - " User design does not utilize linked-object clk40 wrapped-instance port EN", + " Skip reason: User design does not utilize linked-object clk40 wrapped-instance port EN", " Module=I_BUF_DS LinkedObject=din30_n+din30_p Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din30_n+din30_p Location=HR_2_1_0N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din30_n+din30_p Location=HR_2_1_0N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF_DS LinkedObject=din31_n+din31_p Location=HR_2_2_1P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din31_n+din31_p Location=HR_2_3_1N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din31_n+din31_p Location=HR_2_3_1N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout30_n+dout30_p Location=HR_2_7_3N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout30_n+dout30_p Location=HR_2_7_3N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", "End of IO Analysis" ], "instances" : [ @@ -1473,7 +1519,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out", "linked_object" : "clk_out", "linked_objects" : { @@ -1517,7 +1563,7 @@ "CLOCK_PHASE" : "270", "DATA_RATE" : "SDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1526,7 +1572,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out_osc", "linked_object" : "clk_out_osc", "linked_objects" : { @@ -1570,7 +1616,7 @@ "CLOCK_PHASE" : "180", "DATA_RATE" : "DDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1580,7 +1626,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dinoutosc", "linked_object" : "dinoutosc", "linked_objects" : { @@ -1605,7 +1651,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout00", "linked_object" : "dout00", "linked_objects" : { @@ -1647,7 +1693,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1656,7 +1702,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout01", "linked_object" : "dout01", "linked_objects" : { @@ -1698,7 +1744,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1707,7 +1753,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout10", "linked_object" : "dout10", "linked_objects" : { @@ -1749,7 +1795,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1758,7 +1804,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout11", "linked_object" : "dout11", "linked_objects" : { @@ -1800,7 +1846,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1809,7 +1855,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout12", "linked_object" : "dout12", "linked_objects" : { @@ -1851,7 +1897,7 @@ }, "parameters" : { }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1860,7 +1906,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout20", "linked_object" : "dout20", "linked_objects" : { diff --git a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json index 1b677096b..2d583fc86 100644 --- a/tests/unittest/ModelConfig/model_config_netlist.ppdb.json +++ b/tests/unittest/ModelConfig/model_config_netlist.ppdb.json @@ -59,34 +59,34 @@ " Cell port \\I is connected to input port \\reset", " Parameter \\WEAK_KEEPER: \"NONE\"", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_clk_out", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_clk_out", " Cell port \\O is connected to output port \\clk_out", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap", " Cell port \\O is connected to output port \\delay_tap[0]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap_1", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap_1", " Cell port \\O is connected to output port \\delay_tap[1]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap_2", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap_2", " Cell port \\O is connected to output port \\delay_tap[2]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap_3", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap_3", " Cell port \\O is connected to output port \\delay_tap[3]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap_4", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap_4", " Cell port \\O is connected to output port \\delay_tap[4]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_delay_tap_5", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_delay_tap_5", " Cell port \\O is connected to output port \\delay_tap[5]", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout", " Cell port \\O is connected to output port \\dout", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout_clk2", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout_clk2", " Cell port \\O is connected to output port \\dout_clk2", " Data Width: 1", - " Get important connection of cell \\O_BUF $obuf$top.$obuf_dout_serdes", + " Get important connection of cell \\O_BUFT $obuf$top.$obuf_dout_serdes", " Cell port \\O is connected to output port \\dout_serdes", " Data Width: 1", " Get important connection of cell \\BOOT_CLOCK \\boot_clock", @@ -160,20 +160,20 @@ " Trace \\I_DELAY --> \\I_DDR", " Trace \\I_DELAY --> \\I_SERDES", " Trace \\O_BUF --> \\O_DELAY", - " Try \\O_BUF $obuf$top.$obuf_dout out connection: $obuf_dout -> \\o_delay", + " Trace \\O_BUF --> \\O_DDR", + " Trace \\O_BUF --> \\O_SERDES", + " Trace \\O_BUFT --> \\O_DELAY", + " Try \\O_BUFT $obuf$top.$obuf_dout out connection: $obuf_dout -> \\o_delay", " Connected \\o_delay", " Parameter \\DELAY: 60", " Data Width: 1", - " Trace \\O_BUF --> \\O_DDR", - " Trace \\O_BUF --> \\O_SERDES", - " Try \\O_BUF $obuf$top.$obuf_dout_serdes out connection: $obuf_dout_serdes -> \\o_serdes", + " Trace \\O_BUFT --> \\O_DDR", + " Trace \\O_BUFT --> \\O_SERDES", + " Try \\O_BUFT $obuf$top.$obuf_dout_serdes out connection: $obuf_dout_serdes -> \\o_serdes", " Connected \\o_serdes", " Parameter \\DATA_RATE: \"DDR\"", " Parameter \\WIDTH: 4", " Data Width: 4", - " Trace \\O_BUFT --> \\O_DELAY", - " Trace \\O_BUFT --> \\O_DDR", - " Trace \\O_BUFT --> \\O_SERDES", " Trace \\O_BUF_DS --> \\O_DELAY", " Trace \\O_BUF_DS --> \\O_DDR", " Try \\O_BUF_DS \\o_buf_ds out connection: \\o_buf_ds_i -> \\o_ddr", @@ -189,12 +189,12 @@ " Trace \\O_DELAY --> \\O_DDR", " Trace \\O_DELAY --> \\O_SERDES", " Trace \\O_BUF --> \\O_SERDES_CLK", - " Try \\O_BUF $obuf$top.$obuf_clk_out out connection: $obuf_clk_out -> \\o_serdes_clk", + " Trace \\O_BUFT --> \\O_SERDES_CLK", + " Try \\O_BUFT $obuf$top.$obuf_clk_out out connection: $obuf_clk_out -> \\o_serdes_clk", " Connected \\o_serdes_clk", " Parameter \\CLOCK_PHASE: 270", " Parameter \\DATA_RATE: \"SDR\"", " Data Width: -2", - " Trace \\O_BUFT --> \\O_SERDES_CLK", " Trace \\O_BUF_DS --> \\O_SERDES_CLK", " Trace \\O_BUFT_DS --> \\O_SERDES_CLK", " Trace fabric clock buffer", @@ -216,7 +216,7 @@ " Connected to \\PLL \\pll port \\CLK_OUT", " Trace Fabric Clock", " Module \\CLK_BUF $clkbuf$top.$ibuf_clk0: clock port \\O, net $clk_buf_$ibuf_clk0", - " Connected to cell \\DFFRE $abc$218$auto$blifparse.cc:377:parse_blif$219", + " Connected to cell \\DFFRE $abc$218$auto_219", " Which is not a IO primitive. Send to fabric", " Module \\CLK_BUF \\clk_buf: clock port \\O, net \\clk1_buf", " Connected to cell \\O_DELAY \\o_delay", @@ -234,10 +234,10 @@ " Does not meet core_clk checking criteria. Not sending to fabric", " Connected to cell \\O_DDR \\o_ddr", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\PLL \\pll: clock port \\CLK_OUT_DIV4, net $delete_wire$530", " Module \\CLK_BUF $clkbuf$top.$ibuf_clk2: clock port \\O, net $clk_buf_$ibuf_clk2", - " Connected to cell \\DFFRE $abc$222$auto$blifparse.cc:377:parse_blif$223", + " Connected to cell \\DFFRE $abc$222$auto_223", " Which is not a IO primitive. Send to fabric", " Module \\BOOT_CLOCK \\boot_clock: clock port \\O, net \\osc", " Connected to cell \\PLL \\pll_osc", @@ -246,9 +246,9 @@ " Module \\PLL \\pll_osc: clock port \\CLK_OUT, net \\osc_pll", " Connected to cell \\O_DDR \\o_ddr_osc", " Which is a primitive", - " This is core_clk. Send to fabric", + " This is gearbox core_clk. Send to fabric", " Module \\FCLK_BUF $clkbuf$top.clk0_div: clock port \\O, net $fclk_buf_clk0_div", - " Connected to cell \\DFFRE $abc$210$auto$blifparse.cc:377:parse_blif$211", + " Connected to cell \\DFFRE $abc$210$auto_211", " Which is not a IO primitive. Send to fabric", " Summary", " |---------------------------------------------------------------------------------------------------|", @@ -261,16 +261,16 @@ " IN | din_serdes * I_BUF |-> I_SERDES * |", " IN | enable * I_BUF * |", " IN | reset * I_BUF * |", - " OUT | * O_SERDES_CLK |-> O_BUF * clk_out |", - " OUT | * O_BUF * delay_tap[0] |", - " OUT | * O_BUF * delay_tap[1] |", - " OUT | * O_BUF * delay_tap[2] |", - " OUT | * O_BUF * delay_tap[3] |", - " OUT | * O_BUF * delay_tap[4] |", - " OUT | * O_BUF * delay_tap[5] |", - " OUT | * O_DELAY |-> O_BUF * dout |", - " OUT | * O_BUF * dout_clk2 |", - " OUT | * O_SERDES |-> O_BUF * dout_serdes |", + " OUT | * O_SERDES_CLK |-> O_BUFT * clk_out |", + " OUT | * O_BUFT * delay_tap[0] |", + " OUT | * O_BUFT * delay_tap[1] |", + " OUT | * O_BUFT * delay_tap[2] |", + " OUT | * O_BUFT * delay_tap[3] |", + " OUT | * O_BUFT * delay_tap[4] |", + " OUT | * O_BUFT * delay_tap[5] |", + " OUT | * O_DELAY |-> O_BUFT * dout |", + " OUT | * O_BUFT * dout_clk2 |", + " OUT | * O_SERDES |-> O_BUFT * dout_serdes |", " IN | BOOT_CLOCK#0 * BOOT_CLOCK |-> PLL * |", " IN | din_n+din_p * I_BUF_DS |-> I_DDR * |", " OUT | * O_DDR |-> O_BUF_DS * dout_n+dout_p |", @@ -307,15 +307,15 @@ " Determine data signals", " Pin object=clk0, location: HR_1_CC_18_9P", " Data signal from object clk0", - " Module=I_BUF Linked-object=clk0 Port=O Net=$flatten$auto$rs_design_edit.cc:1153:execute$575.$ibuf_clk0 - Not found", - " Failure reason: Clock data from object clk0 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk0 Port=O Net=$flatten$auto_577.$ibuf_clk0 - Not found", + " Fail reason: Clock data from object clk0 port O is not routed to fabric", " Pin object=clk1, location: HP_1_CC_18_9P", " Data signal from object clk1", - " Failure reason: Object clk1 is primitive \\PLL but data signal is not defined", + " Fail reason: Object clk1 is primitive \\PLL but data signal is not defined", " Pin object=clk2, location: HR_5_CC_38_19P", " Data signal from object clk2", - " Module=I_BUF Linked-object=clk2 Port=O Net=$flatten$auto$rs_design_edit.cc:1153:execute$575.$ibuf_clk2 - Not found", - " Failure reason: Clock data from object clk2 port O is not routed to fabric", + " Module=I_BUF Linked-object=clk2 Port=O Net=$flatten$auto_577.$ibuf_clk2 - Not found", + " Fail reason: Clock data from object clk2 port O is not routed to fabric", " Pin object=din, location: HP_1_20_10P", " Data signal from object din", " Module=I_DELAY Linked-object=din Port=O Net=din_delay - Found", @@ -339,31 +339,31 @@ " Module=I_BUF Linked-object=reset Port=O Net=$ibuf_reset - Found", " Pin object=clk_out, location: HR_2_4_2P", " Data signal from object clk_out", - " Failure reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", + " Fail reason: Object clk_out is primitive \\O_SERDES_CLK but data signal is not defined", " Pin object=delay_tap[0], location: HR_2_20_10P", " Data signal from object delay_tap[0]", - " Module=O_BUF Linked-object=delay_tap[0] Port=I Net=$obuf_delay_tap[0] - Found", + " Module=O_BUFT Linked-object=delay_tap[0] Port=I Net=$obuf_delay_tap[0] - Found", " Pin object=delay_tap[1], location: HR_2_22_11P", " Data signal from object delay_tap[1]", - " Module=O_BUF Linked-object=delay_tap[1] Port=I Net=$obuf_delay_tap[1] - Found", + " Module=O_BUFT Linked-object=delay_tap[1] Port=I Net=$obuf_delay_tap[1] - Found", " Pin object=delay_tap[2], location: HR_2_24_12P", " Data signal from object delay_tap[2]", - " Module=O_BUF Linked-object=delay_tap[2] Port=I Net=$obuf_delay_tap[2] - Found", + " Module=O_BUFT Linked-object=delay_tap[2] Port=I Net=$obuf_delay_tap[2] - Found", " Pin object=delay_tap[3], location: HR_2_26_13P", " Data signal from object delay_tap[3]", - " Module=O_BUF Linked-object=delay_tap[3] Port=I Net=$obuf_delay_tap[3] - Found", + " Module=O_BUFT Linked-object=delay_tap[3] Port=I Net=$obuf_delay_tap[3] - Found", " Pin object=delay_tap[4], location: HR_2_28_14P", " Data signal from object delay_tap[4]", - " Module=O_BUF Linked-object=delay_tap[4] Port=I Net=$obuf_delay_tap[4] - Found", + " Module=O_BUFT Linked-object=delay_tap[4] Port=I Net=$obuf_delay_tap[4] - Found", " Pin object=delay_tap[5], location: HR_2_30_15P", " Data signal from object delay_tap[5]", - " Module=O_BUF Linked-object=delay_tap[5] Port=I Net=$obuf_delay_tap[5] - Found", + " Module=O_BUFT Linked-object=delay_tap[5] Port=I Net=$obuf_delay_tap[5] - Found", " Pin object=dout, location: HP_2_20_10P", " Data signal from object dout", " Module=O_DELAY Linked-object=dout Port=I Net=dout_pre_delay - Found", " Pin object=dout_clk2, location: HR_5_1_0N", " Data signal from object dout_clk2", - " Module=O_BUF Linked-object=dout_clk2 Port=I Net=$obuf_dout_clk2 - Found", + " Module=O_BUFT Linked-object=dout_clk2 Port=I Net=$obuf_dout_clk2 - Found", " Pin object=dout_serdes, location: HR_2_2_1P", " Data signal from object dout_serdes", " Module=O_SERDES Linked-object=dout_serdes Port=D Net=$abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[0] - Found", @@ -380,20 +380,21 @@ " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_p, location: HP_1_8_4P", " Data signal from object dout_p", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$557 - Found", - " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$558 - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto_567 - Found", + " Module=O_DDR Linked-object=dout_n+dout_p Port=D Net=$auto_568 - Found", " Pin object=dout_osc_n, location: HP_2_23_11N", " Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid'", " Pin object=dout_osc_p, location: HP_2_22_11P", " Data signal from object dout_osc_p", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$559 - Found", - " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto$rs_design_edit.cc:621:add_wire_btw_prims$560 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto_569 - Found", + " Module=O_DDR Linked-object=dout_osc_n+dout_osc_p Port=D Net=$auto_570 - Found", " Determine internal control signals", " Module=I_BUF LinkedObject=clk0 Location=HR_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=clk1 Location=HP_1_CC_18_9P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=PLL LinkedObject=clk1 Location=HP_1_CC_18_9P Port=LOCK Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object clk1 wrapped-instance port LOCK", + " Skip reason: User design does not utilize linked-object clk1 wrapped-instance port LOCK", " Module=PLL LinkedObject=clk1 Location=HP_1_CC_18_9P Port=PLL_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_BUF LinkedObject=clk2 Location=HR_5_CC_38_19P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=din Location=HP_1_20_10P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DELAY LinkedObject=din Location=HP_1_20_10P Port=DLY_ADJ Signal=in:rule=half-first:f2g_trx_dly_adj", @@ -403,49 +404,69 @@ " Module=I_BUF LinkedObject=din_clk2 Location=HR_5_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_BUF LinkedObject=din_serdes Location=HR_2_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=BITSLIP_ADJ Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DATA_VALID Signal=out:g2f_rx_dvalid_{A|B}", - " User design does not utilize linked-object din_serdes wrapped-instance port DATA_VALID", + " Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DATA_VALID", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DPA_ERROR Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object din_serdes wrapped-instance port DPA_ERROR", + " Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DPA_ERROR", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=DPA_LOCK Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object din_serdes wrapped-instance port DPA_LOCK", + " Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DPA_LOCK", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object din_serdes wrapped-instance port PLL_LOCK", + " Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port PLL_LOCK", " Module=I_SERDES LinkedObject=din_serdes Location=HR_2_0_0P Port=RST Signal=in:f2g_trx_reset_n_{A|B}", " Module=I_BUF LinkedObject=enable Location= Port=EN Signal=in:f2g_in_en_{A|B}", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF LinkedObject=reset Location=HP_1_0_0P Port=EN Signal=in:f2g_in_en_{A|B}", + " Module=O_BUFT LinkedObject=clk_out Location=HR_2_4_2P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_4_2P Port=CLK_EN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_SERDES_CLK LinkedObject=clk_out Location=HR_2_4_2P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", + " Skip reason: User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK", + " Module=O_BUFT LinkedObject=delay_tap[0] Location=HR_2_20_10P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=delay_tap[1] Location=HR_2_22_11P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=delay_tap[2] Location=HR_2_24_12P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=delay_tap[3] Location=HR_2_26_13P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=delay_tap[4] Location=HR_2_28_14P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=delay_tap[5] Location=HR_2_30_15P Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dout Location=HP_2_20_10P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_ADJ Signal=in:rule=half-first:f2g_trx_dly_adj", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_INCDEC Signal=in:rule=half-first:f2g_trx_dly_inc", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_LOAD Signal=in:rule=half-first:f2g_trx_dly_ld", " Module=O_DELAY LinkedObject=dout Location=HP_2_20_10P Port=DLY_TAP_VALUE Signal=out:rule=half-first:g2f_trx_dly_tap", - " User design does not utilize linked-object dout wrapped-instance port DLY_TAP_VALUE", + " Skip reason: User design does not utilize linked-object dout wrapped-instance port DLY_TAP_VALUE", + " Module=O_BUFT LinkedObject=dout_clk2 Location=HR_5_1_0N Port=T Signal=in:f2g_tx_oe_{A|B}", + " Module=O_BUFT LinkedObject=dout_serdes Location=HR_2_2_1P Port=T Signal=in:f2g_tx_oe_{A|B}", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=CHANNEL_BOND_SYNC_IN Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_IN", + " Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_IN", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=CHANNEL_BOND_SYNC_OUT Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_OUT", + " Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_OUT", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=DATA_VALID Signal=in:f2g_tx_dvalid_{A|B}", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=OE_IN Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=OE_OUT Signal=out:TO_BE_DETERMINED", - " User design does not utilize linked-object dout_serdes wrapped-instance port OE_OUT", + " Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port OE_OUT", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=PLL_LOCK Signal=in:TO_BE_DETERMINED", - " User design does not utilize linked-object dout_serdes wrapped-instance port PLL_LOCK", + " Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port PLL_LOCK", " Module=O_SERDES LinkedObject=dout_serdes Location=HR_2_2_1P Port=RST Signal=in:f2g_trx_reset_n_{A|B}", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=LOCK Signal=out:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=PLL LinkedObject=BOOT_CLOCK#0 Location= Port=PLL_EN Signal=in:TO_BE_DETERMINED", - " Location does not have any mode to begin with", + " Skip reason: Location does not have any mode to begin with", " Module=I_BUF_DS LinkedObject=din_n+din_p Location=HP_1_4_2P Port=EN Signal=in:f2g_in_en_{A|B}", " Module=I_DDR LinkedObject=din_n+din_p Location=HP_1_5_2N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=I_DDR LinkedObject=din_n+din_p Location=HP_1_5_2N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_9_4N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_n+dout_p Location=HP_1_9_4N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_23_11N Port=E Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", " Module=O_DDR LinkedObject=dout_osc_n+dout_osc_p Location=HP_2_23_11N Port=R Signal=in:TO_BE_DETERMINED", + " Skip reason: TO_BE_DETERMINED", "End of IO Analysis" ], "instances" : [ @@ -845,7 +866,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_clk_out", "linked_object" : "clk_out", "linked_objects" : { @@ -889,7 +910,7 @@ "CLOCK_PHASE" : "270", "DATA_RATE" : "SDR" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -898,7 +919,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap", "linked_object" : "delay_tap[0]", "linked_objects" : { @@ -923,7 +944,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_1", "linked_object" : "delay_tap[1]", "linked_objects" : { @@ -948,7 +969,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_2", "linked_object" : "delay_tap[2]", "linked_objects" : { @@ -973,7 +994,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_3", "linked_object" : "delay_tap[3]", "linked_objects" : { @@ -998,7 +1019,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_4", "linked_object" : "delay_tap[4]", "linked_objects" : { @@ -1023,7 +1044,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_delay_tap_5", "linked_object" : "delay_tap[5]", "linked_objects" : { @@ -1048,7 +1069,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout", "linked_object" : "dout", "linked_objects" : { @@ -1092,7 +1113,7 @@ "parameters" : { "DELAY" : "60" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { @@ -1101,7 +1122,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout_clk2", "linked_object" : "dout_clk2", "linked_objects" : { @@ -1126,7 +1147,7 @@ ] }, { - "module" : "O_BUF", + "module" : "O_BUFT", "name" : "$obuf$top.$obuf_dout_serdes", "linked_object" : "dout_serdes", "linked_objects" : { @@ -1171,7 +1192,7 @@ "DATA_RATE" : "DDR", "WIDTH" : "4" }, - "pre_primitive" : "O_BUF", + "pre_primitive" : "O_BUFT", "post_primitives" : [ ], "route_clock_to" : { From da41414d5ffeda3a2b0e6abe21a1a4de8b44ca6b Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 12:55:24 -0700 Subject: [PATCH 02/14] Support CORE clock setting --- src/Compiler/CompilerOpenFPGA.cpp | 48 +- src/Compiler/CompilerOpenFPGA.h | 1 + src/Configuration/ModelConfig/CMakeLists.txt | 1 + src/Configuration/ModelConfig/ModelConfig.cpp | 9 +- .../ModelConfig_BITSTREAM_SETTING_XML.cpp | 149 ++++ .../ModelConfig_BITSTREAM_SETTING_XML.h | 46 + .../ModelConfig/ModelConfig_IO.cpp | 2 +- .../ModelConfig/ModelConfig_IO.h | 4 +- tests/unittest/CMakeLists.txt | 1 + ...ModelConfig_BITSTREAM_SETTING_XML_test.cpp | 49 ++ tests/unittest/ModelConfig/Pin_Table.csv | 815 ++++++++++++++++++ tests/unittest/ModelConfig/design_edit.sdc | 580 +++++++++++++ .../ModelConfig/empty_bitstream_setting.xml | 2 + .../ModelConfig/golden/bitstream_setting.xml | 11 + 14 files changed, 1707 insertions(+), 11 deletions(-) create mode 100644 src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp create mode 100644 src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h create mode 100644 tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp create mode 100644 tests/unittest/ModelConfig/Pin_Table.csv create mode 100644 tests/unittest/ModelConfig/design_edit.sdc create mode 100644 tests/unittest/ModelConfig/empty_bitstream_setting.xml create mode 100644 tests/unittest/ModelConfig/golden/bitstream_setting.xml diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index 4350df167..2a9bef383 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -739,8 +739,12 @@ std::pair CompilerOpenFPGA::IsDeviceSizeCorrect( return std::make_pair(false, "Architecture file: fixed_layout is missing"); for (int i = 0; i < fixedLayout.count(); i++) { auto node = fixedLayout.at(i).toElement(); - if (node.attribute("name").toStdString() == size) - return std::make_pair(true, std::string{}); + if (node.attribute("name").toStdString() == size) { + std::string device_dimension = + CFG_print("%sx%s", node.attribute("width").toStdString().c_str(), + node.attribute("height").toStdString().c_str()); + return std::make_pair(true, device_dimension); + } } return std::make_pair(false, std::string{"Device size is not correct"}); } @@ -3293,7 +3297,7 @@ repack --design_constraints ${OPENFPGA_REPACK_CONSTRAINTS} build_architecture_bitstream --verbose \ --write_file fabric_independent_bitstream.xml - + build_fabric_bitstream write_fabric_verilog --file BIT_SIM \ @@ -3438,15 +3442,15 @@ std::string CompilerOpenFPGA::FinishOpenFPGAScript(const std::string& script) { // Don't skip result = ReplaceAll(result, "${VPR_PB_PIN_FIXUP}", "off"); } - if (m_OpenFpgaBitstreamSettingFile.string().empty()) { + if (m_runtime_OpenFpgaBitstreamSettingFile.string().empty()) { result = ReplaceAll(result, "${OPENFPGA_BITSTREAM_SETTING_FILE}", ""); } else { result = ReplaceAll(result, "${OPENFPGA_BITSTREAM_SETTING_FILE}", "read_openfpga_bitstream_setting -f " + - m_OpenFpgaBitstreamSettingFile.string()); + m_runtime_OpenFpgaBitstreamSettingFile.string()); } result = ReplaceAll(result, "${OPENFPGA_BITSTREAM_SETTING_FILE}", - m_OpenFpgaBitstreamSettingFile.string()); + m_runtime_OpenFpgaBitstreamSettingFile.string()); result = ReplaceAll(result, "${OPENFPGA_PIN_CONSTRAINTS}", m_OpenFpgaPinConstraintXml.string()); @@ -3568,6 +3572,38 @@ bool CompilerOpenFPGA::GenerateBitstream() { // Force bitstream generation } + // Before generating fabric bitstream script, determine the runtime bitstream + // setting file which might include the runtime design IO tile clock out + std::pair io_status = IsDeviceSizeCorrect(m_deviceSize); + if (io_status.first) { + std::filesystem::path design_edit_sdc = + FilePath(Action::Synthesis, "design_edit.sdc"); + if (std::filesystem::exists(design_edit_sdc)) { + std::string command = CFG_print( + "model_config gen_bitstream_setting_xml -device_size %s -design %s " + "-pin %s " + "%s bitstream_setting.xml", + io_status.second.c_str(), design_edit_sdc.c_str(), + m_PinMapCSV.c_str(), m_OpenFpgaBitstreamSettingFile.c_str()); + auto file = ProjManager()->projectName() + "_io_clk_out_cmd.tcl"; + FileUtils::WriteToFile(file, command); + command = CFG_print("source %s", file.c_str()); + int status = TCL_OK; + m_interp->evalCmd(command, &status); + if (status != TCL_OK) { + ErrorMessage("Design " + ProjManager()->projectName() + + " IO Clock out generation failed"); + return false; + } else { + m_runtime_OpenFpgaBitstreamSettingFile = "bitstream_setting.xml"; + } + } else { + m_runtime_OpenFpgaBitstreamSettingFile = m_OpenFpgaBitstreamSettingFile; + } + } else { + m_runtime_OpenFpgaBitstreamSettingFile = m_OpenFpgaBitstreamSettingFile; + } + std::string command = m_openFpgaExecutablePath.string() + " -batch -f " + ProjManager()->projectName() + ".openfpga"; diff --git a/src/Compiler/CompilerOpenFPGA.h b/src/Compiler/CompilerOpenFPGA.h index cbf3a8910..400eebbf8 100644 --- a/src/Compiler/CompilerOpenFPGA.h +++ b/src/Compiler/CompilerOpenFPGA.h @@ -228,6 +228,7 @@ class CompilerOpenFPGA : public Compiler { std::filesystem::path m_routingGraphFile = ""; std::filesystem::path m_OpenFpgaSimSettingFile = ""; std::filesystem::path m_OpenFpgaBitstreamSettingFile = ""; + std::filesystem::path m_runtime_OpenFpgaBitstreamSettingFile = ""; std::filesystem::path m_OpenFpgaRepackConstraintsFile = ""; std::filesystem::path m_OpenFpgaFabricKeyFile = ""; std::filesystem::path m_OpenFpgaPinMapXml = ""; diff --git a/src/Configuration/ModelConfig/CMakeLists.txt b/src/Configuration/ModelConfig/CMakeLists.txt index 50db7dd73..b97d948f8 100644 --- a/src/Configuration/ModelConfig/CMakeLists.txt +++ b/src/Configuration/ModelConfig/CMakeLists.txt @@ -53,6 +53,7 @@ add_library( ModelConfig.cpp ModelConfig_IO_resource.cpp ModelConfig_IO.cpp + ModelConfig_BITSTREAM_SETTING_XML.cpp ) ################### diff --git a/src/Configuration/ModelConfig/ModelConfig.cpp b/src/Configuration/ModelConfig/ModelConfig.cpp index fcf07a475..c82bcee17 100644 --- a/src/Configuration/ModelConfig/ModelConfig.cpp +++ b/src/Configuration/ModelConfig/ModelConfig.cpp @@ -23,6 +23,7 @@ along with this program. If not, see . #include "CFGCommon/CFGCommon.h" #include "DeviceModeling/Model.h" #include "DeviceModeling/device.h" +#include "ModelConfig_BITSTREAM_SETTING_XML.h" #include "ModelConfig_IO.h" #include "nlohmann_json/json.hpp" @@ -911,7 +912,13 @@ void model_config_entry(CFGCommon_ARG* cmdarg) { &cmdarg->raws[0], flag_options, options, positional_options, {"is_unittest"}, {"netlist_ppdb", "config_mapping"}, {"property_json", "pll_workaround"}, 1); - ModelConfig_IO io(cmdarg, flag_options, options, positional_options[0]); + ModelConfig_IO io(flag_options, options, positional_options[0]); + } else if (cmdarg->raws[0] == "gen_bitstream_setting_xml") { + CFGArg::parse("model_config|gen_bitstream_setting_xml", cmdarg->raws.size(), + &cmdarg->raws[0], flag_options, options, positional_options, + {}, {"device_size", "design", "pin"}, {}, 2); + ModelConfig_BITSREAM_SETTINGS_XML xml( + flag_options, options, positional_options[0], positional_options[1]); } else if (cmdarg->raws[0] == "backdoor") { CFGArg::parse("model_config|gen_ppdb", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp new file mode 100644 index 000000000..142b3f765 --- /dev/null +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -0,0 +1,149 @@ +/* +Copyright 2023 The Foedag team + +GPL License + +Copyright (c) 2023 The Open-Source FPGA Foundation + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +*/ + +#include "ModelConfig_BITSTREAM_SETTING_XML.h" + +#include +#include + +namespace FOEDAG { + +struct PIN_INFO { + PIN_INFO(uint32_t i) : fabric_clk_index(i) {} + const uint32_t fabric_clk_index = 0; + uint32_t x = 0; + uint32_t y = 0; + std::string type = ""; +}; + +/* + Constructor +*/ +ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( + const std::vector& flag_options, + const std::map& options, const std::string& input, + const std::string& output) { + std::vector device_sizes = + CFG_split_string(options.at("device_size"), "x"); + if (device_sizes.size() == 2) { + uint32_t device_x = (uint32_t)(CFG_convert_string_to_u64(device_sizes[0])); + uint32_t device_y = (uint32_t)(CFG_convert_string_to_u64(device_sizes[1])); + std::ifstream design(options.at("design").c_str()); + CFG_ASSERT(design.is_open() && design.good()); + std::string line = ""; + std::map location_map; + while (std::getline(design, line)) { + CFG_get_rid_trailing_whitespace(line); + if (line.size() > 0 && line.find("set_core_clk") == 0) { + std::vector words = CFG_split_string(line, " ", 0, false); + CFG_ASSERT(words.size() == 3); + CFG_ASSERT(words[0] == "set_core_clk"); + uint32_t index = (uint32_t)(CFG_convert_string_to_u64(words[2])); + location_map[words[1]] = new PIN_INFO(index); + } + } + design.close(); + if (location_map.size()) { + std::ifstream pin(options.at("pin").c_str()); + CFG_ASSERT(pin.is_open() && pin.good()); + while (std::getline(pin, line)) { + CFG_get_rid_trailing_whitespace(line); + std::vector words = CFG_split_string(line, ","); + if (words.size() >= 11 && words[2].size() > 0 && + location_map.find(words[2]) != location_map.end()) { + location_map.at(words[2])->x = + (uint32_t)(CFG_convert_string_to_u64(words[9])); + location_map.at(words[2])->y = + (uint32_t)(CFG_convert_string_to_u64(words[10])); + } + } + pin.close(); + } + std::ofstream oxml(output.c_str()); + if (input.size() && std::filesystem::exists(input.c_str())) { + std::ifstream ixml(input.c_str()); + CFG_ASSERT(ixml.is_open()); + CFG_ASSERT(ixml.good()); + oxml << "\n"; + bool found_xml_end = false; + std::string line = ""; + while (std::getline(ixml, line)) { + std::string xml_line = line; + CFG_get_rid_whitespace(xml_line); + if (xml_line.find("") == 0) { + found_xml_end = true; + break; + } + oxml << line.c_str() << "\n"; + } + ixml.close(); + CFG_ASSERT(found_xml_end); + } else { + oxml << "\n"; + } + oxml << " \n"; + for (auto& iter : location_map) { + if (iter.second->y == 1 && iter.second->x >= 2 && + iter.second->x < (device_x - 2)) { + iter.second->type = "bottom"; + } else if (iter.second->y == (device_y - 2) && iter.second->x >= 2 && + iter.second->x < (device_x - 2)) { + iter.second->type = "top"; + } else if (iter.second->x == 1 && iter.second->y >= 2 && + iter.second->y < (device_y - 2)) { + iter.second->type = "left"; + } else if (iter.second->x == (device_x - 2) && iter.second->y >= 2 && + iter.second->y < (device_y - 2)) { + iter.second->type = "right"; + } + if (iter.second->type.size()) { + oxml << " \n"; + for (int i = 0; i < 4; i++) { + oxml << CFG_print( + " \n", + (iter.second->fabric_clk_index & (1 << i)) ? 1 : 0, + iter.second->type.c_str(), iter.second->x, iter.second->y, + i) + .c_str(); + } + } else { + oxml << " \n"; + } + } + oxml << " \n"; + oxml << "\n"; + oxml.close(); + for (auto& iter : location_map) { + delete iter.second; + } + } +} + +/* + Destructor +*/ +ModelConfig_BITSREAM_SETTINGS_XML::~ModelConfig_BITSREAM_SETTINGS_XML() {} + +} // namespace FOEDAG diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h new file mode 100644 index 000000000..7637bde12 --- /dev/null +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h @@ -0,0 +1,46 @@ +/* +Copyright 2023 The Foedag team + +GPL License + +Copyright (c) 2023 The Open-Source FPGA Foundation + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . + */ + +#ifndef MODEL_CONFIG_BITSTREAM_SETTING_XML_H +#define MODEL_CONFIG_BITSTREAM_SETTING_XML_H + +#include + +#include +#include +#include + +namespace FOEDAG { + +class ModelConfig_BITSREAM_SETTINGS_XML { + public: + ModelConfig_BITSREAM_SETTINGS_XML( + const std::vector& flag_options, + const std::map& options, + const std::string& input, const std::string& output); + ~ModelConfig_BITSREAM_SETTINGS_XML(); + + private: +}; + +} // namespace FOEDAG + +#endif diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.cpp b/src/Configuration/ModelConfig/ModelConfig_IO.cpp index 90c702cba..a65d3346d 100644 --- a/src/Configuration/ModelConfig/ModelConfig_IO.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_IO.cpp @@ -60,7 +60,7 @@ namespace FOEDAG { Constructor */ ModelConfig_IO::ModelConfig_IO( - CFGCommon_ARG* cmdarg, const std::vector& flag_options, + const std::vector& flag_options, const std::map& options, const std::string& output) { std::string netlist_ppdb = options.at("netlist_ppdb"); diff --git a/src/Configuration/ModelConfig/ModelConfig_IO.h b/src/Configuration/ModelConfig/ModelConfig_IO.h index 424d783b3..f80b3f6ed 100644 --- a/src/Configuration/ModelConfig/ModelConfig_IO.h +++ b/src/Configuration/ModelConfig/ModelConfig_IO.h @@ -31,7 +31,6 @@ along with this program. If not, see . #include "ModelConfig_IO_resource.h" #include "nlohmann_json/json.hpp" -struct CFGCommon_ARG; struct ModelConfig_IO_MSG; // clang-format off @@ -78,8 +77,7 @@ namespace FOEDAG { class ModelConfig_IO { public: - ModelConfig_IO(CFGCommon_ARG* cmdarg, - const std::vector& flag_options, + ModelConfig_IO(const std::vector& flag_options, const std::map& options, const std::string& output); ~ModelConfig_IO(); diff --git a/tests/unittest/CMakeLists.txt b/tests/unittest/CMakeLists.txt index 2915e3593..77313629d 100644 --- a/tests/unittest/CMakeLists.txt +++ b/tests/unittest/CMakeLists.txt @@ -72,6 +72,7 @@ set(CPP_LIST CFGCompiler/CFGCompiler_test.cpp ModelConfig/ModelConfig_test.cpp ModelConfig/ModelConfig_IO_test.cpp + ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp CFGProgrammer/CFGProgrammer_test.cpp MainWindow/PerfomanceTracker_test.cpp MainWindow/ProjectFileComponent_test.cpp diff --git a/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp new file mode 100644 index 000000000..a0b9b59ec --- /dev/null +++ b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp @@ -0,0 +1,49 @@ +/* +Copyright 2023 The Foedag team + +GPL License + +Copyright (c) 2023 The Open-Source FPGA Foundation + +This program is free software: you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation, either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see . +*/ + +#include "Utils/FileUtils.h" +#include "compiler_tcl_infra_common.h" + +class ModelConfig_BITSTREAM_SETTING_XML : public ::testing::Test { + protected: + void SetUp() override { + compiler_tcl_common_setup(); + create_unittest_directory("ModelConfig"); + std::filesystem::current_path("utst/ModelConfig"); + } + void TearDown() override { std::filesystem::current_path("../.."); } +}; + +TEST_F(ModelConfig_BITSTREAM_SETTING_XML, gen_bitstream_setting_xml) { + std::string current_dir = COMPILER_TCL_COMMON_GET_CURRENT_DIR(); + std::string cmd = CFG_print( + "model_config gen_bitstream_setting_xml -device_size 22x4 -design " + "%s/design_edit.sdc -pin %s/Pin_Table.csv %s/empty_bitstream_setting.xml " + "bitstream_setting.xml", + current_dir.c_str(), current_dir.c_str(), current_dir.c_str()); + compiler_tcl_common_run(cmd); +} + +TEST_F(ModelConfig_BITSTREAM_SETTING_XML, compare_result) { + std::string golden_dir = COMPILER_TCL_COMMON_GET_CURRENT_GOLDEN_DIR(); + compare_unittest_file(false, "bitstream_setting.xml", "ModelConfig", + golden_dir); +} diff --git a/tests/unittest/ModelConfig/Pin_Table.csv b/tests/unittest/ModelConfig/Pin_Table.csv new file mode 100644 index 000000000..9378a7a05 --- /dev/null +++ b/tests/unittest/ModelConfig/Pin_Table.csv @@ -0,0 +1,815 @@ +Group,Bump/Pin Name,Customer Name,Ball ID,Bump center_x,Bump center_y,Ball center_x,Ball center_y,IO_tile_pin,IO_tile_pin_x,IO_tile_pin_y,IO_tile_pin_z,EFPGA_PIN,Fullchip_NAME,MODE_GBOX_CC,MODE_BP_DIR_A_TX,MODE_BP_SDR_A_TX,MODE_BP_DDR_A_TX,MODE_RATE_3_A_TX,MODE_RATE_4_A_TX,MODE_RATE_5_A_TX,MODE_RATE_6_A_TX,MODE_RATE_7_A_TX,MODE_RATE_8_A_TX,MODE_RATE_9_A_TX,MODE_RATE_10_A_TX,MODE_BP_DIR_B_TX,MODE_BP_SDR_B_TX,MODE_BP_DDR_B_TX,MODE_RATE_3_B_TX,MODE_RATE_4_B_TX,MODE_RATE_5_B_TX,MODE_BP_DIR_A_RX,MODE_BP_SDR_A_RX,MODE_BP_DDR_A_RX,MODE_RATE_3_A_RX,MODE_RATE_4_A_RX,MODE_RATE_5_A_RX,MODE_RATE_6_A_RX,MODE_RATE_7_A_RX,MODE_RATE_8_A_RX,MODE_RATE_9_A_RX,MODE_RATE_10_A_RX,MODE_BP_DIR_B_RX,MODE_BP_SDR_B_RX,MODE_BP_DDR_B_RX,MODE_RATE_3_B_RX,MODE_RATE_4_B_RX,MODE_RATE_5_B_RX,MODE_MIPI,MODE_GPIO,MODE_UART0,MODE_UART1,MODE_I2C,MODE_SPI0,MODE_PWM,MODE_DDR,MODE_USB,MODE_ETH,Ref clock,BANK,ALT Function,Debug Mode,Scan Mode,Mbist Mode,Type,Direction,Voltage,Power Pad,Discription,Voltage2,Remark,Identifier,Customer Internal Name,Main Function,IS_FPGA_GPIO +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_23,2,1,23,A2F_21216,g2f_trx_dly_tap[0],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_22,2,1,22,A2F_21217,g2f_trx_dly_tap[1],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_21,2,1,21,A2F_21218,g2f_trx_dly_tap[2],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_20,2,1,20,A2F_21219,g2f_trx_dly_tap[3],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_19,2,1,19,A2F_21220,g2f_trx_dly_tap[4],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_2_1_18,2,1,18,A2F_21221,g2f_trx_dly_tap[5],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_2_1_17,2,1,17,A2F_21222,g2f_rx_dpa_lock,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_2_1_16,2,1,16,A2F_21223,g2f_rx_dpa_error,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_2_1_15,2,1,15,A2F_21224,g2f_rx_dpa_phase[0],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_2_1_14,2,1,14,A2F_21225,g2f_rx_dpa_phase[1],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_2_1_13,2,1,13,A2F_21226,g2f_rx_dpa_phase[2],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_71,2,1,71,F2A_21240,f2g_addr[0],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_70,2,1,70,F2A_21241,f2g_addr[1],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_69,2,1,69,F2A_21242,f2g_addr[2],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_68,2,1,68,F2A_21243,f2g_addr[3],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_67,2,1,67,F2A_21244,f2g_addr[4],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_66,2,1,66,F2A_21245,f2g_trx_dly_ld,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_65,2,1,65,F2A_21246,f2g_trx_dly_adj,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_64,2,1,64,F2A_21247,f2g_trx_dly_inc,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_2_1_63,2,1,63,F2A_21248,f2g_rx_bitslip_adj,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_3_1_23,3,1,23,A2F_21144,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_3_1_22,3,1,22,A2F_21145,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,460,40,1000,4000,FPGA_3_1_21,3,1,21,A2F_21146,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_20,3,1,20,A2F_21147,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_19,3,1,19,A2F_21148,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_18,3,1,18,A2F_21149,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_17,3,1,17,A2F_21150,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_16,3,1,16,A2F_21151,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_15,3,1,15,A2F_21152,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_14,3,1,14,A2F_21153,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_13,3,1,13,A2F_21154,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,980,40,2000,1000,FPGA_3_1_12,3,1,12,A2F_21155,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,980,40,2000,1000,FPGA_3_1_11,3,1,11,A2F_21156,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,980,40,2000,1000,FPGA_3_1_10,3,1,10,A2F_21157,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,70,40,1000,1000,FPGA_3_1_71,3,1,71,F2A_21168,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_70,3,1,70,F2A_21169,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_69,3,1,69,F2A_21170,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_68,3,1,68,F2A_21171,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_67,3,1,67,F2A_21172,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_66,3,1,66,F2A_21173,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_65,3,1,65,F2A_21174,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_64,3,1,64,F2A_21175,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_63,3,1,63,F2A_21176,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,200,40,1000,2000,FPGA_3_1_62,3,1,62,F2A_21177,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_3_1_61,3,1,61,F2A_21178,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_3_1_60,3,1,60,F2A_21179,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_3_1_59,3,1,59,F2A_21180,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,330,40,1000,3000,FPGA_3_1_58,3,1,58,F2A_21181,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_57,3,1,57,F2A_21182,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_56,3,1,56,F2A_21183,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,590,40,1000,5000,FPGA_3_1_55,3,1,55,F2A_21184,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,720,40,1000,6000,FPGA_3_1_54,3,1,54,F2A_21185,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,720,40,1000,6000,FPGA_3_1_53,3,1,53,F2A_21186,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,720,40,1000,6000,FPGA_3_1_52,3,1,52,F2A_21187,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,720,40,1000,6000,FPGA_3_1_51,3,1,51,F2A_21188,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_1,HP_1_0_0P,Y22,720,40,1000,6000,FPGA_3_1_50,3,1,50,F2A_21189,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_49,3,1,49,F2A_21190,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_48,3,1,48,F2A_21191,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_47,3,1,47,F2A_21192,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_46,3,1,46,F2A_21193,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_45,3,1,45,F2A_21194,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_44,3,1,44,F2A_21195,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_2,HP_1_1_0N,AA22,720,40,1000,6000,FPGA_3_1_43,3,1,43,F2A_21196,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,460,40,1000,4000,FPGA_4_1_23,4,1,23,A2F_21072,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,460,40,1000,4000,FPGA_4_1_22,4,1,22,A2F_21073,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,460,40,1000,4000,FPGA_4_1_21,4,1,21,A2F_21074,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_20,4,1,20,A2F_21075,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_19,4,1,19,A2F_21076,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_18,4,1,18,A2F_21077,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_17,4,1,17,A2F_21078,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_16,4,1,16,A2F_21079,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_15,4,1,15,A2F_21080,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_14,4,1,14,A2F_21081,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_13,4,1,13,A2F_21082,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,980,40,2000,1000,FPGA_4_1_12,4,1,12,A2F_21083,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,980,40,2000,1000,FPGA_4_1_11,4,1,11,A2F_21084,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,980,40,2000,1000,FPGA_4_1_10,4,1,10,A2F_21085,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,70,40,1000,1000,FPGA_4_1_71,4,1,71,F2A_21096,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_70,4,1,70,F2A_21097,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_69,4,1,69,F2A_21098,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_68,4,1,68,F2A_21099,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_67,4,1,67,F2A_21100,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_66,4,1,66,F2A_21101,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_65,4,1,65,F2A_21102,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_64,4,1,64,F2A_21103,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_63,4,1,63,F2A_21104,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,200,40,1000,2000,FPGA_4_1_62,4,1,62,F2A_21105,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,330,40,1000,3000,FPGA_4_1_61,4,1,61,F2A_21106,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,330,40,1000,3000,FPGA_4_1_60,4,1,60,F2A_21107,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,330,40,1000,3000,FPGA_4_1_59,4,1,59,F2A_21108,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,330,40,1000,3000,FPGA_4_1_58,4,1,58,F2A_21109,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_57,4,1,57,F2A_21110,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_56,4,1,56,F2A_21111,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,590,40,1000,5000,FPGA_4_1_55,4,1,55,F2A_21112,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,720,40,1000,6000,FPGA_4_1_54,4,1,54,F2A_21113,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,720,40,1000,6000,FPGA_4_1_53,4,1,53,F2A_21114,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,720,40,1000,6000,FPGA_4_1_52,4,1,52,F2A_21115,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,720,40,1000,6000,FPGA_4_1_51,4,1,51,F2A_21116,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_3,HP_1_2_1P,W21,720,40,1000,6000,FPGA_4_1_50,4,1,50,F2A_21117,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_49,4,1,49,F2A_21118,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_48,4,1,48,F2A_21119,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_47,4,1,47,F2A_21120,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_46,4,1,46,F2A_21121,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_45,4,1,45,F2A_21122,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_44,4,1,44,F2A_21123,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_4,HP_1_3_1N,W20,720,40,1000,6000,FPGA_4_1_43,4,1,43,F2A_21124,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,460,40,1000,4000,FPGA_5_1_23,5,1,23,A2F_21000,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,460,40,1000,4000,FPGA_5_1_22,5,1,22,A2F_21001,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,460,40,1000,4000,FPGA_5_1_21,5,1,21,A2F_21002,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_20,5,1,20,A2F_21003,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_19,5,1,19,A2F_21004,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_18,5,1,18,A2F_21005,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_17,5,1,17,A2F_21006,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_16,5,1,16,A2F_21007,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_15,5,1,15,A2F_21008,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_14,5,1,14,A2F_21009,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_13,5,1,13,A2F_21010,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,980,40,2000,1000,FPGA_5_1_12,5,1,12,A2F_21011,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,980,40,2000,1000,FPGA_5_1_11,5,1,11,A2F_21012,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,980,40,2000,1000,FPGA_5_1_10,5,1,10,A2F_21013,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,70,40,1000,1000,FPGA_5_1_71,5,1,71,F2A_21024,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_70,5,1,70,F2A_21025,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_69,5,1,69,F2A_21026,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_68,5,1,68,F2A_21027,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_67,5,1,67,F2A_21028,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_66,5,1,66,F2A_21029,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_65,5,1,65,F2A_21030,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_64,5,1,64,F2A_21031,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_63,5,1,63,F2A_21032,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,200,40,1000,2000,FPGA_5_1_62,5,1,62,F2A_21033,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,330,40,1000,3000,FPGA_5_1_61,5,1,61,F2A_21034,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,330,40,1000,3000,FPGA_5_1_60,5,1,60,F2A_21035,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,330,40,1000,3000,FPGA_5_1_59,5,1,59,F2A_21036,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,330,40,1000,3000,FPGA_5_1_58,5,1,58,F2A_21037,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_57,5,1,57,F2A_21038,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_56,5,1,56,F2A_21039,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,590,40,1000,5000,FPGA_5_1_55,5,1,55,F2A_21040,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,720,40,1000,6000,FPGA_5_1_54,5,1,54,F2A_21041,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,720,40,1000,6000,FPGA_5_1_53,5,1,53,F2A_21042,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,720,40,1000,6000,FPGA_5_1_52,5,1,52,F2A_21043,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,720,40,1000,6000,FPGA_5_1_51,5,1,51,F2A_21044,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_5,HP_1_4_2P,V16,720,40,1000,6000,FPGA_5_1_50,5,1,50,F2A_21045,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_49,5,1,49,F2A_21046,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_48,5,1,48,F2A_21047,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_47,5,1,47,F2A_21048,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_46,5,1,46,F2A_21049,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_45,5,1,45,F2A_21050,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_44,5,1,44,F2A_21051,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_6,HP_1_5_2N,V17,720,40,1000,6000,FPGA_5_1_43,5,1,43,F2A_21052,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,460,40,1000,4000,FPGA_6_1_23,6,1,23,A2F_20928,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,460,40,1000,4000,FPGA_6_1_22,6,1,22,A2F_20929,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,460,40,1000,4000,FPGA_6_1_21,6,1,21,A2F_20930,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_20,6,1,20,A2F_20931,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_19,6,1,19,A2F_20932,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_18,6,1,18,A2F_20933,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_17,6,1,17,A2F_20934,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_16,6,1,16,A2F_20935,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_15,6,1,15,A2F_20936,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_14,6,1,14,A2F_20937,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_13,6,1,13,A2F_20938,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,980,40,2000,1000,FPGA_6_1_12,6,1,12,A2F_20939,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,980,40,2000,1000,FPGA_6_1_11,6,1,11,A2F_20940,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,980,40,2000,1000,FPGA_6_1_10,6,1,10,A2F_20941,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,70,40,1000,1000,FPGA_6_1_71,6,1,71,F2A_20952,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_70,6,1,70,F2A_20953,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_69,6,1,69,F2A_20954,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_68,6,1,68,F2A_20955,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_67,6,1,67,F2A_20956,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_66,6,1,66,F2A_20957,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_65,6,1,65,F2A_20958,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_64,6,1,64,F2A_20959,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_63,6,1,63,F2A_20960,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,200,40,1000,2000,FPGA_6_1_62,6,1,62,F2A_20961,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,330,40,1000,3000,FPGA_6_1_61,6,1,61,F2A_20962,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,330,40,1000,3000,FPGA_6_1_60,6,1,60,F2A_20963,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,330,40,1000,3000,FPGA_6_1_59,6,1,59,F2A_20964,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,330,40,1000,3000,FPGA_6_1_58,6,1,58,F2A_20965,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_57,6,1,57,F2A_20966,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_56,6,1,56,F2A_20967,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,590,40,1000,5000,FPGA_6_1_55,6,1,55,F2A_20968,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,720,40,1000,6000,FPGA_6_1_54,6,1,54,F2A_20969,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,720,40,1000,6000,FPGA_6_1_53,6,1,53,F2A_20970,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,720,40,1000,6000,FPGA_6_1_52,6,1,52,F2A_20971,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,720,40,1000,6000,FPGA_6_1_51,6,1,51,F2A_20972,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_7,HP_1_6_3P,V18,720,40,1000,6000,FPGA_6_1_50,6,1,50,F2A_20973,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_49,6,1,49,F2A_20974,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_48,6,1,48,F2A_20975,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_47,6,1,47,F2A_20976,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_46,6,1,46,F2A_20977,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_45,6,1,45,F2A_20978,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_44,6,1,44,F2A_20979,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_8,HP_1_7_3N,V19,720,40,1000,6000,FPGA_6_1_43,6,1,43,F2A_20980,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,460,40,1000,4000,FPGA_7_1_23,7,1,23,A2F_20856,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,460,40,1000,4000,FPGA_7_1_22,7,1,22,A2F_20857,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,460,40,1000,4000,FPGA_7_1_21,7,1,21,A2F_20858,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_20,7,1,20,A2F_20859,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_19,7,1,19,A2F_20860,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_18,7,1,18,A2F_20861,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_17,7,1,17,A2F_20862,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_16,7,1,16,A2F_20863,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_15,7,1,15,A2F_20864,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_14,7,1,14,A2F_20865,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_13,7,1,13,A2F_20866,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,980,40,2000,1000,FPGA_7_1_12,7,1,12,A2F_20867,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,980,40,2000,1000,FPGA_7_1_11,7,1,11,A2F_20868,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,980,40,2000,1000,FPGA_7_1_10,7,1,10,A2F_20869,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,70,40,1000,1000,FPGA_7_1_71,7,1,71,F2A_20880,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_70,7,1,70,F2A_20881,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_69,7,1,69,F2A_20882,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_68,7,1,68,F2A_20883,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_67,7,1,67,F2A_20884,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_66,7,1,66,F2A_20885,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_65,7,1,65,F2A_20886,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_64,7,1,64,F2A_20887,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_63,7,1,63,F2A_20888,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,200,40,1000,2000,FPGA_7_1_62,7,1,62,F2A_20889,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,330,40,1000,3000,FPGA_7_1_61,7,1,61,F2A_20890,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,330,40,1000,3000,FPGA_7_1_60,7,1,60,F2A_20891,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,330,40,1000,3000,FPGA_7_1_59,7,1,59,F2A_20892,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,330,40,1000,3000,FPGA_7_1_58,7,1,58,F2A_20893,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_57,7,1,57,F2A_20894,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_56,7,1,56,F2A_20895,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,590,40,1000,5000,FPGA_7_1_55,7,1,55,F2A_20896,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,720,40,1000,6000,FPGA_7_1_54,7,1,54,F2A_20897,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,720,40,1000,6000,FPGA_7_1_53,7,1,53,F2A_20898,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,720,40,1000,6000,FPGA_7_1_52,7,1,52,F2A_20899,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,720,40,1000,6000,FPGA_7_1_51,7,1,51,F2A_20900,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_9,HP_1_8_4P,AB20,720,40,1000,6000,FPGA_7_1_50,7,1,50,F2A_20901,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_49,7,1,49,F2A_20902,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_48,7,1,48,F2A_20903,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_47,7,1,47,F2A_20904,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_46,7,1,46,F2A_20905,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_45,7,1,45,F2A_20906,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_44,7,1,44,F2A_20907,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_10,HP_1_9_4N,AB21,720,40,1000,6000,FPGA_7_1_43,7,1,43,F2A_20908,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,460,40,1000,4000,FPGA_8_1_23,8,1,23,A2F_20784,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,460,40,1000,4000,FPGA_8_1_22,8,1,22,A2F_20785,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,460,40,1000,4000,FPGA_8_1_21,8,1,21,A2F_20786,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_20,8,1,20,A2F_20787,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_19,8,1,19,A2F_20788,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_18,8,1,18,A2F_20789,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_17,8,1,17,A2F_20790,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_16,8,1,16,A2F_20791,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_15,8,1,15,A2F_20792,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_14,8,1,14,A2F_20793,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_13,8,1,13,A2F_20794,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,980,40,2000,1000,FPGA_8_1_12,8,1,12,A2F_20795,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,980,40,2000,1000,FPGA_8_1_11,8,1,11,A2F_20796,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,980,40,2000,1000,FPGA_8_1_10,8,1,10,A2F_20797,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,70,40,1000,1000,FPGA_8_1_71,8,1,71,F2A_20808,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_70,8,1,70,F2A_20809,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_69,8,1,69,F2A_20810,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_68,8,1,68,F2A_20811,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_67,8,1,67,F2A_20812,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_66,8,1,66,F2A_20813,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_65,8,1,65,F2A_20814,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_64,8,1,64,F2A_20815,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_63,8,1,63,F2A_20816,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,200,40,1000,2000,FPGA_8_1_62,8,1,62,F2A_20817,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,330,40,1000,3000,FPGA_8_1_61,8,1,61,F2A_20818,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,330,40,1000,3000,FPGA_8_1_60,8,1,60,F2A_20819,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,330,40,1000,3000,FPGA_8_1_59,8,1,59,F2A_20820,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,330,40,1000,3000,FPGA_8_1_58,8,1,58,F2A_20821,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_57,8,1,57,F2A_20822,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_56,8,1,56,F2A_20823,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,590,40,1000,5000,FPGA_8_1_55,8,1,55,F2A_20824,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,720,40,1000,6000,FPGA_8_1_54,8,1,54,F2A_20825,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,720,40,1000,6000,FPGA_8_1_53,8,1,53,F2A_20826,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,720,40,1000,6000,FPGA_8_1_52,8,1,52,F2A_20827,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,720,40,1000,6000,FPGA_8_1_51,8,1,51,F2A_20828,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_11,HP_1_10_5P,Y20,720,40,1000,6000,FPGA_8_1_50,8,1,50,F2A_20829,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_49,8,1,49,F2A_20830,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_48,8,1,48,F2A_20831,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_47,8,1,47,F2A_20832,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_46,8,1,46,F2A_20833,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_45,8,1,45,F2A_20834,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_44,8,1,44,F2A_20835,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_12,HP_1_11_5N,Y21,720,40,1000,6000,FPGA_8_1_43,8,1,43,F2A_20836,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,460,40,1000,4000,FPGA_9_1_23,9,1,23,A2F_20712,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,460,40,1000,4000,FPGA_9_1_22,9,1,22,A2F_20713,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,460,40,1000,4000,FPGA_9_1_21,9,1,21,A2F_20714,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_20,9,1,20,A2F_20715,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_19,9,1,19,A2F_20716,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_18,9,1,18,A2F_20717,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_17,9,1,17,A2F_20718,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_16,9,1,16,A2F_20719,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_15,9,1,15,A2F_20720,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_14,9,1,14,A2F_20721,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_13,9,1,13,A2F_20722,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,980,40,2000,1000,FPGA_9_1_12,9,1,12,A2F_20723,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,980,40,2000,1000,FPGA_9_1_11,9,1,11,A2F_20724,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,980,40,2000,1000,FPGA_9_1_10,9,1,10,A2F_20725,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,70,40,1000,1000,FPGA_9_1_71,9,1,71,F2A_20736,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_70,9,1,70,F2A_20737,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_69,9,1,69,F2A_20738,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_68,9,1,68,F2A_20739,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_67,9,1,67,F2A_20740,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_66,9,1,66,F2A_20741,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_65,9,1,65,F2A_20742,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_64,9,1,64,F2A_20743,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_63,9,1,63,F2A_20744,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,200,40,1000,2000,FPGA_9_1_62,9,1,62,F2A_20745,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,330,40,1000,3000,FPGA_9_1_61,9,1,61,F2A_20746,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,330,40,1000,3000,FPGA_9_1_60,9,1,60,F2A_20747,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,330,40,1000,3000,FPGA_9_1_59,9,1,59,F2A_20748,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,330,40,1000,3000,FPGA_9_1_58,9,1,58,F2A_20749,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_57,9,1,57,F2A_20750,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_56,9,1,56,F2A_20751,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,590,40,1000,5000,FPGA_9_1_55,9,1,55,F2A_20752,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,720,40,1000,6000,FPGA_9_1_54,9,1,54,F2A_20753,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,720,40,1000,6000,FPGA_9_1_53,9,1,53,F2A_20754,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,720,40,1000,6000,FPGA_9_1_52,9,1,52,F2A_20755,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,720,40,1000,6000,FPGA_9_1_51,9,1,51,F2A_20756,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_13,HP_1_12_6P,W17,720,40,1000,6000,FPGA_9_1_50,9,1,50,F2A_20757,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_49,9,1,49,F2A_20758,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_48,9,1,48,F2A_20759,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_47,9,1,47,F2A_20760,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_46,9,1,46,F2A_20761,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_45,9,1,45,F2A_20762,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_44,9,1,44,F2A_20763,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_14,HP_1_13_6N,W16,720,40,1000,6000,FPGA_9_1_43,9,1,43,F2A_20764,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,460,40,1000,4000,FPGA_10_1_23,10,1,23,A2F_20640,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,460,40,1000,4000,FPGA_10_1_22,10,1,22,A2F_20641,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,460,40,1000,4000,FPGA_10_1_21,10,1,21,A2F_20642,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_20,10,1,20,A2F_20643,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_19,10,1,19,A2F_20644,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_18,10,1,18,A2F_20645,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_17,10,1,17,A2F_20646,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_16,10,1,16,A2F_20647,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_15,10,1,15,A2F_20648,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_14,10,1,14,A2F_20649,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_13,10,1,13,A2F_20650,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,980,40,2000,1000,FPGA_10_1_12,10,1,12,A2F_20651,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,980,40,2000,1000,FPGA_10_1_11,10,1,11,A2F_20652,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,980,40,2000,1000,FPGA_10_1_10,10,1,10,A2F_20653,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,70,40,1000,1000,FPGA_10_1_71,10,1,71,F2A_20664,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_70,10,1,70,F2A_20665,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_69,10,1,69,F2A_20666,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_68,10,1,68,F2A_20667,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_67,10,1,67,F2A_20668,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_66,10,1,66,F2A_20669,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_65,10,1,65,F2A_20670,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_64,10,1,64,F2A_20671,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_63,10,1,63,F2A_20672,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,200,40,1000,2000,FPGA_10_1_62,10,1,62,F2A_20673,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,330,40,1000,3000,FPGA_10_1_61,10,1,61,F2A_20674,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,330,40,1000,3000,FPGA_10_1_60,10,1,60,F2A_20675,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,330,40,1000,3000,FPGA_10_1_59,10,1,59,F2A_20676,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,330,40,1000,3000,FPGA_10_1_58,10,1,58,F2A_20677,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_57,10,1,57,F2A_20678,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_56,10,1,56,F2A_20679,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,590,40,1000,5000,FPGA_10_1_55,10,1,55,F2A_20680,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,720,40,1000,6000,FPGA_10_1_54,10,1,54,F2A_20681,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,720,40,1000,6000,FPGA_10_1_53,10,1,53,F2A_20682,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,720,40,1000,6000,FPGA_10_1_52,10,1,52,F2A_20683,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,720,40,1000,6000,FPGA_10_1_51,10,1,51,F2A_20684,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_15,HP_1_14_7P,V15,720,40,1000,6000,FPGA_10_1_50,10,1,50,F2A_20685,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_49,10,1,49,F2A_20686,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_48,10,1,48,F2A_20687,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_47,10,1,47,F2A_20688,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_46,10,1,46,F2A_20689,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_45,10,1,45,F2A_20690,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_44,10,1,44,F2A_20691,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_16,HP_1_15_7N,W15,720,40,1000,6000,FPGA_10_1_43,10,1,43,F2A_20692,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,460,40,1000,4000,FPGA_11_1_23,11,1,23,A2F_20568,g2f_rx_dvalid_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,460,40,1000,4000,FPGA_11_1_22,11,1,22,A2F_20569,g2f_rx_in[0]_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,460,40,1000,4000,FPGA_11_1_21,11,1,21,A2F_20570,g2f_rx_in[1]_A,Y,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_20,11,1,20,A2F_20571,g2f_rx_in[2]_A,Y,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_19,11,1,19,A2F_20572,g2f_rx_in[3]_A,Y,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_18,11,1,18,A2F_20573,g2f_rx_in[4]_A,Y,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_17,11,1,17,A2F_20574,g2f_rx_in[5]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_16,11,1,16,A2F_20575,g2f_rx_in[6]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_15,11,1,15,A2F_20576,g2f_rx_in[7]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_14,11,1,14,A2F_20577,g2f_rx_in[8]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_13,11,1,13,A2F_20578,g2f_rx_in[9]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,980,40,2000,1000,FPGA_11_1_12,11,1,12,A2F_20579,g2f_rx_lp_dp,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,980,40,2000,1000,FPGA_11_1_11,11,1,11,A2F_20580,g2f_rx_lp_dn,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,980,40,2000,1000,FPGA_11_1_10,11,1,10,A2F_20581,g2f_rx_dvalid_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,70,40,1000,1000,FPGA_11_1_71,11,1,71,F2A_20592,f2g_rx_sfifo_reset_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_70,11,1,70,F2A_20593,f2g_rx_dpa_restart_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_69,11,1,69,F2A_20594,f2g_trx_reset_n_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_68,11,1,68,F2A_20595,f2g_in_en_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_67,11,1,67,F2A_20596,f2g_tx_oe_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_66,11,1,66,F2A_20597,f2g_tx_dvalid_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_65,11,1,65,F2A_20598,f2g_tx_out[0]_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_64,11,1,64,F2A_20599,f2g_tx_out[1]_A,Y,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_63,11,1,63,F2A_20600,f2g_tx_out[2]_A,Y,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,200,40,1000,2000,FPGA_11_1_62,11,1,62,F2A_20601,f2g_tx_out[3]_A,Y,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,330,40,1000,3000,FPGA_11_1_61,11,1,61,F2A_20602,f2g_tx_out[4]_A,Y,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,330,40,1000,3000,FPGA_11_1_60,11,1,60,F2A_20603,f2g_tx_out[5]_A,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,330,40,1000,3000,FPGA_11_1_59,11,1,59,F2A_20604,f2g_tx_out[6]_A,Y,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,330,40,1000,3000,FPGA_11_1_58,11,1,58,F2A_20605,f2g_tx_out[7]_A,Y,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_57,11,1,57,F2A_20606,f2g_tx_out[8]_A,Y,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_56,11,1,56,F2A_20607,f2g_tx_out[9]_A,Y,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,590,40,1000,5000,FPGA_11_1_55,11,1,55,F2A_20608,f2g_tx_clk_en_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,720,40,1000,6000,FPGA_11_1_54,11,1,54,F2A_20609,f2g_trx_hs_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,720,40,1000,6000,FPGA_11_1_53,11,1,53,F2A_20610,f2g_trx_lp_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,720,40,1000,6000,FPGA_11_1_52,11,1,52,F2A_20611,f2g_tx_lp_dp,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,720,40,1000,6000,FPGA_11_1_51,11,1,51,F2A_20612,f2g_tx_lp_dn,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_19,HP_1_CC_18_9P,Y19,720,40,1000,6000,FPGA_11_1_50,11,1,50,F2A_20613,f2g_rx_term_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_49,11,1,49,F2A_20614,f2g_rx_sfifo_reset_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_48,11,1,48,F2A_20615,f2g_rx_dpa_restart_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_47,11,1,47,F2A_20616,f2g_trx_reset_n_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_46,11,1,46,F2A_20617,f2g_in_en_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_45,11,1,45,F2A_20618,f2g_tx_oe_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_44,11,1,44,F2A_20619,f2g_tx_dvalid_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_20,HP_1_CC_19_9N,AA19,720,40,1000,6000,FPGA_11_1_43,11,1,43,F2A_20620,f2g_tx_clk_en_B,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_23,12,1,23,A2F_20496,g2f_trx_dly_tap[0],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_22,12,1,22,A2F_20497,g2f_trx_dly_tap[1],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_21,12,1,21,A2F_20498,g2f_trx_dly_tap[2],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_20,12,1,20,A2F_20499,g2f_trx_dly_tap[3],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_19,12,1,19,A2F_20500,g2f_trx_dly_tap[4],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_12_1_18,12,1,18,A2F_20501,g2f_trx_dly_tap[5],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_12_1_17,12,1,17,A2F_20502,g2f_rx_dpa_lock,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_12_1_16,12,1,16,A2F_20503,g2f_rx_dpa_error,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_12_1_15,12,1,15,A2F_20504,g2f_rx_dpa_phase[0],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_12_1_14,12,1,14,A2F_20505,g2f_rx_dpa_phase[1],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_12_1_13,12,1,13,A2F_20506,g2f_rx_dpa_phase[2],,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_71,12,1,71,F2A_20520,f2g_addr[0],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_70,12,1,70,F2A_20521,f2g_addr[1],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_69,12,1,69,F2A_20522,f2g_addr[2],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_68,12,1,68,F2A_20523,f2g_addr[3],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_67,12,1,67,F2A_20524,f2g_addr[4],,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_66,12,1,66,F2A_20525,f2g_trx_dly_ld,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_65,12,1,65,F2A_20526,f2g_trx_dly_adj,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_64,12,1,64,F2A_20527,f2g_trx_dly_inc,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_12_1_63,12,1,63,F2A_20528,f2g_rx_bitslip_adj,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_13_1_23,13,1,23,A2F_20424,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_13_1_22,13,1,22,A2F_20425,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,460,40,1000,4000,FPGA_13_1_21,13,1,21,A2F_20426,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_20,13,1,20,A2F_20427,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_19,13,1,19,A2F_20428,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_18,13,1,18,A2F_20429,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_17,13,1,17,A2F_20430,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_16,13,1,16,A2F_20431,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_15,13,1,15,A2F_20432,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_14,13,1,14,A2F_20433,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_13,13,1,13,A2F_20434,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,980,40,2000,1000,FPGA_13_1_12,13,1,12,A2F_20435,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,980,40,2000,1000,FPGA_13_1_11,13,1,11,A2F_20436,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,980,40,2000,1000,FPGA_13_1_10,13,1,10,A2F_20437,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,70,40,1000,1000,FPGA_13_1_71,13,1,71,F2A_20448,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_70,13,1,70,F2A_20449,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_69,13,1,69,F2A_20450,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_68,13,1,68,F2A_20451,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_67,13,1,67,F2A_20452,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_66,13,1,66,F2A_20453,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_65,13,1,65,F2A_20454,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_64,13,1,64,F2A_20455,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_63,13,1,63,F2A_20456,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,200,40,1000,2000,FPGA_13_1_62,13,1,62,F2A_20457,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_13_1_61,13,1,61,F2A_20458,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_13_1_60,13,1,60,F2A_20459,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_13_1_59,13,1,59,F2A_20460,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,330,40,1000,3000,FPGA_13_1_58,13,1,58,F2A_20461,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_57,13,1,57,F2A_20462,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_56,13,1,56,F2A_20463,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,590,40,1000,5000,FPGA_13_1_55,13,1,55,F2A_20464,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,720,40,1000,6000,FPGA_13_1_54,13,1,54,F2A_20465,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,720,40,1000,6000,FPGA_13_1_53,13,1,53,F2A_20466,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,720,40,1000,6000,FPGA_13_1_52,13,1,52,F2A_20467,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,720,40,1000,6000,FPGA_13_1_51,13,1,51,F2A_20468,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_21,HP_1_20_10P,AA17,720,40,1000,6000,FPGA_13_1_50,13,1,50,F2A_20469,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_49,13,1,49,F2A_20470,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_48,13,1,48,F2A_20471,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_47,13,1,47,F2A_20472,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_46,13,1,46,F2A_20473,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_45,13,1,45,F2A_20474,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_44,13,1,44,F2A_20475,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_22,HP_1_21_10N,AA18,720,40,1000,6000,FPGA_13_1_43,13,1,43,F2A_20476,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,460,40,1000,4000,FPGA_14_1_23,14,1,23,A2F_20352,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,460,40,1000,4000,FPGA_14_1_22,14,1,22,A2F_20353,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,460,40,1000,4000,FPGA_14_1_21,14,1,21,A2F_20354,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_20,14,1,20,A2F_20355,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_19,14,1,19,A2F_20356,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_18,14,1,18,A2F_20357,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_17,14,1,17,A2F_20358,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_16,14,1,16,A2F_20359,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_15,14,1,15,A2F_20360,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_14,14,1,14,A2F_20361,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_13,14,1,13,A2F_20362,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,980,40,2000,1000,FPGA_14_1_12,14,1,12,A2F_20363,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,980,40,2000,1000,FPGA_14_1_11,14,1,11,A2F_20364,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,980,40,2000,1000,FPGA_14_1_10,14,1,10,A2F_20365,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,70,40,1000,1000,FPGA_14_1_71,14,1,71,F2A_20376,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_70,14,1,70,F2A_20377,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_69,14,1,69,F2A_20378,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_68,14,1,68,F2A_20379,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_67,14,1,67,F2A_20380,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_66,14,1,66,F2A_20381,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_65,14,1,65,F2A_20382,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_64,14,1,64,F2A_20383,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_63,14,1,63,F2A_20384,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,200,40,1000,2000,FPGA_14_1_62,14,1,62,F2A_20385,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,330,40,1000,3000,FPGA_14_1_61,14,1,61,F2A_20386,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,330,40,1000,3000,FPGA_14_1_60,14,1,60,F2A_20387,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,330,40,1000,3000,FPGA_14_1_59,14,1,59,F2A_20388,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,330,40,1000,3000,FPGA_14_1_58,14,1,58,F2A_20389,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_57,14,1,57,F2A_20390,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_56,14,1,56,F2A_20391,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,590,40,1000,5000,FPGA_14_1_55,14,1,55,F2A_20392,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,720,40,1000,6000,FPGA_14_1_54,14,1,54,F2A_20393,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,720,40,1000,6000,FPGA_14_1_53,14,1,53,F2A_20394,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,720,40,1000,6000,FPGA_14_1_52,14,1,52,F2A_20395,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,720,40,1000,6000,FPGA_14_1_51,14,1,51,F2A_20396,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_23,HP_1_22_11P,AB18,720,40,1000,6000,FPGA_14_1_50,14,1,50,F2A_20397,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_49,14,1,49,F2A_20398,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_48,14,1,48,F2A_20399,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_47,14,1,47,F2A_20400,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_46,14,1,46,F2A_20401,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_45,14,1,45,F2A_20402,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_44,14,1,44,F2A_20403,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_24,HP_1_23_11N,AB17,720,40,1000,6000,FPGA_14_1_43,14,1,43,F2A_20404,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,460,40,1000,4000,FPGA_15_1_23,15,1,23,A2F_20280,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,460,40,1000,4000,FPGA_15_1_22,15,1,22,A2F_20281,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,460,40,1000,4000,FPGA_15_1_21,15,1,21,A2F_20282,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_20,15,1,20,A2F_20283,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_19,15,1,19,A2F_20284,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_18,15,1,18,A2F_20285,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_17,15,1,17,A2F_20286,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_16,15,1,16,A2F_20287,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_15,15,1,15,A2F_20288,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_14,15,1,14,A2F_20289,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_13,15,1,13,A2F_20290,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,980,40,2000,1000,FPGA_15_1_12,15,1,12,A2F_20291,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,980,40,2000,1000,FPGA_15_1_11,15,1,11,A2F_20292,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,980,40,2000,1000,FPGA_15_1_10,15,1,10,A2F_20293,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,70,40,1000,1000,FPGA_15_1_71,15,1,71,F2A_20304,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_70,15,1,70,F2A_20305,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_69,15,1,69,F2A_20306,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_68,15,1,68,F2A_20307,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_67,15,1,67,F2A_20308,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_66,15,1,66,F2A_20309,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_65,15,1,65,F2A_20310,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_64,15,1,64,F2A_20311,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_63,15,1,63,F2A_20312,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,200,40,1000,2000,FPGA_15_1_62,15,1,62,F2A_20313,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,330,40,1000,3000,FPGA_15_1_61,15,1,61,F2A_20314,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,330,40,1000,3000,FPGA_15_1_60,15,1,60,F2A_20315,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,330,40,1000,3000,FPGA_15_1_59,15,1,59,F2A_20316,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,330,40,1000,3000,FPGA_15_1_58,15,1,58,F2A_20317,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_57,15,1,57,F2A_20318,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_56,15,1,56,F2A_20319,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,590,40,1000,5000,FPGA_15_1_55,15,1,55,F2A_20320,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,720,40,1000,6000,FPGA_15_1_54,15,1,54,F2A_20321,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,720,40,1000,6000,FPGA_15_1_53,15,1,53,F2A_20322,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,720,40,1000,6000,FPGA_15_1_52,15,1,52,F2A_20323,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,720,40,1000,6000,FPGA_15_1_51,15,1,51,F2A_20324,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_25,HP_1_24_12P,Y16,720,40,1000,6000,FPGA_15_1_50,15,1,50,F2A_20325,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_49,15,1,49,F2A_20326,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_48,15,1,48,F2A_20327,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_47,15,1,47,F2A_20328,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_46,15,1,46,F2A_20329,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_45,15,1,45,F2A_20330,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_44,15,1,44,F2A_20331,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_26,HP_1_25_12N,Y15,720,40,1000,6000,FPGA_15_1_43,15,1,43,F2A_20332,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,460,40,1000,4000,FPGA_16_1_23,16,1,23,A2F_20208,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,460,40,1000,4000,FPGA_16_1_22,16,1,22,A2F_20209,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,460,40,1000,4000,FPGA_16_1_21,16,1,21,A2F_20210,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_20,16,1,20,A2F_20211,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_19,16,1,19,A2F_20212,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_18,16,1,18,A2F_20213,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_17,16,1,17,A2F_20214,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_16,16,1,16,A2F_20215,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_15,16,1,15,A2F_20216,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_14,16,1,14,A2F_20217,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_13,16,1,13,A2F_20218,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,980,40,2000,1000,FPGA_16_1_12,16,1,12,A2F_20219,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,980,40,2000,1000,FPGA_16_1_11,16,1,11,A2F_20220,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,980,40,2000,1000,FPGA_16_1_10,16,1,10,A2F_20221,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,70,40,1000,1000,FPGA_16_1_71,16,1,71,F2A_20232,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_70,16,1,70,F2A_20233,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_69,16,1,69,F2A_20234,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_68,16,1,68,F2A_20235,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_67,16,1,67,F2A_20236,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_66,16,1,66,F2A_20237,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_65,16,1,65,F2A_20238,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_64,16,1,64,F2A_20239,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_63,16,1,63,F2A_20240,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,200,40,1000,2000,FPGA_16_1_62,16,1,62,F2A_20241,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,330,40,1000,3000,FPGA_16_1_61,16,1,61,F2A_20242,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,330,40,1000,3000,FPGA_16_1_60,16,1,60,F2A_20243,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,330,40,1000,3000,FPGA_16_1_59,16,1,59,F2A_20244,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,330,40,1000,3000,FPGA_16_1_58,16,1,58,F2A_20245,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_57,16,1,57,F2A_20246,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_56,16,1,56,F2A_20247,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,590,40,1000,5000,FPGA_16_1_55,16,1,55,F2A_20248,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,720,40,1000,6000,FPGA_16_1_54,16,1,54,F2A_20249,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,720,40,1000,6000,FPGA_16_1_53,16,1,53,F2A_20250,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,720,40,1000,6000,FPGA_16_1_52,16,1,52,F2A_20251,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,720,40,1000,6000,FPGA_16_1_51,16,1,51,F2A_20252,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_27,HP_1_26_13P,V14,720,40,1000,6000,FPGA_16_1_50,16,1,50,F2A_20253,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_49,16,1,49,F2A_20254,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_48,16,1,48,F2A_20255,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_47,16,1,47,F2A_20256,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_46,16,1,46,F2A_20257,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_45,16,1,45,F2A_20258,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_44,16,1,44,F2A_20259,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_28,HP_1_27_13N,W14,720,40,1000,6000,FPGA_16_1_43,16,1,43,F2A_20260,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,460,40,1000,4000,FPGA_17_1_23,17,1,23,A2F_20136,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,460,40,1000,4000,FPGA_17_1_22,17,1,22,A2F_20137,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,460,40,1000,4000,FPGA_17_1_21,17,1,21,A2F_20138,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_20,17,1,20,A2F_20139,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_19,17,1,19,A2F_20140,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_18,17,1,18,A2F_20141,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_17,17,1,17,A2F_20142,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_16,17,1,16,A2F_20143,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_15,17,1,15,A2F_20144,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_14,17,1,14,A2F_20145,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_13,17,1,13,A2F_20146,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,980,40,2000,1000,FPGA_17_1_12,17,1,12,A2F_20147,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,980,40,2000,1000,FPGA_17_1_11,17,1,11,A2F_20148,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,980,40,2000,1000,FPGA_17_1_10,17,1,10,A2F_20149,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,70,40,1000,1000,FPGA_17_1_71,17,1,71,F2A_20160,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_70,17,1,70,F2A_20161,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_69,17,1,69,F2A_20162,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_68,17,1,68,F2A_20163,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_67,17,1,67,F2A_20164,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_66,17,1,66,F2A_20165,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_65,17,1,65,F2A_20166,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_64,17,1,64,F2A_20167,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_63,17,1,63,F2A_20168,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,200,40,1000,2000,FPGA_17_1_62,17,1,62,F2A_20169,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,330,40,1000,3000,FPGA_17_1_61,17,1,61,F2A_20170,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,330,40,1000,3000,FPGA_17_1_60,17,1,60,F2A_20171,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,330,40,1000,3000,FPGA_17_1_59,17,1,59,F2A_20172,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,330,40,1000,3000,FPGA_17_1_58,17,1,58,F2A_20173,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_57,17,1,57,F2A_20174,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_56,17,1,56,F2A_20175,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,590,40,1000,5000,FPGA_17_1_55,17,1,55,F2A_20176,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,720,40,1000,6000,FPGA_17_1_54,17,1,54,F2A_20177,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,720,40,1000,6000,FPGA_17_1_53,17,1,53,F2A_20178,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,720,40,1000,6000,FPGA_17_1_52,17,1,52,F2A_20179,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,720,40,1000,6000,FPGA_17_1_51,17,1,51,F2A_20180,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_29,HP_1_28_14P,AB14,720,40,1000,6000,FPGA_17_1_50,17,1,50,F2A_20181,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_49,17,1,49,F2A_20182,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_48,17,1,48,F2A_20183,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_47,17,1,47,F2A_20184,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_46,17,1,46,F2A_20185,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_45,17,1,45,F2A_20186,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_44,17,1,44,F2A_20187,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_30,HP_1_29_14N,AB15,720,40,1000,6000,FPGA_17_1_43,17,1,43,F2A_20188,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,460,40,1000,4000,FPGA_18_1_23,18,1,23,A2F_20064,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,460,40,1000,4000,FPGA_18_1_22,18,1,22,A2F_20065,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,460,40,1000,4000,FPGA_18_1_21,18,1,21,A2F_20066,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_20,18,1,20,A2F_20067,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_19,18,1,19,A2F_20068,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_18,18,1,18,A2F_20069,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_17,18,1,17,A2F_20070,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_16,18,1,16,A2F_20071,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_15,18,1,15,A2F_20072,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_14,18,1,14,A2F_20073,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_13,18,1,13,A2F_20074,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,980,40,2000,1000,FPGA_18_1_12,18,1,12,A2F_20075,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,980,40,2000,1000,FPGA_18_1_11,18,1,11,A2F_20076,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,980,40,2000,1000,FPGA_18_1_10,18,1,10,A2F_20077,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,70,40,1000,1000,FPGA_18_1_71,18,1,71,F2A_20088,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_70,18,1,70,F2A_20089,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_69,18,1,69,F2A_20090,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_68,18,1,68,F2A_20091,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_67,18,1,67,F2A_20092,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_66,18,1,66,F2A_20093,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_65,18,1,65,F2A_20094,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_64,18,1,64,F2A_20095,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_63,18,1,63,F2A_20096,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,200,40,1000,2000,FPGA_18_1_62,18,1,62,F2A_20097,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,330,40,1000,3000,FPGA_18_1_61,18,1,61,F2A_20098,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,330,40,1000,3000,FPGA_18_1_60,18,1,60,F2A_20099,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,330,40,1000,3000,FPGA_18_1_59,18,1,59,F2A_20100,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,330,40,1000,3000,FPGA_18_1_58,18,1,58,F2A_20101,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_57,18,1,57,F2A_20102,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_56,18,1,56,F2A_20103,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,590,40,1000,5000,FPGA_18_1_55,18,1,55,F2A_20104,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,720,40,1000,6000,FPGA_18_1_54,18,1,54,F2A_20105,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,720,40,1000,6000,FPGA_18_1_53,18,1,53,F2A_20106,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,720,40,1000,6000,FPGA_18_1_52,18,1,52,F2A_20107,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,720,40,1000,6000,FPGA_18_1_51,18,1,51,F2A_20108,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_31,HP_1_30_15P,Y14,720,40,1000,6000,FPGA_18_1_50,18,1,50,F2A_20109,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_49,18,1,49,F2A_20110,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_48,18,1,48,F2A_20111,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_47,18,1,47,F2A_20112,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_46,18,1,46,F2A_20113,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_45,18,1,45,F2A_20114,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_44,18,1,44,F2A_20115,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_32,HP_1_31_15N,AA14,720,40,1000,6000,FPGA_18_1_43,18,1,43,F2A_20116,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,460,40,1000,4000,FPGA_19_1_23,19,1,23,A2F_19992,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,460,40,1000,4000,FPGA_19_1_22,19,1,22,A2F_19993,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,460,40,1000,4000,FPGA_19_1_21,19,1,21,A2F_19994,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_20,19,1,20,A2F_19995,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_19,19,1,19,A2F_19996,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_18,19,1,18,A2F_19997,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_17,19,1,17,A2F_19998,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_16,19,1,16,A2F_19999,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_15,19,1,15,A2F_20000,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_14,19,1,14,A2F_20001,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_13,19,1,13,A2F_20002,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,980,40,2000,1000,FPGA_19_1_12,19,1,12,A2F_20003,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,980,40,2000,1000,FPGA_19_1_11,19,1,11,A2F_20004,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,980,40,2000,1000,FPGA_19_1_10,19,1,10,A2F_20005,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,70,40,1000,1000,FPGA_19_1_71,19,1,71,F2A_20016,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_70,19,1,70,F2A_20017,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_69,19,1,69,F2A_20018,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_68,19,1,68,F2A_20019,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_67,19,1,67,F2A_20020,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_66,19,1,66,F2A_20021,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_65,19,1,65,F2A_20022,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_64,19,1,64,F2A_20023,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_63,19,1,63,F2A_20024,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,200,40,1000,2000,FPGA_19_1_62,19,1,62,F2A_20025,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,330,40,1000,3000,FPGA_19_1_61,19,1,61,F2A_20026,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,330,40,1000,3000,FPGA_19_1_60,19,1,60,F2A_20027,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,330,40,1000,3000,FPGA_19_1_59,19,1,59,F2A_20028,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,330,40,1000,3000,FPGA_19_1_58,19,1,58,F2A_20029,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_57,19,1,57,F2A_20030,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_56,19,1,56,F2A_20031,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,590,40,1000,5000,FPGA_19_1_55,19,1,55,F2A_20032,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,720,40,1000,6000,FPGA_19_1_54,19,1,54,F2A_20033,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,720,40,1000,6000,FPGA_19_1_53,19,1,53,F2A_20034,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,720,40,1000,6000,FPGA_19_1_52,19,1,52,F2A_20035,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,720,40,1000,6000,FPGA_19_1_51,19,1,51,F2A_20036,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_33,HP_1_32_16P,AB12,720,40,1000,6000,FPGA_19_1_50,19,1,50,F2A_20037,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_49,19,1,49,F2A_20038,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_48,19,1,48,F2A_20039,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_47,19,1,47,F2A_20040,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_46,19,1,46,F2A_20041,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_45,19,1,45,F2A_20042,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_44,19,1,44,F2A_20043,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_34,HP_1_33_16N,AA12,720,40,1000,6000,FPGA_19_1_43,19,1,43,F2A_20044,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,460,40,1000,4000,FPGA_20_1_23,20,1,23,A2F_19920,g2f_rx_dvalid_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,460,40,1000,4000,FPGA_20_1_22,20,1,22,A2F_19921,g2f_rx_in[0]_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,460,40,1000,4000,FPGA_20_1_21,20,1,21,A2F_19922,g2f_rx_in[1]_A,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_20,20,1,20,A2F_19923,g2f_rx_in[2]_A,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_19,20,1,19,A2F_19924,g2f_rx_in[3]_A,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_18,20,1,18,A2F_19925,g2f_rx_in[4]_A,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_17,20,1,17,A2F_19926,g2f_rx_in[5]_A,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_16,20,1,16,A2F_19927,g2f_rx_in[6]_A,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_15,20,1,15,A2F_19928,g2f_rx_in[7]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_14,20,1,14,A2F_19929,g2f_rx_in[8]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_13,20,1,13,A2F_19930,g2f_rx_in[9]_A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,980,40,2000,1000,FPGA_20_1_12,20,1,12,A2F_19931,g2f_rx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,980,40,2000,1000,FPGA_20_1_11,20,1,11,A2F_19932,g2f_rx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,980,40,2000,1000,FPGA_20_1_10,20,1,10,A2F_19933,g2f_rx_dvalid_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,70,40,1000,1000,FPGA_20_1_71,20,1,71,F2A_19944,f2g_rx_sfifo_reset_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_70,20,1,70,F2A_19945,f2g_rx_dpa_restart_A,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_69,20,1,69,F2A_19946,f2g_trx_reset_n_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_68,20,1,68,F2A_19947,f2g_in_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_67,20,1,67,F2A_19948,f2g_tx_oe_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_66,20,1,66,F2A_19949,f2g_tx_dvalid_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_65,20,1,65,F2A_19950,f2g_tx_out[0]_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_64,20,1,64,F2A_19951,f2g_tx_out[1]_A,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_63,20,1,63,F2A_19952,f2g_tx_out[2]_A,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,200,40,1000,2000,FPGA_20_1_62,20,1,62,F2A_19953,f2g_tx_out[3]_A,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,330,40,1000,3000,FPGA_20_1_61,20,1,61,F2A_19954,f2g_tx_out[4]_A,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,330,40,1000,3000,FPGA_20_1_60,20,1,60,F2A_19955,f2g_tx_out[5]_A,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,330,40,1000,3000,FPGA_20_1_59,20,1,59,F2A_19956,f2g_tx_out[6]_A,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,330,40,1000,3000,FPGA_20_1_58,20,1,58,F2A_19957,f2g_tx_out[7]_A,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_57,20,1,57,F2A_19958,f2g_tx_out[8]_A,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_56,20,1,56,F2A_19959,f2g_tx_out[9]_A,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,590,40,1000,5000,FPGA_20_1_55,20,1,55,F2A_19960,f2g_tx_clk_en_A,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,720,40,1000,6000,FPGA_20_1_54,20,1,54,F2A_19961,f2g_trx_hs_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,720,40,1000,6000,FPGA_20_1_53,20,1,53,F2A_19962,f2g_trx_lp_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,720,40,1000,6000,FPGA_20_1_52,20,1,52,F2A_19963,f2g_tx_lp_dp,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,720,40,1000,6000,FPGA_20_1_51,20,1,51,F2A_19964,f2g_tx_lp_dn,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_35,HP_1_34_17P,Y13,720,40,1000,6000,FPGA_20_1_50,20,1,50,F2A_19965,f2g_rx_term_en,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_49,20,1,49,F2A_19966,f2g_rx_sfifo_reset_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_48,20,1,48,F2A_19967,f2g_rx_dpa_restart_B,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_47,20,1,47,F2A_19968,f2g_trx_reset_n_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_46,20,1,46,F2A_19969,f2g_in_en_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_45,20,1,45,F2A_19970,f2g_tx_oe_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_44,20,1,44,F2A_19971,f2g_tx_dvalid_B,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_36,HP_1_35_17N,AA13,720,40,1000,6000,FPGA_20_1_43,20,1,43,F2A_19972,f2g_tx_clk_en_B,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,460,40,1000,4000,FPGA_21_1_23,21,1,23,A2F_19848,g2f_rx_dvalid_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,460,40,1000,4000,FPGA_21_1_22,21,1,22,A2F_19849,g2f_rx_in[0]_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,460,40,1000,4000,FPGA_21_1_21,21,1,21,A2F_19850,g2f_rx_in[1]_A,Y,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_20,21,1,20,A2F_19851,g2f_rx_in[2]_A,Y,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_19,21,1,19,A2F_19852,g2f_rx_in[3]_A,Y,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_18,21,1,18,A2F_19853,g2f_rx_in[4]_A,Y,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_17,21,1,17,A2F_19854,g2f_rx_in[5]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_16,21,1,16,A2F_19855,g2f_rx_in[6]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_15,21,1,15,A2F_19856,g2f_rx_in[7]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_14,21,1,14,A2F_19857,g2f_rx_in[8]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_13,21,1,13,A2F_19858,g2f_rx_in[9]_A,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,980,40,2000,1000,FPGA_21_1_12,21,1,12,A2F_19859,g2f_rx_lp_dp,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,980,40,2000,1000,FPGA_21_1_11,21,1,11,A2F_19860,g2f_rx_lp_dn,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,980,40,2000,1000,FPGA_21_1_10,21,1,10,A2F_19861,g2f_rx_dvalid_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,70,40,1000,1000,FPGA_21_1_71,21,1,71,F2A_19872,f2g_rx_sfifo_reset_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_70,21,1,70,F2A_19873,f2g_rx_dpa_restart_A,Y,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_69,21,1,69,F2A_19874,f2g_trx_reset_n_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_68,21,1,68,F2A_19875,f2g_in_en_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_67,21,1,67,F2A_19876,f2g_tx_oe_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_66,21,1,66,F2A_19877,f2g_tx_dvalid_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_65,21,1,65,F2A_19878,f2g_tx_out[0]_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_64,21,1,64,F2A_19879,f2g_tx_out[1]_A,Y,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_63,21,1,63,F2A_19880,f2g_tx_out[2]_A,Y,,,,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,200,40,1000,2000,FPGA_21_1_62,21,1,62,F2A_19881,f2g_tx_out[3]_A,Y,,,,,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,330,40,1000,3000,FPGA_21_1_61,21,1,61,F2A_19882,f2g_tx_out[4]_A,Y,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,330,40,1000,3000,FPGA_21_1_60,21,1,60,F2A_19883,f2g_tx_out[5]_A,Y,,,,,,,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,330,40,1000,3000,FPGA_21_1_59,21,1,59,F2A_19884,f2g_tx_out[6]_A,Y,,,,,,,,Y,Y,Y,Y,,,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,330,40,1000,3000,FPGA_21_1_58,21,1,58,F2A_19885,f2g_tx_out[7]_A,Y,,,,,,,,,Y,Y,Y,,,,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_57,21,1,57,F2A_19886,f2g_tx_out[8]_A,Y,,,,,,,,,,Y,Y,,,,,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_56,21,1,56,F2A_19887,f2g_tx_out[9]_A,Y,,,,,,,,,,,Y,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,590,40,1000,5000,FPGA_21_1_55,21,1,55,F2A_19888,f2g_tx_clk_en_A,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,720,40,1000,6000,FPGA_21_1_54,21,1,54,F2A_19889,f2g_trx_hs_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,720,40,1000,6000,FPGA_21_1_53,21,1,53,F2A_19890,f2g_trx_lp_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,720,40,1000,6000,FPGA_21_1_52,21,1,52,F2A_19891,f2g_tx_lp_dp,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,720,40,1000,6000,FPGA_21_1_51,21,1,51,F2A_19892,f2g_tx_lp_dn,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_39,HP_1_CC_38_19P,V13,720,40,1000,6000,FPGA_21_1_50,21,1,50,F2A_19893,f2g_rx_term_en,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_49,21,1,49,F2A_19894,f2g_rx_sfifo_reset_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_48,21,1,48,F2A_19895,f2g_rx_dpa_restart_B,Y,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_47,21,1,47,F2A_19896,f2g_trx_reset_n_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_46,21,1,46,F2A_19897,f2g_in_en_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_45,21,1,45,F2A_19898,f2g_tx_oe_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_44,21,1,44,F2A_19899,f2g_tx_dvalid_B,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, +GBOX GPIO,Bank_H_1_40,HP_1_CC_39_19N,V12,720,40,1000,6000,FPGA_21_1_43,21,1,43,F2A_19900,f2g_tx_clk_en_B,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,Y,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/tests/unittest/ModelConfig/design_edit.sdc b/tests/unittest/ModelConfig/design_edit.sdc new file mode 100644 index 000000000..d1a7b4211 --- /dev/null +++ b/tests/unittest/ModelConfig/design_edit.sdc @@ -0,0 +1,580 @@ +############# +# +# Fabric clock assignment +# +############# +# set_clock_pin -device_clock clk[0] -design_clock clk0 (Physical port name) +# set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk0 (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[0] -design_clock $clk_buf_$ibuf_clk0 + +# set_clock_pin -device_clock clk[1] -design_clock clk1 (Physical port name) +# set_clock_pin -device_clock clk[1] -design_clock pll_clk (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[1] -design_clock pll_clk + +# set_clock_pin -device_clock clk[2] -design_clock clk2 (Physical port name) +# set_clock_pin -device_clock clk[2] -design_clock $clk_buf_$ibuf_clk2 (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[2] -design_clock $clk_buf_$ibuf_clk2 + +# Fail reason: Failed to find the mapped name +# set_clock_pin -device_clock clk[3] -design_clock BOOT_CLOCK#0 (Physical port name) +set_clock_pin -device_clock clk[3] -design_clock osc_pll + +# This is fabric clock buffer +# set_clock_pin -device_clock clk[4] -design_clock FABRIC_CLKBUF#0 (Physical port name) +# set_clock_pin -device_clock clk[4] -design_clock $fclk_buf_clk0_div (Original clock primitive out-net to fabric) +set_clock_pin -device_clock clk[4] -design_clock $fclk_buf_clk0_div + +# For fabric clock buffer output +# set_clock_out -device_clock clk[0] -design_clock clk0_div +set_clock_out -device_clock clk[0] -design_clock clk0_div + +############# +# +# Each pin mode and location assignment +# +############# +# Clock data from object clk0 port O is not routed to fabric +# Pin clk0 :: I_BUF |-> CLK_BUF + +# Object clk1 is primitive \PLL but data signal is not defined +# Pin clk1 :: I_BUF |-> CLK_BUF |-> PLL + +# Clock data from object clk2 port O is not routed to fabric +# Pin clk2 :: I_BUF |-> CLK_BUF + +# Pin din :: I_BUF |-> I_DELAY +# set_mode MODE_BP_DIR_A_RX HP_1_20_10P +# set_io din HP_1_20_10P --> (original) +set_io din_delay HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin din_clk2 :: I_BUF +# set_mode MODE_BP_DIR_A_RX HR_5_0_0P +# set_io din_clk2 HR_5_0_0P --> (original) +set_io $ibuf_din_clk2 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Pin din_serdes :: I_BUF |-> I_SERDES +# set_mode MODE_RATE_8_A_RX HR_2_0_0P +# set_io din_serdes HR_2_0_0P --> (original) +set_io serdes_data[0] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[0]_A +set_io serdes_data[1] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[1]_A +set_io serdes_data[2] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[2]_A +set_io serdes_data[3] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[3]_A +set_io serdes_data[4] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[4]_A +set_io serdes_data[5] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[5]_A +set_io serdes_data[6] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[6]_A +set_io serdes_data[7] HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin g2f_rx_in[7]_A + +# Pin location is not assigned +# Pin enable :: I_BUF + +# Pin reset :: I_BUF +# set_mode MODE_BP_DIR_A_RX HP_1_0_0P +# set_io reset HP_1_0_0P --> (original) +set_io $ibuf_reset HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin g2f_rx_in[0]_A + +# Object clk_out is primitive \O_SERDES_CLK but data signal is not defined +# Pin clk_out :: O_SERDES_CLK |-> O_BUFT + +# Pin delay_tap[0] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_20_10P +# set_io delay_tap[0] HR_2_20_10P --> (original) +set_io $obuf_delay_tap[0] HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[1] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_22_11P +# set_io delay_tap[1] HR_2_22_11P --> (original) +set_io $obuf_delay_tap[1] HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[2] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_24_12P +# set_io delay_tap[2] HR_2_24_12P --> (original) +set_io $obuf_delay_tap[2] HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[3] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_26_13P +# set_io delay_tap[3] HR_2_26_13P --> (original) +set_io $obuf_delay_tap[3] HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[4] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_28_14P +# set_io delay_tap[4] HR_2_28_14P --> (original) +set_io $obuf_delay_tap[4] HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin delay_tap[5] :: O_BUFT +# set_mode MODE_BP_DIR_A_TX HR_2_30_15P +# set_io delay_tap[5] HR_2_30_15P --> (original) +set_io $obuf_delay_tap[5] HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dout :: O_DELAY |-> O_BUFT +# set_mode MODE_BP_DIR_A_TX HP_2_20_10P +# set_io dout HP_2_20_10P --> (original) +set_io dout_pre_delay HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_out[0]_A + +# Pin dout_clk2 :: O_BUFT +# set_mode MODE_BP_DIR_B_TX HR_5_1_0N +# set_io dout_clk2 HR_5_1_0N --> (original) +set_io $obuf_dout_clk2 HR_5_0_0P -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_out[5]_A + +# Pin dout_serdes :: O_SERDES |-> O_BUFT +# set_mode MODE_RATE_4_A_TX HR_2_2_1P +# set_io dout_serdes HR_2_2_1P --> (original) +set_io $abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[0] HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_out[0]_A +set_io $abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[1] HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_out[1]_A +set_io $abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[2] HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_out[2]_A +set_io $abc$194$xor$/home/cschai/desktop/raptor_projects/ppdb/foedag_unit_test/./top.v:199$5_Y[3] HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_out[3]_A + +# Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' +# Pin din_n :: I_BUF_DS |-> I_DDR + +# Pin din_p :: I_BUF_DS |-> I_DDR +# set_mode MODE_BP_DDR_A_RX HP_1_4_2P +# set_io din_p HP_1_4_2P --> (original) +set_io o_ddr_d[0] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[0]_A +set_io o_ddr_d[1] HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin g2f_rx_in[1]_A + +# Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' +# Pin dout_n :: O_DDR |-> O_BUF_DS + +# Pin dout_p :: O_DDR |-> O_BUF_DS +# set_mode MODE_BP_DDR_A_TX HP_1_8_4P +# set_io dout_p HP_1_8_4P --> (original) +set_io $auto_567 HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A +set_io $auto_568 HP_1_8_4P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A + +# Skip this because 'This is secondary pin. But IO bitstream generation will still make sure it is used in pair. Otherwise the IO bitstream will be invalid' +# Pin dout_osc_n :: O_DDR |-> O_BUF_DS + +# Pin dout_osc_p :: O_DDR |-> O_BUF_DS +# set_mode MODE_BP_DDR_A_TX HP_2_22_11P +# set_io dout_osc_p HP_2_22_11P --> (original) +set_io $auto_569 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[0]_A +set_io $auto_570 HP_2_22_11P -mode MODE_BP_DDR_A_TX -internal_pin f2g_tx_out[1]_A + +############# +# +# Internal Control Signals +# +############# +# Module: I_BUF +# LinkedObject: clk0 +# Location: HR_1_CC_18_9P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_531 HR_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: clk1 +# Location: HP_1_CC_18_9P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_532 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: PLL +# LinkedObject: clk1 +# Location: HP_1_CC_18_9P +# Port: LOCK +# Signal: out:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object clk1 wrapped-instance port LOCK + +# Module: PLL +# LinkedObject: clk1 +# Location: HP_1_CC_18_9P +# Port: PLL_EN +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $auto_565 HP_1_CC_18_9P -mode MODE_BP_DIR_A_RX -internal_pin TO_BE_DETERMINED + +# Module: I_BUF +# LinkedObject: clk2 +# Location: HR_5_CC_38_19P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_533 HR_5_CC_38_19P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: din +# Location: HP_1_20_10P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_534 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_DELAY +# LinkedObject: din +# Location: HP_1_20_10P +# Port: DLY_ADJ +# Signal: in:rule=half-first:f2g_trx_dly_adj +# Remap location from HP_1_20_10P to HP_1_20_10P +set_io $auto_550 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_adj + +# Module: I_DELAY +# LinkedObject: din +# Location: HP_1_20_10P +# Port: DLY_INCDEC +# Signal: in:rule=half-first:f2g_trx_dly_inc +# Remap location from HP_1_20_10P to HP_1_20_10P +set_io $auto_551 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_inc + +# Module: I_DELAY +# LinkedObject: din +# Location: HP_1_20_10P +# Port: DLY_LOAD +# Signal: in:rule=half-first:f2g_trx_dly_ld +# Remap location from HP_1_20_10P to HP_1_20_10P +set_io $auto_552 HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin f2g_trx_dly_ld + +# Module: I_DELAY +# LinkedObject: din +# Location: HP_1_20_10P +# Port: DLY_TAP_VALUE +# Signal: out:rule=half-first:g2f_trx_dly_tap +# Remap location from HP_1_20_10P to HP_1_20_10P +set_io $ifab_$obuf_delay_tap[0] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[0] +set_io $ifab_$obuf_delay_tap[1] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[1] +set_io $ifab_$obuf_delay_tap[2] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[2] +set_io $ifab_$obuf_delay_tap[3] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[3] +set_io $ifab_$obuf_delay_tap[4] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[4] +set_io $ifab_$obuf_delay_tap[5] HP_1_20_10P -mode MODE_BP_DIR_A_RX -internal_pin g2f_trx_dly_tap[5] + +# Module: I_BUF +# LinkedObject: din_clk2 +# Location: HR_5_0_0P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_535 HR_5_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: I_BUF +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_536 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_in_en_A + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: BITSLIP_ADJ +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $auto_553 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin TO_BE_DETERMINED + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: DATA_VALID +# Signal: out:g2f_rx_dvalid_{A|B} +# Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DATA_VALID + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: DPA_ERROR +# Signal: out:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DPA_ERROR + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: DPA_LOCK +# Signal: out:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port DPA_LOCK + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: EN +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $auto_555 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin TO_BE_DETERMINED + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: PLL_LOCK +# Signal: in:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object din_serdes wrapped-instance port PLL_LOCK + +# Module: I_SERDES +# LinkedObject: din_serdes +# Location: HR_2_0_0P +# Port: RST +# Signal: in:f2g_trx_reset_n_{A|B} +set_io $auto_556 HR_2_0_0P -mode MODE_RATE_8_A_RX -internal_pin f2g_trx_reset_n_A + +# Module: I_BUF +# LinkedObject: enable +# Location: +# Port: EN +# Signal: in:f2g_in_en_{A|B} +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF +# LinkedObject: reset +# Location: HP_1_0_0P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_538 HP_1_0_0P -mode MODE_BP_DIR_A_RX -internal_pin f2g_in_en_A + +# Module: O_BUFT +# LinkedObject: clk_out +# Location: HR_2_4_2P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_539 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_SERDES_CLK +# LinkedObject: clk_out +# Location: HR_2_4_2P +# Port: CLK_EN +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $auto_564 HR_2_4_2P -mode MODE_BP_SDR_A_TX -internal_pin TO_BE_DETERMINED + +# Module: O_SERDES_CLK +# LinkedObject: clk_out +# Location: HR_2_4_2P +# Port: PLL_LOCK +# Signal: in:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object clk_out wrapped-instance port PLL_LOCK + +# Module: O_BUFT +# LinkedObject: delay_tap[0] +# Location: HR_2_20_10P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_540 HR_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: delay_tap[1] +# Location: HR_2_22_11P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_541 HR_2_22_11P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: delay_tap[2] +# Location: HR_2_24_12P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_542 HR_2_24_12P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: delay_tap[3] +# Location: HR_2_26_13P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_543 HR_2_26_13P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: delay_tap[4] +# Location: HR_2_28_14P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_544 HR_2_28_14P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: delay_tap[5] +# Location: HR_2_30_15P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_545 HR_2_30_15P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_BUFT +# LinkedObject: dout +# Location: HP_2_20_10P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_546 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_DELAY +# LinkedObject: dout +# Location: HP_2_20_10P +# Port: DLY_ADJ +# Signal: in:rule=half-first:f2g_trx_dly_adj +# Remap location from HP_2_20_10P to HP_2_20_10P +set_io $auto_557 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_adj + +# Module: O_DELAY +# LinkedObject: dout +# Location: HP_2_20_10P +# Port: DLY_INCDEC +# Signal: in:rule=half-first:f2g_trx_dly_inc +# Remap location from HP_2_20_10P to HP_2_20_10P +set_io $auto_558 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_inc + +# Module: O_DELAY +# LinkedObject: dout +# Location: HP_2_20_10P +# Port: DLY_LOAD +# Signal: in:rule=half-first:f2g_trx_dly_ld +# Remap location from HP_2_20_10P to HP_2_20_10P +set_io $auto_559 HP_2_20_10P -mode MODE_BP_DIR_A_TX -internal_pin f2g_trx_dly_ld + +# Module: O_DELAY +# LinkedObject: dout +# Location: HP_2_20_10P +# Port: DLY_TAP_VALUE +# Signal: out:rule=half-first:g2f_trx_dly_tap +# Skip reason: User design does not utilize linked-object dout wrapped-instance port DLY_TAP_VALUE + +# Module: O_BUFT +# LinkedObject: dout_clk2 +# Location: HR_5_1_0N +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_547 HR_5_1_0N -mode MODE_BP_DIR_B_TX -internal_pin f2g_tx_oe_B + +# Module: O_BUFT +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: T +# Signal: in:f2g_tx_oe_{A|B} +set_io $auto_548 HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_oe_A + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: CHANNEL_BOND_SYNC_IN +# Signal: in:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_IN + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: CHANNEL_BOND_SYNC_OUT +# Signal: out:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port CHANNEL_BOND_SYNC_OUT + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: DATA_VALID +# Signal: in:f2g_tx_dvalid_{A|B} +set_io $auto_561 HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_tx_dvalid_A + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: OE_IN +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $auto_562 HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin TO_BE_DETERMINED + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: OE_OUT +# Signal: out:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port OE_OUT + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: PLL_LOCK +# Signal: in:TO_BE_DETERMINED +# Skip reason: User design does not utilize linked-object dout_serdes wrapped-instance port PLL_LOCK + +# Module: O_SERDES +# LinkedObject: dout_serdes +# Location: HR_2_2_1P +# Port: RST +# Signal: in:f2g_trx_reset_n_{A|B} +set_io $auto_563 HR_2_2_1P -mode MODE_RATE_4_A_TX -internal_pin f2g_trx_reset_n_A + +# Module: PLL +# LinkedObject: BOOT_CLOCK#0 +# Location: +# Port: LOCK +# Signal: out:TO_BE_DETERMINED +# Skip reason: Location does not have any mode to begin with + +# Module: PLL +# LinkedObject: BOOT_CLOCK#0 +# Location: +# Port: PLL_EN +# Signal: in:TO_BE_DETERMINED +# Skip reason: Location does not have any mode to begin with + +# Module: I_BUF_DS +# LinkedObject: din_n+din_p +# Location: HP_1_4_2P +# Port: EN +# Signal: in:f2g_in_en_{A|B} +set_io $auto_549 HP_1_4_2P -mode MODE_BP_DDR_A_RX -internal_pin f2g_in_en_A + +# Module: I_DDR +# LinkedObject: din_n+din_p +# Location: HP_1_5_2N +# Port: E +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable_4 HP_1_5_2N -mode MODE_BP_DDR_B_RX -internal_pin TO_BE_DETERMINED + +# Module: I_DDR +# LinkedObject: din_n+din_p +# Location: HP_1_5_2N +# Port: R +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_A_$ibuf_reset_4 HP_1_5_2N -mode MODE_BP_DDR_B_RX -internal_pin TO_BE_DETERMINED + +# Module: O_DDR +# LinkedObject: dout_n+dout_p +# Location: HP_1_9_4N +# Port: E +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable HP_1_9_4N -mode MODE_BP_DDR_B_TX -internal_pin TO_BE_DETERMINED + +# Module: O_DDR +# LinkedObject: dout_n+dout_p +# Location: HP_1_9_4N +# Port: R +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_A_$ibuf_reset HP_1_9_4N -mode MODE_BP_DDR_B_TX -internal_pin TO_BE_DETERMINED + +# Module: O_DDR +# LinkedObject: dout_osc_n+dout_osc_p +# Location: HP_2_23_11N +# Port: E +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $ofab_$ibuf_enable_2 HP_2_23_11N -mode MODE_BP_DDR_B_TX -internal_pin TO_BE_DETERMINED + +# Module: O_DDR +# LinkedObject: dout_osc_n+dout_osc_p +# Location: HP_2_23_11N +# Port: R +# Signal: in:TO_BE_DETERMINED +# Skip reason: TO_BE_DETERMINED +# set_io $f2g_trx_reset_n_A_$ibuf_reset_2 HP_2_23_11N -mode MODE_BP_DDR_B_TX -internal_pin TO_BE_DETERMINED + +############# +# +# Each gearbox core clock +# +############# +# Module: I_SERDES +# Location: HR_2_0_0P +# Port: CLK_IN +# Net: 1'1 +# Fail reason: Cannot locate the fabric clock + +# Module: O_SERDES +# Location: HR_2_2_1P +# Port: CLK_IN +# Net: 1'1 +# Fail reason: Cannot locate the fabric clock + +# Module: O_DDR +# Location: HP_1_9_4N +# Port: C +# Net: pll_clk +set_core_clk HP_1_9_4N 1 + +# Module: O_DDR +# Location: HP_2_23_11N +# Port: C +# Net: osc_pll +set_core_clk HP_2_23_11N 3 + diff --git a/tests/unittest/ModelConfig/empty_bitstream_setting.xml b/tests/unittest/ModelConfig/empty_bitstream_setting.xml new file mode 100644 index 000000000..dc4206652 --- /dev/null +++ b/tests/unittest/ModelConfig/empty_bitstream_setting.xml @@ -0,0 +1,2 @@ + + \ No newline at end of file diff --git a/tests/unittest/ModelConfig/golden/bitstream_setting.xml b/tests/unittest/ModelConfig/golden/bitstream_setting.xml new file mode 100644 index 000000000..ff7a07fb0 --- /dev/null +++ b/tests/unittest/ModelConfig/golden/bitstream_setting.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + From 132977e2d99f0dc3c5775902001c16bcac27b81c Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 13:00:58 -0700 Subject: [PATCH 03/14] Misc wording update --- src/Compiler/CompilerOpenFPGA.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index 2a9bef383..b324aca25 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -3585,14 +3585,14 @@ bool CompilerOpenFPGA::GenerateBitstream() { "%s bitstream_setting.xml", io_status.second.c_str(), design_edit_sdc.c_str(), m_PinMapCSV.c_str(), m_OpenFpgaBitstreamSettingFile.c_str()); - auto file = ProjManager()->projectName() + "_io_clk_out_cmd.tcl"; + auto file = ProjManager()->projectName() + "_gen_bitstream_setting_xml_cmd.tcl"; FileUtils::WriteToFile(file, command); command = CFG_print("source %s", file.c_str()); int status = TCL_OK; m_interp->evalCmd(command, &status); if (status != TCL_OK) { ErrorMessage("Design " + ProjManager()->projectName() + - " IO Clock out generation failed"); + " Bitstream Setting XML generation failed"); return false; } else { m_runtime_OpenFpgaBitstreamSettingFile = "bitstream_setting.xml"; From 6f987149f3056ea89b8a62662e3762587ee9c06d Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 13:20:17 -0700 Subject: [PATCH 04/14] Make sure always generate good unittest result --- src/Compiler/CompilerOpenFPGA.cpp | 3 ++- src/Configuration/ModelConfig/ModelConfig.cpp | 2 +- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 8 +++++++- .../ModelConfig_BITSTREAM_SETTING_XML_test.cpp | 6 +++--- tests/unittest/ModelConfig/golden/bitstream_setting.xml | 2 +- 5 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index b324aca25..82eecf6c7 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -3585,7 +3585,8 @@ bool CompilerOpenFPGA::GenerateBitstream() { "%s bitstream_setting.xml", io_status.second.c_str(), design_edit_sdc.c_str(), m_PinMapCSV.c_str(), m_OpenFpgaBitstreamSettingFile.c_str()); - auto file = ProjManager()->projectName() + "_gen_bitstream_setting_xml_cmd.tcl"; + auto file = + ProjManager()->projectName() + "_gen_bitstream_setting_xml_cmd.tcl"; FileUtils::WriteToFile(file, command); command = CFG_print("source %s", file.c_str()); int status = TCL_OK; diff --git a/src/Configuration/ModelConfig/ModelConfig.cpp b/src/Configuration/ModelConfig/ModelConfig.cpp index c82bcee17..cc261e850 100644 --- a/src/Configuration/ModelConfig/ModelConfig.cpp +++ b/src/Configuration/ModelConfig/ModelConfig.cpp @@ -916,7 +916,7 @@ void model_config_entry(CFGCommon_ARG* cmdarg) { } else if (cmdarg->raws[0] == "gen_bitstream_setting_xml") { CFGArg::parse("model_config|gen_bitstream_setting_xml", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, - {}, {"device_size", "design", "pin"}, {}, 2); + {"is_unittest"}, {"device_size", "design", "pin"}, {}, 2); ModelConfig_BITSREAM_SETTINGS_XML xml( flag_options, options, positional_options[0], positional_options[1]); } else if (cmdarg->raws[0] == "backdoor") { diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 142b3f765..ab1adfcec 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -41,6 +41,8 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( const std::vector& flag_options, const std::map& options, const std::string& input, const std::string& output) { + bool is_unittest = std::find(flag_options.begin(), flag_options.end(), + "is_unittest") != flag_options.end(); std::vector device_sizes = CFG_split_string(options.at("device_size"), "x"); if (device_sizes.size() == 2) { @@ -82,7 +84,11 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( std::ifstream ixml(input.c_str()); CFG_ASSERT(ixml.is_open()); CFG_ASSERT(ixml.good()); - oxml << "\n"; + if (is_unittest) { + oxml << "\n"; + } else { + oxml << "\n"; + } bool found_xml_end = false; std::string line = ""; while (std::getline(ixml, line)) { diff --git a/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp index a0b9b59ec..aae838349 100644 --- a/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp +++ b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp @@ -35,9 +35,9 @@ class ModelConfig_BITSTREAM_SETTING_XML : public ::testing::Test { TEST_F(ModelConfig_BITSTREAM_SETTING_XML, gen_bitstream_setting_xml) { std::string current_dir = COMPILER_TCL_COMMON_GET_CURRENT_DIR(); std::string cmd = CFG_print( - "model_config gen_bitstream_setting_xml -device_size 22x4 -design " - "%s/design_edit.sdc -pin %s/Pin_Table.csv %s/empty_bitstream_setting.xml " - "bitstream_setting.xml", + "model_config gen_bitstream_setting_xml -is_unittest -device_size 22x4 " + "-design %s/design_edit.sdc -pin %s/Pin_Table.csv " + "%s/empty_bitstream_setting.xml bitstream_setting.xml", current_dir.c_str(), current_dir.c_str(), current_dir.c_str()); compiler_tcl_common_run(cmd); } diff --git a/tests/unittest/ModelConfig/golden/bitstream_setting.xml b/tests/unittest/ModelConfig/golden/bitstream_setting.xml index ff7a07fb0..7e2c43dd6 100644 --- a/tests/unittest/ModelConfig/golden/bitstream_setting.xml +++ b/tests/unittest/ModelConfig/golden/bitstream_setting.xml @@ -1,4 +1,4 @@ - + From 5b3e1b49efe08f376b35bf7a8ca80271a085480b Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 20:32:08 +0000 Subject: [PATCH 05/14] Incremented patch version --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 71c1394f2..d6c63efbe 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -39,7 +39,7 @@ set(VERSION_MINOR 0) # Add the spdlog directory to the include path include_directories(${CMAKE_CURRENT_SOURCE_DIR}/third_party/spdlog/include ${CMAKE_CURRENT_SOURCE_DIR}/third_party/exprtk ${CMAKE_CURRENT_SOURCE_DIR}/third_party/scope_guard) -set(VERSION_PATCH 410) +set(VERSION_PATCH 411) option( From 7cbb2e110632c3ddf27eb0cb17bc52c92768884a Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 14:34:57 -0700 Subject: [PATCH 06/14] Try another delete approach --- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index ab1adfcec..916885086 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -58,6 +58,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( std::vector words = CFG_split_string(line, " ", 0, false); CFG_ASSERT(words.size() == 3); CFG_ASSERT(words[0] == "set_core_clk"); + CFG_ASSERT(location_map.find(words[1]) == location_map.end()); uint32_t index = (uint32_t)(CFG_convert_string_to_u64(words[2])); location_map[words[1]] = new PIN_INFO(index); } @@ -90,7 +91,6 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( oxml << "\n"; } bool found_xml_end = false; - std::string line = ""; while (std::getline(ixml, line)) { std::string xml_line = line; CFG_get_rid_whitespace(xml_line); @@ -141,8 +141,10 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( oxml << " \n"; oxml << "\n"; oxml.close(); - for (auto& iter : location_map) { - delete iter.second; + while (location_map.size()) { + auto iter = location_map.begin(); + delete iter->second; + location_map.erase(iter); } } } From 8971cfd148496a5dcc1e094ce992c7650bce8337 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 14:47:29 -0700 Subject: [PATCH 07/14] No pointer --- .../ModelConfig_BITSTREAM_SETTING_XML.cpp | 51 +++++++++---------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 916885086..a2a78158d 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -27,8 +27,9 @@ along with this program. If not, see . namespace FOEDAG { struct PIN_INFO { + PIN_INFO() {} PIN_INFO(uint32_t i) : fabric_clk_index(i) {} - const uint32_t fabric_clk_index = 0; + uint32_t fabric_clk_index = 0; uint32_t x = 0; uint32_t y = 0; std::string type = ""; @@ -51,7 +52,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( std::ifstream design(options.at("design").c_str()); CFG_ASSERT(design.is_open() && design.good()); std::string line = ""; - std::map location_map; + std::map location_map; while (std::getline(design, line)) { CFG_get_rid_trailing_whitespace(line); if (line.size() > 0 && line.find("set_core_clk") == 0) { @@ -60,7 +61,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( CFG_ASSERT(words[0] == "set_core_clk"); CFG_ASSERT(location_map.find(words[1]) == location_map.end()); uint32_t index = (uint32_t)(CFG_convert_string_to_u64(words[2])); - location_map[words[1]] = new PIN_INFO(index); + location_map[words[1]] = PIN_INFO(index); } } design.close(); @@ -72,9 +73,9 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( std::vector words = CFG_split_string(line, ","); if (words.size() >= 11 && words[2].size() > 0 && location_map.find(words[2]) != location_map.end()) { - location_map.at(words[2])->x = + location_map.at(words[2]).x = (uint32_t)(CFG_convert_string_to_u64(words[9])); - location_map.at(words[2])->y = + location_map.at(words[2]).y = (uint32_t)(CFG_convert_string_to_u64(words[10])); } } @@ -107,45 +108,39 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( } oxml << " \n"; for (auto& iter : location_map) { - if (iter.second->y == 1 && iter.second->x >= 2 && - iter.second->x < (device_x - 2)) { - iter.second->type = "bottom"; - } else if (iter.second->y == (device_y - 2) && iter.second->x >= 2 && - iter.second->x < (device_x - 2)) { - iter.second->type = "top"; - } else if (iter.second->x == 1 && iter.second->y >= 2 && - iter.second->y < (device_y - 2)) { - iter.second->type = "left"; - } else if (iter.second->x == (device_x - 2) && iter.second->y >= 2 && - iter.second->y < (device_y - 2)) { - iter.second->type = "right"; + if (iter.second.y == 1 && iter.second.x >= 2 && + iter.second.x < (device_x - 2)) { + iter.second.type = "bottom"; + } else if (iter.second.y == (device_y - 2) && iter.second.x >= 2 && + iter.second.x < (device_x - 2)) { + iter.second.type = "top"; + } else if (iter.second.x == 1 && iter.second.y >= 2 && + iter.second.y < (device_y - 2)) { + iter.second.type = "left"; + } else if (iter.second.x == (device_x - 2) && iter.second.y >= 2 && + iter.second.y < (device_y - 2)) { + iter.second.type = "right"; } - if (iter.second->type.size()) { + if (iter.second.type.size()) { oxml << " \n"; + << ", Value: " << iter.second.fabric_clk_index << " -->\n"; for (int i = 0; i < 4; i++) { oxml << CFG_print( " \n", - (iter.second->fabric_clk_index & (1 << i)) ? 1 : 0, - iter.second->type.c_str(), iter.second->x, iter.second->y, - i) + (iter.second.fabric_clk_index & (1 << i)) ? 1 : 0, + iter.second.type.c_str(), iter.second.x, iter.second.y, i) .c_str(); } } else { oxml << " \n"; + << ", Value: " << iter.second.fabric_clk_index << " -->\n"; } } oxml << " \n"; oxml << "\n"; oxml.close(); - while (location_map.size()) { - auto iter = location_map.begin(); - delete iter->second; - location_map.erase(iter); - } } } From 9edc6fad1c017d38ffe494afce9e62fe624dbef9 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 15:36:26 -0700 Subject: [PATCH 08/14] debug0 --- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index a2a78158d..1760e0e38 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -42,6 +42,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( const std::vector& flag_options, const std::map& options, const std::string& input, const std::string& output) { + /* bool is_unittest = std::find(flag_options.begin(), flag_options.end(), "is_unittest") != flag_options.end(); std::vector device_sizes = @@ -142,6 +143,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( oxml << "\n"; oxml.close(); } + */ } /* From 3ca12dede2d4e19d51c3724a80a79855b38f7f63 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 16:14:07 -0700 Subject: [PATCH 09/14] debug1 --- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 1760e0e38..44c8f82ee 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -42,7 +42,6 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( const std::vector& flag_options, const std::map& options, const std::string& input, const std::string& output) { - /* bool is_unittest = std::find(flag_options.begin(), flag_options.end(), "is_unittest") != flag_options.end(); std::vector device_sizes = @@ -54,6 +53,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( CFG_ASSERT(design.is_open() && design.good()); std::string line = ""; std::map location_map; + /* while (std::getline(design, line)) { CFG_get_rid_trailing_whitespace(line); if (line.size() > 0 && line.find("set_core_clk") == 0) { @@ -65,6 +65,7 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( location_map[words[1]] = PIN_INFO(index); } } + */ design.close(); if (location_map.size()) { std::ifstream pin(options.at("pin").c_str()); @@ -143,7 +144,6 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( oxml << "\n"; oxml.close(); } - */ } /* From 677043173fa0174edfb564510501b1a39f5fb0ee Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 16:25:08 -0700 Subject: [PATCH 10/14] debug2 --- src/Configuration/ModelConfig/ModelConfig.cpp | 7 +++++-- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 2 -- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig.cpp b/src/Configuration/ModelConfig/ModelConfig.cpp index cc261e850..4c06c87e5 100644 --- a/src/Configuration/ModelConfig/ModelConfig.cpp +++ b/src/Configuration/ModelConfig/ModelConfig.cpp @@ -917,8 +917,11 @@ void model_config_entry(CFGCommon_ARG* cmdarg) { CFGArg::parse("model_config|gen_bitstream_setting_xml", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, {"is_unittest"}, {"device_size", "design", "pin"}, {}, 2); - ModelConfig_BITSREAM_SETTINGS_XML xml( - flag_options, options, positional_options[0], positional_options[1]); + ModelConfig_BITSREAM_SETTINGS_XML* xml = + new ModelConfig_BITSREAM_SETTINGS_XML(flag_options, options, + positional_options[0], + positional_options[1]); + delete xml; } else if (cmdarg->raws[0] == "backdoor") { CFGArg::parse("model_config|gen_ppdb", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 44c8f82ee..a2a78158d 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -53,7 +53,6 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( CFG_ASSERT(design.is_open() && design.good()); std::string line = ""; std::map location_map; - /* while (std::getline(design, line)) { CFG_get_rid_trailing_whitespace(line); if (line.size() > 0 && line.find("set_core_clk") == 0) { @@ -65,7 +64,6 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( location_map[words[1]] = PIN_INFO(index); } } - */ design.close(); if (location_map.size()) { std::ifstream pin(options.at("pin").c_str()); From e618faf2a920c822f3f446b67c11551b5bf0cab3 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 16:53:06 -0700 Subject: [PATCH 11/14] debug3 --- .../ModelConfig_BITSTREAM_SETTING_XML.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index a2a78158d..52366b7ec 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -71,12 +71,12 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( while (std::getline(pin, line)) { CFG_get_rid_trailing_whitespace(line); std::vector words = CFG_split_string(line, ","); - if (words.size() >= 11 && words[2].size() > 0 && - location_map.find(words[2]) != location_map.end()) { - location_map.at(words[2]).x = - (uint32_t)(CFG_convert_string_to_u64(words[9])); - location_map.at(words[2]).y = - (uint32_t)(CFG_convert_string_to_u64(words[10])); + if (words.size() >= 11 && words[2].size() > 0) { + auto iter = location_map.find(words[2]); + if (iter != location_map.end()) { + iter->second.x = (uint32_t)(CFG_convert_string_to_u64(words[9])); + iter->second.y = (uint32_t)(CFG_convert_string_to_u64(words[10])); + } } } pin.close(); From 073b991a5d32e8a04cf4c72915b9aacf9f407357 Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 17:11:54 -0700 Subject: [PATCH 12/14] debug4 --- src/Configuration/ModelConfig/ModelConfig.cpp | 7 ++----- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 9 ++------- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h | 8 +++----- 3 files changed, 7 insertions(+), 17 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig.cpp b/src/Configuration/ModelConfig/ModelConfig.cpp index 4c06c87e5..fa7eed070 100644 --- a/src/Configuration/ModelConfig/ModelConfig.cpp +++ b/src/Configuration/ModelConfig/ModelConfig.cpp @@ -917,11 +917,8 @@ void model_config_entry(CFGCommon_ARG* cmdarg) { CFGArg::parse("model_config|gen_bitstream_setting_xml", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, {"is_unittest"}, {"device_size", "design", "pin"}, {}, 2); - ModelConfig_BITSREAM_SETTINGS_XML* xml = - new ModelConfig_BITSREAM_SETTINGS_XML(flag_options, options, - positional_options[0], - positional_options[1]); - delete xml; + ModelConfig_BITSREAM_SETTINGS_XML::gen( + flag_options, options, positional_options[0], positional_options[1]); } else if (cmdarg->raws[0] == "backdoor") { CFGArg::parse("model_config|gen_ppdb", cmdarg->raws.size(), &cmdarg->raws[0], flag_options, options, positional_options, diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 52366b7ec..e77c01662 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -36,9 +36,9 @@ struct PIN_INFO { }; /* - Constructor + Generate bitstream setting XML */ -ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( +void ModelConfig_BITSREAM_SETTINGS_XML::gen( const std::vector& flag_options, const std::map& options, const std::string& input, const std::string& output) { @@ -144,9 +144,4 @@ ModelConfig_BITSREAM_SETTINGS_XML::ModelConfig_BITSREAM_SETTINGS_XML( } } -/* - Destructor -*/ -ModelConfig_BITSREAM_SETTINGS_XML::~ModelConfig_BITSREAM_SETTINGS_XML() {} - } // namespace FOEDAG diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h index 7637bde12..b3a11ec22 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.h @@ -32,11 +32,9 @@ namespace FOEDAG { class ModelConfig_BITSREAM_SETTINGS_XML { public: - ModelConfig_BITSREAM_SETTINGS_XML( - const std::vector& flag_options, - const std::map& options, - const std::string& input, const std::string& output); - ~ModelConfig_BITSREAM_SETTINGS_XML(); + static void gen(const std::vector& flag_options, + const std::map& options, + const std::string& input, const std::string& output); private: }; From 33d52b920a47c5c7f8e454ff9a046a446b8fc01b Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Thu, 1 Aug 2024 17:55:35 -0700 Subject: [PATCH 13/14] debug5 --- .../ModelConfig_BITSTREAM_SETTING_XML.cpp | 33 ++++++++++--------- ...ModelConfig_BITSTREAM_SETTING_XML_test.cpp | 2 +- .../ModelConfig/golden/bitstream_setting.xml | 4 +-- 3 files changed, 20 insertions(+), 19 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index e77c01662..779e93495 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -108,22 +108,19 @@ void ModelConfig_BITSREAM_SETTINGS_XML::gen( } oxml << " \n"; for (auto& iter : location_map) { - if (iter.second.y == 1 && iter.second.x >= 2 && - iter.second.x < (device_x - 2)) { - iter.second.type = "bottom"; - } else if (iter.second.y == (device_y - 2) && iter.second.x >= 2 && - iter.second.x < (device_x - 2)) { - iter.second.type = "top"; - } else if (iter.second.x == 1 && iter.second.y >= 2 && - iter.second.y < (device_y - 2)) { - iter.second.type = "left"; - } else if (iter.second.x == (device_x - 2) && iter.second.y >= 2 && - iter.second.y < (device_y - 2)) { - iter.second.type = "right"; + if ((iter.second.y == 1 || iter.second.y == (device_y - 2)) && + iter.second.x >= 2 && iter.second.x < (device_x - 2)) { + iter.second.type = iter.second.y == 1 ? "bottom" : "top"; + } else if ((iter.second.x == 1 || iter.second.x == (device_x - 2)) && + iter.second.y >= 2 && iter.second.y < (device_y - 2)) { + iter.second.type = iter.second.x == 1 ? "left" : "right"; } if (iter.second.type.size()) { - oxml << " \n"; + oxml << CFG_print( + " \n", + iter.first.c_str(), iter.second.fabric_clk_index, + iter.second.x, iter.second.y) + .c_str(); for (int i = 0; i < 4; i++) { oxml << CFG_print( " \n"; + oxml << CFG_print( + " \n", + iter.first.c_str(), iter.second.fabric_clk_index, + iter.second.x, iter.second.y) + .c_str(); } } oxml << " \n"; diff --git a/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp index aae838349..8155a7b49 100644 --- a/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp +++ b/tests/unittest/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML_test.cpp @@ -35,7 +35,7 @@ class ModelConfig_BITSTREAM_SETTING_XML : public ::testing::Test { TEST_F(ModelConfig_BITSTREAM_SETTING_XML, gen_bitstream_setting_xml) { std::string current_dir = COMPILER_TCL_COMMON_GET_CURRENT_DIR(); std::string cmd = CFG_print( - "model_config gen_bitstream_setting_xml -is_unittest -device_size 22x4 " + "model_config gen_bitstream_setting_xml -is_unittest -device_size 24x6 " "-design %s/design_edit.sdc -pin %s/Pin_Table.csv " "%s/empty_bitstream_setting.xml bitstream_setting.xml", current_dir.c_str(), current_dir.c_str(), current_dir.c_str()); diff --git a/tests/unittest/ModelConfig/golden/bitstream_setting.xml b/tests/unittest/ModelConfig/golden/bitstream_setting.xml index 7e2c43dd6..2c8a1a58a 100644 --- a/tests/unittest/ModelConfig/golden/bitstream_setting.xml +++ b/tests/unittest/ModelConfig/golden/bitstream_setting.xml @@ -1,11 +1,11 @@ - + - + From 1403f05d4ff9de18ff2fc965d4a4440050949b3b Mon Sep 17 00:00:00 2001 From: chungshien-chai Date: Fri, 2 Aug 2024 01:05:44 -0700 Subject: [PATCH 14/14] Should solve unit test issue --- .../ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp index 779e93495..bc68ed30a 100644 --- a/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp +++ b/src/Configuration/ModelConfig/ModelConfig_BITSTREAM_SETTING_XML.cpp @@ -26,9 +26,9 @@ along with this program. If not, see . namespace FOEDAG { -struct PIN_INFO { - PIN_INFO() {} - PIN_INFO(uint32_t i) : fabric_clk_index(i) {} +struct PIN_TABLE_INFO { + PIN_TABLE_INFO() {} + PIN_TABLE_INFO(uint32_t i) : fabric_clk_index(i) {} uint32_t fabric_clk_index = 0; uint32_t x = 0; uint32_t y = 0; @@ -52,7 +52,7 @@ void ModelConfig_BITSREAM_SETTINGS_XML::gen( std::ifstream design(options.at("design").c_str()); CFG_ASSERT(design.is_open() && design.good()); std::string line = ""; - std::map location_map; + std::map location_map; while (std::getline(design, line)) { CFG_get_rid_trailing_whitespace(line); if (line.size() > 0 && line.find("set_core_clk") == 0) { @@ -61,7 +61,7 @@ void ModelConfig_BITSREAM_SETTINGS_XML::gen( CFG_ASSERT(words[0] == "set_core_clk"); CFG_ASSERT(location_map.find(words[1]) == location_map.end()); uint32_t index = (uint32_t)(CFG_convert_string_to_u64(words[2])); - location_map[words[1]] = PIN_INFO(index); + location_map[words[1]] = PIN_TABLE_INFO(index); } } design.close();