From 7f21249b029075bf45445c5869b3803c86d96f2a Mon Sep 17 00:00:00 2001 From: awaisabbas006 Date: Mon, 12 Aug 2024 14:03:01 +0500 Subject: [PATCH 1/3] revert PR 1670 --- src/Compiler/CompilerOpenFPGA.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index 93a2fee0b..82eecf6c7 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -1465,7 +1465,7 @@ std::string CompilerOpenFPGA::GhdlDesignParsingCommmands() { "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " "--PREFIX=" + prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + - " -e " + ProjManager()->DesignTopModule() + " " + designLibraries + "\n"; + " -e " + designLibraries + "\n"; fileList += verilogcmd; return fileList; From 0031d2a02355279ab2c9981e241c0cdd4d813a37 Mon Sep 17 00:00:00 2001 From: awaisabbas006 Date: Mon, 12 Aug 2024 15:49:18 +0500 Subject: [PATCH 2/3] fix CI --- src/Compiler/CompilerOpenFPGA.cpp | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index 82eecf6c7..bdc8a8f07 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -1461,12 +1461,21 @@ std::string CompilerOpenFPGA::GhdlDesignParsingCommmands() { verilogcmd += "read_verilog " + includes + verilogFiles + "\n"; } } - fileList = - "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " - "--PREFIX=" + - prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + - " -e " + designLibraries + "\n"; - fileList += verilogcmd; + if (!verilogFiles.empty()){ + fileList = + "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " + "--PREFIX=" + + prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + + " -e " + designLibraries + "\n"; + fileList += verilogcmd; + } + else{ + fileList = + "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " + "--PREFIX=" + + prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + + " -e " + ProjManager()->DesignTopModule() + " " + designLibraries + "\n"; + } return fileList; } From adc94edc892d276d03411d3ac9732417c8aa55dd Mon Sep 17 00:00:00 2001 From: awaisabbas006 Date: Wed, 14 Aug 2024 13:33:42 +0500 Subject: [PATCH 3/3] C++ code formating --- src/Compiler/CompilerOpenFPGA.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/Compiler/CompilerOpenFPGA.cpp b/src/Compiler/CompilerOpenFPGA.cpp index bdc8a8f07..48cef437a 100644 --- a/src/Compiler/CompilerOpenFPGA.cpp +++ b/src/Compiler/CompilerOpenFPGA.cpp @@ -1461,20 +1461,20 @@ std::string CompilerOpenFPGA::GhdlDesignParsingCommmands() { verilogcmd += "read_verilog " + includes + verilogFiles + "\n"; } } - if (!verilogFiles.empty()){ + if (!verilogFiles.empty()) { fileList = - "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " - "--PREFIX=" + + "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys " + "-fexplicit --PREFIX=" + prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + " -e " + designLibraries + "\n"; fileList += verilogcmd; - } - else{ + } else { fileList = - "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys -fexplicit " - "--PREFIX=" + + "plugin -i ghdl\nghdl -frelaxed-rules --no-formal -fsynopsys " + "-fexplicit --PREFIX=" + prefixPackagePath.string() + " " + searchPath + lang + " " + fileList + - " -e " + ProjManager()->DesignTopModule() + " " + designLibraries + "\n"; + " -e " + ProjManager()->DesignTopModule() + " " + designLibraries + + "\n"; } return fileList;