From 211f69a4a41570430084ff3b532f13a0e2e8d98a Mon Sep 17 00:00:00 2001
From: Alain Dargelas <90641725+alain-rs@users.noreply.github.com>
Date: Thu, 31 Aug 2023 19:03:19 -0700
Subject: [PATCH] Ghdl synth support (#497)

* GHDL plugin support

* default yosys parser

---------

Co-authored-by: Alain Dargelas <alain.dargelas@gmail.com>
---
 src/Compiler/CompilerRS.cpp | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/Compiler/CompilerRS.cpp b/src/Compiler/CompilerRS.cpp
index 10dbbe932..46ce38de0 100644
--- a/src/Compiler/CompilerRS.cpp
+++ b/src/Compiler/CompilerRS.cpp
@@ -74,6 +74,25 @@ plugin -i ${PLUGIN_LIB}
 
 ${PLUGIN_NAME} -tech ${MAP_TO_TECHNOLOGY} ${OPTIMIZATION} ${EFFORT} ${CARRY} ${IO} ${LIMITS} ${FSM_ENCODING} ${FAST} ${NO_FLATTEN} ${MAX_THREADS} ${NO_SIMPLIFY} ${CLKE_STRATEGY} ${CEC}
 
+${OUTPUT_NETLIST}
+
+  )";
+
+const std::string RapidSiliconYosysDefaultScript = R"( 
+# Yosys/Verific synthesis script for ${TOP_MODULE}
+# Read source files
+read_verilog -sv ${PRIMITIVES_BLACKBOX}
+${READ_DESIGN_FILES}
+
+# Technology mapping
+hierarchy ${TOP_MODULE_DIRECTIVE}
+
+${KEEP_NAMES}
+
+plugin -i ${PLUGIN_LIB}
+
+${PLUGIN_NAME} -tech ${MAP_TO_TECHNOLOGY} ${OPTIMIZATION} ${EFFORT} ${CARRY} ${IO} ${LIMITS} ${FSM_ENCODING} ${FAST} ${NO_FLATTEN} ${MAX_THREADS} ${NO_SIMPLIFY} ${CLKE_STRATEGY} ${CEC}
+
 ${OUTPUT_NETLIST}
 
   )";
@@ -185,7 +204,7 @@ std::string CompilerRS::InitSynthesisScript() {
           break;
         }
         case ParserType::Default: {
-          YosysScript(QLYosysScript);
+          YosysScript(RapidSiliconYosysDefaultScript);
           break;
         }
       }