From b831062bf146db7811e7c36c3cd8b8d37ec6927f Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain.dargelas@gmail.com>
Date: Thu, 31 Aug 2023 18:51:07 -0700
Subject: [PATCH] GHDL plugin support

---
 FOEDAG                      |  2 +-
 src/Compiler/CompilerRS.cpp | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/FOEDAG b/FOEDAG
index 9f482e029..01fc99f56 160000
--- a/FOEDAG
+++ b/FOEDAG
@@ -1 +1 @@
-Subproject commit 9f482e0291f537d6936463ff2cc07be6bfb57146
+Subproject commit 01fc99f56d289f45bc7ec0b9bc08c34538043d5d
diff --git a/src/Compiler/CompilerRS.cpp b/src/Compiler/CompilerRS.cpp
index 4182e111b..10dbbe932 100644
--- a/src/Compiler/CompilerRS.cpp
+++ b/src/Compiler/CompilerRS.cpp
@@ -94,6 +94,26 @@ plugin -i ${PLUGIN_LIB}
 
 ${PLUGIN_NAME} -tech ${MAP_TO_TECHNOLOGY} ${OPTIMIZATION} ${EFFORT} ${CARRY} ${IO} ${LIMITS} ${FSM_ENCODING} ${FAST} ${NO_FLATTEN} ${MAX_THREADS} ${NO_SIMPLIFY} ${CLKE_STRATEGY} ${CEC}
 
+${OUTPUT_NETLIST}
+
+  )";
+
+const std::string RapidSiliconYosysGhdlScript = R"( 
+# Yosys/Ghdl synthesis script for ${TOP_MODULE}
+# Read source files
+plugin -i ghdl
+read_verilog -sv ${PRIMITIVES_BLACKBOX}
+${READ_DESIGN_FILES}
+
+# Technology mapping
+hierarchy ${TOP_MODULE_DIRECTIVE}
+
+${KEEP_NAMES}
+
+plugin -i ${PLUGIN_LIB}
+
+${PLUGIN_NAME} -tech ${MAP_TO_TECHNOLOGY} ${OPTIMIZATION} ${EFFORT} ${CARRY} ${IO} ${LIMITS} ${FSM_ENCODING} ${FAST} ${NO_FLATTEN} ${MAX_THREADS} ${NO_SIMPLIFY} ${CLKE_STRATEGY} ${CEC}
+
 ${OUTPUT_NETLIST}
 
   )";
@@ -161,6 +181,7 @@ std::string CompilerRS::InitSynthesisScript() {
           break;
         }
         case ParserType::GHDL: {
+          YosysScript(RapidSiliconYosysGhdlScript);
           break;
         }
         case ParserType::Default: {