diff --git a/models_customer/verilog/TDP_RAM18KX2.v b/models_customer/verilog/TDP_RAM18KX2.v
index 7aa3219..d8e96a7 100644
--- a/models_customer/verilog/TDP_RAM18KX2.v
+++ b/models_customer/verilog/TDP_RAM18KX2.v
@@ -169,9 +169,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B1)
         if (WEN_B1) begin
@@ -210,9 +212,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -277,9 +281,11 @@ module TDP_RAM18KX2 #(
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B1)
     if (WEN_B1) begin
@@ -328,9 +334,11 @@ module TDP_RAM18KX2 #(
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   // Collision checking
     always @(posedge collision_a_write_flag) begin
@@ -472,9 +480,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B2)
         if (WEN_B2) begin
@@ -513,9 +523,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -580,9 +592,11 @@ module TDP_RAM18KX2 #(
       collision_a2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B2)
     if (WEN_B2) begin
@@ -631,9 +645,11 @@ module TDP_RAM18KX2 #(
       collision_b2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
     // Collision checking
     always @(posedge collision_a2_write_flag) begin
diff --git a/models_customer/verilog/TDP_RAM36K.v b/models_customer/verilog/TDP_RAM36K.v
index 8d1e0f6..78c88e9 100644
--- a/models_customer/verilog/TDP_RAM36K.v
+++ b/models_customer/verilog/TDP_RAM36K.v
@@ -141,9 +141,12 @@ module TDP_RAM36K #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
+
 
       always @(posedge CLK_B)
         if (WEN_B) begin
@@ -183,9 +186,11 @@ module TDP_RAM36K #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -249,9 +254,11 @@ module TDP_RAM36K #(
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B)
     if (WEN_B) begin
@@ -298,9 +305,11 @@ module TDP_RAM36K #(
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
 
 /*
diff --git a/models_internal/verilog/TDP_RAM18KX2.v b/models_internal/verilog/TDP_RAM18KX2.v
index 7aa3219..d8e96a7 100644
--- a/models_internal/verilog/TDP_RAM18KX2.v
+++ b/models_internal/verilog/TDP_RAM18KX2.v
@@ -169,9 +169,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B1)
         if (WEN_B1) begin
@@ -210,9 +212,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -277,9 +281,11 @@ module TDP_RAM18KX2 #(
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B1)
     if (WEN_B1) begin
@@ -328,9 +334,11 @@ module TDP_RAM18KX2 #(
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   // Collision checking
     always @(posedge collision_a_write_flag) begin
@@ -472,9 +480,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B2)
         if (WEN_B2) begin
@@ -513,9 +523,11 @@ module TDP_RAM18KX2 #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -580,9 +592,11 @@ module TDP_RAM18KX2 #(
       collision_a2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B2)
     if (WEN_B2) begin
@@ -631,9 +645,11 @@ module TDP_RAM18KX2 #(
       collision_b2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
     // Collision checking
     always @(posedge collision_a2_write_flag) begin
diff --git a/models_internal/verilog/TDP_RAM36K.v b/models_internal/verilog/TDP_RAM36K.v
index 8d1e0f6..78c88e9 100644
--- a/models_internal/verilog/TDP_RAM36K.v
+++ b/models_internal/verilog/TDP_RAM36K.v
@@ -141,9 +141,12 @@ module TDP_RAM36K #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
+
 
       always @(posedge CLK_B)
         if (WEN_B) begin
@@ -183,9 +186,11 @@ module TDP_RAM36K #(
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -249,9 +254,11 @@ module TDP_RAM36K #(
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B)
     if (WEN_B) begin
@@ -298,9 +305,11 @@ module TDP_RAM36K #(
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
 
 /*
diff --git a/models_internal/verilog/inc/TDP_RAM18KX2.inc.v b/models_internal/verilog/inc/TDP_RAM18KX2.inc.v
index 98a4f67..7469ba4 100644
--- a/models_internal/verilog/inc/TDP_RAM18KX2.inc.v
+++ b/models_internal/verilog/inc/TDP_RAM18KX2.inc.v
@@ -105,9 +105,11 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B1)
         if (WEN_B1) begin
@@ -146,9 +148,11 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B1 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B1 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -213,9 +217,11 @@
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B1)
     if (WEN_B1) begin
@@ -264,9 +270,11 @@
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B1 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B1 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   // Collision checking
     always @(posedge collision_a_write_flag) begin
@@ -408,9 +416,11 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
 
       always @(posedge CLK_B2)
         if (WEN_B2) begin
@@ -449,9 +459,11 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B2 <= 2'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B2 <= 2'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -516,9 +528,11 @@
       collision_a2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B2)
     if (WEN_B2) begin
@@ -567,9 +581,11 @@
       collision_b2_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B2 <= 16'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B2 <= 16'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
     // Collision checking
     always @(posedge collision_a2_write_flag) begin
diff --git a/models_internal/verilog/inc/TDP_RAM36K.inc.v b/models_internal/verilog/inc/TDP_RAM36K.inc.v
index a67737f..1c1e33e 100644
--- a/models_internal/verilog/inc/TDP_RAM36K.inc.v
+++ b/models_internal/verilog/inc/TDP_RAM36K.inc.v
@@ -103,9 +103,12 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_A <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_A <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
+
 
       always @(posedge CLK_B)
         if (WEN_B) begin
@@ -145,9 +148,11 @@
           end
         end
         else
-          // verilator lint_off BLKANDNBLK
-          RPARITY_B <= 4'bx;
-          // verilator lint_on BLKANDNBLK
+          `ifndef FIFO
+            // verilator lint_off BLKANDNBLK
+            RPARITY_B <= 4'bx;
+            // verilator lint_on BLKANDNBLK
+          `endif
     end
   endgenerate
 
@@ -211,9 +216,11 @@
       collision_a_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_A <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_A <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
   always @(posedge CLK_B)
     if (WEN_B) begin
@@ -260,9 +267,11 @@
       collision_b_read_flag = 0;
     end
     else
-      // verilator lint_off BLKANDNBLK
-      RDATA_B <= 32'bx;
-      // verilator lint_on BLKANDNBLK
+      `ifndef FIFO
+        // verilator lint_off BLKANDNBLK
+        RDATA_B <= 32'bx;
+        // verilator lint_on BLKANDNBLK
+      `endif
 
 
 /*
diff --git a/models_internal/verilog/tb/TDP_RAM18KX2_tb.v b/models_internal/verilog/tb/TDP_RAM18KX2_tb.v
index 747a86e..edab870 100644
--- a/models_internal/verilog/tb/TDP_RAM18KX2_tb.v
+++ b/models_internal/verilog/tb/TDP_RAM18KX2_tb.v
@@ -691,7 +691,7 @@ begin
 end
 endtask
 
-task compare(input reg [RAM1_DATA_WIDTH-1:0] dout, exp_dout, input reg [RAM1_ADDR_WIDTH-1:0] addr, input reg parity);
+task compare(input bit [RAM1_DATA_WIDTH-1:0] dout, exp_dout, input bit [RAM1_ADDR_WIDTH-1:0] addr, input bit parity);
 	if (RAM1_PARITY_WIDTH < 1 && parity == 1)
 		exp_dout = 0;
 	if(dout !== exp_dout) begin
@@ -708,7 +708,7 @@ task compare(input reg [RAM1_DATA_WIDTH-1:0] dout, exp_dout, input reg [RAM1_ADD
 			$display("Data:: Write/Read MATCHED. Address: %0h, DUT_Out: %0h, Exp_Out: %0h, Time: %0t", addr, dout, exp_dout,$time);
 endtask
 
-task compare_RAM2(input reg [RAM2_DATA_WIDTH-1:0] dout, exp_dout, input reg [RAM2_ADDR_WIDTH-1:0] addr, input reg parity);
+task compare_RAM2(input bit [RAM2_DATA_WIDTH-1:0] dout, exp_dout, input bit [RAM2_ADDR_WIDTH-1:0] addr, input bit parity);
 	if (RAM2_PARITY_WIDTH < 1 && parity == 1)
 		exp_dout = 0;
 	if(dout !== exp_dout) begin
diff --git a/models_internal/verilog/tb/TDP_RAM36K_tb.v b/models_internal/verilog/tb/TDP_RAM36K_tb.v
index 5797d60..ff9963b 100644
--- a/models_internal/verilog/tb/TDP_RAM36K_tb.v
+++ b/models_internal/verilog/tb/TDP_RAM36K_tb.v
@@ -31,10 +31,10 @@ module TDP_RAM36K_tb();
 	/* verilator lint_off WIDTHCONCAT */
   parameter [4095:0] INIT_PARITY = {4096{1'b0}}; // Initial Contents of memory
 	/* verilator lint_on WIDTHCONCAT */
-  parameter WRITE_WIDTH_A = 36; // Write data width on port A (1-36)
-  parameter READ_WIDTH_A = 	36; // Read data width on port A (1-36)
-  parameter WRITE_WIDTH_B = 36; // Write data width on port B (1-36)
-  parameter READ_WIDTH_B = 	36; // Read data width on port B (1-36)
+  parameter WRITE_WIDTH_A = 18; // Write data width on port A (1-36)
+  parameter READ_WIDTH_A = 	18; // Read data width on port A (1-36)
+  parameter WRITE_WIDTH_B = 18; // Write data width on port B (1-36)
+  parameter READ_WIDTH_B = 	18; // Read data width on port B (1-36)
 
 	//Local_RAM
   localparam A_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A);
@@ -612,7 +612,7 @@ begin
 end
 endtask
 
-task compare(input reg [RAM_DATA_WIDTH-1:0] dout, exp_dout, input reg [RAM_ADDR_WIDTH-1:0] addr, input reg parity);
+task compare(input bit [RAM_DATA_WIDTH-1:0] dout, exp_dout, input bit [RAM_ADDR_WIDTH-1:0] addr, input bit parity);
 	if (RAM_PARITY_WIDTH < 1 && parity == 1)
 		exp_dout = 0;
 	if(dout !== exp_dout) begin