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Merge pull request #56 from AllahWasya/main
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updated overflow and underflow logic in Async FIFO model
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@muhammadhamza15
muhammadhamza15 authored Aug 21, 2024
2 parents ae2581a + b48c047 commit 863acb3
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Showing 2 changed files with 56 additions and 94 deletions.
75 changes: 28 additions & 47 deletions models_internal/verilog/FIFO36K.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,6 @@ module FIFO36K #(
output reg UNDERFLOW = 1'b0 // FIFO underflow error flag
);


if ( FIFO_TYPE == "SYNCHRONOUS" ) begin: SYNCRONOUS


Expand Down Expand Up @@ -195,7 +194,7 @@ if ( FIFO_TYPE == "SYNCHRONOUS" ) begin: SYNCRONOUS

else begin: ASYNCRONOUS // ASYNCRONOUS LOGIC

reg fwft = 1'b0;
reg fwft = 1'b0;


localparam DATA_WIDTH_WRITE = DATA_WRITE_WIDTH;
Expand Down Expand Up @@ -233,7 +232,7 @@ parameter W_PTR_WIDTH = $clog2(fifo_depth_write);
parameter R_PTR_WIDTH = $clog2(fifo_depth_read);

wire [W_PTR_WIDTH:0] b_wptr_sync, b_wptr_w;
wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w, b_rptr_w1;
wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w;


TDP_RAM36K #(
Expand Down Expand Up @@ -294,7 +293,7 @@ wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w, b_rptr_w1;

if(DATA_WIDTH_WRITE==36) begin
assign ram_wr_data = {{36-DATA_WIDTH_WRITE{1'b0}}, WR_DATA[DATA_WIDTH_WRITE-5:0]};
assign ram_wr_parity = {2'b00, WR_DATA[DATA_WIDTH_WRITE-1:DATA_WIDTH_WRITE-2]};
assign ram_wr_parity = {2'b00, WR_DATA[DATA_WIDTH_WRITE-1:DATA_WIDTH_WRITE-4]};
end


Expand Down Expand Up @@ -356,15 +355,6 @@ assign b_rptr_sync = d_out2;

assign b_wptr_w = b_wptr;

reg [2:0] rem,rem1, rem2, rem3;

always @(posedge WR_CLK) begin
rem1 <= b_wptr_next%(SCALING_FACTOR_WPTR);
end

always @(posedge WR_CLK) begin
rem2 <= b_rptr_sync%(SCALING_FACTOR_WPTR);
end

assign diff_ptr0 =(DATA_WIDTH_WRITE>DATA_WIDTH_READ)? /* W>R */ ((((b_wptr_next/SCALING_FACTOR_WPTR >= (b_rptr_sync/SCALING_FACTOR_RPTR))? (b_wptr_next/SCALING_FACTOR_WPTR-(b_rptr_sync/SCALING_FACTOR_RPTR)): (b_wptr_next/SCALING_FACTOR_WPTR+(1<<(W_PTR_WIDTH+1))-(b_rptr_sync/SCALING_FACTOR_RPTR)))))

Expand Down Expand Up @@ -431,7 +421,6 @@ always @(*) begin
end

assign b_rptr_w = b_rptr_next;
assign b_rptr_w1 = b_rptr;

assign diff_ptr1 = (DATA_WIDTH_WRITE > DATA_WIDTH_READ)? ( ((b_wptr_sync/SCALING_FACTOR_WPTR) >= (b_rptr_next/SCALING_FACTOR_RPTR))? (b_wptr_sync/SCALING_FACTOR_WPTR-(b_rptr_next/SCALING_FACTOR_RPTR)): (b_wptr_sync/SCALING_FACTOR_WPTR+(1<<(W_PTR_WIDTH+1))-(b_rptr_next/SCALING_FACTOR_RPTR)))

Expand Down Expand Up @@ -503,12 +492,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -2
if (DATA_WIDTH_WRITE == 9 && DATA_WIDTH_READ==18) begin

if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097 ) begin
fwft_data [7:0] <= WR_DATA[7:0] ;
Expand All @@ -522,12 +513,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -3
if (DATA_WIDTH_WRITE == 9 && DATA_WIDTH_READ==36) begin

if(b_wptr_next==4 || b_wptr_next==8196 || b_wptr_next==4100) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==4 || b_wptr_next==8196 || b_wptr_next==4100) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097) begin
fwft_data [7:0] <= WR_DATA[7:0];
Expand All @@ -550,12 +543,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -4
if (DATA_WIDTH_WRITE == 18 && DATA_WIDTH_READ==36) begin

if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097 ) begin
fwft_data [15:0] <= WR_DATA[15:0];
Expand All @@ -582,7 +577,7 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH

/*---------------------------------------------------------------*/

/*------------ Adding logic of OVERFLOW and UNDERFLOW -----------*/
/*--------- Adding logic of OVERFLOW and UNDERFLOW -----------*/

always @(posedge WR_CLK) begin
if (RESET) begin
Expand All @@ -591,9 +586,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (FULL & WR_EN ) begin
OVERFLOW <= 1;
end
else begin
OVERFLOW <= OVERFLOW;
end
end

always @(posedge RD_CLK) begin
Expand All @@ -603,9 +595,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if(RD_EN & OVERFLOW) begin
OVERFLOW <= 0;
end
else begin
OVERFLOW <= OVERFLOW;
end
end

always @(posedge RD_CLK) begin
Expand All @@ -616,10 +605,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (EMPTY & RD_EN) begin
UNDERFLOW <= 1;
end
else begin
UNDERFLOW <= UNDERFLOW;
end

end

always @(posedge WR_CLK) begin
Expand All @@ -629,13 +614,9 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (EMPTY & WR_EN ) begin
UNDERFLOW <= 0;
end
else begin
UNDERFLOW <= UNDERFLOW;
end
end

end : ASYNCRONOUS

initial begin
case(DATA_WRITE_WIDTH)
9 ,
Expand Down
75 changes: 28 additions & 47 deletions models_internal/verilog/inc/FIFO36K.inc.v
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@


if ( FIFO_TYPE == "SYNCHRONOUS" ) begin: SYNCRONOUS


Expand Down Expand Up @@ -163,7 +162,7 @@ if ( FIFO_TYPE == "SYNCHRONOUS" ) begin: SYNCRONOUS

else begin: ASYNCRONOUS // ASYNCRONOUS LOGIC

reg fwft = 1'b0;
reg fwft = 1'b0;


localparam DATA_WIDTH_WRITE = DATA_WRITE_WIDTH;
Expand Down Expand Up @@ -201,7 +200,7 @@ parameter W_PTR_WIDTH = $clog2(fifo_depth_write);
parameter R_PTR_WIDTH = $clog2(fifo_depth_read);

wire [W_PTR_WIDTH:0] b_wptr_sync, b_wptr_w;
wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w, b_rptr_w1;
wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w;


TDP_RAM36K #(
Expand Down Expand Up @@ -262,7 +261,7 @@ wire [R_PTR_WIDTH:0] b_rptr_sync, b_rptr_w, b_rptr_w1;

if(DATA_WIDTH_WRITE==36) begin
assign ram_wr_data = {{36-DATA_WIDTH_WRITE{1'b0}}, WR_DATA[DATA_WIDTH_WRITE-5:0]};
assign ram_wr_parity = {2'b00, WR_DATA[DATA_WIDTH_WRITE-1:DATA_WIDTH_WRITE-2]};
assign ram_wr_parity = {2'b00, WR_DATA[DATA_WIDTH_WRITE-1:DATA_WIDTH_WRITE-4]};
end


Expand Down Expand Up @@ -324,15 +323,6 @@ assign b_rptr_sync = d_out2;

assign b_wptr_w = b_wptr;

reg [2:0] rem,rem1, rem2, rem3;

always @(posedge WR_CLK) begin
rem1 <= b_wptr_next%(SCALING_FACTOR_WPTR);
end

always @(posedge WR_CLK) begin
rem2 <= b_rptr_sync%(SCALING_FACTOR_WPTR);
end

assign diff_ptr0 =(DATA_WIDTH_WRITE>DATA_WIDTH_READ)? /* W>R */ ((((b_wptr_next/SCALING_FACTOR_WPTR >= (b_rptr_sync/SCALING_FACTOR_RPTR))? (b_wptr_next/SCALING_FACTOR_WPTR-(b_rptr_sync/SCALING_FACTOR_RPTR)): (b_wptr_next/SCALING_FACTOR_WPTR+(1<<(W_PTR_WIDTH+1))-(b_rptr_sync/SCALING_FACTOR_RPTR)))))

Expand Down Expand Up @@ -399,7 +389,6 @@ always @(*) begin
end

assign b_rptr_w = b_rptr_next;
assign b_rptr_w1 = b_rptr;

assign diff_ptr1 = (DATA_WIDTH_WRITE > DATA_WIDTH_READ)? ( ((b_wptr_sync/SCALING_FACTOR_WPTR) >= (b_rptr_next/SCALING_FACTOR_RPTR))? (b_wptr_sync/SCALING_FACTOR_WPTR-(b_rptr_next/SCALING_FACTOR_RPTR)): (b_wptr_sync/SCALING_FACTOR_WPTR+(1<<(W_PTR_WIDTH+1))-(b_rptr_next/SCALING_FACTOR_RPTR)))

Expand Down Expand Up @@ -471,12 +460,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -2
if (DATA_WIDTH_WRITE == 9 && DATA_WIDTH_READ==18) begin

if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097 ) begin
fwft_data [7:0] <= WR_DATA[7:0] ;
Expand All @@ -490,12 +481,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -3
if (DATA_WIDTH_WRITE == 9 && DATA_WIDTH_READ==36) begin

if(b_wptr_next==4 || b_wptr_next==8196 || b_wptr_next==4100) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==4 || b_wptr_next==8196 || b_wptr_next==4100) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097) begin
fwft_data [7:0] <= WR_DATA[7:0];
Expand All @@ -518,12 +511,14 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
// -4
if (DATA_WIDTH_WRITE == 18 && DATA_WIDTH_READ==36) begin

if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
fwft=1;
end
else begin
fwft=fwft;
end
// if(b_wptr_next==2 || b_wptr_next==4098 || b_wptr_next==2049) begin
// fwft=1;
// end
// else begin
// fwft=fwft;
// end

fwft <= (EMPTY && WR_EN && !fwft)? 1 : fwft;

if(b_wptr_next==1 || b_wptr_next==4097 ) begin
fwft_data [15:0] <= WR_DATA[15:0];
Expand All @@ -550,7 +545,7 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH

/*---------------------------------------------------------------*/

/*------------ Adding logic of OVERFLOW and UNDERFLOW -----------*/
/*--------- Adding logic of OVERFLOW and UNDERFLOW -----------*/

always @(posedge WR_CLK) begin
if (RESET) begin
Expand All @@ -559,9 +554,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (FULL & WR_EN ) begin
OVERFLOW <= 1;
end
else begin
OVERFLOW <= OVERFLOW;
end
end

always @(posedge RD_CLK) begin
Expand All @@ -571,9 +563,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if(RD_EN & OVERFLOW) begin
OVERFLOW <= 0;
end
else begin
OVERFLOW <= OVERFLOW;
end
end

always @(posedge RD_CLK) begin
Expand All @@ -584,10 +573,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (EMPTY & RD_EN) begin
UNDERFLOW <= 1;
end
else begin
UNDERFLOW <= UNDERFLOW;
end

end

always @(posedge WR_CLK) begin
Expand All @@ -597,10 +582,6 @@ assign p_empty = (diff_ptr1 ==PROG_EMPTY_THRESH || diff_ptr1 <=PROG_EMPTY_THRESH
else if (EMPTY & WR_EN ) begin
UNDERFLOW <= 0;
end
else begin
UNDERFLOW <= UNDERFLOW;
end
end

end : ASYNCRONOUS

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