diff --git a/Makefile b/Makefile index 122199b..24c0cf9 100644 --- a/Makefile +++ b/Makefile @@ -34,7 +34,7 @@ bb_models: $(BB_TARGETS) # we need to make TDP_RAM36K.v first as it is used by the FIFO. core_sim_models: models_internal/verilog/TDP_RAM36K.v -sim_models: core_sim_models $(SIM_TARGETS) $(CUST_SIM_TARGETS) +sim_models: core_sim_models $(SIM_TARGETS) #$(CUST_SIM_TARGETS) models_internal/verilog_blackbox/rundir/%.v: specs/%.yaml mkdir -p models_internal/verilog_blackbox/rundir diff --git a/bin/p4def_to_simv.py b/bin/p4def_to_simv.py index b4043a2..e287f12 100755 --- a/bin/p4def_to_simv.py +++ b/bin/p4def_to_simv.py @@ -316,9 +316,10 @@ def main(): if has_parameters and has_properties: outstr += f"module {name} #(\n " outstr += param_str - outstr += "`ifdef RAPIDSILICON_INTERNAL\n ," + #outstr += "`ifdef RAPIDSILICON_INTERNAL\n ," + outstr += "," outstr += prop_str - outstr += "`endif // RAPIDSILICON_INTERNAL\n" + #outstr += "`endif // RAPIDSILICON_INTERNAL\n" outstr += ") (\n" stream.write(outstr) @@ -330,11 +331,11 @@ def main(): if not has_parameters and has_properties: outstr += f"module {name}\n" - outstr += "`ifdef RAPIDSILICON_INTERNAL\n " + #outstr += "`ifdef RAPIDSILICON_INTERNAL\n " outstr += "#(\n" outstr += prop_str outstr += ")\n" - outstr += "`endif // RAPIDSILICON_INTERNAL\n" + #outstr += "`endif // RAPIDSILICON_INTERNAL\n" outstr += "(\n" stream.write(outstr) @@ -475,7 +476,7 @@ def main(): # property checking if 'properties' in spec_dict: - stream.write('\n`ifdef RAPIDSILICON_INTERNAL\n') + #stream.write('\n`ifdef RAPIDSILICON_INTERNAL\n') for param in spec_dict["properties"]: # determine if property is numeric or not @@ -514,7 +515,7 @@ def main(): stream.write(" end\n") stream.write(" endcase\n") - stream.write('`endif // RAPIDSILICON_INTERNAL\n') + #stream.write('`endif // RAPIDSILICON_INTERNAL\n') if needs_checking(spec_dict): stream.write("\n end\n") diff --git a/etc/bb.mako b/etc/bb.mako index 320f139..86c5c2d 100644 --- a/etc/bb.mako +++ b/etc/bb.mako @@ -130,9 +130,9 @@ def generate_port_str(port): % if has_parameters and has_properties: module ${dd['name']} #( ${param_str} -`ifdef RAPIDSILICON_INTERNAL - , ${prop_str} -`endif // RAPIDSILICON_INTERNAL +##`ifdef RAPIDSILICON_INTERNAL +,${prop_str} +##`endif // RAPIDSILICON_INTERNAL ) ( % endif ## ONLY PARAMETERS @@ -144,11 +144,11 @@ ${param_str} ## ONLY PROPERTIES % if not has_parameters and has_properties: module ${dd['name']} -`ifdef RAPIDSILICON_INTERNAL +##`ifdef RAPIDSILICON_INTERNAL #( ${prop_str} ) -`endif // RAPIDSILICON_INTERNAL +##`endif // RAPIDSILICON_INTERNAL ( % endif ## NEITHER PARAMETERS NOR PROPERTIES diff --git a/models_customer/README.txt b/models_customer/README.txt deleted file mode 100644 index 40bdd15..0000000 --- a/models_customer/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -This directory holds simulation models for the customer. These should -not include internal code guarded by RAPIDSILICON_INTERNAL macro. diff --git a/models_customer/ibis/GeminiPlus-0.0.1.tar.gz b/models_customer/ibis/GeminiPlus-0.0.1.tar.gz deleted file mode 100644 index 6ed2dc2..0000000 Binary files a/models_customer/ibis/GeminiPlus-0.0.1.tar.gz and /dev/null differ diff --git a/models_customer/verilog/BOOT_CLOCK.v b/models_customer/verilog/BOOT_CLOCK.v deleted file mode 100644 index 07fcf82..0000000 --- a/models_customer/verilog/BOOT_CLOCK.v +++ /dev/null @@ -1,29 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// BOOT_CLOCK simulation model -// Internal BOOT_CLK connection -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module BOOT_CLOCK #( - parameter PERIOD = 25.0 // Clock period for simulation purposes (nS) -) ( - output reg O = 1'b0 // Clock output -); -localparam HALF_PERIOD = PERIOD/2.0; - - - always - #HALF_PERIOD O <= ~O; - initial begin - - if ((PERIOD < 16.0) || (PERIOD > 30.0)) begin - $fatal(1,"BOOT_CLOCK instance %m PERIOD set to incorrect value, %f. Values must be between 16.0 and 30.0.", PERIOD); - end - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/CARRY.v b/models_customer/verilog/CARRY.v deleted file mode 100644 index e9fba50..0000000 --- a/models_customer/verilog/CARRY.v +++ /dev/null @@ -1,20 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// CARRY simulation model -// FLE carry logic -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module CARRY ( - input P, // Partial data input - input G, // Partial data input - input CIN, // Carry in - output O, // Data output - output COUT // Carry out -); - - assign {COUT, O} = {P ? CIN : G, P ^ CIN}; -endmodule -`endcelldefine diff --git a/models_customer/verilog/CLK_BUF.v b/models_customer/verilog/CLK_BUF.v deleted file mode 100644 index ace2a8b..0000000 --- a/models_customer/verilog/CLK_BUF.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// CLK_BUF simulation model -// Global clock buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module CLK_BUF ( - input I, // Clock input - output O // Clock output -); - - assign O = I ; - -endmodule -`endcelldefine diff --git a/models_customer/verilog/DFFNRE.v b/models_customer/verilog/DFFNRE.v deleted file mode 100644 index 30c8828..0000000 --- a/models_customer/verilog/DFFNRE.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// DFFNRE simulation model -// Negedge D flipflop with async reset and enable -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -// No prologue needed. -module DFFNRE ( - input D, // Data Input - input R, // Active-low, asynchronous reset - input E, // Active-high enable - input C, // Negedge clock - output reg Q = 1'b0 // Data Output -); - - always @(negedge C, negedge R) - if (!R) - Q <= 1'b0; - else if (E) - Q <= D; - -endmodule -`endcelldefine diff --git a/models_customer/verilog/DFFRE.v b/models_customer/verilog/DFFRE.v deleted file mode 100644 index 33964db..0000000 --- a/models_customer/verilog/DFFRE.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// DFFRE simulation model -// Posedge D flipflop with async reset and enable -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -// No prologue needed. -module DFFRE ( - input D, // Data Input - input R, // Active-low, asynchronous reset - input E, // Active-high enable - input C, // Clock - output reg Q = 1'b0 // Data Output -); - - always @(posedge C, negedge R) - if (!R) - Q <= 1'b0; - else if (E) - Q <= D; - -endmodule -`endcelldefine diff --git a/models_customer/verilog/DSP19X2.v b/models_customer/verilog/DSP19X2.v deleted file mode 100644 index 3761c34..0000000 --- a/models_customer/verilog/DSP19X2.v +++ /dev/null @@ -1,432 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// DSP19X2 simulation model -// Paramatizable dual 10x9-bit multiplier accumulator -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module DSP19X2 #( - parameter DSP_MODE = "MULTIPLY_ACCUMULATE", // DSP arithmetic mode (MULTIPLY/MULTIPLY_ACCUMULATE) - parameter [9:0] COEFF1_0 = 10'h000, // Multiplier 1 10-bit A input coefficient 0 - parameter [9:0] COEFF1_1 = 10'h000, // Multiplier 1 10-bit A input coefficient 1 - parameter [9:0] COEFF1_2 = 10'h000, // Multiplier 1 10-bit A input coefficient 2 - parameter [9:0] COEFF1_3 = 10'h000, // Multiplier 1 10-bit A input coefficient 3 - parameter [9:0] COEFF2_0 = 10'h000, // Multiplier 2 10-bit A input coefficient 0 - parameter [9:0] COEFF2_1 = 10'h000, // Multiplier 2 10-bit A input coefficient 1 - parameter [9:0] COEFF2_2 = 10'h000, // Multiplier 2 10-bit A input coefficient 2 - parameter [9:0] COEFF2_3 = 10'h000, // Multiplier 2 10-bit A input coefficient 3 - parameter OUTPUT_REG_EN = "TRUE", // Enable output register (TRUE/FALSE) - parameter INPUT_REG_EN = "TRUE" // Enable input register (TRUE/FALSE) -) ( - input [9:0] A1, // Multiplier 1 10-bit data input for multiplier or accumulator loading - input [8:0] B1, // 9-bit data input for multiplication - output [18:0] Z1, // Multiplier 1 19-bit data output - output [8:0] DLY_B1, // Multiplier 1 9-bit B registered output - input [9:0] A2, // Multiplier 2 10-bit data input for multiplier or accumulator loading - input [8:0] B2, // Multiplier 2 9-bit data input for multiplication - output [18:0] Z2, // Multiplier 2 19-bit data output - output [8:0] DLY_B2, // Multiplier 2 9-bit B registered output - input CLK, // Clock - input RESET, // Reset input - input [4:0] ACC_FIR, // 5-bit left shift A input - input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient - input LOAD_ACC, // Load accumulator input - input UNSIGNED_A, // Selects signed or unsigned data for A input - input UNSIGNED_B, // Selects signed or unsigned data for B input - input SATURATE, // Saturate enable - input [4:0] SHIFT_RIGHT, // 5-bit Shift right - input ROUND, // Round - input SUBTRACT // Add or subtract -); - - - // registers - reg subtract_reg = 1'b0; - reg [4:0] acc_fir_reg = 5'h00; - reg [2:0] feedback_reg = 3'h0; - reg [4:0] shift_right_reg1 = 5'h00; - reg [4:0] shift_right_reg2 = 5'h00; - reg round_reg1 = 1'b0; - reg round_reg2 = 1'b0; - reg saturate_reg1 = 1'b0; - reg saturate_reg2 = 1'b0; - reg load_acc_reg = 1'b0; - reg [9:0] a1_reg = 10'h000; - reg [9:0] a2_reg = 10'h000; - reg [8:0] b1_reg = 9'h000; - reg [8:0] b2_reg = 9'h000; - reg unsigned_a_reg = 1'b1; - reg unsigned_b_reg = 1'b1; -////////////////////////////////////////////////////////////// - reg subtract_int = 1'b0; - reg [4:0] acc_fir_int = 5'h00; - reg [2:0] feedback_int = 3'h0; - reg [4:0] shift_right_int = 5'h00; - reg round_int = 1'b0; - reg saturate_int = 1'b0; - reg load_acc_int = 1'b0; - reg [9:0] a1_int = 10'h000; - reg [9:0] a2_int = 10'h000; - reg [8:0] b1_int = 9'h000; - reg [8:0] b2_int = 9'h000; - reg unsigned_a_int = 1'b1; - reg unsigned_b_int = 1'b1; - reg signed [63:0] accumulator = 64'h0000000000000000; - reg signed [63:0] add_sub_in = 64'h0000000000000000; - reg signed [63:0] mult_out = 64'h0000000000000000; - reg signed [31:0] mult_out1 = 32'h00000000; - reg signed [31:0] mult_out2 = 32'h00000000; - reg signed [63:0] add_sub_out = 64'h0000000000000000; - reg signed [63:0] pre_shift = 64'h0000000000000000; - reg signed [31:0] shift_right_f0 = 32'h00000000; - reg signed [31:0] shift_right_f1 = 32'h00000000; - reg signed [31:0] round_f0 = 32'h00000000; - reg signed [31:0] round_f1 = 32'h00000000; - reg signed [18:0] saturate_f0 = 19'h00000; - reg signed [18:0] saturate_f1 = 19'h00000; - reg [37:0] z_out = 38'h0000000000; - reg [37:0] z_out_reg = 38'h0000000000; - reg [8:0] dly_b1 = 9'h000; - reg [8:0] dly_b2 = 9'h000; - - - - reg [9:0] mult_a1 = 10'h000; - reg [9:0] mult_a2 = 10'h000; - reg [8:0] mult_b1 = 9'h000; - reg [8:0] mult_b2 = 9'h000; - - // pipelining - always @(posedge CLK or posedge RESET) - begin - if (RESET) - begin - subtract_reg <= 1'b0; - acc_fir_reg <= 6'h00; - feedback_reg <= 1'b0; - shift_right_reg1 <= 6'h00; - shift_right_reg2 <= 6'h00; - round_reg1 <= 1'b0; - round_reg2 <= 1'b0; - saturate_reg1 <= 1'b0; - saturate_reg2 <= 1'b0; - load_acc_reg <= 1'b0; - a1_reg <= 10'h000; - a2_reg <= 10'h000; - b1_reg <= 9'h000; - b2_reg <= 9'h000; - unsigned_a_reg <= 1'b1; - unsigned_b_reg <= 1'b1; - end - else - begin - subtract_reg <= SUBTRACT; - acc_fir_reg <= ACC_FIR; - feedback_reg <= FEEDBACK; - shift_right_reg1 <= SHIFT_RIGHT; - shift_right_reg2 <= shift_right_reg1; - round_reg1 <= ROUND; - round_reg2 <= round_reg1; - saturate_reg1 <= SATURATE; - saturate_reg2 <= saturate_reg1; - load_acc_reg <= LOAD_ACC; - a1_reg <= A1; - a2_reg <= A2; - b1_reg <= B1; - b2_reg <= B2; - unsigned_a_reg <= UNSIGNED_A; - unsigned_b_reg <= UNSIGNED_B; - - - end - end - - always @(*) - begin - if (INPUT_REG_EN == "TRUE") - begin - a1_int = a1_reg; - a2_int = a2_reg; - b1_int = b1_reg; - b2_int = b2_reg; - subtract_int = subtract_reg; - acc_fir_int = acc_fir_reg; - feedback_int = feedback_reg; - load_acc_int = load_acc_reg; - unsigned_a_int = unsigned_a_reg; - unsigned_b_int = unsigned_b_reg; - shift_right_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?shift_right_reg2:shift_right_reg1; - round_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?round_reg2:round_reg1; - saturate_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?saturate_reg2:saturate_reg1; - end - else - begin - a1_int = A1; - a2_int = A2; - b1_int = B1; - b2_int = B2; - subtract_int = SUBTRACT; - acc_fir_int = ACC_FIR; - feedback_int = FEEDBACK; - load_acc_int = LOAD_ACC; - unsigned_a_int = UNSIGNED_A; - unsigned_b_int = UNSIGNED_B; - shift_right_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?shift_right_reg1:SHIFT_RIGHT; - round_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?round_reg1:ROUND; - saturate_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?saturate_reg1:SATURATE; - - end - end - - // Feedback paths - always @(*) - begin - case (feedback_int) - 3'b000: begin - mult_a1 = a1_int; - mult_b1 = b1_int; - mult_a2 = a2_int; - mult_b2 = b2_int; - add_sub_in = accumulator; - end - 3'b001: begin - mult_a1 = a1_int; - mult_b1 = b1_int; - mult_a2 = a2_int; - mult_b2 = b2_int; - add_sub_in = 64'h0000000000000000; - end - 3'b010: begin - mult_a1 = a1_int; - mult_b1 = 9'h000; - mult_a2 = a2_int; - mult_b2 = 9'h000; - add_sub_in = (unsigned_a_int)?{({{22{1'b0}},a2_int}<>> shift_right_int; - shift_right_f1 = pre_shift[63:32] >>> shift_right_int; - round_f0 = (round_int && shift_right_int>0)? (pre_shift[shift_right_int-1]==1)?shift_right_f0+1:shift_right_f0:shift_right_f0; - round_f1 = (round_int && shift_right_int>0)? (pre_shift[(shift_right_int+32)-1]==1)?shift_right_f1+1:shift_right_f1:shift_right_f1; - - if(saturate_int) - begin - if(unsigned_a_int && unsigned_b_int) - begin - if($signed(round_f0)<0) - saturate_f0 = 19'h00000; - else if($signed(round_f0)>19'h7ffff) - saturate_f0 = 19'h7ffff; - else - saturate_f0 = round_f0; - - if($signed(round_f1)<0) - saturate_f1 = 19'h00000; - else if($signed(round_f1)>19'h7ffff) - saturate_f1 = 19'h7ffff; - else - saturate_f1 = round_f1; - end - else - begin - if($signed(round_f0)>$signed(19'h3ffff)) - saturate_f0 = 19'h3ffff; - else if($signed(round_f0)<$signed(19'h40000)) - saturate_f0 = 19'h40000; - else - saturate_f0 = round_f0; - - if($signed(round_f1)>$signed(19'h3ffff)) - saturate_f1 = 19'h3ffff; - else if($signed(round_f1)<$signed(19'h40000)) - saturate_f1 = 19'h40000; - else - saturate_f1 = round_f1; - end - - end - else - begin - saturate_f0 = round_f0; - saturate_f1 = round_f1; - end - z_out = (DSP_MODE== "MULTIPLY")? {mult_out[50:32],mult_out[18:0]}:{saturate_f1,saturate_f0}; - end - - - // output register - always @(posedge CLK or posedge RESET) - begin - if(RESET) - begin - dly_b1 <= 9'h000; - dly_b2 <= 9'h000; - z_out_reg <= 38'h0000000000; - end - else - begin - dly_b1 <= B1; - dly_b2 <= B2; - z_out_reg <= z_out; - end - end - - assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0]; - assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19]; - assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx; - assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx; - - `ifndef SYNTHESIS - // If ACC_FIR is greater than 21, result is invalid - always @(ACC_FIR) - if (ACC_FIR > 21) - begin - $fatal(1,"\nERROR: DSP19x2 instance %m ACC_FIR input is %d which is greater than 21 which serves no function", ACC_FIR); - end - // If SHIFT_RIGHT is greater than 31, result is invalid - always @(SHIFT_RIGHT) - if (SHIFT_RIGHT > 31) - begin - $fatal(1,"\nERROR: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT); - end - - always@(*) - begin - case(DSP_MODE) - "MULTIPLY_ACCUMULATE": begin - if(FEEDBACK>1) - $fatal(1,"\nERROR: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK); - end - endcase - - end - `endif // `ifndef SYNTHESIS - - initial begin - case(DSP_MODE) - "MULTIPLY" , - "MULTIPLY_ADD_SUB" , - "MULTIPLY_ACCUMULATE": begin end - default: begin - $fatal(1,"\nError: DSP19X2 instance %m has parameter DSP_MODE set to %s. Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE); - end - endcase - case(OUTPUT_REG_EN) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: DSP19X2 instance %m has parameter OUTPUT_REG_EN set to %s. Valid values are TRUE, FALSE\n", OUTPUT_REG_EN); - end - endcase - case(INPUT_REG_EN) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: DSP19X2 instance %m has parameter INPUT_REG_EN set to %s. Valid values are TRUE, FALSE\n", INPUT_REG_EN); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/DSP38.v b/models_customer/verilog/DSP38.v deleted file mode 100644 index f1c3300..0000000 --- a/models_customer/verilog/DSP38.v +++ /dev/null @@ -1,342 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// DSP38 simulation model -// Paramatizable 20x18-bit multiplier accumulator -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module DSP38 #( - parameter DSP_MODE = "MULTIPLY_ACCUMULATE", // DSP arithmetic mode (MULTIPLY/MULTIPLY_ADD_SUB/MULTIPLY_ACCUMULATE) - parameter [19:0] COEFF_0 = 20'h00000, // 20-bit A input coefficient 0 - parameter [19:0] COEFF_1 = 20'h00000, // 20-bit A input coefficient 1 - parameter [19:0] COEFF_2 = 20'h00000, // 20-bit A input coefficient 2 - parameter [19:0] COEFF_3 = 20'h00000, // 20-bit A input coefficient 3 - parameter OUTPUT_REG_EN = "TRUE", // Enable output register (TRUE/FALSE) - parameter INPUT_REG_EN = "TRUE" // Enable input register (TRUE/FALSE) -) ( - input [19:0] A, // 20-bit data input for multipluier or accumulator loading - input [17:0] B, // 18-bit data input for multiplication - input [5:0] ACC_FIR, // 6-bit left shift A input - output [37:0] Z, // 38-bit data output - output reg [17:0] DLY_B, // 18-bit B registered output - input CLK, // Clock - input RESET, // Active high reset - input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient - input LOAD_ACC, // Load accumulator input - input SATURATE, // Saturate enable - input [5:0] SHIFT_RIGHT, // 6-bit Shift right - input ROUND, // Round - input SUBTRACT, // Add or subtract - input UNSIGNED_A, // Selects signed or unsigned data for A input - input UNSIGNED_B // Selects signed or unsigned data for B input -); - - - // registers - reg subtract_reg = 1'b0; - reg [5:0] acc_fir_reg = 6'h00; - reg [2:0] feedback_reg = 3'h0; - reg [5:0] shift_right_reg1 = 6'h00; - reg [5:0] shift_right_reg2 = 6'h00; - reg round_reg1 = 1'b0; - reg round_reg2 = 1'b0; - reg saturate_reg1 = 1'b0; - reg saturate_reg2 = 1'b0; - reg load_acc_reg = 1'b0; - reg [19:0] a_reg = 20'h00000; - reg [17:0] b_reg = 18'h00000; - reg unsigned_a_reg = 1'b1; - reg unsigned_b_reg = 1'b1; - - - - reg subtract_int = 1'b0; - reg [5:0] acc_fir_int = 6'h00; - reg [2:0] feedback_int = 3'h0; - reg [5:0] shift_right_int = 6'h00; - reg round_int = 1'b0; - reg saturate_int = 1'b0; - reg load_acc_int = 1'b0; - reg [19:0] a_int = 20'h00000; - reg [17:0] b_int = 18'h00000; - reg unsigned_a_int = 1'b1; - reg unsigned_b_int = 1'b1; - reg signed [63:0] accumulator = 64'h0000000000000000; - reg signed [63:0] add_sub_in = 64'h0000000000000000; - reg signed [63:0] mult_out = 64'h0000000000000000; - reg signed [63:0] add_sub_out = 64'h0000000000000000; - reg signed [63:0] pre_shift = 64'h0000000000000000; - reg signed [63:0] shift_right = 64'h0000000000000000; - reg signed [63:0] round = 64'h0000000000000000; - reg signed [37:0] saturate = 38'h00000000; - reg [37:0] z_out = 38'h00000000; - reg [37:0] z_out_reg = 38'h00000000; - - - - reg [19:0] mult_a = 20'h00000; - reg [17:0] mult_b = 18'h00000; - - // pipelining - always @(posedge CLK or posedge RESET) - begin - if (RESET) - begin - subtract_reg <= 1'b0; - acc_fir_reg <= 6'h00; - feedback_reg <= 1'b0; - shift_right_reg1 <= 6'h00; - shift_right_reg2 <= 6'h00; - round_reg1 <= 1'b0; - round_reg2 <= 1'b0; - saturate_reg1 <= 1'b0; - saturate_reg2 <= 1'b0; - load_acc_reg <= 1'b0; - a_reg <= 20'h00000; - b_reg <= 18'h00000; - unsigned_a_reg <= 1'b1; - unsigned_b_reg <= 1'b1; - end - else - begin - subtract_reg <= SUBTRACT; - acc_fir_reg <= ACC_FIR; - feedback_reg <= FEEDBACK; - shift_right_reg1 <= SHIFT_RIGHT; - shift_right_reg2 <= shift_right_reg1; - round_reg1 <= ROUND; - round_reg2 <= round_reg1; - saturate_reg1 <= SATURATE; - saturate_reg2 <= saturate_reg1; - load_acc_reg <= LOAD_ACC; - a_reg <= A; - b_reg <= B; - unsigned_a_reg <= UNSIGNED_A; - unsigned_b_reg <= UNSIGNED_B; - - - end - end - - always @(*) - begin - if (INPUT_REG_EN == "TRUE") - begin - a_int = a_reg; - b_int = b_reg; - subtract_int = subtract_reg; - acc_fir_int = acc_fir_reg; - feedback_int = feedback_reg; - load_acc_int = load_acc_reg; - unsigned_a_int = unsigned_a_reg; - unsigned_b_int = unsigned_b_reg; - shift_right_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?shift_right_reg2:shift_right_reg1; - round_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?round_reg2:round_reg1; - saturate_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?saturate_reg2:saturate_reg1; - end - else - begin - a_int = A; - b_int = B; - subtract_int = SUBTRACT; - acc_fir_int = ACC_FIR; - feedback_int = FEEDBACK; - load_acc_int = LOAD_ACC; - unsigned_a_int = UNSIGNED_A; - unsigned_b_int = UNSIGNED_B; - shift_right_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?shift_right_reg1:SHIFT_RIGHT; - round_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?round_reg1:ROUND; - saturate_int = (DSP_MODE== "MULTIPLY_ACCUMULATE")?saturate_reg1:SATURATE; - - end - end - - // Feedback paths - always @(*) - begin - case (feedback_int) - 3'b000: begin - mult_a = a_int; - mult_b = b_int; - add_sub_in = accumulator; - end - 3'b001: begin - mult_a = a_int; - mult_b = b_int; - add_sub_in = 64'h0000000000000000; - end - 3'b010: begin - mult_a = a_int; - mult_b = 18'h00000; - add_sub_in = (unsigned_a_int)? a_int<>> shift_right_int; - round = (round_int && shift_right_int>0)? (pre_shift[shift_right_int-1]==1)?shift_right+1:shift_right:shift_right; - - if(saturate_int) - begin - if(unsigned_a_int && unsigned_b_int) - begin - if($signed(round)<0) - saturate = 38'h0000000000; - else if($signed(round)>38'h3fffffffff) - saturate = 38'h3fffffffff; - else - saturate = round[37:0]; - end - else - begin - if($signed(round)>$signed(38'h1fffffffff)) - saturate = 38'h1fffffffff; - else if($signed(round)<$signed(38'h2000000000)) - saturate = 38'h2000000000; - else - saturate = round[37:0]; - end - - end - else - saturate = round[37:0]; - - z_out = (DSP_MODE== "MULTIPLY")? mult_out:saturate; - end - - - // output register - always @(posedge CLK or posedge RESET) - begin - if(RESET) - begin - if(DSP_MODE== "MULTIPLY_ADD_SUB") - DLY_B <= 18'h00000; - - z_out_reg <= 38'h00000000; - end - else - begin - if(DSP_MODE== "MULTIPLY_ADD_SUB") - DLY_B <= B; - else - DLY_B <= 18'dx; - - z_out_reg <= z_out; - end - end - - assign Z = (OUTPUT_REG_EN == "TRUE")?z_out_reg:z_out; - - `ifndef SYNTHESIS - // If ACC_FIR is greater than 43, result is invalid - always @(ACC_FIR) - if (ACC_FIR > 43) - $fatal(1,"\nERROR: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR); - - always@(*) - begin - case(DSP_MODE) - "MULTIPLY_ACCUMULATE": begin - if(FEEDBACK>1) - $fatal(1,"\nERROR: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK); - end - endcase - - end - `endif // `ifndef SYNTHESIS - - initial begin - case(DSP_MODE) - "MULTIPLY" , - "MULTIPLY_ADD_SUB" , - "MULTIPLY_ACCUMULATE": begin end - default: begin - $fatal(1,"\nError: DSP38 instance %m has parameter DSP_MODE set to %s. Valid values are MULTIPLY, MULTIPLY_ADD_SUB, MULTIPLY_ACCUMULATE\n", DSP_MODE); - end - endcase - case(OUTPUT_REG_EN) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: DSP38 instance %m has parameter OUTPUT_REG_EN set to %s. Valid values are TRUE, FALSE\n", OUTPUT_REG_EN); - end - endcase - case(INPUT_REG_EN) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: DSP38 instance %m has parameter INPUT_REG_EN set to %s. Valid values are TRUE, FALSE\n", INPUT_REG_EN); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/FCLK_BUF.v b/models_customer/verilog/FCLK_BUF.v deleted file mode 100644 index 4916e65..0000000 --- a/models_customer/verilog/FCLK_BUF.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// FCLK_BUF simulation model -// Clock buffer for routing logic signal to the global clock -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module FCLK_BUF ( - input I, // Clock input - output O // Clock output -); - - assign O = I ; - -endmodule -`endcelldefine diff --git a/models_customer/verilog/FIFO18KX2.v b/models_customer/verilog/FIFO18KX2.v deleted file mode 100644 index 8109b6d..0000000 --- a/models_customer/verilog/FIFO18KX2.v +++ /dev/null @@ -1,382 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// FIFO18KX2 simulation model -// Dual 18Kb FIFO -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module FIFO18KX2 #( - parameter DATA_WRITE_WIDTH1 = 18, // FIFO data write width, FIFO 1 (9, 18) - parameter DATA_READ_WIDTH1 = 18, // FIFO data read width, FIFO 1 (9, 18) - parameter FIFO_TYPE1 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 1 (SYNCHRONOUS/ASYNCHRONOUS) - parameter [10:0] PROG_EMPTY_THRESH1 = 11'h004, // 11-bit Programmable empty depth, FIFO 1 - parameter [10:0] PROG_FULL_THRESH1 = 11'h7fa, // 11-bit Programmable full depth, FIFO 1 - parameter DATA_WRITE_WIDTH2 = 18, // FIFO data write width, FIFO 2 (9, 18) - parameter DATA_READ_WIDTH2 = 18, // FIFO data read width, FIFO 2 (9, 18) - parameter FIFO_TYPE2 = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer, FIFO 2 (SYNCHRONOUS/ASYNCHRONOUS) - parameter [10:0] PROG_EMPTY_THRESH2 = 11'h004, // 11-bit Programmable empty depth, FIFO 2 - parameter [10:0] PROG_FULL_THRESH2 = 11'h7fa // 11-bit Programmable full depth, FIFO 2 -) ( - input RESET1, // Active high asynchronous FIFO reset, FIFO 1 - input WR_CLK1, // Write clock, FIFO 1 - input RD_CLK1, // Read clock, FIFO 1 - input WR_EN1, // Write enable, FIFO 1 - input RD_EN1, // Read enable, FIFO 1 - input [DATA_WRITE_WIDTH1-1:0] WR_DATA1, // Write data, FIFO 1 - output [DATA_READ_WIDTH1-1:0] RD_DATA1, // Read data, FIFO 1 - output reg EMPTY1 = 1'b1, // FIFO empty flag, FIFO 1 - output reg FULL1 = 1'b0, // FIFO full flag, FIFO 1 - output reg ALMOST_EMPTY1 = 1'b0, // FIFO almost empty flag, FIFO 1 - output reg ALMOST_FULL1 = 1'b0, // FIFO almost full flag, FIFO 1 - output reg PROG_EMPTY1 = 1'b1, // FIFO programmable empty flag, FIFO 1 - output reg PROG_FULL1 = 1'b0, // FIFO programmable full flag, FIFO 1 - output reg OVERFLOW1 = 1'b0, // FIFO overflow error flag, FIFO 1 - output reg UNDERFLOW1 = 1'b0, // FIFO underflow error flag, FIFO 1 - input RESET2, // Active high synchronous FIFO reset, FIFO 2 - input WR_CLK2, // Write clock, FIFO 2 - input RD_CLK2, // Read clock, FIFO 2 - input WR_EN2, // Write enable, FIFO 2 - input RD_EN2, // Read enable, FIFO 2 - input [DATA_WRITE_WIDTH2-1:0] WR_DATA2, // Write data, FIFO 2 - output [DATA_READ_WIDTH2-1:0] RD_DATA2, // Read data, FIFO 2 - output reg EMPTY2 = 1'b1, // FIFO empty flag, FIFO 2 - output reg FULL2 = 1'b0, // FIFO full flag, FIFO 2 - output reg ALMOST_EMPTY2 = 1'b0, // FIFO almost empty flag, FIFO 2 - output reg ALMOST_FULL2 = 1'b0, // FIFO almost full flag, FIFO 2 - output reg PROG_EMPTY2 = 1'b1, // FIFO programmable empty flag, FIFO 2 - output reg PROG_FULL2 = 1'b0, // FIFO programmable full flag, FIFO 2 - output reg OVERFLOW2 = 1'b0, // FIFO overflow error flag, FIFO 2 - output reg UNDERFLOW2 = 1'b0 // FIFO underflow error flag, FIFO 2 -); - - //FIFO1 - localparam DATA_WIDTH1 = DATA_WRITE_WIDTH1; - localparam fifo_depth1 = (DATA_WIDTH1 <= 9) ? 2048 : 1024; - localparam fifo_addr_width1 = (DATA_WIDTH1 <= 9) ? 11 : 10; - - reg [fifo_addr_width1-1:0] fifo_wr_addr1 = {fifo_addr_width1{1'b0}}; - reg [fifo_addr_width1-1:0] fifo_rd_addr1 = {fifo_addr_width1{1'b0}}; - - wire [15:0] ram_wr_data1; - wire [1:0] ram_wr_parity1; - - reg fwft1 = 1'b0; - reg fall_through1; - reg wr_data_fwft1; - reg [DATA_WIDTH1-1:0] fwft_data1 = {DATA_WIDTH1{1'b0}}; - - wire [15:0] ram_rd_data1; - wire [1:0] ram_rd_parity1; - wire ram_clk_b1; - - integer number_entries1 = 0; - reg underrun_status1 = 0; - reg overrun_status1 = 0; - - generate - - if ((DATA_WIDTH1 == 9)|| (DATA_WIDTH1 == 17)) begin: one_parity - assign ram_wr_data1 = {{16-DATA_WIDTH1{1'b0}}, WR_DATA1}; - assign ram_wr_parity1 = {1'b0, WR_DATA1[DATA_WIDTH1-1]}; - assign RD_DATA1 = fwft1 ? fwft_data1 : {ram_rd_parity1[0], ram_rd_data1[DATA_WIDTH1-2:0]}; - end else if ((DATA_WIDTH1 == 18)) begin: two_parity - assign ram_wr_data1 = WR_DATA1[15:0]; - assign ram_wr_parity1 = WR_DATA1[DATA_WIDTH1-1:DATA_WIDTH1-2]; - assign RD_DATA1 = fwft1 ? fwft_data1 : {ram_rd_parity1[1:0], ram_rd_data1[DATA_WIDTH1-3:0]}; - end else begin: no_parity - assign ram_wr_data1 = fall_through1 ? wr_data_fwft1 : {{16-DATA_WIDTH1{1'b0}}, WR_DATA1}; - assign ram_wr_parity1 = 2'b0; - assign RD_DATA1 = fwft1 ? fwft_data1 : ram_rd_data1[DATA_WIDTH1-1:0]; - end - - if ( FIFO_TYPE1 == "SYNCHRONOUS" ) begin: sync - - always @(posedge WR_CLK1) - if (WR_EN1 && !RD_EN1) begin - number_entries1 <= number_entries1 + 1; - underrun_status1 = 0; - if (number_entries1 >= fifo_depth1) - overrun_status1 = 1; - end - else if (!WR_EN1 && RD_EN1 && number_entries1 == 0) begin - number_entries1 <= 0; - underrun_status1 = 1; - end - else if (!WR_EN1 && RD_EN1) begin - number_entries1 <= number_entries1 - 1; - underrun_status1 = 0; - end - - always @(posedge RESET1, posedge WR_CLK1) - if (RESET1) begin - fifo_wr_addr1 <= {fifo_addr_width1{1'b0}}; - fifo_rd_addr1 <= {fifo_addr_width1{1'b0}}; - EMPTY1 <= 1'b1; - FULL1 <= 1'b0; - ALMOST_EMPTY1 <= 1'b0; - ALMOST_FULL1 <= 1'b0; - PROG_EMPTY1 <= 1'b1; - PROG_FULL1 <= 1'b0; - OVERFLOW1 <= 1'b0; - UNDERFLOW1 <= 1'b0; - number_entries1 = 0; - fwft1 <= 1'b0; - fwft_data1 <= {DATA_WIDTH1-1{1'b0}}; - underrun_status1 <=1'b0; - overrun_status1 <= 1'b0; - end else begin - if (WR_EN1) - fifo_wr_addr1 <= fifo_wr_addr1 + 1'b1; - EMPTY1 <= ((number_entries1==0) && (underrun_status1==0) || ((RD_EN1 && !WR_EN1) && (number_entries1==1))); - FULL1 <= ((number_entries1==fifo_depth1) || ((number_entries1==(fifo_depth1-1)) && WR_EN1 && !RD_EN1)); - ALMOST_EMPTY1 <= (((number_entries1==1) && !(RD_EN1 && !WR_EN1)) || ((RD_EN1 && !WR_EN1) && (number_entries1==2))); - ALMOST_FULL1 <= (((number_entries1==(fifo_depth1-1)) && !(!RD_EN1 && WR_EN1)) || ((!RD_EN1 && WR_EN1) && (number_entries1==fifo_depth1-2))); - PROG_EMPTY1 <= ((number_entries1) < (PROG_EMPTY_THRESH1)) || ((RD_EN1 && !WR_EN1) && ((number_entries1) <= PROG_EMPTY_THRESH1) ); - PROG_FULL1 <= ((fifo_depth1-number_entries1) < (PROG_FULL_THRESH1)) || ((!RD_EN1 && WR_EN1) && ((fifo_depth1-number_entries1) <= PROG_FULL_THRESH1) ); - UNDERFLOW1 <= (EMPTY1 && RD_EN1) || (underrun_status1==1); - OVERFLOW1 <= (FULL1 && WR_EN1) || (overrun_status1==1); - if (EMPTY1 && WR_EN1 && !fwft1) begin - fwft_data1 <= WR_DATA1; - fifo_rd_addr1 <= fifo_rd_addr1 + 1'b1; - fwft1 <= 1'b1; - end else if (RD_EN1) begin - fwft1 <= 1'b0; - if (!(ALMOST_EMPTY1 && !WR_EN1)) - fifo_rd_addr1 <= fifo_rd_addr1 + 1'b1; - end - end - - assign ram_clk_b1 = WR_CLK1; - - initial begin - #1; - @(RD_CLK1); - $display("\nWarning: FIFO36K instance %m RD_CLK1 should be tied to ground when FIFO36K is configured as FIFO1_TYPE=SYNCHRONOUS."); - end - - end else begin: async - - assign ram_clk_b1 = RD_CLK1; - - end - - endgenerate - - //FIFO2 - localparam DATA_WIDTH2 = DATA_WRITE_WIDTH2; - localparam fifo_depth2 = (DATA_WIDTH2 <= 9) ? 2048 : 1024; - localparam fifo_addr_width2 = (DATA_WIDTH2 <= 9) ? 11 : 10; - - reg [fifo_addr_width2-1:0] fifo_wr_addr2 = {fifo_addr_width2{1'b0}}; - reg [fifo_addr_width2-1:0] fifo_rd_addr2 = {fifo_addr_width2{1'b0}}; - - wire [15:0] ram_wr_data2; - wire [1:0] ram_wr_parity2; - - reg fwft2 = 1'b0; - reg fall_through2; - reg wr_data_fwft2; - reg [DATA_WIDTH2-1:0] fwft_data2 = {DATA_WIDTH2{1'b0}}; - - wire [15:0] ram_rd_data2; - wire [1:0] ram_rd_parity2; - wire ram_clk_b2; - - integer number_entries2 = 0; - reg underrun_status2 = 0; - reg overrun_status2 = 0; - - generate - - if ((DATA_WIDTH2 == 9)|| (DATA_WIDTH2 == 17)) begin: one_parity_fifo2 - assign ram_wr_data2 = {{16-DATA_WIDTH2{1'b0}}, WR_DATA2}; - assign ram_wr_parity2 = {1'b0, WR_DATA2[DATA_WIDTH2-1]}; - assign RD_DATA2 = fwft2 ? fwft_data2 : {ram_rd_parity2[0], ram_rd_data2[DATA_WIDTH2-2:0]}; - end else if ((DATA_WIDTH2 == 18)) begin: two_parity_fifo2 - assign ram_wr_data2 = WR_DATA2[15:0]; - assign ram_wr_parity2 = WR_DATA2[DATA_WIDTH2-1:DATA_WIDTH2-2]; - assign RD_DATA2 = fwft2 ? fwft_data2 : {ram_rd_parity2[1:0], ram_rd_data2[DATA_WIDTH2-3:0]}; - end else begin: no_parity_fifo2 - assign ram_wr_data2 = fall_through2 ? wr_data_fwft2 : {{16-DATA_WIDTH2{1'b0}}, WR_DATA2}; - assign ram_wr_parity2 = 2'b0; - assign RD_DATA2 = fwft2 ? fwft_data2 : ram_rd_data2[DATA_WIDTH2-1:0]; - end - - if ( FIFO_TYPE2 == "SYNCHRONOUS" ) begin: sync_fifo2 - - always @(posedge WR_CLK2) - if (WR_EN2 && !RD_EN2) begin - number_entries2 <= number_entries2 + 1; - underrun_status2 = 0; - if (number_entries2 >= fifo_depth2) - overrun_status2 = 1; - end - else if (!WR_EN2 && RD_EN2 && number_entries2 == 0) begin - number_entries2 <= 0; - underrun_status2 = 1; - end - else if (!WR_EN2 && RD_EN2) begin - number_entries2 <= number_entries2 - 1; - underrun_status2 = 0; - end - - always @(posedge RESET2, posedge WR_CLK2) - if (RESET2) begin - fifo_wr_addr2 <= {fifo_addr_width2{1'b0}}; - fifo_rd_addr2 <= {fifo_addr_width2{1'b0}}; - EMPTY2 <= 1'b1; - FULL2 <= 1'b0; - ALMOST_EMPTY2 <= 1'b0; - ALMOST_FULL2 <= 1'b0; - PROG_EMPTY2 <= 1'b1; - PROG_FULL2 <= 1'b0; - OVERFLOW2 <= 1'b0; - UNDERFLOW2 <= 1'b0; - number_entries2 = 0; - fwft2 <= 1'b0; - fwft_data2 <= {DATA_WIDTH2-1{1'b0}}; - underrun_status2 <=1'b0; - overrun_status2 <= 1'b0; - end else begin - if (WR_EN2) - fifo_wr_addr2 <= fifo_wr_addr2 + 1'b1; - EMPTY2 <= ((number_entries2==0) && (underrun_status2==0) || ((RD_EN2 && !WR_EN2) && (number_entries2==1))); - FULL2 <= ((number_entries2==fifo_depth2) || ((number_entries2==(fifo_depth2-1)) && WR_EN2 && !RD_EN2)); - ALMOST_EMPTY2 <= (((number_entries2==1) && !(RD_EN2 && !WR_EN2)) || ((RD_EN2 && !WR_EN2) && (number_entries2==2))); - ALMOST_FULL2 <= (((number_entries2==(fifo_depth2-1)) && !(!RD_EN2 && WR_EN2)) || ((!RD_EN2 && WR_EN2) && (number_entries2==fifo_depth2-2))); - PROG_EMPTY2 <= ((number_entries2) < (PROG_EMPTY_THRESH2)) || ((RD_EN2 && !WR_EN2) && ((number_entries2) <= PROG_EMPTY_THRESH2) ); - PROG_FULL2 <= ((fifo_depth2-number_entries2) < (PROG_FULL_THRESH2)) || ((!RD_EN2 && WR_EN2) && ((fifo_depth2-number_entries2) <= PROG_FULL_THRESH2) ); - UNDERFLOW2 <= (EMPTY2 && RD_EN2) || (underrun_status2==1); - OVERFLOW2 <= (FULL2 && WR_EN2) || (overrun_status2==1); - if (EMPTY2 && WR_EN2 && !fwft2) begin - fwft_data2 <= WR_DATA2; - fifo_rd_addr2 <= fifo_rd_addr2 + 1'b1; - fwft2 <= 1'b1; - end else if (RD_EN2) begin - fwft2 <= 1'b0; - if (!(ALMOST_EMPTY2 && !WR_EN2)) - fifo_rd_addr2 <= fifo_rd_addr2 + 1'b1; - end - end - - assign ram_clk_b2 = WR_CLK2; - - initial begin - #1; - @(RD_CLK2); - $display("\nWarning: FIFO36K instance %m RD_CLK2 should be tied to ground when FIFO36K is configured as FIFO_TYPE2=SYNCHRONOUS."); - end - - end else begin: async_fifo2 - - assign ram_clk_b2 = RD_CLK2; - - end - - endgenerate - -// Use BRAM -TDP_RAM18KX2 #( - .INIT1({16384{1'b0}}), // Initial Contents of memory, RAM 1 - .INIT1_PARITY({2048{1'b0}}), // Initial Contents of memory - .WRITE_WIDTH_A1(DATA_WRITE_WIDTH1), // Write data width on port A, RAM 1 (1-18) - .WRITE_WIDTH_B1(DATA_WRITE_WIDTH1), // Write data width on port B, RAM 1 (1-18) - .READ_WIDTH_A1(DATA_READ_WIDTH1), // Read data width on port A, RAM 1 (1-18) - .READ_WIDTH_B1(DATA_READ_WIDTH1), // Read data width on port B, RAM 1 (1-18) - .INIT2({16384{1'b0}}), // Initial Contents of memory, RAM 2 - .INIT2_PARITY({2048{1'b0}}), // Initial Contents of memory - .WRITE_WIDTH_A2(DATA_WRITE_WIDTH2), // Write data width on port A, RAM 2 (1-18) - .WRITE_WIDTH_B2(DATA_WRITE_WIDTH2), // Write data width on port B, RAM 2 (1-18) - .READ_WIDTH_A2(DATA_READ_WIDTH2), // Read data width on port A, RAM 2 (1-18) - .READ_WIDTH_B2(DATA_READ_WIDTH2) // Read data width on port B, RAM 2 (1-18) -) -tdp_ram18kx2_inst -( - // Ports for 1st 18K RAM - .WEN_A1(WR_EN1), // Write-enable port A, RAM 1 - .WEN_B1(1'b0), // Write-enable port B, RAM 1 - .REN_A1(1'b0), // Read-enable port A, RAM 1 - .REN_B1(RD_EN1), // Read-enable port B, RAM 1 - .CLK_A1(WR_CLK1), // Clock port A, RAM 1 - .CLK_B1(ram_clk_b1), // Clock port B, RAM 1 - .BE_A1(2'b11), // Byte-write enable port A, RAM 1 - .BE_B1(2'b11), // Byte-write enable port B, RAM 1 - .ADDR_A1({fifo_wr_addr1, {14-fifo_addr_width1{1'b0}}}), // Address port A, RAM 1 - .ADDR_B1({fifo_rd_addr1, {14-fifo_addr_width1{1'b0}}}), // Address port B, RAM 1 - .WDATA_A1(ram_wr_data1), // Write data port A, RAM 1 - .WPARITY_A1(ram_wr_parity1), // Write parity port A, RAM 1 - .WDATA_B1(16'h0000), // Write data port B, RAM 1 - .WPARITY_B1(2'b00), // Write parity port B, RAM 1 - .RDATA_A1(), // Read data port A, RAM 1 - .RPARITY_A1(), // Read parity port A, RAM 1 - .RDATA_B1(ram_rd_data1), // Read data port B, RAM 1 - .RPARITY_B1(ram_rd_parity1), // Read parity port B, RAM 1 - // Ports for 2nd 18K RAM - .WEN_A2(WR_EN2), // Write-enable port A, RAM 2 - .WEN_B2(1'b0), // Write-enable port B, RAM 2 - .REN_A2(1'b0), // Read-enable port A, RAM 2 - .REN_B2(RD_EN2), // Read-enable port B, RAM 2 - .CLK_A2(WR_CLK2), // Clock port A, RAM 2 - .CLK_B2(ram_clk_b2), // Clock port B, RAM 2 - .BE_A2(2'b11), // Byte-write enable port A, RAM 2 - .BE_B2(2'b11), // Byte-write enable port B, RAM 2 - .ADDR_A2({fifo_wr_addr2, {14-fifo_addr_width2{1'b0}}}), // Address port A, RAM 2 - .ADDR_B2({fifo_rd_addr2, {14-fifo_addr_width2{1'b0}}}), // Address port B, RAM 2 - .WDATA_A2(ram_wr_data2), // Write data port A, RAM 2 - .WPARITY_A2(ram_wr_parity2), // Write parity port A, RAM 2 - .WDATA_B2(16'h0000), // Write data port B, RAM 2 - .WPARITY_B2(2'b00), // Write parity port B, RAM 2 - .RDATA_A2(), // Read data port A, RAM 2 - .RPARITY_A2(), // Read parity port A, RAM 2 - .RDATA_B2(ram_rd_data2), // Read data port B, RAM 2 - .RPARITY_B2(ram_rd_parity2) // Read parity port B, RAM 2 -); initial begin - case(DATA_WRITE_WIDTH1) - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH1 set to %d. Valid values are 9, 18\n", DATA_WRITE_WIDTH1); - end - endcase - case(DATA_READ_WIDTH1) - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH1 set to %d. Valid values are 9, 18\n", DATA_READ_WIDTH1); - end - endcase - case(FIFO_TYPE1) - "SYNCHRONOUS" , - "ASYNCHRONOUS": begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE1 set to %s. Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE1); - end - endcase - case(DATA_WRITE_WIDTH2) - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_WRITE_WIDTH2 set to %d. Valid values are 9, 18\n", DATA_WRITE_WIDTH2); - end - endcase - case(DATA_READ_WIDTH2) - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter DATA_READ_WIDTH2 set to %d. Valid values are 9, 18\n", DATA_READ_WIDTH2); - end - endcase - case(FIFO_TYPE2) - "SYNCHRONOUS" , - "ASYNCHRONOUS": begin end - default: begin - $fatal(1,"\nError: FIFO18KX2 instance %m has parameter FIFO_TYPE2 set to %s. Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE2); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/FIFO36K.v b/models_customer/verilog/FIFO36K.v deleted file mode 100644 index c23d16c..0000000 --- a/models_customer/verilog/FIFO36K.v +++ /dev/null @@ -1,227 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// FIFO36K simulation model -// 36Kb FIFO -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module FIFO36K #( - parameter DATA_WRITE_WIDTH = 36, // FIFO data write width (9, 18, 36) - parameter DATA_READ_WIDTH = 36, // FIFO data read width (9, 18, 36) - parameter FIFO_TYPE = "SYNCHRONOUS", // Synchronous or Asynchronous data transfer (SYNCHRONOUS/ASYNCHRONOUS) - parameter [11:0] PROG_EMPTY_THRESH = 12'h004, // 12-bit Programmable empty depth - parameter [11:0] PROG_FULL_THRESH = 12'hffa // 12-bit Programmable full depth -) ( - input RESET, // Active high synchronous FIFO reset - input WR_CLK, // Write clock - input RD_CLK, // Read clock - input WR_EN, // Write enable - input RD_EN, // Read enable - input [DATA_WRITE_WIDTH-1:0] WR_DATA, // Write data - output [DATA_READ_WIDTH-1:0] RD_DATA, // Read data - output reg EMPTY = 1'b1, // FIFO empty flag - output reg FULL = 1'b0, // FIFO full flag - output reg ALMOST_EMPTY = 1'b0, // FIFO almost empty flag - output reg ALMOST_FULL = 1'b0, // FIFO almost full flag - output reg PROG_EMPTY = 1'b1, // FIFO programmable empty flag - output reg PROG_FULL = 1'b0, // FIFO programmable full flag - output reg OVERFLOW = 1'b0, // FIFO overflow error flag - output reg UNDERFLOW = 1'b0 // FIFO underflow error flag -); - - localparam DATA_WIDTH = DATA_WRITE_WIDTH; - localparam fifo_depth = (DATA_WIDTH <= 9) ? 4096 : - (DATA_WIDTH <= 18) ? 2048 : - 1024; - - localparam fifo_addr_width = (DATA_WIDTH <= 9) ? 12 : - (DATA_WIDTH <= 18) ? 11 : - 10; - - reg [fifo_addr_width-1:0] fifo_wr_addr = {fifo_addr_width{1'b0}}; - reg [fifo_addr_width-1:0] fifo_rd_addr = {fifo_addr_width{1'b0}}; - - wire [31:0] ram_wr_data; - wire [3:0] ram_wr_parity; - - reg fwft = 1'b0; - reg fall_through; - reg wr_data_fwft; - reg [DATA_WIDTH-1:0] fwft_data = {DATA_WIDTH{1'b0}}; - - wire [31:0] ram_rd_data; - wire [3:0] ram_rd_parity; - wire ram_clk_b; - - integer number_entries = 0; - reg underrun_status = 0; - reg overrun_status = 0; - - generate - - if ((DATA_WIDTH == 9)|| (DATA_WIDTH == 17) || (DATA_WIDTH == 25)) begin: one_parity - assign ram_wr_data = {{32-DATA_WIDTH{1'b0}}, WR_DATA}; - assign ram_wr_parity = {3'b000, WR_DATA[DATA_WIDTH-1]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[0], ram_rd_data[DATA_WIDTH-2:0]}; - end else if (DATA_WIDTH == 33) begin: width_33 - assign ram_wr_data = WR_DATA[31:0]; - assign ram_wr_parity = {3'b000, WR_DATA[32]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[0], ram_rd_data[31:0]}; - end else if ((DATA_WIDTH == 18) || (DATA_WIDTH == 26)) begin: two_parity - assign ram_wr_data = {{32-DATA_WIDTH{1'b0}}, WR_DATA}; - assign ram_wr_parity = {2'b00, WR_DATA[DATA_WIDTH-1:DATA_WIDTH-2]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[1:0], ram_rd_data[DATA_WIDTH-3:0]}; - end else if (DATA_WIDTH == 34) begin: width_34 - assign ram_wr_data = WR_DATA[31:0]; - assign ram_wr_parity = {2'b00, WR_DATA[33:32]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[1:0], ram_rd_data[31:0]}; - end else if (DATA_WIDTH == 27) begin: width_27 - assign ram_wr_data = {8'h00, WR_DATA[23:0]}; - assign ram_wr_parity = {1'b0, WR_DATA[26:24]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[2:0], ram_rd_data[23:0]}; - end else if (DATA_WIDTH == 35) begin: width_35 - assign ram_wr_data = WR_DATA[31:0]; - assign ram_wr_parity = {1'b0, WR_DATA[34:32]}; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[2:0], ram_rd_data[31:0]}; - end else if (DATA_WIDTH == 36) begin: width_36 - assign ram_wr_data = WR_DATA[31:0]; - assign ram_wr_parity = WR_DATA[35:32]; - assign RD_DATA = fwft ? fwft_data : {ram_rd_parity[3:0], ram_rd_data[31:0]}; - end else begin: no_parity - assign ram_wr_data = fall_through ? wr_data_fwft : {{32-DATA_WIDTH{1'b0}}, WR_DATA}; - assign ram_wr_parity = 4'h0; - assign RD_DATA = fwft ? fwft_data : ram_rd_data[DATA_WIDTH-1:0]; - end - - if ( FIFO_TYPE == "SYNCHRONOUS" ) begin: sync - - always @(posedge WR_CLK) - if (WR_EN && !RD_EN) begin - number_entries <= number_entries + 1; - underrun_status = 0; - if (number_entries >= fifo_depth) - overrun_status = 1; - end - else if (!WR_EN && RD_EN && number_entries == 0) begin - number_entries <= 0; - underrun_status = 1; - end - else if (!WR_EN && RD_EN) begin - number_entries <= number_entries - 1; - underrun_status = 0; - end - - always @(posedge RESET, posedge WR_CLK) - if (RESET) begin - fifo_wr_addr <= {fifo_addr_width{1'b0}}; - fifo_rd_addr <= {fifo_addr_width{1'b0}}; - EMPTY <= 1'b1; - FULL <= 1'b0; - ALMOST_EMPTY <= 1'b0; - ALMOST_FULL <= 1'b0; - PROG_EMPTY <= 1'b1; - PROG_FULL <= 1'b0; - OVERFLOW <= 1'b0; - UNDERFLOW <= 1'b0; - number_entries = 0; - fwft <= 1'b0; - fwft_data <= {DATA_WIDTH-1{1'b0}}; - underrun_status <=1'b0; - overrun_status <= 1'b0; - end else begin - if (WR_EN) - fifo_wr_addr <= fifo_wr_addr + 1'b1; - EMPTY <= ((number_entries==0) && (underrun_status==0) || ((RD_EN && !WR_EN) && (number_entries==1))); - FULL <= ((number_entries==fifo_depth) || ((number_entries==(fifo_depth-1)) && WR_EN && !RD_EN)); - ALMOST_EMPTY <= (((number_entries==1) && !(RD_EN && !WR_EN)) || ((RD_EN && !WR_EN) && (number_entries==2))); - ALMOST_FULL <= (((number_entries==(fifo_depth-1)) && !(!RD_EN && WR_EN)) || ((!RD_EN && WR_EN) && (number_entries==fifo_depth-2))); - PROG_EMPTY <= ((number_entries) < (PROG_EMPTY_THRESH)) || ((RD_EN && !WR_EN) && ((number_entries) <= PROG_EMPTY_THRESH) ); - PROG_FULL <= ((fifo_depth-number_entries) < (PROG_FULL_THRESH)) || ((!RD_EN && WR_EN) && ((fifo_depth-number_entries) <= PROG_FULL_THRESH) ); - UNDERFLOW <= (EMPTY && RD_EN) || (underrun_status==1); - OVERFLOW <= (FULL && WR_EN) || (overrun_status==1); - if (EMPTY && WR_EN && !fwft) begin - fwft_data <= WR_DATA; - fifo_rd_addr <= fifo_rd_addr + 1'b1; - fwft <= 1'b1; - end else if (RD_EN) begin - fwft <= 1'b0; - if (!(ALMOST_EMPTY && !WR_EN)) - fifo_rd_addr <= fifo_rd_addr + 1'b1; - end - end - - assign ram_clk_b = WR_CLK; - - initial begin - #1; - @(RD_CLK); - $display("\nWarning: FIFO36K instance %m RD_CLK should be tied to ground when FIFO36K is configured as FIFO_TYPE=SYNCHRONOUS."); - end - - end else begin: async - - assign ram_clk_b = RD_CLK; - - end - - endgenerate - - // Use BRAM - - TDP_RAM36K #( - .INIT({32768{1'b0}}), // Initial Contents of memory - .INIT_PARITY({2048{1'b0}}), // Initial Contents of memory - .WRITE_WIDTH_A(DATA_WIDTH), // Write data width on port A (1-36) - .READ_WIDTH_A(DATA_WIDTH), // Read data width on port A (1-36) - .WRITE_WIDTH_B(DATA_WIDTH), // Write data width on port B (1-36) - .READ_WIDTH_B(DATA_WIDTH) // Read data width on port B (1-36) - ) FIFO_RAM_inst ( - .WEN_A(WR_EN), // Write-enable port A - .WEN_B(1'b0), // Write-enable port B - .REN_A(1'b0), // Read-enable port A - .REN_B(RD_EN), // Read-enable port B - .CLK_A(WR_CLK), // Clock port A - .CLK_B(ram_clk_b), // Clock port B - .BE_A(4'hf), // Byte-write enable port A - .BE_B(4'h0), // Byte-write enable port B - .ADDR_A({fifo_wr_addr, {15-fifo_addr_width{1'b0}}}), // Address port A, align MSBs and connect unused MSBs to logic 0 - .ADDR_B({fifo_rd_addr, {15-fifo_addr_width{1'b0}}}), // Address port B, align MSBs and connect unused MSBs to logic 0 - .WDATA_A(ram_wr_data), // Write data port A - .WPARITY_A(ram_wr_parity), // Write parity data port A - .WDATA_B(32'h00000000), // Write data port B - .WPARITY_B(4'h0), // Write parity port B - .RDATA_A(), // Read data port A - .RPARITY_A(), // Read parity port A - .RDATA_B(ram_rd_data), // Read data port B - .RPARITY_B(ram_rd_parity) // Read parity port B - ); initial begin - case(DATA_WRITE_WIDTH) - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: FIFO36K instance %m has parameter DATA_WRITE_WIDTH set to %d. Valid values are 9, 18, 36\n", DATA_WRITE_WIDTH); - end - endcase - case(DATA_READ_WIDTH) - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: FIFO36K instance %m has parameter DATA_READ_WIDTH set to %d. Valid values are 9, 18, 36\n", DATA_READ_WIDTH); - end - endcase - case(FIFO_TYPE) - "SYNCHRONOUS" , - "ASYNCHRONOUS": begin end - default: begin - $fatal(1,"\nError: FIFO36K instance %m has parameter FIFO_TYPE set to %s. Valid values are SYNCHRONOUS, ASYNCHRONOUS\n", FIFO_TYPE); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_BUF.v b/models_customer/verilog/I_BUF.v deleted file mode 100644 index 77781dc..0000000 --- a/models_customer/verilog/I_BUF.v +++ /dev/null @@ -1,42 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// I_BUF simulation model -// Input buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module I_BUF #( - parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN) -) ( - input I, // Data input (connect to top-level port) - input EN, // Enable the input - output O // Data output -); - generate - if ( WEAK_KEEPER == "PULLUP" ) begin: add_pullup - pullup(I); - end else if ( WEAK_KEEPER == "PULLDOWN" ) begin: add_pulldown - pulldown(I); - end - endgenerate - - assign O = EN ? I : 1'b0; - - - initial begin - case(WEAK_KEEPER) - "NONE" , - "PULLUP" , - "PULLDOWN": begin end - default: begin - $fatal(1,"\nError: I_BUF instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER); - end - endcase - - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_BUF_DS.v b/models_customer/verilog/I_BUF_DS.v deleted file mode 100644 index 8041c7c..0000000 --- a/models_customer/verilog/I_BUF_DS.v +++ /dev/null @@ -1,82 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// I_BUF_DS simulation model -// input differential buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module I_BUF_DS #( - parameter WEAK_KEEPER = "NONE", // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN) - parameter IOSTANDARD = "DEFAULT", // IO Standard - parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination -) ( - input I_P, // Data positive input (connect to top-level port) - input I_N, // Data negative input (connect to top-level port) - input EN, // Enable the input - output reg O // Data output -); - - generate - if ( WEAK_KEEPER == "PULLUP" ) begin: add_pullup - pullup(I_P); - pullup(I_N); - end else if ( WEAK_KEEPER == "PULLDOWN" ) begin: add_pulldown - pulldown(I_P); - pulldown(I_N); - end - endgenerate - - always @(I_P, I_N, EN) begin - casez ({I_P, I_N, EN}) - 3'b??0 : O = 0; // When not enabled, output is set to zero - 3'b101 : O = 1; - 3'b011 : O = 0; - default : begin end // If enabled and I_P and I_N are the same, output does not change - endcase - end - - - initial begin - case(WEAK_KEEPER) - "NONE" , - "PULLUP" , - "PULLDOWN": begin end - default: begin - $fatal(1,"\nError: I_BUF_DS instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER); - end - endcase - case(IOSTANDARD) - "DEFAULT" , - "BLVDS_DIFF" , - "LVDS_HP_DIFF" , - "LVDS_HR_DIFF" , - "LVPECL_25_DIFF" , - "LVPECL_33_DIFF" , - "HSTL_12_DIFF" , - "HSTL_15_DIFF" , - "HSUL_12_DIFF" , - "MIPI_DIFF" , - "POD_12_DIFF" , - "RSDS_DIFF" , - "SLVS_DIFF" , - "SSTL_15_DIFF" , - "SSTL_18_HP_DIFF" , - "SSTL_18_HR_DIFF": begin end - default: begin - $fatal(1,"\nError: I_BUF_DS instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, BLVDS_DIFF, LVDS_HP_DIFF, LVDS_HR_DIFF, LVPECL_25_DIFF, LVPECL_33_DIFF, HSTL_12_DIFF, HSTL_15_DIFF, HSUL_12_DIFF, MIPI_DIFF, POD_12_DIFF, RSDS_DIFF, SLVS_DIFF, SSTL_15_DIFF, SSTL_18_HP_DIFF, SSTL_18_HR_DIFF\n", IOSTANDARD); - end - endcase - case(DIFFERENTIAL_TERMINATION) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: I_BUF_DS instance %m has parameter DIFFERENTIAL_TERMINATION set to %s. Valid values are TRUE, FALSE\n", DIFFERENTIAL_TERMINATION); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_DDR.v b/models_customer/verilog/I_DDR.v deleted file mode 100644 index 12dbb4b..0000000 --- a/models_customer/verilog/I_DDR.v +++ /dev/null @@ -1,59 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// I_DDR simulation model -// DDR input register -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module I_DDR ( - input D, // Data input (connect to input port, buffer or I_DELAY) - input R, // Active-low asynchrnous reset - input E, // Active-high enable - input C, // Clock input - output reg [1:0] Q = 2'b00 // Data output -); - - reg data_pos; - reg data_neg; - - always @(negedge R) - begin - Q <= 2'b00; - data_pos<=2'b00; - data_neg<=2'b00; - end - - always@(posedge C) - begin - if(!R) - data_pos<=0; - else - data_pos<=D; - end - - always@(negedge C) - begin - if(!R) - data_neg<=0; - else - data_neg<=D; - end - - always @(posedge C) - begin - if(!R) - Q<=0; - else if(E) - begin - Q[1]<=data_pos; - Q[0]<=data_neg; - end - else - Q<=Q; - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_DELAY.v b/models_customer/verilog/I_DELAY.v deleted file mode 100644 index bd8f6b5..0000000 --- a/models_customer/verilog/I_DELAY.v +++ /dev/null @@ -1,68 +0,0 @@ -`timescale 1ps/1ps -`celldefine -// -// I_DELAY simulation model -// Input Delay -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module I_DELAY #( - parameter DELAY = 0 // TAP delay value (0-63) -) ( - input I, // Data Input (Connect to input port or buffer) - input DLY_LOAD, // Delay load input - input DLY_ADJ, // Delay adjust input - input DLY_INCDEC, // Delay increment / decrement input - output [5:0] DLY_TAP_VALUE, // Delay tap value output - input CLK_IN, // Clock input - output O // Data output -); - -// Adding local variable for delay load -reg dly_ld_0, dly_ld_1; -wire dly_ld_p; - -// Adding local variable for delay adjust -reg dly_adj_0, dly_adj_1; -wire dly_adj_p; - -// reg counter; -reg [5:0] dly_tap_val = 0; - -always_ff @(posedge CLK_IN) -begin - dly_ld_0 <= DLY_LOAD; - dly_ld_1 <= dly_ld_0; - - dly_adj_0 <= DLY_ADJ; - dly_adj_1 <= dly_adj_0; -end - -// Detecting 0 to 1 transition -assign dly_ld_p = dly_ld_0 && !dly_ld_1; -assign dly_adj_p = dly_adj_0 && !dly_adj_1; - -always_ff @(posedge CLK_IN) -begin - if (dly_ld_p) - dly_tap_val <= DELAY; - else if (dly_adj_p && DLY_INCDEC && dly_tap_val!=63) - dly_tap_val <= dly_tap_val + 1; - else if (dly_adj_p && !DLY_INCDEC && dly_tap_val!=0) - dly_tap_val <= dly_tap_val - 1; -end - -assign DLY_TAP_VALUE = dly_tap_val; -assign #(30.0ps + (21.56ps*dly_tap_val)) O = I; // Adjusted Delay for TT corner - - initial begin - - if ((DELAY < 0) || (DELAY > 63)) begin - $fatal(1,"I_DELAY instance %m DELAY set to incorrect value, %d. Values must be between 0 and 63.", DELAY); - end - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_FAB.v b/models_customer/verilog/I_FAB.v deleted file mode 100644 index a69b17e..0000000 --- a/models_customer/verilog/I_FAB.v +++ /dev/null @@ -1,19 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// I_FAB simulation model -// Marker Buffer for periphery to fabric transition -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module I_FAB ( - input I, // Input - output O // Output -); - -assign O = I ; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/I_SERDES.v b/models_customer/verilog/I_SERDES.v deleted file mode 100644 index 76061d7..0000000 --- a/models_customer/verilog/I_SERDES.v +++ /dev/null @@ -1,780 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// I_SERDES simulation model -// Input Serial Deserializer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - - -module synchronizer #( - - /* Total number of synchronization stages, to handle metastaibility. This value can be greater but minimum value is 2 */ - parameter SYNC_STAGES = 2, - parameter ADDRSIZE = 4 -) -( - output [ADDRSIZE:0] wptr_reg, - output [ADDRSIZE:0] rptr_reg, - input wr_clk, - input rd_clk, - input wr_rst, - input rd_rst, - input [ADDRSIZE:0] wptr, - input [ADDRSIZE:0] rptr - -); - - reg [ADDRSIZE:0] wr_sync_register[0:SYNC_STAGES-1]; - reg [ADDRSIZE:0] rd_sync_register[0:SYNC_STAGES-1]; - - - assign wptr_reg = wr_sync_register[SYNC_STAGES-1]; - assign rptr_reg = rd_sync_register[SYNC_STAGES-1]; - - always @(posedge wr_clk or posedge wr_rst) begin - if (wr_rst) begin - wr_sync_register[0] <= 0; - end - else begin - wr_sync_register[0] <= rptr; - end - end - - always @(posedge rd_clk or posedge rd_rst) begin - if (rd_rst) begin - rd_sync_register[0] <= 0; - end - else begin - rd_sync_register[0] <= wptr; - end - - end - - genvar i; - - generate - for(i=0; i<(SYNC_STAGES-1); i = i+1)begin - always@(posedge wr_clk or posedge wr_rst) begin - if(wr_rst) begin - wr_sync_register[i+1] <= 0; - end - else begin - wr_sync_register[i+1] <= wr_sync_register[i]; - end - end - always @(posedge rd_clk or posedge rd_rst) begin - if (rd_rst) begin - rd_sync_register[i+1] <= 0; - end - else begin - rd_sync_register[i+1] <= rd_sync_register[i]; - end - end - end - endgenerate - - -endmodule - -module dual_port_ram #( - /* Define width of memory */ - parameter DATASIZE = 32, - /* Define depth of memory */ - parameter ADDRSIZE = 4, - /* For BRAM set MEM_TYPE=1, while for Distributed memory set MEM_TYPE=0 */ - parameter MEM_TYPE = 0 -) -( - output reg [DATASIZE-1:0] rdata, - input wr_clk, - input rd_clk, - input wen, - input ren, - input [DATASIZE-1:0] wdata, - input [ADDRSIZE:0] waddr, - input [ADDRSIZE:0] raddr -); - - /* Inferring Block memory as Dual Port RAM */ - - generate if (MEM_TYPE) begin - (* ram_style = "block" *) reg [DATASIZE-1:0] mem [(1<> 1); - end - - /* increment read pointer when rd signal goes high and fifo is not empty */ - assign next_rd_addr = rd_addr + 1; - always @(posedge rclk or posedge rd_reset) - if (rd_reset) - begin - rd_addr <= 0; - rgray <= 0; - end else if (ren && !read_empty) - begin - rd_addr <= next_rd_addr; - /* Binary to Gray code conversion */ - rgray <= next_rd_addr ^ (next_rd_addr >> 1); - end - - - /* wr_full signal goes high if fifo is full */ - assign wr_full = (wr_rgray == { ~wgray[ADDRSIZE:ADDRSIZE-1], wgray[ADDRSIZE-2:0] }); - - /* this signal goes high if fifo is empty */ - assign read_empty = (rd_wgray == rgray); - - assign ren = (rd_empty || rd); - - - always @(posedge rclk or posedge rd_reset) - if (rd_reset) - rd_empty <= 1'b1; - else if (ren) - rd_empty <= read_empty; - - - synchronizer # (.SYNC_STAGES(SYNC_STAGES), - .ADDRSIZE (ADDRSIZE)) - synchronizer( - .wptr_reg (wr_rgray), - .rptr_reg (rd_wgray), - .wr_clk (wclk), - .rd_clk (rclk), - .wr_rst (wr_reset), - .rd_rst (rd_reset), - .wptr (wgray), - .rptr (rgray) - ); - - dual_port_ram # (.DATASIZE(DATASIZE), - .ADDRSIZE (ADDRSIZE), - .MEM_TYPE(MEM_TYPE)) - dual_port_ram( - .rdata (rd_data), - .wr_clk (wclk), - .rd_clk (rclk), - .wen (wr && !wr_full), - .ren (ren), - .wdata (wr_data), - .waddr (wr_addr), - .raddr (rd_addr) - ); - -endmodule -module I_SERDES #( - parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR) - parameter WIDTH = 4, // Width of Deserialization (3-10) - parameter DPA_MODE = "NONE" // Select Dynamic Phase Alignment or Clock Data Recovery (NONE/DPA/CDR) -) ( - input D, // Data input (connect to input port, buffer or I_DELAY) - input RST, // Active-low asycnhronous reset - input BITSLIP_ADJ, // BITSLIP_ADJ input - input EN, // EN input data (input data is low when driven low) - input CLK_IN, // Fabric clock input - output CLK_OUT, // Fabric clock output - output [WIDTH-1:0] Q, // Data output - output DATA_VALID, // DATA_VALID output - output DPA_LOCK, // DPA_LOCK output - output DPA_ERROR, // DPA_ERROR output - input PLL_LOCK, // PLL lock input - input PLL_CLK // PLL clock input -); - -reg clk_0=0; -reg clk_90=0 ; -reg clk_180=0; -reg clk_270=0; -real start_point; -real end_point; -real clk_period; -real period_quarter; -reg clk_start=0; - -// dpa block signals -reg [3:0] clk0_data_reg; -reg [3:0] clk0_data_comp; -reg [3:0] clk90_data_reg; -reg [3:0] clk90_data_comp; -reg [3:0] clk180_data_reg; -reg [3:0] clk180_data_comp; -reg [3:0] clk270_data_reg; -reg [3:0] clk270_data_comp; - -reg [4:0] clk0_data_count; -reg [4:0] clk90_data_count; -reg [4:0] clk180_data_count; -reg [4:0] clk270_data_count; - -reg [1:0] clk0_reg_data_count; -reg [1:0] clk90_reg_data_count; -reg [1:0] clk180_reg_data_count; -reg [1:0] clk270_reg_data_count; - -reg dpa_lock=0; -reg cdr_clk=0; -reg dpa_dout=0; -reg dpa_error=0; - -// dpa fifo signals -wire dpa_fifo_empty; -wire dpa_fifo_full; -reg dpa_fifo_dout; - -// bitslip block signals -reg bitslip_din_mux; -reg bitslip_din; -reg bitslip_des_clk; -reg bitslip_adj_1; -reg bitslip_adj_0; -reg bitslip_adj_pulse; -reg bitslip_dout; -reg bitslip_shifter_out; -reg [WIDTH-1:0] bit_shifter; -reg [3:0] bitslip_counter; - -// gbox clk gen -// FAST CLK -reg core_clk=0; -reg word_load_en; -reg [8:0] pll_lock_count; -reg [3:0] core_clk_count; - -// CDR CLOCK -reg cdr_core_clk=0; -reg cdr_word_load_en; -reg [8:0] cdr_pll_lock_count; -reg [3:0] cdr_core_clk_count; - -// deserializer block signals -reg [WIDTH-1:0] des_shifter; -reg [WIDTH-1:0] des_parallel_reg; -reg des_word_load_en; -wire des_fifo_empty; -wire des_fifo_full; - -// PLL PHASE SHIFTED CLOCKS -initial -begin - @(posedge PLL_CLK); - start_point= $realtime; - @(posedge PLL_CLK); - end_point = $realtime; - clk_period=end_point-start_point; - period_quarter=clk_period/4; - clk_start=1; - #1; -end - -// CLOCK 0 -always@(posedge PLL_CLK or negedge PLL_CLK) -begin - if(clk_start) - clk_0<=PLL_CLK; -end - -// CLOCK 90 & 180 -always@(posedge clk_0 or negedge clk_0) -begin - if(clk_start) - begin - #(period_quarter); - clk_90<=~clk_90; - #(period_quarter); - clk_180<=~clk_180; - end -end - -// CLOCK 270 -always@(posedge clk_180 or negedge clk_180) -begin - if(clk_start) - begin - #(period_quarter); - clk_270<=~clk_270; - end -end - -// DPA BLOCK // - -// clk 0 check -always@(posedge clk_0 or negedge RST) -begin - if(!RST) - begin - clk0_data_reg<=0; - clk0_data_comp<=0; - clk0_data_count<=0; - clk0_reg_data_count<=0; - end - else if(!DPA_LOCK && EN) - begin - clk0_data_reg<={clk0_data_reg[2:0],D}; - clk0_reg_data_count<=clk0_reg_data_count+1; - if(clk0_reg_data_count==3) // fill the 4 bit reg and compare with previous 4 bit data - begin - if(clk0_data_comp == clk0_data_reg) - begin - clk0_data_count<=clk0_data_count+1; - end - else //if mismatch then update the current reg value and restart dpa counter - begin - clk0_data_comp<=clk0_data_reg; - clk0_data_count<=0; - end - end - end -end - -// clk 90 check -always@(posedge clk_90 or negedge RST) -begin - if(!RST) - begin - clk90_data_reg<=0; - clk90_data_comp<=0; - clk90_data_count<=0; - clk90_reg_data_count<=0; - end - else if(!DPA_LOCK && EN) - begin - clk90_data_reg<={clk90_data_reg[2:0],D}; - clk90_reg_data_count<=clk90_reg_data_count+1; - if(clk90_reg_data_count==3) // fill the 4 bit reg and compare with previous 4 bit data - begin - if(clk90_data_comp == clk90_data_reg) - begin - clk90_data_count<=clk90_data_count+1; - end - else //if mismatch then update the current reg value and restart dpa counter - begin - clk90_data_comp<=clk90_data_reg; - clk90_data_count<=0; - end - end - end -end - -// clk 180 check -always@(posedge clk_180 or negedge RST) -begin - if(!RST) - begin - clk180_data_reg<=0; - clk180_data_comp<=0; - clk180_data_count<=0; - clk180_reg_data_count<=0; - end - else if(!DPA_LOCK && EN) - begin - clk180_data_reg<={clk180_data_reg[2:0],D}; - clk180_reg_data_count<=clk180_reg_data_count+1; - if(clk180_reg_data_count==3) // fill the 4 bit reg and compare with previous 4 bit data - begin - if(clk180_data_comp == clk180_data_reg) - begin - clk180_data_count<=clk180_data_count+1; - end - else //if mismatch then update the current reg value and restart dpa counter - begin - clk180_data_comp<=clk180_data_reg; - clk180_data_count<=0; - end - end - end -end - -// clk 270 check -always@(posedge clk_270 or negedge RST) -begin - if(!RST) - begin - clk270_data_reg<=0; - clk270_data_comp<=0; - clk270_data_count<=0; - clk270_reg_data_count<=0; - end - else if(!DPA_LOCK && EN) - begin - clk270_data_reg<={clk270_data_reg[2:0],D}; - clk270_reg_data_count<=clk270_reg_data_count+1; - if(clk270_reg_data_count==3) // fill the 4 bit reg and compare with previous 4 bit data - begin - if(clk270_data_comp == clk270_data_reg) - begin - clk270_data_count<=clk270_data_count+1; - end - else //if mismatch then update the current reg value and restart dpa counter - begin - clk270_data_comp<=clk270_data_reg; - clk270_data_count<=0; - end - end - end -end - - -always@(*) -begin - if(clk0_data_count==16) - begin - cdr_clk=clk_0; - dpa_lock=1; - dpa_error=0; - end - else if(clk90_data_count==16) - begin - cdr_clk=clk_90; - dpa_lock=1; - dpa_error=0; - end - else if(clk180_data_count==16) - begin - cdr_clk=clk_180; - dpa_lock=1; - dpa_error=0; - end - else if(clk270_data_count==16) - begin - cdr_clk=clk_270; - dpa_lock=1; - dpa_error=0; - end - else - dpa_lock=0; - - dpa_dout=D; - -end - -assign DPA_LOCK = dpa_lock; -assign DPA_ERROR= dpa_error; - -// DPA BLOCK END // - -// GBOX CLK GEN - -// FOR FAST CLOCK -// count cycles after PLL LOCK -always@(posedge PLL_CLK or negedge RST) -begin -if(!RST) - pll_lock_count<=0; -else if(!PLL_LOCK) - pll_lock_count<=0; - -// else if(PLL_LOCK && pll_lock_count<=31+(WIDTH/2)) // delay before clock starting = 32 clocks + rate_sel/2 clocks -else if(PLL_LOCK && pll_lock_count<=255) - pll_lock_count<=pll_lock_count+1; -end - -// Generate Core CLK And Word Load Enable -always@(posedge PLL_CLK or negedge RST) -begin -if(!RST) -begin - core_clk<=0; - core_clk_count<=0; - word_load_en<=0; -end - -else if(core_clk_count==WIDTH-1) -begin - core_clk_count<=0; - word_load_en<=1; -end -// else if(pll_lock_count>=31+(WIDTH/2)) // if delay before clock starting = 32 clocks + rate_sel/2 clocks -else if(pll_lock_count>=255) -begin - core_clk_count<=core_clk_count+1; - core_clk<=(core_clk_count=255) -begin - cdr_core_clk_count<=cdr_core_clk_count+1; - cdr_core_clk<=(cdr_core_clk_count 10)) begin - $fatal(1,"I_SERDES instance %m WIDTH set to incorrect value, %d. Values must be between 3 and 10.", WIDTH); - end - case(DPA_MODE) - "NONE" , - "DPA" , - "CDR": begin end - default: begin - $fatal(1,"\nError: I_SERDES instance %m has parameter DPA_MODE set to %s. Valid values are NONE, DPA, CDR\n", DPA_MODE); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT1.v b/models_customer/verilog/LUT1.v deleted file mode 100644 index c662bad..0000000 --- a/models_customer/verilog/LUT1.v +++ /dev/null @@ -1,21 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT1 simulation model -// 1-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module LUT1 #( - parameter [1:0] INIT_VALUE = 2'h0 // 2-bit LUT logic value -) ( - input A, // Data Input - output Y // Data Output -); - - assign Y = A ? INIT_VALUE[1] : INIT_VALUE[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT2.v b/models_customer/verilog/LUT2.v deleted file mode 100644 index 943993a..0000000 --- a/models_customer/verilog/LUT2.v +++ /dev/null @@ -1,22 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT2 simulation model -// 2-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module LUT2 #( - parameter [3:0] INIT_VALUE = 4'h0 // 4-bit LUT logic value -) ( - input [1:0] A, // Data Input - output Y // Data Output -); - - wire [ 1: 0] s1 = A[1] ? INIT_VALUE[ 3: 2] : INIT_VALUE[ 1: 0]; - assign Y = A[0] ? s1[1] : s1[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT3.v b/models_customer/verilog/LUT3.v deleted file mode 100644 index c5e45cd..0000000 --- a/models_customer/verilog/LUT3.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT3 simulation model -// 3-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module LUT3 #( - parameter [7:0] INIT_VALUE = 8'h00 // 8-bit LUT logic value -) ( - input [2:0] A, // Data Input - output Y // Data Output -); - - wire [ 3: 0] s2 = A[2] ? INIT_VALUE[ 7: 4] : INIT_VALUE[ 3: 0]; - wire [ 1: 0] s1 = A[1] ? s2[ 3: 2] : s2[ 1: 0]; - assign Y = A[0] ? s1[1] : s1[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT4.v b/models_customer/verilog/LUT4.v deleted file mode 100644 index 0603918..0000000 --- a/models_customer/verilog/LUT4.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT4 simulation model -// 4-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - - -module LUT4 #( - parameter [15:0] INIT_VALUE = 16'h0000 // 16-bit LUT logic value -) ( - input [3:0] A, // Data Input - output Y // Data Output -); - - wire [ 7: 0] s3 = A[3] ? INIT_VALUE[15: 8] : INIT_VALUE[ 7: 0]; - wire [ 3: 0] s2 = A[2] ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = A[1] ? s2[ 3: 2] : s2[ 1: 0]; - - assign Y = A[0] ? s1[1] : s1[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT5.v b/models_customer/verilog/LUT5.v deleted file mode 100644 index 40aed25..0000000 --- a/models_customer/verilog/LUT5.v +++ /dev/null @@ -1,25 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT5 simulation model -// 5-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module LUT5 #( - parameter [31:0] INIT_VALUE = 32'h00000000 // LUT logic value -) ( - input [4:0] A, // Data Input - output Y // Data Output -); - - wire [15: 0] s4 = A[4] ? INIT_VALUE[31:16] : INIT_VALUE[15: 0]; - wire [ 7: 0] s3 = A[3] ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = A[2] ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = A[1] ? s2[ 3: 2] : s2[ 1: 0]; - assign Y = A[0] ? s1[1] : s1[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/LUT6.v b/models_customer/verilog/LUT6.v deleted file mode 100644 index e933ec9..0000000 --- a/models_customer/verilog/LUT6.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// LUT6 simulation model -// 6-input lookup table (LUT) -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module LUT6 #( - parameter [63:0] INIT_VALUE = 64'h0000000000000000 // 64-bit LUT logic value -) ( - input [5:0] A, // Data Input - output Y // Data Output -); - - wire [31: 0] s5 = A[5] ? INIT_VALUE[63:32] : INIT_VALUE[31: 0]; - wire [15: 0] s4 = A[4] ? s5[31:16] : s5[15: 0]; - wire [ 7: 0] s3 = A[3] ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = A[2] ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = A[1] ? s2[ 3: 2] : s2[ 1: 0]; - assign Y = A[0] ? s1[1] : s1[0]; - - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_BUF.v b/models_customer/verilog/O_BUF.v deleted file mode 100644 index 54b45d7..0000000 --- a/models_customer/verilog/O_BUF.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_BUF simulation model -// Output buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_BUF -( - input I, // Data input - output O // Data output (connect to top-level port) -); - - assign O = I ; - initial begin - - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_BUFT.v b/models_customer/verilog/O_BUFT.v deleted file mode 100644 index d0f48e5..0000000 --- a/models_customer/verilog/O_BUFT.v +++ /dev/null @@ -1,42 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_BUFT simulation model -// Output tri-state buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_BUFT #( - parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -) ( - input I, // Data input - input T, // Tri-state output - output O // Data output (connect to top-level port) -); - - generate - if ( WEAK_KEEPER == "PULLUP" ) begin: add_pullup - pullup(O); - end else if ( WEAK_KEEPER == "PULLDOWN" ) begin: add_pulldown - pulldown(O); - end - endgenerate - - assign O = T ? I : 1'bz; - - initial begin - case(WEAK_KEEPER) - "NONE" , - "PULLUP" , - "PULLDOWN": begin end - default: begin - $fatal(1,"\nError: O_BUFT instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER); - end - endcase - - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_BUFT_DS.v b/models_customer/verilog/O_BUFT_DS.v deleted file mode 100644 index e2a9885..0000000 --- a/models_customer/verilog/O_BUFT_DS.v +++ /dev/null @@ -1,46 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_BUFT_DS simulation model -// Output differential tri-state buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_BUFT_DS #( - parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -) ( - input I, // Data input - input T, // Tri-state output - output O_P, // Data positive output (connect to top-level port) - output O_N // Data negative output (connect to top-level port) -); - - generate - if ( WEAK_KEEPER == "PULLUP" ) begin: add_pullup - pullup(O_P); - pullup(O_N); - end else if ( WEAK_KEEPER == "PULLDOWN" ) begin: add_pulldown - pulldown(O_P); - pulldown(O_N); - end - endgenerate - - assign O_P = T ? I : 'hz; - assign O_N = T ? ~I : 'hz; - - initial begin - case(WEAK_KEEPER) - "NONE" , - "PULLUP" , - "PULLDOWN": begin end - default: begin - $fatal(1,"\nError: O_BUFT_DS instance %m has parameter WEAK_KEEPER set to %s. Valid values are NONE, PULLUP, PULLDOWN\n", WEAK_KEEPER); - end - endcase - - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_BUF_DS.v b/models_customer/verilog/O_BUF_DS.v deleted file mode 100644 index 4985edd..0000000 --- a/models_customer/verilog/O_BUF_DS.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_BUF_DS simulation model -// Output differential buffer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_BUF_DS -( - input I, // Data input - output O_P, // Data positive output (connect to top-level port) - output O_N // Data negative output (connect to top-level port) -); - - assign O_P = I; - assign O_N = ~I; - - initial begin - - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_DDR.v b/models_customer/verilog/O_DDR.v deleted file mode 100644 index d7b6c8f..0000000 --- a/models_customer/verilog/O_DDR.v +++ /dev/null @@ -1,63 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_DDR simulation model -// DDR output register -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_DDR ( - input [1:0] D, // Data input - input R, // Active-low asynchrnous reset - input E, // Active-high enable - input C, // Clock - output reg Q = 1'b0 // Data output (connect to output port, buffer or O_DELAY) -); - - reg Q0; - reg Qp; - reg Q1; - - always @(negedge R) - Q <= 1'b0; - - always@(posedge C) - begin - if(!R) - begin - Qp<=0; - Q0<=0; - end - - else - begin - Q0<=D[0]; - Qp<=D[1]; - end - end - - always@(negedge C) - begin - if(!R) - Q1<=0; - else - Q1<=Qp; - end - - - always @(*) - begin - if (!R) - Q <= 1'b0; - else if (E) - if (C) - Q <= Q0; - else - Q <= Q1; - else - Q <= Q; - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_DELAY.v b/models_customer/verilog/O_DELAY.v deleted file mode 100644 index 470438d..0000000 --- a/models_customer/verilog/O_DELAY.v +++ /dev/null @@ -1,68 +0,0 @@ -`timescale 1ps/1ps -`celldefine -// -// O_DELAY simulation model -// Serdes output -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_DELAY #( - parameter DELAY = 0 // TAP delay value (0-63) -) ( - input I, // Data input - input DLY_LOAD, // Delay load input - input DLY_ADJ, // Delay adjust input - input DLY_INCDEC, // Delay increment / decrement input - output [5:0] DLY_TAP_VALUE, // Delay tap value output - input CLK_IN, // Clock input - output O // Data output -); - -// Adding local variable for delay load -reg dly_ld_0, dly_ld_1; -wire dly_ld_p; - -// Adding local variable for delay adjust -reg dly_adj_0, dly_adj_1; -wire dly_adj_p; - -// reg counter; -reg [5:0] dly_tap_val = 0; - -always_ff @(posedge CLK_IN) -begin - dly_ld_0 <= DLY_LOAD; - dly_ld_1 <= dly_ld_0; - - dly_adj_0 <= DLY_ADJ; - dly_adj_1 <= dly_adj_0; -end - -// Detecting 0 to 1 transition -assign dly_ld_p = dly_ld_0 && !dly_ld_1; -assign dly_adj_p = dly_adj_0 && !dly_adj_1; - -always_ff @(posedge CLK_IN) -begin - if (dly_ld_p) - dly_tap_val <= DELAY; - else if (dly_adj_p && DLY_INCDEC && dly_tap_val!=63) - dly_tap_val <= dly_tap_val + 1; - else if (dly_adj_p && !DLY_INCDEC && dly_tap_val!=0) - dly_tap_val <= dly_tap_val - 1; -end - -assign DLY_TAP_VALUE = dly_tap_val; -assign #(30.0ps + (21.56ps*dly_tap_val)) O = I; // Adjusted Delay for TT corner - - initial begin - - if ((DELAY < 0) || (DELAY > 63)) begin - $fatal(1,"O_DELAY instance %m DELAY set to incorrect value, %d. Values must be between 0 and 63.", DELAY); - end - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_FAB.v b/models_customer/verilog/O_FAB.v deleted file mode 100644 index 956a0a2..0000000 --- a/models_customer/verilog/O_FAB.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_FAB simulation model -// Marker Buffer for fabric to periphery transition -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_FAB ( - input I, // Input - output O // Output -); - -assign O = I ; - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_SERDES.v b/models_customer/verilog/O_SERDES.v deleted file mode 100644 index 482b693..0000000 --- a/models_customer/verilog/O_SERDES.v +++ /dev/null @@ -1,258 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_SERDES simulation model -// Output Serializer -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - - - - -module SyncFIFO #( - parameter DEPTH = 4, - parameter DATA_WIDTH = 5 - )( - input wire clk, // core clock - input wire reset, - input wire wr_en, - input wire rd_en, - input wire [DATA_WIDTH:0] wr_data, - output wire [DATA_WIDTH:0] rd_data, - output wire empty, - output wire full, - output wire almost_full - ); - - reg [DATA_WIDTH:0] fifo [DEPTH-1:0]; - reg [DATA_WIDTH:0] rd_data_reg; - reg [$clog2(DEPTH)-1:0] wr_ptr, rd_ptr; - - assign empty = (wr_ptr == rd_ptr); - assign full = ((wr_ptr == rd_ptr - 1) || (wr_ptr == DEPTH - 1 && rd_ptr == 0)); - assign almost_full = !empty; //(wr_ptr >= (DEPTH - 4)); - - always @(posedge clk or negedge reset) - begin - if(!reset) - begin - rd_data_reg <= 0; - wr_ptr <= 0; - rd_ptr <= 0; - for (int i = 0; i< DEPTH; i++) - fifo[i] <= '0; - end - else - begin - if(wr_en && !full) - begin - fifo[wr_ptr] <= wr_data; - wr_ptr <= wr_ptr + 1; - end - if(rd_en && !empty) - begin - rd_data_reg <= fifo[rd_ptr]; - rd_ptr <= rd_ptr + 1; - end - end - end - - assign rd_data = rd_data_reg; - -endmodule - - -module O_SERDES #( - parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR) - parameter WIDTH = 4 // Width of input data to serializer (3-10) -) ( - input [WIDTH-1:0] D, // D input bus - input RST, // Active-low, asynchronous reset - input DATA_VALID, // Active high data valid signal - input CLK_IN, // Fabric clock input - input OE_IN, // Output tri-state enable input - output OE_OUT, // Output tri-state enable output (conttect to O_BUFT or inferred tri-state signal) - output Q, // Data output (Connect to output port, buffer or O_DELAY) - input CHANNEL_BOND_SYNC_IN, // Channel bond sync input - output CHANNEL_BOND_SYNC_OUT, // Channel bond sync output - input PLL_LOCK, // PLL lock input - input PLL_CLK // PLL clock input -); - - - // GBOX CLK GEN - reg core_clk=0; - reg word_load_en; - reg [8:0] pll_lock_count; - reg [3:0] core_clk_count; - - - // count cycles after PLL LOCK - always@(posedge PLL_CLK or negedge RST) - begin - if(!RST) - pll_lock_count<=0; - else if(!PLL_LOCK) - pll_lock_count<=0; - - // else if(PLL_LOCK && pll_lock_count<=31+(WIDTH/2)) // delay before clock starting = 32 clocks + rate_sel/2 clocks - else if(PLL_LOCK && pll_lock_count<=255) - pll_lock_count<=pll_lock_count+1; - end - - // Generate Core CLK And Word Load Enable - always@(posedge PLL_CLK or negedge RST) - begin - if(!RST) - begin - core_clk<=0; - core_clk_count<=0; - word_load_en<=0; - end - - else if(core_clk_count==WIDTH-1) - begin - core_clk_count<=0; - word_load_en<=1; - end - // else if(pll_lock_count>=31+(WIDTH/2)) // if delay before clock starting = 32 clocks + rate_sel/2 clocks - else if(pll_lock_count>=255) - begin - core_clk_count<=core_clk_count+1; - core_clk<=(core_clk_count 10)) begin - $fatal(1,"O_SERDES instance %m WIDTH set to incorrect value, %d. Values must be between 3 and 10.", WIDTH); - end - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/O_SERDES_CLK.v b/models_customer/verilog/O_SERDES_CLK.v deleted file mode 100644 index 674d02f..0000000 --- a/models_customer/verilog/O_SERDES_CLK.v +++ /dev/null @@ -1,72 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// O_SERDES_CLK simulation model -// Output Serializer Clock -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module O_SERDES_CLK #( - parameter DATA_RATE = "SDR", // Single or double data rate (SDR/DDR) - parameter CLOCK_PHASE = 0 // Clock phase (0,90,180,270) -) ( - input CLK_EN, // Gates output OUTPUT_CLK - output reg OUTPUT_CLK = 1'b0, // Clock output (Connect to output port, buffer or O_DELAY) - input PLL_LOCK, // PLL lock input - input PLL_CLK // PLL clock input -); - - time period = 0.0; // This is the calculated period for OUTPUT_CLOCK after PLL_LOCK - localparam ddr_multiplier = (DATA_RATE == "DDR") ? 2.0 : 1.0; // If operating in DDR, must multiply period by 2 - localparam phase_multiplier = (CLOCK_PHASE == 90) ? 0.25 : // Phase offset - (CLOCK_PHASE == 180) ? 0.5 : - (CLOCK_PHASE == 270) ? 0.75 : - 0; - - reg clock_enabled = 1'b0; // Enables clock 256 cycles after LOCK - - always begin - if (!clock_enabled && PLL_LOCK) begin - @(posedge PLL_CLK); - period = $realtime; - @(posedge PLL_CLK); - period = ($realtime - period); - period = period*ddr_multiplier*2.0; // Calculated period for output clock - clock_enabled = 1'b1; - repeat(254) - @(posedge PLL_CLK); // Wait 256 PLL_CLKs after lock to enable clock - #(period*phase_multiplier); - end else if (!PLL_LOCK) begin - clock_enabled = 1'b0; - @(posedge PLL_LOCK); - end else - if (CLK_EN) begin - #(period/2.0) OUTPUT_CLK = ~OUTPUT_CLK; - end else begin - OUTPUT_CLK = 1'b0; - @(posedge CLK_EN); - end - end - initial begin - case(DATA_RATE) - "SDR" , - "DDR": begin end - default: begin - $fatal(1,"\nError: O_SERDES_CLK instance %m has parameter DATA_RATE set to %s. Valid values are SDR, DDR\n", DATA_RATE); - end - endcase - case(CLOCK_PHASE) - 0 , - 90 , - 180 , - 270: begin end - default: begin - $fatal(1,"\nError: O_SERDES_CLK instance %m has parameter CLOCK_PHASE set to %d. Valid values are 0, 90, 180, 270\n", CLOCK_PHASE); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/PLL.v b/models_customer/verilog/PLL.v deleted file mode 100644 index 1efcd89..0000000 --- a/models_customer/verilog/PLL.v +++ /dev/null @@ -1,276 +0,0 @@ -`timescale 1ps/10fs -`celldefine -// -// PLL simulation model -// Phase locked loop -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module PLL #( - parameter DEV_FAMILY = "VIRGO", // Device Family - parameter DIVIDE_CLK_IN_BY_2 = "FALSE", // Enable input divider (TRUE/FALSE) - parameter PLL_MULT = 16, // VCO clock multiplier value (16-640) - parameter PLL_DIV = 1, // VCO clock divider value (1-63) - parameter PLL_MULT_FRAC = 0, // Fraction mode not supported - parameter PLL_POST_DIV = 17 // VCO clock post-divider value (17,18,19,20,21,22,23,34,35,36,37,38,39,51,52,53,54,55,68,69,70,71,85,86,87,102,103,119) -) ( - input PLL_EN, // PLL Enable - input CLK_IN, // Clock input - output CLK_OUT, // Output clock, frequency is (CLK_IN/PLL_DIV)*(PLL_MULT/(PLL_POST_DIV0*PLL_POST_DIV1)) - output CLK_OUT_DIV2, // CLK_OUT divided by 2 output - output CLK_OUT_DIV3, // CLK_OUT divided by 3 output - output CLK_OUT_DIV4, // CLK_OUT divided by 4 output - output FAST_CLK, // VCO clock output, frequency is (CLK_IN/PLL_DIV)*(PLL_MULT) - output LOCK // PLL lock signal -); - -localparam FAST_LOCK = 0; // Reduce lock time - - localparam real REF_MAX_PERIOD = PLL_MULT_FRAC ? 100000: 200000; //10 MHz or 5 MHz - localparam real REF_MIN_PERIOD = 833.33 ; //1200 MHz - - localparam real VCO_MAX_PERIOD = 62500; //16 MHz - localparam real VCO_MIN_PERIOD = 312.5; //3200 MHz - - - localparam LOCK_TIMER = FAST_LOCK ? 10 : 500; - - logic [ 2:0] PLL_POST_DIV0; - logic [ 2:0] PLL_POST_DIV1; - - assign PLL_POST_DIV0 = PLL_POST_DIV[2:0]; - assign PLL_POST_DIV1 = PLL_POST_DIV[6:4]; -//--------------------------- - real t0 ; - real t1 ; - real ref_period ; - real vco_period ; - real postdiv_period ; - real old_ref_period ; - logic clk_pll ; - logic pllen_rse ; - logic pllstart = 0; - logic pllstart_ff1 = 0; - logic pllstart_ff2 = 0; - logic vcostart = 0; - logic vcostart_ff = 0; - logic lose_lock = 0; - logic clk_out_div2 = 0; - logic clk_out_div3 = 0; - logic clk_out_div4 = 0; - logic clk_vco ; - logic clk_postdiv ; - integer div3_count = 1; - logic [ 5:0] PLL_DIV_ff = 0; - logic [11:0] PLL_MULT_ff = 0; - - logic [$clog2(LOCK_TIMER)-1:0] lock_counter = 0; - - - assign pllen_rse = pllstart==1 && pllstart_ff2==0; - - always @ (posedge CLK_IN) begin - if(PLL_EN) pllstart <= 1; - else pllstart <= 0; - - pllstart_ff1 <= pllstart; - pllstart_ff2 <= pllstart_ff1; - - end - - always @ (posedge CLK_IN) begin - if(pllstart_ff2) vcostart <= 1; - else vcostart <= 0; - - vcostart_ff <= vcostart; - end - - - always @ (posedge CLK_IN) begin - @(posedge CLK_IN) t0 = $realtime; - @(posedge CLK_IN) t1 = $realtime; - ref_period = t1 - t0; - vco_period = DIVIDE_CLK_IN_BY_2=="TRUE" ? (ref_period*PLL_DIV*2)/PLL_MULT : (ref_period*PLL_DIV)/PLL_MULT; - postdiv_period = DIVIDE_CLK_IN_BY_2=="TRUE" ? (ref_period*PLL_DIV*2*PLL_POST_DIV0*PLL_POST_DIV1)/PLL_MULT : (ref_period*PLL_DIV*PLL_POST_DIV0*PLL_POST_DIV1)/PLL_MULT; - end - - always @ (posedge CLK_IN) begin - old_ref_period = ref_period; - end - - initial begin - clk_vco = 0; - forever begin - wait(vcostart_ff) - #(vco_period/2) clk_vco = PLL_EN ? ~clk_vco : '0; - end - end - - - initial begin - clk_postdiv = 0; - forever begin - wait(vcostart_ff) - #(postdiv_period/2) clk_postdiv = PLL_EN ? ~clk_postdiv : '0; - end - end - - - always @(posedge CLK_IN) begin - PLL_DIV_ff <= PLL_DIV; - PLL_MULT_ff <= PLL_MULT; - end - - always @ (posedge CLK_IN, negedge PLL_EN) begin - if(LOCK==0 & vcostart) lock_counter <= lock_counter + 1; - else if(lose_lock || PLL_EN==0 || PLL_MULT_ff!=PLL_MULT || PLL_DIV_ff!=PLL_DIV ) lock_counter <= 0; - end - - - always @(posedge CLK_OUT, negedge PLL_EN) - if(PLL_EN==0) clk_out_div2 = 1'b0; - else clk_out_div2 = ~clk_out_div2; - - always @(CLK_OUT, negedge PLL_EN) - if(PLL_EN==0) clk_out_div3 = 1'b0; - else begin - if (div3_count==2) begin - clk_out_div3 = ~clk_out_div3; - div3_count = 0; - end else - div3_count = div3_count + 1; - end - - always @(posedge clk_out_div2, negedge PLL_EN) - if(PLL_EN==0) clk_out_div4 = 1'b0; - else clk_out_div4 = ~clk_out_div4; - - - assign CLK_OUT = (PLL_POST_DIV0==1 && PLL_POST_DIV0==1) ? clk_vco : clk_postdiv; - assign CLK_OUT_DIV2 = clk_out_div2; - assign CLK_OUT_DIV3 = clk_out_div3; - assign CLK_OUT_DIV4 = clk_out_div4; - assign FAST_CLK = clk_vco; - assign LOCK = lock_counter >= LOCK_TIMER; - - - - // Checking for proper CLK_IN and VCO frequencies - always @ (posedge CLK_IN) begin - if(pllstart_ff2)begin - if (ref_periodVCO_MAX_PERIOD) begin - $fatal(1,"\nError at time %t: PLL instance %m REF clock period %0d fs violates maximum period.\nMust be less than %0d fs.\n", $realtime, ref_period, VCO_MAX_PERIOD); - end - end - end - - - always @ (posedge CLK_IN) begin - if ((LOCK==1'b1) && (ref_period > old_ref_period*1.05) || (ref_period < old_ref_period*0.95)) begin - $display("Warning at time %t: PLL instance %m input clock, CLK_IN, changed frequency and lost lock. Current value = %0d fs, old value = %d fs.\n", $realtime, ref_period, old_ref_period); - lose_lock = 1; - end - else lose_lock = 0; - end - - always @ (posedge FAST_CLK) begin - if(vcostart_ff) begin - if (vco_periodVCO_MAX_PERIOD) begin - $fatal(1,"\nError at time %t: PLL instance %m VCO clock period %0d fs violates maximum period.\nMust be less than %0d fs.\nTry increasing PLL_MULT or decreasing PLL_DIV values.\n", $realtime, vco_period, VCO_MAX_PERIOD); - end - end - end - - - - // Checking control inputs - always @ (posedge CLK_IN, posedge PLL_EN) begin - if(PLL_EN)begin - if(PLL_POST_DIV0==0)begin - $fatal(1,"Error at time %t: \n \t PLL instance %m, PLL_POST_DIV0 is equal to zero.\n \t Must be greater than 0", $realtime); - end - - else if(PLL_POST_DIV1==0)begin - $fatal(1,"Error at time %t: \n \t PLL instance %m, PLL_POST_DIV1 is equal to zero.\n \t Must be greater than 0", $realtime); - end - - - else if(PLL_POST_DIV1>PLL_POST_DIV0) begin - $fatal(1,"Error at time %t: PLL_POST_DIV1 > PLL_POST_DIV0\n", $realtime); - end - end - end - - initial begin - case(DEV_FAMILY) - "VIRGO": begin end - default: begin - $fatal(1,"\nError: PLL instance %m has parameter DEV_FAMILY set to %s. Valid values are VIRGO\n", DEV_FAMILY); - end - endcase - case(DIVIDE_CLK_IN_BY_2) - "TRUE" , - "FALSE": begin end - default: begin - $fatal(1,"\nError: PLL instance %m has parameter DIVIDE_CLK_IN_BY_2 set to %s. Valid values are TRUE, FALSE\n", DIVIDE_CLK_IN_BY_2); - end - endcase - - if ((PLL_MULT < 16) || (PLL_MULT > 640)) begin - $fatal(1,"PLL instance %m PLL_MULT set to incorrect value, %d. Values must be between 16 and 640.", PLL_MULT); - end - - if ((PLL_DIV < 1) || (PLL_DIV > 63)) begin - $fatal(1,"PLL instance %m PLL_DIV set to incorrect value, %d. Values must be between 1 and 63.", PLL_DIV); - end - case(PLL_MULT_FRAC) - 0: begin end - default: begin - $fatal(1,"\nError: PLL instance %m has parameter PLL_MULT_FRAC set to %d. Valid values are 0\n", PLL_MULT_FRAC); - end - endcase - case(PLL_POST_DIV) - 17 , - 18 , - 19 , - 20 , - 21 , - 22 , - 23 , - 34 , - 35 , - 36 , - 37 , - 38 , - 39 , - 51 , - 52 , - 53 , - 54 , - 55 , - 68 , - 69 , - 70 , - 71 , - 85 , - 86 , - 87 , - 102 , - 103 , - 119: begin end - default: begin - $fatal(1,"\nError: PLL instance %m has parameter PLL_POST_DIV set to %d. Valid values are 17, 18, 19, 20, 21, 22, 23, 34, 35, 36, 37, 38, 39, 51, 52, 53, 54, 55, 68, 69, 70, 71, 85, 86, 87, 102, 103, 119\n", PLL_POST_DIV); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/README.txt b/models_customer/verilog/README.txt deleted file mode 100644 index 3e1ac1a..0000000 --- a/models_customer/verilog/README.txt +++ /dev/null @@ -1 +0,0 @@ -This directory contains Verilog models. diff --git a/models_customer/verilog/SOC_FPGA_INTF_AHB_M.v b/models_customer/verilog/SOC_FPGA_INTF_AHB_M.v deleted file mode 100644 index 1735337..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_AHB_M.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_AHB_M simulation model -// SOC interface connection AHB Master -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_AHB_M ( - input HRESETN_I, // None - input [31:0] HADDR, // None - input [2:0] HBURST, // None - input [3:0] HPROT, // None - input [2:0] HSIZE, // None - input [2:0] HTRANS, // None - input [31:0] HWDATA, // None - input HWWRITE, // None - output [31:0] HRDATA, // None - output HREADY, // None - output HRESP, // None - input HCLK // None -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_AHB_S.v b/models_customer/verilog/SOC_FPGA_INTF_AHB_S.v deleted file mode 100644 index 00b1556..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_AHB_S.v +++ /dev/null @@ -1,29 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_AHB_S simulation model -// SOC interface connection AHB Slave -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_AHB_S ( - output HRESETN_I, // None - output [31:0] HADDR, // None - output [2:0] HBURST, // None - output HMASTLOCK, // None - input HREADY, // None - output [3:0] HPROT, // None - input [31:0] HRDATA, // None - input HRESP, // None - output HSEL, // None - output [2:0] HSIZE, // None - output [1:0] HTRANS, // None - output [3:0] HWBE, // None - output [31:0] HWDATA, // None - output HWRITE, // None - input HCLK // None -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_AXI_M0.v b/models_customer/verilog/SOC_FPGA_INTF_AXI_M0.v deleted file mode 100644 index 2396fae..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_AXI_M0.v +++ /dev/null @@ -1,51 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_AXI_M0 simulation model -// SOC interface connection AXI Master 0 -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_AXI_M0 ( - input [31:0] M0_ARADDR, // None - input [1:0] M0_ARBURST, // None - input [3:0] M0_ARCACHE, // None - input [3:0] M0_ARID, // None - input [2:0] M0_ARLEN, // None - input M0_ARLOCK, // None - input [2:0] M0_ARPROT, // None - output M0_ARREADY, // None - input [2:0] M0_ARSIZE, // None - input M0_ARVALID, // None - input [31:0] M0_AWADDR, // None - input [1:0] M0_AWBURST, // None - input [3:0] M0_AWCACHE, // None - input [3:0] M0_AWID, // None - input [2:0] M0_AWLEN, // None - input M0_AWLOCK, // None - input [2:0] M0_AWPROT, // None - output M0_AWREADY, // None - input [2:0] M0_AWSIZE, // None - input M0_AWVALID, // None - output [3:0] M0_BID, // None - input M0_BREADY, // None - output [1:0] M0_BRESP, // None - output M0_BVALID, // None - output [63:0] M0_RDATA, // None - output [3:0] M0_RID, // None - output M0_RLAST, // None - input M0_RREADY, // None - output [1:0] M0_RRESP, // None - output M0_RVALID, // None - input [63:0] M0_WDATA, // None - input M0_WLAST, // None - output M0_WREADY, // None - input [7:0] M0_WSTRB, // None - input M0_WVALID, // None - input M0_ACLK, // None - output M0_ARESETN_I // None -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_AXI_M1.v b/models_customer/verilog/SOC_FPGA_INTF_AXI_M1.v deleted file mode 100644 index 7c7ebf2..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_AXI_M1.v +++ /dev/null @@ -1,51 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_AXI_M1 simulation model -// SOC interface connection AXI Master 1 -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_AXI_M1 ( - input [31:0] M1_ARADDR, // None - input [1:0] M1_ARBURST, // None - input [3:0] M1_ARCACHE, // None - input [3:0] M1_ARID, // None - input [2:0] M1_ARLEN, // None - input M1_ARLOCK, // None - input [2:0] M1_ARPROT, // None - output M1_ARREADY, // None - input [2:0] M1_ARSIZE, // None - input M1_ARVALID, // None - input [31:0] M1_AWADDR, // None - input [1:0] M1_AWBURST, // None - input [3:0] M1_AWCACHE, // None - input [3:0] M1_AWID, // None - input [2:0] M1_AWLEN, // None - input M1_AWLOCK, // None - input [2:0] M1_AWPROT, // None - output M1_AWREADY, // None - input [2:0] M1_AWSIZE, // None - input M1_AWVALID, // None - output [3:0] M1_BID, // None - input M1_BREADY, // None - output [1:0] M1_BRESP, // None - output M1_BVALID, // None - output [63:0] M1_RDATA, // None - output [3:0] M1_RID, // None - output M1_RLAST, // None - input M1_RREADY, // None - output [1:0] M1_RRESP, // None - output M1_RVALID, // None - input [63:0] M1_WDATA, // None - input M1_WLAST, // None - output M1_WREADY, // None - input [7:0] M1_WSTRB, // None - input M1_WVALID, // None - input M1_ACLK, // None - output M1_ARESETN_I // None -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_DMA.v b/models_customer/verilog/SOC_FPGA_INTF_DMA.v deleted file mode 100644 index 76420a3..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_DMA.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_DMA simulation model -// SOC DMA interface -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_DMA ( - input [3:0] DMA_REQ, // DMA request - output [3:0] DMA_ACK, // DMA acknowledge - input DMA_CLK, // DMA clock - input DMA_RST_N // DMA reset -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_IRQ.v b/models_customer/verilog/SOC_FPGA_INTF_IRQ.v deleted file mode 100644 index 642853c..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_IRQ.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_IRQ simulation model -// SOC Interupt connection -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_IRQ ( - input [15:0] IRQ_SRC, // Interupt source - output [15:0] IRQ_SET, // Interupt set - input IRQ_CLK, // interupt clock - input IRQ_RST_N // Interupt reset -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_INTF_JTAG.v b/models_customer/verilog/SOC_FPGA_INTF_JTAG.v deleted file mode 100644 index c115535..0000000 --- a/models_customer/verilog/SOC_FPGA_INTF_JTAG.v +++ /dev/null @@ -1,20 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_INTF_JTAG simulation model -// SOC JTAG connection -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_INTF_JTAG ( - input BOOT_JTAG_TCK, // JTAG TCK - output reg BOOT_JTAG_TDI = 1'b0, // JTAG TDI - input BOOT_JTAG_TDO, // JTAG TDO - output reg BOOT_JTAG_TMS = 1'b0, // JTAG TMS - output reg BOOT_JTAG_TRSTN = 1'b0, // JTAG TRSTN - input BOOT_JTAG_EN // JTAG enable -); - -endmodule -`endcelldefine diff --git a/models_customer/verilog/SOC_FPGA_TEMPERATURE.v b/models_customer/verilog/SOC_FPGA_TEMPERATURE.v deleted file mode 100644 index 67727a0..0000000 --- a/models_customer/verilog/SOC_FPGA_TEMPERATURE.v +++ /dev/null @@ -1,80 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// SOC_FPGA_TEMPERATURE simulation model -// SOC Temperature Interface -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module SOC_FPGA_TEMPERATURE #( - parameter INITIAL_TEMPERATURE = 25, // Specify initial temperature for simulation (0-125) - parameter TEMPERATURE_FILE = "" // Specify ASCII file containing temperature values over time -) ( - output reg [7:0] TEMPERATURE = INITIAL_TEMPERATURE, // Temperature data - output reg VALID = 1'b0, // Temperature data valid - output reg ERROR = 1'b0 // Temperature error -); - - localparam temperature_update_time = 2000.0; // Update temperature every 2 uS - - integer temp_file; - integer scan_temp_file; - integer d; - integer temp_file_line = 1; - real delay_time, temp_time; - integer temp_data = INITIAL_TEMPERATURE, temp_data2 = INITIAL_TEMPERATURE; - reg valid_data= 1'b1, error_data = 1'b0, valid_data2= 1'b1, error_data2 = 1'b0; - reg [8*80:0] comment; - - always begin - if ((temp_data2<0) || (temp_data2>125)) begin - $display("\nError: Temperature specified at %d is out of range, 0-125C.", temp_data2); - $finish; - end - #temperature_update_time TEMPERATURE = temp_data2; - VALID = valid_data2; - ERROR = error_data2; - end - - initial begin - if (TEMPERATURE_FILE != "no_file") begin - temp_file = $fopenr(TEMPERATURE_FILE); - if (temp_file == 0) begin - $display("\nError: Could not locate TEMPEARTURE_FILE %s.\nSpecify no_file for TEMPERATUE_FILE if not modifying tempearture for simulation.\n", TEMPERATURE_FILE); - #1; - $finish; - end - scan_temp_file = $fgetc(temp_file); - while (scan_temp_file != 32'hffffffff) begin - d = $ungetc(scan_temp_file, temp_file); - if (scan_temp_file != "#") begin - d = $fscanf(temp_file," %f: %d %b %b\n", temp_time, temp_data, valid_data, error_data); - if ($realtime > temp_time) begin - $display("\nError: Time specified on line %0d of %0s: %0t is earlier than a previous specified simulation time.\nSimulation times must appear in increasing order.\n", temp_file_line, TEMPERATURE_FILE, temp_time); - $finish; - end - #(temp_time - $realtime); - temp_data2 = temp_data; - valid_data2 = valid_data; - error_data2 = error_data; - end else begin - d = $fgets(comment, temp_file); - end - scan_temp_file = $fgetc(temp_file); - temp_file_line = temp_file_line + 1; - end - $fclose(temp_file); - end - end - - initial begin - - if ((INITIAL_TEMPERATURE < 0) || (INITIAL_TEMPERATURE > 125)) begin - $fatal(1,"SOC_FPGA_TEMPERATURE instance %m INITIAL_TEMPERATURE set to incorrect value, %d. Values must be between 0 and 125.", INITIAL_TEMPERATURE); - end - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/TDP_RAM18KX2.v b/models_customer/verilog/TDP_RAM18KX2.v deleted file mode 100644 index afd8d7a..0000000 --- a/models_customer/verilog/TDP_RAM18KX2.v +++ /dev/null @@ -1,924 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// TDP_RAM18KX2 simulation model -// Dual 18Kb True-dual-port RAM -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module TDP_RAM18KX2 #( - /* verilator lint_off WIDTHCONCAT */ - parameter [16383:0] INIT1 = {16384{1'b0}}, // Initial Contents of data memory, RAM 1 - /* verilator lint_on WIDTHCONCAT */ - parameter [2047:0] INIT1_PARITY = {2048{1'b0}}, // Initial Contents of parity memory, RAM 1 - parameter WRITE_WIDTH_A1 = 18, // Write data width on port A, RAM 1 (1, 2, 4, 9, 18) - parameter WRITE_WIDTH_B1 = 18, // Write data width on port B, RAM 1 (1, 2, 4, 9, 18) - parameter READ_WIDTH_A1 = 18, // Read data width on port A, RAM 1 (1, 2, 4, 9, 18) - parameter READ_WIDTH_B1 = 18, // Read data width on port B, RAM 1 (1, 2, 4, 9, 18) - /* verilator lint_off WIDTHCONCAT */ - parameter [16383:0] INIT2 = {16384{1'b0}}, // Initial Contents of memory, RAM 2 - /* verilator lint_on WIDTHCONCAT */ - parameter [2047:0] INIT2_PARITY = {2048{1'b0}}, // Initial Contents of memory, RAM 2 - parameter WRITE_WIDTH_A2 = 18, // Write data width on port A, RAM 2 (1, 2, 4, 9, 18) - parameter WRITE_WIDTH_B2 = 18, // Write data width on port B, RAM 2 (1, 2, 4, 9, 18) - parameter READ_WIDTH_A2 = 18, // Read data width on port A, RAM 2 (1, 2, 4, 9, 18) - parameter READ_WIDTH_B2 = 18 // Read data width on port B, RAM 2 (1, 2, 4, 9, 18) -) ( - input WEN_A1, // Write-enable port A, RAM 1 - input WEN_B1, // Write-enable port B, RAM 1 - input REN_A1, // Read-enable port A, RAM 1 - input REN_B1, // Read-enable port B, RAM 1 - input CLK_A1, // Clock port A, RAM 1 - input CLK_B1, // Clock port B, RAM 1 - input [1:0] BE_A1, // Byte-write enable port A, RAM 1 - input [1:0] BE_B1, // Byte-write enable port B, RAM 1 - input [13:0] ADDR_A1, // Address port A, RAM 1 - input [13:0] ADDR_B1, // Address port B, RAM 1 - input [15:0] WDATA_A1, // Write data port A, RAM 1 - input [1:0] WPARITY_A1, // Write parity port A, RAM 1 - input [15:0] WDATA_B1, // Write data port B, RAM 1 - input [1:0] WPARITY_B1, // Write parity port B, RAM 1 - output reg [15:0] RDATA_A1 = {16{1'b0}}, // Read data port A, RAM 1 - output reg [1:0] RPARITY_A1 = {2{1'b0}}, // Read parity port A, RAM 1 - output reg [15:0] RDATA_B1 = {16{1'b0}}, // Read data port B, RAM 1 - output reg [1:0] RPARITY_B1 = {2{1'b0}}, // Read parity port B, RAM 1 - input WEN_A2, // Write-enable port A, RAM 2 - input WEN_B2, // Write-enable port B, RAM 2 - input REN_A2, // Read-enable port A, RAM 2 - input REN_B2, // Read-enable port B, RAM 2 - input CLK_A2, // Clock port A, RAM 2 - input CLK_B2, // Clock port B, RAM 2 - input [1:0] BE_A2, // Byte-write enable port A, RAM 2 - input [1:0] BE_B2, // Byte-write enable port B, RAM 2 - input [13:0] ADDR_A2, // Address port A, RAM 2 - input [13:0] ADDR_B2, // Address port B, RAM 2 - input [15:0] WDATA_A2, // Write data port A, RAM 2 - input [1:0] WPARITY_A2, // Write parity port A, RAM 2 - input [15:0] WDATA_B2, // Write data port B, RAM 2 - input [1:0] WPARITY_B2, // Write parity port B, RAM 2 - output reg [15:0] RDATA_A2 = {16{1'b0}}, // Read data port A, RAM 2 - output reg [1:0] RPARITY_A2 = {2{1'b0}}, // Read parity port A, RAM 2 - output reg [15:0] RDATA_B2 = {16{1'b0}}, // Read data port B, RAM 2 - output reg [1:0] RPARITY_B2 = {2{1'b0}} // Read parity port B, RAM 2 -); - - - //RAM1 - localparam A1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A1); - localparam A1_WRITE_ADDR_WIDTH = calc_depth(A1_DATA_WRITE_WIDTH); - localparam A1_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_A1); - localparam A1_READ_ADDR_WIDTH = calc_depth(A1_DATA_READ_WIDTH); - localparam A1_DATA_WIDTH = (A1_DATA_WRITE_WIDTH > A1_DATA_READ_WIDTH) ? A1_DATA_WRITE_WIDTH : A1_DATA_READ_WIDTH; - - localparam A1_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_A1); - localparam A1_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_A1); - localparam A1_PARITY_WIDTH = (A1_PARITY_WRITE_WIDTH > A1_PARITY_READ_WIDTH) ? A1_PARITY_WRITE_WIDTH : A1_PARITY_READ_WIDTH; - - localparam B1_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_B1); - localparam B1_WRITE_ADDR_WIDTH = calc_depth(B1_DATA_WRITE_WIDTH); - localparam B1_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_B1); - localparam B1_READ_ADDR_WIDTH = calc_depth(B1_DATA_READ_WIDTH); - localparam B1_DATA_WIDTH = (B1_DATA_WRITE_WIDTH > B1_DATA_READ_WIDTH) ? B1_DATA_WRITE_WIDTH : B1_DATA_READ_WIDTH; - - localparam B1_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_B1); - localparam B1_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_B1); - localparam B1_PARITY_WIDTH = (B1_PARITY_WRITE_WIDTH > B1_PARITY_READ_WIDTH) ? B1_PARITY_WRITE_WIDTH : B1_PARITY_READ_WIDTH; - - localparam RAM1_DATA_WIDTH = (A1_DATA_WIDTH > B1_DATA_WIDTH) ? A1_DATA_WIDTH : B1_DATA_WIDTH; - localparam RAM1_PARITY_WIDTH = (A1_PARITY_WIDTH > B1_PARITY_WIDTH) ? A1_PARITY_WIDTH : B1_PARITY_WIDTH; - localparam RAM1_ADDR_WIDTH = calc_depth(RAM1_DATA_WIDTH); - - integer f, g, h, i, j, k, m; - - reg collision_window = 1; - reg collision_a_write_flag = 0; - reg collision_b_write_flag = 0; - reg collision_a_read_flag = 0; - reg collision_b_read_flag = 0; - reg [RAM1_ADDR_WIDTH-1:0] collision_a_address = {RAM1_ADDR_WIDTH{1'b0}}; - reg [RAM1_ADDR_WIDTH-1:0] collision_b_address = {RAM1_ADDR_WIDTH{1'b0}}; - - wire [RAM1_ADDR_WIDTH-1:0] a1_addr = ADDR_A1[13:14-RAM1_ADDR_WIDTH]; - wire [RAM1_ADDR_WIDTH-1:0] b1_addr = ADDR_B1[13:14-RAM1_ADDR_WIDTH]; - - reg [RAM1_DATA_WIDTH-1:0] RAM1_DATA [2**RAM1_ADDR_WIDTH-1:0]; - - /* verilator lint_off LITENDIAN */ - reg [RAM1_PARITY_WIDTH-1:0] temp_WPARITY_A1; - reg [RAM1_PARITY_WIDTH-1:0] temp_WPARITY_B1; - /* verilator lint_on LITENDIAN */ - reg [RAM1_DATA_WIDTH-1:0] temp_WDATA_A1; - reg [RAM1_DATA_WIDTH-1:0] temp_WDATA_B1; - - generate - if (RAM1_PARITY_WIDTH > 0) begin: parity_RAM1 - reg [RAM1_PARITY_WIDTH-1:0] RAM1_PARITY [2**RAM1_ADDR_WIDTH-1:0]; - - integer f_p, g_p, h_p, i_p, j_p, k_p, m_p; - - // Initialize Parity RAM contents - initial begin - f_p = 0; - for (g_p = 0; g_p < 2**RAM1_ADDR_WIDTH; g_p = g_p + 1) - for (h_p = 0; h_p < RAM1_PARITY_WIDTH; h_p = h_p + 1) begin - `ifdef SIM_VERILATOR - RAM1_PARITY[g_p][h_p] = INIT1_PARITY[f_p]; - `else - RAM1_PARITY[g_p][h_p] <= INIT1_PARITY[f_p]; - `endif - f_p = f_p + 1; - end - end - - always @(posedge CLK_A1) - if (WEN_A1) begin - for (i_p = find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH; i_p < find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH+A1_PARITY_WRITE_WIDTH; i_p = i_p + 1) begin - if (A1_PARITY_WRITE_WIDTH > 1) begin - if (BE_A1[i_p/1] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_PARITY[a1_addr][i_p] = WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_PARITY[a1_addr][i_p] <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_PARITY[a1_addr][i_p] = WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_PARITY[a1_addr][i_p] <= WPARITY_A1[i_p-(find_a1_write_index(ADDR_A1)*A1_PARITY_WRITE_WIDTH)]; - //$display("i_p: %0h, [i_p/1] %0h", i_p, i_p/2,$time); - `endif - end - end - end - - always @(posedge CLK_A1) - if (REN_A1) begin - for (j_p = find_a1_read_index(ADDR_A1)*A1_PARITY_READ_WIDTH; j_p < find_a1_read_index(ADDR_A1)*A1_PARITY_READ_WIDTH+A1_PARITY_READ_WIDTH; j_p = j_p + 1) begin - `ifdef SIM_VERILATOR - RPARITY_A1[j_p-(find_a1_read_index(ADDR_A1)*A1_PARITY_READ_WIDTH)] = RAM1_PARITY[a1_addr][j_p]; - `else - RPARITY_A1[j_p-(find_a1_read_index(ADDR_A1)*A1_PARITY_READ_WIDTH)] <= RAM1_PARITY[a1_addr][j_p]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_A1 <= 2'bx; - // verilator lint_on BLKANDNBLK - `endif - - always @(posedge CLK_B1) - if (WEN_B1) begin - for (k_p = find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH; k_p < find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH+B1_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin - if (B1_PARITY_WRITE_WIDTH > 1) begin - if (BE_B1[k_p/1] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_PARITY[b1_addr][k_p] = WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_PARITY[b1_addr][k_p] <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_PARITY[b1_addr][k_p] = WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_PARITY[b1_addr][k_p] <= WPARITY_B1[k_p-(find_b1_write_index(ADDR_B1)*B1_PARITY_WRITE_WIDTH)]; - `endif - end - end - end - - always @(posedge CLK_B1) - if (REN_B1) begin - for (m_p = find_b1_read_index(ADDR_B1)*B1_PARITY_READ_WIDTH; m_p < find_b1_read_index(ADDR_B1)*B1_PARITY_READ_WIDTH+B1_PARITY_READ_WIDTH; m_p = m_p + 1) begin - `ifdef SIM_VERILATOR - RPARITY_B1[m_p-(find_b1_read_index(ADDR_B1)*B1_PARITY_READ_WIDTH)] = RAM1_PARITY[b1_addr][m_p]; - `else - RPARITY_B1[m_p-(find_b1_read_index(ADDR_B1)*B1_PARITY_READ_WIDTH)] <= RAM1_PARITY[b1_addr][m_p]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_B1 <= 2'bx; - // verilator lint_on BLKANDNBLK - `endif - end - endgenerate - - // Initialize Base RAM contents - initial begin - f = 0; - for (g = 0; g < 2**RAM1_ADDR_WIDTH; g = g + 1) - for (h = 0; h < RAM1_DATA_WIDTH; h = h + 1) begin - `ifdef SIM_VERILATOR - RAM1_DATA[g][h] = INIT1[f]; - `else - RAM1_DATA[g][h] <= INIT1[f]; - `endif - f = f + 1; - end - end - - // Base RAM read/write functionality - always @(posedge CLK_A1) - if (WEN_A1) begin - //$display("AADR_A: %b index: %d", ADDR_A1, find_a1_write_index(ADDR_A1)*8); - for (i = find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH; i < find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH+A1_DATA_WRITE_WIDTH; i = i + 1) begin - if (A1_DATA_WRITE_WIDTH > 9) begin - if (BE_A1[i/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_DATA[a1_addr][i] = WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_DATA[a1_addr][i] <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_DATA[a1_addr][i] = WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_DATA[a1_addr][i] <= WDATA_A1[i-(find_a1_write_index(ADDR_A1)*A1_DATA_WRITE_WIDTH)]; - `endif - end - end - collision_a_address = a1_addr; - collision_a_write_flag = 1; - #collision_window; - collision_a_write_flag = 0; - end - - always @(posedge CLK_A1) - if (REN_A1) begin - for (j = find_a1_read_index(ADDR_A1)*A1_DATA_READ_WIDTH; j < find_a1_read_index(ADDR_A1)*A1_DATA_READ_WIDTH+A1_DATA_READ_WIDTH; j = j + 1) begin - `ifdef SIM_VERILATOR - RDATA_A1[j-(find_a1_read_index(ADDR_A1)*A1_DATA_READ_WIDTH)] = RAM1_DATA[a1_addr][j]; - `else - RDATA_A1[j-(find_a1_read_index(ADDR_A1)*A1_DATA_READ_WIDTH)] <= RAM1_DATA[a1_addr][j]; - `endif - end - collision_a_address = a1_addr; - collision_a_read_flag = 1; - #collision_window; - collision_a_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_A1 <= 16'bx; - // verilator lint_on BLKANDNBLK - `endif - - always @(posedge CLK_B1) - if (WEN_B1) begin - for (k = find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH; k < find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH+B1_DATA_WRITE_WIDTH; k = k + 1) begin - if (B1_DATA_WRITE_WIDTH > 9) begin - if (BE_B1[k/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_DATA[b1_addr][k] = WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_DATA[b1_addr][k] <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM1_DATA[b1_addr][k] = WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM1_DATA[b1_addr][k] <= WDATA_B1[k-(find_b1_write_index(ADDR_B1)*B1_DATA_WRITE_WIDTH)]; - `endif - end - - end - collision_b_address = b1_addr; - collision_b_write_flag = 1; - #collision_window; - collision_b_write_flag = 0; - end - - always @(posedge CLK_B1) - if (REN_B1) begin - //$display("index: %d b1_addr: %h ADDR_B1: %h", find_b1_read_index(ADDR_B1), b1_addr, ADDR_B1); - for (m = find_b1_read_index(ADDR_B1)*B1_DATA_READ_WIDTH; m < find_b1_read_index(ADDR_B1)*B1_DATA_READ_WIDTH+B1_DATA_READ_WIDTH; m = m + 1) begin - `ifdef SIM_VERILATOR - RDATA_B1[m-(find_b1_read_index(ADDR_B1)*B1_DATA_READ_WIDTH)] = RAM1_DATA[b1_addr][m]; - `else - RDATA_B1[m-(find_b1_read_index(ADDR_B1)*B1_DATA_READ_WIDTH)] <= RAM1_DATA[b1_addr][m]; - `endif - end - collision_b_address = b1_addr; - collision_b_read_flag = 1; - #collision_window; - collision_b_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_B1 <= 16'bx; - // verilator lint_on BLKANDNBLK - `endif - - // Collision checking - always @(posedge collision_a_write_flag) begin - if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Write collision occured on TDP_RAM18K instance %m at time %t where port A1 is writing to the same address, %h, as port B1.\n The write data may not be valid.", $realtime, collision_a_address); - collision_a_write_flag = 0; - end - if (collision_b_read_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port A1 is writing to the same address, %h, as port B1 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_a_write_flag = 0; - end - end - - always @(posedge collision_a_read_flag) begin - if (collision_b_write_flag && (collision_a_address == collision_b_address)) - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port B1 is writing to the same address, %h, as port A1 is reading.\n The write data is valid but the read data is not.", $realtime, collision_a_address); - collision_a_read_flag = 0; - end - - always @(posedge collision_b_write_flag) begin - if (collision_a_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Write collision occured on TDP_RAM18K instance %m at time %t where port B1 is writing to the same address, %h, as port A1.\n The write data may not be valid.", $realtime, collision_b_address); - collision_b_write_flag = 0; - end - if (collision_a_read_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port B1 is writing to the same address, %h, as port A1 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_b_write_flag = 0; - end - end - - always @(posedge collision_b_read_flag) begin - if (collision_a_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port A1 is writing to the same address, %h, as port B1 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_b_read_flag = 0; - end - end - - //RAM2 - localparam A2_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A2); - localparam A2_WRITE_ADDR_WIDTH = calc_depth(A2_DATA_WRITE_WIDTH); - localparam A2_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_A2); - localparam A2_READ_ADDR_WIDTH = calc_depth(A2_DATA_READ_WIDTH); - localparam A2_DATA_WIDTH = (A2_DATA_WRITE_WIDTH > A2_DATA_READ_WIDTH) ? A2_DATA_WRITE_WIDTH : A2_DATA_READ_WIDTH; - - localparam A2_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_A2); - localparam A2_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_A2); - localparam A2_PARITY_WIDTH = (A2_PARITY_WRITE_WIDTH > A2_PARITY_READ_WIDTH) ? A2_PARITY_WRITE_WIDTH : A2_PARITY_READ_WIDTH; - - localparam B2_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_B2); - localparam B2_WRITE_ADDR_WIDTH = calc_depth(B2_DATA_WRITE_WIDTH); - localparam B2_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_B2); - localparam B2_READ_ADDR_WIDTH = calc_depth(B2_DATA_READ_WIDTH); - localparam B2_DATA_WIDTH = (B2_DATA_WRITE_WIDTH > B2_DATA_READ_WIDTH) ? B2_DATA_WRITE_WIDTH : B2_DATA_READ_WIDTH; - - localparam B2_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_B2); - localparam B2_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_B2); - localparam B2_PARITY_WIDTH = (B2_PARITY_WRITE_WIDTH > B2_PARITY_READ_WIDTH) ? B2_PARITY_WRITE_WIDTH : B2_PARITY_READ_WIDTH; - - localparam RAM2_DATA_WIDTH = (A2_DATA_WIDTH > B2_DATA_WIDTH) ? A2_DATA_WIDTH : B2_DATA_WIDTH; - localparam RAM2_PARITY_WIDTH = (A2_PARITY_WIDTH > B2_PARITY_WIDTH) ? A2_PARITY_WIDTH : B2_PARITY_WIDTH; - localparam RAM2_ADDR_WIDTH = calc_depth(RAM2_DATA_WIDTH); - - integer a, b, c, l, n, p, r; - - reg collision_a2_write_flag = 0; - reg collision_b2_write_flag = 0; - reg collision_a2_read_flag = 0; - reg collision_b2_read_flag = 0; - reg [RAM2_ADDR_WIDTH-1:0] collision_a2_address = {RAM2_ADDR_WIDTH{1'b0}}; - reg [RAM2_ADDR_WIDTH-1:0] collision_b2_address = {RAM2_ADDR_WIDTH{1'b0}}; - - wire [RAM2_ADDR_WIDTH-1:0] a2_addr = ADDR_A2[13:14-RAM2_ADDR_WIDTH]; - wire [RAM2_ADDR_WIDTH-1:0] b2_addr = ADDR_B2[13:14-RAM2_ADDR_WIDTH]; - - reg [RAM2_DATA_WIDTH-1:0] RAM2_DATA [2**RAM2_ADDR_WIDTH-1:0]; - - /* verilator lint_off LITENDIAN */ - reg [RAM2_PARITY_WIDTH-1:0] temp_WPARITY_A2; - reg [RAM2_PARITY_WIDTH-1:0] temp_WPARITY_B2; - /* verilator lint_on LITENDIAN */ - reg [RAM2_DATA_WIDTH-1:0] temp_WDATA_A2; - reg [RAM2_DATA_WIDTH-1:0] temp_WDATA_B2; - - generate - if (RAM2_PARITY_WIDTH > 0) begin: parity_RAM2 - reg [RAM2_PARITY_WIDTH-1:0] RAM2_PARITY [2**RAM2_ADDR_WIDTH-1:0]; - - integer f_p2, g_p2, h_p2, i_p2, j_p2, k_p2, m_p2; - - // Initialize Parity RAM contents - initial begin - f_p2 = 0; - for (g_p2 = 0; g_p2 < 2**RAM2_ADDR_WIDTH; g_p2 = g_p2 + 1) - for (h_p2 = 0; h_p2 < RAM2_PARITY_WIDTH; h_p2 = h_p2 + 1) begin - `ifdef SIM_VERILATOR - RAM2_PARITY[g_p2][h_p2] = INIT2_PARITY[f_p2]; - `else - RAM2_PARITY[g_p2][h_p2] <= INIT2_PARITY[f_p2]; - `endif - f_p2 = f_p2 + 1; - end - end - - always @(posedge CLK_A2) - if (WEN_A2) begin - for (i_p2 = find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH; i_p2 < find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH+A2_PARITY_WRITE_WIDTH; i_p2 = i_p2 + 1) begin - if (A2_PARITY_WRITE_WIDTH > 1) begin - if (BE_A2[i_p2/1] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_PARITY[a2_addr][i_p2] = WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_PARITY[a2_addr][i_p2] <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_PARITY[a2_addr][i_p2] = WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_PARITY[a2_addr][i_p2] <= WPARITY_A2[i_p2-(find_a2_write_index(ADDR_A2)*A2_PARITY_WRITE_WIDTH)]; - //$display("i_p2: %0h, [i_p2/1] %0h", i_p2, i_p2/2,$time); - `endif - end - end - end - - always @(posedge CLK_A2) - if (REN_A2) begin - for (j_p2 = find_a2_read_index(ADDR_A2)*A2_PARITY_READ_WIDTH; j_p2 < find_a2_read_index(ADDR_A2)*A2_PARITY_READ_WIDTH+A2_PARITY_READ_WIDTH; j_p2 = j_p2 + 1) begin - `ifdef SIM_VERILATOR - RPARITY_A2[j_p2-(find_a2_read_index(ADDR_A2)*A2_PARITY_READ_WIDTH)] = RAM2_PARITY[a2_addr][j_p2]; - `else - RPARITY_A2[j_p2-(find_a2_read_index(ADDR_A2)*A2_PARITY_READ_WIDTH)] <= RAM2_PARITY[a2_addr][j_p2]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_A2 <= 2'bx; - // verilator lint_on BLKANDNBLK - `endif - - always @(posedge CLK_B2) - if (WEN_B2) begin - for (k_p2 = find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH; k_p2 < find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH+B2_PARITY_WRITE_WIDTH; k_p2 = k_p2 + 1) begin - if (B2_PARITY_WRITE_WIDTH > 1) begin - if (BE_B2[k_p2/1] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_PARITY[b2_addr][k_p2] = WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_PARITY[b2_addr][k_p2] <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_PARITY[b2_addr][k_p2] = WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_PARITY[b2_addr][k_p2] <= WPARITY_B2[k_p2-(find_b2_write_index(ADDR_B2)*B2_PARITY_WRITE_WIDTH)]; - `endif - end - end - end - - always @(posedge CLK_B2) - if (REN_B2) begin - for (m_p2 = find_b2_read_index(ADDR_B2)*B2_PARITY_READ_WIDTH; m_p2 < find_b2_read_index(ADDR_B2)*B2_PARITY_READ_WIDTH+B2_PARITY_READ_WIDTH; m_p2 = m_p2 + 1) begin - `ifdef SIM_VERILATOR - RPARITY_B2[m_p2-(find_b2_read_index(ADDR_B2)*B2_PARITY_READ_WIDTH)] = RAM2_PARITY[b2_addr][m_p2]; - `else - RPARITY_B2[m_p2-(find_b2_read_index(ADDR_B2)*B2_PARITY_READ_WIDTH)] <= RAM2_PARITY[b2_addr][m_p2]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_B2 <= 2'bx; - // verilator lint_on BLKANDNBLK - `endif - end - endgenerate - - // Initialize Base RAM contents - initial begin - a = 0; - for (b = 0; b < 2**RAM2_ADDR_WIDTH; b = b + 1) - for (c = 0; c < RAM2_DATA_WIDTH; c = c + 1) begin - `ifdef SIM_VERILATOR - RAM2_DATA[b][c] = INIT2[a]; - `else - RAM2_DATA[b][c] <= INIT2[a]; - `endif - a = a + 1; - end - end - - // Base RAM read/write functionality - always @(posedge CLK_A2) - if (WEN_A2) begin - //$display("AADR_A: %b index: %d", ADDR_A2, find_a2_write_index(ADDR_A2)*8); - for (l = find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH; l < find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH+A2_DATA_WRITE_WIDTH; l = l + 1) begin - if (A2_DATA_WRITE_WIDTH > 9) begin - if (BE_A2[l/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_DATA[a2_addr][l] = WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_DATA[a2_addr][l] <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_DATA[a2_addr][l] = WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_DATA[a2_addr][l] <= WDATA_A2[l-(find_a2_write_index(ADDR_A2)*A2_DATA_WRITE_WIDTH)]; - `endif - end - end - collision_a2_address = a2_addr; - collision_a2_write_flag = 1; - #collision_window; - collision_a2_write_flag = 0; - end - - always @(posedge CLK_A2) - if (REN_A2) begin - for (l = find_a2_read_index(ADDR_A2)*A2_DATA_READ_WIDTH; l < find_a2_read_index(ADDR_A2)*A2_DATA_READ_WIDTH+A2_DATA_READ_WIDTH; l = l + 1) begin - `ifdef SIM_VERILATOR - RDATA_A2[l-(find_a2_read_index(ADDR_A2)*A2_DATA_READ_WIDTH)] = RAM2_DATA[a2_addr][l]; - `else - RDATA_A2[l-(find_a2_read_index(ADDR_A2)*A2_DATA_READ_WIDTH)] <= RAM2_DATA[a2_addr][l]; - `endif - end - collision_a2_address = a2_addr; - collision_a2_read_flag = 1; - #collision_window; - collision_a2_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_A2 <= 16'bx; - // verilator lint_on BLKANDNBLK - `endif - - always @(posedge CLK_B2) - if (WEN_B2) begin - for (p = find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH; p < find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH+B2_DATA_WRITE_WIDTH; p = p + 1) begin - if (B2_DATA_WRITE_WIDTH > 9) begin - if (BE_B2[p/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_DATA[b2_addr][p] = WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM2_DATA[b2_addr][p] = WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM2_DATA[b2_addr][p] <= WDATA_B2[p-(find_b2_write_index(ADDR_B2)*B2_DATA_WRITE_WIDTH)]; - `endif - end - - end - collision_b2_address = b2_addr; - collision_b2_write_flag = 1; - #collision_window; - collision_b2_write_flag = 0; - end - - always @(posedge CLK_B2) - if (REN_B2) begin - //$display("index: %d b2_addr: %h ADDR_B2: %h", find_b2_read_index(ADDR_B2), b2_addr, ADDR_B2); - for (r = find_b2_read_index(ADDR_B2)*B2_DATA_READ_WIDTH; r < find_b2_read_index(ADDR_B2)*B2_DATA_READ_WIDTH+B2_DATA_READ_WIDTH; r = r + 1) begin - `ifdef SIM_VERILATOR - RDATA_B2[r-(find_b2_read_index(ADDR_B2)*B2_DATA_READ_WIDTH)] = RAM2_DATA[b2_addr][r]; - `else - RDATA_B2[r-(find_b2_read_index(ADDR_B2)*B2_DATA_READ_WIDTH)] <= RAM2_DATA[b2_addr][r]; - `endif - end - collision_b2_address = b2_addr; - collision_b2_read_flag = 1; - #collision_window; - collision_b2_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_B2 <= 16'bx; - // verilator lint_on BLKANDNBLK - `endif - - // Collision checking - always @(posedge collision_a2_write_flag) begin - if (collision_b2_write_flag && (collision_a2_address == collision_b2_address)) begin - $display("ERROR: Write collision occured on TDP_RAM18K instance %m at time %t where port A2 is writing to the same address, %h, as port B2.\n The write data may not be valid.", $realtime, collision_a2_address); - collision_a2_write_flag = 0; - end - if (collision_b2_read_flag && (collision_a2_address == collision_b2_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port A2 is writing to the same address, %h, as port B2 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b2_address); - collision_a2_write_flag = 0; - end - end - - always @(posedge collision_a2_read_flag) begin - if (collision_b2_write_flag && (collision_a2_address == collision_b2_address)) - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port B2 is writing to the same address, %h, as port A2 is reading.\n The write data is valid but the read data is not.", $realtime, collision_a2_address); - collision_a2_read_flag = 0; - end - - always @(posedge collision_b2_write_flag) begin - if (collision_a2_write_flag && (collision_a2_address == collision_b2_address)) begin - $display("ERROR: Write collision occured on TDP_RAM18K instance %m at time %t where port B2 is writing to the same address, %h, as port A2.\n The write data may not be valid.", $realtime, collision_b2_address); - collision_b2_write_flag = 0; - end - if (collision_a2_read_flag && (collision_a2_address == collision_b2_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port B2 is writing to the same address, %h, as port A2 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b2_address); - collision_b2_write_flag = 0; - end - end - - always @(posedge collision_b2_read_flag) begin - if (collision_a2_write_flag && (collision_a2_address == collision_b2_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM18K instance %m at time %t where port A2 is writing to the same address, %h, as port B2 is reading.\n The write data is valid but the read data is not.", $realtime, collision_b2_address); - collision_b2_read_flag = 0; - end - end - - function integer find_a1_write_index; - input [13:0] addr; - - if (RAM1_ADDR_WIDTH == A1_WRITE_ADDR_WIDTH) - find_a1_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a1_write_index = ADDR_A1[13-RAM1_ADDR_WIDTH:14-A1_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_a1_read_index; - input [13:0] addr; - - if (RAM1_ADDR_WIDTH == A1_READ_ADDR_WIDTH) - find_a1_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a1_read_index = ADDR_A1[13-RAM1_ADDR_WIDTH:14-A1_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b1_write_index; - input [13:0] addr; - - if (RAM1_ADDR_WIDTH == B1_WRITE_ADDR_WIDTH) - find_b1_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b1_write_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b1_read_index; - input [13:0] addr; - - if (RAM1_ADDR_WIDTH == B1_READ_ADDR_WIDTH) - find_b1_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b1_read_index = ADDR_B1[13-RAM1_ADDR_WIDTH:14-B1_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_a2_write_index; - input [13:0] addr; - - if (RAM2_ADDR_WIDTH == A2_WRITE_ADDR_WIDTH) - find_a2_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a2_write_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_a2_read_index; - input [13:0] addr; - - if (RAM2_ADDR_WIDTH == A2_READ_ADDR_WIDTH) - find_a2_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a2_read_index = ADDR_A2[13-RAM2_ADDR_WIDTH:14-A2_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b2_write_index; - input [13:0] addr; - - if (RAM2_ADDR_WIDTH == B2_WRITE_ADDR_WIDTH) - find_b2_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b2_write_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b2_read_index; - input [13:0] addr; - - if (RAM2_ADDR_WIDTH == B2_READ_ADDR_WIDTH) - find_b2_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b2_read_index = ADDR_B2[13-RAM2_ADDR_WIDTH:14-B2_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer calc_data_width; - input integer width; - if (width==9) - calc_data_width = 8; - else if (width==18) - calc_data_width = 16; - else - calc_data_width = width; - endfunction - - function integer calc_parity_width; - input integer width; - if (width==9) - calc_parity_width = 1; - else if (width==18) - calc_parity_width = 2; - else - calc_parity_width = 0; - endfunction - - function integer calc_depth; - input integer width; - if (width<=1) - calc_depth = 14; - else if (width<=2) - calc_depth = 13; - else if (width<=4) - calc_depth = 12; - else if (width<=9) - calc_depth = 11; - else if (width<=18) - calc_depth = 10; - else - calc_depth = 0; - endfunction - - initial - $timeformat(-9,0," ns", 5); initial begin - case(WRITE_WIDTH_A1) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter WRITE_WIDTH_A1 set to %d. Valid values are 1, 2, 4, 9, 18\n", WRITE_WIDTH_A1); - end - endcase - case(WRITE_WIDTH_B1) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter WRITE_WIDTH_B1 set to %d. Valid values are 1, 2, 4, 9, 18\n", WRITE_WIDTH_B1); - end - endcase - case(READ_WIDTH_A1) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter READ_WIDTH_A1 set to %d. Valid values are 1, 2, 4, 9, 18\n", READ_WIDTH_A1); - end - endcase - case(READ_WIDTH_B1) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter READ_WIDTH_B1 set to %d. Valid values are 1, 2, 4, 9, 18\n", READ_WIDTH_B1); - end - endcase - case(WRITE_WIDTH_A2) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter WRITE_WIDTH_A2 set to %d. Valid values are 1, 2, 4, 9, 18\n", WRITE_WIDTH_A2); - end - endcase - case(WRITE_WIDTH_B2) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter WRITE_WIDTH_B2 set to %d. Valid values are 1, 2, 4, 9, 18\n", WRITE_WIDTH_B2); - end - endcase - case(READ_WIDTH_A2) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter READ_WIDTH_A2 set to %d. Valid values are 1, 2, 4, 9, 18\n", READ_WIDTH_A2); - end - endcase - case(READ_WIDTH_B2) - 1 , - 2 , - 4 , - 9 , - 18: begin end - default: begin - $fatal(1,"\nError: TDP_RAM18KX2 instance %m has parameter READ_WIDTH_B2 set to %d. Valid values are 1, 2, 4, 9, 18\n", READ_WIDTH_B2); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/verilog/TDP_RAM36K.v b/models_customer/verilog/TDP_RAM36K.v deleted file mode 100644 index 12bda78..0000000 --- a/models_customer/verilog/TDP_RAM36K.v +++ /dev/null @@ -1,531 +0,0 @@ -`timescale 1ns/1ps -`celldefine -// -// TDP_RAM36K simulation model -// 36Kb True-dual-port RAM -// -// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved. -// - -module TDP_RAM36K #( - /* verilator lint_off WIDTHCONCAT */ - parameter [32767:0] INIT = {32768{1'b0}}, // Initial Contents of memory - /* verilator lint_on WIDTHCONCAT */ - parameter [4095:0] INIT_PARITY = {4096{1'b0}}, // Initial Contents of memory - parameter WRITE_WIDTH_A = 36, // Write data width on port A (1, 2, 4, 9, 18, 36) - parameter READ_WIDTH_A = WRITE_WIDTH_A, // Read data width on port A (1, 2, 4, 9, 18, 36) - parameter WRITE_WIDTH_B = WRITE_WIDTH_A, // Write data width on port B (1, 2, 4, 9, 18, 36) - parameter READ_WIDTH_B = READ_WIDTH_A // Read data width on port B (1, 2, 4, 9, 18, 36) -) ( - input WEN_A, // Write-enable port A - input WEN_B, // Write-enable port B - input REN_A, // Read-enable port A - input REN_B, // Read-enable port B - input CLK_A, // Clock port A - input CLK_B, // Clock port B - input [3:0] BE_A, // Byte-write enable port A - input [3:0] BE_B, // Byte-write enable port B - input [14:0] ADDR_A, // Address port A, align MSBs and connect unused MSBs to logic 0 - input [14:0] ADDR_B, // Address port B, align MSBs and connect unused MSBs to logic 0 - input [31:0] WDATA_A, // Write data port A - input [3:0] WPARITY_A, // Write parity data port A - input [31:0] WDATA_B, // Write data port B - input [3:0] WPARITY_B, // Write parity port B - output reg [31:0] RDATA_A = {32{1'b0}}, // Read data port A - output reg [3:0] RPARITY_A = 4'h0, // Read parity port A - output reg [31:0] RDATA_B = {32{1'b0}}, // Read data port B - output reg [3:0] RPARITY_B = 4'h0 // Read parity port B -); - - localparam A_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_A); - localparam A_WRITE_ADDR_WIDTH = calc_depth(A_DATA_WRITE_WIDTH); - localparam A_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_A); - localparam A_READ_ADDR_WIDTH = calc_depth(A_DATA_READ_WIDTH); - localparam A_DATA_WIDTH = (A_DATA_WRITE_WIDTH > A_DATA_READ_WIDTH) ? A_DATA_WRITE_WIDTH : A_DATA_READ_WIDTH; - - localparam A_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_A); - localparam A_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_A); - localparam A_PARITY_WIDTH = (A_PARITY_WRITE_WIDTH > A_PARITY_READ_WIDTH) ? A_PARITY_WRITE_WIDTH : A_PARITY_READ_WIDTH; - - localparam B_DATA_WRITE_WIDTH = calc_data_width(WRITE_WIDTH_B); - localparam B_WRITE_ADDR_WIDTH = calc_depth(B_DATA_WRITE_WIDTH); - localparam B_DATA_READ_WIDTH = calc_data_width(READ_WIDTH_B); - localparam B_READ_ADDR_WIDTH = calc_depth(B_DATA_READ_WIDTH); - localparam B_DATA_WIDTH = (B_DATA_WRITE_WIDTH > B_DATA_READ_WIDTH) ? B_DATA_WRITE_WIDTH : B_DATA_READ_WIDTH; - - localparam B_PARITY_WRITE_WIDTH = calc_parity_width(WRITE_WIDTH_B); - localparam B_PARITY_READ_WIDTH = calc_parity_width(READ_WIDTH_B); - localparam B_PARITY_WIDTH = (B_PARITY_WRITE_WIDTH > B_PARITY_READ_WIDTH) ? B_PARITY_WRITE_WIDTH : B_PARITY_READ_WIDTH; - - localparam RAM_DATA_WIDTH = (A_DATA_WIDTH > B_DATA_WIDTH) ? A_DATA_WIDTH : B_DATA_WIDTH; - localparam RAM_PARITY_WIDTH = (A_PARITY_WIDTH > B_PARITY_WIDTH) ? A_PARITY_WIDTH : B_PARITY_WIDTH; - localparam RAM_ADDR_WIDTH = calc_depth(RAM_DATA_WIDTH); - - integer f, g, h, i, j, k, m; - - reg collision_window = 1; - reg collision_a_write_flag = 0; - reg collision_b_write_flag = 0; - reg collision_a_read_flag = 0; - reg collision_b_read_flag = 0; - reg [RAM_ADDR_WIDTH-1:0] collision_a_address = {RAM_ADDR_WIDTH{1'b0}}; - reg [RAM_ADDR_WIDTH-1:0] collision_b_address = {RAM_ADDR_WIDTH{1'b0}}; - - wire [RAM_ADDR_WIDTH-1:0] a_addr = ADDR_A[14:15-RAM_ADDR_WIDTH]; - wire [RAM_ADDR_WIDTH-1:0] b_addr = ADDR_B[14:15-RAM_ADDR_WIDTH]; - - reg [RAM_DATA_WIDTH-1:0] RAM_DATA [2**RAM_ADDR_WIDTH-1:0]; - - /* verilator lint_off LITENDIAN */ - reg [RAM_PARITY_WIDTH-1:0] temp_WPARITY_A; - reg [RAM_PARITY_WIDTH-1:0] temp_WPARITY_B; - /* verilator lint_on LITENDIAN */ - reg [RAM_DATA_WIDTH-1:0] temp_WDATA_A; - reg [RAM_DATA_WIDTH-1:0] temp_WDATA_B; - - generate - if (RAM_PARITY_WIDTH > 0) begin: parity - reg [RAM_PARITY_WIDTH-1:0] RAM_PARITY [2**RAM_ADDR_WIDTH-1:0]; - - integer f_p, g_p, h_p, i_p, j_p, k_p, m_p; - - // Initialize PARITY RAM Contents - initial begin - f_p = 0; - for (g_p = 0; g_p < 2**RAM_ADDR_WIDTH; g_p = g_p + 1) - for (h_p = 0; h_p < RAM_PARITY_WIDTH; h_p = h_p + 1) begin - `ifdef SIM_VERILATOR - RAM_PARITY[g_p][h_p] = INIT_PARITY[f_p]; - `else - RAM_PARITY[g_p][h_p] <= INIT_PARITY[f_p]; - `endif - f_p = f_p + 1; - end - end - - always @(posedge CLK_A) - if (WEN_A) begin - for (i_p = find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH; i_p < find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH+A_PARITY_WRITE_WIDTH; i_p = i_p + 1) begin - if (A_PARITY_WRITE_WIDTH > 1) begin - //if (BE_A[i_p/8] == 1'b1) - if (BE_A[i_p%5] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_PARITY[a_addr][i_p] = WPARITY_A[i_p-(find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_PARITY[a_addr][i_p] <= WPARITY_A[i_p-(find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_PARITY[a_addr][i_p] = WPARITY_A[i_p-(find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_PARITY[a_addr][i_p] <= WPARITY_A[i_p-(find_a_write_index(ADDR_A)*A_PARITY_WRITE_WIDTH)]; - `endif - end - end - end - - always @(posedge CLK_A) - if (REN_A) begin - for (j_p = find_a_read_index(ADDR_A)*A_PARITY_READ_WIDTH; j_p < find_a_read_index(ADDR_A)*A_PARITY_READ_WIDTH+A_PARITY_READ_WIDTH; j_p = j_p + 1) begin - `ifdef SIM_VERILATOR - RPARITY_A[j_p-(find_a_read_index(ADDR_A)*A_PARITY_READ_WIDTH)] = RAM_PARITY[a_addr][j_p]; - `else - RPARITY_A[j_p-(find_a_read_index(ADDR_A)*A_PARITY_READ_WIDTH)] <= RAM_PARITY[a_addr][j_p]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_A <= 4'bx; - // verilator lint_on BLKANDNBLK - `endif - - - always @(posedge CLK_B) - if (WEN_B) begin - for (k_p = find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH; k_p < find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH+B_PARITY_WRITE_WIDTH; k_p = k_p + 1) begin - if (B_PARITY_WRITE_WIDTH > 1) begin - //if (BE_B[k_p/8] == 1'b1) - if (BE_B[k_p%5] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_PARITY[b_addr][k_p] = WPARITY_B[k_p-(find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_PARITY[b_addr][k_p] <= WPARITY_B[k_p-(find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_PARITY[b_addr][k_p] = WPARITY_B[k_p-(find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_PARITY[b_addr][k_p] <= WPARITY_B[k_p-(find_b_write_index(ADDR_B)*B_PARITY_WRITE_WIDTH)]; - `endif - end - end - end - - always @(posedge CLK_B) - if (REN_B) begin - for (m_p = find_b_read_index(ADDR_B)*B_PARITY_READ_WIDTH; m_p < find_b_read_index(ADDR_B)*B_PARITY_READ_WIDTH+B_PARITY_READ_WIDTH; m_p = m_p + 1) begin - `ifdef SIM_VERILATOR - RPARITY_B[m_p-(find_b_read_index(ADDR_B)*B_PARITY_READ_WIDTH)] = RAM_PARITY[b_addr][m_p]; - `else - RPARITY_B[m_p-(find_b_read_index(ADDR_B)*B_PARITY_READ_WIDTH)] <= RAM_PARITY[b_addr][m_p]; - `endif - end - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RPARITY_B <= 4'bx; - // verilator lint_on BLKANDNBLK - `endif - end - endgenerate - - // Initialize RAM contents - initial begin - f = 0; - for (g = 0; g < 2**RAM_ADDR_WIDTH; g = g + 1) - for (h = 0; h < RAM_DATA_WIDTH; h = h + 1) begin - `ifdef SIM_VERILATOR - RAM_DATA[g][h] = INIT[f]; - `else - RAM_DATA[g][h] <= INIT[f]; - `endif - f = f + 1; - end - end - - // Base RAM read/write functionality - always @(posedge CLK_A) - if (WEN_A) begin - //$display("AADR_A: %b index: %d", ADDR_A, find_a_write_index(ADDR_A)*8); - for (i = find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH; i < find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH+A_DATA_WRITE_WIDTH; i = i + 1) - if (A_DATA_WRITE_WIDTH > 9) begin - if (BE_A[i/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_DATA[a_addr][i] = WDATA_A[i-(find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_DATA[a_addr][i] <= WDATA_A[i-(find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_DATA[a_addr][i] = WDATA_A[i-(find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_DATA[a_addr][i] <= WDATA_A[i-(find_a_write_index(ADDR_A)*A_DATA_WRITE_WIDTH)]; - `endif - end - collision_a_address = a_addr; - collision_a_write_flag = 1; - #collision_window; - collision_a_write_flag = 0; - end - - always @(posedge CLK_A) - if (REN_A) begin - for (j = find_a_read_index(ADDR_A)*A_DATA_READ_WIDTH; j < find_a_read_index(ADDR_A)*A_DATA_READ_WIDTH+A_DATA_READ_WIDTH; j = j + 1) begin - `ifdef SIM_VERILATOR - RDATA_A[j-(find_a_read_index(ADDR_A)*A_DATA_READ_WIDTH)] = RAM_DATA[a_addr][j]; - `else - RDATA_A[j-(find_a_read_index(ADDR_A)*A_DATA_READ_WIDTH)] <= RAM_DATA[a_addr][j]; - `endif - end - collision_a_address = a_addr; - collision_a_read_flag = 1; - #collision_window; - collision_a_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_A <= 32'bx; - // verilator lint_on BLKANDNBLK - `endif - - always @(posedge CLK_B) - if (WEN_B) begin - for (k = find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH; k < find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH+B_DATA_WRITE_WIDTH; k = k + 1) - if (B_DATA_WRITE_WIDTH > 9) begin - if (BE_B[k/8] == 1'b1) begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_DATA[b_addr][k] = WDATA_B[k-(find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_DATA[b_addr][k] <= WDATA_B[k-(find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH)]; - `endif - end - end - else begin - `ifdef SIM_VERILATOR - /* verilator lint_off WIDTH */ - RAM_DATA[b_addr][k] = WDATA_B[k-(find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH)]; - /* verilator lint_on WIDTH */ - `else - RAM_DATA[b_addr][k] <= WDATA_B[k-(find_b_write_index(ADDR_B)*B_DATA_WRITE_WIDTH)]; - `endif - end - collision_b_address = b_addr; - collision_b_write_flag = 1; - #collision_window; - collision_b_write_flag = 0; - end - - always @(posedge CLK_B) - if (REN_B) begin - //$display("index: %d b_addr: %h ADDR_B: %h", find_b_read_index(ADDR_B), b_addr, ADDR_B); - for (m = find_b_read_index(ADDR_B)*B_DATA_READ_WIDTH; m < find_b_read_index(ADDR_B)*B_DATA_READ_WIDTH+B_DATA_READ_WIDTH; m = m + 1) begin - `ifdef SIM_VERILATOR - RDATA_B[m-(find_b_read_index(ADDR_B)*B_DATA_READ_WIDTH)] = RAM_DATA[b_addr][m]; - `else - RDATA_B[m-(find_b_read_index(ADDR_B)*B_DATA_READ_WIDTH)] <= RAM_DATA[b_addr][m]; - `endif - end - collision_b_address = b_addr; - collision_b_read_flag = 1; - #collision_window; - collision_b_read_flag = 0; - end - else - `ifndef FIFO - // verilator lint_off BLKANDNBLK - RDATA_B <= 32'bx; - // verilator lint_on BLKANDNBLK - `endif - - -/* - always @(posedge CLK_B) - if (WEN_B) begin - //$display("AADR_B: %b index: %d", ADDR_B, find_b_write_index(ADDR_B)); - for (k = find_b_write_index(ADDR_B); k < find_b_write_index(ADDR_B)+WRITE_WIDTH_B; k = k + 1) - if (BE_B[k/9] == 1'b1) - RAM[b_addr][k] <= WDATA_B[k-find_b_write_index(ADDR_B)]; - collision_b_address = b_addr; - collision_b_write_flag = 1; - #collision_window; - collision_b_write_flag = 0; - end - - always @(posedge CLK_B) - if (REN_B) begin - for (m = find_b_read_index(ADDR_B); m < find_b_read_index(ADDR_B)+READ_WIDTH_B; m = m + 1) - RDATA_B[m-find_b_read_index(ADDR_B)] <= RAM[b_addr][m]; - collision_b_address = b_addr; - collision_b_read_flag = 1; - #collision_window; - collision_b_read_flag = 0; - end - */ - - // Collision checking - always @(posedge collision_a_write_flag) begin - if (collision_b_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Write collision occured on TDP_RAM36K instance %m at time %t where port A is writing to the same address, %h, as port B.\n The write data may not be valid.", $realtime, collision_a_address); - collision_a_write_flag = 0; - end - if (collision_b_read_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM36K instance %m at time %t where port A is writing to the same address, %h, as port B is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_a_write_flag = 0; - end - end - - always @(posedge collision_a_read_flag) begin - if (collision_b_write_flag && (collision_a_address == collision_b_address)) - $display("ERROR: Memory collision occured on TDP_RAM36K instance %m at time %t where port B is writing to the same address, %h, as port A is reading.\n The write data is valid but the read data is not.", $realtime, collision_a_address); - collision_a_read_flag = 0; - end - - always @(posedge collision_b_write_flag) begin - if (collision_a_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Write collision occured on TDP_RAM36K instance %m at time %t where port B is writing to the same address, %h, as port A.\n The write data may not be valid.", $realtime, collision_b_address); - collision_b_write_flag = 0; - end - if (collision_a_read_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM36K instance %m at time %t where port B is writing to the same address, %h, as port A is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_b_write_flag = 0; - end - end - - always @(posedge collision_b_read_flag) begin - if (collision_a_write_flag && (collision_a_address == collision_b_address)) begin - $display("ERROR: Memory collision occured on TDP_RAM36K instance %m at time %t where port A is writing to the same address, %h, as port B is reading.\n The write data is valid but the read data is not.", $realtime, collision_b_address); - collision_b_read_flag = 0; - end - end - - - - function integer find_a_write_index; - input [14:0] addr; - - if (RAM_ADDR_WIDTH == A_WRITE_ADDR_WIDTH) - find_a_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a_write_index = ADDR_A[14-RAM_ADDR_WIDTH:15-A_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_a_read_index; - input [14:0] addr; - - if (RAM_ADDR_WIDTH == A_READ_ADDR_WIDTH) - find_a_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_a_read_index = ADDR_A[14-RAM_ADDR_WIDTH:15-A_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b_write_index; - input [14:0] addr; - - if (RAM_ADDR_WIDTH == B_WRITE_ADDR_WIDTH) - find_b_write_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b_write_index = ADDR_B[14-RAM_ADDR_WIDTH:15-B_WRITE_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer find_b_read_index; - input [14:0] addr; - - if (RAM_ADDR_WIDTH == B_READ_ADDR_WIDTH) - find_b_read_index = 0; - else - /* verilator lint_off SELRANGE */ - /* verilator lint_off WIDTH */ - find_b_read_index = ADDR_B[14-RAM_ADDR_WIDTH:15-B_READ_ADDR_WIDTH]; - /* verilator lint_on SELRANGE */ - /* verilator lint_on WIDTH */ - - endfunction - - function integer calc_data_width; - input integer width; - if (width==9) - calc_data_width = 8; - else if (width==18) - calc_data_width = 16; - else if (width==27) - calc_data_width = 24; - else if (width==36) - calc_data_width = 32; - else - calc_data_width = width; - endfunction - - function integer calc_parity_width; - input integer width; - if (width==9) - calc_parity_width = 1; - else if (width==18) - calc_parity_width = 2; - else if (width==27) - calc_parity_width = 3; - else if (width==36) - calc_parity_width = 4; - else - calc_parity_width = 0; - endfunction - - function integer calc_depth; - input integer width; - if (width<=1) - calc_depth = 15; - else if (width<=2) - calc_depth = 14; - else if (width<=4) - calc_depth = 13; - else if (width<=9) - calc_depth = 12; - else if (width<=18) - calc_depth = 11; - else if (width<=36) - calc_depth = 10; - else - calc_depth = 0; - endfunction - - initial - $timeformat(-9,0," ns", 5); - - initial begin - case(WRITE_WIDTH_A) - 1 , - 2 , - 4 , - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: TDP_RAM36K instance %m has parameter WRITE_WIDTH_A set to %d. Valid values are 1, 2, 4, 9, 18, 36\n", WRITE_WIDTH_A); - end - endcase - case(READ_WIDTH_A) - 1 , - 2 , - 4 , - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: TDP_RAM36K instance %m has parameter READ_WIDTH_A set to %d. Valid values are 1, 2, 4, 9, 18, 36\n", READ_WIDTH_A); - end - endcase - case(WRITE_WIDTH_B) - 1 , - 2 , - 4 , - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: TDP_RAM36K instance %m has parameter WRITE_WIDTH_B set to %d. Valid values are 1, 2, 4, 9, 18, 36\n", WRITE_WIDTH_B); - end - endcase - case(READ_WIDTH_B) - 1 , - 2 , - 4 , - 9 , - 18 , - 36: begin end - default: begin - $fatal(1,"\nError: TDP_RAM36K instance %m has parameter READ_WIDTH_B set to %d. Valid values are 1, 2, 4, 9, 18, 36\n", READ_WIDTH_B); - end - endcase - - end - -endmodule -`endcelldefine diff --git a/models_customer/vhdl/README.txt b/models_customer/vhdl/README.txt deleted file mode 100644 index 7d79df4..0000000 --- a/models_customer/vhdl/README.txt +++ /dev/null @@ -1 +0,0 @@ -This directory holds VHDL models. diff --git a/models_internal/verilog/CARRY.v b/models_internal/verilog/CARRY.v index e9fba50..b441644 100644 --- a/models_internal/verilog/CARRY.v +++ b/models_internal/verilog/CARRY.v @@ -16,5 +16,18 @@ module CARRY ( ); assign {COUT, O} = {P ? CIN : G, P ^ CIN}; + + specify + + if (P == 1'b1) + (CIN => COUT) = (0, 0); + if (P == 1'b0) + (G => COUT) = (0, 0); + + ( P, CIN *> O ) = (0, 0); + + endspecify + + endmodule `endcelldefine diff --git a/models_internal/verilog/CLK_BUF.v b/models_internal/verilog/CLK_BUF.v index ace2a8b..435214c 100644 --- a/models_internal/verilog/CLK_BUF.v +++ b/models_internal/verilog/CLK_BUF.v @@ -14,5 +14,10 @@ module CLK_BUF ( assign O = I ; + specify + (I => O) = (0, 0); + endspecify + + endmodule `endcelldefine diff --git a/models_internal/verilog/DFFNRE.v b/models_internal/verilog/DFFNRE.v index 30c8828..6a8d36e 100644 --- a/models_internal/verilog/DFFNRE.v +++ b/models_internal/verilog/DFFNRE.v @@ -22,5 +22,57 @@ module DFFNRE ( else if (E) Q <= D; + wire C_D_SDFCHK; + wire C_nD_SDFCHK; + wire nC_D_SDFCHK; + wire nC_nD_SDFCHK; + wire R_D_SDFCHK; + wire R_nD_SDFCHK; + wire R_SDFCHK; + wire D_SDFCHK; + + assign C_D_SDFCHK = C & D; + assign C_nD_SDFCHK = C & !D; + assign nC_D_SDFCHK = !C & D; + assign nC_nD_SDFCHK = !C & !D; + assign R_D_SDFCHK = R & D; + assign R_nD_SDFCHK = R & !D; + assign R_SDFCHK = R; + assign D_SDFCHK = D; + + + specify + if (C == 1'b1 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + (negedge C => (Q+:D)) = (0, 0); + + $width (negedge R &&& C_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier); + + $setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier); + $setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier); + $recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier); + $hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier); + endspecify endmodule `endcelldefine diff --git a/models_internal/verilog/DFFRE.v b/models_internal/verilog/DFFRE.v index 33964db..aaa1c40 100644 --- a/models_internal/verilog/DFFRE.v +++ b/models_internal/verilog/DFFRE.v @@ -22,5 +22,58 @@ module DFFRE ( else if (E) Q <= D; + wire C_D_SDFCHK; + wire C_nD_SDFCHK; + wire nC_D_SDFCHK; + wire nC_nD_SDFCHK; + wire R_D_SDFCHK; + wire R_nD_SDFCHK; + wire R_SDFCHK; + wire D_SDFCHK; + + assign C_D_SDFCHK = C & D; + assign C_nD_SDFCHK = C & !D; + assign nC_D_SDFCHK = !C & D; + assign nC_nD_SDFCHK = !C & !D; + assign R_D_SDFCHK = R & D; + assign R_nD_SDFCHK = R & !D; + assign R_SDFCHK = R; + assign D_SDFCHK = D; + + + specify + if (C == 1'b0 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + (posedge C => (Q+:D)) = (0, 0); + + $width (negedge R &&& C_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier); + + $setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier); + $setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier); + $recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier); + $hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier); + $hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier); + endspecify endmodule `endcelldefine diff --git a/models_internal/verilog/DSP38.v b/models_internal/verilog/DSP38.v index f1c3300..ee19b60 100644 --- a/models_internal/verilog/DSP38.v +++ b/models_internal/verilog/DSP38.v @@ -193,8 +193,8 @@ module DSP38 #( add_sub_in = (unsigned_a_int)? a_int< O) = (0, 0); + endspecify + + endmodule `endcelldefine diff --git a/models_internal/verilog/I_BUF.v b/models_internal/verilog/I_BUF.v index f5825f5..d2532ea 100644 --- a/models_internal/verilog/I_BUF.v +++ b/models_internal/verilog/I_BUF.v @@ -9,9 +9,7 @@ module I_BUF #( parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT" // IO Standard -`endif // RAPIDSILICON_INTERNAL +, parameter IOSTANDARD = "DEFAULT" // IO Standard ) ( input I, // Data input (connect to top-level port) input EN, // Enable the input @@ -27,7 +25,10 @@ module I_BUF #( assign O = EN ? I : 1'b0; - + specify + if (EN == 1'b1) + (I => O) = (0, 0); + endspecify initial begin case(WEAK_KEEPER) "NONE" , @@ -38,8 +39,6 @@ module I_BUF #( end endcase -`ifdef RAPIDSILICON_INTERNAL - case(IOSTANDARD) "DEFAULT" , "LVCMOS_12" , @@ -71,7 +70,6 @@ module I_BUF #( $fatal(1,"\nError: I_BUF instance %m has parameter IOSTANDARD set to %s. Valid values are DEFAULT, LVCMOS_12, LVCMOS_15, LVCMOS_18_HP, LVCMOS_18_HR, LVCMOS_25, LVCMOS_33, LVTTL, HSTL_I_12, HSTL_II_12, HSTL_I_15, HSTL_II_15, HSUL_12, PCI66, PCIX133, POD_12, SSTL_I_15, SSTL_II_15, SSTL_I_18_HP, SSTL_II_18_HP, SSTL_I_18_HR, SSTL_II_18_HR, SSTL_I_25, SSTL_II_25, SSTL_I_33, SSTL_II_33\n", IOSTANDARD); end endcase -`endif // RAPIDSILICON_INTERNAL end diff --git a/models_internal/verilog/I_BUF_DS.v b/models_internal/verilog/I_BUF_DS.v index 8041c7c..d3a37ea 100644 --- a/models_internal/verilog/I_BUF_DS.v +++ b/models_internal/verilog/I_BUF_DS.v @@ -37,8 +37,12 @@ module I_BUF_DS #( endcase end + specify + if (EN == 1'b1) + ( I_P, I_N *> O ) = (0, 0); + endspecify - initial begin + initial begin case(WEAK_KEEPER) "NONE" , "PULLUP" , diff --git a/models_internal/verilog/O_BUF.v b/models_internal/verilog/O_BUF.v index c32ed9d..cc65f85 100644 --- a/models_internal/verilog/O_BUF.v +++ b/models_internal/verilog/O_BUF.v @@ -8,22 +8,21 @@ // module O_BUF -`ifdef RAPIDSILICON_INTERNAL - #( +#( parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards ) -`endif // RAPIDSILICON_INTERNAL ( input I, // Data input output O // Data output (connect to top-level port) ); assign O = I ; - initial begin -`ifdef RAPIDSILICON_INTERNAL + specify + (I => O) = (0, 0); + endspecify initial begin case(IOSTANDARD) "DEFAULT" , @@ -76,7 +75,6 @@ module O_BUF $fatal(1,"\nError: O_BUF instance %m has parameter SLEW_RATE set to %s. Valid values are SLOW, FAST\n", SLEW_RATE); end endcase -`endif // RAPIDSILICON_INTERNAL end diff --git a/models_internal/verilog/O_BUFT.v b/models_internal/verilog/O_BUFT.v index 99dab80..e5d9af1 100644 --- a/models_internal/verilog/O_BUFT.v +++ b/models_internal/verilog/O_BUFT.v @@ -9,11 +9,9 @@ module O_BUFT #( parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT", // IO Standard +, parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards -`endif // RAPIDSILICON_INTERNAL ) ( input I, // Data input input T, // Tri-state output @@ -40,8 +38,6 @@ module O_BUFT #( end endcase -`ifdef RAPIDSILICON_INTERNAL - case(IOSTANDARD) "DEFAULT" , "LVCMOS_12" , @@ -93,7 +89,6 @@ module O_BUFT #( $fatal(1,"\nError: O_BUFT instance %m has parameter SLEW_RATE set to %s. Valid values are SLOW, FAST\n", SLEW_RATE); end endcase -`endif // RAPIDSILICON_INTERNAL end diff --git a/models_internal/verilog/O_BUFT_DS.v b/models_internal/verilog/O_BUFT_DS.v index a447497..e6ff22f 100644 --- a/models_internal/verilog/O_BUFT_DS.v +++ b/models_internal/verilog/O_BUFT_DS.v @@ -9,10 +9,8 @@ module O_BUFT_DS #( parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT", // IO Standard +, parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination -`endif // RAPIDSILICON_INTERNAL ) ( input I, // Data input input T, // Tri-state output @@ -43,8 +41,6 @@ module O_BUFT_DS #( end endcase -`ifdef RAPIDSILICON_INTERNAL - case(IOSTANDARD) "DEFAULT" , "BLVDS_DIFF" , @@ -74,7 +70,6 @@ module O_BUFT_DS #( $fatal(1,"\nError: O_BUFT_DS instance %m has parameter DIFFERENTIAL_TERMINATION set to %s. Valid values are TRUE, FALSE\n", DIFFERENTIAL_TERMINATION); end endcase -`endif // RAPIDSILICON_INTERNAL end diff --git a/models_internal/verilog/O_BUF_DS.v b/models_internal/verilog/O_BUF_DS.v index 378b73e..a3de260 100644 --- a/models_internal/verilog/O_BUF_DS.v +++ b/models_internal/verilog/O_BUF_DS.v @@ -8,12 +8,10 @@ // module O_BUF_DS -`ifdef RAPIDSILICON_INTERNAL - #( +#( parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination ) -`endif // RAPIDSILICON_INTERNAL ( input I, // Data input output O_P, // Data positive output (connect to top-level port) @@ -23,9 +21,12 @@ module O_BUF_DS assign O_P = I; assign O_N = ~I; - initial begin + specify + (I => O_P) = (0, 0); + (I => O_N) = (0, 0); + endspecify -`ifdef RAPIDSILICON_INTERNAL + initial begin case(IOSTANDARD) "DEFAULT" , @@ -56,7 +57,6 @@ module O_BUF_DS $fatal(1,"\nError: O_BUF_DS instance %m has parameter DIFFERENTIAL_TERMINATION set to %s. Valid values are TRUE, FALSE\n", DIFFERENTIAL_TERMINATION); end endcase -`endif // RAPIDSILICON_INTERNAL end diff --git a/models_internal/verilog/inc/CARRY.inc.v b/models_internal/verilog/inc/CARRY.inc.v index be768b5..fdc6a38 100644 --- a/models_internal/verilog/inc/CARRY.inc.v +++ b/models_internal/verilog/inc/CARRY.inc.v @@ -1,2 +1,15 @@ - assign {COUT, O} = {P ? CIN : G, P ^ CIN}; \ No newline at end of file + assign {COUT, O} = {P ? CIN : G, P ^ CIN}; + + specify + + if (P == 1'b1) + (CIN => COUT) = (0, 0); + if (P == 1'b0) + (G => COUT) = (0, 0); + + ( P, CIN *> O ) = (0, 0); + + endspecify + + \ No newline at end of file diff --git a/models_internal/verilog/inc/CLK_BUF.inc.v b/models_internal/verilog/inc/CLK_BUF.inc.v index 354a4a5..b173e3d 100644 --- a/models_internal/verilog/inc/CLK_BUF.inc.v +++ b/models_internal/verilog/inc/CLK_BUF.inc.v @@ -1,2 +1,8 @@ assign O = I ; + + specify + (I => O) = (0, 0); + endspecify + + \ No newline at end of file diff --git a/models_internal/verilog/inc/DFFNRE.inc.v b/models_internal/verilog/inc/DFFNRE.inc.v index dbde327..2d32a3d 100644 --- a/models_internal/verilog/inc/DFFNRE.inc.v +++ b/models_internal/verilog/inc/DFFNRE.inc.v @@ -4,3 +4,56 @@ Q <= 1'b0; else if (E) Q <= D; + + wire C_D_SDFCHK; + wire C_nD_SDFCHK; + wire nC_D_SDFCHK; + wire nC_nD_SDFCHK; + wire R_D_SDFCHK; + wire R_nD_SDFCHK; + wire R_SDFCHK; + wire D_SDFCHK; + + assign C_D_SDFCHK = C & D; + assign C_nD_SDFCHK = C & !D; + assign nC_D_SDFCHK = !C & D; + assign nC_nD_SDFCHK = !C & !D; + assign R_D_SDFCHK = R & D; + assign R_nD_SDFCHK = R & !D; + assign R_SDFCHK = R; + assign D_SDFCHK = D; + + + specify + if (C == 1'b1 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + (negedge C => (Q+:D)) = (0, 0); + + $width (negedge R &&& C_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier); + + $setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier); + $setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier); + $recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier); + $hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier); + endspecify \ No newline at end of file diff --git a/models_internal/verilog/inc/DFFRE.inc.v b/models_internal/verilog/inc/DFFRE.inc.v index 0d7c124..5b5de72 100644 --- a/models_internal/verilog/inc/DFFRE.inc.v +++ b/models_internal/verilog/inc/DFFRE.inc.v @@ -4,3 +4,57 @@ Q <= 1'b0; else if (E) Q <= D; + + wire C_D_SDFCHK; + wire C_nD_SDFCHK; + wire nC_D_SDFCHK; + wire nC_nD_SDFCHK; + wire R_D_SDFCHK; + wire R_nD_SDFCHK; + wire R_SDFCHK; + wire D_SDFCHK; + + assign C_D_SDFCHK = C & D; + assign C_nD_SDFCHK = C & !D; + assign nC_D_SDFCHK = !C & D; + assign nC_nD_SDFCHK = !C & !D; + assign R_D_SDFCHK = R & D; + assign R_nD_SDFCHK = R & !D; + assign R_SDFCHK = R; + assign D_SDFCHK = D; + + + specify + if (C == 1'b0 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b0) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b0 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b1 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + if (C == 1'b1 && D == 1'b0 && E == 1'b1) + (negedge R => (Q+:1'b0)) = (0, 0); + (posedge C => (Q+:D)) = (0, 0); + + $width (negedge R &&& C_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier); + $width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_D_SDFCHK, 0, 0, notifier); + $width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier); + $width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier); + + $setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier); + $setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier); + $recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier); + $hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier); + $hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier); + endspecify \ No newline at end of file diff --git a/models_internal/verilog/inc/DSP38.inc.v b/models_internal/verilog/inc/DSP38.inc.v index 0f40b17..54b194e 100644 --- a/models_internal/verilog/inc/DSP38.inc.v +++ b/models_internal/verilog/inc/DSP38.inc.v @@ -159,8 +159,8 @@ add_sub_in = (unsigned_a_int)? a_int< O) = (0, 0); + endspecify + diff --git a/models_internal/verilog/inc/I_BUF.inc.v b/models_internal/verilog/inc/I_BUF.inc.v index 9f5edd9..bf504ae 100644 --- a/models_internal/verilog/inc/I_BUF.inc.v +++ b/models_internal/verilog/inc/I_BUF.inc.v @@ -8,4 +8,7 @@ assign O = EN ? I : 1'b0; - + specify + if (EN == 1'b1) + (I => O) = (0, 0); + endspecify diff --git a/models_internal/verilog/inc/I_BUF_DS.inc.v b/models_internal/verilog/inc/I_BUF_DS.inc.v index e63ac77..9878689 100644 --- a/models_internal/verilog/inc/I_BUF_DS.inc.v +++ b/models_internal/verilog/inc/I_BUF_DS.inc.v @@ -18,4 +18,9 @@ endcase end + specify + if (EN == 1'b1) + ( I_P, I_N *> O ) = (0, 0); + endspecify + \ No newline at end of file diff --git a/models_internal/verilog/inc/O_BUF.inc.v b/models_internal/verilog/inc/O_BUF.inc.v index 354a4a5..dcbf87f 100644 --- a/models_internal/verilog/inc/O_BUF.inc.v +++ b/models_internal/verilog/inc/O_BUF.inc.v @@ -1,2 +1,6 @@ assign O = I ; + + specify + (I => O) = (0, 0); + endspecify \ No newline at end of file diff --git a/models_internal/verilog/inc/O_BUF_DS.inc.v b/models_internal/verilog/inc/O_BUF_DS.inc.v index 905324a..ed9ee58 100644 --- a/models_internal/verilog/inc/O_BUF_DS.inc.v +++ b/models_internal/verilog/inc/O_BUF_DS.inc.v @@ -2,3 +2,9 @@ assign O_P = I; assign O_N = ~I; + specify + (I => O_P) = (0, 0); + (I => O_N) = (0, 0); + endspecify + + \ No newline at end of file diff --git a/models_internal/verilog_blackbox/cell_sim_blackbox.v b/models_internal/verilog_blackbox/cell_sim_blackbox.v index 869ddd9..5cc8f01 100644 --- a/models_internal/verilog_blackbox/cell_sim_blackbox.v +++ b/models_internal/verilog_blackbox/cell_sim_blackbox.v @@ -299,9 +299,7 @@ endmodule (* blackbox *) module I_BUF #( parameter WEAK_KEEPER = "NONE" // Specify Pull-up/Pull-down on input (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT" // IO Standard -`endif // RAPIDSILICON_INTERNAL +, parameter IOSTANDARD = "DEFAULT" // IO Standard ) ( (* iopad_external_pin *) input logic I, @@ -498,12 +496,10 @@ endmodule `celldefine (* blackbox *) module O_BUF_DS -`ifdef RAPIDSILICON_INTERNAL #( parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination ) -`endif // RAPIDSILICON_INTERNAL ( input logic I, (* iopad_external_pin *) @@ -523,10 +519,8 @@ endmodule (* blackbox *) module O_BUFT_DS #( parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT", // IO Standard +, parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DIFFERENTIAL_TERMINATION = "TRUE" // Enable differential termination -`endif // RAPIDSILICON_INTERNAL ) ( input logic I, input logic T, @@ -547,11 +541,9 @@ endmodule (* blackbox *) module O_BUFT #( parameter WEAK_KEEPER = "NONE" // Enable pull-up/pull-down on output (NONE/PULLUP/PULLDOWN) -`ifdef RAPIDSILICON_INTERNAL - , parameter IOSTANDARD = "DEFAULT", // IO Standard +, parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards -`endif // RAPIDSILICON_INTERNAL ) ( input logic I, input logic T, @@ -569,13 +561,11 @@ endmodule `celldefine (* blackbox *) module O_BUF -`ifdef RAPIDSILICON_INTERNAL #( parameter IOSTANDARD = "DEFAULT", // IO Standard parameter DRIVE_STRENGTH = 2, // Drive strength in mA for LVCMOS standards parameter SLEW_RATE = "SLOW" // Transition rate for LVCMOS standards ) -`endif // RAPIDSILICON_INTERNAL ( input logic I, (* iopad_external_pin *)