From a3590f1b9862de2cc9ac10f36da793a3a8a114cc Mon Sep 17 00:00:00 2001
From: muhammadhamza15 <muhammadhamza1507@gmail.com>
Date: Mon, 1 Jul 2024 19:05:44 +0500
Subject: [PATCH 1/4] fixing I/O_DDR (EDA-2976)

---
 models_customer/verilog/I_DDR.v         | 2 ++
 models_customer/verilog/O_DDR.v         | 2 ++
 models_internal/verilog/I_DDR.v         | 2 ++
 models_internal/verilog/O_DDR.v         | 2 ++
 models_internal/verilog/inc/I_DDR.inc.v | 2 ++
 models_internal/verilog/inc/O_DDR.inc.v | 2 ++
 6 files changed, 12 insertions(+)

diff --git a/models_customer/verilog/I_DDR.v b/models_customer/verilog/I_DDR.v
index 9179df8..12dbb4b 100644
--- a/models_customer/verilog/I_DDR.v
+++ b/models_customer/verilog/I_DDR.v
@@ -50,6 +50,8 @@ module I_DDR (
       Q[1]<=data_pos;
       Q[0]<=data_neg;
     end
+    else
+      Q<=Q;
     
   end
 
diff --git a/models_customer/verilog/O_DDR.v b/models_customer/verilog/O_DDR.v
index b9d2413..d7b6c8f 100644
--- a/models_customer/verilog/O_DDR.v
+++ b/models_customer/verilog/O_DDR.v
@@ -55,6 +55,8 @@ module O_DDR (
         Q <= Q0;
       else
         Q <= Q1;
+    else
+      Q <= Q;
   end
   
 endmodule
diff --git a/models_internal/verilog/I_DDR.v b/models_internal/verilog/I_DDR.v
index 9179df8..12dbb4b 100644
--- a/models_internal/verilog/I_DDR.v
+++ b/models_internal/verilog/I_DDR.v
@@ -50,6 +50,8 @@ module I_DDR (
       Q[1]<=data_pos;
       Q[0]<=data_neg;
     end
+    else
+      Q<=Q;
     
   end
 
diff --git a/models_internal/verilog/O_DDR.v b/models_internal/verilog/O_DDR.v
index b9d2413..d7b6c8f 100644
--- a/models_internal/verilog/O_DDR.v
+++ b/models_internal/verilog/O_DDR.v
@@ -55,6 +55,8 @@ module O_DDR (
         Q <= Q0;
       else
         Q <= Q1;
+    else
+      Q <= Q;
   end
   
 endmodule
diff --git a/models_internal/verilog/inc/I_DDR.inc.v b/models_internal/verilog/inc/I_DDR.inc.v
index bbf3d68..8178f41 100644
--- a/models_internal/verilog/inc/I_DDR.inc.v
+++ b/models_internal/verilog/inc/I_DDR.inc.v
@@ -34,5 +34,7 @@
       Q[1]<=data_pos;
       Q[0]<=data_neg;
     end
+    else
+      Q<=Q;
     
   end
diff --git a/models_internal/verilog/inc/O_DDR.inc.v b/models_internal/verilog/inc/O_DDR.inc.v
index 75444b4..fc4578c 100644
--- a/models_internal/verilog/inc/O_DDR.inc.v
+++ b/models_internal/verilog/inc/O_DDR.inc.v
@@ -39,5 +39,7 @@
         Q <= Q0;
       else
         Q <= Q1;
+    else
+      Q <= Q;
   end
   
\ No newline at end of file

From 5cb10dadf9f55b7896eb90c41b4ed34bb67f1bba Mon Sep 17 00:00:00 2001
From: muhammadhamza15 <muhammadhamza1507@gmail.com>
Date: Tue, 2 Jul 2024 15:06:36 +0500
Subject: [PATCH 2/4] adding warning

---
 models_customer/verilog/DSP38.v         | 27 ++++++++--
 models_internal/verilog/DSP38.v         | 27 ++++++++--
 models_internal/verilog/inc/DSP38.inc.v | 25 ++++++++-
 models_internal/verilog/tb/DSP38_tb.v   | 72 ++++++++++++-------------
 specs/DSP38.yaml                        |  1 -
 5 files changed, 107 insertions(+), 45 deletions(-)

diff --git a/models_customer/verilog/DSP38.v b/models_customer/verilog/DSP38.v
index f330343..71044b3 100644
--- a/models_customer/verilog/DSP38.v
+++ b/models_customer/verilog/DSP38.v
@@ -20,7 +20,7 @@ module DSP38 #(
   input [17:0] B, // 18-bit data input for multiplication
   input [5:0] ACC_FIR, // 6-bit left shift A input
   output [37:0] Z, // 38-bit data output
-  output reg [17:0] DLY_B = 18'h00000, // 18-bit B registered output
+  output reg [17:0] DLY_B, // 18-bit B registered output
   input CLK, // Clock
   input RESET, // Active high reset
   input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient
@@ -33,6 +33,7 @@ module DSP38 #(
   input UNSIGNED_B // Selects signed or unsigned data for B input
 );
 
+	 
 	// registers
 	reg subtract_reg = 1'b0;
 	reg [5:0] acc_fir_reg = 6'h00;
@@ -275,12 +276,18 @@ module DSP38 #(
 	begin
 		if(RESET)
 		begin
-			DLY_B <= 18'h00000;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= 18'h00000;
+			
 			z_out_reg <= 38'h00000000;
 		end
 		else 
 		begin
-			DLY_B <= B;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= B;
+			else
+				DLY_B <= 18'dx;
+			
 			z_out_reg <= z_out;	
 		end
 	end
@@ -292,6 +299,20 @@ module DSP38 #(
 		if (ACC_FIR > 43)
 			$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
 
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+    			    $stop ;
+				end
+			end
+		endcase
+		
+	end
+
  initial begin
     case(DSP_MODE)
       "MULTIPLY" ,
diff --git a/models_internal/verilog/DSP38.v b/models_internal/verilog/DSP38.v
index f330343..71044b3 100644
--- a/models_internal/verilog/DSP38.v
+++ b/models_internal/verilog/DSP38.v
@@ -20,7 +20,7 @@ module DSP38 #(
   input [17:0] B, // 18-bit data input for multiplication
   input [5:0] ACC_FIR, // 6-bit left shift A input
   output [37:0] Z, // 38-bit data output
-  output reg [17:0] DLY_B = 18'h00000, // 18-bit B registered output
+  output reg [17:0] DLY_B, // 18-bit B registered output
   input CLK, // Clock
   input RESET, // Active high reset
   input [2:0] FEEDBACK, // 3-bit feedback input selects coefficient
@@ -33,6 +33,7 @@ module DSP38 #(
   input UNSIGNED_B // Selects signed or unsigned data for B input
 );
 
+	 
 	// registers
 	reg subtract_reg = 1'b0;
 	reg [5:0] acc_fir_reg = 6'h00;
@@ -275,12 +276,18 @@ module DSP38 #(
 	begin
 		if(RESET)
 		begin
-			DLY_B <= 18'h00000;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= 18'h00000;
+			
 			z_out_reg <= 38'h00000000;
 		end
 		else 
 		begin
-			DLY_B <= B;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= B;
+			else
+				DLY_B <= 18'dx;
+			
 			z_out_reg <= z_out;	
 		end
 	end
@@ -292,6 +299,20 @@ module DSP38 #(
 		if (ACC_FIR > 43)
 			$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
 
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+    			    $stop ;
+				end
+			end
+		endcase
+		
+	end
+
  initial begin
     case(DSP_MODE)
       "MULTIPLY" ,
diff --git a/models_internal/verilog/inc/DSP38.inc.v b/models_internal/verilog/inc/DSP38.inc.v
index 1309716..4f3ffa5 100644
--- a/models_internal/verilog/inc/DSP38.inc.v
+++ b/models_internal/verilog/inc/DSP38.inc.v
@@ -1,4 +1,5 @@
 
+	 
 	// registers
 	reg subtract_reg = 1'b0;
 	reg [5:0] acc_fir_reg = 6'h00;
@@ -241,12 +242,18 @@
 	begin
 		if(RESET)
 		begin
-			DLY_B <= 18'h00000;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= 18'h00000;
+			
 			z_out_reg <= 38'h00000000;
 		end
 		else 
 		begin
-			DLY_B <= B;
+			if(DSP_MODE== "MULTIPLY_ADD_SUB")
+				DLY_B <= B;
+			else
+				DLY_B <= 18'dx;
+			
 			z_out_reg <= z_out;	
 		end
 	end
@@ -258,3 +265,17 @@
 		if (ACC_FIR > 43)
 			$display("WARNING: DSP38 instance %m ACC_FIR input is %d which is greater than 43 which serves no function", ACC_FIR);
 
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+    			    $stop ;
+				end
+			end
+		endcase
+		
+	end
+
diff --git a/models_internal/verilog/tb/DSP38_tb.v b/models_internal/verilog/tb/DSP38_tb.v
index 5ad8209..aef73b3 100644
--- a/models_internal/verilog/tb/DSP38_tb.v
+++ b/models_internal/verilog/tb/DSP38_tb.v
@@ -431,44 +431,44 @@ module DSP38_tb;
 				$display("ACC SUBTRACTION TEST FAILED \n Z = %0d",Z);
 
 			// FEEDBACK 3 -> ACC Mult x B
-			@(negedge CLK);
-			A=3;
-			B=1;
-			ACC_FIR=1;
-			FEEDBACK=3;
-			LOAD_ACC=1;
-			SATURATE=0;
-			SHIFT_RIGHT=0;
-			ROUND=0;
-			SUBTRACT=0;
-			UNSIGNED_A=1;
-			UNSIGNED_B=1;
-
-			if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
-				repeat(2)@(posedge CLK);
-			else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
-				@(posedge CLK);
+			// @(negedge CLK);
+			// A=3;
+			// B=1;
+			// ACC_FIR=1;
+			// FEEDBACK=3;
+			// LOAD_ACC=1;
+			// SATURATE=0;
+			// SHIFT_RIGHT=0;
+			// ROUND=0;
+			// SUBTRACT=0;
+			// UNSIGNED_A=1;
+			// UNSIGNED_B=1;
+
+			// if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
+			// 	repeat(2)@(posedge CLK);
+			// else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
+			// 	@(posedge CLK);
 			
-			@(posedge CLK);
-			#1;
-			if(Z===6)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z = %0d",Z);
-
-			@(posedge CLK);
-			#1;
-			if(Z===12)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z = %0d",Z);
+			// @(posedge CLK);
+			// #1;
+			// if(Z===6)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z = %0d",Z);
+
+			// @(posedge CLK);
+			// #1;
+			// if(Z===12)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z = %0d",Z);
 				
-			@(posedge CLK);
-			#1;
-			if(Z===18)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z = %0d",Z);
+			// @(posedge CLK);
+			// #1;
+			// if(Z===18)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z = %0d",Z);
 
 			// UNSIGNED SATURATION OVERFLOW
 			@(negedge CLK);
diff --git a/specs/DSP38.yaml b/specs/DSP38.yaml
index a832ece..22160a0 100644
--- a/specs/DSP38.yaml
+++ b/specs/DSP38.yaml
@@ -64,7 +64,6 @@ ports:
      dir: output
      desc: 18-bit B registered output
      type: reg
-     default: 18'h00000
    CLK:
      dir: input
      desc: Clock

From 44f640e3ca8636ee9e2a2ecece371eda940512bc Mon Sep 17 00:00:00 2001
From: muhammadhamza15 <muhammadhamza1507@gmail.com>
Date: Tue, 2 Jul 2024 15:38:14 +0500
Subject: [PATCH 3/4] adding warnings to dsp 19x2

---
 models_customer/verilog/DSP19X2.v         | 18 +++++-
 models_internal/verilog/DSP19X2.v         | 18 +++++-
 models_internal/verilog/inc/DSP19X2.inc.v | 18 +++++-
 models_internal/verilog/tb/DSP19x2_tb.v   | 76 +++++++++++------------
 4 files changed, 86 insertions(+), 44 deletions(-)

diff --git a/models_customer/verilog/DSP19X2.v b/models_customer/verilog/DSP19X2.v
index d15b93e..8cdc933 100644
--- a/models_customer/verilog/DSP19X2.v
+++ b/models_customer/verilog/DSP19X2.v
@@ -373,8 +373,8 @@ module DSP19X2 #(
 
 	assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
 	assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
-	assign DLY_B1 = dly_b1;
-	assign DLY_B2 = dly_b2;
+	assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
+	assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
 
 
 	// If ACC_FIR is greater than 21, result is invalid
@@ -391,6 +391,20 @@ module DSP19X2 #(
 			$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
 			#1 $finish ;
 		end
+	
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+					$stop ;
+				end
+			end
+		endcase
+		
+	end
 
  initial begin
     case(DSP_MODE)
diff --git a/models_internal/verilog/DSP19X2.v b/models_internal/verilog/DSP19X2.v
index d15b93e..8cdc933 100644
--- a/models_internal/verilog/DSP19X2.v
+++ b/models_internal/verilog/DSP19X2.v
@@ -373,8 +373,8 @@ module DSP19X2 #(
 
 	assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
 	assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
-	assign DLY_B1 = dly_b1;
-	assign DLY_B2 = dly_b2;
+	assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
+	assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
 
 
 	// If ACC_FIR is greater than 21, result is invalid
@@ -391,6 +391,20 @@ module DSP19X2 #(
 			$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
 			#1 $finish ;
 		end
+	
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+					$stop ;
+				end
+			end
+		endcase
+		
+	end
 
  initial begin
     case(DSP_MODE)
diff --git a/models_internal/verilog/inc/DSP19X2.inc.v b/models_internal/verilog/inc/DSP19X2.inc.v
index 526373c..1cb518d 100644
--- a/models_internal/verilog/inc/DSP19X2.inc.v
+++ b/models_internal/verilog/inc/DSP19X2.inc.v
@@ -331,8 +331,8 @@
 
 	assign Z1 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[18:0]:z_out[18:0];
 	assign Z2 = (OUTPUT_REG_EN == "TRUE")?z_out_reg[37:19]:z_out[37:19];
-	assign DLY_B1 = dly_b1;
-	assign DLY_B2 = dly_b2;
+	assign DLY_B1 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b1:9'dx;
+	assign DLY_B2 = (DSP_MODE== "MULTIPLY_ADD_SUB")?dly_b2:9'dx;
 
 
 	// If ACC_FIR is greater than 21, result is invalid
@@ -349,4 +349,18 @@
 			$display("WARNING: DSP19x2 instance %m SHIFT_RIGHT input is %d which is greater than 31 which serves no function", SHIFT_RIGHT);
 			#1 $finish ;
 		end
+	
+	always@(*) 
+	begin
+		case(DSP_MODE)
+			"MULTIPLY_ACCUMULATE": begin  
+				if(FEEDBACK>1)
+				begin
+					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
+					$stop ;
+				end
+			end
+		endcase
+		
+	end
 
diff --git a/models_internal/verilog/tb/DSP19x2_tb.v b/models_internal/verilog/tb/DSP19x2_tb.v
index 8992461..142da23 100644
--- a/models_internal/verilog/tb/DSP19x2_tb.v
+++ b/models_internal/verilog/tb/DSP19x2_tb.v
@@ -456,46 +456,46 @@ module DSP19x2_tb;
 				$display("ACC SUBTRACTION TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
 
 			// FEEDBACK 3 -> ACC Mult x B
-			@(negedge CLK);
-			A1=3;
-			B1=1;
-			A2=3;
-			B2=1;
-			ACC_FIR=1;
-			FEEDBACK=3;
-			LOAD_ACC=1;
-			SATURATE=0;
-			SHIFT_RIGHT=0;
-			ROUND=0;
-			SUBTRACT=0;
-			UNSIGNED_A=1;
-			UNSIGNED_B=1;
-
-			if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
-				repeat(2)@(posedge CLK);
-			else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
-				@(posedge CLK);
+			// @(negedge CLK);
+			// A1=3;
+			// B1=1;
+			// A2=3;
+			// B2=1;
+			// ACC_FIR=1;
+			// FEEDBACK=3;
+			// LOAD_ACC=1;
+			// SATURATE=0;
+			// SHIFT_RIGHT=0;
+			// ROUND=0;
+			// SUBTRACT=0;
+			// UNSIGNED_A=1;
+			// UNSIGNED_B=1;
+
+			// if(INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "TRUE")
+			// 	repeat(2)@(posedge CLK);
+			// else if ((INPUT_REG_EN == "TRUE" && OUTPUT_REG_EN == "FALSE") || (INPUT_REG_EN == "FALSE" && OUTPUT_REG_EN == "TRUE"))
+			// 	@(posedge CLK);
 			
-			@(posedge CLK);
-			#1;
-			if(Z1===6 && Z2===6)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
-
-			@(posedge CLK);
-			#1;
-			if(Z1===12 && Z2===12)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
+			// @(posedge CLK);
+			// #1;
+			// if(Z1===6 && Z2===6)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
+
+			// @(posedge CLK);
+			// #1;
+			// if(Z1===12 && Z2===12)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
 				
-			@(posedge CLK);
-			#1;
-			if(Z1===18 && Z2===18)
-				$display("ACC MULT TEST PASSED");
-			else
-				$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
+			// @(posedge CLK);
+			// #1;
+			// if(Z1===18 && Z2===18)
+			// 	$display("ACC MULT TEST PASSED");
+			// else
+			// 	$display("ACC MULT TEST FAILED \n Z1 = %0d \t Z2= %0d",Z1,Z2);
 
 			// UNSIGNED SATURATION OVERFLOW
 			@(negedge CLK);

From aa8165101e6730ed72101efd1752a0b679b5f9a9 Mon Sep 17 00:00:00 2001
From: muhammadhamza15 <muhammadhamza1507@gmail.com>
Date: Thu, 4 Jul 2024 11:11:07 +0500
Subject: [PATCH 4/4] removing  from warning message

---
 models_customer/verilog/DSP19X2.v         | 5 +----
 models_customer/verilog/DSP38.v           | 5 +----
 models_internal/verilog/DSP19X2.v         | 5 +----
 models_internal/verilog/DSP38.v           | 5 +----
 models_internal/verilog/inc/DSP19X2.inc.v | 5 +----
 models_internal/verilog/inc/DSP38.inc.v   | 5 +----
 6 files changed, 6 insertions(+), 24 deletions(-)

diff --git a/models_customer/verilog/DSP19X2.v b/models_customer/verilog/DSP19X2.v
index 8cdc933..26018a3 100644
--- a/models_customer/verilog/DSP19X2.v
+++ b/models_customer/verilog/DSP19X2.v
@@ -397,10 +397,7 @@ module DSP19X2 #(
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-					$stop ;
-				end
+					$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 		
diff --git a/models_customer/verilog/DSP38.v b/models_customer/verilog/DSP38.v
index 71044b3..b6a65fc 100644
--- a/models_customer/verilog/DSP38.v
+++ b/models_customer/verilog/DSP38.v
@@ -304,10 +304,7 @@ module DSP38 #(
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-    			    $stop ;
-				end
+					$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 		
diff --git a/models_internal/verilog/DSP19X2.v b/models_internal/verilog/DSP19X2.v
index 8cdc933..26018a3 100644
--- a/models_internal/verilog/DSP19X2.v
+++ b/models_internal/verilog/DSP19X2.v
@@ -397,10 +397,7 @@ module DSP19X2 #(
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-					$stop ;
-				end
+					$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 		
diff --git a/models_internal/verilog/DSP38.v b/models_internal/verilog/DSP38.v
index 71044b3..b6a65fc 100644
--- a/models_internal/verilog/DSP38.v
+++ b/models_internal/verilog/DSP38.v
@@ -304,10 +304,7 @@ module DSP38 #(
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-    			    $stop ;
-				end
+					$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 		
diff --git a/models_internal/verilog/inc/DSP19X2.inc.v b/models_internal/verilog/inc/DSP19X2.inc.v
index 1cb518d..5cc069e 100644
--- a/models_internal/verilog/inc/DSP19X2.inc.v
+++ b/models_internal/verilog/inc/DSP19X2.inc.v
@@ -355,10 +355,7 @@
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-					$stop ;
-				end
+					$display("\nWARNING: DSP19x2 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase
 		
diff --git a/models_internal/verilog/inc/DSP38.inc.v b/models_internal/verilog/inc/DSP38.inc.v
index 4f3ffa5..30e9033 100644
--- a/models_internal/verilog/inc/DSP38.inc.v
+++ b/models_internal/verilog/inc/DSP38.inc.v
@@ -270,10 +270,7 @@
 		case(DSP_MODE)
 			"MULTIPLY_ACCUMULATE": begin  
 				if(FEEDBACK>1)
-				begin
-					$display("\nError: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
-    			    $stop ;
-				end
+					$display("\nWARNING: DSP38 instance %m has parameter DSP_MODE set to %s and FEEDBACK set to %0d. Valid values of FEEDBACK for this mode are 0,1 \n", DSP_MODE,FEEDBACK);
 			end
 		endcase