Releases: os-fpga/device_modeling
Releases · os-fpga/device_modeling
Simulation Models Updates
This release contains:
- I_DDR fixes
- O_DDR fixes
- TDP_RAM36k verilator support
TDPRAM Verilator fixes
Merge pull request #33 from anaszameer/ram18kx2_verilator Add Verilator Support for TDP_RAM18KX2
Device Modeling Updates
Merge pull request #32 from muhammadhamza15/mhamza_dev Reverting commit "resolved verilator simulator issues for BRAMTDP36K"
TDPRAM Verilator fixes
Merge pull request #29 from anaszameer/bram_verilator Resolved Verilator Simulator Issues for BRAM Model "TDP_RAM36K"
Device Modeling Updates
This release contains:
- Verilator support for TDP_RAM18KX2 Model
- New primitive FCLK_BUF
- Update in PLL primitive to infer CLK_BUF
p4def_to_simv script update
Merge pull request #24 from muhammadhamza15/main P4def_to_simv file update to support above & below comments
I_SERDES, I_DELAY, O_DELAY models fixes
- EDA-2808 fixes
- EDA-2740 fixes
Support Verilator for TDP_RAM36K Simulation Model
Merge pull request #22 from anaszameer/main Support Verilator for TDP_RAM36K Simulation Model
Update parameters definition for I_BUF_DS primitive
Merge pull request #21 from muhammadhamza15/main Update parameters definition for I_BUF_DS primitive
Modify BRAM models to mimic RTL behavior
Merge pull request #20 from anaszameer/fix_eda_2621 EDA-2621 Modify Model to mimic BRAM's RTL behavior i.e RDATA is X whe…