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Added explanation for fields and their defaults on FPGA input section #280

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wants to merge 15 commits into from
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Added explanation for fields and their defaults on FPGA input section #280

wants to merge 15 commits into from

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MustafaAbdaal
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Motivate of the pull request

  • To address an existing issue. If so, please provide a link to the issue:
  • Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

Which part of the code base require a change

  • Frontend:
  • Backend:
  • Library: <Specify the library name, e.g. npm packages>
  • Plug-in: <Specify the plugin name, e.g. Webpack, jtest>
  • Documentation
  • Regression tests
  • Continuous Integration (CI) scripts

Impact of the pull request

  • Require a change on Quality of Results (QoR)
  • Break backward-compatibility. If so, please list who may be influenced.

@MustafaAbdaal
modified conf.py file
96daba1
@MustafaAbdaal
Modified main index.rst & created User Guide index.rst
e2358e7 
To keep the user_guide table of contents easy to modify, I created a seperate user_guide folder with it's own index.rst, the file shows the sections covering basic RPE usage. As a starting point files for each section are located within the same user_guide folder, they will be moved to their own directories with respective index.rst files once subsections are finalized.
@MustafaAbdaal
Updated each section's .rst file with subsections
653b914 
Subsections were added to the following sections: Setting up .RPE Project, FPGA input, SoC input, Analyzing Results. For now subsections will not be needed on Peripheral Usage & Memory Usage sections.
@MustafaAbdaal
Merge branch 'main' into user-guide-ToC
8dfe5d8
@MustafaAbdaal
Merge branch 'main' into user-guide-ToC
1a3527b
@MustafaAbdaal
adding sections folders for images and code snippets
d04229a
@MustafaAbdaal
Adding screenshots to main figure folder
e1834fd
@MustafaAbdaal
edited SoC Input section to include peripherals, connectivity, memory…
9503ab4 
…. Rearranged subsections to align with RPE excel sheet's input order
@MustafaAbdaal
Completed initial draft content for setup section. figures will be fo…
bcefdf5 
…rmatted and content to be refined, but all info/steps have been covered
@MustafaAbdaal
Merge branch 'main' of github.com:os-fpga/rapid_power_estimator into …
c307a6e 
…user-guide-ToC
@MustafaAbdaal
Finished writing initial content for SoC input section on SoC_index.rst
7eb0f23
@MustafaAbdaal
Added screenshots and general instructions to fill out FPGA input, mo…
f35309c 
…re explicit instructions to follow in next commit
@MustafaAbdaal
Added initial instructions for BRAM, DSP & IO subsections of FPGA input
735b7b0
@MustafaAbdaal
Modified FPGA input content to explicity mention fields and their def…
5929f65 
…aults.
@MustafaAbdaal MustafaAbdaal added the documentation Improvements or additions to documentation label Nov 27, 2024
@shivaahir158
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image

@MustafaAbdaal this should have the updated logo of RPE application, I suggest you uninstall this version of RPE and fetch the latest executable of RPE

@MustafaAbdaal
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Will make new PR with some minor modifications made to FPGA input section.

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@ravikiranchollangi ravikiranchollangi Awaiting requested review from ravikiranchollangi

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@MustafaAbdaal @shivaahir158