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Added sim change files from 1.1.2
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@AYYAZmayo
AYYAZmayo committed Apr 3, 2024
1 parent 09658ea commit 07d9a6b
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion genesis3/FPGA_PRIMITIVES_MODELS
Submodule FPGA_PRIMITIVES_MODELS updated 12 files
+32 −20 sim_models/verilog/FIFO18KX2.v
+18 −10 sim_models/verilog/FIFO36K.v
+1 −1 sim_models/verilog/O_SERDES_CLK.v
+1 −1 sim_models/verilog/PLL.v
+96 −48 sim_models/verilog/TDP_RAM18KX2.v
+48 −20 sim_models/verilog/TDP_RAM36K.v
+32 −20 sim_models_internal/verilog/FIFO18KX2.v
+18 −10 sim_models_internal/verilog/FIFO36K.v
+1 −1 sim_models_internal/verilog/O_SERDES_CLK.v
+1 −1 sim_models_internal/verilog/PLL.v
+96 −48 sim_models_internal/verilog/TDP_RAM18KX2.v
+48 −20 sim_models_internal/verilog/TDP_RAM36K.v

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