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Merge pull request #315 from AYYAZmayo/main
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Port latest FPGA_PRIMITIVES_MODELS, rev 1.1.9
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@alaindargelas
alaindargelas authored Apr 25, 2024
2 parents 20b9f5b + 3dfd44b commit 2e6f155
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion genesis3/FPGA_PRIMITIVES_MODELS
Submodule FPGA_PRIMITIVES_MODELS updated 6 files
+33 −2 sim_models/verilog/I_BUF_DS.v
+20 −4 sim_models/verilog/TDP_RAM18KX2.v
+10 −2 sim_models/verilog/TDP_RAM36K.v
+2 −9 sim_models_internal/verilog/I_BUF_DS.v
+20 −4 sim_models_internal/verilog/TDP_RAM18KX2.v
+10 −2 sim_models_internal/verilog/TDP_RAM36K.v

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