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Merge pull request #287 from AYYAZmayo/main
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Submodule FPGA_PRIMITIVES_MODELS is updated
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@alaindargelas
alaindargelas authored Mar 18, 2024
2 parents f92072e + 306abda commit 7c548ec
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion genesis3/FPGA_PRIMITIVES_MODELS
Submodule FPGA_PRIMITIVES_MODELS updated 23 files
+0 −448 blackbox_models/cell_sim_blackbox.v
+1 −2 sim_models/verilog/LUT1.v
+2 −3 sim_models/verilog/LUT2.v
+3 −3 sim_models/verilog/LUT3.v
+5 −3 sim_models/verilog/LUT4.v
+5 −3 sim_models/verilog/LUT5.v
+6 −3 sim_models/verilog/LUT6.v
+24 −15 sim_models/verilog/PLL.v
+20 −15 sim_models_internal/primitives_mapping/BRAM/rs_tdp36k_post_pnr_mapping.v
+94 −177 sim_models_internal/primitives_mapping/FIFO/fifo18kx2_to_rs_tdp_36k_mapping.v
+72 −187 sim_models_internal/primitives_mapping/FIFO/fifo36k_to_rs_tdp_36k_mapping.v
+26 −11 sim_models_internal/primitives_mapping/FIFO/tb_test_design/tb_sync_fifo_R36W36.v
+46 −17 sim_models_internal/primitives_mapping/FIFO/tb_test_design/tb_sync_split_fifo_R18W18_R9W9.v
+0 −20 sim_models_internal/verilog/CARRY_CHAIN.v
+1 −3 sim_models_internal/verilog/LUT1.v
+2 −3 sim_models_internal/verilog/LUT2.v
+3 −3 sim_models_internal/verilog/LUT3.v
+5 −3 sim_models_internal/verilog/LUT4.v
+5 −3 sim_models_internal/verilog/LUT5.v
+6 −3 sim_models_internal/verilog/LUT6.v
+24 −15 sim_models_internal/verilog/PLL.v
+0 −65 specs_internal/CARRY_CHAIN.yaml
+0 −87 tb/CARRY_CHAIN/CARRY_CHAIN_tb.v

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