Merge pull request #298 from os-fpga/revert-296-revert-295-revert-293…

…-main Revert "Revert "Revert "EDA-2629: Remove dangling wires after CLK_BUF-MAP"""
os-fpga · Mar 28, 2024 · 8588b5e · 8588b5e
2 parents 2d1d328 + b6ca042
commit 8588b5e
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
@@ -4406,8 +4406,6 @@ static void show_sig(const RTLIL::SigSpec &sig)
                 run("read_verilog -sv -lib "+readIOArgs);
                 run("clkbufmap -buf rs__CLK_BUF O:I");
                 run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS
-                //EDA-2629: Remove dangling wires after CLK_BUF-MAP
-                run("opt_clean");
                 run("iopadmap -bits -inpad rs__I_BUF O:I -outpad rs__O_BUF I:O -toutpad rs__O_BUFT T:I:O -limit "+ std::to_string(max_device_ios));
                 run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS