From b6ca042399ccdf9fd1a464a8c24e4981d095ad9a Mon Sep 17 00:00:00 2001
From: alaindargelas <63669492+alaindargelas@users.noreply.github.com>
Date: Wed, 27 Mar 2024 17:17:39 -0700
Subject: [PATCH] Revert "Revert "Revert "EDA-2629: Remove dangling wires after
 CLK_BUF-MAP"""

---
 src/synth_rapidsilicon.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
index a35ddd4e..9575e5ab 100644
--- a/src/synth_rapidsilicon.cc
+++ b/src/synth_rapidsilicon.cc
@@ -4406,8 +4406,6 @@ static void show_sig(const RTLIL::SigSpec &sig)
                 run("read_verilog -sv -lib "+readIOArgs);
                 run("clkbufmap -buf rs__CLK_BUF O:I");
                 run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS
-                //EDA-2629: Remove dangling wires after CLK_BUF-MAP
-                run("opt_clean");
                 run("iopadmap -bits -inpad rs__I_BUF O:I -outpad rs__O_BUF I:O -toutpad rs__O_BUFT T:I:O -limit "+ std::to_string(max_device_ios));
                 run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS