From 72381593778bb5ab30202504ec48b3172c7dc46d Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Thu, 14 Mar 2024 09:36:56 -0700 Subject: [PATCH] Turn back on clock buf inference --- src/synth_rapidsilicon.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc index e614a9a5..c3a1d414 100644 --- a/src/synth_rapidsilicon.cc +++ b/src/synth_rapidsilicon.cc @@ -3251,6 +3251,7 @@ void Set_INIT_PlacementWithNoParity_mode(Cell* cell,RTLIL::Const mode) { if (!no_iobuf){ run("read_verilog -sv -lib "+readIOArgs); + run("clkbufmap -buf rs__CLK_BUF O:I"); run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS run("iopadmap -bits -inpad rs__I_BUF O:I -outpad rs__O_BUF I:O -toutpad rs__O_BUFT T:I:O -limit "+ std::to_string(max_device_ios)); run("techmap -map " GET_TECHMAP_FILE_PATH(GENESIS_3_DIR,IO_CELLs_final_map));// TECHMAP CELLS