From c9559f357508384a3eded90111c13bfaf3a1e8d7 Mon Sep 17 00:00:00 2001
From: awaisabbas006 <awaisabbas006@gmail.com>
Date: Mon, 29 Apr 2024 10:43:01 +0500
Subject: [PATCH] adding fix for EDA-2752

---
 src/synth_rapidsilicon.cc | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
index dfbd585d..66a31788 100644
--- a/src/synth_rapidsilicon.cc
+++ b/src/synth_rapidsilicon.cc
@@ -897,6 +897,19 @@ struct SynthRapidSiliconPass : public ScriptPass {
     // Performs Formal Verification between design in current memory (called "original") 
     // and "previous" design saved as "previous".
     //
+
+
+    void remove_print_cell(){
+        for(auto& modules : _design->selected_modules()){
+            for(auto& cell : modules->selected_cells()){
+                if (cell->type == RTLIL::escape_id("$print")){
+                    log("Deleting Cell = %s\n",log_id(cell->type));
+                    modules->remove(cell);
+                }
+            }
+        }
+    }
+
     void sec_check(string checkName, bool verify) {
         
         if (sec_mode == SECMode::OFF) {
@@ -950,6 +963,7 @@ struct SynthRapidSiliconPass : public ScriptPass {
         
         run("proc");
         run("opt_expr");
+
         run("opt_clean -purge");
 
         // Transform the network so that the blif dumped is easier to process for 'dsec'
@@ -4036,6 +4050,8 @@ static void show_sig(const RTLIL::SigSpec &sig)
               run("flatten");
             }
 
+            remove_print_cell();
+
             transform(nobram /* bmuxmap */); // no "$bmux" mapping in bram state
 
 #if 1