From d11932f02a63130e8fd1763d910fd44266bbf2df Mon Sep 17 00:00:00 2001 From: thierryBesson Date: Mon, 28 Oct 2024 19:16:38 +0500 Subject: [PATCH] fix for EDA-3307 --- src/synth_rapidsilicon.cc | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc index 6c0f513a..d4b8b9f8 100644 --- a/src/synth_rapidsilicon.cc +++ b/src/synth_rapidsilicon.cc @@ -5829,6 +5829,44 @@ static void show_sig(const RTLIL::SigSpec &sig) run("write_verilog -org-name -noattr -noexpr -nohex after_rewire_obuft.v"); } } + + // Force 'keep' attribute on original IO BUF cells instantiated at RTL. + // (ex: EDA-3307 where one I_BUF is removed by optimizer because input is not used) + // + void set_iobuf_keep_attribute() + { + for(auto& modules : _design->selected_modules()) { + + for(auto& cell : modules->selected_cells()) { + + if (cell->type == RTLIL::escape_id("I_BUF")) { + cell->set_bool_attribute(ID::keep); + continue; + } + if (cell->type == RTLIL::escape_id("I_BUF_DS")) { + cell->set_bool_attribute(ID::keep); + continue; + } + if (cell->type == RTLIL::escape_id("O_BUF")) { + cell->set_bool_attribute(ID::keep); + continue; + } + if (cell->type == RTLIL::escape_id("O_BUF_DS")) { + cell->set_bool_attribute(ID::keep); + continue; + } + if (cell->type == RTLIL::escape_id("O_BUFT")) { + cell->set_bool_attribute(ID::keep); + continue; + } + if (cell->type == RTLIL::escape_id("O_BUFT_DS")) { + cell->set_bool_attribute(ID::keep); + continue; + } + } + } + } + // Map the $TBUF cells into OBUFT equivalent. // void map_obuft(RTLIL::Module* top_module) @@ -8491,6 +8529,10 @@ void collect_clocks (RTLIL::Module* module, remove_print_cell(); illegal_clk_connection(); + // set keep attribute on original IO buf cells + // + set_iobuf_keep_attribute(); + transform(nobram /* bmuxmap */); // no "$bmux" mapping in bram state #if 1