diff --git a/.gitignore b/.gitignore index 9953f88f5..f69b8c537 100644 --- a/.gitignore +++ b/.gitignore @@ -16,4 +16,7 @@ gmon.out # Installation directories /.venv/ -/tools/ \ No newline at end of file +/tools/ + +# traces +sim.vcd \ No newline at end of file diff --git a/.vscode/lint.py b/.vscode/lint.py index 0ec4c4471..efdfc572c 100644 --- a/.vscode/lint.py +++ b/.vscode/lint.py @@ -11,7 +11,8 @@ '--error-limit', '9999', '-Wall', - '-Wno-MULTITOP' + '-Wno-MULTITOP', + '-Wno-MODDUP' ], stderr=subprocess.STDOUT) except subprocess.CalledProcessError as e: out = e.output.decode('ascii') diff --git a/.vscode/linter.vc b/.vscode/linter.vc index 5d9bdb1da..e03a4026d 100644 --- a/.vscode/linter.vc +++ b/.vscode/linter.vc @@ -153,8 +153,8 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include /workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/src/axi_pkg.sv /workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/src/axi_intf.sv /workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/src/axi_atop_filter.sv @@ -226,8 +226,8 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include /workspaces/stitch_cluster/.bender/git/checkouts/axi_riscv_atomics-baa633fa798ef2d4/src/axi_res_tbl.sv /workspaces/stitch_cluster/.bender/git/checkouts/axi_riscv_atomics-baa633fa798ef2d4/src/axi_riscv_amos_alu.sv /workspaces/stitch_cluster/.bender/git/checkouts/axi_riscv_atomics-baa633fa798ef2d4/src/axi_riscv_amos.sv @@ -275,10 +275,10 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/apb-856f26900b176af1/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include /workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/src/reg_intf.sv /workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv /workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv @@ -333,14 +333,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR ++incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include /workspaces/stitch_cluster/hw/future/src/mem_to_axi_lite.sv /workspaces/stitch_cluster/hw/future/src/idma_reg64_frontend_reg_pkg.sv /workspaces/stitch_cluster/hw/future/src/idma_tf_id_gen.sv @@ -357,14 +357,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include /workspaces/stitch_cluster/hw/reqrsp_interface/src/reqrsp_pkg.sv /workspaces/stitch_cluster/hw/reqrsp_interface/src/reqrsp_intf.sv /workspaces/stitch_cluster/hw/reqrsp_interface/src/axi_to_reqrsp.sv @@ -378,13 +378,13 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include +incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include /workspaces/stitch_cluster/hw/mem_interface/src/mem_wide_narrow_mux.sv /workspaces/stitch_cluster/hw/mem_interface/src/mem_interface.sv @@ -393,14 +393,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include /workspaces/stitch_cluster/hw/tcdm_interface/src/tcdm_interface.sv /workspaces/stitch_cluster/hw/tcdm_interface/src/axi_to_tcdm.sv /workspaces/stitch_cluster/hw/tcdm_interface/src/reqrsp_to_tcdm.sv @@ -410,14 +410,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include /workspaces/stitch_cluster/hw/snitch/src/snitch_pma_pkg.sv /workspaces/stitch_cluster/hw/snitch/src/riscv_instr.sv /workspaces/stitch_cluster/hw/snitch/src/snitch_pkg.sv @@ -430,14 +430,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include /workspaces/stitch_cluster/hw/snitch/src/snitch.sv +define+TARGET_RTL @@ -447,25 +447,25 @@ +incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include /workspaces/stitch_cluster/hw/snitch_vm/src/snitch_ptw.sv +define+TARGET_RTL +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR ++incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include /workspaces/stitch_cluster/hw/snitch_dma/src/axi_dma_pkg.sv /workspaces/stitch_cluster/hw/snitch_dma/src/axi_dma_error_handler.sv /workspaces/stitch_cluster/hw/snitch_dma/src/axi_dma_perf_counters.sv @@ -476,14 +476,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include /workspaces/stitch_cluster/hw/snitch_icache/src/snitch_icache_pkg.sv /workspaces/stitch_cluster/hw/snitch_icache/src/snitch_icache_l0.sv /workspaces/stitch_cluster/hw/snitch_icache/src/snitch_icache_refill.sv @@ -496,14 +496,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/hw/snitch/include -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include /workspaces/stitch_cluster/hw/snitch_ipu/src/snitch_ipu_pkg.sv /workspaces/stitch_cluster/hw/snitch_ipu/src/snitch_ipu_alu.sv /workspaces/stitch_cluster/hw/snitch_ipu/src/snitch_int_ss.sv @@ -512,14 +512,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include /workspaces/stitch_cluster/hw/snitch_ssr/src/snitch_ssr_pkg.sv /workspaces/stitch_cluster/hw/snitch_ssr/src/snitch_ssr_switch.sv /workspaces/stitch_cluster/hw/snitch_ssr/src/snitch_ssr_credit_counter.sv @@ -533,20 +533,23 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/hw/snitch/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_amo_shim.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_fpu.sv +/workspaces/stitch_cluster/hw/snitch_cluster/src/stream_reduce.sv +/workspaces/stitch_cluster/hw/snitch_cluster/src/stream_stall.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_tcdm_router.sv +/workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_vfpr.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_sb_ipool.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_sb.sv /workspaces/stitch_cluster/hw/snitch_cluster/src/snitch_sequencer.sv @@ -563,14 +566,14 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include ++incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include /workspaces/stitch_cluster/target/common/test/tb_memory_regbus.sv /workspaces/stitch_cluster/target/common/test/tb_memory_axi.sv @@ -578,26 +581,26 @@ +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include -+incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include +incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include /workspaces/stitch_cluster/target/snitch_cluster/generated/snitch_cluster_wrapper.sv +define+TARGET_RTL +define+TARGET_SNITCH_CLUSTER +define+TARGET_SYNTHESIS +define+TARGET_VERILATOR -+incdir+/workspaces/stitch_cluster/hw/mem_interface/include +incdir+/workspaces/stitch_cluster/hw/tcdm_interface/include -+incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/register_interface-60fff8e94b3912d9/include -+incdir+/workspaces/stitch_cluster/hw/snitch/include ++incdir+/workspaces/stitch_cluster/hw/mem_interface/include ++incdir+/workspaces/stitch_cluster/.bender/git/checkouts/axi-b118383cbcd3267b/include ++incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include +incdir+/workspaces/stitch_cluster/hw/reqrsp_interface/include ++incdir+/workspaces/stitch_cluster/hw/snitch/include +incdir+/workspaces/stitch_cluster/.bender/git/checkouts/common_cells-dd89ab0d1382ef18/include -+incdir+/workspaces/stitch_cluster/hw/snitch_ssr/include -/workspaces/stitch_cluster/target/snitch_cluster/test/testharness.sv \ No newline at end of file +/workspaces/stitch_cluster/target/snitch_cluster/test/testharness.sv diff --git a/Bender.yml b/Bender.yml index 9016df7be..b6143077d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -255,6 +255,9 @@ sources: - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv - hw/snitch_cluster/src/snitch_fpu.sv + - hw/snitch_cluster/src/stream_reduce.sv + - hw/snitch_cluster/src/stream_stall.sv + - hw/snitch_cluster/src/stream_merge.sv - hw/snitch_cluster/src/snitch_tcdm_router.sv - hw/snitch_cluster/src/snitch_vfpr.sv - hw/snitch_cluster/src/snitch_sb_ipool.sv diff --git a/hw/snitch/src/snitch_pkg.sv b/hw/snitch/src/snitch_pkg.sv index c4130f770..788b5c4c3 100644 --- a/hw/snitch/src/snitch_pkg.sv +++ b/hw/snitch/src/snitch_pkg.sv @@ -176,11 +176,12 @@ package snitch_pkg; // Trace Infrastructure // -------------------- // pragma translate_off - typedef enum logic [1:0] { + typedef enum logic [2:0] { SrcSnitch = 0, SrcFpu = 1, SrcFpuSeq = 2, - SrcFpuSB = 3 + SrcFpuSB = 3, + SrcFpuVFPR = 4 } trace_src_e; typedef struct packed { @@ -275,6 +276,10 @@ package snitch_pkg; longint op_0; longint op_1; longint op_2; + longint vfpr_in_valid; + longint vfpr_in_ready; + longint vfpr_out_valid; + longint vfpr_out_ready; longint use_fpu; longint fpu_in_rd; longint fpu_in_acc; @@ -314,6 +319,10 @@ package snitch_pkg; extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_0", fpu_trace.op_0); extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_1", fpu_trace.op_1); extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_2", fpu_trace.op_2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vfpr_in_valid", fpu_trace.vfpr_in_valid); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vfpr_in_ready", fpu_trace.vfpr_in_ready); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vfpr_out_valid", fpu_trace.vfpr_out_valid); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vfpr_out_ready", fpu_trace.vfpr_out_ready); extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "use_fpu", fpu_trace.use_fpu); extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_rd", fpu_trace.fpu_in_rd); extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_acc", fpu_trace.fpu_in_acc); @@ -383,4 +392,39 @@ package snitch_pkg; return extras_str; endfunction + typedef struct packed { + longint source; + longint read; + longint read_result; + longint reg0; + longint reg1; + longint reg2; + longint reg_enabled; + longint data0; + longint data1; + longint data2; + longint write; + longint wr_addr; + longint wr_data; + } fpu_vfpr_trace_port_t; + + function automatic string print_fpu_vfpr_trace(fpu_vfpr_trace_port_t fpu_vfpr); + string extras_str = "{"; + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "source", fpu_vfpr.source); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "read", fpu_vfpr.read); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "read_result", fpu_vfpr.read_result); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "reg0", fpu_vfpr.reg0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "reg1", fpu_vfpr.reg1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "reg2", fpu_vfpr.reg2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "reg_enabled", fpu_vfpr.reg_enabled); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "data0", fpu_vfpr.data0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "data1", fpu_vfpr.data1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "data2", fpu_vfpr.data2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "write", fpu_vfpr.write); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "wr_addr", fpu_vfpr.wr_addr); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "wr_data", fpu_vfpr.wr_data); + extras_str = $sformatf("%s}", extras_str); + return extras_str; + endfunction + endpackage diff --git a/hw/snitch_cluster/src/snitch_cc.sv b/hw/snitch_cluster/src/snitch_cc.sv index 0d8850af6..fd647b371 100644 --- a/hw/snitch_cluster/src/snitch_cc.sv +++ b/hw/snitch_cluster/src/snitch_cc.sv @@ -447,6 +447,7 @@ module snitch_cc #( snitch_pkg::fpu_trace_port_t fpu_trace; snitch_pkg::fpu_sequencer_trace_port_t fpu_sequencer_trace; snitch_pkg::fpu_sb_trace_port_t fpu_sb_trace; + snitch_pkg::fpu_vfpr_trace_port_t fpu_vfpr_trace; // pragma translate_on logic [2:0][4:0] ssr_raddr; @@ -508,6 +509,7 @@ module snitch_cc #( .trace_port_o ( fpu_trace ), .sequencer_tracer_port_o ( fpu_sequencer_trace ), .sb_tracer_port_o ( fpu_sb_trace ), + .vfpr_tracer_port_o ( fpu_vfpr_trace ), // pragma translate_on .hart_id_i ( hart_id_i ), .acc_req_i ( acc_snitch_req ), @@ -870,6 +872,7 @@ module snitch_cc #( automatic snitch_pkg::fpu_trace_port_t extras_fpu; automatic snitch_pkg::fpu_sequencer_trace_port_t extras_fpu_seq_out; automatic snitch_pkg::fpu_sb_trace_port_t extras_fpu_sb_out; + automatic snitch_pkg::fpu_vfpr_trace_port_t extras_fpu_vfpr_out; if (rst_ni) begin extras_snitch = '{ @@ -919,6 +922,7 @@ module snitch_cc #( // Addenda to FPU extras iff popping sequencer extras_fpu_seq_out = fpu_sequencer_trace; extras_fpu_sb_out = fpu_sb_trace; + extras_fpu_vfpr_out = fpu_vfpr_trace; end end @@ -964,6 +968,13 @@ module snitch_cc #( $fwrite(f, trace_entry); end + if (extras_fpu_vfpr_out.read || extras_fpu_vfpr_out.write) begin + $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, i_snitch.priv_lvl_q, 32'hz, 64'hz, + snitch_pkg::print_fpu_vfpr_trace(extras_fpu_vfpr_out)); + $fwrite(f, trace_entry); + end + end end else begin cycle = '0; diff --git a/hw/snitch_cluster/src/snitch_cluster.sv b/hw/snitch_cluster/src/snitch_cluster.sv index c03727dc1..6f19376e5 100644 --- a/hw/snitch_cluster/src/snitch_cluster.sv +++ b/hw/snitch_cluster/src/snitch_cluster.sv @@ -1002,10 +1002,6 @@ module snitch_cluster end end - initial begin - $display("xfrep: %b", Xfrep); - end - for (genvar i = 0; i < NrHives; i++) begin : gen_hive localparam int unsigned HiveSize = get_hive_size(i); diff --git a/hw/snitch_cluster/src/snitch_fp_ss.sv b/hw/snitch_cluster/src/snitch_fp_ss.sv index 04e6cfd56..0411cb823 100644 --- a/hw/snitch_cluster/src/snitch_fp_ss.sv +++ b/hw/snitch_cluster/src/snitch_fp_ss.sv @@ -40,7 +40,10 @@ module snitch_fp_ss import snitch_pkg::*; #( parameter int unsigned FLEN = DataWidth, /// Derived parameter *Do not override* parameter type addr_t = logic [AddrWidth-1:0], - parameter type data_t = logic [DataWidth-1:0] + parameter type data_t = logic [DataWidth-1:0], + parameter int unsigned ReqAddrWidth = TCDMMemAddrWidth, + parameter int unsigned ReqPrefixWidth = ReqAddrWidth-3, + parameter type regaddr_t = logic [ReqAddrWidth-1:0] ) ( input logic clk_i, input logic rst_i, @@ -48,6 +51,7 @@ module snitch_fp_ss import snitch_pkg::*; #( output fpu_trace_port_t trace_port_o, output fpu_sequencer_trace_port_t sequencer_tracer_port_o, output fpu_sb_trace_port_t sb_tracer_port_o, + output fpu_vfpr_trace_port_t vfpr_tracer_port_o, // pragma translate_on input logic [31:0] hart_id_i, // Accelerator Interface - Slave @@ -92,14 +96,14 @@ module snitch_fp_ss import snitch_pkg::*; #( localparam ScoreboardDepth = 5; - fpnew_pkg::operation_e fpu_op; - fpnew_pkg::roundmode_e fpu_rnd_mode; - fpnew_pkg::fp_format_e src_fmt, dst_fmt; - fpnew_pkg::int_format_e int_fmt; - logic vectorial_op; - logic set_dyn_rm; + // fpnew_pkg::operation_e vfpr_tag_in.fpu_op; + // fpnew_pkg::roundmode_e vfpr_tag_in.fpu_rnd_mode; + // fpnew_pkg::fp_format_e vfpr_tag_in.src_fmt, vfpr_tag_in.dst_fmt; + // fpnew_pkg::int_format_e vfpr_tag_in.int_fmt; + // logic vfpr_tag_in.vectorial_op; + // logic vfpr_tag_in.set_dyn_rm; - logic [2:0][4:0] fpr_raddr; + // logic [2:0][4:0] vfpr_tag_in.fpr_raddr; logic [2:0][FLEN-1:0] fpr_rdata; logic [0:0] fpr_we; @@ -124,24 +128,24 @@ module snitch_fp_ss import snitch_pkg::*; #( tag_t lsu_tag_in, lsu_tag_out; // scoreboard - logic [ScoreboardDepth-1:0] rd_index; + // logic [ScoreboardDepth-1:0] rd_index; logic [3:0][4:0] sb_tests; logic [3:0] sb_collision; logic sb_full; - logic use_fpu; + // logic vfpr_tag_in.is_fpu; logic [2:0][FLEN-1:0] op; - logic [2:0] op_ready; // operand is ready + logic [2:0] vfpr_op_ready; - logic lsu_qready; - logic lsu_qvalid; + logic lsu_in_ready; + logic lsu_in_valid; logic [FLEN-1:0] ld_result; logic lsu_pvalid; logic lsu_pready; - logic is_store, is_load; + // logic vfpr_tag_in.is_store, vfpr_tag_in.is_load; // logic [31:0] sb_d, sb_q; - logic rd_is_fp; + // logic vfpr_tag_in.rd_is_fp; // `FFAR(sb_q, sb_d, '0, clk_i, rst_i) logic csr_instr; @@ -150,6 +154,13 @@ module snitch_fp_ss import snitch_pkg::*; #( logic fpu_out_valid, fpu_out_ready; logic fpu_in_valid, fpu_in_ready; + // WR tcdm requests + tcdm_req_t fpr_wr_req; + tcdm_rsp_t fpss_wr_rsp; + + tcdm_req_t vfpr_req; + tcdm_req_t vfpr_rsp; + typedef enum logic [2:0] { None, AccBus, @@ -157,16 +168,16 @@ module snitch_fp_ss import snitch_pkg::*; #( RegBRep, // Replication for vectors RegDest } op_select_e; - op_select_e [2:0] op_select; + // op_select_e [2:0] vfpr_tag_in.op_select; typedef enum logic [1:0] { ResNone, ResAccBus } result_select_e; result_select_e result_select; - logic op_mode; + // logic vfpr_tag_in.op_mode; - logic [4:0] rs1, rs2, rs3, rd; + logic [4:0] rs1, rs2, rs3; // vfpr_tag_in.rd; // LSU typedef enum logic [1:0] { @@ -175,11 +186,42 @@ module snitch_fp_ss import snitch_pkg::*; #( Word = 2'b10, DoubleWord = 2'b11 } ls_size_e; - ls_size_e ls_size; + // ls_size_e vfpr_tag_in.ls_size; logic dst_ready; + // VFPR Controller + logic vfpr_in_valid, vfpr_in_ready; + logic vfpr_out_valid, vfpr_out_ready; + + typedef struct packed { + op_select_e [2:0] op_select; + logic [2:0][4:0] fpr_raddr; // TODO remove + fpnew_pkg::operation_e fpu_op; + fpnew_pkg::roundmode_e fpu_rnd_mode; + fpnew_pkg::fp_format_e src_fmt; + fpnew_pkg::fp_format_e dst_fmt; + fpnew_pkg::int_format_e int_fmt; + logic vectorial_op; + logic set_dyn_rm; + logic op_mode; + logic is_fpu; + logic is_store; + logic is_load; + logic rd_is_fp; + logic rd_is_acc; + ls_size_e ls_size; + data_t data_arga; + data_t data_argb; + data_t data_argc; + logic [4:0] rd; + regaddr_t rd_bnk_addr; + logic [ScoreboardDepth-1:0] fpr_windex; + } vfpr_tag_t; + + vfpr_tag_t vfpr_tag_in, vfpr_tag_out; + // ------------- // FPU Sequencer // ------------- @@ -226,9 +268,6 @@ module snitch_fp_ss import snitch_pkg::*; #( assign acc_req = acc_req_i; end - logic seq_valid; - assign acc_req_valid_q = seq_valid & ~sb_full; - // Optional spill-register spill_register #( .T ( acc_req_t ), @@ -239,16 +278,23 @@ module snitch_fp_ss import snitch_pkg::*; #( .valid_i ( acc_req_valid ), .ready_o ( acc_req_ready ), .data_i ( acc_req ), - .valid_o ( seq_valid ), + .valid_o ( acc_req_valid_q ), .ready_i ( acc_req_ready_q ), .data_o ( acc_req_q ) ); - assign sb_tests[0] = fpr_raddr[0]; - assign sb_tests[1] = fpr_raddr[1]; - assign sb_tests[2] = fpr_raddr[2]; - assign sb_tests[3] = rd; - // assign sb_tests = {rd, fpr_raddr[2], fpr_raddr[1], fpr_raddr[0]}; + assign vfpr_tag_in.data_arga = acc_req_q.data_arga; + assign vfpr_tag_in.data_argb = acc_req_q.data_argb; + assign vfpr_tag_in.data_argc = acc_req_q.data_argc; + assign vfpr_tag_in.rd_bnk_addr = vfpr_tag_in.rd; // TODO + + assign sb_tests[0] = vfpr_tag_in.fpr_raddr[0]; + assign sb_tests[1] = vfpr_tag_in.fpr_raddr[1]; + assign sb_tests[2] = vfpr_tag_in.fpr_raddr[2]; + assign sb_tests[3] = vfpr_tag_in.rd; + // assign sb_tests = {vfpr_tag_in.rd, vfpr_tag_in.fpr_raddr[2], vfpr_tag_in.fpr_raddr[1], vfpr_tag_in.fpr_raddr[0]}; + + logic sb_push_valid; snitch_sb #( .AddrWidth(5), .Depth(ScoreboardDepth), @@ -256,9 +302,9 @@ module snitch_fp_ss import snitch_pkg::*; #( ) i_sb ( .clk_i, .rst_i, - .push_rd_addr_i(rd), - .push_valid_i(acc_req_valid_q & acc_req_ready_q & ~sb_full & rd_is_fp), - .entry_index_o(rd_index), + .push_rd_addr_i(vfpr_tag_in.rd), + .push_valid_i(sb_push_valid), + .entry_index_o(vfpr_tag_in.fpr_windex), .pop_index_i(fpr_windex), .pop_valid_i(sb_pop_valid), .test_addr_i(sb_tests), @@ -272,68 +318,112 @@ module snitch_fp_ss import snitch_pkg::*; #( // this handles WAW Hazards - Potentially this can be relaxed if necessary // at the expense of increased timing pressure - // assign dst_ready = ~(rd_is_fp & sb_q[rd]); - assign dst_ready = ~(rd_is_fp & sb_collision[3]); + // assign dst_ready = ~(vfpr_tag_in.rd_is_fp & sb_q[vfpr_tag_in.rd]); + assign dst_ready = ~(vfpr_tag_in.rd_is_fp & (sb_collision[3] | sb_full)); + + // if this is a csr instruction, or something we don't recognize, skip + logic ex_ins_valid, ex_ins_ready; + logic drop_ins; + assign drop_ins = csr_instr | ~(vfpr_tag_in.is_fpu | vfpr_tag_in.is_load | vfpr_tag_in.is_store | (result_select == ResAccBus)); + stream_filter i_csr_filter ( + .valid_i(acc_req_valid_q), + .ready_o(acc_req_ready_q), + .drop_i(drop_ins), + .valid_o(ex_ins_valid), + .ready_i(ex_ins_ready) + ); + + // stall the stream if rd isn't ready yet + logic ex_dst_valid, ex_dst_ready; + stream_stall i_dst_stall ( + .valid_i(ex_ins_valid), + .ready_o(ex_ins_ready), + .stall(~dst_ready), + .valid_o(ex_dst_valid), + .ready_i(ex_dst_ready) + ); + + // demux accelerator write datapath (despite being unused atm) + logic vfpr_dp_valid, vfpr_dp_ready; + logic acc_dp_valid, acc_dp_ready; + logic acc_demux_sel; + assign acc_demux_sel = (result_select == ResAccBus); + stream_demux #( + .N_OUP(2) + ) i_acc_demux ( + .inp_valid_i(ex_dst_valid), + .inp_ready_o(ex_dst_ready), + .oup_sel_i(acc_demux_sel), + .oup_valid_o({acc_dp_valid, vfpr_dp_valid}), + .oup_ready_i({acc_dp_ready, vfpr_dp_ready}) + ); + + // stall if operands are not ready + stream_stall i_vfpr_op_stall ( + .valid_i(vfpr_dp_valid), + .ready_o(vfpr_dp_ready), + .stall(~(&vfpr_op_ready)), + .valid_o(vfpr_in_valid), + .ready_i(vfpr_in_ready) + ); + + // ready to commit - check in addr to scoreboard + assign sb_push_valid = (vfpr_in_valid & vfpr_in_ready & vfpr_tag_in.rd_is_fp); + + // determine whether to use lsu or fpu + // (assumes that op can only be lsu op or fpu op) + logic fpu_lsu_sel; + assign fpu_lsu_sel = vfpr_tag_out.is_load | vfpr_tag_out.is_store; + stream_demux #( + .N_OUP(2) + ) i_fpu_lsu_demux ( + .inp_valid_i(vfpr_out_valid), + .inp_ready_o(vfpr_out_ready), + .oup_sel_i(fpu_lsu_sel), + .oup_valid_o({lsu_in_valid, fpu_in_valid}), + .oup_ready_i({lsu_in_ready, fpu_in_ready}) + ); always_ff @(posedge clk_i) begin if (hart_id_i == 0) begin - // if (fpu_in_valid & fpu_in_ready) begin - // $display("%t IN: fpu tag rd: %d", $time, fpu_tag_in.rd); - // $display("%t IN: rd: %d", $time, rd); - // $display("%t IN: rd index: %d", $time, rd_index); - // end - // if (fpu_out_valid & fpu_out_ready) begin - // $display("%t OUT: fpu tag rd: %d", $time, fpu_tag_out.rd); - // $display("%t OUT: waddr: %d", $time, fpr_waddr); - // $display("%t OUT: windex: %d", $time, fpr_windex); - // end - // $display("*** Pre SB signals:"); - // $display("acc_req_valid: %d", acc_req_valid); - // $display("acc_req_ready: %d", acc_req_ready); - // $display("acc_req_valid_q: %d", acc_req_valid_q); - // $display("acc_req_ready_q: %d", acc_req_ready_q); - // $display("*** SB signals:"); - // $display("sb_collision: %d, %d, %d, %d", sb_collision[0], sb_collision[1], sb_collision[2], sb_collision[3]); - // $display("rd_is_fp: %d", rd_is_fp); - // $display("pop index: %b", fpr_windex); - // $display("sb out index: %b", rd_index); - // $display("push_valid_i: %d", acc_req_valid_q & acc_req_ready_q & rd_is_fp); - // $display("rd: %d", rd); - // $display("seq_valid: %d", seq_valid); - // $display("free_slots: %d", i_sb.i_indices.usage_o); - // $display("fifo read pointer: %d", i_sb.i_indices.read_pointer_q); - // $display("fifo read value: %b", i_sb.i_indices.data_o); - // $display("fifo %b %b %b %b %b", i_sb.i_indices.mem_q[0], i_sb.i_indices.mem_q[1], i_sb.i_indices.mem_q[2], i_sb.i_indices.mem_q[3], i_sb.i_indices.mem_q[4]); - // $display("occupied: %b", i_sb.occupied); - // $display("sb_tests: %d, %d, %d, %d", sb_tests[0], sb_tests[1], sb_tests[2], sb_tests[3]); - // $display("sb_full: %d", sb_full); - // $display("sb_pop_valid: %d", sb_pop_valid); - // $display("*** EX signals:"); - // $display("op_ready: %d, %d, %d", op_ready[0], op_ready[1], op_ready[2]); - // $display("use_fpu: %d", use_fpu); - // $display("fpu_in_valid: %d", fpu_in_valid); - // $display("fpu_in_ready: %d", fpu_in_ready); - // $display("lsu_qvalid: %d", lsu_qvalid); - // $display("lsu_qready: %d", lsu_qready); - // $display("dst_ready: %d", dst_ready); - // $display("op_select: %d, %d, %d", op_select[0], op_select[1], op_select[2]); - // $display("---"); + if (ex_ins_valid & ex_ins_ready) begin + $display("%d: ex_dp", $time); + end + if (ex_dst_valid & ex_dst_ready) begin + $display("%d: ex_dst", $time); + end + if (vfpr_dp_valid & vfpr_dp_ready) begin + $display("%d: vfpr_dp", $time); + end + if (acc_dp_valid & acc_dp_ready) begin + $display("%d: acc_dp", $time); + end + if (vfpr_in_valid & vfpr_in_ready) begin + $display("%d: vfpr_in", $time); + end + if (vfpr_out_valid & vfpr_out_ready) begin + $display("%d: vfpr_out", $time); + end + if (sb_push_valid) begin + $display("%d: sb_push", $time); + end + if (fpu_in_valid & fpu_in_ready) begin + $display("%d: fpu_in", $time); + end + if (fpu_out_valid & fpu_out_ready) begin + $display("%d: fpu_out, %b, %b, %b, %b, %b", + $time, fpu_in_valid, vfpr_out_valid, vfpr_tag_out.is_fpu, vfpr_tag_out.is_load, vfpr_tag_out.is_store + ); + end + if (lsu_in_valid & lsu_in_ready) begin + $display("%d: lsu_in", $time); + end + if (lsu_pvalid & lsu_pready) begin + $display("%d: lsu_out", $time); + end end end - // check that either: - // 1. The FPU and all operands are ready - // 2. The LSU request can be handled - // 3. The regfile operand is ready - assign fpu_in_valid = use_fpu & acc_req_valid_q & (&op_ready) & dst_ready; - // FPU ready - assign acc_req_ready_q = ~(sb_full & rd_is_fp) & dst_ready & ((fpu_in_ready & fpu_in_valid) - // Load/Store - | (lsu_qvalid & lsu_qready) - | csr_instr - // Direct Reg Write - | (acc_req_valid_q && result_select == ResAccBus)); - // either the FPU or the regfile produced a result assign acc_resp_valid_o = (fpu_tag_out.acc & fpu_out_valid); // stall FPU if we forward from reg @@ -347,7 +437,7 @@ module snitch_fp_ss import snitch_pkg::*; #( // accelerator bus write-port assign acc_resp_o.data = fpu_result; - assign rd = acc_req_q.data_op[11:7]; + assign vfpr_tag_in.rd = acc_req_q.data_op[11:7]; assign rs1 = acc_req_q.data_op[19:15]; assign rs2 = acc_req_q.data_op[24:20]; assign rs3 = acc_req_q.data_op[31:27]; @@ -357,7 +447,7 @@ module snitch_fp_ss import snitch_pkg::*; #( // always_comb begin // sb_d = sb_q; // // if the instruction is going to write the FPR mark it - // if (acc_req_valid_q & acc_req_ready_q & rd_is_fp) sb_d[rd] = 1'b1; + // if (acc_req_valid_q & acc_req_ready_q & vfpr_tag_in.rd_is_fp) sb_d[vfpr_tag_in.rd] = 1'b1; // // reset the value if we are committing the register // if (fpr_we) sb_d[fpr_waddr] = 1'b0; // // don't track any dependencies for SSRs if enabled @@ -367,50 +457,43 @@ module snitch_fp_ss import snitch_pkg::*; #( // end // Determine whether destination register is SSR - logic is_rd_ssr; - always_comb begin - is_rd_ssr = 1'b0; - for (int s = 0; s < NumSsrs; s++) - is_rd_ssr |= (SsrRegs[s] == rd); - end - always_comb begin acc_resp_o.error = 1'b0; - fpu_op = fpnew_pkg::ADD; - use_fpu = 1'b1; - fpu_rnd_mode = (fpnew_pkg::roundmode_e'(acc_req_q.data_op[14:12]) == fpnew_pkg::DYN) + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.is_fpu = 1'b1; + vfpr_tag_in.fpu_rnd_mode = (fpnew_pkg::roundmode_e'(acc_req_q.data_op[14:12]) == fpnew_pkg::DYN) ? fpu_rnd_mode_i : fpnew_pkg::roundmode_e'(acc_req_q.data_op[14:12]); - set_dyn_rm = 1'b0; + vfpr_tag_in.set_dyn_rm = 1'b0; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - int_fmt = fpnew_pkg::INT32; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.int_fmt = fpnew_pkg::INT32; result_select = ResNone; - op_select[0] = None; - op_select[1] = None; - op_select[2] = None; + vfpr_tag_in.op_select[0] = None; + vfpr_tag_in.op_select[1] = None; + vfpr_tag_in.op_select[2] = None; - vectorial_op = 1'b0; - op_mode = 1'b0; + vfpr_tag_in.vectorial_op = 1'b0; + vfpr_tag_in.op_mode = 1'b0; - fpu_tag_in.rd = rd; - fpu_tag_in.fpr_windex = rd_index; - fpu_tag_in.acc = 1'b0; // RD is on accelerator bus - fpu_tag_in.ssr = ssr_active_q & is_rd_ssr; + fpu_tag_in.rd = vfpr_tag_out.rd; + fpu_tag_in.fpr_windex = vfpr_tag_out.fpr_windex; + fpu_tag_in.acc = vfpr_tag_out.rd_is_acc; - lsu_tag_in.rd = rd; - lsu_tag_in.fpr_windex = rd_index; + lsu_tag_in.rd = vfpr_tag_out.rd; + lsu_tag_in.fpr_windex = vfpr_tag_out.fpr_windex; - is_store = 1'b0; - is_load = 1'b0; - ls_size = Word; + vfpr_tag_in.is_store = 1'b0; + vfpr_tag_in.is_load = 1'b0; + vfpr_tag_in.ls_size = Word; + vfpr_tag_in.rd_is_acc = 1'b0; // RD is on accelerator bus // Destination register is in FPR - rd_is_fp = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b1; csr_instr = 1'b0; // is a csr instruction // SSR register ssr_active_d = ssr_active_q; @@ -418,1293 +501,1293 @@ module snitch_fp_ss import snitch_pkg::*; #( // FP - FP Operations // Single Precision riscv_instr::FADD_S: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; end riscv_instr::FSUB_S: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; end riscv_instr::FMUL_S: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; end riscv_instr::FDIV_S: begin // currently illegal - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; end riscv_instr::FSGNJ_S, riscv_instr::FSGNJN_S, riscv_instr::FSGNJX_S: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; end riscv_instr::FMIN_S, riscv_instr::FMAX_S: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; end riscv_instr::FSQRT_S: begin // currently illegal - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; end riscv_instr::FMADD_S: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; end riscv_instr::FMSUB_S: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; end riscv_instr::FNMSUB_S: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; end riscv_instr::FNMADD_S: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; end // Vectorial Single Precision riscv_instr::VFADD_S, riscv_instr::VFADD_R_S: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_S}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFADD_R_S}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFSUB_S, riscv_instr::VFSUB_R_S: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_S}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_S}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFMUL_S, riscv_instr::VFMUL_R_S: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFDIV_S, riscv_instr::VFDIV_R_S: begin // currently illegal - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMIN_S, riscv_instr::VFMIN_R_S: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMAX_S, riscv_instr::VFMAX_R_S: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSQRT_S: begin // currently illegal - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFMAC_S, riscv_instr::VFMAC_R_S: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMRE_S, riscv_instr::VFMRE_R_S: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJ_S, riscv_instr::VFSGNJ_R_S: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJN_S, riscv_instr::VFSGNJN_R_S: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJX_S, riscv_instr::VFSGNJX_R_S: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSUM_S, riscv_instr::VFNSUM_S: begin - fpu_op = fpnew_pkg::VSUM; - op_select[0] = RegA; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_S}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::VSUM; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNSUM_S}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCPKA_S_S: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFCPKA_S_D: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end // Double Precision riscv_instr::FADD_D: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FSUB_D: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FMUL_D: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FDIV_D: begin - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FSGNJ_D, riscv_instr::FSGNJN_D, riscv_instr::FSGNJX_D: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FMIN_D, riscv_instr::FMAX_D: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FSQRT_D: begin - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FMADD_D: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FMSUB_D: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FNMSUB_D: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FNMADD_D: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FCVT_S_D: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_D_S: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end // [Alternate] Half Precision riscv_instr::FADD_H: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FSUB_H: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FMUL_H: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FDIV_H: begin - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FSGNJ_H, riscv_instr::FSGNJN_H, riscv_instr::FSGNJX_H: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FMIN_H, riscv_instr::FMAX_H: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FSQRT_H: begin - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FMADD_H: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FMSUB_H: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FNMSUB_H: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FNMADD_H: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::VFSUM_H, riscv_instr::VFNSUM_H: begin - fpu_op = fpnew_pkg::VSUM; - op_select[0] = RegA; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_H}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::VSUM; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNSUM_H}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::FMULEX_S_H: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FMACEX_S_H: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_S_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_H_S: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; end riscv_instr::FCVT_D_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FCVT_H_D: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; end riscv_instr::FCVT_H_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; end // Vectorial [alternate] Half Precision riscv_instr::VFADD_H, riscv_instr::VFADD_R_H: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_H}) op_select[2] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFADD_R_H}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFSUB_H, riscv_instr::VFSUB_R_H: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_H}) op_select[2] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_H}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFMUL_H, riscv_instr::VFMUL_R_H: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFDIV_H, riscv_instr::VFDIV_R_H: begin - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMIN_H, riscv_instr::VFMIN_R_H: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMAX_H, riscv_instr::VFMAX_R_H: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - fpu_rnd_mode = fpnew_pkg::RTZ; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSQRT_H: begin - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFMAC_H, riscv_instr::VFMAC_R_H: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMRE_H, riscv_instr::VFMRE_R_H: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJ_H, riscv_instr::VFSGNJ_R_H: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJN_H, riscv_instr::VFSGNJN_R_H: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJX_H, riscv_instr::VFSGNJX_R_H: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFCPKA_H_S: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFCPKB_H_S: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFCVT_S_H, riscv_instr::VFCVTU_S_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_H}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_H}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_H_S, riscv_instr::VFCVTU_H_S: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_S}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_S}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCPKA_H_D: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFCPKB_H_D: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFDOTPEX_S_H, riscv_instr::VFDOTPEX_S_R_H: begin - fpu_op = fpnew_pkg::SDOTP; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_S_R_H}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SDOTP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_S_R_H}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFNDOTPEX_S_H, riscv_instr::VFNDOTPEX_S_R_H: begin - fpu_op = fpnew_pkg::SDOTP; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_S_R_H}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SDOTP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_S_R_H}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFSUMEX_S_H, riscv_instr::VFNSUMEX_S_H: begin - fpu_op = fpnew_pkg::EXVSUM; - op_select[0] = RegA; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_S_H}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::EXVSUM; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_S_H}) vfpr_tag_in.op_mode = 1'b1; end // [Alternate] Quarter Precision riscv_instr::FADD_B: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FSUB_B: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FMUL_B: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FDIV_B: begin - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FSGNJ_B, riscv_instr::FSGNJN_B, riscv_instr::FSGNJX_B: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FMIN_B, riscv_instr::FMAX_B: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FSQRT_B: begin - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FMADD_B: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FMSUB_B: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FNMSUB_B: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FNMADD_B: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegC; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegC; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::VFSUM_B, riscv_instr::VFNSUM_B: begin - fpu_op = fpnew_pkg::VSUM; - op_select[0] = RegA; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_B}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::VSUM; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNSUM_B}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::FMULEX_S_B: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FMACEX_S_B: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_S_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_B_S: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; end riscv_instr::FCVT_D_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; end riscv_instr::FCVT_B_D: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; end riscv_instr::FCVT_H_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; end riscv_instr::FCVT_B_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; end // Vectorial [alternate] Quarter Precision riscv_instr::VFADD_B, riscv_instr::VFADD_R_B: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_B}) op_select[2] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFADD_R_B}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFSUB_B, riscv_instr::VFSUB_R_B: begin - fpu_op = fpnew_pkg::ADD; - op_select[1] = RegA; - op_select[2] = RegB; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::ADD; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.op_select[2] = RegB; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_B}) op_select[2] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_B}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFMUL_B, riscv_instr::VFMUL_R_B: begin - fpu_op = fpnew_pkg::MUL; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::MUL; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFDIV_B, riscv_instr::VFDIV_R_B: begin - fpu_op = fpnew_pkg::DIV; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::DIV; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMIN_B, riscv_instr::VFMIN_R_B: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMAX_B, riscv_instr::VFMAX_R_B: begin - fpu_op = fpnew_pkg::MINMAX; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::MINMAX; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - fpu_rnd_mode = fpnew_pkg::RTZ; - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSQRT_B: begin - fpu_op = fpnew_pkg::SQRT; - op_select[0] = RegA; - op_select[1] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SQRT; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; end riscv_instr::VFMAC_B, riscv_instr::VFMAC_R_B: begin - fpu_op = fpnew_pkg::FMADD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FMADD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFMRE_B, riscv_instr::VFMRE_R_B: begin - fpu_op = fpnew_pkg::FNMSUB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::FNMSUB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJ_B, riscv_instr::VFSGNJ_R_B: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJN_B, riscv_instr::VFSGNJN_R_B: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFSGNJX_B, riscv_instr::VFSGNJX_R_B: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFCPKA_B_S, riscv_instr::VFCPKB_B_S: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_S}) op_mode = 1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_S}) vfpr_tag_in.op_mode = 1; end riscv_instr::VFCPKC_B_S, riscv_instr::VFCPKD_B_S: begin - fpu_op = fpnew_pkg::CPKCD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_S}) op_mode = 1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKCD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_S}) vfpr_tag_in.op_mode = 1; end riscv_instr::VFCPKA_B_D, riscv_instr::VFCPKB_B_D: begin - fpu_op = fpnew_pkg::CPKAB; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_D}) op_mode = 1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKAB; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_D}) vfpr_tag_in.op_mode = 1; end riscv_instr::VFCPKC_B_D, riscv_instr::VFCPKD_B_D: begin - fpu_op = fpnew_pkg::CPKCD; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_D}) op_mode = 1; + vfpr_tag_in.fpu_op = fpnew_pkg::CPKCD; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_D}) vfpr_tag_in.op_mode = 1; end riscv_instr::VFCVT_S_B, riscv_instr::VFCVTU_S_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_B}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_B}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_B_S, riscv_instr::VFCVTU_B_S: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_S}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_S}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_H_H, riscv_instr::VFCVTU_H_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_H}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_H}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_H_B, riscv_instr::VFCVTU_H_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_B}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_B}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_B_H, riscv_instr::VFCVTU_B_H: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_H}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_H}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFCVT_B_B, riscv_instr::VFCVTU_B_B: begin - fpu_op = fpnew_pkg::F2F; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_B}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::F2F; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_B}) vfpr_tag_in.op_mode = 1'b1; end riscv_instr::VFDOTPEX_H_B, riscv_instr::VFDOTPEX_H_R_B: begin - fpu_op = fpnew_pkg::SDOTP; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_H_R_B}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SDOTP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_H_R_B}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFNDOTPEX_H_B, riscv_instr::VFNDOTPEX_H_R_B: begin - fpu_op = fpnew_pkg::SDOTP; - op_select[0] = RegA; - op_select[1] = RegB; - op_select[2] = RegDest; - op_mode = 1'b1; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_H_R_B}) op_select[2] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::SDOTP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_H_R_B}) vfpr_tag_in.op_select[2] = RegBRep; end riscv_instr::VFSUMEX_H_B, riscv_instr::VFNSUMEX_H_B: begin - fpu_op = fpnew_pkg::EXVSUM; - op_select[0] = RegA; - op_select[2] = RegDest; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_H_B}) op_mode = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::EXVSUM; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[2] = RegDest; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_H_B}) vfpr_tag_in.op_mode = 1'b1; end // ------------------- // From float to int @@ -1713,795 +1796,837 @@ module snitch_fp_ss import snitch_pkg::*; #( riscv_instr::FLE_S, riscv_instr::FLT_S, riscv_instr::FEQ_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCLASS_S: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCVT_W_S, riscv_instr::FCVT_WU_S: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_S}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_S}) vfpr_tag_in.op_mode = 1'b1; // unsigned end riscv_instr::FMV_X_W: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end // Vectorial Single Precision riscv_instr::VFEQ_S, riscv_instr::VFEQ_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFNE_S, riscv_instr::VFNE_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFNE_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLT_S, riscv_instr::VFLT_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLT_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGE_S, riscv_instr::VFGE_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGE_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLE_S, riscv_instr::VFLE_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLE_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGT_S, riscv_instr::VFGT_R_S: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_S}) op_select[1] = RegBRep; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGT_R_S}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFCLASS_S: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end // Double Precision Floating-Point riscv_instr::FLE_D, riscv_instr::FLT_D, riscv_instr::FEQ_D: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCLASS_D: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCVT_W_D, riscv_instr::FCVT_WU_D: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_D}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_D}) vfpr_tag_in.op_mode = 1'b1; // unsigned end riscv_instr::FMV_X_D: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end // [Alternate] Half Precision Floating-Point riscv_instr::FLE_H, riscv_instr::FLT_H, riscv_instr::FEQ_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCLASS_H: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCVT_W_H, riscv_instr::FCVT_WU_H: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_H}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_H}) vfpr_tag_in.op_mode = 1'b1; // unsigned end riscv_instr::FMV_X_H: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end // Vectorial [alternate] Half Precision riscv_instr::VFEQ_H, riscv_instr::VFEQ_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFNE_H, riscv_instr::VFNE_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFNE_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLT_H, riscv_instr::VFLT_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLT_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGE_H, riscv_instr::VFGE_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGE_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLE_H, riscv_instr::VFLE_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLE_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGT_H, riscv_instr::VFGT_R_H: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_H}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGT_R_H}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFCLASS_H: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::VFMV_X_H: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::VFCVT_X_H, riscv_instr::VFCVT_XU_H: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - int_fmt = fpnew_pkg::INT16; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_H}) op_mode = 1'b1; // upper + vfpr_tag_in.int_fmt = fpnew_pkg::INT16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_H}) vfpr_tag_in.op_mode = 1'b1; // upper end // [Alternate] Quarter Precision Floating-Point riscv_instr::FLE_B, riscv_instr::FLT_B, riscv_instr::FEQ_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCLASS_B: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::FCVT_W_B, riscv_instr::FCVT_WU_B: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_B}) op_mode = 1'b1; // unsigned + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_B}) vfpr_tag_in.op_mode = 1'b1; // unsigned end riscv_instr::FMV_X_B: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end // Vectorial Quarter Precision riscv_instr::VFEQ_B, riscv_instr::VFEQ_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFNE_B, riscv_instr::VFNE_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RDN; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RDN; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFNE_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLT_B, riscv_instr::VFLT_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLT_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGE_B, riscv_instr::VFGE_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RTZ; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RTZ; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGE_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFLE_B, riscv_instr::VFLE_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFLE_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFGT_B, riscv_instr::VFGT_R_B: begin - fpu_op = fpnew_pkg::CMP; - op_select[0] = RegA; - op_select[1] = RegB; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CMP; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - op_mode = 1'b1; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_B}) op_select[1] = RegBRep; + vfpr_tag_in.op_mode = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + if (acc_req_q.data_op inside {riscv_instr::VFGT_R_B}) vfpr_tag_in.op_select[1] = RegBRep; end riscv_instr::VFCLASS_B: begin - fpu_op = fpnew_pkg::CLASSIFY; - op_select[0] = RegA; - fpu_rnd_mode = fpnew_pkg::RNE; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::CLASSIFY; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RNE; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::VFMV_X_B: begin - fpu_op = fpnew_pkg::SGNJ; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - op_mode = 1'b1; // sign-extend result - op_select[0] = RegA; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.op_mode = 1'b1; // sign-extend result + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; end riscv_instr::VFCVT_X_B, riscv_instr::VFCVT_XU_B: begin - fpu_op = fpnew_pkg::F2I; - op_select[0] = RegA; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::F2I; + vfpr_tag_in.op_select[0] = RegA; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.src == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end - int_fmt = fpnew_pkg::INT8; - vectorial_op = 1'b1; - fpu_tag_in.acc = 1'b1; - rd_is_fp = 1'b0; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_B}) op_mode = 1'b1; // upper + vfpr_tag_in.int_fmt = fpnew_pkg::INT8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.rd_is_acc = 1'b1; + vfpr_tag_in.rd_is_fp = 1'b0; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_B}) vfpr_tag_in.op_mode = 1'b1; // upper end // ------------------- // From int to float // ------------------- // Single Precision Floating-Point riscv_instr::FMV_W_X: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = AccBus; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP32; - dst_fmt = fpnew_pkg::FP32; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP32; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; end riscv_instr::FCVT_S_W, riscv_instr::FCVT_S_WU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - dst_fmt = fpnew_pkg::FP32; - if (acc_req_q.data_op inside {riscv_instr::FCVT_S_WU}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP32; + if (acc_req_q.data_op inside {riscv_instr::FCVT_S_WU}) vfpr_tag_in.op_mode = 1'b1; // unsigned end // Double Precision Floating-Point riscv_instr::FCVT_D_W, riscv_instr::FCVT_D_WU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - src_fmt = fpnew_pkg::FP64; - dst_fmt = fpnew_pkg::FP64; - if (acc_req_q.data_op inside {riscv_instr::FCVT_D_WU}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.src_fmt = fpnew_pkg::FP64; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP64; + if (acc_req_q.data_op inside {riscv_instr::FCVT_D_WU}) vfpr_tag_in.op_mode = 1'b1; // unsigned end // [Alternate] Half Precision Floating-Point riscv_instr::FMV_H_X: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = AccBus; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end end riscv_instr::FCVT_H_W, riscv_instr::FCVT_H_WU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - if (acc_req_q.data_op inside {riscv_instr::FCVT_H_WU}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {riscv_instr::FCVT_H_WU}) vfpr_tag_in.op_mode = 1'b1; // unsigned end // Vectorial Half Precision Floating-Point riscv_instr::VFMV_H_X: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = AccBus; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - vectorial_op = 1'b1; + vfpr_tag_in.vectorial_op = 1'b1; end riscv_instr::VFCVT_H_X, riscv_instr::VFCVT_H_XU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - src_fmt = fpnew_pkg::FP16; - dst_fmt = fpnew_pkg::FP16; + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP16ALT; - dst_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; end - int_fmt = fpnew_pkg::INT16; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_H_XU}) op_mode = 1'b1; // upper + vfpr_tag_in.int_fmt = fpnew_pkg::INT16; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVT_H_XU}) vfpr_tag_in.op_mode = 1'b1; // upper end // [Alternate] Quarter Precision Floating-Point riscv_instr::FMV_B_X: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = AccBus; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; if (fpu_fmt_mode_i.dst == 1'b1) begin - src_fmt = fpnew_pkg::FP8ALT; - dst_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; end end riscv_instr::FCVT_B_W, riscv_instr::FCVT_B_WU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; - if (acc_req_q.data_op inside {riscv_instr::FCVT_B_WU}) op_mode = 1'b1; // unsigned + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + if (acc_req_q.data_op inside {riscv_instr::FCVT_B_WU}) vfpr_tag_in.op_mode = 1'b1; // unsigned end // Vectorial Quarter Precision Floating-Point riscv_instr::VFMV_B_X: begin - fpu_op = fpnew_pkg::SGNJ; - op_select[0] = AccBus; - fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; - vectorial_op = 1'b1; + vfpr_tag_in.fpu_op = fpnew_pkg::SGNJ; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.vectorial_op = 1'b1; end riscv_instr::VFCVT_B_X, riscv_instr::VFCVT_B_XU: begin - fpu_op = fpnew_pkg::I2F; - op_select[0] = AccBus; - src_fmt = fpnew_pkg::FP8; - dst_fmt = fpnew_pkg::FP8; - int_fmt = fpnew_pkg::INT8; - vectorial_op = 1'b1; - set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_B_XU}) op_mode = 1'b1; // upper + vfpr_tag_in.fpu_op = fpnew_pkg::I2F; + vfpr_tag_in.op_select[0] = AccBus; + vfpr_tag_in.src_fmt = fpnew_pkg::FP8; + vfpr_tag_in.dst_fmt = fpnew_pkg::FP8; + vfpr_tag_in.int_fmt = fpnew_pkg::INT8; + vfpr_tag_in.vectorial_op = 1'b1; + vfpr_tag_in.set_dyn_rm = 1'b1; + if (acc_req_q.data_op inside {riscv_instr::VFCVT_B_XU}) vfpr_tag_in.op_mode = 1'b1; // upper end // ------------- // Load / Store // ------------- // Single Precision Floating-Point riscv_instr::FLW: begin - is_load = 1'b1; - use_fpu = 1'b0; + vfpr_tag_in.is_load = 1'b1; + vfpr_tag_in.is_fpu = 1'b0; end riscv_instr::FSW: begin - is_store = 1'b1; - op_select[1] = RegB; - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_store = 1'b1; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; end // Double Precision Floating-Point riscv_instr::FLD: begin - is_load = 1'b1; - ls_size = DoubleWord; - use_fpu = 1'b0; + vfpr_tag_in.is_load = 1'b1; + vfpr_tag_in.ls_size = DoubleWord; + vfpr_tag_in.is_fpu = 1'b0; end riscv_instr::FSD: begin - is_store = 1'b1; - op_select[1] = RegB; - ls_size = DoubleWord; - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_store = 1'b1; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.ls_size = DoubleWord; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; end // [Alternate] Half Precision Floating-Point riscv_instr::FLH: begin - is_load = 1'b1; - ls_size = HalfWord; - use_fpu = 1'b0; + vfpr_tag_in.is_load = 1'b1; + vfpr_tag_in.ls_size = HalfWord; + vfpr_tag_in.is_fpu = 1'b0; end riscv_instr::FSH: begin - is_store = 1'b1; - op_select[1] = RegB; - ls_size = HalfWord; - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_store = 1'b1; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.ls_size = HalfWord; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; end // [Alternate] Quarter Precision Floating-Point riscv_instr::FLB: begin - is_load = 1'b1; - ls_size = Byte; - use_fpu = 1'b0; + vfpr_tag_in.is_load = 1'b1; + vfpr_tag_in.ls_size = Byte; + vfpr_tag_in.is_fpu = 1'b0; end riscv_instr::FSB: begin - is_store = 1'b1; - op_select[1] = RegB; - ls_size = Byte; - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_store = 1'b1; + vfpr_tag_in.op_select[1] = RegB; + vfpr_tag_in.ls_size = Byte; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; end // ------------- // CSR Handling // ------------- // Set or clear corresponding CSR riscv_instr::CSRRSI: begin - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; csr_instr = 1'b1; ssr_active_d |= rs1[0]; end riscv_instr::CSRRCI: begin - use_fpu = 1'b0; - rd_is_fp = 1'b0; + vfpr_tag_in.is_fpu = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; csr_instr = 1'b1; ssr_active_d &= ~rs1[0]; end default: begin - use_fpu = 1'b0; + vfpr_tag_in.is_fpu = 1'b0; acc_resp_o.error = 1'b1; - rd_is_fp = 1'b0; + vfpr_tag_in.rd_is_fp = 1'b0; end endcase // fix round mode for vectors and fp16alt - if (set_dyn_rm) fpu_rnd_mode = fpu_rnd_mode_i; - // check if src_fmt or dst_fmt is acutually the alternate version + if (vfpr_tag_in.set_dyn_rm) vfpr_tag_in.fpu_rnd_mode = fpu_rnd_mode_i; + // check if vfpr_tag_in.src_fmt or vfpr_tag_in.dst_fmt is acutually the alternate version // single-format float operations ignore fpu_fmt_mode_i.src // reason: for performance reasons when mixing expanding and non-expanding operations - if (src_fmt == fpnew_pkg::FP16 && fpu_fmt_mode_i.src == 1'b1) src_fmt = fpnew_pkg::FP16ALT; - if (dst_fmt == fpnew_pkg::FP16 && fpu_fmt_mode_i.dst == 1'b1) dst_fmt = fpnew_pkg::FP16ALT; - if (src_fmt == fpnew_pkg::FP8 && fpu_fmt_mode_i.src == 1'b1) src_fmt = fpnew_pkg::FP8ALT; - if (dst_fmt == fpnew_pkg::FP8 && fpu_fmt_mode_i.dst == 1'b1) dst_fmt = fpnew_pkg::FP8ALT; + if (vfpr_tag_in.src_fmt == fpnew_pkg::FP16 && fpu_fmt_mode_i.src == 1'b1) vfpr_tag_in.src_fmt = fpnew_pkg::FP16ALT; + if (vfpr_tag_in.dst_fmt == fpnew_pkg::FP16 && fpu_fmt_mode_i.dst == 1'b1) vfpr_tag_in.dst_fmt = fpnew_pkg::FP16ALT; + if (vfpr_tag_in.src_fmt == fpnew_pkg::FP8 && fpu_fmt_mode_i.src == 1'b1) vfpr_tag_in.src_fmt = fpnew_pkg::FP8ALT; + if (vfpr_tag_in.dst_fmt == fpnew_pkg::FP8 && fpu_fmt_mode_i.dst == 1'b1) vfpr_tag_in.dst_fmt = fpnew_pkg::FP8ALT; + end + + for (genvar i = 0; i < 3; i++) begin: gen_vfpr_op_ready + always_comb begin + unique case (vfpr_tag_in.op_select[i]) + None: begin + vfpr_op_ready[i] = 1'b1; + end + AccBus: begin + vfpr_op_ready[i] = acc_req_valid_q; + end + RegA, RegB, RegBRep, RegC, RegDest: begin + vfpr_op_ready[i] = ~sb_collision[i]; + end + default: begin + vfpr_op_ready[i] = 1'b1; + end + endcase + end end + // snitch_vfpr #( + // .DataWidth(DataWidth), + // .TCDMMemAddrWidth(TCDMMemAddrWidth), + // .tcdm_req_t(tcdm_req_t), + // .tcdm_rsp_t(tcdm_rsp_t), + // .mem_req_t(mem_req_t), + // .mem_rsp_t(mem_rsp_t), + // .tcdm_user_t(tcdm_user_t) + // ) i_vfpr ( + // .clk_i, + // .rst_i, + // .wr_req_i(data_req_i), + // .wr_rsp_o(data_rsp_o), + // .mem_req_o(mem_req_o), + // .mem_rsp_i(mem_rsp_i) + // ); + + logic [2:0][4:0] vfpr_rdata; + regaddr_t [2:0] reg_addrs; + assign reg_addrs[0] = vfpr_tag_in.fpr_raddr[0]; + assign reg_addrs[1] = vfpr_tag_in.fpr_raddr[1]; + assign reg_addrs[2] = vfpr_tag_in.fpr_raddr[2]; + snitch_vfpr #( .DataWidth(DataWidth), .TCDMMemAddrWidth(TCDMMemAddrWidth), @@ -2509,14 +2634,29 @@ module snitch_fp_ss import snitch_pkg::*; #( .tcdm_rsp_t(tcdm_rsp_t), .mem_req_t(mem_req_t), .mem_rsp_t(mem_rsp_t), - .tcdm_user_t(tcdm_user_t) + .tcdm_user_t(tcdm_user_t), + .tag_t(vfpr_tag_t) ) i_vfpr ( .clk_i, .rst_i, + .raddr_i(reg_addrs), + .ren_i({ + vfpr_tag_in.op_select[2] inside {RegA, RegB, RegBRep, RegC, RegDest}, + vfpr_tag_in.op_select[1] inside {RegA, RegB, RegBRep, RegC, RegDest}, + vfpr_tag_in.op_select[0] inside {RegA, RegB, RegBRep, RegC, RegDest} + }), + .rvalid_i(vfpr_in_valid), + .rready_o(vfpr_in_ready), + .rdata_o(vfpr_rdata), + .rvalid_o(vfpr_out_valid), + .rready_i(vfpr_out_ready), + .rtag_i(vfpr_tag_in), + .rtag_o(vfpr_tag_out), .wr_req_i(data_req_i), .wr_rsp_o(data_rsp_o), .mem_req_o(mem_req_o), - .mem_rsp_i(mem_rsp_i) + .mem_rsp_i(mem_rsp_i), + .vfpr_tracer_port(vfpr_tracer_port_o) ); snitch_regfile #( @@ -2527,7 +2667,7 @@ module snitch_fp_ss import snitch_pkg::*; #( .ADDR_WIDTH ( 5 ) ) i_ff_regfile ( .clk_i, - .raddr_i ( fpr_raddr ), + .raddr_i ( vfpr_tag_out.fpr_raddr ), .rdata_o ( fpr_rdata ), .waddr_i ( fpr_waddr ), .wdata_i ( fpr_wdata ), @@ -2538,63 +2678,49 @@ module snitch_fp_ss import snitch_pkg::*; #( // Operand Select // ---------------------- logic [2:0][FLEN-1:0] acc_qdata; - assign acc_qdata = {acc_req_q.data_argc, acc_req_q.data_argb, acc_req_q.data_arga}; + assign acc_qdata = {vfpr_tag_out.data_argc, vfpr_tag_out.data_argb, vfpr_tag_out.data_arga}; // Mux address lines as operands for the FPU can be mangled always_comb begin - fpr_raddr[0] = rs1; - fpr_raddr[1] = rs2; - fpr_raddr[2] = rs3; + vfpr_tag_in.fpr_raddr[0] = rs1; + vfpr_tag_in.fpr_raddr[1] = rs2; + vfpr_tag_in.fpr_raddr[2] = rs3; - unique case (op_select[1]) + unique case (vfpr_tag_in.op_select[1]) RegA: begin - fpr_raddr[1] = rs1; + vfpr_tag_in.fpr_raddr[1] = rs1; end default:; endcase - unique case (op_select[2]) + unique case (vfpr_tag_in.op_select[2]) RegB, RegBRep: begin - fpr_raddr[2] = rs2; + vfpr_tag_in.fpr_raddr[2] = rs2; end RegDest: begin - fpr_raddr[2] = rd; + vfpr_tag_in.fpr_raddr[2] = vfpr_tag_in.rd; end default:; endcase end for (genvar i = 0; i < 3; i++) begin: gen_operand_select - logic is_raddr_ssr; always_comb begin - is_raddr_ssr = 1'b0; - for (int s = 0; s < NumSsrs; s++) - is_raddr_ssr |= (SsrRegs[s] == fpr_raddr[i]); - end - always_comb begin - ssr_rvalid_o[i] = 1'b0; - unique case (op_select[i]) + unique case (vfpr_tag_out.op_select[i]) None: begin op[i] = '1; - op_ready[i] = 1'b1; end AccBus: begin op[i] = acc_qdata[i]; - op_ready[i] = acc_req_valid_q; end // Scoreboard or SSR RegA, RegB, RegBRep, RegC, RegDest: begin // map register 0 and 1 to SSRs - ssr_rvalid_o[i] = ssr_active_q & is_raddr_ssr; - op[i] = ssr_rvalid_o[i] ? ssr_rdata_i[i] : fpr_rdata[i]; - // the operand is ready if it is not marked in the scoreboard - // and in case of it being an SSR it need to be ready as well - // op_ready[i] = ~sb_q[fpr_raddr[i]] & (~ssr_rvalid_o[i] | ssr_rready_i[i]); - op_ready[i] = ~sb_collision[i] & (~ssr_rvalid_o[i] | ssr_rready_i[i]); + op[i] = fpr_rdata[i]; // Replicate if needed - if (op_select[i] == RegBRep) begin - unique case (src_fmt) + if (vfpr_tag_out.op_select[i] == RegBRep) begin + unique case (vfpr_tag_out.src_fmt) fpnew_pkg::FP32: op[i] = {(FLEN / 32){op[i][31:0]}}; fpnew_pkg::FP16, fpnew_pkg::FP16ALT: op[i] = {(FLEN / 16){op[i][15:0]}}; @@ -2606,7 +2732,6 @@ module snitch_fp_ss import snitch_pkg::*; #( end default: begin op[i] = '0; - op_ready[i] = 1'b1; end endcase end @@ -2633,13 +2758,13 @@ module snitch_fp_ss import snitch_pkg::*; #( .rst_ni ( ~rst_i ), .hart_id_i ( hart_id_i ), .operands_i ( op ), - .rnd_mode_i ( fpu_rnd_mode ), - .op_i ( fpu_op ), - .op_mod_i ( op_mode ), // Sign of operand? - .src_fmt_i ( src_fmt ), - .dst_fmt_i ( dst_fmt ), - .int_fmt_i ( int_fmt ), - .vectorial_op_i ( vectorial_op ), + .rnd_mode_i ( vfpr_tag_out.fpu_rnd_mode ), + .op_i ( vfpr_tag_out.fpu_op ), + .op_mod_i ( vfpr_tag_out.op_mode ), // Sign of operand? + .src_fmt_i ( vfpr_tag_out.src_fmt ), + .dst_fmt_i ( vfpr_tag_out.dst_fmt ), + .int_fmt_i ( vfpr_tag_out.int_fmt ), + .vectorial_op_i ( vfpr_tag_out.vectorial_op ), .tag_i ( fpu_tag_in ), .in_valid_i ( fpu_in_valid ), .in_ready_o ( fpu_in_ready ), @@ -2653,6 +2778,7 @@ module snitch_fp_ss import snitch_pkg::*; #( assign ssr_waddr_o = fpr_waddr; assign ssr_wdata_o = fpr_wdata; logic [63:0] nan_boxed_arga; + // this datapath bypasses vfpr assign nan_boxed_arga = {{32{1'b1}}, acc_req_q.data_arga[31:0]}; // Arbitrate Register File Write Port @@ -2666,13 +2792,19 @@ module snitch_fp_ss import snitch_pkg::*; #( ssr_wvalid_o = 1'b0; ssr_wdone_o = 1'b1; sb_pop_valid = 1'b0; + acc_dp_ready = '0; + fpr_wr_req.q_valid = 1'b0; // the accelerator master wants to write - if (acc_req_valid_q && result_select == ResAccBus) begin + if (acc_dp_valid) begin + acc_dp_ready = '1; fpr_we = 1'b1; // NaN-Box the value fpr_wdata = nan_boxed_arga[FLEN-1:0]; - fpr_waddr = rd; + fpr_wr_req.q.data = nan_boxed_arga[FLEN-1:0]; + fpr_waddr = vfpr_tag_in.rd; + fpr_wr_req.q.addr = vfpr_tag_in.rd; fpr_wvalid = 1'b1; + fpr_wr_req.q_valid = 1'b1; fpr_wready = 1'b0; end else if (fpu_out_valid && !fpu_tag_out.acc) begin fpr_we = 1'b1; @@ -2706,7 +2838,6 @@ module snitch_fp_ss import snitch_pkg::*; #( // ---------------------- // Load/Store Unit // ---------------------- - assign lsu_qvalid = acc_req_valid_q & (&op_ready) & (is_load | is_store) & dst_ready; snitch_lsu #( .AddrWidth (AddrWidth), @@ -2721,14 +2852,14 @@ module snitch_fp_ss import snitch_pkg::*; #( .clk_i (clk_i), .rst_i (rst_i), .lsu_qtag_i (lsu_tag_in), - .lsu_qwrite_i (is_store), + .lsu_qwrite_i (vfpr_tag_out.is_store), .lsu_qsigned_i (1'b1), // all floating point loads are signed - .lsu_qaddr_i (acc_req_q.data_argc[AddrWidth-1:0]), + .lsu_qaddr_i (vfpr_tag_out.data_argc[AddrWidth-1:0]), .lsu_qdata_i (op[1]), - .lsu_qsize_i (ls_size), + .lsu_qsize_i (vfpr_tag_out.ls_size), .lsu_qamo_i (reqrsp_pkg::AMONone), - .lsu_qvalid_i (lsu_qvalid), - .lsu_qready_o (lsu_qready), + .lsu_qvalid_i (lsu_in_valid), + .lsu_qready_o (lsu_in_ready), .lsu_pdata_o (ld_result), .lsu_ptag_o (lsu_tag_out), .lsu_perror_o (), // ignored for the moment @@ -2740,8 +2871,14 @@ module snitch_fp_ss import snitch_pkg::*; #( ); // SSRs - for (genvar i = 0; i < 3; i++) assign ssr_rdone_o[i] = ssr_rvalid_o[i] & acc_req_ready_q; - assign ssr_raddr_o = fpr_raddr; + for (genvar i = 0; i < 3; i++) begin + assign ssr_rdone_o[i] = '0; + assign ssr_rvalid_o[i] = '0; + end + assign ssr_raddr_o = '0; + assign ssr_wdata_o = '0; + assign ssr_wvalid_o = 1'b0; + assign ssr_wdone_o = 1'b1; // Counter pipeline. logic issue_fpu, issue_core_to_fpu, issue_fpu_seq; @@ -2761,30 +2898,30 @@ module snitch_fp_ss import snitch_pkg::*; #( assign trace_port_o.source = snitch_pkg::SrcFpu; assign trace_port_o.acc_q_hs = (acc_req_valid_q && acc_req_ready_q ); assign trace_port_o.fpu_out_hs = (fpu_out_valid && fpu_out_ready ); - assign trace_port_o.lsu_q_hs = (lsu_qvalid && lsu_qready ); + assign trace_port_o.lsu_q_hs = (lsu_in_valid && lsu_in_ready ); assign trace_port_o.op_in = acc_req_q.data_op; assign trace_port_o.rs1 = rs1; assign trace_port_o.rs2 = rs2; assign trace_port_o.rs3 = rs3; - assign trace_port_o.rd = rd; - assign trace_port_o.op_sel_0 = op_select[0]; - assign trace_port_o.op_sel_1 = op_select[1]; - assign trace_port_o.op_sel_2 = op_select[2]; - assign trace_port_o.src_fmt = src_fmt; - assign trace_port_o.dst_fmt = dst_fmt; - assign trace_port_o.int_fmt = int_fmt; + assign trace_port_o.rd = vfpr_tag_out.rd; + assign trace_port_o.op_sel_0 = vfpr_tag_out.op_select[0]; + assign trace_port_o.op_sel_1 = vfpr_tag_out.op_select[1]; + assign trace_port_o.op_sel_2 = vfpr_tag_out.op_select[2]; + assign trace_port_o.src_fmt = vfpr_tag_out.src_fmt; + assign trace_port_o.dst_fmt = vfpr_tag_out.dst_fmt; + assign trace_port_o.int_fmt = vfpr_tag_out.int_fmt; assign trace_port_o.acc_qdata_0 = acc_qdata[0]; assign trace_port_o.acc_qdata_1 = acc_qdata[1]; assign trace_port_o.acc_qdata_2 = acc_qdata[2]; assign trace_port_o.op_0 = op[0]; assign trace_port_o.op_1 = op[1]; assign trace_port_o.op_2 = op[2]; - assign trace_port_o.use_fpu = use_fpu; + assign trace_port_o.use_fpu = vfpr_tag_out.is_fpu; assign trace_port_o.fpu_in_rd = fpu_tag_in.rd; - assign trace_port_o.fpu_in_acc = fpu_tag_in.acc; - assign trace_port_o.ls_size = ls_size; - assign trace_port_o.is_load = is_load; - assign trace_port_o.is_store = is_store; + assign trace_port_o.fpu_in_acc = vfpr_tag_in.rd_is_acc; + assign trace_port_o.ls_size = vfpr_tag_out.ls_size; + assign trace_port_o.is_load = vfpr_tag_out.is_load; + assign trace_port_o.is_store = vfpr_tag_out.is_store; assign trace_port_o.lsu_qaddr = i_snitch_lsu.lsu_qaddr_i; assign trace_port_o.lsu_rd = lsu_tag_out.rd; assign trace_port_o.acc_wb_ready = (result_select == ResAccBus); diff --git a/hw/snitch_cluster/src/snitch_tcdm_router.sv b/hw/snitch_cluster/src/snitch_tcdm_router.sv index c63d1622a..6370831c4 100644 --- a/hw/snitch_cluster/src/snitch_tcdm_router.sv +++ b/hw/snitch_cluster/src/snitch_tcdm_router.sv @@ -143,29 +143,29 @@ module snitch_tcdm_router #( assign mst_rsp_o[i].p_valid = rsp_valid[i]; end - initial begin - $display("addr_width: %d, mem_coall: %d, ByteOffset: %d, SelWidth: %d", AddrWidth, MemCoallWidth, ByteOffset, SelWidth); - $display("mem_high_width: %d", $bits(mst_req_i[0].q.addr[AddrWidth-1:ByteOffset+MemCoallWidth+SelWidth])); - $display("mem_low_width: %d", $bits(mst_req_i[0].q.addr[ByteOffset+MemCoallWidth-1:0])); - $display("mst addr width: %d", $bits(mst_req_i[0].q.addr)); - $display("payload addr width: %d", $bits(payload_req_i[0].q.addr)); - end + // initial begin + // $display("addr_width: %d, mem_coall: %d, ByteOffset: %d, SelWidth: %d", AddrWidth, MemCoallWidth, ByteOffset, SelWidth); + // $display("mem_high_width: %d", $bits(mst_req_i[0].q.addr[AddrWidth-1:ByteOffset+MemCoallWidth+SelWidth])); + // $display("mem_low_width: %d", $bits(mst_req_i[0].q.addr[ByteOffset+MemCoallWidth-1:0])); + // $display("mst addr width: %d", $bits(mst_req_i[0].q.addr)); + // $display("payload addr width: %d", $bits(payload_req_i[0].q.addr)); + // end - always @(posedge clk_i) begin - // if a transactions is happening - if (|mst_req_q_valid_flat & |mst_rsp_q_ready_flat) begin - $write("router: "); - end - foreach (bank_select[i]) begin - if (mst_req_q_valid_flat[i] && mst_rsp_q_ready_flat[i]) begin - $write("[%2d:%x]->[%2d:%x] ", i, mst_req_i[i].q.addr, bank_select[i], payload_req_i[i].q.addr); - end - end - if (|mst_req_q_valid_flat & |mst_rsp_q_ready_flat) begin - $write("\n"); - end - if (|rsp_valid) begin - $display("- router: response: %b", rsp_valid); - end - end + // always @(posedge clk_i) begin + // // if a transactions is happening + // if (|mst_req_q_valid_flat & |mst_rsp_q_ready_flat) begin + // $write("router: "); + // end + // foreach (bank_select[i]) begin + // if (mst_req_q_valid_flat[i] && mst_rsp_q_ready_flat[i]) begin + // $write("[%2d:%x]->[%2d:%x] ", i, mst_req_i[i].q.addr, bank_select[i], payload_req_i[i].q.addr); + // end + // end + // if (|mst_req_q_valid_flat & |mst_rsp_q_ready_flat) begin + // $write("\n"); + // end + // if (|rsp_valid) begin + // $display("- router: response: %b", rsp_valid); + // end + // end endmodule diff --git a/hw/snitch_cluster/src/snitch_vfpr.sv b/hw/snitch_cluster/src/snitch_vfpr.sv index 38bec3d72..713af5883 100644 --- a/hw/snitch_cluster/src/snitch_vfpr.sv +++ b/hw/snitch_cluster/src/snitch_vfpr.sv @@ -1,22 +1,149 @@ -module snitch_vfpr #( +module snitch_vfpr import snitch_pkg::*; #( parameter int unsigned DataWidth = 0, parameter int unsigned TCDMMemAddrWidth = 0, parameter type tcdm_req_t = logic, parameter type tcdm_rsp_t = logic, parameter type tcdm_user_t = logic, parameter type mem_req_t = logic, - parameter type mem_rsp_t = logic + parameter type mem_rsp_t = logic, + parameter type tag_t = logic, + // derived parameters + parameter type addr_t = logic [TCDMMemAddrWidth-1:0], + parameter type data_t = logic [DataWidth-1:0] ) ( - input logic clk_i, - input logic rst_i, - input tcdm_req_t wr_req_i, - output tcdm_rsp_t wr_rsp_o, - output mem_req_t [3:0] mem_req_o, - input mem_rsp_t [3:0] mem_rsp_i + input logic clk_i, + input logic rst_i, + + // read port + input addr_t [2:0] raddr_i, + input logic [2:0] ren_i, + input logic rvalid_i, + output logic rready_o, + output data_t [2:0] rdata_o, + output logic rvalid_o, + input logic rready_i, + + // tag to propagate while reading + input tag_t rtag_i, + output tag_t rtag_o, + + // write port + input tcdm_req_t wr_req_i, + output tcdm_rsp_t wr_rsp_o, + + // memory port + output mem_req_t [3:0] mem_req_o, + input mem_rsp_t [3:0] mem_rsp_i, + output fpu_vfpr_trace_port_t vfpr_tracer_port ); + tcdm_req_t [3:0] vfpr_req; + tcdm_rsp_t [3:0] vfpr_rsp; + + logic [2:0] rvalid_fork, rready_fork; + logic [2:0] rrsp_valid, rrsp_ready; + + logic spill_valid, spill_ready; + logic spill_valid_q, spill_ready_q; + + logic [3:0] fork_out_valid, fork_out_ready; + assign fork_out_valid = {rvalid_fork, spill_valid}; + assign fork_out_ready = {rready_fork, spill_ready}; + + stream_fork #( + .N_OUP(4) + ) i_fork ( + .clk_i, + .rst_ni(~rst_i), + .valid_i(rvalid_i), + .ready_o(rready_o), + .valid_o({rvalid_fork, spill_valid}), + .ready_i({rready_fork, spill_ready}) + ); + + for (genvar i = 0; i < 3; i++) begin + logic ic_in_valid, ic_in_ready; + logic track_in_valid, track_in_ready; + + stream_fork #( + .N_OUP(2) + ) i_tcdm_bypass ( + .clk_i, + .rst_ni(~rst_i), + .valid_i(rvalid_fork[i]), + .ready_o(rready_fork[i]), + .valid_o({ic_in_valid, track_in_valid}), + .ready_i({ic_in_ready, track_in_ready}) + ); + + // bypass requires one cycle of delay to allow + // ic a change to execute memory request + logic track_out_valid, track_out_ready; + logic wait_for_tcdm_rsp; + spill_register i_track ( + .clk_i, + .rst_ni(~rst_i), + .valid_i(track_in_valid), + .ready_o(track_in_ready), + .data_i(ren_i[i]), + .valid_o(track_out_valid), + .ready_i(track_out_ready), + .data_o(wait_for_tcdm_rsp) + ); + + logic ic_in_en_valid, ic_in_en_ready; + stream_filter i_skip_ic ( + .valid_i(ic_in_valid), + .ready_o(ic_in_ready), + .drop_i(~ren_i[i]), + .valid_o(ic_in_en_valid), + .ready_i(ic_in_en_ready) + ); + + assign vfpr_req[i].q.addr = raddr_i[i]; + assign vfpr_req[i].q.write = '0; + assign vfpr_req[i].q.amo = reqrsp_pkg::AMONone; + assign vfpr_req[i].q.data = '0; + assign vfpr_req[i].q.strb = '1; + assign vfpr_req[i].q.user = '0; + assign vfpr_req[i].q_valid = ic_in_en_valid; + assign ic_in_en_ready = vfpr_rsp[i].q_ready; + + // buffer the interconnect output - necessary because + // the ic expects output to be always ready + logic ic_out_valid, ic_out_ready; + fall_through_register #( + .T(data_t) + ) i_rsp_buffer ( + .clk_i, + .rst_ni(~rst_i), + .clr_i('0), + .testmode_i('0), + .valid_i(vfpr_rsp[i].p_valid), + .ready_o(/* unused */), + .data_i(vfpr_rsp[i].p.data), + .valid_o(ic_out_valid), + .ready_i(ic_out_ready), + .data_o(rdata_o[i]) + ); + + + stream_merge #( + .N_INP(2) + ) i_rsp_join ( + .inp_valid_i({ic_out_valid, track_out_valid}), + .inp_ready_o({ic_out_ready, track_out_ready}), + .sel_i({wait_for_tcdm_rsp, 1'b1}), + .oup_valid_o(rrsp_valid[i]), + .oup_ready_i(rrsp_ready[i]) + ); + end + + assign vfpr_req[3] = wr_req_i; + assign wr_rsp_o = vfpr_rsp[3]; + snitch_tcdm_interconnect #( - .NumInp (1), + .NumInp (4), .NumOut (4), .tcdm_req_t(tcdm_req_t), .tcdm_rsp_t(tcdm_rsp_t), @@ -28,34 +155,78 @@ module snitch_vfpr #( ) i_vregfile ( .clk_i, .rst_ni(~rst_i), - .req_i(wr_req_i), - .rsp_o(wr_rsp_o), + .req_i(vfpr_req), + .rsp_o(vfpr_rsp), .mem_req_o(mem_req_o), .mem_rsp_i(mem_rsp_i) ); + // buffer the input tag + spill_register #( + .T(tag_t) + ) i_tag_buffer ( + .clk_i, + .rst_ni(~rst_i), + .valid_i(spill_valid), + .ready_o(spill_ready), + .data_i(rtag_i), + .valid_o(spill_valid_q), + .ready_i(spill_ready_q), + .data_o(rtag_o) + ); + + // wait for all streams to complete + stream_join #( + .N_INP(4) + ) i_join ( + .inp_valid_i({rrsp_valid, spill_valid_q}), + .inp_ready_o({rrsp_ready, spill_ready_q}), + .oup_valid_o(rvalid_o), + .oup_ready_i(rready_i) + ); + initial begin $display("vfpr mem addr width %d, data width %d", TCDMMemAddrWidth, DataWidth); $display("mem req addr width: %d", $bits(mem_req_o[0].q.addr)); end - always @(posedge clk_i) begin - // if a transactions is happening - if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[0].q_valid) begin - $display("- ic: [%x]->[0:%x]", wr_req_i.q.addr, mem_req_o[0].q.addr); - end - if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[1].q_valid) begin - $display("- ic: [%x]->[1:%x]", wr_req_i.q.addr, mem_req_o[1].q.addr); - end - if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[2].q_valid) begin - $display("- ic: [%x]->[2:%x]", wr_req_i.q.addr, mem_req_o[2].q.addr); - end - if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[3].q_valid) begin - $display("- ic: [%x]->[3:%x]", wr_req_i.q.addr, mem_req_o[3].q.addr); - end - if (wr_rsp_o.p_valid) begin - $display("- ic response data:", wr_rsp_o.p.data); - end - end + // always @(posedge clk_i) begin + // // if a transactions is happening + // if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[0].q_valid) begin + // $display("- ic: [%x]->[0:%x]", wr_req_i.q.addr, mem_req_o[0].q.addr); + // end + // if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[1].q_valid) begin + // $display("- ic: [%x]->[1:%x]", wr_req_i.q.addr, mem_req_o[1].q.addr); + // end + // if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[2].q_valid) begin + // $display("- ic: [%x]->[2:%x]", wr_req_i.q.addr, mem_req_o[2].q.addr); + // end + // if (wr_req_i.q_valid & wr_rsp_o.q_ready & mem_req_o[3].q_valid) begin + // $display("- ic: [%x]->[3:%x]", wr_req_i.q.addr, mem_req_o[3].q.addr); + // end + // if (wr_rsp_o.p_valid) begin + // $display("- ic response data:", wr_rsp_o.p.data); + // end + // if (spill_valid != rvalid_o) begin + // $display("tag spill valid state does not match ic state: %b!=%b", spill_valid, rvalid_o); + // end + // if (spill_ready != rready_o) begin + // $display("tag spill ready state does not match ic state: %b!=%b", spill_ready, rready_o); + // end + // end + + assign vfpr_tracer_port.source = SrcFpuVFPR; + assign vfpr_tracer_port.read = rvalid_i & rready_o; + assign vfpr_tracer_port.read_result = {vfpr_rsp[0].p_valid, vfpr_rsp[1].p_valid, vfpr_rsp[2].p_valid}; + assign vfpr_tracer_port.reg0 = raddr_i[0]; + assign vfpr_tracer_port.reg1 = raddr_i[1]; + assign vfpr_tracer_port.reg2 = raddr_i[2]; + assign vfpr_tracer_port.reg_enabled = ren_i; + assign vfpr_tracer_port.data0 = rdata_o[0]; + assign vfpr_tracer_port.data1 = rdata_o[1]; + assign vfpr_tracer_port.data2 = rdata_o[2]; + assign vfpr_tracer_port.write = wr_req_i.q_valid & wr_rsp_o.q_ready; + assign vfpr_tracer_port.wr_addr = wr_req_i.q.addr; + assign vfpr_tracer_port.wr_data = wr_req_i.q.data; endmodule \ No newline at end of file diff --git a/hw/snitch_cluster/src/stream_merge.sv b/hw/snitch_cluster/src/stream_merge.sv new file mode 100644 index 000000000..166ed8a6f --- /dev/null +++ b/hw/snitch_cluster/src/stream_merge.sv @@ -0,0 +1,23 @@ +module stream_merge #( + /// Number of input streams + parameter int unsigned N_INP = 32'd0 // Synopsys DC requires a default value for parameters. +) ( + /// Input streams valid handshakes + input logic [N_INP-1:0] inp_valid_i, + /// Input streams ready handshakes + output logic [N_INP-1:0] inp_ready_o, + /// Selection mask for the output handshake + input logic [N_INP-1:0] sel_i, + /// Output stream valid handshake + output logic oup_valid_o, + /// Output stream ready handshake + input logic oup_ready_i +); + + // Corner case when `sel_i` is all 0s should not generate valid + assign oup_valid_o = &(inp_valid_i | ~sel_i) && |sel_i; + for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready + assign inp_ready_o[i] = oup_valid_o & oup_ready_i & sel_i[i]; + end + +endmodule \ No newline at end of file diff --git a/hw/snitch_cluster/src/stream_stall.sv b/hw/snitch_cluster/src/stream_stall.sv new file mode 100644 index 000000000..bddeea823 --- /dev/null +++ b/hw/snitch_cluster/src/stream_stall.sv @@ -0,0 +1,16 @@ +module stream_stall ( + input logic valid_i, + output logic ready_o, + input logic stall, + output logic valid_o, + input logic ready_i +); + always_comb begin + valid_o = valid_i; + ready_o = ready_i; + if (stall) begin + valid_o = 0; + ready_o = 0; + end + end +endmodule \ No newline at end of file diff --git a/target/snitch_cluster/Makefile b/target/snitch_cluster/Makefile index 3470a444c..a2bf977c3 100644 --- a/target/snitch_cluster/Makefile +++ b/target/snitch_cluster/Makefile @@ -79,6 +79,7 @@ VLOG_FLAGS += -suppress 13314 VLOG_FLAGS += ${VLOG_64BIT} VLT_FLAGS += --trace +VLT_FLAGS += --trace-structs ############### # C testbench # diff --git a/util/trace/gen_trace.py b/util/trace/gen_trace.py index fff73870b..44ab02ab5 100755 --- a/util/trace/gen_trace.py +++ b/util/trace/gen_trace.py @@ -53,7 +53,7 @@ for i in range(2, 12)), *('ft{}'.format(i) for i in range(8, 12))) -TRACE_SRCES = {'snitch': 0, 'fpu': 1, 'sequencer': 2, 'scoreboard': 3} +TRACE_SRCES = {'snitch': 0, 'fpu': 1, 'sequencer': 2, 'scoreboard': 3, 'vfpr': 4} LS_SIZES = ('Byte', 'Half', 'Word', 'Doub') @@ -683,7 +683,24 @@ def annotate_insn( else: insn, pc_str, annot = ('', '', '') elif extras['source'] == TRACE_SRCES['scoreboard']: - annot = '' + annot_list = [] + if extras['push_valid_i'] == 1: + annot_list.append(f'tracking 0x{extras["push_rd_addr_i"]:x} -> 0x{extras["entry_index_o"]:x}') + if extras['pop_valid_i'] == 1: + annot_list.append(f'releasing 0x{extras["pop_index_i"]:x}') + annot_list = ', '.join(annot_list); + annot = f'(sb) {annot_list}' + elif extras['source'] == TRACE_SRCES['vfpr']: + annot_list = [] + if extras['read'] == 1: + all_regs = [extras['reg0'], extras['reg1'], extras['reg2']] + regs = [r for i, r in enumerate(all_regs) if extras['reg_enabled'] & (0b1 << i) == (0b1 << i)] + if len(regs) > 0: + annot_list.append(f'reading {regs}') + if extras['write'] == 1: + annot_list.append(f'wr/tcdm to 0x{extras["wr_addr"]:x}') + annot_list = ', '.join(annot_list); + annot = f'(vfpr) {annot_list}' # Annotate FPSS elif extras['source'] == TRACE_SRCES['fpu']: annot_list = []