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  • ICer in Southeast University
  • WuHan

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out-of-order55/README.md

My github stats

⚡ 我的技术栈 | My Tech Stack

  • systemverilog verilog chisel c python

  • verilator quartus vivado vcs

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  1. booth-multiplier booth-multiplier Public

    基4booth乘法器设计与验证

    VHDL 9

  2. DCache DCache Public

    2 way|PLRU|2*4k

    SystemVerilog 5

  3. SRT-Divider SRT-Divider Public

    简单的未优化的SRT除法器

    Verilog 6

  4. cache-sim cache-sim Public

    一个可配置的cachesim

    C 1

  5. ysyx-question ysyx-question Public

    一生一芯必答题

    1

  6. prefetcher-sim prefetcher-sim Public

    A sim has l1 and l2 cache

    Python 2