From 9248e27ac5199f3dc7af4869dcec46533ae7eb39 Mon Sep 17 00:00:00 2001 From: wanda-phi <145241585+wanda-phi@users.noreply.github.com> Date: Tue, 1 Oct 2024 23:24:16 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=207d631?= =?UTF-8?q?ac7a812c0aecde81b42ba840f4e6cf579e4=20=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- _sources/xilinx/virtex5/cmt.rst.txt | 23 + _sources/xilinx/virtex5/index.rst.txt | 1 + _sources/xilinx/virtex6/cmt.rst.txt | 26 + _sources/xilinx/virtex6/index.rst.txt | 1 + _sources/xilinx/virtex7/center.rst.txt | 20 + _sources/xilinx/virtex7/cmt.rst.txt | 20 + _sources/xilinx/virtex7/config.rst.txt | 82 + _sources/xilinx/virtex7/index.rst.txt | 2 + _sources/xilinx/virtex7/io.rst.txt | 14 + objects.inv | Bin 2927 -> 2973 bytes searchindex.js | 2 +- xilinx/index.html | 4 + xilinx/spartan3/dcm-s3.html | 64 +- xilinx/spartan3/dcm-s3e.html | 432 +- xilinx/spartan6/dcm.html | 108 +- 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xilinx/virtex7/config.html diff --git a/_sources/xilinx/virtex5/cmt.rst.txt b/_sources/xilinx/virtex5/cmt.rst.txt new file mode 100644 index 00000000..244b4523 --- /dev/null +++ b/_sources/xilinx/virtex5/cmt.rst.txt @@ -0,0 +1,23 @@ +.. _virtex5-cmt: + +Clock management tile +##################### + +.. todo:: describe this madness + + +``CMT`` +======= + +.. raw:: html + :file: ../gen/tile-xc5v-CMT.html + + +Tables +====== + +.. raw:: html + :file: ../gen/xc5v-pll-filter.html + +.. raw:: html + :file: ../gen/xc5v-pll-in-dly-set.html diff --git a/_sources/xilinx/virtex5/index.rst.txt b/_sources/xilinx/virtex5/index.rst.txt index b75a323b..1d9f3323 100644 --- a/_sources/xilinx/virtex5/index.rst.txt +++ b/_sources/xilinx/virtex5/index.rst.txt @@ -15,6 +15,7 @@ Virtex 5 io center clock + cmt ppc emac pcie diff --git a/_sources/xilinx/virtex6/cmt.rst.txt b/_sources/xilinx/virtex6/cmt.rst.txt new file mode 100644 index 00000000..cdc3a8e6 --- /dev/null +++ b/_sources/xilinx/virtex6/cmt.rst.txt @@ -0,0 +1,26 @@ +.. _virtex6-cmt: + +Clock management tile +##################### + +.. todo:: describe this madness + + +``CMT`` +======= + +.. raw:: html + :file: ../gen/tile-xc6v-CMT.html + + +Tables +====== + +.. raw:: html + :file: ../gen/xc6v-mmcm-filter.html + +.. raw:: html + :file: ../gen/xc6v-mmcm-lock.html + +.. raw:: html + :file: ../gen/xc6v-mmcm-in-dly-set.html diff --git a/_sources/xilinx/virtex6/index.rst.txt b/_sources/xilinx/virtex6/index.rst.txt index 46d9f3cb..bac1771b 100644 --- a/_sources/xilinx/virtex6/index.rst.txt +++ b/_sources/xilinx/virtex6/index.rst.txt @@ -15,6 +15,7 @@ Virtex 6 io center clock + cmt emac pcie gtx diff --git a/_sources/xilinx/virtex7/center.rst.txt b/_sources/xilinx/virtex7/center.rst.txt new file mode 100644 index 00000000..7d59a71f --- /dev/null +++ b/_sources/xilinx/virtex7/center.rst.txt @@ -0,0 +1,20 @@ +.. _virtex7-center: + +Configuration Center +#################### + +.. todo:: document + + +Bitstream +========= + +.. raw:: html + :file: ../gen/tile-xc7v-CFG.html + + +XADC +==== + +.. raw:: html + :file: ../gen/tile-xc7v-XADC.html diff --git a/_sources/xilinx/virtex7/cmt.rst.txt b/_sources/xilinx/virtex7/cmt.rst.txt index 2700fef0..746fcd4f 100644 --- a/_sources/xilinx/virtex7/cmt.rst.txt +++ b/_sources/xilinx/virtex7/cmt.rst.txt @@ -18,3 +18,23 @@ Clock management tile .. raw:: html :file: ../gen/tile-xc7v-CMT_FIFO.html + + +MMCM Tables +=========== + +.. raw:: html + :file: ../gen/xc7v-mmcm-filter.html + +.. raw:: html + :file: ../gen/xc7v-mmcm-lock.html + + +PLL Tables +========== + +.. raw:: html + :file: ../gen/xc7v-pll-filter.html + +.. raw:: html + :file: ../gen/xc7v-pll-lock.html diff --git a/_sources/xilinx/virtex7/config.rst.txt b/_sources/xilinx/virtex7/config.rst.txt new file mode 100644 index 00000000..cba0280b --- /dev/null +++ b/_sources/xilinx/virtex7/config.rst.txt @@ -0,0 +1,82 @@ +.. _virtex7-config: + +Configuration registers +####################### + +.. todo:: document + +``COR`` +======= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.COR.html + + +``COR1`` +======== + +.. raw:: html + :file: ../gen/tile-xc7v-REG.COR1.html + + +``CTL`` +======= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.CTL.html + + +``CTL1`` +======== + +.. raw:: html + :file: ../gen/tile-xc7v-REG.CTL1.html + + +``BSPI`` +======== + +.. raw:: html + :file: ../gen/tile-xc7v-REG.BSPI.html + + +``WBSTAR`` +========== + +.. raw:: html + :file: ../gen/tile-xc7v-REG.WBSTAR.html + + +``TIMER`` +========= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.TIMER.html + + +``TESTMODE`` +============ + +.. raw:: html + :file: ../gen/tile-xc7v-REG.TESTMODE.html + + +``TRIM0`` +========= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.TRIM0.html + + +``TRIM1`` +========= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.TRIM1.html + + +``TRIM2`` +========= + +.. raw:: html + :file: ../gen/tile-xc7v-REG.TRIM2.html diff --git a/_sources/xilinx/virtex7/index.rst.txt b/_sources/xilinx/virtex7/index.rst.txt index 0d4d5091..9d14ffc9 100644 --- a/_sources/xilinx/virtex7/index.rst.txt +++ b/_sources/xilinx/virtex7/index.rst.txt @@ -13,7 +13,9 @@ Virtex 7 bram dsp io + center clock cmt pcie pcie3 + config diff --git a/_sources/xilinx/virtex7/io.rst.txt b/_sources/xilinx/virtex7/io.rst.txt index a5b3351e..b52be6c9 100644 --- a/_sources/xilinx/virtex7/io.rst.txt +++ b/_sources/xilinx/virtex7/io.rst.txt @@ -178,3 +178,17 @@ The devices also have dedicated configuration bank 0, which has no user I/O and - ``M0``, ``M1``, ``M2`` - ``PROGRAM_B`` - ``TCK``, ``TDI``, ``TDO``, ``TMS`` + + +Bitstream — ``HCLK_IOI_HP`` +=========================== + +.. raw:: html + :file: ../gen/tile-xc7v-HCLK_IOI_HP.html + + +Bitstream — ``HCLK_IOI_HR`` +=========================== + +.. raw:: html + :file: ../gen/tile-xc7v-HCLK_IOI_HR.html diff --git a/objects.inv b/objects.inv index c6acacf4160a7e16684113528fa5856d85d46ec3..40f16dc35ba6ccb8d99a29901adecfa0bfc3a208 100644 GIT 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"bitstream-geometry"], [144, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [155, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [127, "bitstream-clbll"], [140, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [127, "bitstream-clblm"], [140, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_IOI": [[137, "bitstream-hclk-ioi"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[121, "bitstream-intf"], [136, "bitstream-intf"], [146, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[146, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[121, "bitstream-intf-delay"], [136, "bitstream-intf-delay"], [146, "bitstream-intf-delay"]], "Bitstream \u2014 IO": [[137, "bitstream-io"]], "Bitstream \u2014 IOI tile": [[68, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[55, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[55, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[61, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[61, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[61, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[61, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[61, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PowerPC hole tiles": [[91, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[61, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[38, "bitstream-bottom-tiles"], [47, "bitstream-bottom-tiles"], [83, "bitstream-bottom-tiles"]], "Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [125, "block-ram"], [139, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [156, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [166, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [154, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[154, "clkh"]], "CLKL": [[80, "clkl"], [154, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [154, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [154, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[154, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_BALI_REBUF": [[141, "clk-bali-rebuf"]], "CLK_BUFG": [[141, "clk-bufg"]], "CLK_BUFG_REBUF": [[141, "clk-bufg-rebuf"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"], [141, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CMT": [[142, "cmt"]], "CMT_BUFG_BOT": [[128, "cmt-bufg-bot"]], "CMT_BUFG_TOP": [[128, "cmt-bufg-top"]], "CMT_FIFO": [[142, "cmt-fifo"]], "CNR.BL": [[76, "cnr-bl"], [151, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [151, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [151, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [151, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [114, "cor"], [129, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [114, "cor1"], [129, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [114, "ctl"], [129, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[129, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [117, "center-column"], [132, "center-column"]], "Center column and configuration center": [[144, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"], [128, "clock-interconnect"], [141, "clock-interconnect"]], "Clock management tile": [[142, "clock-management-tile"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [127, "configurable-logic-block"], [140, "configurable-logic-block"], [150, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [126, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [114, "configuration-registers"], [129, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [120, null], [135, null], [145, null], [152, null], [163, null], [164, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [151, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [115, "dsp"], [130, "dsp"], [143, "dsp"]], "Database schema": [[17, "database-schema"], [156, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [163, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [156, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [117, "device-geometry"], [132, "device-geometry"], [144, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [165, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [167, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [165, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [117, "ecc"], [132, "ecc"], [144, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[116, "ethernet-macs"], [131, "ethernet-macs"]], "FB columns and rows": [[167, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[167, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[155, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[155, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[155, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [155, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[155, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTH transceivers": [[133, "gth-transceivers"]], "GTP and GTX right column holes": [[144, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[118, "gtp-transceivers"]], "GTX transceivers": [[119, "gtx-transceivers"], [134, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [117, "general-structure"], [132, "general-structure"], [144, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [157, "global-bits"], [158, "global-bits"], [159, "global-bits"], [160, "global-bits"], [161, "global-bits"], [162, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [128, "hclk"], [141, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [122, "i-o-banks-and-special-functions"], [137, "i-o-banks-and-special-functions"], [147, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [157, "i-o-pins"], [158, "i-o-pins"], [159, "i-o-pins"], [160, "i-o-pins"], [161, "i-o-pins"], [162, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [166, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [157, "imux-bits"], [158, "imux-bits"], [159, "imux-bits"], [160, "imux-bits"], [161, "imux-bits"], [162, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[144, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [153, "io-b"]], "IO.L": [[79, "io-l"], [153, "io-l"]], "IO.R": [[79, "io-r"], [153, "io-r"]], "IO.T": [[79, "io-t"], [153, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [166, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [166, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [122, "input-output"], [137, "input-output"], [147, "input-output"], [153, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [167, "input-output-buffer"]], "Interconnect": [[121, "interconnect"], [136, "interconnect"], [146, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [165, "introduction"]], "JED bits": [[156, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [155, "jed-mapping"], [157, "jed-mapping"], [158, "jed-mapping"], [159, "jed-mapping"], [160, "jed-mapping"], [161, "jed-mapping"], [162, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[155, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[155, "jed-mapping-macrocells-without-iob"]], "JED structure": [[155, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [166, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[167, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [167, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[144, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [167, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [167, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[148, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[149, "pci-express-gen3-cores"]], "PCI Express cores": [[123, "pci-express-cores"], [138, "pci-express-cores"]], "PCI Express holes": [[144, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[148, "pcie-l"]], "PCIE_R": [[148, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[128, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [165, "packages"]], "Part": [[17, "part"], [156, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[124, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [117, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[144, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [167, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [166, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [167, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [156, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [157, "speed-data"], [158, "speed-data"], [159, "speed-data"], [160, "speed-data"], [161, "speed-data"], [162, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [117, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[154, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[167, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [129, "testmode"]], "TIMER": [[62, "timer"], [114, "timer"], [129, "timer"]], "TRIM": [[129, "trim"]], "Tables": [[71, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[81, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[81, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[83, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [156, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [38, "id2"], [38, "id3"], [38, "id4"], [38, "id5"], [38, "id6"], [38, "id7"], [38, "id8"], [39, "id1"], [40, "id1"], [40, "id2"], [40, "id3"], [40, "id4"], [40, "id5"], [41, "id1"], [43, "id1"], [43, "id2"], [43, "id3"], [46, "id1"], [47, "id1"], [47, "id2"], [47, "id3"], [47, "id4"], [47, "id5"], [47, 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"9985": [45, 59, 81, 96, 110, 125, 139], "9986": [45, 59, 81, 96, 110, 125, 139], "9987": [45, 59, 81, 96, 110, 125, 139], "9988": [45, 59, 81, 96, 110, 125, 139], "9989": [45, 59, 81, 96, 110, 125, 139], "999": [45, 59, 72, 81, 96, 110, 125, 139], "9990": [45, 59, 81, 96, 110, 125, 139], "9991": [45, 59, 81, 96, 110, 125, 139], "9992": [45, 59, 81, 96, 110, 125, 139], "9993": [45, 59, 81, 96, 110, 125, 139], "9994": [45, 59, 81, 96, 110, 125, 139], "9995": [45, 59, 81, 96, 110, 125, 139], "9996": [45, 59, 81, 96, 110, 125, 139], "9997": [45, 59, 81, 96, 110, 125, 139], "9998": [45, 59, 81, 96, 110, 125, 139], "9999": [45, 59, 81, 96, 110, 125, 139], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 155, "9fb_group": [157, 158, 159, 160, 161, 162], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 155, "9reg_d_ireg": 155, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 123, 126, 142, 148, 149], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 116, 124, 131, 138, 141], "9rowcolumn01234567891011121314151617181920212223242526272829": [133, 134, 148], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [118, 119], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 117, 122, 132, 137, 144, 147, 156, 167], "AED": [12, 165], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 167], "As": [35, 132, 167], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 117, 132, 144, 167], "ISE": [35, 167], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 117, 132, 137, 144, 167], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 117, 122, 132, 137, 144, 147, 167], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 117, 132, 137, 144, 147, 156, 165, 167], "Its": [35, 81], "No": 144, "Not": [15, 16, 36, 55, 91, 167], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 144, 167], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 165, 166, 167], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 117, 132, 137, 144, 147], "These": [36, 91, 137, 144], "To": [35, 36, 96], "_": [17, 34, 36, 156, 167], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 155, 167], "_gclk": 167, "_init": [46, 82], "_inv": [36, 167], "_lct": 167, "_mc": [12, 165], "_mux": [36, 46, 82], "_none": 167, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a17": [6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a18": [6, 7, 22, 23, 24, 25, 160, 161, 162], "a19": [6, 7, 22, 23, 24, 25, 160, 161, 162], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a20": [6, 7, 22, 23, 24, 161, 162], "a21": [6, 7, 22, 23, 161, 162], "a22": [6, 7, 22, 23, 161, 162], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a5ffinit": [127, 140], "a5ffinitslice0": [127, 140], "a5ffmux": [127, 140], "a5ffsr": [127, 140], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 127, "a5q0": 60, "a5q0100": [60, 127, 140], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a6lut": [60, 112, 127, 140], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a_dfeclkdlyadj": 134, "a_dfedlyovrd": 134, "a_dfedlyovrdgtx0": 134, "a_dfedlyovrdgtx1": 134, "a_dfedlyovrdgtx2": 134, "a_dfedlyovrdgtx3": 134, "a_dfetap1": 134, "a_dfetap2": 134, "a_dfetap3": 134, "a_dfetap4": 134, "a_dfetapovrd": 134, "a_dfetapovrdgtx0": 134, "a_dfetapovrdgtx1": 134, "a_dfetapovrdgtx2": 134, "a_dfetapovrdgtx3": 134, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 134, "a_gtxrxresetgtx0": 134, "a_gtxrxresetgtx1": 134, "a_gtxrxresetgtx2": 134, "a_gtxrxresetgtx3": 134, "a_gtxtxreset": 134, "a_gtxtxresetgtx0": 134, "a_gtxtxresetgtx1": 134, "a_gtxtxresetgtx2": 134, "a_gtxtxresetgtx3": 134, "a_input": [115, 130, 143], "a_loopback": 134, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 134, "a_pllclkrxresetgtx0": 134, "a_pllclkrxresetgtx1": 134, "a_pllclkrxresetgtx2": 134, "a_pllclkrxresetgtx3": 134, "a_pllclktxreset": 134, "a_pllclktxresetgtx0": 134, "a_pllclktxresetgtx1": 134, "a_pllclktxresetgtx2": 134, "a_pllclktxresetgtx3": 134, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 134, "a_pllrxresetgtx0": 134, "a_pllrxresetgtx1": 134, "a_pllrxresetgtx2": 134, "a_pllrxresetgtx3": 134, "a_plltxreset": 134, "a_plltxresetgtx0": 134, "a_plltxresetgtx1": 134, "a_plltxresetgtx2": 134, "a_plltxresetgtx3": 134, "a_prbscntreset": 134, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 134, "a_prbscntresetgtx1": 134, "a_prbscntresetgtx2": 134, "a_prbscntresetgtx3": 134, "a_q": 81, "a_rxbufreset": 134, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 134, "a_rxbufresetgtx1": 134, "a_rxbufresetgtx2": 134, "a_rxbufresetgtx3": 134, "a_rxcdrfreqreset": 134, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 134, "a_rxcdrfreqresetgtx1": 134, "a_rxcdrfreqresetgtx2": 134, "a_rxcdrfreqresetgtx3": 134, "a_rxcdrhold": 134, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 134, "a_rxcdrholdgtx1": 134, "a_rxcdrholdgtx2": 134, "a_rxcdrholdgtx3": 134, "a_rxcdrphasereset": 134, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 134, "a_rxcdrphaseresetgtx1": 134, "a_rxcdrphaseresetgtx2": 134, "a_rxcdrphaseresetgtx3": 134, "a_rxcdrreset": 134, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 134, "a_rxcdrresetgtx1": 134, "a_rxcdrresetgtx2": 134, "a_rxcdrresetgtx3": 134, "a_rxdfereset": 134, "a_rxdferesetgtx0": 134, "a_rxdferesetgtx1": 134, "a_rxdferesetgtx2": 134, "a_rxdferesetgtx3": 134, "a_rxenpmaphasealign": 134, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 134, "a_rxenpmaphasealigngtx1": 134, "a_rxenpmaphasealigngtx2": 134, "a_rxenpmaphasealigngtx3": 134, "a_rxenprbstst": 134, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 134, "a_rxensamplealigngtx0": 134, "a_rxensamplealigngtx1": 134, "a_rxensamplealigngtx2": 134, "a_rxensamplealigngtx3": 134, "a_rxeqmix": 134, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 134, "a_rxplllkdetengtx0": 134, "a_rxplllkdetengtx1": 134, "a_rxplllkdetengtx2": 134, "a_rxplllkdetengtx3": 134, "a_rxpllpowerdown": 134, "a_rxpllpowerdowngtx0": 134, "a_rxpllpowerdowngtx1": 134, "a_rxpllpowerdowngtx2": 134, "a_rxpllpowerdowngtx3": 134, "a_rxpmasetphas": 134, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 134, "a_rxpmasetphasegtx1": 134, "a_rxpmasetphasegtx2": 134, "a_rxpmasetphasegtx3": 134, "a_rxpolar": 134, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 134, "a_rxpolaritygtx1": 134, "a_rxpolaritygtx2": 134, "a_rxpolaritygtx3": 134, "a_rxpowerdown": 134, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 134, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 134, "a_rxresetgtx1": 134, "a_rxresetgtx2": 134, "a_rxresetgtx3": 134, "a_txbufdiffctrl": 134, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 134, "a_txdeemphgtx0": 134, "a_txdeemphgtx1": 134, "a_txdeemphgtx2": 134, "a_txdeemphgtx3": 134, "a_txdiffctrl": 134, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 134, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 134, "a_txelecidlegtx1": 134, "a_txelecidlegtx2": 134, "a_txelecidlegtx3": 134, "a_txenpmaphasealign": 134, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 134, "a_txenpmaphasealigngtx1": 134, "a_txenpmaphasealigngtx2": 134, "a_txenpmaphasealigngtx3": 134, "a_txenprbstst": 134, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 134, "a_txplllkdeten": 134, "a_txplllkdetengtx0": 134, "a_txplllkdetengtx1": 134, "a_txplllkdetengtx2": 134, "a_txplllkdetengtx3": 134, "a_txpllpowerdown": 134, "a_txpllpowerdowngtx0": 134, "a_txpllpowerdowngtx1": 134, "a_txpllpowerdowngtx2": 134, "a_txpllpowerdowngtx3": 134, "a_txpmasetphas": 134, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 134, "a_txpmasetphasegtx1": 134, "a_txpmasetphasegtx2": 134, "a_txpmasetphasegtx3": 134, "a_txpolar": 134, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 134, "a_txpolaritygtx1": 134, "a_txpolaritygtx2": 134, "a_txpolaritygtx3": 134, "a_txpostemphasi": 134, "a_txpowerdown": 134, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 134, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 134, "a_txprbsforceerrgtx1": 134, "a_txprbsforceerrgtx2": 134, "a_txprbsforceerrgtx3": 134, "a_txpreemphasi": 134, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 134, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 134, "a_txresetgtx1": 134, "a_txresetgtx2": 134, "a_txresetgtx3": 134, "a_txsw": 134, "a_txswinggtx0": 134, "a_txswinggtx1": 134, "a_txswinggtx2": 134, "a_txswinggtx3": 134, "aa1": [6, 7, 22, 23, 161, 162], "aa10": [6, 7, 161, 162], "aa11": [6, 7, 161, 162], "aa12": [6, 7, 161, 162], "aa13": [6, 7, 161, 162], "aa14": [6, 7, 161, 162], "aa15": [6, 7, 161, 162], "aa16": [6, 7, 161, 162], "aa17": [6, 7, 161, 162], "aa18": [6, 7, 161, 162], "aa19": [6, 7, 161, 162], "aa2": [6, 7, 22, 23, 161, 162], "aa20": [6, 7, 161, 162], "aa21": [6, 7, 161, 162], "aa22": [6, 7, 161, 162], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 161, 162], "aa4": [6, 7, 22, 23, 161, 162], "aa5": [6, 7, 161, 162], "aa6": [6, 7, 161, 162], "aa7": [6, 7, 161, 162], "aa8": [6, 7, 161, 162], "aa9": [6, 7, 161, 162], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 161, 162], "ab10": [6, 7, 161, 162], "ab11": [6, 7, 161, 162], "ab12": [6, 7, 161, 162], "ab13": [6, 7, 161, 162], "ab14": [6, 7, 161, 162], "ab15": [6, 7, 161, 162], "ab16": [6, 7, 161, 162], "ab17": [6, 7, 161, 162], "ab18": [6, 7, 161, 162], "ab19": [6, 7, 161, 162], "ab2": [6, 7, 22, 23, 161, 162], "ab20": [6, 7, 161, 162], "ab21": [6, 7, 161, 162], "ab22": [6, 7, 161, 162], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 161, 162], "ab4": [6, 7, 22, 23, 161, 162], "ab5": [6, 7, 161, 162], "ab6": [6, 7, 161, 162], "ab7": [6, 7, 161, 162], "ab8": [6, 7, 161, 162], "ab9": [6, 7, 161, 162], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 132, 144, 147, 167], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 156, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 134, "ac_cap_dis_0": [66, 118, 119], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 118, "ac_cap_dis_0gtx_du": 119, "ac_cap_dis_1": [66, 118, 119], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 118, "ac_cap_dis_1gtx_du": 119, "ac_cap_disgtx0": 134, "ac_cap_disgtx1": 134, "ac_cap_disgtx2": 134, "ac_cap_disgtx3": 134, "acb": [12, 34, 165], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 165, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 117, 132, 144, 147, 156, 165, 167], "activ": [35, 36, 46, 82, 166], "activelanesin": 123, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 117, 132, 144, 167], "acy0": [60, 112, 127, 140], "acy0slice0": [112, 127, 140], "acy0slice1": [60, 127], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 117, 132, 144, 167], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 117, 132], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 72, "addr_cascade_out_a": 139, "addr_cascade_out_abram": 139, "addr_cascade_out_b": 139, "addr_cascade_out_bbram": 139, "addra0": 72, "addra1": 72, "addra10": 72, "addra11": 72, "addra2": 72, "addra3": 72, "addra4": 72, "addra5": 72, "addra6": 72, "addra7": 72, "addra8": 72, "addra9": 72, "addral0": 139, "addral1": 139, "addral10": 139, "addral11": 139, "addral12": 139, "addral13": 139, "addral14": 139, "addral2": 139, "addral3": 139, "addral4": 139, "addral5": 139, "addral6": 139, "addral7": 139, "addral8": 139, "addral9": 139, "addrau0": 139, "addrau1": 139, "addrau10": 139, "addrau11": 139, "addrau12": 139, "addrau13": 139, "addrau14": 139, "addrau2": 139, "addrau3": 139, "addrau4": 139, "addrau5": 139, "addrau6": 139, "addrau7": 139, "addrau8": 139, "addrau9": 139, "addrb0": 72, "addrb1": 72, "addrb10": 72, "addrb11": 72, "addrb2": 72, "addrb3": 72, "addrb4": 72, "addrb5": 72, "addrb6": 72, "addrb7": 72, "addrb8": 72, "addrb9": 72, "addrbl0": 139, "addrbl1": 139, "addrbl10": 139, "addrbl11": 139, "addrbl12": 139, "addrbl13": 139, "addrbl14": 139, "addrbl2": 139, "addrbl3": 139, "addrbl4": 139, "addrbl5": 139, "addrbl6": 139, "addrbl7": 139, "addrbl8": 139, "addrbl9": 139, "addrbu0": 139, "addrbu1": 139, "addrbu10": 139, "addrbu11": 139, "addrbu12": 139, "addrbu13": 139, "addrbu14": 139, "addrbu2": 139, "addrbu3": 139, "addrbu4": 139, "addrbu5": 139, "addrbu6": 139, "addrbu7": 139, "addrbu8": 139, "addrbu9": 139, "address": [15, 16, 35, 46, 81, 82, 91, 96], "adi1mux": [60, 112, 127, 140], "adi1muxslice0": [60, 112, 127], "adjac": [55, 91, 96, 144, 147], "adreg": [130, 143], "adregdsp0": 130, "adregdsp1": 130, "adv_b": 147, "advanc": 14, "ae1": [22, 23], "ae10": [22, 23], "ae11": [22, 23], "ae12": [22, 23], "ae13": [22, 23], "ae14": [22, 23], "ae15": [22, 23], "ae16": [22, 23], "ae17": [22, 23], "ae18": [22, 23], "ae19": [22, 23], "ae2": [22, 23], "ae20": [22, 23], "ae21": [22, 23], "ae22": [22, 23], "ae23": [22, 23], "ae24": [22, 23], "ae25": [22, 23], "ae26": [22, 23], "ae3": [22, 23], "ae4": [22, 23], "ae5": [22, 23], "ae6": [22, 23], "ae7": [22, 23], "ae8": [22, 23], "ae9": [22, 23], "aer_base_ptr": [138, 148], "aer_cap_ecrc_check_cap": [138, 148], "aer_cap_ecrc_check_capablepci": [138, 148], "aer_cap_ecrc_gen_cap": [138, 148], "aer_cap_id": [138, 148], "aer_cap_int_msg_num_msi": 138, "aer_cap_int_msg_num_msix": 138, "aer_cap_multihead": 148, "aer_cap_nextptr": [138, 148], "aer_cap_on": [138, 148], "aer_cap_optional_err_support": 148, "aer_cap_permit_rooterr_upd": [138, 148], "aer_cap_permit_rooterr_updatepci": [138, 148], "aer_cap_vers": [138, 148], "aerbaseptr": 123, "aercapabilityecrccheckcap": 123, "aercapabilityecrcgencap": 123, "aercapabilityecrcgencapablepci": 123, "aercapabilitynextptr": 123, "af1": [22, 23], "af10": [22, 23], "af11": [22, 23], "af12": [22, 23], "af13": [22, 23], "af14": [22, 23], "af15": [22, 23], "af16": [22, 23], "af17": [22, 23], "af18": [22, 23], "af19": [22, 23], "af2": [22, 23], "af20": [22, 23], "af21": [22, 23], "af22": [22, 23], "af23": [22, 23], "af24": [22, 23], "af25": [22, 23], "af26": [22, 23], "af3": [22, 23], "af4": [22, 23], "af5": [22, 23], "af6": [22, 23], "af7": [22, 23], "af8": [22, 23], "af9": [22, 23], "aff_latch": 127, "aff_latchslice0": 127, "affect": [36, 91, 144, 167], "affinit": [112, 127, 140], "affinitslice0": [112, 127, 140], "affinitslice1": 127, "affmux": [60, 112, 127, 140], "affmuxslice1": 60, "affsr": [112, 127, 140], "affsrinit": 60, "affsrinitslice0": 60, "affsrinitslice1": 60, "affsrslice0": 140, "affsrslice1": [127, 140], "after": [35, 36, 55, 91, 104, 117], "afterward": 167, "ag": 35, "again": [35, 91], "agp": 79, "agp0": 93, "agp00011": 79, "agp0100101011": 93, "agp0111": 79, "agp011101010": 79, "agp011101011": 79, "agp1111": 93, "ai1": [127, 140], "aim": 11, "align": [96, 144], "align_comma_msb": 88, "align_comma_word": [89, 105, 134], "align_comma_word_0": [66, 118, 119], "align_comma_word_0gtp": 66, "align_comma_word_0gtp_du": 118, "align_comma_word_0gtx_du": 119, "align_comma_word_1": [66, 118, 119], "align_comma_word_1gtp": 66, "align_comma_word_1gtp_du": 118, "align_comma_word_1gtx_du": 119, "align_comma_wordgtx0": 134, "align_comma_wordgtx1": 134, "align_comma_wordgtx2": 134, "align_comma_wordgtx3": 134, "all": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 166, 167], "alloc": [15, 16, 36, 58], "alloc1312": [15, 16], "alloc1514": [15, 16], "alloc1716": [15, 16], "alloc1918": [15, 16], "alloc2120": [15, 16], "allow": [36, 55, 56, 81, 82, 91, 92, 167], "allow_x8_gen2": [138, 148], "allow_x8_gen2pci": [138, 148], "almost": [58, 104, 144], "almost_empty_offset": [96, 110, 125, 139], "almost_empty_valu": 142, "almost_full_offset": [96, 110, 125, 139], "almost_full_valu": 142, "almostempti": 96, "almostful": 96, "alon": 82, "along": [144, 165], "alreadi": [35, 167], "also": [12, 14, 34, 36, 46, 55, 58, 81, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 165, 167], "alt": [46, 82], "alt0": [37, 46, 60, 82, 99, 112, 127, 140], "alt00010001": 107, "alt0010001": 107, "altdig": [46, 82], "altern": [46, 82, 144], "alumode0": [115, 130, 143], "alumode0dsp0": 115, "alumode0dsp1": 115, "alumode1": [115, 130, 143], "alumode2": [115, 130, 143], "alumode2dsp0": 143, "alumode2dsp1": 143, "alumode3": [115, 130, 143], "alumode3dsp0": [115, 130], "alumode3dsp1": 130, "alumodereg": [115, 130, 143], "alwai": [12, 14, 17, 35, 36, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 132, 137, 144, 156, 167], "amount": [58, 87, 104], "an": [12, 14, 15, 17, 34, 35, 36, 46, 55, 56, 58, 81, 87, 91, 92, 96, 144, 147, 155, 156, 165, 166, 167], "analog": [55, 91, 108, 122, 137, 147], "analog_read111": 63, "and1": [37, 46], "ani": [35, 36, 46, 55, 58, 87, 91, 108, 122, 144, 167], "anoth": [46, 82, 91, 104, 117, 132, 144, 147], "anyth": [35, 82], "anywai": [55, 144], "anywher": 144, "aoutmux": [60, 112, 127, 140], "aoutmuxslice1": 60, "appear": [35, 46, 144], "appli": 144, "applic": [16, 36, 46, 144], "appropri": [36, 96], "apu_control": 124, "apu_test": 124, "apu_udi0": 124, "apu_udi1": 124, "apu_udi10": 124, "apu_udi11": 124, "apu_udi12": 124, "apu_udi13": 124, "apu_udi14": 124, "apu_udi15": 124, "apu_udi2": 124, "apu_udi3": 124, "apu_udi4": 124, "apu_udi5": 124, "apu_udi6": 124, "apu_udi7": 124, "apu_udi8": 124, "apu_udi9": 124, "ar": [12, 13, 15, 16, 17, 34, 35, 36, 38, 42, 45, 46, 47, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 166, 167], "arammod": [60, 112, 127, 140], "arb_num_time_slot": 69, "arb_time_slot_0": 69, "arb_time_slot_1": 69, "arb_time_slot_10": 69, "arb_time_slot_11": 69, "arb_time_slot_2": 69, "arb_time_slot_3": 69, "arb_time_slot_4": 69, "arb_time_slot_5": 69, "arb_time_slot_6": 69, "arb_time_slot_7": 69, "arb_time_slot_8": 69, "arb_time_slot_9": 69, "arbitrari": [14, 36, 144, 167], "arbitrarili": 12, "architectur": [104, 165], "area": [15, 16, 35, 45, 47, 55, 58, 81, 83, 87, 91, 96, 104, 117, 132, 144, 155, 156, 167], "areg": [45, 81, 103], "areg_acascreg": [115, 130, 143], "aren": [55, 58, 147], "ari_cap_en": 149, "ari_cap_enablepcie3": 149, "arm": 144, "around": [91, 104, 132], "arrai": [35, 155, 156, 167], "arrang": [147, 155], "array_mod": 142, "array_mode_4_x_40": 142, "array_mode_4_x_81": 142, "array_mode_8_x_41": 142, "array_modein_fifo": 142, "ascii": 167, "assembl": [46, 82], "assert": [15, 16], "assign": [13, 15, 16, 58, 87, 104, 117, 132, 144, 167], "associ": [12, 34, 36, 37, 42, 46, 55, 58, 82, 87, 91, 99, 104, 108, 117, 122, 132, 144, 156, 165, 166, 167], "async": [14, 36, 81, 167], "async1": [53, 61, 65, 141], "async11": [45, 59], "asynchron": [46, 56, 82, 167], "atbbumpen": 105, "atben": 105, "atbsel": 105, "attempt": 35, "attribut": [45, 46, 81, 82, 96], "auto": 35, "auto01": 134, "auto_c": 105, "auto_calgt11a": 105, "auto_calgt11b": 105, "auto_dps00": 102, "auto_zd211": 102, "autoincr": 35, "automot": [12, 34], "autoreset_over_under_flow": 115, "autoreset_patdet": [130, 143], "autoreset_pattern_detect": 115, "autoreset_pattern_detect_optinv": 115, "autoreset_pattern_detectdsp0": 115, "aux": [2, 3, 4, 5, 6, 7, 8, 9], "auxiliari": [108, 122, 137, 147], "avail": [17, 55, 91, 104, 117, 132, 144, 156], "ave_freq_lock10": 102, "awai": [104, 117, 144], "ax0": [60, 112, 127, 140], "ax01": [60, 112, 127, 140], "ax0100": [112, 127, 140], "ax1": [60, 112], "ax10": [127, 140], "ax1010": 60, "axisten_if_cc_alignment_mod": 149, "axisten_if_cc_alignment_modepcie3": 149, "axisten_if_cc_parity_chk": 149, "axisten_if_cq_alignment_mod": 149, "axisten_if_enable_client_tag": 149, "axisten_if_enable_msg_rout": 149, "axisten_if_enable_rx_msg_intfc": 149, "axisten_if_rc_alignment_mod": 149, "axisten_if_rc_alignment_modepcie3": 149, "axisten_if_rc_straddl": 149, "axisten_if_rq_alignment_mod": 149, "axisten_if_rq_parity_chk": 149, "axisten_if_rq_parity_chkpcie3": 149, "axisten_if_width": 149, "b": [2, 3, 4, 5, 6, 7, 8, 9, 36, 46, 55, 78, 81, 87, 91, 96, 150, 151, 152, 157, 158, 159, 160, 161, 162], "b0": [45, 81], "b0reg": [53, 65], "b1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "b10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "b11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "b11100": 150, "b12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 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8, 9, 36, 155, 167], "clk_mux3433": 16, "clk_mux3736": 15, "clk_out_gtp_sel_0": 66, "clk_out_gtp_sel_0gtp": 66, "clk_out_gtp_sel_1": 66, "clk_out_gtp_sel_1gtp": 66, "clk_rebuf": 141, "clk_sel_typ": 61, "clk_switch_opt": 49, "clk_term": 100, "clk_term_b": 104, "clk_term_t": 104, "clk_to_dcm0": 71, "clk_to_dcm1": 71, "clk_to_pll": 64, "clka": [72, 96, 97], "clka00": 97, "clka1d81010000010000": 97, "clka_en": 97, "clkaint": 72, "clkardclkl": [110, 125, 139], "clkardclklbram": 125, "clkardclku": [110, 125, 139], "clkardclkubram": 125, "clkawrclk": 59, "clkawrclkbram_h0": 59, "clkawrclkbram_h1": 59, "clkb": [58, 72, 78, 87, 96, 97, 122, 152], "clkb01": 97, "clkb_2dll": 78, "clkb_4dll": 78, "clkb_enabl": 97, "clkb_enablepmcd1": 97, "clkbint": 72, "clkbrdclk": 59, "clkbrdclkbram_h0": 59, "clkbrdclkbram_h1": 59, "clkbrst": 71, "clkbwrclkl": [110, 125, 139], "clkbwrclku": [110, 125, 139], "clkbwrclkubram": 125, "clkc": [41, 54, 58, 67, 87, 97], "clkc10": 97, "clkc_50a": [54, 58], "clkc_clkout0": 61, "clkc_clkout1": 61, "clkc_enabl": 97, "clkc_enablepmcd1": 97, "clkc_mux": 103, "clkcm_cfg": 134, "clkcm_cfggtx1": 134, "clkd": 97, "clkd11": 97, "clkd_enabl": 97, "clkd_enablepmcd1": 97, "clkdiv": 122, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkdivologic0": 122, "clkdivologic1": 122, "clkdsp0": 130, "clkdsp1": 130, "clkdv": [51, 52, 64, 86], "clkdv0010000": 74, "clkdv0010000010": 74, "clkdv00100000110": 74, "clkdv001011": 74, "clkdv01000000110": 74, "clkdv010100": 74, "clkdv0110": 64, "clkdv1000000010": 74, "clkdv10000010010": 74, "clkdv10000011": 102, "clkdv10100000011": 74, "clkdv101101": 74, "clkdv1100001": 74, "clkdv110100": 74, "clkdv1101000": 74, "clkdv1110000": 74, "clkdv_count_fal": [51, 52, 64, 77, 86, 102], "clkdv_count_fall_2": [51, 52, 64, 77, 86, 102], "clkdv_count_max": [51, 52, 64, 77, 86, 102], "clkdv_enabl": 102, "clkdv_enabledcm": 102, "clkdv_mode": [51, 52, 64, 77, 86, 102], "clkdv_modedcm": [51, 52, 86, 102], "clkdv_modedcm0": 64, "clkdv_modedcm1": 64, "clkdv_modedl": 77, "clkdv_phase_fal": [51, 52, 64, 77, 86, 102], "clkdv_phase_ris": [51, 52, 64, 77, 86, 102], "clkdvdcm": [51, 52, 86], "clkdvdcm0": 64, "clkdvdcm1": 64, "clkfb": [51, 64, 77, 86, 102], "clkfb0": [51, 86, 102], "clkfb011": 55, "clkfb_enabl": 102, "clkfb_enabledcm": 102, "clkfb_feedback": 102, "clkfb_feedbackdcm": 102, "clkfb_iob": [51, 52, 64, 86, 102], "clkfb_iobdcm": [51, 52, 86, 102], "clkfb_iobdcm0": 64, "clkfb_iobdcm1": 64, "clkfb_pad": 77, "clkfb_padint": 77, "clkfbdcm": [51, 86], "clkfbdcm10111": 71, "clkfbin": 71, "clkfbin110": 71, "clkfbout10100": 71, "clkfbout111": 71, "clkfx": [51, 52, 64, 86], "clkfx00110001": 102, "clkfx0111": 64, "clkfx180": [51, 86], "clkfx18000101001": 102, "clkfx1801000": 64, "clkfx180_enabl": 102, "clkfx180_enabledcm": 102, "clkfx180dcm": [51, 86], "clkfx_divid": [51, 52, 64, 86, 102], "clkfx_enabl": 102, "clkfx_enabledcm": 102, "clkfx_multipli": [51, 52, 64, 86, 102], "clkfxdcm": [51, 52, 86], "clkfxdcm0": 64, "clkfxdcm1": 64, "clkfxdv_divid": 64, "clkh": 152, "clkin": [64, 71, 77, 102, 118, 119], "clkin011": 55, "clkin1": [51, 86, 102], "clkin1100": 71, "clkin_clkfb_en": 64, "clkin_clkfb_enabledcm0": 64, "clkin_clkfb_enabledcm1": 64, "clkin_clkfbin_us": 71, "clkin_clkfbin_usedpl": 71, "clkin_divide_by_2": [51, 52, 64, 86, 102], "clkin_divide_by_2dcm": [51, 52, 86, 102], "clkin_divide_by_2dcm0": 64, "clkin_divide_by_2dcm1": 64, "clkin_en": 102, "clkin_enabledcm": 102, "clkin_iob": [51, 52, 64, 86, 102], "clkin_iobdcm": [51, 52, 86, 102], "clkin_iobdcm0": 64, "clkin_iobdcm1": 64, "clkin_pad": 77, "clkindc_b": [118, 119], "clkindc_b_0": 66, "clkindc_b_0gtp": 66, "clkindc_b_1": 66, "clkindc_b_1gtp": 66, "clkindc_bgtp_dual": 118, "clkindc_bgtx_dual": 119, "clkineast011": 66, "clkinsel": 71, "clkinsel_mod": 71, "clkinsel_modepl": 71, "clkinsel_stat": 71, "clkinsel_staticpl": 71, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 151, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 152], "clkout0000": 71, "clkout1001": 71, "clkout2010": 71, "clkout3011": 71, "clkout4100": 71, "clkout5101": 71, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [118, 119], "clkout_north_s0": [118, 119], "clkout_north_s101": [118, 119], "clkout_phase_shift": 64, "clkout_south": [118, 119], "clkout_south_n0": [118, 119], "clkout_south_n001": [118, 119], "clkout_west": 66, "clkout_westgtp": 66, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [118, 119], "clkpn1": [118, 119], "clkr": [58, 78, 152], "clkrcv_trst": [119, 134], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 134, "clkrcv_trstgtx_dual": 119, "clkslice0": 112, "clkslice1": [60, 127], "clkt": [58, 78, 87, 152], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 134, "clktestsig1": 133, "clktestsig11": 134, "clktestsig1111": 134, "clktestsig_sel": 133, "clktestsig_selgth": 133, "clkv": [78, 152], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 117, 120, 122, 132, 135, 137, 144, 145, 147, 156, 165, 167], "clock_delai": 124, "clock_invert_m": 115, "clock_invert_p": 115, "clock_invert_pdsp1": 115, "clockwis": [58, 87], "close": [58, 81, 132, 144], "closest": 58, "clr0": 150, "clrmux": 150, "clrmuxlc0": 150, "clrmuxlc1": 150, "clrmuxlc2": 150, "clrmuxlc3": 150, "cm_trim": 134, "cm_trim_0": [66, 119], "cm_trim_1": [66, 119], "cmd_intx_impl": [138, 148], "cmd_intx_implementedpci": [138, 148], "cmo": 14, "cmos0": 151, "cmos00": [74, 79], "cmos00111": 137, "cmos01": 74, "cmos111": [57, 93, 108, 122], "cmos1200011": 137, "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 117, 120, 122, 132, 144, 145], "cmt0": 61, "cmt10": 61, "cmt_bufg_": 132, "cmt_bufg_bot": [132, 135], "cmt_bufg_top": [132, 135], "cmt_clk010000000001000": 113, "cmt_clk100000010001000": 113, "cmt_clk1000001000010000": 113, "cmt_clk1100100000010000": 113, "cmt_clk1200000001010000": 113, "cmt_clk1300000100010000": 113, "cmt_clk1400010000010000": 113, "cmt_clk1501000000010000": 113, "cmt_clk1610000000100000": 113, "cmt_clk1700000010100000": 113, "cmt_clk1800001000100000": 113, "cmt_clk1900100000100000": 113, "cmt_clk2000000001100000": 113, "cmt_clk200001000001000": 113, "cmt_clk2100000100100000": 113, "cmt_clk2200010000100000": 113, "cmt_clk2301000000100000": 113, "cmt_clk2410000000000010": 113, "cmt_clk2500000010000010": 113, "cmt_clk2600001000000010": 113, "cmt_clk2700100000000010": 113, "cmt_clk300100000001000": 113, "cmt_clk400000001001000": 113, "cmt_clk500000100001000": 113, "cmt_clk600010000001000": 113, "cmt_clk701000000001000": 113, "cmt_clk810000000010000": 113, "cmt_clk900000010010000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_fifo": 145, "cmt_pll": 71, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 151, "cmuxosc": 151, "cnr": [58, 78, 87, 152], "co01": 150, "co1": 150, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 117, 132, 144], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 122, 137, 147, 155, 156, 157, 158, 159, 160, 161, 162, 164, 166], "columnar": 104, "com": [51, 86], "com_burst_v": 134, "com_burst_val_0": [66, 118, 119], "com_burst_val_1": [66, 118, 119], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 167], "combination": 81, "combinatori": [14, 36, 167], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 117, 122, 132, 144, 165, 167], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 134, "comma_10b_enable_0": [66, 118, 119], "comma_10b_enable_1": [66, 118, 119], "comma_10b_mask": [88, 89, 105], "comma_doubl": 134, "comma_double_0": [118, 119], "comma_double_0gtp_du": 118, "comma_double_0gtx_du": 119, "comma_double_1": [118, 119], "comma_double_1gtp_du": 118, "comma_double_1gtx_du": 119, "comma_doublegtx0": 134, "comma_doublegtx1": 134, "comma_doublegtx2": 134, "comma_doublegtx3": 134, "commerci": [17, 156], "common": [100, 147], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [144, 155], "companion": [44, 106], "compat": [12, 34, 165], "compens": 82, "complement": [108, 122, 137, 147], "complet": [12, 13, 16, 34, 35, 36, 104, 144, 155, 165], "complex": [15, 16, 144], "comput": [81, 155], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86], "concur00100101": 102, "concur1001": 64, "concur_en": 102, "concur_enabledcm": 102, "concurdcm": [51, 52, 86], "concurdcm0": 64, "concurdcm1": 64, "config": [15, 16, 155], "config10": 102, "config_fallback": [114, 129], "config_r": [39, 48, 49, 75, 84, 101, 114, 129, 151], "configrout": 123, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 117, 120, 122, 132, 135, 137, 145, 147, 152, 155, 164], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 122, 137, 144, 166, 167], "consecut": 132, "consid": [35, 104, 108, 117, 122, 132, 137, 144, 147], "consist": [35, 36, 81, 104, 117, 122, 132, 137, 144], "const": [13, 14, 35, 36, 46, 82, 166, 167], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 167, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 132, 137, 144, 147, 166, 167], "content": [35, 46, 82, 132], "contigu": [15, 16], "continu": [35, 147], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "convert": [15, 16], "convst": 109, "convstclk": [111, 126], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 155, 156, 167], "cor": [41, 54, 78, 90, 106, 120, 135], "cor1": [54, 67, 120, 135], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 117, 120, 135, 145, 165, 167], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 144, 152], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 156, 167], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 117, 132, 144, 157, 158, 159, 160, 161, 162], "cout": [46, 82, 153], "coutmux": [60, 112, 127, 140], "coutmuxslice1": 60, "cover": [104, 117, 132, 144, 147, 167], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 158, 165], "cpl_timeout_disable_support": [138, 148], "cpl_timeout_ranges_support": [138, 148], "cpld": [0, 12, 34, 36, 165, 167], "cpmc440clk": 124, "cpmc440timerclock": 124, "cpmdcrclk": 124, "cpmdma0llclk": 124, "cpmdma1llclk": 124, "cpmdma2llclk": 124, "cpmdma3llclk": 124, "cpmfcmclk": 124, "cpminterconnectclk": 124, "cpmmcclk": 124, "cpmppcmplbclk": 124, "cpmppcs0plbclk": 124, "cpmppcs1plbclk": 124, "crammod": [60, 112, 127, 140], "crc": [39, 48, 49, 62, 84, 101, 114, 151], "crc32_0": [118, 119], "crc32_1": [118, 119], "crc32_2": [118, 119], "crc32_3": [118, 119], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [118, 119], "crc_start_of_pkt": [88, 89], "crcclk": [118, 119], "crcclkgtp_dual": 118, "crcclkgtx_dual": 119, "creat": [55, 87, 91, 104, 117], "create_edg": [98, 111, 128, 141], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 115, 130, 143], "cregdsp": [53, 65], "cregdsp0": [115, 130], "cregdsp1": 130, "crm_core_clk_freq_500": 149, "crm_core_clk_freq_500pcie3": 149, "crm_module_rst": [138, 148], "crm_user_clk_freq": 149, "crmcoreclk": 123, "crmcoreclkdlo": 123, "crmcoreclkpci": 123, "crmcoreclkrxo": 123, "crmcoreclkrxopci": 123, "crmcoreclktxo": 123, "crmcoreclktxopci": 123, "crmuserclk": 123, "crmuserclkrxo": 123, "crmuserclktxo": 123, "cross": [58, 91, 132, 144], "cs144": [20, 21, 34, 159, 165], "cs280": [24, 25, 34, 160, 165], "cs48": [26, 27, 28, 30, 31, 34, 157, 158, 165], "cs_b": [108, 122], "csi_b": [137, 147], "cso2pin": [50, 63], "cso_b": [122, 137, 147], "cspin": [98, 111, 126], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 120, 135], "ctl1": 135, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [121, 136, 146], "ctrl00001": [136, 146], "ctrl1": [121, 136, 146], "ctrl10010": [136, 146], "ctrl2": 121, "ctrl3": 121, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 117, 144], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 127, 140], "cx0100": [112, 127, 140], "cx1": [60, 112], "cx10": [127, 140], "cx1010": 60, "cxt": 132, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 127, 140], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 127, 140], "cyinitslice0": [73, 99, 112, 127, 140], "cyinitslice1": [37, 46, 60, 73, 112, 127, 140], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 122, 137, 147, 167], "d0": [130, 143], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162, 167], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 143, 158, 159, 160, 161, 162], "d100001": 122, "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d15": [3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d16": [3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d17": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d18": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d19": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d20": [6, 7, 22, 23, 24, 130, 143, 161, 162], "d21": [6, 7, 22, 23, 130, 143, 161, 162], "d22": [6, 7, 22, 23, 130, 143, 161, 162], "d23": [22, 23, 130, 143], "d24": [22, 23, 130, 143], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d3iob0": [108, 122], "d3iob1": [108, 122], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d4iob0": 108, "d4iob1": 108, "d4ologic0": 122, "d4ologic1": 122, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 122, 130, 143, 159, 160, 161, 162], "d5ffinit": [127, 140], "d5ffinitslice0": [127, 140], "d5ffmux": [127, 140], "d5ffsr": [127, 140], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 127, "d5ologic0": [108, 122], "d5ologic1": [108, 122], "d5q0": 60, "d5q0100": [60, 127, 140], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d6iob0": 122, "d6iob1": 122, "d6lut": [60, 112, 127, 140], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 130, 143, 157, 158, 159, 160, 161, 162], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 143, 158, 159, 160, 161, 162], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d_in": [108, 122], "d_out_busi": 122, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 117, 120, 122, 132, 144, 151, 155, 156, 163, 167], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_l": [110, 125, 139], "data_r": [61, 108, 122], "data_u": [110, 125, 139], "data_width": [108, 122], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 155, 164, 166, 167], "datain": 122, "datain1000": 122, "datainilogic0": 122, "datainilogic1": 122, "dataint": 151, "datap": [45, 59, 81, 96], "datap_l": [110, 125, 139], "datap_u": [110, 125, 139], "datareg": 13, "datastream": [17, 156], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 121, 136, 146, 150, 153], "dbl0001010000": 121, "dbl0001100000": 121, "dbl0010010000": 121, "dbl0010100000": 121, "dbl0100010000": 121, "dbl0100100000": 121, "dbl1000010000": 121, "dbl1000100000": 121, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 122, 137, 147], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 126], "dci_clk_enablemisc": 85, "dci_misc": [108, 122, 137], "dci_mod": [57, 93, 108, 122, 137], "dci_osc_sel": 50, "dci_t": [108, 122, 137], "dci_test_mux": 50, "dcireset": [98, 111, 126], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 122, 137], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 118, 119, 126, 133, 134], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 133, "dclkgtp": 66, "dclkgtp_dual": 118, "dclkgtx_dual": 119, "dclksysmon": 111, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": 64, "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": 71, "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": 64, "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": 71, "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": 102, "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_enabl": 50, "dcm_ext_fb_en": 102, "dcm_ext_fb_endcm": 102, "dcm_lock_high": 102, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_shutdown": [48, 84, 101], "dcm_unused_taps_powerdown": 102, "dcm_unused_taps_powerdowndcm": 102, "dcm_vbg_pd": 102, "dcm_vbg_sel": 102, "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": 102, "dcm_vreg_enabledcm": 102, "dcm_vreg_phase_margin": 102, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcr_autolock_en": 124, "dcr_test": 124, "dcremacclk": 116, "dcy0": [60, 112, 127, 140], "dcy0slice0": [112, 127, 140], "dcy0slice1": [60, 140], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 122], "ddr00100": 122, "ddr01": 69, "ddr01100": 122, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": [108, 122], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 134], "dec_mcomma_detect_0": [66, 118, 119], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 118, "dec_mcomma_detect_0gtx_du": 119, "dec_mcomma_detect_1": [66, 118, 119], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 118, "dec_mcomma_detect_1gtx_du": 119, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 134, "dec_mcomma_detectgtx1": 134, "dec_mcomma_detectgtx2": 134, "dec_mcomma_detectgtx3": 134, "dec_pcomma_detect": [88, 89, 105, 134], "dec_pcomma_detect_0": [66, 118, 119], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 118, "dec_pcomma_detect_0gtx_du": 119, "dec_pcomma_detect_1": [66, 118, 119], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 118, "dec_pcomma_detect_1gtx_du": 119, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 134, "dec_pcomma_detectgtx1": 134, "dec_pcomma_detectgtx2": 134, "dec_pcomma_detectgtx3": 134, "dec_valid_comma_onli": [88, 89, 105, 134], "dec_valid_comma_only_0": [66, 118, 119], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 118, "dec_valid_comma_only_0gtx_du": 119, "dec_valid_comma_only_1": [66, 118, 119], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 118, "dec_valid_comma_only_1gtx_du": 119, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 134, "dec_valid_comma_onlygtx1": 134, "dec_valid_comma_onlygtx2": 134, "dec_valid_comma_onlygtx3": 134, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 137, 144, 147, 156, 165, 167], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "default10": 122, "default_idelay_valu": 122, "default_only1011": 113, "defin": 167, "definit": 147, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [157, 158, 159, 160, 161, 162], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_pt_ut": [157, 158, 159, 160, 161, 162], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "delai": [14, 44, 47, 74, 78, 117, 120, 132, 135, 144, 145], "delay0": 153, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_src": 122, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 122, "delayed_write0": 139, "delayed_write00": 125, "delaymux": 153, "delaymuxint": 153, "delaymuxiob2": 153, "delaymuxiob3": 153, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 117, 132, 144, 147, 156, 166, 167], "deriv": [12, 34, 56, 92, 165, 167], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 128, 141, 142, 156], "descript": [45, 99], "design": [12, 36, 58, 165, 167], "deskew_adjust": [54, 64, 90, 102], "despit": 144, "destin": 36, "detail": [35, 58, 87, 96, 166], "determin": [12, 34, 35, 46, 82, 167], "dev_cap2_ari_forwarding_support": 148, "dev_cap2_ari_forwarding_supportedpci": 148, "dev_cap2_atomicop32_completer_support": 148, "dev_cap2_atomicop32_completer_supportedpci": 148, "dev_cap2_atomicop64_completer_support": 148, "dev_cap2_atomicop_routing_support": 148, "dev_cap2_cas128_completer_support": 148, "dev_cap2_cas128_completer_supportedpci": 148, "dev_cap2_endend_tlp_prefix_support": 148, "dev_cap2_endend_tlp_prefix_supportedpci": 148, "dev_cap2_extended_fmt_field_support": 148, "dev_cap2_ltr_mechanism_support": 148, "dev_cap2_ltr_mechanism_supportedpci": 148, "dev_cap2_max_endend_tlp_prefix": 148, "dev_cap2_no_ro_enabled_prpr_pass": 148, "dev_cap2_tph_completer_support": 148, "dev_cap_enable_slot_pwr_limit_scal": [138, 148], "dev_cap_enable_slot_pwr_limit_scalepci": [138, 148], "dev_cap_enable_slot_pwr_limit_valu": [138, 148], "dev_cap_endpoint_l0s_lat": [70, 138, 148], "dev_cap_endpoint_l1_lat": [70, 138, 148], "dev_cap_ext_tag_support": [70, 138, 148], "dev_cap_ext_tag_supportedpci": [138, 148], "dev_cap_function_level_reset_cap": [138, 148], "dev_cap_max_payload_support": [70, 138, 148], "dev_cap_phantom_functions_support": [70, 138, 148], "dev_cap_role_based_error": [70, 138, 148], "dev_cap_rsvd_14_12": [138, 148], "dev_cap_rsvd_17_16": [138, 148], "dev_cap_rsvd_31_29": [138, 148], "dev_control_aux_power_support": [138, 148], "dev_control_aux_power_supportedpci": 148, "dev_control_ext_tag_default": 148, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 120, 122, 135, 137, 145, 147, 155, 164, 166], "device_id": 138, "devicebram": 45, "devicecapabilityendpointl0slat": 123, "devicecapabilityendpointl1lat": 123, "devicedcm": [51, 52, 86], "deviceid": 123, "deviceiodelai": 122, "deviceserialnumb": 123, "devicevalu": [47, 61], "devoid": 144, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [119, 134], "dfe_cfg": 134, "dfe_cfg_0": 119, "dfe_cfg_1": 119, "dfe_drp_en": 134, "dfe_drp_engtx0": 134, "dfe_drp_engtx1": 134, "dfe_drp_engtx2": 134, "dfe_drp_engtx3": 134, "dfe_train_ctrl_lane0": 133, "dfe_train_ctrl_lane1": 133, "dfe_train_ctrl_lane2": 133, "dfe_train_ctrl_lane3": 133, "dff": [14, 36, 167], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 155], "dff1": 15, "dff_latch": 127, "dff_latchslice0": 127, "dffce": 167, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 155], "dffinit": [112, 127, 140], "dffinitslice0": [112, 127, 140], "dffmux": [60, 112, 127, 140], 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125, 139], "init_b_u": [110, 125, 139], "init_bitslipcnt": [108, 122], "init_c": [108, 122], "init_loadcnt": [108, 122], "init_out": [98, 111, 128, 141], "init_outbufgctrl0": 98, "init_outbufgctrl1": 98, "init_outbufgctrl10": 98, "init_outbufgctrl11": 98, "init_outbufgctrl12": 98, "init_outbufgctrl13": 98, "init_outbufgctrl14": 98, "init_outbufgctrl15": 98, "init_outbufgctrl16": 98, "init_outbufgctrl17": 98, "init_outbufgctrl18": 98, "init_outbufgctrl19": 98, "init_outbufgctrl2": 98, "init_outbufgctrl20": 98, "init_outbufgctrl21": 98, "init_outbufgctrl22": 98, "init_outbufgctrl23": 98, "init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_rank1_parti": [108, 122], "init_rank2": [108, 122], "init_rank3": [108, 122], "init_signals_error": 129, "init_skip": 62, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 167], "initp_xx": [81, 96], "initpin": [98, 111, 126], "initpinmisc": 111, "initx": 73, "initxint": 73, "initxslice1": 73, "inityint": 73, "inmode0": [130, 143], "inmode1": [130, 143], "inmode2": [130, 143], "inmode3": [130, 143], "inmode4": [130, 143], "inmodereg": [130, 143], "inner": [58, 87, 104, 117, 132, 137], "input": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 33, 34, 35, 41, 44, 46, 54, 56, 78, 81, 82, 90, 92, 96, 104, 106, 117, 120, 132, 135, 144, 145, 151, 152, 155, 156, 164, 165, 166], "inputtest": 55, "insan": 82, "insert": 144, "insid": [55, 91], "instanc": 87, "instanti": [55, 91], "instead": [12, 14, 16, 34, 35, 36, 42, 56, 58, 81, 91, 108, 144, 147, 165, 167], "instruct": [11, 33, 36, 56, 92, 164], "int": [17, 37, 38, 45, 46, 47, 53, 58, 61, 65, 68, 72, 73, 74, 76, 77, 79, 80, 81, 82, 83, 87, 96, 99, 104, 107, 117, 121, 132, 136, 144, 146, 150, 151, 153, 154, 156], "int0": [45, 142], "int00": [130, 143], "int000": 139, "int00001": 47, "int0001": [47, 83, 153], "int001": 47, "int01": 38, "int1": [51, 52, 64, 77, 86, 102], "int_clk00001": 109, "int_imux00000": 109, "integ": [17, 156], "interconnect": [14, 36, 37, 41, 44, 45, 46, 54, 56, 58, 67, 78, 81, 82, 87, 90, 92, 96, 104, 106, 117, 120, 132, 135, 137, 144, 145, 167], "interconnect_imask": 124, "interconnect_tmpl_sel": 124, "intereconnect": 144, "interfac": [11, 33, 41, 52, 54, 58, 64, 67, 87, 90, 106, 164], "interface_typ": [108, 122], "interface_typeilogic0": 108, "interface_typeilogic1": 108, "interfer": [46, 82], "interleav": 16, "intern": [36, 56, 92, 96, 144, 166], "internal1": 129, "internal_vref": [113, 137], "internalclk0": [49, 62], "interpos": 144, "interpret": 17, "interrupt": [35, 91], "interrupt_pin": [138, 148], "interrupt_stat_auto": 148, "interrupt_stat_autopci": 148, "interruptpin": 123, "intersect": [38, 47, 55, 58, 87, 104, 117, 132, 144], "intest": [13, 35, 166], "intf": [104, 107, 117, 120, 132, 135, 144, 145], "intosc00": 76, "intro": [41, 54, 67, 78, 106, 120, 135, 145, 152], "introduc": [58, 96, 144], "introduct": [11, 33, 44, 54, 90, 164], "inv": [15, 36, 37, 42, 43, 46, 47, 51, 52, 55, 57, 59, 60, 61, 64, 65, 66, 69, 71, 72, 73, 74, 76, 77, 79, 80, 83, 86, 91, 93, 96, 97, 98, 99, 102, 103, 107, 108, 109, 110, 111, 112, 115, 116, 118, 119, 122, 123, 124, 125, 126, 127, 128, 130, 133, 134, 139, 140, 141, 143, 150, 151, 153], "inv0010": 153, "inv1000": 153, "inv22": [15, 16], "invalid": [15, 16, 35], "invers": [17, 34, 36, 57, 59, 79, 82, 93, 108, 122, 137, 156, 167], "invert": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 17, 23, 36, 37, 38, 39, 40, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52, 55, 57, 59, 60, 61, 62, 63, 64, 65, 66, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 91, 93, 96, 97, 98, 99, 100, 101, 102, 103, 105, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 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"out_r7": [47, 83], "out_r7gclkc": 83, "out_t0": [38, 47, 83], "out_t1": [38, 47, 83], "out_t1gclkh": [38, 47, 83], "out_t2": [38, 47, 83], "out_t2gclkh": [38, 47, 83], "out_t3": [38, 47, 83], "out_t3gclkh": [38, 47, 83], "out_t4": [38, 47, 83], "out_t4gclkh": [38, 47, 83], "out_t5": [38, 47, 83], "out_t5gclkh": [38, 47, 83], "out_t6": [38, 47, 83], "out_t6gclkh": [38, 47, 83], "out_t7": [38, 47, 83], "out_t7gclkh": [38, 47, 83], "out_u0": [128, 141], "out_u1": [128, 141], "out_u10": 141, "out_u11": 141, "out_u2": [128, 141], "out_u3": [128, 141], "out_u4": [128, 141], "out_u5": [128, 141], "out_u6": [128, 141], "out_u7": [128, 141], "out_u8": 141, "out_u9": 141, "out_uim": 36, "outbus0": 83, "outbus1": 83, "outbus2": 83, "outbus3": 83, "outbus4": 83, "outbus4dcmconn": 83, "outbus5": 83, "outbus5dcmconn": 83, "outbus6": 83, "outbus7": 83, "outd_clkout0": 61, "outd_clkout1": 61, "outd_lock": 61, "outer": [132, 137], "outgo": 91, "outl_clkout0": 61, "outl_clkout1": 61, "outl_locked0": 61, "outl_locked1": 61, "output": [11, 12, 33, 34, 35, 41, 44, 54, 56, 78, 81, 90, 92, 96, 104, 106, 117, 120, 132, 135, 144, 145, 152, 164, 166], "output0001": [57, 93], "output001": [108, 122, 137], "output_delai": [122, 137], "output_delayiob0": 122, "output_delayiob1": 122, "output_diff": [57, 93], "output_diff_group": 57, "output_dis": 142, "output_disableout_fifo": 142, "output_en": [57, 93, 108, 122, 137], "output_half0010": [57, 93], "output_half010": [108, 122, 137], "output_ht_25101000000001100011": 122, "output_ht_25101100000011001110": 137, "output_ldt_2501100110": 108, "output_lvds_2501101010": 108, "output_lvds_25100000000001100011": 122, "output_lvds_25100100000000011110": 137, "output_lvds_25_dci01000000": 108, "output_lvdsext_25110000000001000101": 122, "output_lvdsext_25110100000000011110": 137, "output_lvdsext_2511100010": 108, "output_lvdsext_25_dci11000000": 108, "output_misc": [57, 79, 93, 108, 122, 137], "output_misciob0": 57, "output_misciob1": [57, 93], "output_misciob2": 57, "output_misciob3": 57, "output_misciob4": [57, 93], "output_rsds_2501101010": 108, "output_rsds_25100000000001100011": 122, "output_rsds_25100100000000011110": 137, "output_ulvds_2501100110": 108, "outputs_act": 151, "outr_clkout0": 61, "outr_clkout1": 61, "outr_locked0": 61, "outr_locked1": 61, "outsel0": 97, "outsel1": 97, "outsel2": 97, "outsid": [35, 91], "outu_clkout0": 61, "outu_clkout1": 61, "outu_lock": 61, "over": [15, 16, 35, 46, 81, 82, 132, 144], "over_temperatur": 109, "over_temperature_delai": 109, "over_temperature_off": 109, "overlap": [35, 37, 46], "overrid": [17, 35, 166], "overriden": [17, 35, 166, 167], "oversample_mod": [118, 119], "overtemp_powerdown": [114, 129], "overview": [11, 33, 164], "own": [17, 36, 91, 147, 167], "p": [15, 16, 36, 81, 144, 147, 155, 167], "p0": 96, "p0cmdclk": 69, "p0cmden": 69, "p0rdclk": 69, "p0rden": 69, "p0wrclk": 69, "p0wren": 69, "p1": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p10": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p100": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p101": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p102": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p103": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p104": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p105": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p106": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p107": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p108": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p109": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p11": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p110": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p111": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p112": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p113": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p114": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p115": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p116": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p117": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p120": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p121": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p122": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p123": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p124": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p125": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p126": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p127": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p128": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p129": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p13": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p130": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p131": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p132": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p133": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p134": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p135": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p136": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p137": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p138": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p139": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p14": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p140": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p141": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p142": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p143": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p144": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p145": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p146": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p147": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p148": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p149": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p15": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p150": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p151": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p152": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p153": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p154": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p155": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p156": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p157": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p158": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p159": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p16": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p160": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p161": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p162": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p163": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p164": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p165": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p166": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p167": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p168": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p169": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p17": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p170": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p171": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p172": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p173": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p174": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p175": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p176": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p177": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p178": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p179": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p18": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p180": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p181": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p182": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p183": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p184": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p185": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p186": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p187": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p188": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p189": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p19": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p190": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p191": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p192": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p193": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p194": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p195": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p196": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p197": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p198": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p199": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p1cmdclk": 69, "p1cmden": 69, "p1rdclk": 69, "p1rden": 69, "p1wrclk": 69, "p1wren": 69, "p2": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p20": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p200": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p201": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p202": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p203": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p204": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p205": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p206": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p207": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p208": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p209": [3, 6, 7], "p21": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p210": [3, 6, 7], "p211": [3, 6, 7], "p212": [3, 6, 7], "p213": [3, 6, 7], "p214": [3, 6, 7], "p215": [3, 6, 7], "p216": [3, 6, 7], "p217": [3, 6, 7], "p218": [3, 6, 7], "p219": [3, 6, 7], "p22": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p220": [3, 6, 7], "p221": [3, 6, 7], "p222": [3, 6, 7], "p223": [6, 7], "p224": [6, 7], "p225": [6, 7], "p226": [6, 7], "p227": [6, 7], "p228": [6, 7], "p229": [6, 7], "p23": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p230": [6, 7], "p231": [6, 7], "p232": [6, 7], "p233": [6, 7], "p234": [6, 7], "p235": [6, 7], "p236": [6, 7], "p237": [6, 7], "p238": [6, 7], "p239": [6, 7], "p24": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p240": [6, 7], "p241": [6, 7], "p242": [6, 7], "p243": [6, 7], "p244": [6, 7], "p245": [6, 7], "p246": [6, 7], "p247": [6, 7], "p248": [6, 7], "p249": [6, 7], "p25": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p250": [6, 7], "p251": [6, 7], "p252": [6, 7], "p253": [6, 7], "p254": [6, 7], "p255": [6, 7], "p256": [6, 7], "p257": [6, 7], "p258": [6, 7], "p259": [6, 7], "p26": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p260": [6, 7], "p261": [6, 7], "p262": [6, 7], "p263": [6, 7], "p264": [6, 7], "p265": [6, 7], "p266": [6, 7], "p267": [6, 7], "p268": [6, 7], "p269": [6, 7], "p27": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p270": [6, 7], "p271": [6, 7], "p272": [6, 7], "p273": [6, 7], "p274": [6, 7], "p275": [6, 7], "p276": [6, 7], "p277": [6, 7], "p278": [6, 7], "p279": [6, 7], "p28": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p280": [6, 7], "p281": [6, 7], "p282": [6, 7], "p283": [6, 7], "p284": [6, 7], "p285": [6, 7], "p286": [6, 7], "p287": [6, 7], "p288": [6, 7], "p289": 7, "p29": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p290": 7, "p291": 7, "p292": 7, "p293": 7, "p294": 7, "p295": 7, "p296": 7, "p297": 7, "p298": 7, "p299": 7, "p2clk": 69, "p2cmdclk": 69, "p2cmden": 69, "p2en": 69, "p3": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p30": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p300": 7, "p301": 7, "p302": 7, "p303": 7, "p304": 7, "p305": 7, "p306": 7, "p307": 7, "p308": 7, "p309": 7, "p31": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p310": 7, "p311": 7, "p312": 7, "p313": 7, "p314": 7, "p315": 7, "p316": 7, "p317": 7, "p318": 7, "p319": 7, "p32": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p3clk": 69, "p3cmdclk": 69, "p3cmden": 69, "p3en": 69, "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p4clk": 69, "p4cmdclk": 69, "p4cmden": 69, "p4en": 69, "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p5clk": 69, "p5cmdclk": 69, "p5cmden": 69, "p5en": 69, "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p_d": 81, "packag": [11, 17, 33, 36, 56, 144, 147, 156, 164, 166], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 122, 137, 147, 156, 165, 167], "pair": [17, 58, 82, 96, 104, 108, 122, 137, 144, 147, 156], "parallel": [16, 108, 122, 137, 147], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 156, 157, 158, 159, 160, 161, 162], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 122, 144, 157, 158, 159, 160, 161, 162, 164, 166], "partial": [34, 81, 96, 166], "particip": 36, "particular": [17, 156], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 132, 144, 150, 151, 153, 154], "pass0": [64, 71], "pass00000000": 102, "pass00000000000001": 113, "pass00000000001": 113, "pass00000001": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 115, "path": [36, 81], "pattern": [87, 115, 130, 143], "pattern0": [115, 130, 143], "pbbaseptr": 123, "pbcapabilitydw0basepow": 123, "pbcapabilitydw0datascal": 123, "pbcapabilitydw0pmst": 123, "pbcapabilitydw0pmsubst": 123, "pbcapabilitydw0powerrail": 123, "pbcapabilitydw0typ": 123, "pbcapabilitydw1basepow": 123, "pbcapabilitydw1datascal": 123, "pbcapabilitydw1pmst": 123, "pbcapabilitydw1pmsubst": 123, "pbcapabilitydw1powerrail": 123, "pbcapabilitydw1typ": 123, "pbcapabilitydw2basepow": 123, "pbcapabilitydw2datascal": 123, "pbcapabilitydw2pmst": 123, "pbcapabilitydw2pmsubst": 123, "pbcapabilitydw2powerrail": 123, "pbcapabilitydw2typ": 123, "pbcapabilitydw3basepow": 123, "pbcapabilitydw3datascal": 123, "pbcapabilitydw3pmst": 123, "pbcapabilitydw3pmsubst": 123, "pbcapabilitydw3powerrail": 123, "pbcapabilitydw3typ": 123, "pbcapabilitynextptr": 123, "pbcapabilitysystemalloc": 123, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 157, 158, 165], "pc84": [18, 29, 34], "pci": [44, 56, 58, 67, 78, 90, 91, 92, 120, 135, 145], "pci000": 91, "pci100": 91, "pci33_3": [57, 79], "pci33_30": [57, 93], "pci33_300": [57, 93], "pci33_30000": 93, "pci33_300000": [57, 93], "pci33_3000000": 122, "pci33_3000000000000": 122, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 122, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 122, "pci66_3000000000000": 122, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 122, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, "pci_clampiob0": 57, "pci_clampiob1": 57, "pci_clampiob3": 57, "pci_clampiob4": 57, "pci_delai": 80, "pci_express_mod": 134, "pci_express_mode_0": [66, 118, 119], "pci_express_mode_1": [66, 118, 119], "pci_express_mode_1gtp": 66, "pci_input": 57, "pci_inputiob1": 57, "pci_inputiob2": 57, "pci_inputiob3": 57, "pci_inputiob4": 57, "pci_inputiob5": 57, "pcice10": 57, "pcice_mux": 57, "pcie": [70, 117, 123, 132, 138, 144, 148], "pcie0": [66, 118, 119], "pcie2": 144, "pcie3": [144, 149], "pcie_base_ptr": [138, 148], "pcie_cap_capability_id": [138, 148], "pcie_cap_capability_vers": [70, 138, 148], "pcie_cap_device_port_typ": [70, 138, 148], "pcie_cap_int_msg_num": [70, 138], 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[17, 38, 47, 61, 72, 77, 83, 91, 156], "tr": [52, 76, 151], "transceiv": [66, 88, 89, 105, 118, 119, 133, 134, 144], "trim": 129, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 167, "unk1c": 129, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 120, 135, 145], "w": 91, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 155], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 152, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 157, "xcr3064xl": 158, "xcr3128xl": 159, "xcr3256xl": 160, "xcr3384xl": 161, "xcr3512xl": 162, "xilinx": [11, 33, 44, 164], "xor": [14, 36], "xpla3": 164, "xv": [16, 35, 36], "zia": 167}}) \ No newline at end of file +Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[45, "bram-s3"]], "BRAM.S3A": [[45, "bram-s3a"]], "BRAM.S3ADSP": [[45, "bram-s3adsp"]], "BRAM.S3E": [[45, "bram-s3e"]], "BSPI": [[146, "bspi"]], "Backbone": [[55, "backbone"], [91, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitstream": [[37, "bitstream"], [45, "bitstream"], [46, "bitstream"], [53, "bitstream"], [59, "bitstream"], [64, "bitstream"], [65, "bitstream"], [66, "bitstream"], [69, "bitstream"], [70, "bitstream"], [71, "bitstream"], [73, "bitstream"], [81, "bitstream"], [82, "bitstream"], [88, "bitstream"], [89, "bitstream"], [96, "bitstream"], [97, "bitstream"], [98, "bitstream"], [99, "bitstream"], [102, "bitstream"], [103, "bitstream"], [105, "bitstream"], [107, "bitstream"], [108, "bitstream"], [109, "bitstream"], [110, "bitstream"], [111, "bitstream"], [116, "bitstream"], [117, "bitstream"], [119, "bitstream"], [120, "bitstream"], [122, "bitstream"], [123, "bitstream"], [124, "bitstream"], [125, "bitstream"], [126, "bitstream"], [127, "bitstream"], [132, "bitstream"], [133, "bitstream"], [135, "bitstream"], [136, "bitstream"], [138, "bitstream"], [140, "bitstream"], [141, "bitstream"], [142, "bitstream"], [147, "bitstream"], [150, "bitstream"], [153, "bitstream"], [154, "bitstream"]], "Bitstream geometry": [[58, "bitstream-geometry"], [87, "bitstream-geometry"], [104, "bitstream-geometry"], [118, "bitstream-geometry"], [134, "bitstream-geometry"], [148, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [159, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [128, "bitstream-clbll"], [143, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [128, "bitstream-clblm"], [143, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_IOI": [[139, "bitstream-hclk-ioi"]], "Bitstream \u2014 HCLK_IOI_HP": [[151, "bitstream-hclk-ioi-hp"]], "Bitstream \u2014 HCLK_IOI_HR": [[151, "bitstream-hclk-ioi-hr"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[122, "bitstream-intf"], [138, "bitstream-intf"], [150, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[150, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[122, "bitstream-intf-delay"], [138, "bitstream-intf-delay"], [150, "bitstream-intf-delay"]], "Bitstream \u2014 IO": [[139, "bitstream-io"]], "Bitstream \u2014 IOI tile": [[68, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[55, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[55, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[61, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[61, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[61, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[61, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[61, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PowerPC hole tiles": [[91, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[61, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[38, "bitstream-bottom-tiles"], [47, "bitstream-bottom-tiles"], [83, "bitstream-bottom-tiles"]], "Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [126, "block-ram"], [141, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [160, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [170, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [158, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[158, "clkh"]], "CLKL": [[80, "clkl"], [158, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [158, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [158, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[158, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_BALI_REBUF": [[144, "clk-bali-rebuf"]], "CLK_BUFG": [[144, "clk-bufg"]], "CLK_BUFG_REBUF": [[144, "clk-bufg-rebuf"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"], [144, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CMT": [[114, "cmt"], [130, "cmt"], [145, "cmt"]], "CMT_BUFG_BOT": [[129, "cmt-bufg-bot"]], "CMT_BUFG_TOP": [[129, "cmt-bufg-top"]], "CMT_FIFO": [[145, "cmt-fifo"]], "CNR.BL": [[76, "cnr-bl"], [155, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [155, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [155, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [155, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [115, "cor"], [131, "cor"], [146, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [115, "cor1"], [131, "cor1"], [146, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [115, "ctl"], [131, "ctl"], [146, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[131, "ctl1"], [146, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [118, "center-column"], [134, "center-column"]], "Center column and configuration center": [[148, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"], [129, "clock-interconnect"], [144, "clock-interconnect"]], "Clock management tile": [[114, "clock-management-tile"], [130, "clock-management-tile"], [145, "clock-management-tile"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [128, "configurable-logic-block"], [143, "configurable-logic-block"], [154, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [127, "configuration-center"], [142, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [115, "configuration-registers"], [131, "configuration-registers"], [146, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [121, null], [137, null], [149, null], [156, null], [167, null], [168, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [155, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [116, "dsp"], [132, "dsp"], [147, "dsp"]], "Database schema": [[17, "database-schema"], [160, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [167, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [160, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [118, "device-geometry"], [134, "device-geometry"], [148, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [169, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [171, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [169, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [118, "ecc"], [134, "ecc"], [148, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[117, "ethernet-macs"], [133, "ethernet-macs"]], "FB columns and rows": [[171, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[171, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[159, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[159, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[159, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [159, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[159, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTH transceivers": [[135, "gth-transceivers"]], "GTP and GTX right column holes": [[148, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[119, "gtp-transceivers"]], "GTX transceivers": [[120, "gtx-transceivers"], [136, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [118, "general-structure"], [134, "general-structure"], [148, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [161, "global-bits"], [162, "global-bits"], [163, "global-bits"], [164, "global-bits"], [165, "global-bits"], [166, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [129, "hclk"], [144, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [123, "i-o-banks-and-special-functions"], [139, "i-o-banks-and-special-functions"], [151, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [161, "i-o-pins"], [162, "i-o-pins"], [163, "i-o-pins"], [164, "i-o-pins"], [165, "i-o-pins"], [166, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [170, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [161, "imux-bits"], [162, "imux-bits"], [163, "imux-bits"], [164, "imux-bits"], [165, "imux-bits"], [166, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[148, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [157, "io-b"]], "IO.L": [[79, "io-l"], [157, "io-l"]], "IO.R": [[79, "io-r"], [157, "io-r"]], "IO.T": [[79, "io-t"], [157, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [170, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [170, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [123, "input-output"], [139, "input-output"], [151, "input-output"], [157, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [171, "input-output-buffer"]], "Interconnect": [[122, "interconnect"], [138, "interconnect"], [150, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [169, "introduction"]], "JED bits": [[160, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [159, "jed-mapping"], [161, "jed-mapping"], [162, "jed-mapping"], [163, "jed-mapping"], [164, "jed-mapping"], [165, "jed-mapping"], [166, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[159, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[159, "jed-mapping-macrocells-without-iob"]], "JED structure": [[159, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [170, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[171, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MMCM Tables": [[145, "mmcm-tables"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [171, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[148, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [171, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [171, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[152, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[153, "pci-express-gen3-cores"]], "PCI Express cores": [[124, "pci-express-cores"], [140, "pci-express-cores"]], "PCI Express holes": [[148, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[152, "pcie-l"]], "PCIE_R": [[152, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PLL Tables": [[145, "pll-tables"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[129, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [169, "packages"]], "Part": [[17, "part"], [160, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[125, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [118, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[148, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [171, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [170, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [171, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [160, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [161, "speed-data"], [162, "speed-data"], [163, "speed-data"], [164, "speed-data"], [165, "speed-data"], [166, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [118, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], 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110, 126, 141], "9998": [45, 59, 81, 96, 110, 126, 141], "9999": [45, 59, 81, 96, 110, 126, 141], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 159, "9fb_group": [161, 162, 163, 164, 165, 166], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 159, "9reg_d_ireg": 159, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 124, 127, 142, 152, 153], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 117, 125, 130, 133, 140, 144], "9rowcolumn01234567891011121314151617181920212223242526272829": [114, 135, 136, 145, 152], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [119, 120], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 118, 123, 134, 139, 148, 151, 160, 171], "AED": [12, 169], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 171], "As": [35, 134, 171], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 118, 134, 148, 171], "ISE": [35, 171], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 118, 134, 139, 148, 171], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 118, 123, 134, 139, 148, 151, 171], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 118, 134, 139, 148, 151, 160, 169, 171], "Its": [35, 81], "No": 148, "Not": [15, 16, 36, 55, 91, 171], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 148, 171], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 118, 134, 139, 148, 151], "These": [36, 91, 139, 148], "To": [35, 36, 96], "_": [17, 34, 36, 160, 171], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 159, 171], "_gclk": 171, "_init": [46, 82], "_inv": [36, 171], "_lct": 171, "_mc": [12, 169], "_mux": [36, 46, 82], "_none": 171, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a17": [6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a18": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a19": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a20": [6, 7, 22, 23, 24, 165, 166], "a21": [6, 7, 22, 23, 165, 166], "a22": [6, 7, 22, 23, 165, 166], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5ffinit": [128, 143], "a5ffinitslice0": [128, 143], "a5ffmux": [128, 143], "a5ffsr": [128, 143], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 128, "a5q0": 60, "a5q0100": [60, 128, 143], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a6lut": [60, 112, 128, 143], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a_dfeclkdlyadj": 136, "a_dfedlyovrd": 136, "a_dfedlyovrdgtx0": 136, "a_dfedlyovrdgtx1": 136, "a_dfedlyovrdgtx2": 136, "a_dfedlyovrdgtx3": 136, "a_dfetap1": 136, "a_dfetap2": 136, "a_dfetap3": 136, "a_dfetap4": 136, "a_dfetapovrd": 136, "a_dfetapovrdgtx0": 136, "a_dfetapovrdgtx1": 136, "a_dfetapovrdgtx2": 136, "a_dfetapovrdgtx3": 136, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 136, "a_gtxrxresetgtx0": 136, "a_gtxrxresetgtx1": 136, "a_gtxrxresetgtx2": 136, "a_gtxrxresetgtx3": 136, "a_gtxtxreset": 136, "a_gtxtxresetgtx0": 136, "a_gtxtxresetgtx1": 136, "a_gtxtxresetgtx2": 136, "a_gtxtxresetgtx3": 136, "a_input": [116, 132, 147], "a_loopback": 136, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 136, "a_pllclkrxresetgtx0": 136, "a_pllclkrxresetgtx1": 136, "a_pllclkrxresetgtx2": 136, "a_pllclkrxresetgtx3": 136, "a_pllclktxreset": 136, "a_pllclktxresetgtx0": 136, "a_pllclktxresetgtx1": 136, "a_pllclktxresetgtx2": 136, "a_pllclktxresetgtx3": 136, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 136, "a_pllrxresetgtx0": 136, "a_pllrxresetgtx1": 136, "a_pllrxresetgtx2": 136, "a_pllrxresetgtx3": 136, "a_plltxreset": 136, "a_plltxresetgtx0": 136, "a_plltxresetgtx1": 136, "a_plltxresetgtx2": 136, "a_plltxresetgtx3": 136, "a_prbscntreset": 136, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 136, "a_prbscntresetgtx1": 136, "a_prbscntresetgtx2": 136, "a_prbscntresetgtx3": 136, "a_q": 81, "a_rxbufreset": 136, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 136, "a_rxbufresetgtx1": 136, "a_rxbufresetgtx2": 136, "a_rxbufresetgtx3": 136, "a_rxcdrfreqreset": 136, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 136, "a_rxcdrfreqresetgtx1": 136, "a_rxcdrfreqresetgtx2": 136, "a_rxcdrfreqresetgtx3": 136, "a_rxcdrhold": 136, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 136, "a_rxcdrholdgtx1": 136, "a_rxcdrholdgtx2": 136, "a_rxcdrholdgtx3": 136, "a_rxcdrphasereset": 136, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 136, "a_rxcdrphaseresetgtx1": 136, "a_rxcdrphaseresetgtx2": 136, "a_rxcdrphaseresetgtx3": 136, "a_rxcdrreset": 136, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 136, "a_rxcdrresetgtx1": 136, "a_rxcdrresetgtx2": 136, "a_rxcdrresetgtx3": 136, "a_rxdfereset": 136, "a_rxdferesetgtx0": 136, "a_rxdferesetgtx1": 136, "a_rxdferesetgtx2": 136, "a_rxdferesetgtx3": 136, "a_rxenpmaphasealign": 136, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 136, "a_rxenpmaphasealigngtx1": 136, "a_rxenpmaphasealigngtx2": 136, "a_rxenpmaphasealigngtx3": 136, "a_rxenprbstst": 136, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 136, "a_rxensamplealigngtx0": 136, "a_rxensamplealigngtx1": 136, "a_rxensamplealigngtx2": 136, "a_rxensamplealigngtx3": 136, "a_rxeqmix": 136, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 136, "a_rxplllkdetengtx0": 136, "a_rxplllkdetengtx1": 136, "a_rxplllkdetengtx2": 136, "a_rxplllkdetengtx3": 136, "a_rxpllpowerdown": 136, "a_rxpllpowerdowngtx0": 136, "a_rxpllpowerdowngtx1": 136, "a_rxpllpowerdowngtx2": 136, "a_rxpllpowerdowngtx3": 136, "a_rxpmasetphas": 136, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 136, "a_rxpmasetphasegtx1": 136, "a_rxpmasetphasegtx2": 136, "a_rxpmasetphasegtx3": 136, "a_rxpolar": 136, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 136, "a_rxpolaritygtx1": 136, "a_rxpolaritygtx2": 136, "a_rxpolaritygtx3": 136, "a_rxpowerdown": 136, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 136, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 136, "a_rxresetgtx1": 136, "a_rxresetgtx2": 136, "a_rxresetgtx3": 136, "a_txbufdiffctrl": 136, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 136, "a_txdeemphgtx0": 136, "a_txdeemphgtx1": 136, "a_txdeemphgtx2": 136, "a_txdeemphgtx3": 136, "a_txdiffctrl": 136, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 136, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 136, "a_txelecidlegtx1": 136, "a_txelecidlegtx2": 136, "a_txelecidlegtx3": 136, "a_txenpmaphasealign": 136, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 136, "a_txenpmaphasealigngtx1": 136, "a_txenpmaphasealigngtx2": 136, "a_txenpmaphasealigngtx3": 136, "a_txenprbstst": 136, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 136, "a_txplllkdeten": 136, "a_txplllkdetengtx0": 136, "a_txplllkdetengtx1": 136, "a_txplllkdetengtx2": 136, "a_txplllkdetengtx3": 136, "a_txpllpowerdown": 136, "a_txpllpowerdowngtx0": 136, "a_txpllpowerdowngtx1": 136, "a_txpllpowerdowngtx2": 136, "a_txpllpowerdowngtx3": 136, "a_txpmasetphas": 136, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 136, "a_txpmasetphasegtx1": 136, "a_txpmasetphasegtx2": 136, "a_txpmasetphasegtx3": 136, "a_txpolar": 136, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 136, "a_txpolaritygtx1": 136, "a_txpolaritygtx2": 136, "a_txpolaritygtx3": 136, "a_txpostemphasi": 136, "a_txpowerdown": 136, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 136, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 136, "a_txprbsforceerrgtx1": 136, "a_txprbsforceerrgtx2": 136, "a_txprbsforceerrgtx3": 136, "a_txpreemphasi": 136, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 136, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 136, "a_txresetgtx1": 136, "a_txresetgtx2": 136, "a_txresetgtx3": 136, "a_txsw": 136, "a_txswinggtx0": 136, "a_txswinggtx1": 136, "a_txswinggtx2": 136, "a_txswinggtx3": 136, "aa1": [6, 7, 22, 23, 165, 166], "aa10": [6, 7, 165, 166], "aa11": [6, 7, 165, 166], "aa12": [6, 7, 165, 166], "aa13": [6, 7, 165, 166], "aa14": [6, 7, 165, 166], "aa15": [6, 7, 165, 166], "aa16": [6, 7, 165, 166], "aa17": [6, 7, 165, 166], "aa18": [6, 7, 165, 166], "aa19": [6, 7, 165, 166], "aa2": [6, 7, 22, 23, 165, 166], "aa20": [6, 7, 165, 166], "aa21": [6, 7, 165, 166], "aa22": [6, 7, 165, 166], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 165, 166], "aa4": [6, 7, 22, 23, 165, 166], "aa5": [6, 7, 165, 166], "aa6": [6, 7, 165, 166], "aa7": [6, 7, 165, 166], "aa8": [6, 7, 165, 166], "aa9": [6, 7, 165, 166], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 165, 166], "ab10": [6, 7, 165, 166], "ab11": [6, 7, 165, 166], "ab12": [6, 7, 165, 166], "ab13": [6, 7, 165, 166], "ab14": [6, 7, 165, 166], "ab15": [6, 7, 165, 166], "ab16": [6, 7, 165, 166], "ab17": [6, 7, 165, 166], "ab18": [6, 7, 165, 166], "ab19": [6, 7, 165, 166], "ab2": [6, 7, 22, 23, 165, 166], "ab20": [6, 7, 165, 166], "ab21": [6, 7, 165, 166], "ab22": [6, 7, 165, 166], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 165, 166], "ab4": [6, 7, 22, 23, 165, 166], "ab5": [6, 7, 165, 166], "ab6": [6, 7, 165, 166], "ab7": [6, 7, 165, 166], "ab8": [6, 7, 165, 166], "ab9": [6, 7, 165, 166], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 148, 151, 171], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 160, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 136, "ac_cap_dis_0": [66, 119, 120], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 119, "ac_cap_dis_0gtx_du": 120, "ac_cap_dis_1": [66, 119, 120], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 119, "ac_cap_dis_1gtx_du": 120, "ac_cap_disgtx0": 136, "ac_cap_disgtx1": 136, "ac_cap_disgtx2": 136, "ac_cap_disgtx3": 136, "acb": [12, 34, 169], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 169, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 118, 134, 148, 151, 160, 169, 171], "activ": [35, 36, 46, 82, 170], "activelanesin": 124, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 118, 134, 148, 171], "acy0": [60, 112, 128, 143], "acy0slice0": [112, 128, 143], "acy0slice1": [60, 128], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 118, 134, 148, 171], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 118, 134], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 72, "addr_cascade_out_a": 141, "addr_cascade_out_abram": 141, "addr_cascade_out_b": 141, "addr_cascade_out_bbram": 141, "addra0": 72, "addra1": 72, "addra10": 72, "addra11": 72, "addra2": 72, "addra3": 72, "addra4": 72, "addra5": 72, "addra6": 72, "addra7": 72, "addra8": 72, "addra9": 72, "addral0": 141, "addral1": 141, "addral10": 141, "addral11": 141, "addral12": 141, "addral13": 141, "addral14": 141, "addral2": 141, "addral3": 141, "addral4": 141, "addral5": 141, "addral6": 141, "addral7": 141, "addral8": 141, "addral9": 141, "addrau0": 141, "addrau1": 141, "addrau10": 141, "addrau11": 141, "addrau12": 141, "addrau13": 141, "addrau14": 141, "addrau2": 141, "addrau3": 141, "addrau4": 141, "addrau5": 141, "addrau6": 141, "addrau7": 141, "addrau8": 141, "addrau9": 141, "addrb0": 72, "addrb1": 72, "addrb10": 72, "addrb11": 72, "addrb2": 72, "addrb3": 72, "addrb4": 72, "addrb5": 72, "addrb6": 72, "addrb7": 72, "addrb8": 72, "addrb9": 72, "addrbl0": 141, "addrbl1": 141, "addrbl10": 141, "addrbl11": 141, "addrbl12": 141, "addrbl13": 141, "addrbl14": 141, "addrbl2": 141, "addrbl3": 141, "addrbl4": 141, "addrbl5": 141, "addrbl6": 141, "addrbl7": 141, "addrbl8": 141, "addrbl9": 141, "addrbu0": 141, "addrbu1": 141, "addrbu10": 141, "addrbu11": 141, "addrbu12": 141, "addrbu13": 141, "addrbu14": 141, "addrbu2": 141, "addrbu3": 141, "addrbu4": 141, "addrbu5": 141, "addrbu6": 141, "addrbu7": 141, "addrbu8": 141, "addrbu9": 141, "address": [15, 16, 35, 46, 81, 82, 91, 96], "adi1mux": [60, 112, 128, 143], "adi1muxslice0": [60, 112, 128], "adjac": [55, 91, 96, 148, 151], "adreg": [132, 147], "adregdsp0": 132, "adregdsp1": 132, "adv_b": 151, "advanc": 14, "ae1": [22, 23], "ae10": [22, 23], "ae11": [22, 23], "ae12": [22, 23], "ae13": [22, 23], "ae14": [22, 23], "ae15": [22, 23], "ae16": [22, 23], "ae17": [22, 23], "ae18": [22, 23], "ae19": [22, 23], "ae2": [22, 23], "ae20": [22, 23], "ae21": [22, 23], "ae22": [22, 23], "ae23": [22, 23], "ae24": [22, 23], "ae25": [22, 23], "ae26": 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[22, 23], "af22": [22, 23], "af23": [22, 23], "af24": [22, 23], "af25": [22, 23], "af26": [22, 23], "af3": [22, 23], "af4": [22, 23], "af5": [22, 23], "af6": [22, 23], "af7": [22, 23], "af8": [22, 23], "af9": [22, 23], "aff_latch": 128, "aff_latchslice0": 128, "affect": [36, 91, 148, 171], "affinit": [112, 128, 143], "affinitslice0": [112, 128, 143], "affinitslice1": 128, "affmux": [60, 112, 128, 143], "affmuxslice1": 60, "affsr": [112, 128, 143], "affsrinit": 60, "affsrinitslice0": 60, "affsrinitslice1": 60, "affsrslice0": 143, "affsrslice1": [128, 143], "after": [35, 36, 55, 91, 104, 118], "afterward": 171, "ag": 35, "again": [35, 91], "agp": 79, "agp0": 93, "agp00011": 79, "agp0100101011": 93, "agp0111": 79, "agp011101010": 79, "agp011101011": 79, "agp1111": 93, "ai1": [128, 143], "aim": 11, "align": [96, 148], "align_comma_msb": 88, "align_comma_word": [89, 105, 136], "align_comma_word_0": [66, 119, 120], "align_comma_word_0gtp": 66, "align_comma_word_0gtp_du": 119, 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134, 139, 148, 151, 159, 160, 169, 171], "alt": [46, 82], "alt0": [37, 46, 60, 82, 99, 112, 128, 143], "alt00010001": 107, "alt0010001": 107, "altdig": [46, 82], "altern": [46, 82, 148], "alumode0": [116, 132, 147], "alumode0dsp0": 116, "alumode0dsp1": 116, "alumode1": [116, 132, 147], "alumode2": [116, 132, 147], "alumode2dsp0": 147, "alumode2dsp1": 147, "alumode3": [116, 132, 147], "alumode3dsp0": [116, 132], "alumode3dsp1": 132, "alumodereg": [116, 132, 147], "alwai": [12, 14, 17, 35, 36, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 139, 148, 160, 171], "amount": [58, 87, 104], "an": [12, 14, 15, 17, 34, 35, 36, 46, 55, 56, 58, 81, 87, 91, 92, 96, 148, 151, 159, 160, 169, 170, 171], "analog": [55, 91, 108, 123, 139, 151], "analog_misc": [130, 145], "analog_read111": 63, "and1": [37, 46], "ani": [35, 36, 46, 55, 58, 87, 91, 108, 123, 148, 171], "anoth": [46, 82, 91, 104, 118, 134, 148, 151], "anyth": [35, 82], "anywai": [55, 148], "anywher": 148, "ao_toggl": 145, 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171], "arbitrarili": 12, "architectur": [104, 169], "area": [15, 16, 35, 45, 47, 55, 58, 81, 83, 87, 91, 96, 104, 118, 134, 148, 159, 160, 171], "areg": [45, 81, 103], "areg_acascreg": [116, 132, 147], "aren": [55, 58, 151], "ari_cap_en": 153, "ari_cap_enablepcie3": 153, "arm": 148, "around": [91, 104, 134], "arrai": [35, 159, 160, 171], "arrang": [151, 159], "array_mod": 145, "array_mode_4_x_40": 145, "array_mode_4_x_81": 145, "array_mode_8_x_41": 145, "array_modein_fifo": 145, "ascii": 171, "assembl": [46, 82], "assert": [15, 16], "assign": [13, 15, 16, 58, 87, 104, 118, 134, 148, 171], "associ": [12, 34, 36, 37, 42, 46, 55, 58, 82, 87, 91, 99, 104, 108, 118, 123, 134, 148, 160, 169, 170, 171], "async": [14, 36, 81, 171], "async1": [53, 61, 65, 144, 145], "async11": [45, 59], "asynchron": [46, 56, 82, 171], "atbbumpen": 105, "atben": 105, "atbsel": 105, "attempt": 35, "attribut": [45, 46, 81, 82, 96], "auto": 35, "auto01": 136, "auto_c": 105, "auto_calgt11a": 105, "auto_calgt11b": 105, "auto_dps00": [102, 114], "auto_zd211": [102, 114], "autoincr": 35, "automot": [12, 34], "autoreset_over_under_flow": 116, "autoreset_patdet": [132, 147], "autoreset_pattern_detect": 116, "autoreset_pattern_detect_optinv": 116, "autoreset_pattern_detectdsp0": 116, "aux": [2, 3, 4, 5, 6, 7, 8, 9], "auxiliari": [108, 123, 139, 151], "avail": [17, 55, 91, 104, 118, 134, 148, 160], "avdd_comp_set": [130, 145], "avdd_vbg_pd": [130, 145], "avdd_vbg_sel": [130, 145], "ave_freq_lock1": 114, "ave_freq_lock10": 102, "awai": [104, 118, 148], "ax0": [60, 112, 128, 143], "ax01": [60, 112, 128, 143], "ax0100": [112, 128, 143], "ax1": [60, 112], "ax10": [128, 143], "ax1010": 60, "axisten_if_cc_alignment_mod": 153, "axisten_if_cc_alignment_modepcie3": 153, "axisten_if_cc_parity_chk": 153, "axisten_if_cq_alignment_mod": 153, "axisten_if_enable_client_tag": 153, "axisten_if_enable_msg_rout": 153, "axisten_if_enable_rx_msg_intfc": 153, "axisten_if_rc_alignment_mod": 153, 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151, "bufio1": [113, 151], "bufio100000001000": 113, "bufio111": 100, "bufio1_i0000000000000010": 139, "bufio1_i00000010": 151, "bufio2": [113, 151], "bufio200000010000": 113, "bufio2_0": 61, "bufio2_1": 61, "bufio2_2": 61, "bufio2_3": 61, "bufio2_4": 61, "bufio2_5": 61, "bufio2_6": 61, "bufio2_7": 61, "bufio2_bt001010": 64, "bufio2_bt0_40000": 71, "bufio2_bt101011": 64, "bufio2_bt1_50001": 71, "bufio2_bt201100": 64, "bufio2_bt2_60010": 71, "bufio2_bt301111": 64, "bufio2_bt3_70011": 71, "bufio2_bt410000": 64, "bufio2_bt510001": 64, "bufio2_bt610010": 64, "bufio2_bt710011": 64, "bufio2_i0000000000000100": 139, "bufio2_i00000100": 151, "bufio2_lr000000": 64, "bufio2_lr0_40101": 71, "bufio2_lr100001": 64, "bufio2_lr1_50110": 71, "bufio2_lr200010": 64, "bufio2_lr2_60111": 71, "bufio2_lr300011": 64, "bufio2_lr3_71111": 71, "bufio2_lr400100": 64, "bufio2_lr500111": 64, "bufio2_lr601000": 64, "bufio2_lr701001": 64, "bufio2fb_bt000000": 71, "bufio2fb_bt001010": 64, "bufio2fb_bt100001": 71, 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5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c20": [6, 7, 22, 23, 24, 165, 166], "c21": [6, 7, 22, 23, 165, 166], "c22": [6, 7, 22, 23, 165, 166], "c23": [22, 23], "c24": [22, 23], "c25": [22, 23], "c26": [22, 23], "c3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c5ffinit": [128, 143], "c5ffinitslice0": [128, 143], "c5ffmux": [128, 143], "c5ffsr": [128, 143], "c5ffsrinit": 60, "c5ffsrinitslice0": 60, "c5ffsrslice0": 128, "c5ffsrslice1": 128, "c5q0": 60, "c5q0100": [60, 128, 143], "c6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c6lut": [60, 112, 128, 143], "c7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 162, 163, 164, 165, 166], "c9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "cal_ba": 69, "cal_bypass": 69, "cal_ca": 69, "cal_calibration_mod": 69, "cal_clk_div": 69, "cal_delai": 69, "cal_ra": 69, "calcul": [15, 16], "calibration0": 69, "call": [36, 55, 58, 87, 91, 134, 148, 171], "came": [35, 91], "can": [12, 14, 17, 34, 35, 36, 46, 55, 56, 58, 81, 82, 87, 91, 96, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "cannot": [35, 46, 82, 96, 134, 148, 171], "cap": 76, "capabilities_ptr": [140, 152], "capabilitiespoint": 124, "capabl": [12, 34, 46, 92, 96, 108, 123, 139, 151], "captur": [39, 46, 48, 49, 56, 75, 82, 84, 92, 101, 115, 131, 146, 170], "cardbus_cis_point": [70, 140, 152], "cardbuscispoint": 124, "cardin": [55, 91], "care": 35, "carri": [54, 90], "carryin": [103, 116, 132, 147], "carryin0": [53, 65], "carryindsp0": [116, 132], "carryindsp1": [116, 132], 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145], "clkinsel_mod": [71, 114], "clkinsel_modepl": [71, 114], "clkinsel_stat": [71, 114], "clkinsel_staticpl": [71, 114], "clkinselmmcm0": 130, "clkinselmmcm1": 130, "clkinselpl": 145, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 155, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 156], "clkout0000": [71, 130], "clkout0001": 130, "clkout001": 145, "clkout01000": 145, "clkout0_deskew_adjust": 114, "clkout0_dt": [130, 145], "clkout0_edg": [130, 145], "clkout0_edgemmcm": 145, "clkout0_edgemmcm0": 130, "clkout0_edgemmcm1": 130, "clkout0_edgepl": 145, "clkout0_en": [130, 145], "clkout0_enmmcm": 145, "clkout0_enmmcm0": 130, "clkout0_enmmcm1": 130, "clkout0_enpl": 145, "clkout0_frac": [130, 145], "clkout0_frac_en": [130, 145], "clkout0_frac_enmmcm": 145, "clkout0_frac_enmmcm0": 130, "clkout0_frac_enmmcm1": 130, "clkout0_frac_wf": 130, "clkout0_frac_wf_fal": 145, "clkout0_frac_wf_fallmmcm": 145, "clkout0_frac_wf_ris": 145, "clkout0_frac_wf_risemmcm": 145, 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[130, 145], "clkout6_lt": [130, 145], "clkout6_mx": [130, 145], "clkout6_nocount": [130, 145], "clkout6_nocountmmcm": 145, "clkout6_nocountmmcm0": 130, "clkout6_nocountmmcm1": 130, "clkout6_pm": [130, 145], "clkout6_use_fine_p": [130, 145], "clkout6_use_fine_psmmcm": 145, "clkout6_use_fine_psmmcm0": 130, "clkout6_use_fine_psmmcm1": 130, "clkout_div": 145, "clkout_div_st": 145, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [119, 120], "clkout_north_s0": [119, 120], "clkout_north_s101": [119, 120], "clkout_phase_shift": 64, "clkout_south": [119, 120], "clkout_south_n0": [119, 120], "clkout_south_n001": [119, 120], "clkout_west": 66, "clkout_westgtp": 66, "clkoutdcm0000": 114, "clkoutdcm1100": 114, "clkoutdcm2001": 114, "clkoutdcm3101": 114, "clkoutdcm4010": 114, "clkoutdcm5110": 114, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [119, 120], "clkpn1": [119, 120], "clkr": [58, 78, 156], "clkrcv_trst": [120, 136], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 136, "clkrcv_trstgtx_dual": 120, "clkslice0": 112, "clkslice1": [60, 128], "clkt": [58, 78, 87, 156], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 136, "clktestsig1": 135, "clktestsig11": 136, "clktestsig1111": 136, "clktestsig_sel": 135, "clktestsig_selgth": 135, "clkv": [78, 156], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 118, 121, 123, 134, 137, 139, 148, 149, 151, 160, 169, 171], "clock_delai": 125, "clock_hold": 130, "clock_holdmmcm0": 130, "clock_holdmmcm1": 130, "clock_invert_m": 116, "clock_invert_p": 116, "clock_invert_pdsp1": 116, "clockwis": [58, 87], "close": [58, 81, 134, 148], "closest": 58, "clr0": 154, "clrmux": 154, "clrmuxlc0": 154, "clrmuxlc1": 154, "clrmuxlc2": 154, "clrmuxlc3": 154, "cm_trim": 136, "cm_trim_0": [66, 120], "cm_trim_1": [66, 120], "cmd_intx_impl": [140, 152], "cmd_intx_implementedpci": [140, 152], "cmd_offset": 145, "cmo": 14, "cmos0": 155, "cmos00": [74, 79], "cmos00111": 139, "cmos01": 74, "cmos111": [57, 93, 108, 123], "cmos1200011": 139, "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 118, 121, 123, 134, 137, 148, 149], "cmt0": 61, "cmt10": 61, "cmt_bot": 145, "cmt_bufg_": 134, "cmt_bufg_bot": [134, 137], "cmt_bufg_top": [134, 137], "cmt_clk010000000001000": 113, "cmt_clk100000010001000": 113, "cmt_clk1000001000010000": 113, "cmt_clk1100100000010000": 113, "cmt_clk1200000001010000": 113, "cmt_clk1300000100010000": 113, "cmt_clk1400010000010000": 113, "cmt_clk1501000000010000": 113, "cmt_clk1610000000100000": 113, "cmt_clk1700000010100000": 113, "cmt_clk1800001000100000": 113, "cmt_clk1900100000100000": 113, "cmt_clk2000000001100000": 113, "cmt_clk200001000001000": 113, "cmt_clk2100000100100000": 113, "cmt_clk2200010000100000": 113, "cmt_clk2301000000100000": 113, "cmt_clk2410000000000010": 113, "cmt_clk2500000010000010": 113, "cmt_clk2600001000000010": 113, "cmt_clk2700100000000010": 113, "cmt_clk300100000001000": 113, "cmt_clk400000001001000": 113, "cmt_clk500000100001000": 113, "cmt_clk600010000001000": 113, "cmt_clk701000000001000": 113, "cmt_clk810000000010000": 113, "cmt_clk900000010010000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_fifo": 149, "cmt_pll": 71, "cmt_top": 145, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 155, "cmuxosc": 155, "cnr": [58, 78, 87, 156], "co01": 154, "co1": 154, "co_dur": 145, "coarse_bypass": 145, "coarse_delai": 145, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 118, 134, 148], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 123, 139, 151, 159, 160, 161, 162, 163, 164, 165, 166, 168, 170], "columnar": 104, "com": [51, 86], "com_burst_v": 136, "com_burst_val_0": [66, 119, 120], "com_burst_val_1": [66, 119, 120], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 171], "combination": 81, "combinatori": [14, 36, 171], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 118, 123, 134, 148, 169, 171], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 136, "comma_10b_enable_0": [66, 119, 120], "comma_10b_enable_1": [66, 119, 120], "comma_10b_mask": [88, 89, 105], "comma_doubl": 136, "comma_double_0": [119, 120], "comma_double_0gtp_du": 119, "comma_double_0gtx_du": 120, "comma_double_1": [119, 120], "comma_double_1gtp_du": 119, "comma_double_1gtx_du": 120, "comma_doublegtx0": 136, "comma_doublegtx1": 136, "comma_doublegtx2": 136, "comma_doublegtx3": 136, "commerci": [17, 160], "common": [100, 151], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [148, 159], "companion": [44, 106], "compat": [12, 34, 169], "compens": 82, "complement": [108, 123, 139, 151], "complet": [12, 13, 16, 34, 35, 36, 104, 148, 159, 169], "complex": [15, 16, 148], "comput": [81, 159], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86, 102, 114], "concur00100101": 102, "concur1001": [64, 114], "concurdcm": [51, 86, 102], "concurdcm0": 114, "concurdcm1": 114, "config": [15, 16, 159], "config01": 114, "config10": 102, "config_fallback": [115, 131, 146], "config_r": [39, 48, 49, 75, 84, 101, 115, 131, 146, 155], "configrout": 124, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 118, 121, 123, 134, 137, 139, 149, 151, 156, 159, 168], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 123, 139, 148, 170, 171], "consecut": 134, "consid": [35, 104, 108, 118, 123, 134, 139, 148, 151], "consist": [35, 36, 81, 104, 118, 123, 134, 139, 148], "const": [13, 14, 35, 36, 46, 82, 170, 171], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 171, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 170, 171], "content": [35, 46, 82, 134], "contigu": [15, 16], "continu": [35, 151], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "control_0": [130, 145], "control_1": [130, 145], "control_2": [130, 145], "control_3": [130, 145], "control_4": [130, 145], "control_5": [130, 145], "control_6": 145, "control_7": 145, "convert": [15, 16], "convst": 109, "convstclk": [111, 127, 142], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 159, 160, 171], "cor": [41, 54, 78, 90, 106, 121, 137, 149], "cor1": [54, 67, 121, 137, 149], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 118, 121, 137, 149, 169, 171], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 148, 156], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 118, 123, 134, 139, 148, 151, 160, 171], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 118, 134, 148, 161, 162, 163, 164, 165, 166], "cout": [46, 82, 157], "coutmux": [60, 112, 128, 143], "coutmuxslice1": 60, "cover": [104, 118, 134, 148, 151, 171], "cp": [130, 145], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 162, 169], "cp_bias_trip_set": [130, 145], "cp_bias_trip_setmmcm": 145, "cp_bias_trip_setmmcm0": 130, "cp_bias_trip_setmmcm1": 130, "cp_bias_trip_setpl": 145, "cp_re": [130, 145], "cpl_timeout_disable_support": [140, 152], "cpl_timeout_ranges_support": [140, 152], "cpld": [0, 12, 34, 36, 169, 171], "cpmc440clk": 125, "cpmc440timerclock": 125, "cpmdcrclk": 125, "cpmdma0llclk": 125, "cpmdma1llclk": 125, "cpmdma2llclk": 125, "cpmdma3llclk": 125, "cpmfcmclk": 125, "cpminterconnectclk": 125, "cpmmcclk": 125, "cpmmcm": [130, 145], "cpmppcmplbclk": 125, "cpmppcs0plbclk": 125, "cpmppcs1plbclk": 125, "cppll": 145, "crammod": [60, 112, 128, 143], "crc": [39, 48, 49, 62, 84, 101, 115, 155], "crc32_0": [119, 120], "crc32_1": [119, 120], "crc32_2": [119, 120], "crc32_3": [119, 120], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [119, 120], "crc_start_of_pkt": [88, 89], "crcclk": [119, 120], "crcclkgtp_dual": 119, "crcclkgtx_dual": 120, "creat": [55, 87, 91, 104, 118], "create_edg": [98, 111, 129, 144], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 116, 132, 147], "cregdsp": [53, 65], "cregdsp0": [116, 132], "cregdsp1": 132, "crm_core_clk_freq_500": 153, "crm_core_clk_freq_500pcie3": 153, "crm_module_rst": [140, 152], "crm_user_clk_freq": 153, "crmcoreclk": 124, "crmcoreclkdlo": 124, "crmcoreclkpci": 124, "crmcoreclkrxo": 124, "crmcoreclkrxopci": 124, "crmcoreclktxo": 124, "crmcoreclktxopci": 124, "crmuserclk": 124, "crmuserclkrxo": 124, "crmuserclktxo": 124, "cross": [58, 91, 134, 148], "cs144": [20, 21, 34, 163, 169], "cs280": [24, 25, 34, 164, 169], "cs48": [26, 27, 28, 30, 31, 34, 161, 162, 169], "cs_b": [108, 123], "csi_b": [139, 151], "cso2pin": [50, 63], "cso_b": [123, 139, 151], "cspin": [98, 111, 127], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 121, 137, 149], "ctl1": [137, 149], "ctl_mode": 145, "ctl_modephaser_in0": 145, "ctl_modephaser_in1": 145, "ctl_modephaser_in2": 145, "ctl_modephaser_in3": 145, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [122, 138, 150], "ctrl00001": [138, 150], "ctrl1": [122, 138, 150], "ctrl10010": [138, 150], "ctrl2": 122, "ctrl3": 122, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 118, 148], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 128, 143], "cx0100": [112, 128, 143], "cx1": [60, 112], "cx10": [128, 143], "cx1010": 60, "cxt": 134, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 128, 143], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 128, 143], "cyinitslice0": [73, 99, 112, 128, 143], "cyinitslice1": [37, 46, 60, 73, 112, 128, 143], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 123, 139, 145, 151, 171], "d0": [132, 147], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166, 171], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d100001": 123, "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d15": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d16": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d17": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d18": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d19": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d20": [6, 7, 22, 23, 24, 132, 147, 165, 166], "d21": [6, 7, 22, 23, 132, 147, 165, 166], "d22": [6, 7, 22, 23, 132, 147, 165, 166], "d23": [22, 23, 132, 147], "d24": [22, 23, 132, 147], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d3iob0": [108, 123], "d3iob1": [108, 123], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d4iob0": 108, "d4iob1": 108, "d4ologic0": 123, "d4ologic1": 123, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 123, 132, 147, 163, 164, 165, 166], "d5ffinit": [128, 143], "d5ffinitslice0": [128, 143], "d5ffmux": [128, 143], "d5ffsr": [128, 143], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 128, "d5ologic0": [108, 123], "d5ologic1": [108, 123], "d5q0": 60, "d5q0100": [60, 128, 143], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d6iob0": 123, "d6iob1": 123, "d6lut": [60, 112, 128, 143], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 132, 147, 161, 162, 163, 164, 165, 166], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d_in": [108, 123], "d_out_busi": 123, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 118, 121, 123, 134, 148, 155, 159, 160, 167, 171], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_ctl_a_n": 145, "data_ctl_a_nphy_control": 145, "data_ctl_b_n": 145, "data_ctl_c_n": 145, "data_ctl_c_nphy_control": 145, "data_ctl_d_n": 145, "data_ctl_n": 145, "data_ctl_nphaser_out0": 145, "data_ctl_nphaser_out1": 145, "data_ctl_nphaser_out2": 145, "data_ctl_nphaser_out3": 145, "data_l": [110, 126, 141], "data_r": [61, 108, 123], "data_rd_cycl": 145, "data_u": [110, 126, 141], "data_width": [108, 123], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 159, 168, 170, 171], "datain": 123, "datain1000": 123, "datainilogic0": 123, "datainilogic1": 123, "dataint": 155, "datap": [45, 59, 81, 96], "datap_l": [110, 126, 141], "datap_u": [110, 126, 141], "datareg": 13, "datastream": [17, 160], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 122, 138, 150, 154, 157], "dbl0001010000": 122, "dbl0001100000": 122, "dbl0010010000": 122, "dbl0010100000": 122, "dbl0100010000": 122, "dbl0100100000": 122, "dbl1000010000": 122, "dbl1000100000": 122, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 123, 139, 151], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 127], "dci_clk_enablemisc": 85, "dci_misc": [108, 123, 139], "dci_mod": [57, 93, 108, 123, 139], "dci_osc_sel": 50, "dci_t": [108, 123, 139], "dci_test_mux": 50, "dcireset": [98, 111, 127, 142], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 123, 139], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 119, 120, 127, 135, 136, 142], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 135, "dclkgtp": 66, "dclkgtp_dual": 119, "dclkgtx_dual": 120, "dclksysmon": 111, "dclkxadc": 142, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": [64, 114], "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": [71, 114], "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin001": 114, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": [64, 114], "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfb010": 114, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": [71, 114], "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": [102, 114], "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_clkdv_clkfx_alignmentdcm0": 114, "dcm_clkdv_clkfx_alignmentdcm1": 114, "dcm_clkfb_iodly_muxinsel": 114, "dcm_clkfb_iodly_muxinseldcm0": 114, "dcm_clkfb_iodly_muxinseldcm1": 114, "dcm_clkfb_iodly_muxout_sel": 114, "dcm_clkfb_iodly_muxout_seldcm0": 114, "dcm_clkfb_iodly_muxout_seldcm1": 114, "dcm_clkin_iodly_muxinsel": 114, "dcm_clkin_iodly_muxinseldcm0": 114, "dcm_clkin_iodly_muxinseldcm1": 114, "dcm_clkin_iodly_muxout_sel": 114, "dcm_clkin_iodly_muxout_seldcm0": 114, "dcm_clkin_iodly_muxout_seldcm1": 114, "dcm_clklost_en": 114, "dcm_clklost_endcm0": 114, "dcm_clklost_endcm1": 114, "dcm_com_pwc_fb_en": 114, "dcm_com_pwc_fb_endcm0": 114, "dcm_com_pwc_fb_endcm1": 114, "dcm_com_pwc_fb_tap": 114, "dcm_com_pwc_ref_en": 114, "dcm_com_pwc_ref_endcm0": 114, "dcm_com_pwc_ref_endcm1": 114, "dcm_com_pwc_ref_tap": 114, "dcm_common_msb_sel": 114, "dcm_enabl": 50, "dcm_ext_fb_en": [102, 114], "dcm_ext_fb_endcm": 102, "dcm_ext_fb_endcm0": 114, "dcm_ext_fb_endcm1": 114, "dcm_lock_high": 102, "dcm_lock_high_b": 114, "dcm_lock_high_bdcm0": 114, "dcm_lock_high_bdcm1": 114, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pll_rst_dcm": 114, "dcm_pll_rst_dcmdcm0": 114, "dcm_pll_rst_dcmdcm1": 114, "dcm_powerdown_common_en_b": 114, "dcm_powerdown_common_en_bdcm0": 114, "dcm_powerdown_common_en_bdcm1": 114, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_reg_pwrd_cfg": 114, "dcm_reg_pwrd_cfgdcm0": 114, "dcm_reg_pwrd_cfgdcm1": 114, "dcm_scanmod": 114, "dcm_scanmodedcm0": 114, "dcm_scanmodedcm1": 114, "dcm_shutdown": [48, 84, 101], "dcm_trim_cal": 114, "dcm_unused_taps_powerdown": [102, 114], "dcm_unused_taps_powerdowndcm": 102, "dcm_use_reg_readi": 114, "dcm_use_reg_readydcm0": 114, "dcm_use_reg_readydcm1": 114, "dcm_vbg_pd": [102, 114], "dcm_vbg_sel": [102, 114], "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": [102, 114], "dcm_vreg_enabledcm": 102, "dcm_vreg_enabledcm0": 114, "dcm_vreg_enabledcm1": 114, "dcm_vreg_phase_margin": 102, "dcm_vsply_valid_acc": 114, "dcm_wait_pll": 114, "dcm_wait_plldcm0": 114, "dcm_wait_plldcm1": 114, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcmt_bot": 145, "dcmt_top": 145, "dcr_autolock_en": 125, "dcr_test": 125, "dcremacclk": 117, "dcy0": [60, 112, 128, 143], "dcy0slice0": [112, 128, 143], "dcy0slice1": [60, 143], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 123], "ddr00100": 123, "ddr01": 69, "ddr01100": 123, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": [108, 123], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 136], "dec_mcomma_detect_0": [66, 119, 120], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 119, "dec_mcomma_detect_0gtx_du": 120, "dec_mcomma_detect_1": [66, 119, 120], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 119, "dec_mcomma_detect_1gtx_du": 120, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 136, "dec_mcomma_detectgtx1": 136, "dec_mcomma_detectgtx2": 136, "dec_mcomma_detectgtx3": 136, "dec_pcomma_detect": [88, 89, 105, 136], "dec_pcomma_detect_0": [66, 119, 120], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 119, "dec_pcomma_detect_0gtx_du": 120, "dec_pcomma_detect_1": [66, 119, 120], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 119, "dec_pcomma_detect_1gtx_du": 120, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 136, "dec_pcomma_detectgtx1": 136, "dec_pcomma_detectgtx2": 136, "dec_pcomma_detectgtx3": 136, "dec_valid_comma_onli": [88, 89, 105, 136], "dec_valid_comma_only_0": [66, 119, 120], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 119, "dec_valid_comma_only_0gtx_du": 120, "dec_valid_comma_only_1": [66, 119, 120], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 119, "dec_valid_comma_only_1gtx_du": 120, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 136, "dec_valid_comma_onlygtx1": 136, "dec_valid_comma_onlygtx2": 136, "dec_valid_comma_onlygtx3": 136, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 139, 148, 151, 160, 169, 171], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "default10": 123, "default_idelay_valu": 123, "default_only1011": 113, "defin": 171, "definit": 151, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [161, 162, 163, 164, 165, 166], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_pt_ut": [161, 162, 163, 164, 165, 166], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "delai": [14, 44, 47, 74, 78, 118, 121, 134, 137, 139, 148, 149], "delay0": 157, "delay_bypass": 151, "delay_bypassbufio0": 151, "delay_bypassbufio1": 151, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_line1": 114, "delay_src": 123, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 123, "delayed_mem_ref0101": 145, "delayed_phase_ref11": 145, "delayed_phase_ref1100": 145, "delayed_ref01": 145, "delayed_ref0100": 145, "delayed_write0": 141, "delayed_write00": 126, "delaymux": 157, "delaymuxint": 157, "delaymuxiob2": 157, "delaymuxiob3": 157, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 118, 134, 148, 151, 160, 170, 171], "deriv": [12, 34, 56, 92, 169, 171], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 114, 129, 130, 144, 145, 160], "descript": [45, 99], "design": [12, 36, 58, 169, 171], "deskew_adjust": [54, 64, 90, 102, 114], "despit": 148, "destin": 36, "detail": [35, 58, 87, 96, 170], "determin": [12, 34, 35, 46, 82, 171], "dev_cap2_ari_forwarding_support": 152, "dev_cap2_ari_forwarding_supportedpci": 152, "dev_cap2_atomicop32_completer_support": 152, "dev_cap2_atomicop32_completer_supportedpci": 152, "dev_cap2_atomicop64_completer_support": 152, "dev_cap2_atomicop_routing_support": 152, "dev_cap2_cas128_completer_support": 152, "dev_cap2_cas128_completer_supportedpci": 152, "dev_cap2_endend_tlp_prefix_support": 152, "dev_cap2_endend_tlp_prefix_supportedpci": 152, "dev_cap2_extended_fmt_field_support": 152, "dev_cap2_ltr_mechanism_support": 152, "dev_cap2_ltr_mechanism_supportedpci": 152, "dev_cap2_max_endend_tlp_prefix": 152, "dev_cap2_no_ro_enabled_prpr_pass": 152, "dev_cap2_tph_completer_support": 152, "dev_cap_enable_slot_pwr_limit_scal": [140, 152], "dev_cap_enable_slot_pwr_limit_scalepci": [140, 152], "dev_cap_enable_slot_pwr_limit_valu": [140, 152], "dev_cap_endpoint_l0s_lat": [70, 140, 152], "dev_cap_endpoint_l1_lat": [70, 140, 152], "dev_cap_ext_tag_support": [70, 140, 152], "dev_cap_ext_tag_supportedpci": [140, 152], "dev_cap_function_level_reset_cap": [140, 152], "dev_cap_max_payload_support": [70, 140, 152], "dev_cap_phantom_functions_support": [70, 140, 152], "dev_cap_role_based_error": [70, 140, 152], "dev_cap_rsvd_14_12": [140, 152], "dev_cap_rsvd_17_16": [140, 152], "dev_cap_rsvd_31_29": [140, 152], "dev_control_aux_power_support": [140, 152], "dev_control_aux_power_supportedpci": 152, "dev_control_ext_tag_default": 152, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 121, 123, 137, 139, 149, 151, 159, 168, 170], "device_id": 140, "devicebram": 45, "devicecapabilityendpointl0slat": 124, "devicecapabilityendpointl1lat": 124, "devicedcm": [51, 52, 86], "deviceid": 124, "deviceiodelai": 123, "devicemmcm": 130, "devicepl": 114, "deviceserialnumb": 124, "devicevalu": [47, 61], "devoid": 148, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [120, 136], "dfe_cfg": 136, "dfe_cfg_0": 120, "dfe_cfg_1": 120, "dfe_drp_en": 136, "dfe_drp_engtx0": 136, "dfe_drp_engtx1": 136, "dfe_drp_engtx2": 136, "dfe_drp_engtx3": 136, "dfe_train_ctrl_lane0": 135, "dfe_train_ctrl_lane1": 135, "dfe_train_ctrl_lane2": 135, "dfe_train_ctrl_lane3": 135, "dff": [14, 36, 171], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dff1": 15, "dff_latch": 128, "dff_latchslice0": 128, "dffce": 171, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dffinit": [112, 128, 143], "dffinitslice0": [112, 128, 143], "dffmux": [60, 112, 128, 143], "dffmuxslice1": 60, "dffsr": [112, 128, 143], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 143, "dffsrslice1": 128, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": [102, 114], "dfs_ave_freq_sample_interv": [102, 114], "dfs_c": [52, 64], "dfs_cfg_bypass": 114, "dfs_cfg_bypassdcm0": 114, "dfs_cfg_bypassdcm1": 114, "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_custom_fast_sync": 114, "dfs_early_lock": [102, 114], "dfs_early_lockdcm": 102, "dfs_early_lockdcm0": 114, "dfs_early_lockdcm1": 114, "dfs_en": 114, "dfs_en_relrst": 102, "dfs_en_relrst_b": 114, "dfs_en_relrst_bdcm0": 114, "dfs_en_relrst_bdcm1": 114, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_endcm0": 114, "dfs_endcm1": 114, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_fast_upd": 114, "dfs_fast_updatedcm0": 114, "dfs_fast_updatedcm1": 114, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102, 114], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": [64, 114], "dfs_frequency_modedcm1": [64, 114], "dfs_hardsync": 102, "dfs_hardsync_b": 114, "dfs_hf_trim_cal": 114, "dfs_jf_lower_limit": 114, "dfs_mpw_high": 114, "dfs_mpw_highdcm0": 114, "dfs_mpw_highdcm1": 114, "dfs_mpw_low": 114, "dfs_mpw_lowdcm0": 114, "dfs_mpw_lowdcm1": 114, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_osc_on_fx": 114, "dfs_osc_on_fxdcm0": 114, "dfs_osc_on_fxdcm1": 114, "dfs_oscillator_mod": [102, 114], "dfs_oscillator_modedcm0": 114, "dfs_oscillator_modedcm1": 114, "dfs_output_psdly_on_concur": 114, "dfs_output_psdly_on_concurdcm0": 114, "dfs_output_psdly_on_concurdcm1": 114, "dfs_pwrd_clkin_stop_b": 114, "dfs_pwrd_clkin_stop_bdcm0": 114, "dfs_pwrd_clkin_stop_bdcm1": 114, "dfs_pwrd_clkin_stop_sticky_b": 114, "dfs_pwrd_clkin_stop_sticky_bdcm0": 114, "dfs_pwrd_clkin_stop_sticky_bdcm1": 114, "dfs_pwrd_reply_times_out_b": 114, "dfs_pwrd_reply_times_out_bdcm0": 114, "dfs_pwrd_reply_times_out_bdcm1": 114, "dfs_ref_on_fx": 114, "dfs_ref_on_fxdcm0": 114, "dfs_ref_on_fxdcm1": 114, "dfs_skip_fin": 102, "dfs_skip_finedcm": 102, "dfs_spare": 102, "dfs_sync_to_dl": 114, "dfs_sync_to_dlldcm0": 114, "dfs_sync_to_dlldcm1": 114, "dfs_synth_clock_spe": 114, "dfs_synth_fast_synch": 114, "dfs_taptrim": 114, "dfs_tp_sel": 102, "dfs_tp_seldcm": 102, "dfs_trackmod": 102, "dfs_trackmodedcm": 102, "dfs_tweak": 114, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 46, 81, 82, 96, 154], "di0": [102, 154], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 154], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "di_dur": 145, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 148, 151, 160], "dif": [46, 82], "dif_mux": [37, 46, 82, 99], "dif_muxslice0": 99, "diff010": [108, 123], "diff10": [74, 79], "diff101": [57, 93], "diff110": 57, "diff_hp10010": 139, "diff_lp00010": 139, "differ": [16, 35, 36, 46, 55, 82, 91, 151, 169, 171], "differenti": [14, 56, 108, 123, 139, 151], "dig": [46, 82], "dig_mux": [37, 46, 82, 99], "dig_muxslice0": 99, "dig_muxslice2": 99, "digit": [44, 54, 55, 56, 67, 90, 91, 92, 106], "digrx_fwdclk": 105, "digrx_sync_mod": 105, "digrx_sync_modegt11a": 105, "digrx_sync_modegt11b": 105, "dimens": 58, "dimension": 159, "din": [139, 151], "din0": 72, "din0000": 72, "din0001": 72, "din0int": 72, "din1": 72, "din10": 72, "din1000": 72, "din10000": 72, "din10001": 72, "din1001": 72, "din10int": 72, "din11": 72, "din11001": 72, "din11010": 72, "din11int": 72, "din12": 72, "din12010": 72, "din12011": 72, "din12int": 72, "din13": 72, "din13010": 72, "din13011": 72, "din13int": 72, "din14": 72, "din14010": 72, "din14011": 72, "din14int": 72, "din15": 72, "din15000": 72, "din15011": 72, "din15int": 72, "din16": 72, "din16110": 72, "din16111": 72, "din16int": 72, "din17": 72, "din17100": 72, "din17111": 72, "din17int": 72, "din18": 72, "din18100": 72, "din18101": 72, "din18int": 72, "din19": 72, "din19100": 72, "din19101": 72, "din19int": 72, "din1int": 72, "din2": 72, "din20": 72, "din2000": 72, "din2001": 72, "din20100": 72, "din20101": 72, "din20int": 72, "din21": 72, "din21101": 72, "din21110": 72, "din21int": 72, "din22": 72, "din22110": 72, "din22111": 72, "din22int": 72, "din23": 72, "din23110": 72, "din23111": 72, "din23int": 72, "din24": 72, "din24110": 72, "din24111": 72, "din24int": 72, "din25": 72, "din25100": 72, "din25111": 72, "din25int": 72, "din26": 72, "din26100": 72, "din26101": 72, "din26int": 72, "din27": 72, "din27100": 72, "din27101": 72, "din27int": 72, "din28": 72, "din28100": 72, "din28101": 72, "din28int": 72, "din29": 72, "din29101": 72, "din29110": 72, "din29int": 72, "din2int": 72, "din3": 72, "din30": 72, "din3001": 72, "din3010": 72, "din30110": 72, "din30111": 72, "din30int": 72, "din31": 72, "din31110": 72, "din31111": 72, "din31int": 72, "din3int": 72, "din4": 72, "din4010": 72, "din4011": 72, "din4int": 72, "din5": 72, "din5010": 72, "din5011": 72, "din5int": 72, "din6": 72, "din6010": 72, "din6011": 72, "din6int": 72, "din7": 72, "din7000": 72, "din7011": 72, "din7int": 72, "din8": 72, "din8000": 72, "din8001": 72, "din8int": 72, "din9": 72, "din9000": 72, "din9001": 72, "din9int": 72, "dinpin": [98, 111, 127], "dip": [81, 96], "dipa": 96, "dipb": 96, "direct": [36, 55, 81, 91], "direct0": [45, 53, 65, 103, 116, 132, 136, 147], "direct_path_cntrl": [130, 145], "direct_path_cntrlmmcm": 145, "direct_path_cntrlmmcm0": 130, "direct_path_cntrlmmcm1": 130, "direct_path_cntrlpl": 145, "directli": [14, 17, 35, 36, 46, 58, 81, 82, 91, 160, 171], "dis_tstblclamp": 141, "dis_tstfiforst": [126, 141], "dis_vgg_reg": [131, 146], "disabl": [36, 171], "disable00": 146, "disable111": 155, "disable_aspm_l1_tim": [140, 152], "disable_aspm_l1_timerpci": [140, 152], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 140, 152], "disable_err_msg": 152, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 140, 152], "disable_id_checkpci": [140, 152], "disable_jtag": [127, 142], "disable_lane_revers": [140, 152], "disable_lane_reversalpci": 140, "disable_locked_filt": 152, "disable_ppm_filt": 152, "disable_ppm_filterpci": 152, "disable_rx_poisoned_resp": 152, "disable_rx_poisoned_resppci": 152, "disable_rx_tc_filt": [140, 152], "disable_scrambl": [70, 140, 152], "disable_scramblingpci": 152, "disable_seq_match": 145, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 171], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 134, 148], "distrubut": 134, "div12110": 69, "div2001": 69, "div201": [69, 145], "div4010": 69, "div410": [69, 145], "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divclk_edg": [130, 145], "divclk_edgemmcm": 145, "divclk_edgemmcm0": 130, "divclk_edgemmcm1": 130, "divclk_edgepl": 145, "divclk_ht": [130, 145], "divclk_lt": [130, 145], "divclk_nocount": [130, 145], "divclk_nocountmmcm": 145, "divclk_nocountmmcm0": 130, "divclk_nocountmmcm1": 130, "divclk_nocountpl": 145, "divid": [11, 12, 58, 61, 104, 118, 134, 148, 159, 171], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 169], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_cfg0": 135, "dll_cfg1": 135, "dll_clkfb_stopped_pwrd_en_b": 114, "dll_clkfb_stopped_pwrd_en_bdcm0": 114, "dll_clkfb_stopped_pwrd_en_bdcm1": 114, "dll_clkin_stopped_pwrd_en_b": 114, "dll_clkin_stopped_pwrd_en_bdcm0": 114, "dll_clkin_stopped_pwrd_en_bdcm1": 114, "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": [102, 114], "dll_deskew_lock_by1": [102, 114], "dll_deskew_lock_by1dcm": 102, "dll_deskew_lock_by1dcm0": 114, "dll_deskew_lock_by1dcm1": 114, "dll_deskew_maxtap": [102, 114], "dll_deskew_mintap": [102, 114], "dll_enabl": [51, 52, 64, 76, 86], "dll_enabledcm": [51, 52], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_etpp_hold": 114, "dll_etpp_holddcm0": 114, "dll_etpp_holddcm1": 114, "dll_fdbklost_en": 114, "dll_fdbklost_endcm0": 114, "dll_fdbklost_endcm1": 114, "dll_frequency_mod": [51, 52, 64, 86, 102, 114], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": [102, 114], "dll_pd_dly_sel": 102, "dll_period_lock_by1": [102, 114], "dll_period_lock_by1dcm": 102, "dll_period_lock_by1dcm0": 114, "dll_period_lock_by1dcm1": 114, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": [102, 114], "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": [102, 114], "dll_phase_shift_lock_by1": [102, 114], "dll_phase_shift_lock_by1dcm": 102, "dll_phase_shift_lock_by1dcm0": 114, "dll_phase_shift_lock_by1dcm1": 114, "dll_pwrd_on_scanmode_b": 114, "dll_pwrd_on_scanmode_bdcm0": 114, "dll_pwrd_on_scanmode_bdcm1": 114, "dll_pwrd_sticky_b": 114, "dll_pwrd_sticky_bdcm0": 114, "dll_pwrd_sticky_bdcm1": 114, "dll_settle_tim": [102, 114], "dll_spare": 102, "dll_synth_clock_spe": 114, "dll_tapinit_ctl": 114, "dll_test_mux_sel": [102, 114], "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dll_zd1_en": 114, "dll_zd1_endcm0": 114, "dll_zd1_endcm1": 114, "dll_zd1_jf_overflow_hold": 114, "dll_zd1_jf_overflow_holddcm0": 114, "dll_zd1_jf_overflow_holddcm1": 114, "dll_zd1_phase_sel_init": 114, "dll_zd1_pwc_en": 114, "dll_zd1_pwc_endcm0": 114, "dll_zd1_pwc_endcm1": 114, "dll_zd1_pwc_tap": 114, "dll_zd1_tap_init": 114, "dll_zd2_en": [102, 114], "dll_zd2_endcm": 102, "dll_zd2_endcm0": 114, "dll_zd2_endcm1": 114, "dll_zd2_jf_overflow_hold": 114, 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"doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 72, "doa6": 72, "doa6int": 72, "doa7": 72, "doa8": 72, "doa8int": 72, "doa9": 72, "doa9int": 72, "doa_reg": [45, 59, 96], "doa_reg_l": [110, 126, 141], "doa_reg_u": [110, 126, 141], "dob": [81, 96], "dob0": 72, "dob0int": 72, "dob1": 72, "dob10": [72, 96], "dob10int": 72, "dob11": [72, 96], "dob11int": 72, "dob12": 72, "dob12int": 72, "dob13": 72, "dob13int": 72, "dob14": 72, "dob14int": 72, "dob15": 72, "dob15int": 72, "dob1int": 72, "dob2": 72, "dob3": 72, "dob4": [72, 96], "dob4int": 72, "dob5": [72, 96], "dob6": [72, 96], "dob6int": 72, "dob7": [72, 96], "dob8": [72, 96], "dob8int": 72, "dob9": [72, 96], "dob9int": 72, "dob_reg": [45, 59, 96], "dob_reg_l": [110, 126, 141], "dob_reg_u": [110, 126, 141], "document": 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[66, 102, 105, 114, 119, 120, 130, 136, 145], "drp47_mask": [102, 105], "drp48": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp48_mask": [102, 105], "drp48_maskdcm": 102, "drp49": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp49_mask": [102, 105], "drp49_maskdcm": 102, "drp4a": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4a_mask": [102, 105], "drp4b": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4b_mask": [102, 105], "drp4c": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4c_mask": [102, 105], "drp4c_maskdcm": 102, "drp4d": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4d_mask": [102, 105], "drp4d_maskdcm": 102, "drp4e": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4e_mask": [102, 105], "drp4f": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4f_mask": [102, 105], "drp50": [66, 102, 105, 114, 130, 145], "drp50_mask": [102, 105], "drp50_maskdcm": 102, "drp51": [66, 102, 105, 114, 130, 145], "drp51_mask": [102, 105], "drp51_maskdcm": 102, "drp52": [66, 102, 105, 114, 130, 145], "drp52_mask": [102, 105], "drp52_maskdcm": 102, "drp53": [66, 102, 105, 114, 130, 145], "drp53_mask": [102, 105], "drp53_maskdcm": 102, "drp54": [66, 102, 105, 114, 130, 145], "drp54_mask": [102, 105], "drp54_maskdcm": 102, "drp55": [66, 102, 105, 114, 130, 145], "drp55_mask": [102, 105], "drp55_maskdcm": 102, "drp56": [66, 102, 105, 114, 130, 145], "drp56_mask": [102, 105], "drp56_maskdcm": 102, "drp57": [66, 102, 105, 114, 130, 145], "drp57_mask": [102, 105], "drp57_maskdcm": 102, "drp58": [66, 102, 105, 130, 145], "drp58_mask": [102, 105], "drp58_maskdcm": 102, "drp59": [66, 102, 105, 130, 145], "drp59_mask": [102, 105], "drp59_maskdcm": 102, "drp5a": [66, 102, 105, 130, 145], "drp5a_mask": [102, 105], "drp5a_maskdcm": 102, "drp5b": [66, 102, 105, 130, 145], "drp5b_mask": [102, 105], "drp5b_maskdcm": 102, "drp5c": [66, 102, 105, 130, 145], "drp5c_mask": [102, 105], "drp5c_maskdcm": 102, "drp5d": [66, 102, 105, 130, 145], "drp5d_mask": [102, 105], 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145], "drp70_mask": 105, "drp71": [66, 105, 130, 145], "drp71_mask": 105, "drp72": [66, 105, 130, 145], "drp72_mask": 105, "drp73": [66, 105, 130, 145], "drp73_mask": 105, "drp74": [66, 105, 130, 145], "drp74_mask": 105, "drp75": [66, 105, 130, 145], "drp75_mask": 105, "drp76": [66, 105, 130, 145], "drp76_mask": 105, "drp77": [66, 105, 130, 145], "drp77_mask": 105, "drp78": [66, 105, 130, 145], "drp78_mask": 105, "drp79": [66, 105, 130, 145], "drp79_mask": 105, "drp7a": [66, 105, 130, 145], "drp7a_mask": 105, "drp7b": [66, 105, 130, 145], "drp7b_mask": 105, "drp7c": [66, 105, 130, 145], "drp7c_mask": 105, "drp7d": [66, 105, 130, 145], "drp7d_mask": 105, "drp7e": [66, 105, 130, 145], "drp7e_mask": 105, "drp7f": [66, 105, 130, 145], "drp7f_mask": 105, "drp_mask": 113, "drp_mask_abov": 129, "drp_mask_above_l": 144, "drp_mask_above_r": 144, "drp_mask_below": 129, "drp_mask_below_l": 144, "drp_mask_below_lhclk": 144, "drp_mask_below_r": 144, "drp_mask_below_rhclk": 144, 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82, 99], "dxmuxslice1": [37, 46, 73], "dxmuxslice3": [37, 46], "dymux": [37, 46, 73, 82, 99], "dymuxslice0": 73, "dymuxslice1": [37, 46, 73], "dymuxslice3": [37, 46], "dynamic1": [71, 114, 136], "dynamic_en": 139, "dynamic_enabledci": 139, "e": [55, 78, 87, 154, 157], "e0": [38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 155, 157], "e000": 154, "e00000010001": 107, "e0000001010": 79, "e000001": [42, 55], "e0000010010": 79, "e00001": [42, 55], "e0000101": 91, "e0001": 72, "e00010": [42, 55], "e000100000001": 91, "e0001000000010": 91, "e000100000010": 91, "e000100000100": 91, "e000100001000": 91, "e0001000010000": 91, "e00010001": [91, 107], "e00011010": 55, "e001000000": 73, "e0010000000010": 107, "e001000000010": 91, "e0010000000100": [91, 107], "e0010000001000": 107, "e00100001": [91, 107], "e0010001": [91, 107], "e0010010": 107, "e0011": 72, "e00110000": 55, "e0011111111": 155, "e0100000000010": 107, "e0100000000100": 91, "e0100000001000": 107, "e0100000010": 79, "e010001": [42, 55], "e0100010": 91, "e01001": [42, 55], "e01101000": [42, 55], "e01110001": 55, "e1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 24, 25, 72, 73, 79, 154, 157, 162, 163, 164, 165, 166], "e100": 154, "e1000000000100": 107, "e1000000010": 79, "e10000010001": 107, "e10000100": [42, 55], "e1001": 72, "e101": 154, "e10100": 72, "e10110": 72, "e1011110": 157, "e10gbasekr_ld_coeff_upd_lane0": 135, "e10gbasekr_ld_coeff_upd_lane1": 135, "e10gbasekr_ld_coeff_upd_lane2": 135, "e10gbasekr_ld_coeff_upd_lane3": 135, "e10gbasekr_lp_coeff_upd_lane0": 135, "e10gbasekr_lp_coeff_upd_lane1": 135, "e10gbasekr_lp_coeff_upd_lane2": 135, "e10gbasekr_lp_coeff_upd_lane3": 135, "e10gbasekr_pma_ctrl_lane0": 135, "e10gbasekr_pma_ctrl_lane1": 135, "e10gbasekr_pma_ctrl_lane2": 135, "e10gbasekr_pma_ctrl_lane3": 135, "e10gbasekx_ctrl_lane0": 135, "e10gbasekx_ctrl_lane1": 135, "e10gbasekx_ctrl_lane2": 135, "e10gbasekx_ctrl_lane3": 135, "e10gbaser_pcs_cfg_lane0": 135, "e10gbaser_pcs_cfg_lane1": 135, "e10gbaser_pcs_cfg_lane2": 135, "e10gbaser_pcs_cfg_lane3": 135, "e10gbaser_pcs_seeda0_lane0": 135, "e10gbaser_pcs_seeda0_lane1": 135, "e10gbaser_pcs_seeda0_lane2": 135, "e10gbaser_pcs_seeda0_lane3": 135, "e10gbaser_pcs_seeda1_lane0": 135, "e10gbaser_pcs_seeda1_lane1": 135, "e10gbaser_pcs_seeda1_lane2": 135, "e10gbaser_pcs_seeda1_lane3": 135, "e10gbaser_pcs_seeda2_lane0": 135, "e10gbaser_pcs_seeda2_lane1": 135, "e10gbaser_pcs_seeda2_lane2": 135, "e10gbaser_pcs_seeda2_lane3": 135, "e10gbaser_pcs_seeda3_lane0": 135, "e10gbaser_pcs_seeda3_lane1": 135, "e10gbaser_pcs_seeda3_lane2": 135, "e10gbaser_pcs_seeda3_lane3": 135, "e10gbaser_pcs_seedb0_lane0": 135, "e10gbaser_pcs_seedb0_lane1": 135, "e10gbaser_pcs_seedb0_lane2": 135, "e10gbaser_pcs_seedb0_lane3": 135, "e10gbaser_pcs_seedb1_lane0": 135, "e10gbaser_pcs_seedb1_lane1": 135, "e10gbaser_pcs_seedb1_lane2": 135, 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"e13101": 72, "e14": [2, 3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e14010": 72, "e14101": 72, "e15": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e15101": 72, "e16": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e16100": 72, "e16111": 72, "e17": [24, 25, 72, 73, 79, 164], "e17110": 72, "e17111": 72, "e18": [24, 25, 72, 73, 79, 164], "e18000": 72, "e18111": 72, "e19": [6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e19111": 72, "e1int": 154, "e2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e20": [6, 7, 24, 72, 73, 79, 165, 166], "e2001": 72, "e20101": 72, "e2011": 72, "e20110": 72, "e21": [6, 7, 72, 73, 79, 165, 166], "e21100": 72, "e2110111111": 155, "e21110": 72, "e22": [6, 7, 72, 73, 79, 165, 166], "e22100": 72, "e22110": 72, "e23": [22, 23, 72, 73, 79], "e23110": 72, "e24": [22, 23], "e25": [22, 23], "e26": [22, 23], "e3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e3001": 72, "e3111011111": 155, "e4": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e4000": 72, "e401": 155, "e4010": 72, "e5": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e500": 155, "e5011": 72, "e6": [2, 3, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 155, 157, 161, 162, 164, 165, 166], "e6001": 72, "e601": 155, "e6011": 72, "e6int": 157, "e7": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e700": 155, "e7011": 72, "e7int": 154, "e8": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 162, 164, 165, 166], "e8001": 72, "e8011": 72, "e8int": 154, "e9": [2, 3, 6, 7, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 164, 165, 166], "e9100": 72, "e9111": 72, "each": [14, 15, 16, 34, 35, 36, 42, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 171], "earlier": [34, 104, 169], "easi": [55, 91], "ebai": 35, "ecc": 106, "edg": [14, 55, 58, 87, 91, 118, 123, 134, 148], "ee0": [68, 138, 150], "ee1": [68, 138, 150], "ee2": [68, 138, 150], "ee3": [68, 138, 150], "efar0": [131, 146], "effect": [35, 36, 46, 81, 82, 91, 148, 171], "efuse1": [62, 115, 131, 146], "eg": [12, 55, 58, 91], "eight": 91, "eighth1011": 69, "eighth2111": 69, "eint": 154, "either": [14, 35, 36, 58, 81, 82, 134, 148, 160, 170, 171], "el0": [68, 122, 138, 150], "el1": [68, 122, 138, 150], "el2": [68, 122, 138, 150], "el3": [68, 138, 150], "electron": [159, 171], "element": [17, 160], "elimin": 58, "els": [15, 16, 36, 171], "em_cclk": 151, "emac": [117, 118, 133, 134], "emac0_1000basex_en": 117, "emac0_addrfilter_en": 117, "emac0_bytephi": 117, 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96], "init_4": [109, 111, 127, 142], "init_40": [109, 111, 127, 142], "init_41": [109, 111, 127, 142], "init_42": [109, 111, 127, 142], "init_43": [109, 111, 127, 142], "init_44": [109, 111, 127, 142], "init_45": [109, 111, 127, 142], "init_46": [109, 111, 127, 142], "init_47": [109, 111, 127, 142], "init_48": [109, 111, 127, 142], "init_49": [109, 111, 127, 142], "init_4a": [109, 111, 127, 142], "init_4b": [109, 111, 127, 142], "init_4c": [109, 111, 127, 142], "init_4d": [109, 111, 127, 142], "init_4f": [109, 111, 127, 142], "init_5": [109, 142], "init_50": [109, 111, 127, 142], "init_51": [109, 111, 127, 142], "init_52": [109, 111, 127, 142], "init_53": [109, 111, 127, 142], "init_54": [109, 111, 127, 142], "init_55": [109, 111, 127, 142], "init_56": [109, 111, 127, 142], "init_57": [109, 111, 127, 142], "init_58": [109, 142], "init_59": [109, 142], "init_5a": [109, 142], "init_5b": [109, 142], "init_5c": [109, 142], "init_5d": [109, 142], "init_5f": [109, 142], "init_6": 109, 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"init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_outbufhce_r0": 130, "init_outbufhce_r10": 130, "init_outbufhce_r2": 130, "init_outbufhce_r4": 130, "init_outbufhce_r6": 130, "init_outbufhce_r8": 130, "init_outbufmrce1": 145, "init_outmmcm0": 130, "init_outmmcm1": 130, "init_rank1_parti": [108, 123], "init_rank2": [108, 123], "init_rank3": [108, 123], "init_signals_error": [131, 146], "init_skip": 62, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 171], "initp_xx": [81, 96], "initpin": [98, 111, 127, 142], "initpinmisc": 111, "initx": 73, "initxint": 73, "initxslice1": 73, "inityint": 73, "inmode0": [132, 147], "inmode1": [132, 147], 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87, 90, 92, 96, 104, 106, 118, 121, 134, 137, 139, 148, 149, 171], "interconnect_imask": 125, "interconnect_tmpl_sel": 125, "intereconnect": 148, "interfac": [11, 33, 41, 52, 54, 58, 64, 67, 87, 90, 106, 168], "interface_typ": [108, 123], "interface_typeilogic0": 108, "interface_typeilogic1": 108, "interfer": [46, 82], "interleav": 16, "intern": [36, 56, 92, 96, 148, 170], "internal1": [131, 146], "internal_vref": [113, 139], "internalclk0": [49, 62], "interp_en": [130, 145], "interp_test": 145, "interpos": 148, "interpret": 17, "interrupt": [35, 91], "interrupt_pin": [140, 152], "interrupt_stat_auto": 152, "interrupt_stat_autopci": 152, "interruptpin": 124, "intersect": [38, 47, 55, 58, 87, 104, 118, 134, 148], "intest": [13, 35, 170], "intf": [104, 107, 118, 121, 134, 137, 148, 149], "intosc00": 76, "intro": [41, 54, 67, 78, 106, 121, 137, 149, 156], "introduc": [58, 96, 148], "introduct": [11, 33, 44, 54, 90, 168], "inv": [15, 36, 37, 42, 43, 46, 47, 51, 52, 55, 57, 59, 60, 61, 64, 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23, 24, 25, 163, 164, 165, 166], "p104": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p105": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p106": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p107": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p108": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p109": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p11": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p110": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p111": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p112": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p113": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p114": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p115": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p116": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p117": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p120": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p121": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p122": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p123": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p124": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p125": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p126": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p127": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p128": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p129": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p13": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p130": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p131": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p132": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p133": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p134": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p135": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p136": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p137": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p138": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p139": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p14": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p140": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p141": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p142": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p143": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p144": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p145": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p146": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p147": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p148": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p149": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p15": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p150": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 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25, 164, 165, 166], "p1cmdclk": 69, "p1cmden": 69, "p1rdclk": 69, "p1rden": 69, "p1wrclk": 69, "p1wren": 69, "p2": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 161, 162, 163, 164, 165, 166], "p20": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p200": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p201": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p202": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p203": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p204": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p205": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p206": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p207": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p208": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p209": [3, 6, 7], "p21": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p210": [3, 6, 7], "p211": [3, 6, 7], "p212": [3, 6, 7], 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6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p250": [6, 7], "p251": [6, 7], "p252": [6, 7], "p253": [6, 7], "p254": [6, 7], "p255": [6, 7], "p256": [6, 7], "p257": [6, 7], "p258": [6, 7], "p259": [6, 7], "p26": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p260": [6, 7], "p261": [6, 7], "p262": [6, 7], "p263": [6, 7], "p264": [6, 7], "p265": [6, 7], "p266": [6, 7], "p267": [6, 7], "p268": [6, 7], "p269": [6, 7], "p27": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p270": [6, 7], "p271": [6, 7], "p272": [6, 7], "p273": [6, 7], "p274": [6, 7], "p275": [6, 7], "p276": [6, 7], "p277": [6, 7], "p278": [6, 7], "p279": [6, 7], "p28": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p280": [6, 7], "p281": [6, 7], "p282": [6, 7], "p283": [6, 7], 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21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p3clk": 69, "p3cmdclk": 69, "p3cmden": 69, "p3en": 69, "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p4clk": 69, "p4cmdclk": 69, "p4cmden": 69, "p4en": 69, "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p5clk": 69, "p5cmdclk": 69, "p5cmden": 69, "p5en": 69, "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p_d": 81, "packag": [11, 17, 33, 36, 56, 148, 151, 160, 168, 170], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 123, 139, 151, 160, 169, 171], "pair": [17, 58, 82, 96, 104, 108, 123, 139, 148, 151, 160], "parallel": [16, 108, 123, 139, 151], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 123, 148, 161, 162, 163, 164, 165, 166, 168, 170], "partial": [34, 81, 96, 170], "particip": 36, "particular": [17, 160], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 134, 148, 154, 155, 157, 158], "pass0": [64, 71, 114], "pass00000000": 102, "pass00000000000001": 113, "pass00000000001": 113, "pass00000001": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 116, "path": [36, 81], "pattern": [87, 116, 132, 147], "pattern0": [116, 132, 147], "pbbaseptr": 124, "pbcapabilitydw0basepow": 124, "pbcapabilitydw0datascal": 124, "pbcapabilitydw0pmst": 124, "pbcapabilitydw0pmsubst": 124, "pbcapabilitydw0powerrail": 124, "pbcapabilitydw0typ": 124, "pbcapabilitydw1basepow": 124, "pbcapabilitydw1datascal": 124, "pbcapabilitydw1pmst": 124, "pbcapabilitydw1pmsubst": 124, "pbcapabilitydw1powerrail": 124, "pbcapabilitydw1typ": 124, "pbcapabilitydw2basepow": 124, "pbcapabilitydw2datascal": 124, "pbcapabilitydw2pmst": 124, "pbcapabilitydw2pmsubst": 124, "pbcapabilitydw2powerrail": 124, "pbcapabilitydw2typ": 124, "pbcapabilitydw3basepow": 124, "pbcapabilitydw3datascal": 124, "pbcapabilitydw3pmst": 124, "pbcapabilitydw3pmsubst": 124, "pbcapabilitydw3powerrail": 124, "pbcapabilitydw3typ": 124, "pbcapabilitynextptr": 124, "pbcapabilitysystemalloc": 124, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 161, 162, 169], "pc84": [18, 29, 34], "pci": [44, 56, 58, 67, 78, 90, 91, 92, 121, 137, 149], "pci000": 91, "pci100": 91, "pci33_3": [57, 79], "pci33_30": [57, 93], "pci33_300": [57, 93], "pci33_30000": 93, "pci33_300000": [57, 93], "pci33_3000000": 123, "pci33_3000000000000": 123, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 123, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 123, "pci66_3000000000000": 123, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 123, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, "pci_clampiob0": 57, "pci_clampiob1": 57, "pci_clampiob3": 57, "pci_clampiob4": 57, "pci_delai": 80, "pci_express_mod": 136, "pci_express_mode_0": [66, 119, 120], "pci_express_mode_1": [66, 119, 120], "pci_express_mode_1gtp": 66, "pci_input": 57, "pci_inputiob1": 57, "pci_inputiob2": 57, "pci_inputiob3": 57, "pci_inputiob4": 57, "pci_inputiob5": 57, "pcice10": 57, "pcice_mux": 57, "pcie": [70, 118, 124, 134, 140, 148, 152], "pcie0": [66, 119, 120], "pcie2": 148, "pcie3": [148, 153], "pcie_base_ptr": [140, 152], "pcie_cap_capability_id": [140, 152], "pcie_cap_capability_vers": [70, 140, 152], "pcie_cap_device_port_typ": [70, 140, 152], "pcie_cap_int_msg_num": [70, 140], "pcie_cap_nextptr": [140, 152], "pcie_cap_on": [140, 152], "pcie_cap_onpci": [140, 152], "pcie_cap_rsvd_15_14": [140, 152], "pcie_cap_slot_impl": [70, 140, 152], "pcie_gener": 70, "pcie_l": [148, 149], "pcie_r": [148, 149], "pcie_revis": [140, 152], "pciecapabilityintmsgnum": 124, "pciecapabilitynextptr": 124, "pciecapabilityslotimpl": 124, "pcierevis": 124, "pcierevisionpci": 124, "pcilog": [58, 80, 87, 90, 91], "pcilogics": [47, 58, 67], "pcix": 57, "pcix0": [57, 93], "pcix00": [93, 108], "pcix000000": 123, "pcix000001": 57, "pcix0011": 93, "pcix001111100000": 123, "pcix0100101011": 93, "pcix0110001100": [108, 123], "pcix011001100": 93, "pcix01111": 93, "pcix01111011": 108, "pcix100110": 57, "pcix111110": 57, "pcix11111111": 57, "pcix66_3": 79, "pcix66_30111": 79, "pcix66_3101001100": 79, "pcomma_10b_valu": [88, 89, 136], "pcomma_10b_value_0": [66, 119, 120], "pcomma_10b_value_1": [66, 119, 120], "pcomma_detect": [88, 89, 105, 136], "pcomma_detect_0": [66, 119, 120], "pcomma_detect_1": [66, 119, 120], "pcomma_detect_1gtp": 66, "pcomma_detectgtx0": 136, "pcomma_detectgtx1": 136, "pcomma_detectgtx2": 136, "pcomma_detectgtx3": 136, "pcomma_valu": 105, "pcs0": [66, 119, 120], "pcs10": 136, "pcs_ability_lane0": 135, "pcs_ability_lane1": 135, "pcs_ability_lane2": 135, "pcs_ability_lane3": 135, "pcs_bit_slip": 105, "pcs_com_cfg": 119, "pcs_ctrl1_lane0": 135, "pcs_ctrl1_lane1": 135, "pcs_ctrl1_lane2": 135, "pcs_ctrl1_lane3": 135, "pcs_ctrl2_lane0": 135, "pcs_ctrl2_lane1": 135, "pcs_ctrl2_lane2": 135, "pcs_ctrl2_lane3": 135, "pcs_misc_cfg_0_lane0": 135, "pcs_misc_cfg_0_lane1": 135, "pcs_misc_cfg_0_lane2": 135, "pcs_misc_cfg_0_lane3": 135, "pcs_misc_cfg_1_lane0": 135, "pcs_misc_cfg_1_lane1": 135, "pcs_misc_cfg_1_lane2": 135, "pcs_misc_cfg_1_lane3": 135, "pcs_mode_lane0": 135, "pcs_mode_lane1": 135, "pcs_mode_lane2": 135, "pcs_mode_lane3": 135, "pcs_reset_1_lane0": 135, "pcs_reset_1_lane1": 135, "pcs_reset_1_lane2": 135, "pcs_reset_1_lane3": 135, "pcs_reset_lane0": 135, "pcs_reset_lane1": 135, "pcs_reset_lane2": 135, "pcs_reset_lane3": 135, "pcs_type_lane0": 135, "pcs_type_lane1": 135, "pcs_type_lane2": 135, "pcs_type_lane3": 135, "pd_revers": 145, "pdelidle_drp_en": 136, "pdelidle_drp_en_0": 66, "pdelidle_drp_en_1": 66, "pdelidle_drp_en_1gtp": 66, "pdrive": [57, 79, 93, 108, 123, 139], "pdriveiostd": [57, 79, 93, 108, 123, 139], "pdstatuspin": 76, "pdstatuspinmisc": 76, "pent": 122, "pent00010100": 122, "pent00011000": 122, "pent00100100": 122, "pent00101000": 122, "pent01000100": 122, "pent01001000": 122, "pent10000100": 122, "pent10001000": 122, "per": [12, 14, 17, 33, 34, 35, 36, 46, 55, 56, 58, 81, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 170, 171], "perf0": [130, 139, 145, 151], "perf0001": 136, "perf01": 139, "perf0_il": 130, "perf0_ilmmcm0": 130, "perf0_ilmmcm1": 130, "perf0_ir": 130, "perf0_irmmcm0": 130, "perf0_irmmcm1": 130, "perf0_ol": 130, "perf0_olmmcm0": 130, "perf0_olmmcm1": 130, "perf0_or": 130, "perf0_ormmcm0": 130, "perf0_ormmcm1": 130, "perf0hclk_ioi": 139, "perf1": [130, 139, 145, 151], "perf1011": 136, "perf11": 139, "perf1_il": 130, "perf1_ilmmcm0": 130, "perf1_ilmmcm1": 130, "perf1_ir": 130, "perf1_irmmcm0": 130, "perf1_irmmcm1": 130, "perf1_ol": 130, "perf1_olmmcm0": 130, "perf1_olmmcm1": 130, "perf1_or": 130, "perf1_ormmcm0": 130, "perf1_ormmcm1": 130, "perf1mmcm": 145, "perf2": [130, 139, 145, 151], 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"pf0_ari_cap_next_func": 153, "pf0_ari_cap_nextptr": 153, "pf0_ari_cap_v": 153, "pf0_bar0_aperture_s": 153, "pf0_bar0_control": 153, "pf0_bar1_aperture_s": 153, "pf0_bar1_control": 153, "pf0_bar2_aperture_s": 153, "pf0_bar2_control": 153, "pf0_bar3_aperture_s": 153, "pf0_bar3_control": 153, "pf0_bar4_aperture_s": 153, "pf0_bar4_control": 153, "pf0_bar5_aperture_s": 153, "pf0_bar5_control": 153, "pf0_bist_regist": 153, "pf0_capability_point": 153, "pf0_class_cod": 153, "pf0_dev_cap2_obff_support": 153, "pf0_dev_cap_endpoint_l0s_lat": 153, "pf0_dev_cap_endpoint_l1_lat": 153, "pf0_dev_cap_max_payload_s": 153, "pf0_device_id": 153, "pf0_dpa_cap_nextptr": 153, "pf0_dpa_cap_sub_state_control": 153, "pf0_dpa_cap_sub_state_power_allocation0": 153, "pf0_dpa_cap_sub_state_power_allocation1": 153, "pf0_dpa_cap_sub_state_power_allocation2": 153, "pf0_dpa_cap_sub_state_power_allocation3": 153, "pf0_dpa_cap_sub_state_power_allocation4": 153, "pf0_dpa_cap_sub_state_power_allocation5": 153, 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"phaser_in_en": 145, "phaser_in_enphaser_in0": 145, "phaser_in_enphaser_in1": 145, "phaser_in_enphaser_in2": 145, "phaser_in_enphaser_in3": 145, "phaser_in_rclk001001": 145, "phaser_in_rclk101010": 145, "phaser_in_rclk201100": 145, "phaser_in_rclk310100": 145, "phaser_out0": 145, "phaser_out1": 145, "phaser_out2": 145, "phaser_out3": 145, "phaser_out_en": 145, "phaser_ref": 145, "phaser_ref_bounce0": 145, "phaser_ref_bounce000100010000": 145, "phaser_ref_bounce001000000010000": 145, "phaser_ref_bounce1": 145, "phaser_ref_bounce100100100000": 145, "phaser_ref_bounce110000000010000": 145, "phaser_ref_bounce2": 145, "phaser_ref_bounce201000000000100": 145, "phaser_ref_bounce201000010000": 145, "phaser_ref_bounce3": 145, "phaser_ref_bounce301000100000": 145, "phaser_ref_bounce310000000000100": 145, "phaser_ref_en": 145, "phaser_ref_misc": 145, "phaserefclk": 145, "phi": 35, "philip": [169, 170], "phy_control": 145, "phy_count_en": 145, "phyemac0gtxclk": 117, "phyemac0mclkin": 117, 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146], "post_crc_sel": [62, 115, 131, 146], "potenti": 36, "power": [12, 17, 34, 35, 36, 160, 169, 171], "power_en": 105, "power_sav": 136, "powerdown": [54, 67], "powerdown_statu": [84, 101], "powerdownpin": [76, 85, 98], "powerdownpinmisc": [76, 85], "powerpc": [44, 82, 90, 92, 96, 121], "powerup_clk": 76, "powerup_delai": 76, "ppc": [87, 90, 104, 118, 125], "ppcdm_asyncmod": 125, "ppcds_asyncmod": 125, "ppcm_arbconfig": 125, "ppcm_control": 125, "ppcm_counter": 125, "ppcs0_addrmap_tmpl0": 125, "ppcs0_addrmap_tmpl1": 125, "ppcs0_addrmap_tmpl2": 125, "ppcs0_addrmap_tmpl3": 125, "ppcs0_control": 125, "ppcs0_width_128n64": 125, "ppcs1_addrmap_tmpl0": 125, "ppcs1_addrmap_tmpl1": 125, "ppcs1_addrmap_tmpl2": 125, "ppcs1_addrmap_tmpl3": 125, "ppcs1_control": 125, "ppcs1_width_128n64": 125, "ppds_25001001000111": 50, "ppds_250111": 57, "ppds_33001001000111": 50, "ppds_330111": 57, "pq100": [18, 19, 29, 34], "pq160": [18, 19, 22, 34], "pq208": [3, 6, 7, 12, 24, 25, 34, 164, 165, 166, 169], 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23], "u25": [22, 23], "u26": [22, 23], "u3": [6, 7, 22, 23, 24, 25, 164, 165, 166], "u4": [6, 7, 22, 23, 24, 25, 164, 165, 166], "u5": [24, 25, 164], "u6": [24, 25, 164], "u7": [24, 25, 164], "u8": [24, 25, 164], "u9": [24, 25, 164], "ucmt_top": 145, "uct": [159, 171], "uct0": [161, 162, 163, 164, 165, 166, 171], "uct0101": 159, "uct1": [161, 162, 163, 164, 165, 166, 171], "uct1110": 159, "uct2": [161, 162, 163, 164, 165, 166, 171], "uct2110": 159, "uct3": [161, 162, 163, 164, 165, 166, 171], "uct3111": 159, "ue": [159, 161, 162, 163, 164, 165, 166, 171], "uim": [16, 17, 32, 33, 34, 35], "uim0": 26, "uim10": 26, "uim110": 29, "uim1110": [18, 19, 22, 29], "uim11110": [19, 22, 23], "uim_area_bit": 15, "uim_ibuf_bit": 17, "uim_o": 36, "uim_oe_mux": 36, "uim_oe_mux4544": 15, "uim_out_inv": [15, 36], "uim_out_inv46": 15, "uim_row_bit": 15, "uim_subarea_bit": 15, "ul": [58, 63, 87], "ulvds_250000000000100": 50, "ulvds_25000100001": 85, "ulvds_250001000111": 100, "ulvds_25001000001": 85, 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"update_nonactivephaser_in2": 145, "update_nonactivephaser_in3": 145, "upgrad": [81, 92], "upload": 35, "upper": [41, 46, 54, 58, 67, 81, 82, 87, 90, 96, 104, 108, 118, 123, 134], "upsid": 104, "upstream_fac": [140, 152], "upstream_facingpci": [140, 152], "upstreamfac": 124, "upstreamfacingpci": 124, "upward": [36, 46, 82, 123], "ur": [58, 63, 87], "ur_atom": 152, "ur_atomicpci": 152, "ur_cfg1": 152, "ur_inv_req": [140, 152], "ur_inv_reqpci": 152, "ur_prs_respons": 152, "us": [12, 14, 15, 16, 17, 34, 35, 36, 42, 45, 46, 47, 50, 55, 56, 58, 81, 82, 83, 85, 87, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "usabl": [55, 58], "use_dport": [132, 147], "use_dportdsp0": 147, "use_dportdsp1": 147, "use_mult": [116, 132, 147], "use_multdsp0": 147, "use_multdsp1": 147, "use_pattern_detect": 116, "use_rid_pin": 152, "use_rid_pinspci": 152, "use_simd": [116, 132, 147], "use_vref01": [2, 3, 6, 7], "useless": [55, 148], "user": [56, 92, 139, 151, 159, 171], "user1": 63, "user_clk2_div2": 152, "user_clk2_div2pci": 152, "user_clk_freq": [140, 152], "user_mode00": [88, 89], "user_operation0": 135, "userclk0": 155, "userclk01": [39, 48, 49, 62, 75, 76, 84, 101, 115, 131, 146], "userclk1": 155, "usercod": [2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 35, 36], "userid": [40, 50, 63, 76, 85, 98, 111, 127, 142], "usr_cfg": 70, "usr_code_err_clr": 136, "usr_code_err_clr_0": 66, "usr_code_err_clr_0gtp": 66, "usr_code_err_clr_1": 66, "usr_code_err_clr_1gtp": 66, "usr_code_err_clrgtx0": 136, "usr_code_err_clrgtx1": 136, "usr_code_err_clrgtx2": 136, "usr_code_err_clrgtx3": 136, "usr_ext_cfg": 70, "usrcclk_en": [98, 111, 127, 142], "usrclk0": [119, 120], "usrclk1": [119, 120], "usual": [17, 35, 36, 91, 104, 118, 171], "v": [12, 78], "v0": [73, 76, 79, 154, 155, 157, 158], "v0000": 155, "v00110": 155, "v0int": 157, "v1": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 154, 155, 157, 158, 164, 165, 166], "v10": [24, 25, 164], "v1001": 155, "v10010": 155, "v11": [24, 25, 164], "v12": [24, 25, 164], "v13": [24, 25, 164], "v14": [24, 25, 164], "v15": [24, 25, 164], "v16": [24, 25, 164], "v17": [24, 25, 164], "v18": [24, 25, 164], "v19": [6, 7, 24, 25, 164, 165, 166], "v1int": 157, "v2": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 90, 154, 155, 157, 158, 164, 165, 166], "v20": [6, 7, 24, 165, 166], "v2010": 155, "v20100": 155, "v21": [6, 7, 165, 166], "v22": [6, 7, 165, 166], "v23": [22, 23], "v24": [22, 23], "v25": [22, 23], "v26": [22, 23], "v2int": [155, 157], "v2osc": 155, "v2p": 90, "v3": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 154, 155, 157, 158, 164, 165, 166], "v30000": 155, "v3011": 155, "v31110": 155, "v3int": 157, "v4": [6, 7, 22, 23, 24, 25, 154, 155, 157, 158, 164, 165, 166], "v40100": 155, "v4100": 155, "v411": 155, "v4111101111": 155, "v4int": [155, 157], "v4tbuf0": 154, "v5": [24, 25, 154, 155, 157, 158, 164], "v50101": 155, "v510": 155, "v5101": 155, "v5111110111": 155, "v5int": [155, 157], "v6": [24, 25, 154, 155, 157, 158, 164], "v60110": 155, "v611": 155, "v6110": 155, "v6111111011": 155, "v6int": [155, 157], "v6tbuf3": 157, "v7": [24, 25, 154, 155, 157, 158, 164], "v70111": 155, "v710": 155, "v7111": 155, "v7111111101": 155, "v7int": 155, "v8": [24, 25, 164], "v9": [24, 25, 164], "valid": [15, 16, 35], "valu": [14, 15, 16, 17, 35, 36, 46, 54, 81, 82, 90, 91, 96, 160, 170, 171], "vari": [34, 35, 36, 104, 108, 118, 134, 148, 171], "variabl": [123, 159], "variable01": 123, "variable11": 108, "variable110": 64, "variant": [12, 34, 36, 55, 58, 87, 91, 104, 118, 134, 148, 151, 171], "variou": [46, 55, 56, 82, 91, 92, 171], "vbg_dll_sel": 115, "vbg_flat_sel": 146, "vbg_pd": [51, 86], "vbg_sel": [51, 52, 86, 115, 131], "vbg_slope_opt": 63, "vbg_vgg_flast_sel": 131, "vbg_vgg_neg_sel": 131, "vbrk": [104, 118], "vc0_cpl_infinit": [70, 140, 152], "vc0_rx_ram_limit": [70, 140, 152], "vc0_total_credits_cd": [70, 140, 152], "vc0_total_credits_ch": [70, 140, 152], "vc0_total_credits_npd": 152, "vc0_total_credits_nph": [70, 140, 152], "vc0_total_credits_pd": [70, 140, 152], "vc0_total_credits_ph": [70, 140, 152], "vc0_tx_lastpacket": [70, 140, 152], "vc0rxfifobasec": 124, "vc0rxfifobasenp": 124, "vc0rxfifobasep": 124, "vc0rxfifolimitc": 124, "vc0rxfifolimitnp": 124, "vc0rxfifolimitp": 124, "vc0totalcreditscd": 124, "vc0totalcreditsch": 124, "vc0totalcreditsnph": 124, "vc0totalcreditspd": 124, "vc0totalcreditsph": 124, "vc0txfifobasec": 124, "vc0txfifobasenp": 124, "vc0txfifobasep": 124, "vc0txfifolimitc": 124, "vc0txfifolimitnp": 124, "vc0txfifolimitp": 124, "vc1rxfifobasec": 124, "vc1rxfifobasenp": 124, "vc1rxfifobasep": 124, "vc1rxfifolimitc": 124, "vc1rxfifolimitnp": 124, "vc1rxfifolimitp": 124, "vc1totalcreditscd": 124, "vc1totalcreditsch": 124, "vc1totalcreditsnph": 124, "vc1totalcreditspd": 124, "vc1totalcreditsph": 124, "vc1txfifobasec": 124, "vc1txfifobasenp": 124, "vc1txfifobasep": 124, "vc1txfifolimitc": 124, "vc1txfifolimitnp": 124, "vc1txfifolimitp": 124, "vc_base_ptr": [140, 152], "vc_cap_id": [140, 152], "vc_cap_nextptr": [140, 152], "vc_cap_on": [140, 152], "vc_cap_reject_snoop_transact": [140, 152], "vc_cap_reject_snoop_transactionspci": 152, "vc_cap_vers": [140, 152], "vcbaseptr": 124, "vcc": [36, 160, 161, 162, 163, 164, 165, 166, 169, 171], "vcc00": 61, "vcc0000": [2, 3, 4, 5, 6, 7, 8, 9], "vcc0000000000": [138, 150], "vcc00000010": 68, "vcc00010001": 107, "vcc0010000001": 122, "vcc00100001": 107, "vcc01": 15, "vcc01000010": 68, "vcc10": [132, 147], "vcc11": [2, 3, 4, 5, 6, 7, 8, 9], "vcc110": 159, "vcc11000001": 68, "vcc11111111": [4, 5, 161], "vcc1111111111111111": [8, 9], "vcc11111111111111111": 162, "vcc111111111111111111111111111": 163, "vcc1111111111111111111111111111": 2, "vcc1111111111111111111111111111111111111111111111": 164, "vcc111111111111111111111111111111111111111111111111": 3, "vcc111111111111111111111111111111111111111111111111111111111111111": 165, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111": 6, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111111111111": 166, "vcc1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111": 7, "vcc_gnd": 154, "vccapabilitynextptr": 124, "vccaux": [2, 3, 4, 5, 6, 7, 8, 9, 12], "vccint": [2, 3, 4, 5, 6, 7, 8, 9, 12, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34], "vccio": [12, 17, 34], "vccio0": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "vccio1": [2, 3, 5, 6, 7, 9, 21, 25], "vccio2": [6, 7, 25], "vccio3": [6, 7, 25], "vco_ctrl_en": 105, "vcodac_init": 105, "vdd11": 114, "vdd_vbg000": 102, "ve": 78, "vendor": [35, 170, 171], "vendor_id": 140, "vendorid": 124, "veri": [12, 34, 36, 46, 55, 81, 139, 148, 169, 171], "verif": 35, "verifi": [35, 91], "version": [12, 16, 34, 36, 46, 48, 49, 55, 56, 58, 92, 96, 148], "vertic": [38, 46, 47, 54, 55, 81, 82, 87, 91, 96, 134, 148], "vf0_ari_cap_nextptr": 153, "vf0_capability_point": 153, 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"zia_gclk2_en": [161, 162, 163, 164, 165, 166], "zia_gclk3_en": [161, 162, 163, 164, 165, 166], "zynq": 148, "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "FPGAcore", "General interconnect", "Input / Output", "Xilinx FPGAs", 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transceivers", "Virtex 6", "Interconnect", "Input/Output", "PCI Express cores", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Clock management tile", "Configuration registers", "DSP", "Device geometry", "Virtex 7", "Interconnect", "Input/Output", "PCI Express Gen2 cores", "PCI Express Gen3 cores", "Configurable Logic Block", "Corners", "XC5200", "Input/Output", "Splitters", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [47, 91], "03": 55, "1": [46, 82], "12": [49, 55, 62], "128": 82, "16": [46, 82], "2": [81, 85, 88, 89, 90, 93], "3": [46, 48, 50, 51, 54, 57, 81], "32": [46, 82], "34": 62, "3a": [49, 50, 52, 57, 58, 81], "3e": [48, 50, 52, 57, 58, 81], "4": [46, 106], "405": 95, "5": 121, "6": [67, 137], "64": [46, 82], "7": 149, "AND": 15, "The": [38, 47, 81, 83], "aim": 14, "alt": 93, "attribut": 47, "b": [43, 57, 79, 83, 88, 89, 93, 157], "b0": 91, "b1": 57, "b123": 91, "b2": [57, 93], "b3": 57, "b4": 57, "backbon": [55, 91], "bank": [14, 58, 87, 108, 123, 139, 151], "bclkpad": 91, "bel": 81, "bit": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 159, 160, 161, 162, 163, 164, 165, 166], "bitstream": [1, 15, 16, 37, 38, 42, 45, 46, 47, 53, 55, 58, 59, 60, 61, 64, 65, 66, 68, 69, 70, 71, 72, 73, 81, 82, 83, 87, 88, 89, 91, 96, 97, 98, 99, 102, 103, 104, 105, 107, 108, 109, 110, 111, 112, 116, 117, 118, 119, 120, 122, 123, 124, 125, 126, 127, 128, 132, 133, 134, 135, 136, 138, 139, 140, 141, 142, 143, 147, 148, 150, 151, 153, 154, 159], "bl": [52, 76, 155], "blank": 35, "block": [37, 45, 46, 59, 60, 69, 72, 73, 81, 82, 96, 99, 110, 112, 126, 128, 141, 143, 154], "bond": [17, 160], "bot": [77, 83], "bottom": [38, 47, 61, 72, 83, 91], "boundari": [13, 35, 170], "br": [52, 76, 155], "bram": [45, 55, 58, 81, 91, 150], "bspi": 146, "bu": [36, 83], "buffer": [14, 15, 36, 43, 57, 58, 79, 87, 93, 171], "buse": 82, "carri": [46, 82], "cclk_freq": [49, 62], "center": [38, 47, 98, 104, 111, 118, 127, 134, 142, 148], "check": 35, "clb": [42, 55, 91], "clbll": [112, 128, 143], "clblm": [112, 128, 143], "clexl": 60, "clexm": 60, "clk": 93, "clk_b": [91, 93], "clk_bali_rebuf": 144, "clk_bufg": 144, "clk_bufg_rebuf": 144, "clk_cmt_b": 113, "clk_cmt_t": 113, "clk_dcm_b": 100, "clk_dcm_t": 100, "clk_hrow": [100, 113, 144], "clk_iob_b": [100, 113], "clk_iob_t": [100, 113], "clk_mgt_b": 113, "clk_mgt_t": 113, "clk_t": [91, 93], "clk_term_b": 100, "clk_term_t": 100, "clkb": [38, 47, 55, 74, 83, 158], "clkb_2dll": 74, "clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 158, "clkl": [47, 80, 158], "clkpad": 91, "clkr": [47, 80, 158], "clkt": [38, 47, 55, 74, 83, 158], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 158], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113, 114, 129, 130, 144, 145], "cmt": [68, 113, 114, 130, 145], "cmt_bufg_bot": 129, "cmt_bufg_top": 129, "cmt_fifo": 145, "cnr": [76, 91, 155], "column": [58, 72, 104, 118, 134, 148, 171], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 115, 127, 128, 131, 142, 143, 146, 148, 154, 171], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 121, 137, 149, 156, 167, 168], "control": [69, 171], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 115, 131, 146], "cor1": [49, 62, 115, 131, 146], "cor2": [49, 62], "core": [95, 124, 125, 140, 152, 153], "corner": [40, 50, 63, 76, 85, 155], "cpld": [11, 33, 168], "ctl": [39, 48, 49, 62, 75, 84, 101, 115, 131, 146], "ctl1": [131, 146], "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 113, 161, 162, 163, 164, 165, 166], "databas": [10, 17, 32, 160, 167], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 122, 138, 150], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 118, 134, 148, 160, 167, 169, 171], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 116, 132, 147], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 118, 134, 148], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [117, 133], "exit": 35, "export": 36, "express": [70, 124, 140, 148, 152, 153], "eye_mask": 62, "fb": [14, 15, 16, 36, 159, 171], "fc": [38, 39, 40, 42, 43], "fclk": 171, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 123, 139, 151], "fuse": [15, 16, 35, 36, 159], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 152, "gen3": 153, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 118, 134, 148], "general5": 62, "geometri": [58, 87, 104, 118, 134, 148], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 159, 161, 162, 163, 164, 165, 166], "gt": 91, "gth": 135, "gtp": [119, 148], "gtx": [120, 136, 148], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113, 129, 144], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": [113, 139], "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_hp": 151, "hclk_ioi_hr": 151, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 118, 148], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "ibuf": 23, "idcod": [35, 170], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 159, 161, 162, 163, 164, 165, 166], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 123, 139, 151, 157, 171], "instruct": [13, 35, 170], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 122, 129, 138, 144, 150], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 170], "intf": [55, 68, 91, 122, 138, 150], "introduct": [12, 34, 56, 92, 169], "io": [58, 79, 87, 100, 113, 139, 148, 157], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 159, 171], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 170], "isp": [13, 35, 170], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 160, 161, 162, 163, 164, 165, 166], "jtag": [13, 35, 170], "keeper": 36, "l": [43, 79, 93, 157], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 160], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 171, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 128, 143, 154], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 171, "mac": [117, 133], "macrocel": [14, 15, 16, 36, 159, 171], "manag": [51, 52, 64, 86, 102, 114, 130, 145], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 161, 162, 163, 164, 165, 166], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 148], "misc": [14, 36, 171], "mmcm": 145, "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 171], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 123, 139, 151, 157, 171], "overview": [14, 36, 171], "packag": [12, 34, 169], "part": [17, 160], "pci": [70, 80, 87, 94, 124, 140, 148, 152, 153], "pci_ce_delai": 61, "pcie_l": 152, "pcie_r": 152, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 161, 162, 163, 164, 165, 166, 169], "placement": 148, "pll": 145, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 129, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 118, 125], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 148, "product": [14, 15, 16, 36, 82, 159, 171], "program": [13, 35, 170], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 157], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 126, 141], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 115, 131, 146, 170, 171], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 148], "row": [38, 47, 58, 83, 87, 100, 171], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 170], "schema": [17, 160], "secondari": [38, 47, 58], "sequenc": [13, 35, 170], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 123, 139, 151], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 118], "splitter": [55, 158], "standard": [100, 113], "structur": [1, 14, 15, 16, 36, 58, 87, 104, 118, 134, 148, 159, 171], "sum": [14, 36, 82, 159, 171], "system": [109, 148], "t": [43, 57, 79, 83, 88, 89, 93, 157], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92, 114, 130, 145], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 159, 171], "termin": [55, 91, 100], "testmod": [62, 131, 146], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 114, 130, 145, 160], "timer": [62, 115, 131, 146], "tl": [52, 76, 155], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 115, 118, 119, 120, 121, 122, 127, 128, 129, 130, 131, 134, 135, 136, 137, 138, 142, 143, 144, 145, 146, 148, 149, 150, 151, 156, 170, 171], "top": [17, 38, 47, 61, 72, 77, 83, 91, 160], "tr": [52, 76, 155], "transceiv": [66, 88, 89, 105, 119, 120, 135, 136, 148], "trim": 131, "trim0": 146, "trim1": 146, "trim2": 146, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 171, "unk1c": 131, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 121, 137, 149], "w": 91, "wbstar": 146, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 159], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xadc": 142, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 156, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 161, "xcr3064xl": 162, "xcr3128xl": 163, "xcr3256xl": 164, "xcr3384xl": 165, "xcr3512xl": 166, "xilinx": [11, 33, 44, 168], "xor": [14, 36], "xpla3": 168, "xv": [16, 35, 36], "zia": 171}}) \ No newline at end of file diff --git a/xilinx/index.html b/xilinx/index.html index 9c1c7327..82ac656e 100644 --- a/xilinx/index.html +++ b/xilinx/index.html @@ -191,6 +191,7 @@

Xilinx FPGAsInput/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • @@ -208,6 +209,7 @@

    Xilinx FPGAsInput/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • @@ -222,10 +224,12 @@

    Xilinx FPGAsBlock RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • diff --git a/xilinx/spartan3/dcm-s3.html b/xilinx/spartan3/dcm-s3.html index a2abd379..f430ca4e 100644 --- a/xilinx/spartan3/dcm-s3.html +++ b/xilinx/spartan3/dcm-s3.html @@ -172,25 +172,25 @@

    DCM.S326 DCM:CFG_DLL_LP[1]DCM:DLLS[10]
    DCM:FACTORY_JF1[2]DCM:COM[10]DCM:MISC[11]
    DCM:STARTUP_WAIT 27 -DCM:CFG_DLL_LP[2]DCM:DLLS[11]
    DCM:FACTORY_JF1[3]DCM:COM[11]DCM:CONCUR
    DCM:MISC[10] +DCM:CFG_DLL_LP[2]DCM:DLLS[11]
    DCM:FACTORY_JF1[3]DCM:COM[11]DCM:ENABLE.CONCUR
    DCM:MISC[10] 28 -DCM:CFG_DLL_PS[0]DCM:DLLS[12]
    DCM:FACTORY_JF1[4]DCM:COM[12]DCM:CLKFX
    DCM:MISC[9] +DCM:CFG_DLL_PS[0]DCM:DLLS[12]
    DCM:FACTORY_JF1[4]DCM:COM[12]DCM:ENABLE.CLKFX
    DCM:MISC[9] 29 -DCM:CFG_DLL_PS[1]DCM:DLLS[13]
    DCM:FACTORY_JF1[5]DCM:COM[13]DCM:CLKFX180
    DCM:MISC[8] +DCM:CFG_DLL_PS[1]DCM:DLLS[13]
    DCM:FACTORY_JF1[5]DCM:COM[13]DCM:ENABLE.CLKFX180
    DCM:MISC[8] 30 -DCM:CFG_DLL_PS[2]DCM:DLLS[14]
    DCM:FACTORY_JF1[6]DCM:COM[14]DCM:CLKDV
    DCM:MISC[7] +DCM:CFG_DLL_PS[2]DCM:DLLS[14]
    DCM:FACTORY_JF1[6]DCM:COM[14]DCM:ENABLE.CLKDV
    DCM:MISC[7] 31 -DCM:CFG_DLL_PS[3]DCM:DLLS[15]
    DCM:FACTORY_JF1[7]DCM:COM[15]DCM:CLK2X180
    DCM:MISC[6] +DCM:CFG_DLL_PS[3]DCM:DLLS[15]
    DCM:FACTORY_JF1[7]DCM:COM[15]DCM:ENABLE.CLK2X180
    DCM:MISC[6] 32 -DCM:CFG_DLL_PS[4]DCM:DFS_ENABLE
    DCM:DLLS[16]DCM:CLKIN_DIVIDE_BY_2
    DCM:COM[16]DCM:CLK2X
    DCM:MISC[5] +DCM:CFG_DLL_PS[4]DCM:DFS_ENABLE
    DCM:DLLS[16]DCM:CLKIN_DIVIDE_BY_2
    DCM:COM[16]DCM:ENABLE.CLK2X
    DCM:MISC[5] 33 -DCM:CFG_DLL_PS[5]DCM:DLLS[17]
    DCM:DLL_ENABLEDCM:COM[17]
    DCM:DESKEW_ADJUST[0]DCM:CLK270
    DCM:MISC[4] +DCM:CFG_DLL_PS[5]DCM:DLLS[17]
    DCM:DLL_ENABLEDCM:COM[17]
    DCM:DESKEW_ADJUST[0]DCM:ENABLE.CLK270
    DCM:MISC[4] 34 -DCM:CFG_DLL_PS[6]DCM:CLKFB
    DCM:DLLS[18]DCM:COM[18]
    DCM:DESKEW_ADJUST[1]DCM:CLK180
    DCM:MISC[3] +DCM:CFG_DLL_PS[6]DCM:DLLS[18]
    DCM:ENABLE.CLKFBDCM:COM[18]
    DCM:DESKEW_ADJUST[1]DCM:ENABLE.CLK180
    DCM:MISC[3] 35 -DCM:CFG_DLL_PS[7]DCM:DLLS[19]
    DCM:PS_ENABLEDCM:COM[19]
    DCM:DESKEW_ADJUST[2]DCM:CLK90
    DCM:MISC[2] +DCM:CFG_DLL_PS[7]DCM:DLLS[19]
    DCM:PS_ENABLEDCM:COM[19]
    DCM:DESKEW_ADJUST[2]DCM:ENABLE.CLK90
    DCM:MISC[2] 36 -DCM:CFG_DLL_PS[8]DCM:DLLS[20]DCM:COM[20]
    DCM:DESKEW_ADJUST[3]DCM:CLK0
    DCM:MISC[1] +DCM:CFG_DLL_PS[8]DCM:DLLS[20]DCM:COM[20]
    DCM:DESKEW_ADJUST[3]DCM:ENABLE.CLK0
    DCM:MISC[1] 37 DCM:RESET_PS_SELDCM:DLLS[21]
    DCM:PHASE_SHIFT_NEGATIVEDCM:CLKIN_IOB
    DCM:COM[21]DCM:MISC[0] 38 @@ -246,23 +246,23 @@

    DCM.S363 ---~DCM:INV.STSADRS4 -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    @@ -287,23 +287,23 @@

    DCM.S3
    - - - - - - - - - - - + + + + + + + + + + + diff --git a/xilinx/spartan3/dcm-s3e.html b/xilinx/spartan3/dcm-s3e.html index 9d9c1d93..f65d0843 100644 --- a/xilinx/spartan3/dcm-s3e.html +++ b/xilinx/spartan3/dcm-s3e.html @@ -272,13 +272,13 @@

    DCM.S3E.BL

    - + - + - + - + @@ -320,11 +320,11 @@

    DCM.S3E.BL

     - + - + - + @@ -403,9 +403,9 @@

    DCM.S3E.BL

     - + - + @@ -817,44 +817,44 @@

    DCM.S3E.BL

    DCM:CLK0[0, 3, 36]
    DCM:CLK180[0, 3, 34]
    DCM:CLK270[0, 3, 33]
    DCM:CLK2X[0, 3, 32]
    DCM:CLK2X180[0, 3, 31]
    DCM:CLK90[0, 3, 35]
    DCM:CLKDV[0, 3, 30]
    DCM:CLKFB[0, 1, 34]
    DCM:CLKFB_IOB[0, 2, 38]
    DCM:CLKFX[0, 3, 28]
    DCM:CLKFX180[0, 3, 29]
    DCM:CLKIN_DIVIDE_BY_2[0, 2, 32]
    DCM:CLKIN_IOB[0, 2, 37]
    DCM:CONCUR[0, 3, 27]
    DCM:DFS_ENABLE[0, 1, 32]
    DCM:DFS_FEEDBACK[0, 2, 59]
    DCM:DLL_ENABLE[0, 1, 33]
    DCM:ENABLE.CLK0[0, 3, 36]
    DCM:ENABLE.CLK180[0, 3, 34]
    DCM:ENABLE.CLK270[0, 3, 33]
    DCM:ENABLE.CLK2X[0, 3, 32]
    DCM:ENABLE.CLK2X180[0, 3, 31]
    DCM:ENABLE.CLK90[0, 3, 35]
    DCM:ENABLE.CLKDV[0, 3, 30]
    DCM:ENABLE.CLKFB[0, 1, 34]
    DCM:ENABLE.CLKFX[0, 3, 28]
    DCM:ENABLE.CLKFX180[0, 3, 29]
    DCM:ENABLE.CONCUR[0, 3, 27]
    DCM:EN_DUMMY_OSC[0, 0, 40]
    DCM:EN_OLD_OSCCTL[0, 0, 16]
    DCM:EN_OSC_COARSE[0, 0, 44]
    8 -
    9DCM:CLK0
    DCM:DLL_C[19]
    DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    10DCM:CLK180
    DCM:DLL_C[20]
    DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    11DCM:CLK90
    DCM:DLL_C[21]
    DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    12DCM:CLK270
    DCM:DLL_C[22]
    DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    13 DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    1432 DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    33DCM:CLK2X
    DCM:DLL_C[23]
    DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    34DCM:CLK2X180
    DCM:DLL_C[24]
    DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    35DCM:CLKDV
    DCM:DLL_C[25]
    DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    36 DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    375 ------------------DCM:DFS_S[19]
    6------------------DCM:CONCUR
    DCM:DFS_S[25]
    ------------------DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    7------------------DCM:CLKFX
    DCM:DFS_S[24]
    ------------------DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    8 -------------------
    9DCM:DFS_C[1, 0, 5][1, 0, 7][1, 0, 6]
    Non-inverted[2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -1081,13 +1081,13 @@

    DCM.S3E.BR

    - + - + - + - + @@ -1129,11 +1129,11 @@

    DCM.S3E.BR

     - + - + - + @@ -1364,9 +1364,9 @@

    DCM.S3E.BR

     - + - + @@ -1778,44 +1778,44 @@

    DCM.S3E.BR

    DCM:CLK0[1, 0, 9]
    DCM:CLK180[1, 0, 10]
    DCM:CLK270[1, 0, 12]
    DCM:CLK2X[1, 0, 33]
    DCM:CLK2X180[1, 0, 34]
    DCM:CLK90[1, 0, 11]
    DCM:CLKDV[1, 0, 35]
    DCM:CLKFB_IOB[1, 0, 37]
    DCM:CLKFX[4, 18, 7]
    DCM:CLKIN_DIVIDE_BY_2[1, 0, 48]
    DCM:CLKIN_IOB[1, 0, 36]
    DCM:CONCUR[4, 18, 6]
    DCM:DFS_ENABLE[4, 18, 12]
    DCM:DFS_FEEDBACK[4, 18, 43]
    DCM:DLL_ENABLE[2, 0, 0]
    DCM:DUTY_CYCLE_CORRECTION[1, 0, 13]
    DCM:ENABLE.CLK0[1, 0, 9]
    DCM:ENABLE.CLK180[1, 0, 10]
    DCM:ENABLE.CLK270[1, 0, 12]
    DCM:ENABLE.CLK2X[1, 0, 33]
    DCM:ENABLE.CLK2X180[1, 0, 34]
    DCM:ENABLE.CLK90[1, 0, 11]
    DCM:ENABLE.CLKDV[1, 0, 35]
    DCM:ENABLE.CLKFX[4, 18, 7]
    DCM:ENABLE.CONCUR[4, 18, 6]
    DCM:PERIOD_NOT_HF[6, 18, 1]
    DCM:PHASE_SHIFT_NEGATIVE[6, 18, 60]
    DCM:PS_ENABLE[1, 0, 40]
    8 -------------------
    9------------------DCM:CLK0
    DCM:DLL_C[19]
    ------------------DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    10------------------DCM:CLK180
    DCM:DLL_C[20]
    ------------------DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    11------------------DCM:CLK90
    DCM:DLL_C[21]
    ------------------DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    12------------------DCM:CLK270
    DCM:DLL_C[22]
    ------------------DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    13 ------------------DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    1432 ------------------DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    33------------------DCM:CLK2X
    DCM:DLL_C[23]
    ------------------DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    34------------------DCM:CLK2X180
    DCM:DLL_C[24]
    ------------------DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    35------------------DCM:CLKDV
    DCM:DLL_C[25]
    ------------------DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    36 ------------------DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    375 DCM:DFS_S[19]
    6DCM:CONCUR
    DCM:DFS_S[25]
    DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    7DCM:CLKFX
    DCM:DFS_S[24]
    DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    8 -
    9DCM:DFS_C[1, 18, 5][1, 18, 7][1, 18, 6]
    Non-inverted[2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -2221,11 +2221,11 @@

    DCM.S3E.TL

    - + - + - + @@ -2267,13 +2267,13 @@

    DCM.S3E.TL

     - + - + - + - + @@ -2661,9 +2661,9 @@

    DCM.S3E.TL

     - + - + @@ -2708,44 +2708,44 @@

    DCM.S3E.TL

    DCM:CLK0[1, 18, 9]
    DCM:CLK180[1, 18, 10]
    DCM:CLK270[1, 18, 12]
    DCM:CLK2X[1, 18, 33]
    DCM:CLK2X180[1, 18, 34]
    DCM:CLK90[1, 18, 11]
    DCM:CLKDV[1, 18, 35]
    DCM:CLKFB_IOB[1, 18, 37]
    DCM:CLKFX[4, 0, 7]
    DCM:CLKIN_DIVIDE_BY_2[1, 18, 48]
    DCM:CLKIN_IOB[1, 18, 36]
    DCM:CONCUR[4, 0, 6]
    DCM:DFS_ENABLE[4, 0, 12]
    DCM:DFS_FEEDBACK[4, 0, 43]
    DCM:DLL_ENABLE[2, 18, 0]
    DCM:DUTY_CYCLE_CORRECTION[1, 18, 13]
    DCM:ENABLE.CLK0[1, 18, 9]
    DCM:ENABLE.CLK180[1, 18, 10]
    DCM:ENABLE.CLK270[1, 18, 12]
    DCM:ENABLE.CLK2X[1, 18, 33]
    DCM:ENABLE.CLK2X180[1, 18, 34]
    DCM:ENABLE.CLK90[1, 18, 11]
    DCM:ENABLE.CLKDV[1, 18, 35]
    DCM:ENABLE.CLKFX[4, 0, 7]
    DCM:ENABLE.CONCUR[4, 0, 6]
    DCM:PERIOD_NOT_HF[6, 0, 1]
    DCM:PHASE_SHIFT_NEGATIVE[6, 0, 60]
    DCM:PS_ENABLE[1, 18, 40]
    27 DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    28DCM:CLKDV
    DCM:DLL_C[25]
    DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    29DCM:CLK2X180
    DCM:DLL_C[24]
    DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    30DCM:CLK2X
    DCM:DLL_C[23]
    DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    31 DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    3250 DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    51DCM:CLK270
    DCM:DLL_C[22]
    DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    52DCM:CLK90
    DCM:DLL_C[21]
    DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    53DCM:CLK180
    DCM:DLL_C[20]
    DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    54DCM:CLK0
    DCM:DLL_C[19]
    DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    55 -
    5655 -------------------
    56------------------DCM:CLKFX
    DCM:DFS_S[24]
    ------------------DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    57------------------DCM:CONCUR
    DCM:DFS_S[25]
    ------------------DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    58 ------------------DCM:DFS_S[19]
    59DCM:INV.STSADRS4[0, 3, 61]
    Inverted~[0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -3181,11 +3181,11 @@

    DCM.S3E.TR

    - + - + - + @@ -3227,13 +3227,13 @@

    DCM.S3E.TR

     - + - + - + - + @@ -3621,9 +3621,9 @@

    DCM.S3E.TR

     - + - + @@ -3686,44 +3686,44 @@

    DCM.S3E.TR

    DCM:CLK0[3, 0, 54]
    DCM:CLK180[3, 0, 53]
    DCM:CLK270[3, 0, 51]
    DCM:CLK2X[3, 0, 30]
    DCM:CLK2X180[3, 0, 29]
    DCM:CLK90[3, 0, 52]
    DCM:CLKDV[3, 0, 28]
    DCM:CLKFB_IOB[3, 0, 26]
    DCM:CLKFX[7, 18, 56]
    DCM:CLKIN_DIVIDE_BY_2[3, 0, 15]
    DCM:CLKIN_IOB[3, 0, 27]
    DCM:CONCUR[7, 18, 57]
    DCM:DFS_ENABLE[7, 18, 51]
    DCM:DFS_FEEDBACK[7, 18, 20]
    DCM:DLL_ENABLE[2, 0, 63]
    DCM:DUTY_CYCLE_CORRECTION[3, 0, 50]
    DCM:ENABLE.CLK0[3, 0, 54]
    DCM:ENABLE.CLK180[3, 0, 53]
    DCM:ENABLE.CLK270[3, 0, 51]
    DCM:ENABLE.CLK2X[3, 0, 30]
    DCM:ENABLE.CLK2X180[3, 0, 29]
    DCM:ENABLE.CLK90[3, 0, 52]
    DCM:ENABLE.CLKDV[3, 0, 28]
    DCM:ENABLE.CLKFX[7, 18, 56]
    DCM:ENABLE.CONCUR[7, 18, 57]
    DCM:PERIOD_NOT_HF[5, 18, 62]
    DCM:PHASE_SHIFT_NEGATIVE[5, 18, 3]
    DCM:PS_ENABLE[3, 0, 23]
    27 ------------------DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    28------------------DCM:CLKDV
    DCM:DLL_C[25]
    ------------------DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    29------------------DCM:CLK2X180
    DCM:DLL_C[24]
    ------------------DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    30------------------DCM:CLK2X
    DCM:DLL_C[23]
    ------------------DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    31 ------------------DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    3250 ------------------DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    51------------------DCM:CLK270
    DCM:DLL_C[22]
    ------------------DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    52------------------DCM:CLK90
    DCM:DLL_C[21]
    ------------------DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    53------------------DCM:CLK180
    DCM:DLL_C[20]
    ------------------DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    54------------------DCM:CLK0
    DCM:DLL_C[19]
    ------------------DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    55 -------------------
    5655 -
    56DCM:CLKFX
    DCM:DFS_S[24]
    DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    57DCM:CONCUR
    DCM:DFS_S[25]
    DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    58 DCM:DFS_S[19]
    59DCM_VREG:VREG[2, 18, 46][2, 18, 48][2, 18, 53][2, 18, 55][2, 18, 57][2, 18, 60][2, 18, 32][2, 18, 49][2, 18, 52][2, 18, 40][2, 18, 38][2, 18, 33][2, 18, 36][2, 18, 41][1, 18, 15][1, 18, 13][1, 18, 12][1, 18, 9][2, 18, 44][2, 18, 29]
    Non-inverted[19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -4116,11 +4116,11 @@

    DCM.S3E.LB

    - + - + - + @@ -4162,13 +4162,13 @@

    DCM.S3E.LB

     - + - + - + - + @@ -4556,9 +4556,9 @@

    DCM.S3E.LB

     - + - + @@ -4603,44 +4603,44 @@

    DCM.S3E.LB

    DCM:CLK0[3, 18, 54]
    DCM:CLK180[3, 18, 53]
    DCM:CLK270[3, 18, 51]
    DCM:CLK2X[3, 18, 30]
    DCM:CLK2X180[3, 18, 29]
    DCM:CLK90[3, 18, 52]
    DCM:CLKDV[3, 18, 28]
    DCM:CLKFB_IOB[3, 18, 26]
    DCM:CLKFX[7, 0, 56]
    DCM:CLKIN_DIVIDE_BY_2[3, 18, 15]
    DCM:CLKIN_IOB[3, 18, 27]
    DCM:CONCUR[7, 0, 57]
    DCM:DFS_ENABLE[7, 0, 51]
    DCM:DFS_FEEDBACK[7, 0, 20]
    DCM:DLL_ENABLE[2, 18, 63]
    DCM:DUTY_CYCLE_CORRECTION[3, 18, 50]
    DCM:ENABLE.CLK0[3, 18, 54]
    DCM:ENABLE.CLK180[3, 18, 53]
    DCM:ENABLE.CLK270[3, 18, 51]
    DCM:ENABLE.CLK2X[3, 18, 30]
    DCM:ENABLE.CLK2X180[3, 18, 29]
    DCM:ENABLE.CLK90[3, 18, 52]
    DCM:ENABLE.CLKDV[3, 18, 28]
    DCM:ENABLE.CLKFX[7, 0, 56]
    DCM:ENABLE.CONCUR[7, 0, 57]
    DCM:PERIOD_NOT_HF[5, 0, 62]
    DCM:PHASE_SHIFT_NEGATIVE[5, 0, 3]
    DCM:PS_ENABLE[3, 18, 23]
    27 ------------------DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    28------------------DCM:CLKDV
    DCM:DLL_C[25]
    ------------------DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    29------------------DCM:CLK2X180
    DCM:DLL_C[24]
    ------------------DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    30------------------DCM:CLK2X
    DCM:DLL_C[23]
    ------------------DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    31 ------------------DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    3250 ------------------DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    51------------------DCM:CLK270
    DCM:DLL_C[22]
    ------------------DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    52------------------DCM:CLK90
    DCM:DLL_C[21]
    ------------------DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    53------------------DCM:CLK180
    DCM:DLL_C[20]
    ------------------DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    54------------------DCM:CLK0
    DCM:DLL_C[19]
    ------------------DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    55 -------------------
    5655 -
    56DCM:CLKFX
    DCM:DFS_S[24]
    DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    57DCM:CONCUR
    DCM:DFS_S[25]
    DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    58 DCM:DFS_S[19]
    59DCM:INV.STSADRS4[0, 3, 61]
    Inverted~[0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -4872,13 +4872,13 @@

    DCM.S3E.LT

    - + - + - + - + @@ -4920,11 +4920,11 @@

    DCM.S3E.LT

     - + - + - + @@ -5155,9 +5155,9 @@

    DCM.S3E.LT

     - + - + @@ -5569,44 +5569,44 @@

    DCM.S3E.LT

    DCM:CLK0[3, 18, 54]
    DCM:CLK180[3, 18, 53]
    DCM:CLK270[3, 18, 51]
    DCM:CLK2X[3, 18, 30]
    DCM:CLK2X180[3, 18, 29]
    DCM:CLK90[3, 18, 52]
    DCM:CLKDV[3, 18, 28]
    DCM:CLKFB_IOB[3, 18, 26]
    DCM:CLKFX[7, 0, 56]
    DCM:CLKIN_DIVIDE_BY_2[3, 18, 15]
    DCM:CLKIN_IOB[3, 18, 27]
    DCM:CONCUR[7, 0, 57]
    DCM:DFS_ENABLE[7, 0, 51]
    DCM:DFS_FEEDBACK[7, 0, 20]
    DCM:DLL_ENABLE[2, 18, 63]
    DCM:DUTY_CYCLE_CORRECTION[3, 18, 50]
    DCM:ENABLE.CLK0[3, 18, 54]
    DCM:ENABLE.CLK180[3, 18, 53]
    DCM:ENABLE.CLK270[3, 18, 51]
    DCM:ENABLE.CLK2X[3, 18, 30]
    DCM:ENABLE.CLK2X180[3, 18, 29]
    DCM:ENABLE.CLK90[3, 18, 52]
    DCM:ENABLE.CLKDV[3, 18, 28]
    DCM:ENABLE.CLKFX[7, 0, 56]
    DCM:ENABLE.CONCUR[7, 0, 57]
    DCM:PERIOD_NOT_HF[5, 0, 62]
    DCM:PHASE_SHIFT_NEGATIVE[5, 0, 3]
    DCM:PS_ENABLE[3, 18, 23]
    8 -------------------
    9------------------DCM:CLK0
    DCM:DLL_C[19]
    ------------------DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    10------------------DCM:CLK180
    DCM:DLL_C[20]
    ------------------DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    11------------------DCM:CLK90
    DCM:DLL_C[21]
    ------------------DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    12------------------DCM:CLK270
    DCM:DLL_C[22]
    ------------------DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    13 ------------------DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    1432 ------------------DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    33------------------DCM:CLK2X
    DCM:DLL_C[23]
    ------------------DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    34------------------DCM:CLK2X180
    DCM:DLL_C[24]
    ------------------DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    35------------------DCM:CLKDV
    DCM:DLL_C[25]
    ------------------DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    36 ------------------DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    375 DCM:DFS_S[19]
    6DCM:CONCUR
    DCM:DFS_S[25]
    DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    7DCM:CLKFX
    DCM:DFS_S[24]
    DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    8 -
    9DCM:DFS_C[1, 18, 5][1, 18, 7][1, 18, 6]
    Non-inverted[2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -6044,11 +6044,11 @@

    DCM.S3E.RB

    - + - + - + @@ -6090,13 +6090,13 @@

    DCM.S3E.RB

     - + - + - + - + @@ -6484,9 +6484,9 @@

    DCM.S3E.RB

     - + - + @@ -6549,44 +6549,44 @@

    DCM.S3E.RB

    DCM:CLK0[1, 18, 9]
    DCM:CLK180[1, 18, 10]
    DCM:CLK270[1, 18, 12]
    DCM:CLK2X[1, 18, 33]
    DCM:CLK2X180[1, 18, 34]
    DCM:CLK90[1, 18, 11]
    DCM:CLKDV[1, 18, 35]
    DCM:CLKFB_IOB[1, 18, 37]
    DCM:CLKFX[4, 0, 7]
    DCM:CLKIN_DIVIDE_BY_2[1, 18, 48]
    DCM:CLKIN_IOB[1, 18, 36]
    DCM:CONCUR[4, 0, 6]
    DCM:DFS_ENABLE[4, 0, 12]
    DCM:DFS_FEEDBACK[4, 0, 43]
    DCM:DLL_ENABLE[2, 18, 0]
    DCM:DUTY_CYCLE_CORRECTION[1, 18, 13]
    DCM:ENABLE.CLK0[1, 18, 9]
    DCM:ENABLE.CLK180[1, 18, 10]
    DCM:ENABLE.CLK270[1, 18, 12]
    DCM:ENABLE.CLK2X[1, 18, 33]
    DCM:ENABLE.CLK2X180[1, 18, 34]
    DCM:ENABLE.CLK90[1, 18, 11]
    DCM:ENABLE.CLKDV[1, 18, 35]
    DCM:ENABLE.CLKFX[4, 0, 7]
    DCM:ENABLE.CONCUR[4, 0, 6]
    DCM:PERIOD_NOT_HF[6, 0, 1]
    DCM:PHASE_SHIFT_NEGATIVE[6, 0, 60]
    DCM:PS_ENABLE[1, 18, 40]
    27 DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    28DCM:CLKDV
    DCM:DLL_C[25]
    DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    29DCM:CLK2X180
    DCM:DLL_C[24]
    DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    30DCM:CLK2X
    DCM:DLL_C[23]
    DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    31 DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    3250 DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    51DCM:CLK270
    DCM:DLL_C[22]
    DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    52DCM:CLK90
    DCM:DLL_C[21]
    DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    53DCM:CLK180
    DCM:DLL_C[20]
    DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    54DCM:CLK0
    DCM:DLL_C[19]
    DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    55 -
    5655 -------------------
    56------------------DCM:CLKFX
    DCM:DFS_S[24]
    ------------------DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    57------------------DCM:CONCUR
    DCM:DFS_S[25]
    ------------------DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    58 ------------------DCM:DFS_S[19]
    59DCM_VREG:VREG[2, 0, 46][2, 0, 48][2, 0, 53][2, 0, 55][2, 0, 57][2, 0, 60][2, 0, 32][2, 0, 49][2, 0, 52][2, 0, 40][2, 0, 38][2, 0, 33][2, 0, 36][2, 0, 41][1, 0, 15][1, 0, 13][1, 0, 12][1, 0, 9][2, 0, 44][2, 0, 29]
    Non-inverted[19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + @@ -6807,13 +6807,13 @@

    DCM.S3E.RT

    - + - + - + - + @@ -6855,11 +6855,11 @@

    DCM.S3E.RT

     - + - + - + @@ -6938,9 +6938,9 @@

    DCM.S3E.RT

     - + - + @@ -7352,44 +7352,44 @@

    DCM.S3E.RT

    DCM:CLK0[3, 0, 54]
    DCM:CLK180[3, 0, 53]
    DCM:CLK270[3, 0, 51]
    DCM:CLK2X[3, 0, 30]
    DCM:CLK2X180[3, 0, 29]
    DCM:CLK90[3, 0, 52]
    DCM:CLKDV[3, 0, 28]
    DCM:CLKFB_IOB[3, 0, 26]
    DCM:CLKFX[7, 18, 56]
    DCM:CLKIN_DIVIDE_BY_2[3, 0, 15]
    DCM:CLKIN_IOB[3, 0, 27]
    DCM:CONCUR[7, 18, 57]
    DCM:DFS_ENABLE[7, 18, 51]
    DCM:DFS_FEEDBACK[7, 18, 20]
    DCM:DLL_ENABLE[2, 0, 63]
    DCM:DUTY_CYCLE_CORRECTION[3, 0, 50]
    DCM:ENABLE.CLK0[3, 0, 54]
    DCM:ENABLE.CLK180[3, 0, 53]
    DCM:ENABLE.CLK270[3, 0, 51]
    DCM:ENABLE.CLK2X[3, 0, 30]
    DCM:ENABLE.CLK2X180[3, 0, 29]
    DCM:ENABLE.CLK90[3, 0, 52]
    DCM:ENABLE.CLKDV[3, 0, 28]
    DCM:ENABLE.CLKFX[7, 18, 56]
    DCM:ENABLE.CONCUR[7, 18, 57]
    DCM:PERIOD_NOT_HF[5, 18, 62]
    DCM:PHASE_SHIFT_NEGATIVE[5, 18, 3]
    DCM:PS_ENABLE[3, 0, 23]
    8 -
    9DCM:CLK0
    DCM:DLL_C[19]
    DCM:DLL_C[19]
    DCM:ENABLE.CLK0
    10DCM:CLK180
    DCM:DLL_C[20]
    DCM:DLL_C[20]
    DCM:ENABLE.CLK180
    11DCM:CLK90
    DCM:DLL_C[21]
    DCM:DLL_C[21]
    DCM:ENABLE.CLK90
    12DCM:CLK270
    DCM:DLL_C[22]
    DCM:DLL_C[22]
    DCM:ENABLE.CLK270
    13 DCM:DLL_C[0]
    DCM:DUTY_CYCLE_CORRECTION
    1432 DCM:DESKEW_ADJUST[1]
    DCM:INTERFACE[4]
    33DCM:CLK2X
    DCM:DLL_C[23]
    DCM:DLL_C[23]
    DCM:ENABLE.CLK2X
    34DCM:CLK2X180
    DCM:DLL_C[24]
    DCM:DLL_C[24]
    DCM:ENABLE.CLK2X180
    35DCM:CLKDV
    DCM:DLL_C[25]
    DCM:DLL_C[25]
    DCM:ENABLE.CLKDV
    36 DCM:CLKIN_IOB
    DCM:INTERFACE[8]
    375 ------------------DCM:DFS_S[19]
    6------------------DCM:CONCUR
    DCM:DFS_S[25]
    ------------------DCM:DFS_S[25]
    DCM:ENABLE.CONCUR
    7------------------DCM:CLKFX
    DCM:DFS_S[24]
    ------------------DCM:DFS_S[24]
    DCM:ENABLE.CLKFX
    8 -------------------
    9DCM:DFS_C[1, 0, 5][1, 0, 7][1, 0, 6]
    Non-inverted[2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - + + + + + + + + + diff --git a/xilinx/spartan6/dcm.html b/xilinx/spartan6/dcm.html index fc7dc021..35113b14 100644 --- a/xilinx/spartan6/dcm.html +++ b/xilinx/spartan6/dcm.html @@ -592,9 +592,9 @@

    BitstreamDCM0:CONCUR
    DCM0:DFS_S[25] +

    - + @@ -711,7 +711,7 @@

    BitstreamDCM0:DFS_S[76]
    DCM0:SPREAD_SPECTRUM[9]

    - + @@ -747,11 +747,11 @@

    BitstreamDCM1:INTERFACE[35]
    DCM1:MUX.SKEWCLKIN2[2]

    - + - + - + @@ -768,11 +768,11 @@

    BitstreamDCM0:INTERFACE[17]

    - + - + - + @@ -1017,9 +1017,9 @@

    BitstreamDCM1:CLKDV_COUNT_MAX[2]
    DCM1:DLL_C[3]

    - + - + @@ -1084,31 +1084,31 @@

    BitstreamDCM1:DFS_S[41]
    DCM1:SPREAD_SPECTRUM[3]

    - + - + - + - + - + - + - + @@ -2144,23 +2144,23 @@

    Bitstream -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    @@ -2185,23 +2185,23 @@

    Bitstream
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    @@ -2227,23 +2227,23 @@

    Bitstream

    DCM:CLK0[1, 0, 9]
    DCM:CLK180[1, 0, 10]
    DCM:CLK270[1, 0, 12]
    DCM:CLK2X[1, 0, 33]
    DCM:CLK2X180[1, 0, 34]
    DCM:CLK90[1, 0, 11]
    DCM:CLKDV[1, 0, 35]
    DCM:CLKFB_IOB[1, 0, 37]
    DCM:CLKFX[4, 18, 7]
    DCM:CLKIN_DIVIDE_BY_2[1, 0, 48]
    DCM:CLKIN_IOB[1, 0, 36]
    DCM:CONCUR[4, 18, 6]
    DCM:DFS_ENABLE[4, 18, 12]
    DCM:DFS_FEEDBACK[4, 18, 43]
    DCM:DLL_ENABLE[2, 0, 0]
    DCM:DUTY_CYCLE_CORRECTION[1, 0, 13]
    DCM:ENABLE.CLK0[1, 0, 9]
    DCM:ENABLE.CLK180[1, 0, 10]
    DCM:ENABLE.CLK270[1, 0, 12]
    DCM:ENABLE.CLK2X[1, 0, 33]
    DCM:ENABLE.CLK2X180[1, 0, 34]
    DCM:ENABLE.CLK90[1, 0, 11]
    DCM:ENABLE.CLKDV[1, 0, 35]
    DCM:ENABLE.CLKFX[4, 18, 7]
    DCM:ENABLE.CONCUR[4, 18, 6]
    DCM:PERIOD_NOT_HF[6, 18, 1]
    DCM:PHASE_SHIFT_NEGATIVE[6, 18, 60]
    DCM:PS_ENABLE[1, 0, 40]
    ------------------------------DCM0:DFS_S[25]
    DCM0:ENABLE.CONCUR
    46------------------------------DCM0:CLKFX
    DCM0:DFS_S[24]
    ------------------------------DCM0:DFS_S[24]
    DCM0:ENABLE.CLKFX
    47 -------------------------------
    48
    41------------------------------DCM0:CLK0
    DCM0:DLL_C[19]
    ------------------------------DCM0:DLL_C[19]
    DCM0:ENABLE.CLK0
    42 -------------------------------
    43
    59------------------------------DCM0:CLK180
    DCM0:DLL_C[20]
    ------------------------------DCM0:DLL_C[20]
    DCM0:ENABLE.CLK180
    60------------------------------DCM0:CLK90
    DCM0:DLL_C[21]
    ------------------------------DCM0:DLL_C[21]
    DCM0:ENABLE.CLK90
    61------------------------------DCM0:CLK270
    DCM0:DLL_C[22]
    ------------------------------DCM0:DLL_C[22]
    DCM0:ENABLE.CLK270
    62 -------------------------------
    63
    4------------------------------DCM0:CLK2X
    DCM0:DLL_C[23]
    ------------------------------DCM0:DLL_C[23]
    DCM0:ENABLE.CLK2X
    5------------------------------DCM0:CLK2X180
    DCM0:DLL_C[24]
    ------------------------------DCM0:DLL_C[24]
    DCM0:ENABLE.CLK2X180
    6------------------------------DCM0:CLKDV
    DCM0:DLL_C[25]
    ------------------------------DCM0:DLL_C[25]
    DCM0:ENABLE.CLKDV
    7 ------------------------------DCM0:INTERFACE[9]
    8
    60------------------------------DCM1:CLKFX
    DCM1:DFS_S[24]
    ------------------------------DCM1:DFS_S[24]
    DCM1:ENABLE.CLKFX
    61------------------------------DCM1:CONCUR
    DCM1:DFS_S[25]
    ------------------------------DCM1:DFS_S[25]
    DCM1:ENABLE.CONCUR
    62 ------------------------------DCM1:CLKDV_COUNT_MAX[3]
    DCM1:DLL_C[4]
    63
    28------------------------------DCM1:CLK0
    DCM1:DLL_C[19]
    ------------------------------DCM1:DLL_C[19]
    DCM1:ENABLE.CLK0
    29------------------------------DCM1:CLK180
    DCM1:DLL_C[20]
    ------------------------------DCM1:DLL_C[20]
    DCM1:ENABLE.CLK180
    30 ------------------------------DCM1:DFS_S[42]
    31 ------------------------------DCM1:DFS_S[43]
    32------------------------------DCM1:CLK90
    DCM1:DLL_C[21]
    ------------------------------DCM1:DLL_C[21]
    DCM1:ENABLE.CLK90
    33------------------------------DCM1:CLK270
    DCM1:DLL_C[22]
    ------------------------------DCM1:DLL_C[22]
    DCM1:ENABLE.CLK270
    34 ------------------------------DCM1:DFS_S[44]
    DCM1:SPREAD_SPECTRUM[8]
    35 ------------------------------DCM1:DFS_S[45]
    DCM1:SPREAD_SPECTRUM[4]
    36------------------------------DCM1:CLK2X
    DCM1:DLL_C[23]
    ------------------------------DCM1:DLL_C[23]
    DCM1:ENABLE.CLK2X
    37------------------------------DCM1:CLK2X180
    DCM1:DLL_C[24]
    ------------------------------DCM1:DLL_C[24]
    DCM1:ENABLE.CLK2X180
    38 ------------------------------DCM1:DFS_S[46]
    39 ------------------------------DCM1:DFS_S[47]
    DCM1:SPREAD_SPECTRUM[11]
    40------------------------------DCM1:CLKDV
    DCM1:DLL_C[25]
    ------------------------------DCM1:DLL_C[25]
    DCM1:ENABLE.CLKDV
    41 ------------------------------DCM1:DFS_S[48]
    42
    - - - - - - - - - + + + + + + + + + @@ -2268,23 +2268,23 @@

    BitstreamDCM.V2

    - + @@ -218,25 +218,25 @@

    DCM.V2

     - + - + - + - + - + - + - + - + - + - + @@ -329,24 +329,24 @@

    DCM.V2

    DCM0:BUF.CLK_FROM_PLL[6, 30, 57]
    DCM0:CLK0[5, 30, 41]
    DCM0:CLK180[5, 30, 59]
    DCM0:CLK270[5, 30, 61]
    DCM0:CLK2X[6, 30, 4]
    DCM0:CLK2X180[6, 30, 5]
    DCM0:CLK90[5, 30, 60]
    DCM0:CLKDV[6, 30, 6]
    DCM0:CLKFB_IOB[6, 30, 20]
    DCM0:CLKFX[4, 30, 46]
    DCM0:CLKIN_CLKFB_ENABLE[6, 30, 40]
    DCM0:CLKIN_DIVIDE_BY_2[6, 30, 31]
    DCM0:CLKIN_IOB[6, 30, 16]
    DCM0:CONCUR[4, 30, 45]
    DCM0:DFS_ENABLE[4, 30, 42]
    DCM0:DFS_FEEDBACK[4, 30, 50]
    DCM0:DLL_ENABLE[2, 30, 59]
    DCM0:DUTY_CYCLE_CORRECTION[5, 30, 57]
    DCM0:ENABLE.CLK0[5, 30, 41]
    DCM0:ENABLE.CLK180[5, 30, 59]
    DCM0:ENABLE.CLK270[5, 30, 61]
    DCM0:ENABLE.CLK2X[6, 30, 4]
    DCM0:ENABLE.CLK2X180[6, 30, 5]
    DCM0:ENABLE.CLK90[5, 30, 60]
    DCM0:ENABLE.CLKDV[6, 30, 6]
    DCM0:ENABLE.CLKFX[4, 30, 46]
    DCM0:ENABLE.CONCUR[4, 30, 45]
    DCM0:INV.CTLGO[6, 30, 53]
    DCM0:INV.CTLMODE[5, 30, 44]
    DCM0:INV.CTLOSC1[6, 30, 58]
    17 DCM:DLLS[17]
    DCM:DLL_ENABLE    		--DCM:CLKFX_DIVIDE[1]
    DCM:DFS[1]
    18DCM:CLKFB
    DCM:DLLS[18]    		--DCM:CLKFX_DIVIDE[2]
    DCM:DFS[2]
    DCM:DLLS[18]
    DCM:ENABLE.CLKFB    		--DCM:CLKFX_DIVIDE[2]
    DCM:DFS[2]
    19 DCM:DLLS[19]
    DCM:PS_ENABLE    		--DCM:CLKFX_DIVIDE[3]
    DCM:DFS[3]
    2048 DCM:CLKDV_PHASE_RISE[0]
    DCM:DLLC[16]    		--DCM:MISC[0]
    49DCM:CLKDV_PHASE_RISE[1]
    DCM:DLLC[17]    		--DCM:CLK0
    DCM:MISC[1]
    DCM:CLKDV_PHASE_RISE[1]
    DCM:DLLC[17]    		--DCM:ENABLE.CLK0
    DCM:MISC[1]
    50DCM:CLKDV_PHASE_FALL[0]
    DCM:DLLC[18]    		--DCM:CLK90
    DCM:MISC[2]
    DCM:CLKDV_PHASE_FALL[0]
    DCM:DLLC[18]    		--DCM:ENABLE.CLK90
    DCM:MISC[2]
    51DCM:CLKDV_PHASE_FALL[1]
    DCM:DLLC[19]    		--DCM:CLK180
    DCM:MISC[3]
    DCM:CLKDV_PHASE_FALL[1]
    DCM:DLLC[19]    		--DCM:ENABLE.CLK180
    DCM:MISC[3]
    52DCM:CLKDV_MODE
    DCM:DLLC[20]    		--DCM:CLK270
    DCM:MISC[4]
    DCM:CLKDV_MODE
    DCM:DLLC[20]    		--DCM:ENABLE.CLK270
    DCM:MISC[4]
    53DCM:DLLC[21]
    DCM:TEST_OSC[0]    		--DCM:CLK2X
    DCM:MISC[5]
    DCM:DLLC[21]
    DCM:TEST_OSC[0]    		--DCM:ENABLE.CLK2X
    DCM:MISC[5]
    54DCM:DLLC[22]
    DCM:TEST_OSC[1]    		--DCM:CLK2X180
    DCM:MISC[6]
    DCM:DLLC[22]
    DCM:TEST_OSC[1]    		--DCM:ENABLE.CLK2X180
    DCM:MISC[6]
    55DCM:CLK_FEEDBACK
    DCM:DLLC[23]    		--DCM:CLKDV
    DCM:MISC[7]
    DCM:CLK_FEEDBACK
    DCM:DLLC[23]    		--DCM:ENABLE.CLKDV
    DCM:MISC[7]
    56DCM:DLLC[24]
    DCM:DLL_FREQUENCY_MODE    		--DCM:CLKFX180
    DCM:MISC[8]
    DCM:DLLC[24]
    DCM:DLL_FREQUENCY_MODE    		--DCM:ENABLE.CLKFX180
    DCM:MISC[8]
    57DCM:DLLC[25]
    DCM:PS_CENTERED    		--DCM:CLKFX
    DCM:MISC[9]
    DCM:DLLC[25]
    DCM:PS_CENTERED    		--DCM:ENABLE.CLKFX
    DCM:MISC[9]
    58DCM:DLLC[26]
    DCM:PS_MODE    		--DCM:CONCUR
    DCM:MISC[10]
    DCM:DLLC[26]
    DCM:PS_MODE    		--DCM:ENABLE.CONCUR
    DCM:MISC[10]
    59 DCM:DLLC[27]
    DCM:STATUS7    		--DCM:MISC[11]
    DCM:STARTUP_WAIT
    60DCM:MISC[0, 3, 79][0, 3, 78][0, 3, 77][0, 3, 76][0, 3, 75][0, 3, 74][0, 3, 73][0, 3, 72][0, 3, 71][0, 3, 70][0, 3, 69][0, 3, 68][0, 3, 67][0, 3, 66][0, 3, 65][0, 3, 64][0, 3, 63][0, 3, 62][0, 3, 61][0, 3, 60][0, 3, 59][0, 3, 58][0, 3, 57][0, 3, 56][0, 3, 55][0, 3, 54][0, 3, 53][0, 3, 52][0, 3, 51][0, 3, 50][0, 3, 49][0, 3, 48]
    Non-inverted[31][30][29][28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    @@ -360,24 +360,24 @@

    DCM.V2
    - - - - - - - - - - - + + + + + + + + + + + @@ -559,7 +559,7 @@

    DCM.V2P<

    - + @@ -621,25 +621,25 @@

    DCM.V2P<

    - + - + - + - + - + - + - + - + - + - + @@ -732,24 +732,24 @@

    DCM.V2P<

    DCM:CLK0[0, 3, 49]
    DCM:CLK180[0, 3, 51]
    DCM:CLK270[0, 3, 52]
    DCM:CLK2X[0, 3, 53]
    DCM:CLK2X180[0, 3, 54]
    DCM:CLK90[0, 3, 50]
    DCM:CLKDV[0, 3, 55]
    DCM:CLKFB[0, 0, 18]
    DCM:CLKFB_IOB[0, 3, 6]
    DCM:CLKFX[0, 3, 57]
    DCM:CLKFX180[0, 3, 56]
    DCM:CLKIN_DIVIDE_BY_2[0, 3, 0]
    DCM:CLKIN_IOB[0, 3, 5]
    DCM:CONCUR[0, 3, 58]
    DCM:DFS_ENABLE[0, 0, 16]
    DCM:DFS_FEEDBACK[0, 3, 43]
    DCM:DLL_ENABLE[0, 0, 17]
    DCM:DSS_ENABLE[0, 0, 20]
    DCM:ENABLE.CLK0[0, 3, 49]
    DCM:ENABLE.CLK180[0, 3, 51]
    DCM:ENABLE.CLK270[0, 3, 52]
    DCM:ENABLE.CLK2X[0, 3, 53]
    DCM:ENABLE.CLK2X180[0, 3, 54]
    DCM:ENABLE.CLK90[0, 3, 50]
    DCM:ENABLE.CLKDV[0, 3, 55]
    DCM:ENABLE.CLKFB[0, 0, 18]
    DCM:ENABLE.CLKFX[0, 3, 57]
    DCM:ENABLE.CLKFX180[0, 3, 56]
    DCM:ENABLE.CONCUR[0, 3, 58]
    DCM:EN_DUMMY_OSC_OR_NON_STOP[1, 7, 9]
    DCM:EN_OSC_COARSE[1, 6, 9]
    DCM:NON_STOP[0, 3, 15]
    17 DCM:DLLS[17]
    DCM:DLL_ENABLE    		--DCM:CLKFX_DIVIDE[1]
    DCM:DFS[1]
    18DCM:CLKFB
    DCM:DLLS[18]    		--DCM:CLKFX_DIVIDE[2]
    DCM:DFS[2]
    DCM:DLLS[18]
    DCM:ENABLE.CLKFB    		--DCM:CLKFX_DIVIDE[2]
    DCM:DFS[2]
    19 DCM:DLLS[19]
    DCM:PS_ENABLE    		--DCM:CLKFX_DIVIDE[3]
    DCM:DFS[3]
    20
    48 DCM:CLKDV_PHASE_RISE[0]
    DCM:DLLC[16]    		--DCM:MISC[0]
    49DCM:CLKDV_PHASE_RISE[1]
    DCM:DLLC[17]    		--DCM:CLK0
    DCM:MISC[1]
    DCM:CLKDV_PHASE_RISE[1]
    DCM:DLLC[17]    		--DCM:ENABLE.CLK0
    DCM:MISC[1]
    50DCM:CLKDV_PHASE_FALL[0]
    DCM:DLLC[18]    		--DCM:CLK90
    DCM:MISC[2]
    DCM:CLKDV_PHASE_FALL[0]
    DCM:DLLC[18]    		--DCM:ENABLE.CLK90
    DCM:MISC[2]
    51DCM:CLKDV_PHASE_FALL[1]
    DCM:DLLC[19]    		--DCM:CLK180
    DCM:MISC[3]
    DCM:CLKDV_PHASE_FALL[1]
    DCM:DLLC[19]    		--DCM:ENABLE.CLK180
    DCM:MISC[3]
    52DCM:CLKDV_MODE
    DCM:DLLC[20]    		--DCM:CLK270
    DCM:MISC[4]
    DCM:CLKDV_MODE
    DCM:DLLC[20]    		--DCM:ENABLE.CLK270
    DCM:MISC[4]
    53DCM:DLLC[21]
    DCM:TEST_OSC[0]    		--DCM:CLK2X
    DCM:MISC[5]
    DCM:DLLC[21]
    DCM:TEST_OSC[0]    		--DCM:ENABLE.CLK2X
    DCM:MISC[5]
    54DCM:DLLC[22]
    DCM:TEST_OSC[1]    		--DCM:CLK2X180
    DCM:MISC[6]
    DCM:DLLC[22]
    DCM:TEST_OSC[1]    		--DCM:ENABLE.CLK2X180
    DCM:MISC[6]
    55DCM:CLK_FEEDBACK
    DCM:DLLC[23]    		--DCM:CLKDV
    DCM:MISC[7]
    DCM:CLK_FEEDBACK
    DCM:DLLC[23]    		--DCM:ENABLE.CLKDV
    DCM:MISC[7]
    56DCM:DLLC[24]
    DCM:DLL_FREQUENCY_MODE    		--DCM:CLKFX180
    DCM:MISC[8]
    DCM:DLLC[24]
    DCM:DLL_FREQUENCY_MODE    		--DCM:ENABLE.CLKFX180
    DCM:MISC[8]
    57DCM:DLLC[25]
    DCM:PS_CENTERED    		--DCM:CLKFX
    DCM:MISC[9]
    DCM:DLLC[25]
    DCM:PS_CENTERED    		--DCM:ENABLE.CLKFX
    DCM:MISC[9]
    58DCM:DLLC[26]
    DCM:PS_MODE    		--DCM:CONCUR
    DCM:MISC[10]
    DCM:DLLC[26]
    DCM:PS_MODE    		--DCM:ENABLE.CONCUR
    DCM:MISC[10]
    59 DCM:DLLC[27]
    DCM:STATUS7    		--DCM:MISC[11]
    DCM:STARTUP_WAIT
    60
    DCM:MISC[0, 3, 79][0, 3, 78][0, 3, 77][0, 3, 76][0, 3, 75][0, 3, 74][0, 3, 73][0, 3, 72][0, 3, 71][0, 3, 70][0, 3, 69][0, 3, 68][0, 3, 67][0, 3, 66][0, 3, 65][0, 3, 64][0, 3, 63][0, 3, 62][0, 3, 61][0, 3, 60][0, 3, 59][0, 3, 58][0, 3, 57][0, 3, 56][0, 3, 55][0, 3, 54][0, 3, 53][0, 3, 52][0, 3, 51][0, 3, 50][0, 3, 49][0, 3, 48]
    Non-inverted[31][30][29][28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    -
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    @@ -765,24 +765,24 @@

    DCM.V2P<
    - - - - - - - - - - - + + + + + + + + + + + diff --git a/xilinx/virtex4/dcm.html b/xilinx/virtex4/dcm.html index a867fef7..8f8fe823 100644 --- a/xilinx/virtex4/dcm.html +++ b/xilinx/virtex4/dcm.html @@ -171,11 +171,11 @@

    BitstreamDCM:DRP51[7]

    - + - + - + @@ -447,7 +447,7 @@

    BitstreamDCM:CLKFB_FEEDBACK
    DCM:DRP58[4]

    - + @@ -678,19 +678,19 @@

    BitstreamDCM:MUX.BUSOUT16[0]

    - + - + - + - + - + - + - + @@ -909,22 +909,12 @@

    Bitstream -
    -
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    @@ -940,10 +930,10 @@

    Bitstream
    -
    +
    @@ -976,6 +966,16 @@

    Bitstream
    +
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    @@ -1012,22 +1012,12 @@

    Bitstream

    DCM:CLK0[0, 3, 49]
    DCM:CLK180[0, 3, 51]
    DCM:CLK270[0, 3, 52]
    DCM:CLK2X[0, 3, 53]
    DCM:CLK2X180[0, 3, 54]
    DCM:CLK90[0, 3, 50]
    DCM:CLKDV[0, 3, 55]
    DCM:CLKFB[0, 0, 18]
    DCM:CLKFB_IOB[0, 3, 6]
    DCM:CLKFX[0, 3, 57]
    DCM:CLKFX180[0, 3, 56]
    DCM:CLKIN_DIVIDE_BY_2[0, 3, 0]
    DCM:CLKIN_IOB[0, 3, 5]
    DCM:CONCUR[0, 3, 58]
    DCM:DFS_ENABLE[0, 0, 16]
    DCM:DFS_FEEDBACK[0, 3, 43]
    DCM:DLL_ENABLE[0, 0, 17]
    DCM:DSS_ENABLE[0, 0, 20]
    DCM:ENABLE.CLK0[0, 3, 49]
    DCM:ENABLE.CLK180[0, 3, 51]
    DCM:ENABLE.CLK270[0, 3, 52]
    DCM:ENABLE.CLK2X[0, 3, 53]
    DCM:ENABLE.CLK2X180[0, 3, 54]
    DCM:ENABLE.CLK90[0, 3, 50]
    DCM:ENABLE.CLKDV[0, 3, 55]
    DCM:ENABLE.CLKFB[0, 0, 18]
    DCM:ENABLE.CLKFX[0, 3, 57]
    DCM:ENABLE.CLKFX180[0, 3, 56]
    DCM:ENABLE.CONCUR[0, 3, 58]
    DCM:EN_DUMMY_OSC_OR_NON_STOP[1, 7, 9]
    DCM:EN_OSC_COARSE[1, 6, 9]
    DCM:NON_STOP[0, 3, 15]
    DCM:DRP41[7]DCM:ENABLE.HCLK6
    29-------------------DCM:CLKFX180_ENABLE
    DCM:DRP51[8]    		DCM:DRP41[8]DCM:ENABLE.HCLK7
    -------------------DCM:DRP51[8]
    DCM:ENABLE.CLKFX180    		DCM:DRP41[8]DCM:ENABLE.HCLK7
    30-------------------DCM:CLKFX_ENABLE
    DCM:DRP51[9]    		DCM:DRP41[9]DCM:ENABLE.GIOB0
    -------------------DCM:DRP51[9]
    DCM:ENABLE.CLKFX    		DCM:DRP41[9]DCM:ENABLE.GIOB0
    31-------------------DCM:CONCUR_ENABLE
    DCM:DRP51[10]    		DCM:DRP41[10]DCM:ENABLE.GIOB1
    -------------------DCM:DRP51[10]
    DCM:ENABLE.CONCUR    		DCM:DRP41[10]DCM:ENABLE.GIOB1
    32 -------------------DCM:DRP51[11]DCM:DRP41[11]DCM:ENABLE.GIOB2
    33DCM:DLL_SPARE[4]
    DCM:DRP48[4]    		DCM:MUX.BUSOUT14[1]
    6-------------------DCM:DLL_ENABLE
    DCM:DRP58[5]    		DCM:DLL_SPARE[5]
    DCM:DRP48[5]    		DCM:MUX.BUSOUT14[5]
    -------------------DCM:DLL_ZD2_EN
    DCM:DRP58[5]    		DCM:DLL_SPARE[5]
    DCM:DRP48[5]    		DCM:MUX.BUSOUT14[5]
    7 -------------------DCM:DLL_FREQUENCY_MODE[0]
    DCM:DRP58[6]    		DCM:DLL_SPARE[6]
    DCM:DRP48[6]    		DCM:MUX.BUSOUT14[6]
    8
    41-------------------DCM:DLL_SETTLE_TIME[0]
    DCM:DRP5E[0]    		DCM:CLK0_ENABLE
    DCM:DRP4E[0]    		DCM:MUX.BUSOUT17[0]
    -------------------DCM:DLL_SETTLE_TIME[0]
    DCM:DRP5E[0]    		DCM:DRP4E[0]
    DCM:ENABLE.CLK0    		DCM:MUX.BUSOUT17[0]
    42-------------------DCM:DLL_SETTLE_TIME[1]
    DCM:DRP5E[1]    		DCM:CLK90_ENABLE
    DCM:DRP4E[1]    		DCM:MUX.BUSOUT18[0]
    -------------------DCM:DLL_SETTLE_TIME[1]
    DCM:DRP5E[1]    		DCM:DRP4E[1]
    DCM:ENABLE.CLK90    		DCM:MUX.BUSOUT18[0]
    43-------------------DCM:DLL_SETTLE_TIME[2]
    DCM:DRP5E[2]    		DCM:CLK180_ENABLE
    DCM:DRP4E[2]    		DCM:MUX.BUSOUT19[0]
    -------------------DCM:DLL_SETTLE_TIME[2]
    DCM:DRP5E[2]    		DCM:DRP4E[2]
    DCM:ENABLE.CLK180    		DCM:MUX.BUSOUT19[0]
    44-------------------DCM:DLL_SETTLE_TIME[3]
    DCM:DRP5E[3]    		DCM:CLK270_ENABLE
    DCM:DRP4E[3]    		DCM:MUX.BUSOUT20[0]
    -------------------DCM:DLL_SETTLE_TIME[3]
    DCM:DRP5E[3]    		DCM:DRP4E[3]
    DCM:ENABLE.CLK270    		DCM:MUX.BUSOUT20[0]
    45-------------------DCM:DLL_SETTLE_TIME[4]
    DCM:DRP5E[4]    		DCM:CLK2X_ENABLE
    DCM:DRP4E[4]    		DCM:MUX.BUSOUT21[0]
    -------------------DCM:DLL_SETTLE_TIME[4]
    DCM:DRP5E[4]    		DCM:DRP4E[4]
    DCM:ENABLE.CLK2X    		DCM:MUX.BUSOUT21[0]
    46-------------------DCM:DLL_SETTLE_TIME[5]
    DCM:DRP5E[5]    		DCM:CLK2X180_ENABLE
    DCM:DRP4E[5]    		DCM:MUX.BUSOUT22[0]
    -------------------DCM:DLL_SETTLE_TIME[5]
    DCM:DRP5E[5]    		DCM:DRP4E[5]
    DCM:ENABLE.CLK2X180    		DCM:MUX.BUSOUT22[0]
    47-------------------DCM:DLL_SETTLE_TIME[6]
    DCM:DRP5E[6]    		DCM:CLKDV_ENABLE
    DCM:DRP4E[6]    		DCM:MUX.BUSOUT23[0]
    -------------------DCM:DLL_SETTLE_TIME[6]
    DCM:DRP5E[6]    		DCM:DRP4E[6]
    DCM:ENABLE.CLKDV    		DCM:MUX.BUSOUT23[0]
    48 -------------------DCM:DLL_SETTLE_TIME[7]
    DCM:DRP5E[7]    		DCM:DRP4E[7]-
    49
    - - - - - - - - - - @@ -1043,10 +1033,10 @@

    BitstreamInput/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/center.html b/xilinx/virtex5/center.html index 92cabe6c..e225412b 100644 --- a/xilinx/virtex5/center.html +++ b/xilinx/virtex5/center.html @@ -67,6 +67,7 @@
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/clb.html b/xilinx/virtex5/clb.html index 85c6cab9..413d4744 100644 --- a/xilinx/virtex5/clb.html +++ b/xilinx/virtex5/clb.html @@ -68,6 +68,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/clock.html b/xilinx/virtex5/clock.html index 2a668b2e..1ef505e9 100644 --- a/xilinx/virtex5/clock.html +++ b/xilinx/virtex5/clock.html @@ -19,7 +19,7 @@ - + @@ -74,6 +74,7 @@
  • I/O standard data
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • @@ -6062,7 +6063,7 @@

    HCLK_CMT

    - +
    DCM:CLK0_ENABLE[3, 20, 41]
    DCM:CLK180_ENABLE[3, 20, 43]
    DCM:CLK270_ENABLE[3, 20, 44]
    DCM:CLK2X180_ENABLE[3, 20, 46]
    DCM:CLK2X_ENABLE[3, 20, 45]
    DCM:CLK90_ENABLE[3, 20, 42]
    DCM:CLKDV_ENABLE[3, 20, 47]
    DCM:CLKFB_ENABLE[0, 19, 73]
    DCM:CLKFB_FEEDBACK[2, 19, 5]
    DCM:CLKFB_IOB[0, 20, 46]
    DCM:CLKFX180_ENABLE[0, 19, 29]
    DCM:CLKFX_ENABLE[0, 19, 30]
    DCM:CLKIN_DIVIDE_BY_2[0, 19, 24]
    DCM:CLKIN_ENABLE[0, 19, 25]
    DCM:CLKIN_IOB[0, 20, 47]
    DCM:CONCUR_ENABLE[0, 19, 31]
    DCM:DCM_CLKDV_CLKFX_ALIGNMENT[0, 19, 66]
    DCM:DCM_EXT_FB_EN[0, 20, 27]
    DCM:DCM_UNUSED_TAPS_POWERDOWN[1, 19, 55]
    14 ----------------------------------------HCLK_CMT:BUF.HCLK8HCLK_CMT:BUF.HCLK4HCLK_CMT:BUF.HCLK0HCLK_CMT:BUF.GIOB6HCLK_CMT:BUF.GIOB2
    15----------------------------------------HCLK_CMT:BUF.HCLK9HCLK_CMT:BUF.HCLK5HCLK_CMT:BUF.HCLK1HCLK_CMT:BUF.GIOB7HCLK_CMT:BUF.GIOB3
    ---------------------------HCLK_CMT:DRP_MASK------------HCLK_CMT:BUF.HCLK9HCLK_CMT:BUF.HCLK5HCLK_CMT:BUF.HCLK1HCLK_CMT:BUF.GIOB7HCLK_CMT:BUF.GIOB3
    @@ -6084,6 +6085,7 @@

    HCLK_CMT
    +
    @@ -6105,6 +6107,7 @@

    HCLK_CMT

    +
    HCLK_CMT:BUF.GIOB0[0, 44, 12]
    HCLK_CMT:BUF.GIOB1[0, 44, 13]
    HCLK_CMT:BUF.HCLK7[0, 40, 13]
    HCLK_CMT:BUF.HCLK8[0, 40, 14]
    HCLK_CMT:BUF.HCLK9[0, 40, 15]
    HCLK_CMT:DRP_MASK[0, 27, 15]
    Non-inverted[0]
    @@ -6164,7 +6167,7 @@

    I/O standard data - +
    diff --git a/xilinx/virtex5/cmt.html b/xilinx/virtex5/cmt.html new file mode 100644 index 00000000..a034d168 --- /dev/null +++ b/xilinx/virtex5/cmt.html @@ -0,0 +1,2789 @@ + + + + + + + Clock management tile — Project Combine documentation + + + + + + + + + + + + + + + + + +
    + + +
    + +
    +
    +
    + +
    +
    +
    +
    + +
    +

    Clock management tile

    +
    +

    Todo

    +

    describe this madness

    +
    +
    +

    CMT

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 0
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM0:DRP40[1]DCM0:DRP40[0]
    1----------------------------DCM0:DRP40[2]DCM0:DRP40[3]
    2----------------------------DCM0:DRP40[5]DCM0:DRP40[4]
    3----------------------------DCM0:DRP40[6]DCM0:DRP40[7]
    4----------------------------DCM0:DRP40[9]DCM0:DRP40[8]
    5----------------------------DCM0:DRP40[10]DCM0:DRP40[11]
    6----------------------------DCM0:DRP40[13]DCM0:DRP40[12]
    7----------------------------DCM0:DRP40[14]DCM0:DRP40[15]
    8----------------------------DCM0:DFS_OSCILLATOR_MODE
    DCM0:DRP41[1]    		DCM0:DRP41[0]
    9----------------------------DCM0:DFS_FREQUENCY_MODE
    DCM0:DRP41[2]    		DCM0:DFS_CFG_BYPASS
    DCM0:DRP41[3]
    10----------------------------DCM0:DFS_SYNTH_FAST_SYNCH[1]
    DCM0:DRP41[5]    		DCM0:DFS_SYNTH_FAST_SYNCH[0]
    DCM0:DRP41[4]
    11----------------------------DCM0:DFS_AVE_FREQ_GAIN[0]
    DCM0:DRP41[6]    		DCM0:DFS_AVE_FREQ_GAIN[1]
    DCM0:DRP41[7]
    12----------------------------DCM0:DFS_EARLY_LOCK
    DCM0:DRP41[9]    		DCM0:DFS_AVE_FREQ_GAIN[2]
    DCM0:DRP41[8]
    13----------------------------DCM0:DRP41[10]DCM0:DRP41[11]
    14----------------------------DCM0:DRP41[13]DCM0:DRP41[12]
    15----------------------------DCM0:DFS_HARDSYNC_B[0]
    DCM0:DRP41[14]    		DCM0:DFS_HARDSYNC_B[1]
    DCM0:DRP41[15]
    16----------------------------DCM0:DRP42[1]DCM0:DRP42[0]
    17----------------------------DCM0:DRP42[2]DCM0:DFS_JF_LOWER_LIMIT[0]
    DCM0:DRP42[3]
    18----------------------------DCM0:DFS_JF_LOWER_LIMIT[2]
    DCM0:DRP42[5]    		DCM0:DFS_JF_LOWER_LIMIT[1]
    DCM0:DRP42[4]
    19----------------------------DCM0:DFS_JF_LOWER_LIMIT[3]
    DCM0:DRP42[6]    		DCM0:DFS_OSC_ON_FX
    DCM0:DRP42[7]
    20----------------------------DCM0:DFS_HF_TRIM_CAL[0]
    DCM0:DRP42[9]    		DCM0:DFS_REF_ON_FX
    DCM0:DRP42[8]
    21----------------------------DCM0:DFS_HF_TRIM_CAL[1]
    DCM0:DRP42[10]    		DCM0:DFS_HF_TRIM_CAL[2]
    DCM0:DRP42[11]
    22----------------------------~DCM0:DFS_PWRD_REPLY_TIMES_OUT_B
    DCM0:DRP42[13]    		DCM0:DRP42[12]
    23----------------------------~DCM0:DFS_PWRD_CLKIN_STOP_STICKY_B
    DCM0:DRP42[14]    		~DCM0:DFS_PWRD_CLKIN_STOP_B
    DCM0:DRP42[15]
    24----------------------------DCM0:DCM_CLKIN_IODLY_MUXOUT_SEL
    DCM0:DRP43[1]    		DCM0:DCM_CLKFB_IODLY_MUXOUT_SEL
    DCM0:DRP43[0]
    25----------------------------DCM0:DRP43[2]DCM0:DESKEW_ADJUST[0]
    DCM0:DRP43[3]
    26----------------------------DCM0:DESKEW_ADJUST[2]
    DCM0:DRP43[5]    		DCM0:DESKEW_ADJUST[1]
    DCM0:DRP43[4]
    27----------------------------DCM0:DESKEW_ADJUST[3]
    DCM0:DRP43[6]    		DCM0:DESKEW_ADJUST[4]
    DCM0:DRP43[7]
    28----------------------------DCM0:DCM_PLL_RST_DCM
    DCM0:DRP43[9]    		DCM0:DRP43[8]
    29----------------------------DCM0:DCM_COM_PWC_REF_TAP[0]
    DCM0:DRP43[10]    		DCM0:DCM_COM_PWC_REF_TAP[1]
    DCM0:DRP43[11]
    30----------------------------DCM0:DCM_COM_PWC_FB_TAP[0]
    DCM0:DRP43[13]    		DCM0:DCM_COM_PWC_REF_TAP[2]
    DCM0:DRP43[12]
    31----------------------------DCM0:DCM_COM_PWC_FB_TAP[1]
    DCM0:DRP43[14]    		DCM0:DCM_COM_PWC_FB_TAP[2]
    DCM0:DRP43[15]
    32----------------------------DCM0:DCM_COM_PWC_FB_EN
    DCM0:DRP44[1]    		DCM0:DCM_COM_PWC_REF_EN
    DCM0:DRP44[0]
    33----------------------------DCM0:DCM_EXT_FB_EN
    DCM0:DRP44[2]    		DCM0:DCM_USE_REG_READY
    DCM0:DRP44[3]
    34----------------------------DCM0:DLL_SYNTH_CLOCK_SPEED[1]
    DCM0:DRP44[5]    		DCM0:DLL_SYNTH_CLOCK_SPEED[0]
    DCM0:DRP44[4]
    35----------------------------DCM0:DFS_SYNTH_CLOCK_SPEED[0]
    DCM0:DRP44[6]    		DCM0:DFS_SYNTH_CLOCK_SPEED[1]
    DCM0:DRP44[7]
    36----------------------------DCM0:DCM_WAIT_PLL
    DCM0:DRP44[9]    		DCM0:DFS_SYNTH_CLOCK_SPEED[2]
    DCM0:DRP44[8]
    37----------------------------DCM0:CLKIN_DIVIDE_BY_2
    DCM0:DRP44[10]    		DCM0:DCM_CLKIN_IODLY_MUXINSEL
    DCM0:DRP44[11]
    38----------------------------DCM0:DFS_SYNC_TO_DLL
    DCM0:DRP44[13]    		DCM0:DCM_CLKFB_IODLY_MUXINSEL
    DCM0:DRP44[12]
    39----------------------------DCM0:DFS_EN
    DCM0:DRP44[14]    		DCM0:DFS_FAST_UPDATE
    DCM0:DRP44[15]
    40----------------------------DCM0:DFS_TAPTRIM[1]
    DCM0:DRP45[1]    		DCM0:DFS_TAPTRIM[0]
    DCM0:DRP45[0]
    41----------------------------DCM0:DFS_TAPTRIM[2]
    DCM0:DRP45[2]    		DCM0:DFS_TAPTRIM[3]
    DCM0:DRP45[3]
    42----------------------------DCM0:DFS_TAPTRIM[5]
    DCM0:DRP45[5]    		DCM0:DFS_TAPTRIM[4]
    DCM0:DRP45[4]
    43----------------------------DCM0:DFS_TAPTRIM[6]
    DCM0:DRP45[6]    		DCM0:DFS_TAPTRIM[7]
    DCM0:DRP45[7]
    44----------------------------DCM0:DFS_TAPTRIM[9]
    DCM0:DRP45[9]    		DCM0:DFS_TAPTRIM[8]
    DCM0:DRP45[8]
    45----------------------------DCM0:DFS_TAPTRIM[10]
    DCM0:DRP45[10]    		DCM0:DRP45[11]
    46----------------------------DCM0:DRP45[13]DCM0:DRP45[12]
    47----------------------------DCM0:DRP45[14]DCM0:DRP45[15]
    48----------------------------DCM0:DFS_TWEAK[1]
    DCM0:DRP46[1]    		DCM0:DFS_TWEAK[0]
    DCM0:DRP46[0]
    49----------------------------DCM0:DFS_TWEAK[2]
    DCM0:DRP46[2]    		DCM0:DFS_TWEAK[3]
    DCM0:DRP46[3]
    50----------------------------DCM0:DFS_TWEAK[5]
    DCM0:DRP46[5]    		DCM0:DFS_TWEAK[4]
    DCM0:DRP46[4]
    51----------------------------DCM0:DFS_TWEAK[6]
    DCM0:DRP46[6]    		DCM0:DFS_TWEAK[7]
    DCM0:DRP46[7]
    52----------------------------DCM0:DRP46[9]DCM0:DRP46[8]
    53----------------------------DCM0:DRP46[10]DCM0:DRP46[11]
    54----------------------------DCM0:DRP46[13]DCM0:DRP46[12]
    55----------------------------DCM0:DRP46[14]DCM0:DRP46[15]
    56----------------------------DCM0:DRP47[1]
    DCM0:ENABLE.CLKFX180    		DCM0:DRP47[0]
    DCM0:ENABLE.CLKFX
    57----------------------------DCM0:DRP47[2]
    DCM0:ENABLE.CONCUR    		DCM0:DFS_OUTPUT_PSDLY_ON_CONCUR
    DCM0:DRP47[3]
    58----------------------------DCM0:DCM_UNUSED_TAPS_POWERDOWN[0]
    DCM0:DRP47[5]    		~DCM0:DFS_EN_RELRST_B
    DCM0:DRP47[4]
    59----------------------------DCM0:DFS_MPW_LOW
    DCM0:DRP47[6]    		DCM0:DFS_MPW_HIGH
    DCM0:DRP47[7]
    60----------------------------DCM0:DFS_CUSTOM_FAST_SYNC[0]
    DCM0:DRP47[9]    		DCM0:DCM_CLKDV_CLKFX_ALIGNMENT
    DCM0:DRP47[8]
    61----------------------------DCM0:DFS_CUSTOM_FAST_SYNC[1]
    DCM0:DRP47[10]    		DCM0:DFS_CUSTOM_FAST_SYNC[2]
    DCM0:DRP47[11]
    62----------------------------DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[0]
    DCM0:DRP47[13]    		DCM0:DFS_CUSTOM_FAST_SYNC[3]
    DCM0:DRP47[12]
    63----------------------------DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[1]
    DCM0:DRP47[14]    		DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[2]
    DCM0:DRP47[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 1
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM0:DRP48[1]
    DCM0:MUX.CLKIN[1]    		DCM0:DRP48[0]
    DCM0:MUX.CLKIN[0]
    1----------------------------DCM0:DRP48[2]
    DCM0:MUX.CLKIN[2]    		DCM0:DRP48[3]
    DCM0:MUX.CLKIN[3]
    2----------------------------DCM0:DRP48[5]
    DCM0:MUX.CLKFB[0]    		DCM0:DRP48[4]
    DCM0:MUX.CLKIN[4]
    3----------------------------DCM0:DRP48[6]
    DCM0:MUX.CLKFB[1]    		DCM0:DRP48[7]
    DCM0:MUX.CLKFB[2]
    4----------------------------DCM0:DRP48[9]
    DCM0:MUX.CLKFB[4]    		DCM0:DRP48[8]
    DCM0:MUX.CLKFB[3]
    5----------------------------DCM0:DRP48[10]
    DCM0:MUX.CLK_TO_PLL[0]    		DCM0:DRP48[11]
    DCM0:MUX.CLK_TO_PLL[1]
    6----------------------------DCM0:DRP48[13]
    DCM0:MUX.CLK_TO_PLL[3]    		DCM0:DRP48[12]
    DCM0:MUX.CLK_TO_PLL[2]
    7----------------------------DCM0:DRP48[14]
    DCM0:INV.SKEWCLKIN1    		DCM0:DRP48[15]
    DCM0:INV.SKEWCLKIN2
    8----------------------------DCM0:DRP49[1]
    DCM0:MUX.SKEWCLKIN2[1]    		DCM0:DRP49[0]
    DCM0:MUX.SKEWCLKIN2[0]
    9----------------------------DCM0:DRP49[2]
    DCM0:MUX.SKEWCLKIN2[2]    		DCM0:DRP49[3]
    DCM0:MUX.SKEWCLKIN2[3]
    10----------------------------DCM0:DRP49[5]
    DCM0:INV.SKEWRST    		DCM0:DRP49[4]
    DCM0:INV.SKEWIN
    11----------------------------DCM0:CLKIN_CLKFB_ENABLE
    DCM0:DRP49[6]    		DCM0:DRP49[7]
    12----------------------------DCM0:DRP49[9]DCM0:DRP49[8]
    13----------------------------DCM0:DRP49[10]DCM0:DRP49[11]
    14----------------------------DCM0:DRP49[13]DCM0:DRP49[12]
    15----------------------------DCM0:DRP49[14]DCM0:DCM_REG_PWRD_CFG
    DCM0:DRP49[15]
    16----------------------------DCM0:DRP4A[1]DCM0:DRP4A[0]
    17----------------------------DCM0:DRP4A[2]DCM0:DRP4A[3]
    18----------------------------DCM0:DRP4A[5]DCM0:DRP4A[4]
    19----------------------------DCM0:DRP4A[6]DCM0:DRP4A[7]
    20----------------------------DCM0:DRP4A[9]DCM0:DRP4A[8]
    21----------------------------DCM0:DRP4A[10]DCM0:DRP4A[11]
    22----------------------------DCM0:DRP4A[13]DCM0:DRP4A[12]
    23----------------------------DCM0:DRP4A[14]DCM0:DRP4A[15]
    24----------------------------DCM0:DLL_PHASE_SHIFT_CALIBRATION[1]
    DCM0:DRP4B[1]    		DCM0:DLL_PHASE_SHIFT_CALIBRATION[0]
    DCM0:DRP4B[0]
    25----------------------------DCM0:DRP4B[2]
    DCM0:PS_CENTERED    		DCM0:DRP4B[3]
    DCM0:PS_DIRECT
    26----------------------------DCM0:DRP4B[5]
    DCM0:INV.RST    		DCM0:DLL_PHASE_SHIFT_LOCK_BY1
    DCM0:DRP4B[4]
    27----------------------------DCM0:DRP4B[6]
    DCM0:INV.PSINCDEC    		DCM0:DRP4B[7]
    DCM0:INV.PSEN
    28----------------------------DCM0:DRP4B[9]DCM0:DRP4B[8]
    29----------------------------DCM0:DRP4B[10]DCM0:DRP4B[11]
    30----------------------------DCM0:DRP4B[13]DCM0:DRP4B[12]
    31----------------------------DCM0:DRP4B[14]DCM0:DRP4B[15]
    32----------------------------DCM0:DCM_SCANMODE
    DCM0:DRP4C[1]    		DCM0:DCM_UNUSED_TAPS_POWERDOWN[2]
    DCM0:DRP4C[0]
    33----------------------------DCM0:DLL_TAPINIT_CTL[0]
    DCM0:DRP4C[2]    		DCM0:DLL_TAPINIT_CTL[1]
    DCM0:DRP4C[3]
    34----------------------------DCM0:DRP4C[5]DCM0:DLL_TAPINIT_CTL[2]
    DCM0:DRP4C[4]
    35----------------------------~DCM0:DLL_PWRD_ON_SCANMODE_B
    DCM0:DRP4C[6]    		DCM0:DLL_ZD1_PHASE_SEL_INIT[0]
    DCM0:DRP4C[7]
    36----------------------------DCM0:DLL_PERIOD_LOCK_BY1
    DCM0:DRP4C[9]    		DCM0:DLL_ZD1_PHASE_SEL_INIT[1]
    DCM0:DRP4C[8]
    37----------------------------DCM0:DLL_DESKEW_LOCK_BY1
    DCM0:DRP4C[10]    		DCM0:DLL_ZD2_JF_OVERFLOW_HOLD
    DCM0:DRP4C[11]
    38----------------------------DCM0:DLL_ZD1_JF_OVERFLOW_HOLD
    DCM0:DRP4C[13]    		DCM0:DCM_UNUSED_TAPS_POWERDOWN[3]
    DCM0:DRP4C[12]
    39----------------------------DCM0:DCM_UNUSED_TAPS_POWERDOWN[1]
    DCM0:DRP4C[14]    		DCM0:DRP4C[15]
    40----------------------------DCM0:DLL_ZD2_TAP_INIT[1]
    DCM0:DRP4D[1]    		DCM0:DLL_ZD2_TAP_INIT[0]
    DCM0:DRP4D[0]
    41----------------------------DCM0:DLL_ZD2_TAP_INIT[2]
    DCM0:DRP4D[2]    		DCM0:DLL_ZD2_TAP_INIT[3]
    DCM0:DRP4D[3]
    42----------------------------DCM0:DLL_ZD2_TAP_INIT[5]
    DCM0:DRP4D[5]    		DCM0:DLL_ZD2_TAP_INIT[4]
    DCM0:DRP4D[4]
    43----------------------------DCM0:DLL_ZD2_TAP_INIT[6]
    DCM0:DRP4D[6]    		DCM0:DRP4D[7]
    44----------------------------DCM0:DLL_ZD1_TAP_INIT[1]
    DCM0:DRP4D[9]    		DCM0:DLL_ZD1_TAP_INIT[0]
    DCM0:DRP4D[8]
    45----------------------------DCM0:DLL_ZD1_TAP_INIT[2]
    DCM0:DRP4D[10]    		DCM0:DLL_ZD1_TAP_INIT[3]
    DCM0:DRP4D[11]
    46----------------------------DCM0:DLL_ZD1_TAP_INIT[5]
    DCM0:DRP4D[13]    		DCM0:DLL_ZD1_TAP_INIT[4]
    DCM0:DRP4D[12]
    47----------------------------DCM0:DLL_ZD1_TAP_INIT[6]
    DCM0:DRP4D[14]    		DCM0:DLL_ZD1_TAP_INIT[7]
    DCM0:DRP4D[15]
    48----------------------------DCM0:DLL_DESKEW_MINTAP[1]
    DCM0:DRP4E[1]    		DCM0:DLL_DESKEW_MINTAP[0]
    DCM0:DRP4E[0]
    49----------------------------DCM0:DLL_DESKEW_MINTAP[2]
    DCM0:DRP4E[2]    		DCM0:DLL_DESKEW_MINTAP[3]
    DCM0:DRP4E[3]
    50----------------------------DCM0:DLL_DESKEW_MINTAP[5]
    DCM0:DRP4E[5]    		DCM0:DLL_DESKEW_MINTAP[4]
    DCM0:DRP4E[4]
    51----------------------------DCM0:DLL_DESKEW_MINTAP[6]
    DCM0:DRP4E[6]    		DCM0:DLL_DESKEW_MINTAP[7]
    DCM0:DRP4E[7]
    52----------------------------DCM0:DLL_DESKEW_MAXTAP[1]
    DCM0:DRP4E[9]    		DCM0:DLL_DESKEW_MAXTAP[0]
    DCM0:DRP4E[8]
    53----------------------------DCM0:DLL_DESKEW_MAXTAP[2]
    DCM0:DRP4E[10]    		DCM0:DLL_DESKEW_MAXTAP[3]
    DCM0:DRP4E[11]
    54----------------------------DCM0:DLL_DESKEW_MAXTAP[5]
    DCM0:DRP4E[13]    		DCM0:DLL_DESKEW_MAXTAP[4]
    DCM0:DRP4E[12]
    55----------------------------DCM0:DLL_DESKEW_MAXTAP[6]
    DCM0:DRP4E[14]    		DCM0:DLL_DESKEW_MAXTAP[7]
    DCM0:DRP4E[15]
    56----------------------------DCM0:DRP4F[1]
    DCM0:FACTORY_JF[1]    		DCM0:DRP4F[0]
    DCM0:FACTORY_JF[0]
    57----------------------------DCM0:DRP4F[2]
    DCM0:FACTORY_JF[2]    		DCM0:DRP4F[3]
    DCM0:FACTORY_JF[3]
    58----------------------------DCM0:DRP4F[5]
    DCM0:FACTORY_JF[5]    		DCM0:DRP4F[4]
    DCM0:FACTORY_JF[4]
    59----------------------------DCM0:DRP4F[6]
    DCM0:FACTORY_JF[6]    		DCM0:DRP4F[7]
    DCM0:FACTORY_JF[7]
    60----------------------------DCM0:DRP4F[9]
    DCM0:FACTORY_JF[9]    		DCM0:DRP4F[8]
    DCM0:FACTORY_JF[8]
    61----------------------------DCM0:DRP4F[10]
    DCM0:FACTORY_JF[10]    		DCM0:DRP4F[11]
    DCM0:FACTORY_JF[11]
    62----------------------------DCM0:DRP4F[13]
    DCM0:FACTORY_JF[13]    		DCM0:DRP4F[12]
    DCM0:FACTORY_JF[12]
    63----------------------------DCM0:DRP4F[14]
    DCM0:FACTORY_JF[14]    		DCM0:DRP4F[15]
    DCM0:FACTORY_JF[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 2
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM0:CLKFX_DIVIDE[1]
    DCM0:DRP50[1]    		DCM0:CLKFX_DIVIDE[0]
    DCM0:DRP50[0]
    1----------------------------DCM0:CLKFX_DIVIDE[2]
    DCM0:DRP50[2]    		DCM0:CLKFX_DIVIDE[3]
    DCM0:DRP50[3]
    2----------------------------DCM0:CLKFX_DIVIDE[5]
    DCM0:DRP50[5]    		DCM0:CLKFX_DIVIDE[4]
    DCM0:DRP50[4]
    3----------------------------DCM0:CLKFX_DIVIDE[6]
    DCM0:DRP50[6]    		DCM0:CLKFX_DIVIDE[7]
    DCM0:DRP50[7]
    4----------------------------DCM0:CLKFX_MULTIPLY[1]
    DCM0:DRP50[9]    		DCM0:CLKFX_MULTIPLY[0]
    DCM0:DRP50[8]
    5----------------------------DCM0:CLKFX_MULTIPLY[2]
    DCM0:DRP50[10]    		DCM0:CLKFX_MULTIPLY[3]
    DCM0:DRP50[11]
    6----------------------------DCM0:CLKFX_MULTIPLY[5]
    DCM0:DRP50[13]    		DCM0:CLKFX_MULTIPLY[4]
    DCM0:DRP50[12]
    7----------------------------DCM0:CLKFX_MULTIPLY[6]
    DCM0:DRP50[14]    		DCM0:CLKFX_MULTIPLY[7]
    DCM0:DRP50[15]
    8----------------------------~DCM0:DLL_CLKIN_STOPPED_PWRD_EN_B
    DCM0:DRP51[1]    		~DCM0:DLL_CLKFB_STOPPED_PWRD_EN_B
    DCM0:DRP51[0]
    9----------------------------DCM0:DLL_FREQUENCY_MODE[0]
    DCM0:DRP51[2]    		DCM0:DLL_FREQUENCY_MODE[1]
    DCM0:DRP51[3]
    10----------------------------DCM0:DLL_ZD2_EN
    DCM0:DRP51[5]    		DCM0:DRP51[4]
    DCM0:PS_MODE
    11----------------------------DCM0:DLL_ZD1_EN
    DCM0:DRP51[6]    		DCM0:DRP51[7]
    DCM0:PS_ENABLE
    12----------------------------DCM0:DLL_SETTLE_TIME[1]
    DCM0:DRP51[9]    		DCM0:DLL_SETTLE_TIME[0]
    DCM0:DRP51[8]
    13----------------------------DCM0:DLL_SETTLE_TIME[2]
    DCM0:DRP51[10]    		DCM0:DLL_SETTLE_TIME[3]
    DCM0:DRP51[11]
    14----------------------------DCM0:DLL_SETTLE_TIME[5]
    DCM0:DRP51[13]    		DCM0:DLL_SETTLE_TIME[4]
    DCM0:DRP51[12]
    15----------------------------DCM0:DLL_SETTLE_TIME[6]
    DCM0:DRP51[14]    		DCM0:DLL_SETTLE_TIME[7]
    DCM0:DRP51[15]
    16----------------------------DCM0:DLL_LIVE_TIME[1]
    DCM0:DRP52[1]    		DCM0:DLL_LIVE_TIME[0]
    DCM0:DRP52[0]
    17----------------------------DCM0:DLL_LIVE_TIME[2]
    DCM0:DRP52[2]    		DCM0:DLL_LIVE_TIME[3]
    DCM0:DRP52[3]
    18----------------------------DCM0:DLL_LIVE_TIME[5]
    DCM0:DRP52[5]    		DCM0:DLL_LIVE_TIME[4]
    DCM0:DRP52[4]
    19----------------------------DCM0:DLL_LIVE_TIME[6]
    DCM0:DRP52[6]    		DCM0:DLL_LIVE_TIME[7]
    DCM0:DRP52[7]
    20----------------------------DCM0:DLL_DEAD_TIME[1]
    DCM0:DRP52[9]    		DCM0:DLL_DEAD_TIME[0]
    DCM0:DRP52[8]
    21----------------------------DCM0:DLL_DEAD_TIME[2]
    DCM0:DRP52[10]    		DCM0:DLL_DEAD_TIME[3]
    DCM0:DRP52[11]
    22----------------------------DCM0:DLL_DEAD_TIME[5]
    DCM0:DRP52[13]    		DCM0:DLL_DEAD_TIME[4]
    DCM0:DRP52[12]
    23----------------------------DCM0:DLL_DEAD_TIME[6]
    DCM0:DRP52[14]    		DCM0:DLL_DEAD_TIME[7]
    DCM0:DRP52[15]
    24----------------------------DCM0:CLKDV_COUNT_MAX[1]
    DCM0:DRP53[1]    		DCM0:CLKDV_COUNT_MAX[0]
    DCM0:DRP53[0]
    25----------------------------DCM0:CLKDV_COUNT_MAX[2]
    DCM0:DRP53[2]    		DCM0:CLKDV_COUNT_MAX[3]
    DCM0:DRP53[3]
    26----------------------------DCM0:CLKDV_COUNT_FALL[1]
    DCM0:DRP53[5]    		DCM0:CLKDV_COUNT_FALL[0]
    DCM0:DRP53[4]
    27----------------------------DCM0:CLKDV_COUNT_FALL[2]
    DCM0:DRP53[6]    		DCM0:CLKDV_COUNT_FALL[3]
    DCM0:DRP53[7]
    28----------------------------DCM0:CLKDV_COUNT_FALL_2[1]
    DCM0:DRP53[9]    		DCM0:CLKDV_COUNT_FALL_2[0]
    DCM0:DRP53[8]
    29----------------------------DCM0:CLKDV_COUNT_FALL_2[2]
    DCM0:DRP53[10]    		DCM0:CLKDV_COUNT_FALL_2[3]
    DCM0:DRP53[11]
    30----------------------------DCM0:CLKDV_PHASE_RISE[1]
    DCM0:DRP53[13]    		DCM0:CLKDV_PHASE_RISE[0]
    DCM0:DRP53[12]
    31----------------------------DCM0:CLKDV_PHASE_FALL[0]
    DCM0:DRP53[14]    		DCM0:CLKDV_PHASE_FALL[1]
    DCM0:DRP53[15]
    32----------------------------DCM0:DLL_FDBKLOST_EN
    DCM0:DRP54[1]    		DCM0:CLKDV_MODE
    DCM0:DRP54[0]
    33----------------------------DCM0:DCM_CLKLOST_EN
    DCM0:DRP54[2]    		~DCM0:DCM_LOCK_HIGH_B
    DCM0:DRP54[3]
    34----------------------------DCM0:DRP54[5]
    DCM0:ENABLE.CLK90    		DCM0:DRP54[4]
    DCM0:ENABLE.CLK0
    35----------------------------DCM0:DRP54[6]
    DCM0:ENABLE.CLK180    		DCM0:DRP54[7]
    DCM0:ENABLE.CLK270
    36----------------------------DCM0:DRP54[9]
    DCM0:ENABLE.CLK2X180    		DCM0:DRP54[8]
    DCM0:ENABLE.CLK2X
    37----------------------------DCM0:DRP54[10]
    DCM0:ENABLE.CLKDV    		DCM0:DCM_TRIM_CAL[0]
    DCM0:DRP54[11]
    38----------------------------DCM0:DCM_TRIM_CAL[2]
    DCM0:DRP54[13]    		DCM0:DCM_TRIM_CAL[1]
    DCM0:DRP54[12]
    39----------------------------DCM0:DLL_TEST_MUX_SEL[0]
    DCM0:DRP54[14]    		DCM0:DLL_TEST_MUX_SEL[1]
    DCM0:DRP54[15]
    40----------------------------DCM0:DRP55[1]
    DCM0:PHASE_SHIFT[1]    		DCM0:DRP55[0]
    DCM0:PHASE_SHIFT[0]
    41----------------------------DCM0:DRP55[2]
    DCM0:PHASE_SHIFT[2]    		DCM0:DRP55[3]
    DCM0:PHASE_SHIFT[3]
    42----------------------------DCM0:DRP55[5]
    DCM0:PHASE_SHIFT[5]    		DCM0:DRP55[4]
    DCM0:PHASE_SHIFT[4]
    43----------------------------DCM0:DRP55[6]
    DCM0:PHASE_SHIFT[6]    		DCM0:DRP55[7]
    DCM0:PHASE_SHIFT[7]
    44----------------------------DCM0:DRP55[9]
    DCM0:PHASE_SHIFT[9]    		DCM0:DRP55[8]
    DCM0:PHASE_SHIFT[8]
    45----------------------------DCM0:DRP55[10]
    DCM0:PHASE_SHIFT_NEGATIVE    		DCM0:DRP55[11]
    46----------------------------DCM0:DRP55[13]DCM0:DRP55[12]
    47----------------------------DCM0:DRP55[14]DCM0:DRP55[15]
    48----------------------------DCM0:DLL_PHASE_SHIFT_LFC[1]
    DCM0:DRP56[1]    		DCM0:DLL_PHASE_SHIFT_LFC[0]
    DCM0:DRP56[0]
    49----------------------------DCM0:DLL_PHASE_SHIFT_LFC[2]
    DCM0:DRP56[2]    		DCM0:DLL_PHASE_SHIFT_LFC[3]
    DCM0:DRP56[3]
    50----------------------------DCM0:DLL_PHASE_SHIFT_LFC[5]
    DCM0:DRP56[5]    		DCM0:DLL_PHASE_SHIFT_LFC[4]
    DCM0:DRP56[4]
    51----------------------------DCM0:DLL_PHASE_SHIFT_LFC[6]
    DCM0:DRP56[6]    		DCM0:DLL_PHASE_SHIFT_LFC[7]
    DCM0:DRP56[7]
    52----------------------------DCM0:DLL_ZD2_PWC_TAP[0]
    DCM0:DRP56[9]    		DCM0:DLL_PHASE_SHIFT_LFC[8]
    DCM0:DRP56[8]
    53----------------------------DCM0:DLL_ZD2_PWC_TAP[1]
    DCM0:DRP56[10]    		DCM0:DLL_ZD2_PWC_TAP[2]
    DCM0:DRP56[11]
    54----------------------------DCM0:DLL_ZD1_PWC_TAP[1]
    DCM0:DRP56[13]    		DCM0:DLL_ZD1_PWC_TAP[0]
    DCM0:DRP56[12]
    55----------------------------DCM0:DLL_ZD1_PWC_TAP[2]
    DCM0:DRP56[14]    		DCM0:DCM_VREG_ENABLE
    DCM0:DRP56[15]
    56----------------------------DCM0:DLL_ZD1_PWC_EN
    DCM0:DRP57[1]    		DCM0:DCM_VSPLY_VALID_ACC[0]
    DCM0:DRP57[0]
    57----------------------------DCM0:DRP57[2]
    DCM0:STARTUP_WAIT    		DCM0:DCM_VBG_SEL[0]
    DCM0:DRP57[3]
    58----------------------------DCM0:DLL_ETPP_HOLD
    DCM0:DRP57[5]    		DCM0:DCM_VBG_SEL[1]
    DCM0:DRP57[4]
    59----------------------------~DCM0:DLL_PWRD_STICKY_B
    DCM0:DRP57[6]    		DCM0:DCM_VBG_SEL[2]
    DCM0:DRP57[7]
    60----------------------------DCM0:DLL_ZD2_PWC_EN
    DCM0:DRP57[9]    		DCM0:DCM_VBG_SEL[3]
    DCM0:DRP57[8]
    61----------------------------~DCM0:DCM_POWERDOWN_COMMON_EN_B
    DCM0:DRP57[10]    		DCM0:DCM_VBG_PD[0]
    DCM0:DRP57[11]
    62----------------------------DCM0:DCM_COMMON_MSB_SEL[0]
    DCM0:DRP57[13]    		DCM0:DCM_VBG_PD[1]
    DCM0:DRP57[12]
    63----------------------------DCM0:DCM_COMMON_MSB_SEL[1]
    DCM0:DRP57[14]    		DCM0:DCM_VSPLY_VALID_ACC[1]
    DCM0:DRP57[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 3
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP00[1]
    PLL:PLL_LF_PEN[0]    		PLL:DRP00[0]
    PLL:PLL_MAN_LF_EN
    1----------------------------PLL:DRP00[2]
    PLL:PLL_LF_PEN[1]    		PLL:DRP00[3]
    PLL:PLL_LF_NEN[0]
    2----------------------------PLL:DRP00[5]
    PLL:PLL_VLFHIGH_DIS    		PLL:DRP00[4]
    PLL:PLL_LF_NEN[1]
    3----------------------------PLL:DRP00[6]
    PLL:PLL_RES[0]    		PLL:DRP00[7]
    PLL:PLL_RES[1]
    4----------------------------PLL:DRP00[9]
    PLL:PLL_RES[3]    		PLL:DRP00[8]
    PLL:PLL_RES[2]
    5----------------------------PLL:DRP00[10]
    PLL:PLL_MISC[0]    		PLL:DRP00[11]
    PLL:PLL_MISC[1]
    6----------------------------PLL:DRP00[13]
    PLL:PLL_MISC[3]    		PLL:DRP00[12]
    PLL:PLL_MISC[2]
    7----------------------------PLL:DRP00[14]
    PLL:PLL_CP_BIAS_TRIP_SHIFT    		PLL:DRP00[15]
    PLL:PLL_SEL_SLIPD
    8----------------------------PLL:DRP01[1]
    PLL:PLL_CP[1]    		PLL:DRP01[0]
    PLL:PLL_CP[0]
    9----------------------------PLL:DRP01[2]
    PLL:PLL_CP[2]    		PLL:DRP01[3]
    PLL:PLL_CP[3]
    10----------------------------PLL:DRP01[5]
    PLL:PLL_CP_RES[1]    		PLL:DRP01[4]
    PLL:PLL_CP_RES[0]
    11----------------------------PLL:DRP01[6]
    PLL:PLL_LFHF[0]    		PLL:DRP01[7]
    PLL:PLL_LFHF[1]
    12----------------------------PLL:DRP01[9]
    PLL:PLL_PFD_DLY[1]    		PLL:DRP01[8]
    PLL:PLL_PFD_DLY[0]
    13----------------------------PLL:DRP01[10]
    PLL:PLL_PFD_CNTRL[0]    		PLL:DRP01[11]
    PLL:PLL_PFD_CNTRL[1]
    14----------------------------PLL:DRP01[13]
    PLL:PLL_PFD_CNTRL[3]    		PLL:DRP01[12]
    PLL:PLL_PFD_CNTRL[2]
    15----------------------------PLL:DRP01[14]PLL:DRP01[15]
    PLL:PLL_PWRD_CFG
    16----------------------------PLL:DRP02[1]
    PLL:PLL_LOCK_CNT[1]    		PLL:DRP02[0]
    PLL:PLL_LOCK_CNT[0]
    17----------------------------PLL:DRP02[2]
    PLL:PLL_LOCK_CNT[2]    		PLL:DRP02[3]
    PLL:PLL_LOCK_CNT[3]
    18----------------------------PLL:DRP02[5]
    PLL:PLL_LOCK_CNT[5]    		PLL:DRP02[4]
    PLL:PLL_LOCK_CNT[4]
    19----------------------------PLL:DRP02[6]
    PLL:PLL_LOCK_REF_P1[0]    		PLL:DRP02[7]
    PLL:PLL_LOCK_REF_P1[1]
    20----------------------------PLL:DRP02[9]
    PLL:PLL_LOCK_REF_P1[3]    		PLL:DRP02[8]
    PLL:PLL_LOCK_REF_P1[2]
    21----------------------------PLL:DRP02[10]
    PLL:PLL_LOCK_REF_P1[4]    		PLL:DRP02[11]
    PLL:PLL_LOCK_REF_P2[0]
    22----------------------------PLL:DRP02[13]
    PLL:PLL_LOCK_REF_P2[2]    		PLL:DRP02[12]
    PLL:PLL_LOCK_REF_P2[1]
    23----------------------------PLL:DRP02[14]
    PLL:PLL_LOCK_REF_P2[3]    		PLL:DRP02[15]
    PLL:PLL_LOCK_REF_P2[4]
    24----------------------------PLL:DRP03[1]
    PLL:PLL_LOCK_FB_P1[1]    		PLL:DRP03[0]
    PLL:PLL_LOCK_FB_P1[0]
    25----------------------------PLL:DRP03[2]
    PLL:PLL_LOCK_FB_P1[2]    		PLL:DRP03[3]
    PLL:PLL_LOCK_FB_P1[3]
    26----------------------------PLL:DRP03[5]
    PLL:PLL_LOCK_FB_P2[0]    		PLL:DRP03[4]
    PLL:PLL_LOCK_FB_P1[4]
    27----------------------------PLL:DRP03[6]
    PLL:PLL_LOCK_FB_P2[1]    		PLL:DRP03[7]
    PLL:PLL_LOCK_FB_P2[2]
    28----------------------------PLL:DRP03[9]
    PLL:PLL_LOCK_FB_P2[4]    		PLL:DRP03[8]
    PLL:PLL_LOCK_FB_P2[3]
    29----------------------------PLL:DRP03[10]
    PLL:PLL_INC_SLOCK    		PLL:DRP03[11]
    PLL:PLL_INC_FLOCK
    30----------------------------PLL:DRP03[13]
    PLL:PLL_UNLOCK_CNT[1]    		PLL:DRP03[12]
    PLL:PLL_UNLOCK_CNT[0]
    31----------------------------PLL:DRP03[14]
    PLL:PLL_UNLOCK_CNT[2]    		PLL:DRP03[15]
    PLL:PLL_UNLOCK_CNT[3]
    32----------------------------PLL:DRP04[1]
    PLL:PLL_UNLOCK_CNT_RST_FAST    		PLL:DRP04[0]
    PLL:PLL_LOCK_CNT_RST_FAST
    33----------------------------PLL:DRP04[2]
    PLL:PLL_FLOCK[0]    		PLL:DRP04[3]
    PLL:PLL_FLOCK[1]
    34----------------------------PLL:DRP04[5]
    PLL:PLL_FLOCK[3]    		PLL:DRP04[4]
    PLL:PLL_FLOCK[2]
    35----------------------------PLL:DRP04[6]
    PLL:PLL_FLOCK[4]    		PLL:DRP04[7]
    PLL:PLL_FLOCK[5]
    36----------------------------PLL:DRP04[9]
    PLL:PLL_INTFB[1]    		PLL:DRP04[8]
    PLL:PLL_INTFB[0]
    37----------------------------PLL:DRP04[10]
    PLL:PLL_EN_TCLK0    		PLL:DRP04[11]
    PLL:PLL_EN_TCLK1
    38----------------------------PLL:DRP04[13]
    PLL:PLL_EN_TCLK3    		PLL:DRP04[12]
    PLL:PLL_EN_TCLK2
    39----------------------------PLL:DRP04[14]
    PLL:PLL_EN_TCLK4    		PLL:DRP04[15]
    ~PLL:PLL_TCK4_SEL
    40----------------------------PLL:DRP05[1]
    PLL:PLL_EN_CNTRL[1]    		PLL:DRP05[0]
    PLL:PLL_EN_CNTRL[0]
    41----------------------------PLL:DRP05[2]
    PLL:PLL_EN_CNTRL[2]    		PLL:DRP05[3]
    PLL:PLL_EN_CNTRL[3]
    42----------------------------PLL:DRP05[5]
    PLL:PLL_EN_CNTRL[5]    		PLL:DRP05[4]
    PLL:PLL_EN_CNTRL[4]
    43----------------------------PLL:DRP05[6]
    PLL:PLL_EN_CNTRL[6]    		PLL:DRP05[7]
    PLL:PLL_EN_CNTRL[7]
    44----------------------------PLL:DRP05[9]
    PLL:PLL_EN_CNTRL[9]    		PLL:DRP05[8]
    PLL:PLL_EN_CNTRL[8]
    45----------------------------PLL:DRP05[10]
    PLL:PLL_EN_CNTRL[10]    		PLL:DRP05[11]
    PLL:PLL_EN_CNTRL[11]
    46----------------------------PLL:DRP05[13]
    PLL:PLL_EN_CNTRL[13]    		PLL:DRP05[12]
    PLL:PLL_EN_CNTRL[12]
    47----------------------------PLL:DRP05[14]
    PLL:PLL_EN_CNTRL[14]    		PLL:DRP05[15]
    PLL:PLL_EN_CNTRL[15]
    48----------------------------PLL:DRP06[1]
    PLL:PLL_DIVCLK_LT[1]    		PLL:DRP06[0]
    PLL:PLL_DIVCLK_LT[0]
    49----------------------------PLL:DRP06[2]
    PLL:PLL_DIVCLK_LT[2]    		PLL:DRP06[3]
    PLL:PLL_DIVCLK_LT[3]
    50----------------------------PLL:DRP06[5]
    PLL:PLL_DIVCLK_LT[5]    		PLL:DRP06[4]
    PLL:PLL_DIVCLK_LT[4]
    51----------------------------PLL:DRP06[6]
    PLL:PLL_DIVCLK_HT[0]    		PLL:DRP06[7]
    PLL:PLL_DIVCLK_HT[1]
    52----------------------------PLL:DRP06[9]
    PLL:PLL_DIVCLK_HT[3]    		PLL:DRP06[8]
    PLL:PLL_DIVCLK_HT[2]
    53----------------------------PLL:DRP06[10]
    PLL:PLL_DIVCLK_HT[4]    		PLL:DRP06[11]
    PLL:PLL_DIVCLK_HT[5]
    54----------------------------PLL:DRP06[13]
    PLL:PLL_DIVCLK_EDGE    		PLL:DRP06[12]
    PLL:PLL_DIVCLK_NOCOUNT
    55----------------------------PLL:DRP06[14]PLL:DRP06[15]
    56----------------------------PLL:DRP07[1]
    PLL:PLL_IN_DLY_SET[1]    		PLL:DRP07[0]
    PLL:PLL_IN_DLY_SET[0]
    57----------------------------PLL:DRP07[2]
    PLL:PLL_IN_DLY_SET[2]    		PLL:DRP07[3]
    PLL:PLL_IN_DLY_SET[3]
    58----------------------------PLL:DRP07[5]
    PLL:PLL_IN_DLY_SET[5]    		PLL:DRP07[4]
    PLL:PLL_IN_DLY_SET[4]
    59----------------------------PLL:DRP07[6]
    PLL:PLL_IN_DLY_SET[6]    		PLL:DRP07[7]
    PLL:PLL_IN_DLY_SET[7]
    60----------------------------PLL:DRP07[9]
    PLL:PLL_EN_DLY    		PLL:DRP07[8]
    PLL:PLL_IN_DLY_SET[8]
    61----------------------------PLL:DRP07[10]
    PLL:PLL_IN_DLY_MX_SEL[0]    		PLL:DRP07[11]
    PLL:PLL_IN_DLY_MX_SEL[1]
    62----------------------------PLL:DRP07[13]
    PLL:PLL_IN_DLY_MX_SEL[3]    		PLL:DRP07[12]
    PLL:PLL_IN_DLY_MX_SEL[2]
    63----------------------------PLL:DRP07[14]
    PLL:PLL_IN_DLY_MX_SEL[4]    		PLL:DRP07[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 4
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP08[1]
    PLL:PLL_EN_CNTRL[17]    		PLL:DRP08[0]
    PLL:PLL_EN_CNTRL[16]
    1----------------------------PLL:DRP08[2]
    PLL:PLL_EN_CNTRL[18]    		PLL:DRP08[3]
    PLL:PLL_EN_CNTRL[19]
    2----------------------------PLL:DRP08[5]
    PLL:PLL_EN_CNTRL[21]    		PLL:DRP08[4]
    PLL:PLL_EN_CNTRL[20]
    3----------------------------PLL:DRP08[6]
    PLL:PLL_EN_CNTRL[22]    		PLL:DRP08[7]
    PLL:PLL_EN_CNTRL[23]
    4----------------------------PLL:DRP08[9]
    PLL:PLL_EN_CNTRL[25]    		PLL:DRP08[8]
    PLL:PLL_EN_CNTRL[24]
    5----------------------------PLL:DRP08[10]
    PLL:PLL_EN_CNTRL[26]    		PLL:DRP08[11]
    PLL:PLL_EN_CNTRL[27]
    6----------------------------PLL:DRP08[13]
    PLL:PLL_EN_CNTRL[29]    		PLL:DRP08[12]
    PLL:PLL_EN_CNTRL[28]
    7----------------------------PLL:DRP08[14]
    PLL:PLL_EN_CNTRL[30]    		PLL:DRP08[15]
    PLL:PLL_EN_CNTRL[31]
    8----------------------------PLL:DRP09[1]
    PLL:PLL_CLKFBOUT2_LT[1]    		PLL:DRP09[0]
    PLL:PLL_CLKFBOUT2_LT[0]
    9----------------------------PLL:DRP09[2]
    PLL:PLL_CLKFBOUT2_LT[2]    		PLL:DRP09[3]
    PLL:PLL_CLKFBOUT2_LT[3]
    10----------------------------PLL:DRP09[5]
    PLL:PLL_CLKFBOUT2_LT[5]    		PLL:DRP09[4]
    PLL:PLL_CLKFBOUT2_LT[4]
    11----------------------------PLL:DRP09[6]
    PLL:PLL_CLKFBOUT2_HT[0]    		PLL:DRP09[7]
    PLL:PLL_CLKFBOUT2_HT[1]
    12----------------------------PLL:DRP09[9]
    PLL:PLL_CLKFBOUT2_HT[3]    		PLL:DRP09[8]
    PLL:PLL_CLKFBOUT2_HT[2]
    13----------------------------PLL:DRP09[10]
    PLL:PLL_CLKFBOUT2_HT[4]    		PLL:DRP09[11]
    PLL:PLL_CLKFBOUT2_HT[5]
    14----------------------------PLL:DRP09[13]PLL:DRP09[12]
    15----------------------------PLL:DRP09[14]PLL:DRP09[15]
    16----------------------------PLL:DRP0A[1]
    PLL:PLL_CLKFBOUT2_DT[1]    		PLL:DRP0A[0]
    PLL:PLL_CLKFBOUT2_DT[0]
    17----------------------------PLL:DRP0A[2]
    PLL:PLL_CLKFBOUT2_DT[2]    		PLL:DRP0A[3]
    PLL:PLL_CLKFBOUT2_DT[3]
    18----------------------------PLL:DRP0A[5]
    PLL:PLL_CLKFBOUT2_DT[5]    		PLL:DRP0A[4]
    PLL:PLL_CLKFBOUT2_DT[4]
    19----------------------------PLL:DRP0A[6]
    PLL:PLL_CLKFBOUT2_NOCOUNT    		PLL:DRP0A[7]
    PLL:PLL_CLKFBOUT2_EDGE
    20----------------------------PLL:DRP0A[9]PLL:DRP0A[8]
    21----------------------------PLL:DRP0A[10]
    PLL:PLL_DIVCLK_DT[0]    		PLL:DRP0A[11]
    PLL:PLL_DIVCLK_DT[1]
    22----------------------------PLL:DRP0A[13]
    PLL:PLL_DIVCLK_DT[3]    		PLL:DRP0A[12]
    PLL:PLL_DIVCLK_DT[2]
    23----------------------------PLL:DRP0A[14]
    PLL:PLL_DIVCLK_DT[4]    		PLL:DRP0A[15]
    PLL:PLL_DIVCLK_DT[5]
    24----------------------------PLL:DRP0B[1]
    PLL:PLL_EN_CNTRL[33]    		PLL:DRP0B[0]
    PLL:PLL_EN_CNTRL[32]
    25----------------------------PLL:DRP0B[2]
    PLL:PLL_EN_CNTRL[34]    		PLL:DRP0B[3]
    PLL:PLL_EN_CNTRL[35]
    26----------------------------PLL:DRP0B[5]
    PLL:PLL_EN_CNTRL[37]    		PLL:DRP0B[4]
    PLL:PLL_EN_CNTRL[36]
    27----------------------------PLL:DRP0B[6]
    PLL:PLL_EN_CNTRL[38]    		PLL:DRP0B[7]
    PLL:PLL_EN_CNTRL[39]
    28----------------------------PLL:DRP0B[9]
    PLL:PLL_EN_CNTRL[41]    		PLL:DRP0B[8]
    PLL:PLL_EN_CNTRL[40]
    29----------------------------PLL:DRP0B[10]
    PLL:PLL_EN_CNTRL[42]    		PLL:DRP0B[11]
    PLL:PLL_EN_CNTRL[43]
    30----------------------------PLL:DRP0B[13]
    PLL:PLL_EN_CNTRL[45]    		PLL:DRP0B[12]
    PLL:PLL_EN_CNTRL[44]
    31----------------------------PLL:DRP0B[14]
    PLL:PLL_EN_CNTRL[46]    		PLL:DRP0B[15]
    PLL:PLL_EN_CNTRL[47]
    32----------------------------PLL:DRP0C[1]
    PLL:PLL_CLKFBOUT_LT[1]    		PLL:DRP0C[0]
    PLL:PLL_CLKFBOUT_LT[0]
    33----------------------------PLL:DRP0C[2]
    PLL:PLL_CLKFBOUT_LT[2]    		PLL:DRP0C[3]
    PLL:PLL_CLKFBOUT_LT[3]
    34----------------------------PLL:DRP0C[5]
    PLL:PLL_CLKFBOUT_LT[5]    		PLL:DRP0C[4]
    PLL:PLL_CLKFBOUT_LT[4]
    35----------------------------PLL:DRP0C[6]
    PLL:PLL_CLKFBOUT_HT[0]    		PLL:DRP0C[7]
    PLL:PLL_CLKFBOUT_HT[1]
    36----------------------------PLL:DRP0C[9]
    PLL:PLL_CLKFBOUT_HT[3]    		PLL:DRP0C[8]
    PLL:PLL_CLKFBOUT_HT[2]
    37----------------------------PLL:DRP0C[10]
    PLL:PLL_CLKFBOUT_HT[4]    		PLL:DRP0C[11]
    PLL:PLL_CLKFBOUT_HT[5]
    38----------------------------PLL:DRP0C[13]
    PLL:PLL_CLKFBOUT_PM[0]    		PLL:DRP0C[12]
    PLL:PLL_CLKFBOUT_EN
    39----------------------------PLL:DRP0C[14]
    PLL:PLL_CLKFBOUT_PM[1]    		PLL:DRP0C[15]
    PLL:PLL_CLKFBOUT_PM[2]
    40----------------------------PLL:DRP0D[1]
    PLL:PLL_CLKFBOUT_DT[1]    		PLL:DRP0D[0]
    PLL:PLL_CLKFBOUT_DT[0]
    41----------------------------PLL:DRP0D[2]
    PLL:PLL_CLKFBOUT_DT[2]    		PLL:DRP0D[3]
    PLL:PLL_CLKFBOUT_DT[3]
    42----------------------------PLL:DRP0D[5]
    PLL:PLL_CLKFBOUT_DT[5]    		PLL:DRP0D[4]
    PLL:PLL_CLKFBOUT_DT[4]
    43----------------------------PLL:DRP0D[6]
    PLL:PLL_CLKFBOUT_NOCOUNT    		PLL:DRP0D[7]
    PLL:PLL_CLKFBOUT_EDGE
    44----------------------------PLL:DRP0D[9]
    PLL:PLL_CLKFBMX[1]    		PLL:DRP0D[8]
    PLL:PLL_CLKFBMX[0]
    45----------------------------PLL:DRP0D[10]
    PLL:PLL_NBTI_EN    		PLL:CLKFBOUT_DESKEW_ADJUST[0]
    PLL:DRP0D[11]
    46----------------------------PLL:CLKFBOUT_DESKEW_ADJUST[2]
    PLL:DRP0D[13]    		PLL:CLKFBOUT_DESKEW_ADJUST[1]
    PLL:DRP0D[12]
    47----------------------------PLL:CLKFBOUT_DESKEW_ADJUST[3]
    PLL:DRP0D[14]    		PLL:CLKFBOUT_DESKEW_ADJUST[4]
    PLL:DRP0D[15]
    48----------------------------PLL:DRP0E[1]
    PLL:PLL_CLKOUT5_LT[1]    		PLL:DRP0E[0]
    PLL:PLL_CLKOUT5_LT[0]
    49----------------------------PLL:DRP0E[2]
    PLL:PLL_CLKOUT5_LT[2]    		PLL:DRP0E[3]
    PLL:PLL_CLKOUT5_LT[3]
    50----------------------------PLL:DRP0E[5]
    PLL:PLL_CLKOUT5_LT[5]    		PLL:DRP0E[4]
    PLL:PLL_CLKOUT5_LT[4]
    51----------------------------PLL:DRP0E[6]
    PLL:PLL_CLKOUT5_HT[0]    		PLL:DRP0E[7]
    PLL:PLL_CLKOUT5_HT[1]
    52----------------------------PLL:DRP0E[9]
    PLL:PLL_CLKOUT5_HT[3]    		PLL:DRP0E[8]
    PLL:PLL_CLKOUT5_HT[2]
    53----------------------------PLL:DRP0E[10]
    PLL:PLL_CLKOUT5_HT[4]    		PLL:DRP0E[11]
    PLL:PLL_CLKOUT5_HT[5]
    54----------------------------PLL:DRP0E[13]
    PLL:PLL_CLKOUT5_PM[0]    		PLL:DRP0E[12]
    PLL:PLL_CLKOUT5_EN
    55----------------------------PLL:DRP0E[14]
    PLL:PLL_CLKOUT5_PM[1]    		PLL:DRP0E[15]
    PLL:PLL_CLKOUT5_PM[2]
    56----------------------------PLL:DRP0F[1]
    PLL:PLL_CLKOUT5_DT[1]    		PLL:DRP0F[0]
    PLL:PLL_CLKOUT5_DT[0]
    57----------------------------PLL:DRP0F[2]
    PLL:PLL_CLKOUT5_DT[2]    		PLL:DRP0F[3]
    PLL:PLL_CLKOUT5_DT[3]
    58----------------------------PLL:DRP0F[5]
    PLL:PLL_CLKOUT5_DT[5]    		PLL:DRP0F[4]
    PLL:PLL_CLKOUT5_DT[4]
    59----------------------------PLL:DRP0F[6]
    PLL:PLL_CLKOUT5_NOCOUNT    		PLL:DRP0F[7]
    PLL:PLL_CLKOUT5_EDGE
    60----------------------------PLL:DRP0F[9]
    PLL:PLL_CLK5MX[1]    		PLL:DRP0F[8]
    PLL:PLL_CLK5MX[0]
    61----------------------------PLL:DRP0F[10]PLL:CLKOUT5_DESKEW_ADJUST[0]
    PLL:DRP0F[11]
    62----------------------------PLL:CLKOUT5_DESKEW_ADJUST[2]
    PLL:DRP0F[13]    		PLL:CLKOUT5_DESKEW_ADJUST[1]
    PLL:DRP0F[12]
    63----------------------------PLL:CLKOUT5_DESKEW_ADJUST[3]
    PLL:DRP0F[14]    		PLL:CLKOUT5_DESKEW_ADJUST[4]
    PLL:DRP0F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 5
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP10[1]
    PLL:PLL_EN_CNTRL[49]    		PLL:DRP10[0]
    PLL:PLL_EN_CNTRL[48]
    1----------------------------PLL:DRP10[2]
    PLL:PLL_EN_CNTRL[50]    		PLL:DRP10[3]
    PLL:PLL_EN_CNTRL[51]
    2----------------------------PLL:DRP10[5]
    PLL:PLL_EN_CNTRL[53]    		PLL:DRP10[4]
    PLL:PLL_EN_CNTRL[52]
    3----------------------------PLL:DRP10[6]
    PLL:PLL_EN_CNTRL[54]    		PLL:DRP10[7]
    PLL:PLL_EN_CNTRL[55]
    4----------------------------PLL:DRP10[9]
    PLL:PLL_EN_CNTRL[57]    		PLL:DRP10[8]
    PLL:PLL_EN_CNTRL[56]
    5----------------------------PLL:DRP10[10]
    PLL:PLL_EN_CNTRL[58]    		PLL:DRP10[11]
    PLL:PLL_EN_CNTRL[59]
    6----------------------------PLL:DRP10[13]
    PLL:PLL_EN_CNTRL[61]    		PLL:DRP10[12]
    PLL:PLL_EN_CNTRL[60]
    7----------------------------PLL:DRP10[14]
    PLL:PLL_EN_CNTRL[62]    		PLL:DRP10[15]
    PLL:PLL_EN_CNTRL[63]
    8----------------------------PLL:DRP11[1]
    PLL:PLL_EN_CNTRL[65]    		PLL:DRP11[0]
    PLL:PLL_EN_CNTRL[64]
    9----------------------------PLL:DRP11[2]
    PLL:PLL_EN_CNTRL[66]    		PLL:DRP11[3]
    PLL:PLL_EN_CNTRL[67]
    10----------------------------PLL:DRP11[5]
    PLL:PLL_EN_CNTRL[69]    		PLL:DRP11[4]
    PLL:PLL_EN_CNTRL[68]
    11----------------------------PLL:DRP11[6]
    PLL:PLL_EN_CNTRL[70]    		PLL:DRP11[7]
    PLL:PLL_EN_CNTRL[71]
    12----------------------------PLL:DRP11[9]
    PLL:PLL_EN_CNTRL[73]    		PLL:DRP11[8]
    PLL:PLL_EN_CNTRL[72]
    13----------------------------PLL:DRP11[10]
    PLL:PLL_EN_CNTRL[74]    		PLL:DRP11[11]
    PLL:PLL_EN_CNTRL[75]
    14----------------------------PLL:DRP11[13]
    PLL:PLL_EN_CNTRL[77]    		PLL:DRP11[12]
    PLL:PLL_EN_CNTRL[76]
    15----------------------------PLL:DRP11[14]
    PLL:PLL_PMCD_MODE    		PLL:DRP11[15]
    PLL:PLL_EN
    16----------------------------PLL:DRP12[1]
    PLL:PLL_CLKOUT4_LT[1]    		PLL:DRP12[0]
    PLL:PLL_CLKOUT4_LT[0]
    17----------------------------PLL:DRP12[2]
    PLL:PLL_CLKOUT4_LT[2]    		PLL:DRP12[3]
    PLL:PLL_CLKOUT4_LT[3]
    18----------------------------PLL:DRP12[5]
    PLL:PLL_CLKOUT4_LT[5]    		PLL:DRP12[4]
    PLL:PLL_CLKOUT4_LT[4]
    19----------------------------PLL:DRP12[6]
    PLL:PLL_CLKOUT4_HT[0]    		PLL:DRP12[7]
    PLL:PLL_CLKOUT4_HT[1]
    20----------------------------PLL:DRP12[9]
    PLL:PLL_CLKOUT4_HT[3]    		PLL:DRP12[8]
    PLL:PLL_CLKOUT4_HT[2]
    21----------------------------PLL:DRP12[10]
    PLL:PLL_CLKOUT4_HT[4]    		PLL:DRP12[11]
    PLL:PLL_CLKOUT4_HT[5]
    22----------------------------PLL:DRP12[13]
    PLL:PLL_CLKOUT4_PM[0]    		PLL:DRP12[12]
    PLL:PLL_CLKOUT4_EN
    23----------------------------PLL:DRP12[14]
    PLL:PLL_CLKOUT4_PM[1]    		PLL:DRP12[15]
    PLL:PLL_CLKOUT4_PM[2]
    24----------------------------PLL:DRP13[1]
    PLL:PLL_CLKOUT4_DT[1]    		PLL:DRP13[0]
    PLL:PLL_CLKOUT4_DT[0]
    25----------------------------PLL:DRP13[2]
    PLL:PLL_CLKOUT4_DT[2]    		PLL:DRP13[3]
    PLL:PLL_CLKOUT4_DT[3]
    26----------------------------PLL:DRP13[5]
    PLL:PLL_CLKOUT4_DT[5]    		PLL:DRP13[4]
    PLL:PLL_CLKOUT4_DT[4]
    27----------------------------PLL:DRP13[6]
    PLL:PLL_CLKOUT4_NOCOUNT    		PLL:DRP13[7]
    PLL:PLL_CLKOUT4_EDGE
    28----------------------------PLL:DRP13[9]
    PLL:PLL_CLK4MX[1]    		PLL:DRP13[8]
    PLL:PLL_CLK4MX[0]
    29----------------------------PLL:DRP13[10]PLL:CLKOUT4_DESKEW_ADJUST[0]
    PLL:DRP13[11]
    30----------------------------PLL:CLKOUT4_DESKEW_ADJUST[2]
    PLL:DRP13[13]    		PLL:CLKOUT4_DESKEW_ADJUST[1]
    PLL:DRP13[12]
    31----------------------------PLL:CLKOUT4_DESKEW_ADJUST[3]
    PLL:DRP13[14]    		PLL:CLKOUT4_DESKEW_ADJUST[4]
    PLL:DRP13[15]
    32----------------------------PLL:DRP14[1]
    PLL:PLL_CLKOUT3_LT[1]    		PLL:DRP14[0]
    PLL:PLL_CLKOUT3_LT[0]
    33----------------------------PLL:DRP14[2]
    PLL:PLL_CLKOUT3_LT[2]    		PLL:DRP14[3]
    PLL:PLL_CLKOUT3_LT[3]
    34----------------------------PLL:DRP14[5]
    PLL:PLL_CLKOUT3_LT[5]    		PLL:DRP14[4]
    PLL:PLL_CLKOUT3_LT[4]
    35----------------------------PLL:DRP14[6]
    PLL:PLL_CLKOUT3_HT[0]    		PLL:DRP14[7]
    PLL:PLL_CLKOUT3_HT[1]
    36----------------------------PLL:DRP14[9]
    PLL:PLL_CLKOUT3_HT[3]    		PLL:DRP14[8]
    PLL:PLL_CLKOUT3_HT[2]
    37----------------------------PLL:DRP14[10]
    PLL:PLL_CLKOUT3_HT[4]    		PLL:DRP14[11]
    PLL:PLL_CLKOUT3_HT[5]
    38----------------------------PLL:DRP14[13]
    PLL:PLL_CLKOUT3_PM[0]    		PLL:DRP14[12]
    PLL:PLL_CLKOUT3_EN
    39----------------------------PLL:DRP14[14]
    PLL:PLL_CLKOUT3_PM[1]    		PLL:DRP14[15]
    PLL:PLL_CLKOUT3_PM[2]
    40----------------------------PLL:DRP15[1]
    PLL:PLL_CLKOUT3_DT[1]    		PLL:DRP15[0]
    PLL:PLL_CLKOUT3_DT[0]
    41----------------------------PLL:DRP15[2]
    PLL:PLL_CLKOUT3_DT[2]    		PLL:DRP15[3]
    PLL:PLL_CLKOUT3_DT[3]
    42----------------------------PLL:DRP15[5]
    PLL:PLL_CLKOUT3_DT[5]    		PLL:DRP15[4]
    PLL:PLL_CLKOUT3_DT[4]
    43----------------------------PLL:DRP15[6]
    PLL:PLL_CLKOUT3_NOCOUNT    		PLL:DRP15[7]
    PLL:PLL_CLKOUT3_EDGE
    44----------------------------PLL:DRP15[9]
    PLL:PLL_CLK3MX[1]    		PLL:DRP15[8]
    PLL:PLL_CLK3MX[0]
    45----------------------------PLL:DRP15[10]PLL:CLKOUT3_DESKEW_ADJUST[0]
    PLL:DRP15[11]
    46----------------------------PLL:CLKOUT3_DESKEW_ADJUST[2]
    PLL:DRP15[13]    		PLL:CLKOUT3_DESKEW_ADJUST[1]
    PLL:DRP15[12]
    47----------------------------PLL:CLKOUT3_DESKEW_ADJUST[3]
    PLL:DRP15[14]    		PLL:CLKOUT3_DESKEW_ADJUST[4]
    PLL:DRP15[15]
    48----------------------------PLL:DRP16[1]
    PLL:PLL_CLKOUT2_LT[1]    		PLL:DRP16[0]
    PLL:PLL_CLKOUT2_LT[0]
    49----------------------------PLL:DRP16[2]
    PLL:PLL_CLKOUT2_LT[2]    		PLL:DRP16[3]
    PLL:PLL_CLKOUT2_LT[3]
    50----------------------------PLL:DRP16[5]
    PLL:PLL_CLKOUT2_LT[5]    		PLL:DRP16[4]
    PLL:PLL_CLKOUT2_LT[4]
    51----------------------------PLL:DRP16[6]
    PLL:PLL_CLKOUT2_HT[0]    		PLL:DRP16[7]
    PLL:PLL_CLKOUT2_HT[1]
    52----------------------------PLL:DRP16[9]
    PLL:PLL_CLKOUT2_HT[3]    		PLL:DRP16[8]
    PLL:PLL_CLKOUT2_HT[2]
    53----------------------------PLL:DRP16[10]
    PLL:PLL_CLKOUT2_HT[4]    		PLL:DRP16[11]
    PLL:PLL_CLKOUT2_HT[5]
    54----------------------------PLL:DRP16[13]
    PLL:PLL_CLKOUT2_PM[0]    		PLL:DRP16[12]
    PLL:PLL_CLKOUT2_EN
    55----------------------------PLL:DRP16[14]
    PLL:PLL_CLKOUT2_PM[1]    		PLL:DRP16[15]
    PLL:PLL_CLKOUT2_PM[2]
    56----------------------------PLL:DRP17[1]
    PLL:PLL_CLKOUT2_DT[1]    		PLL:DRP17[0]
    PLL:PLL_CLKOUT2_DT[0]
    57----------------------------PLL:DRP17[2]
    PLL:PLL_CLKOUT2_DT[2]    		PLL:DRP17[3]
    PLL:PLL_CLKOUT2_DT[3]
    58----------------------------PLL:DRP17[5]
    PLL:PLL_CLKOUT2_DT[5]    		PLL:DRP17[4]
    PLL:PLL_CLKOUT2_DT[4]
    59----------------------------PLL:DRP17[6]
    PLL:PLL_CLKOUT2_NOCOUNT    		PLL:DRP17[7]
    PLL:PLL_CLKOUT2_EDGE
    60----------------------------PLL:DRP17[9]
    PLL:PLL_CLK2MX[1]    		PLL:DRP17[8]
    PLL:PLL_CLK2MX[0]
    61----------------------------PLL:DRP17[10]PLL:CLKOUT2_DESKEW_ADJUST[0]
    PLL:DRP17[11]
    62----------------------------PLL:CLKOUT2_DESKEW_ADJUST[2]
    PLL:DRP17[13]    		PLL:CLKOUT2_DESKEW_ADJUST[1]
    PLL:DRP17[12]
    63----------------------------PLL:CLKOUT2_DESKEW_ADJUST[3]
    PLL:DRP17[14]    		PLL:CLKOUT2_DESKEW_ADJUST[4]
    PLL:DRP17[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 6
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP18[1]
    PLL:PLL_EN_VCO_DIV1    		PLL:DRP18[0]
    PLL:PLL_DIRECT_PATH_CNTRL
    1----------------------------PLL:DRP18[2]
    PLL:PLL_EN_VCO_DIV6    		PLL:DRP18[3]
    PLL:PLL_EN_VCO0
    2----------------------------PLL:DRP18[5]
    PLL:PLL_EN_VCO2    		PLL:DRP18[4]
    PLL:PLL_EN_VCO1
    3----------------------------PLL:DRP18[6]
    PLL:PLL_EN_VCO3    		PLL:DRP18[7]
    PLL:PLL_EN_VCO4
    4----------------------------PLL:DRP18[9]
    PLL:PLL_EN_VCO6    		PLL:DRP18[8]
    PLL:PLL_EN_VCO5
    5----------------------------PLL:DRP18[10]
    PLL:PLL_EN_VCO7    		PLL:DRP18[11]
    6----------------------------PLL:DRP18[13]
    PLL:PLL_CLKBURST_CNT[0]    		PLL:DRP18[12]
    PLL:PLL_CLKBURST_ENABLE
    7----------------------------PLL:DRP18[14]
    PLL:PLL_CLKBURST_CNT[1]    		PLL:DRP18[15]
    PLL:PLL_CLKBURST_CNT[2]
    8----------------------------PLL:DRP19[1]
    PLL:PLL_CLKOUT1_LT[1]    		PLL:DRP19[0]
    PLL:PLL_CLKOUT1_LT[0]
    9----------------------------PLL:DRP19[2]
    PLL:PLL_CLKOUT1_LT[2]    		PLL:DRP19[3]
    PLL:PLL_CLKOUT1_LT[3]
    10----------------------------PLL:DRP19[5]
    PLL:PLL_CLKOUT1_LT[5]    		PLL:DRP19[4]
    PLL:PLL_CLKOUT1_LT[4]
    11----------------------------PLL:DRP19[6]
    PLL:PLL_CLKOUT1_HT[0]    		PLL:DRP19[7]
    PLL:PLL_CLKOUT1_HT[1]
    12----------------------------PLL:DRP19[9]
    PLL:PLL_CLKOUT1_HT[3]    		PLL:DRP19[8]
    PLL:PLL_CLKOUT1_HT[2]
    13----------------------------PLL:DRP19[10]
    PLL:PLL_CLKOUT1_HT[4]    		PLL:DRP19[11]
    PLL:PLL_CLKOUT1_HT[5]
    14----------------------------PLL:DRP19[13]
    PLL:PLL_CLKOUT1_PM[0]    		PLL:DRP19[12]
    PLL:PLL_CLKOUT1_EN
    15----------------------------PLL:DRP19[14]
    PLL:PLL_CLKOUT1_PM[1]    		PLL:DRP19[15]
    PLL:PLL_CLKOUT1_PM[2]
    16----------------------------PLL:DRP1A[1]
    PLL:PLL_CLKOUT1_DT[1]    		PLL:DRP1A[0]
    PLL:PLL_CLKOUT1_DT[0]
    17----------------------------PLL:DRP1A[2]
    PLL:PLL_CLKOUT1_DT[2]    		PLL:DRP1A[3]
    PLL:PLL_CLKOUT1_DT[3]
    18----------------------------PLL:DRP1A[5]
    PLL:PLL_CLKOUT1_DT[5]    		PLL:DRP1A[4]
    PLL:PLL_CLKOUT1_DT[4]
    19----------------------------PLL:DRP1A[6]
    PLL:PLL_CLKOUT1_NOCOUNT    		PLL:DRP1A[7]
    PLL:PLL_CLKOUT1_EDGE
    20----------------------------PLL:DRP1A[9]
    PLL:PLL_CLK1MX[1]    		PLL:DRP1A[8]
    PLL:PLL_CLK1MX[0]
    21----------------------------PLL:DRP1A[10]PLL:CLKOUT1_DESKEW_ADJUST[0]
    PLL:DRP1A[11]
    22----------------------------PLL:CLKOUT1_DESKEW_ADJUST[2]
    PLL:DRP1A[13]    		PLL:CLKOUT1_DESKEW_ADJUST[1]
    PLL:DRP1A[12]
    23----------------------------PLL:CLKOUT1_DESKEW_ADJUST[3]
    PLL:DRP1A[14]    		PLL:CLKOUT1_DESKEW_ADJUST[4]
    PLL:DRP1A[15]
    24----------------------------PLL:DRP1B[1]
    PLL:PLL_CLKOUT0_LT[1]    		PLL:DRP1B[0]
    PLL:PLL_CLKOUT0_LT[0]
    25----------------------------PLL:DRP1B[2]
    PLL:PLL_CLKOUT0_LT[2]    		PLL:DRP1B[3]
    PLL:PLL_CLKOUT0_LT[3]
    26----------------------------PLL:DRP1B[5]
    PLL:PLL_CLKOUT0_LT[5]    		PLL:DRP1B[4]
    PLL:PLL_CLKOUT0_LT[4]
    27----------------------------PLL:DRP1B[6]
    PLL:PLL_CLKOUT0_HT[0]    		PLL:DRP1B[7]
    PLL:PLL_CLKOUT0_HT[1]
    28----------------------------PLL:DRP1B[9]
    PLL:PLL_CLKOUT0_HT[3]    		PLL:DRP1B[8]
    PLL:PLL_CLKOUT0_HT[2]
    29----------------------------PLL:DRP1B[10]
    PLL:PLL_CLKOUT0_HT[4]    		PLL:DRP1B[11]
    PLL:PLL_CLKOUT0_HT[5]
    30----------------------------PLL:DRP1B[13]
    PLL:PLL_CLKOUT0_PM[0]    		PLL:DRP1B[12]
    PLL:PLL_CLKOUT0_EN
    31----------------------------PLL:DRP1B[14]
    PLL:PLL_CLKOUT0_PM[1]    		PLL:DRP1B[15]
    PLL:PLL_CLKOUT0_PM[2]
    32----------------------------PLL:DRP1C[1]
    PLL:PLL_CLKOUT0_DT[1]    		PLL:DRP1C[0]
    PLL:PLL_CLKOUT0_DT[0]
    33----------------------------PLL:DRP1C[2]
    PLL:PLL_CLKOUT0_DT[2]    		PLL:DRP1C[3]
    PLL:PLL_CLKOUT0_DT[3]
    34----------------------------PLL:DRP1C[5]
    PLL:PLL_CLKOUT0_DT[5]    		PLL:DRP1C[4]
    PLL:PLL_CLKOUT0_DT[4]
    35----------------------------PLL:DRP1C[6]
    PLL:PLL_CLKOUT0_NOCOUNT    		PLL:DRP1C[7]
    PLL:PLL_CLKOUT0_EDGE
    36----------------------------PLL:DRP1C[9]
    PLL:PLL_CLK0MX[1]    		PLL:DRP1C[8]
    PLL:PLL_CLK0MX[0]
    37----------------------------PLL:DRP1C[10]PLL:CLKOUT0_DESKEW_ADJUST[0]
    PLL:DRP1C[11]
    38----------------------------PLL:CLKOUT0_DESKEW_ADJUST[2]
    PLL:DRP1C[13]    		PLL:CLKOUT0_DESKEW_ADJUST[1]
    PLL:DRP1C[12]
    39----------------------------PLL:CLKOUT0_DESKEW_ADJUST[3]
    PLL:DRP1C[14]    		PLL:CLKOUT0_DESKEW_ADJUST[4]
    PLL:DRP1C[15]
    40----------------------------PLL:DRP1D[1]
    PLL:INV.MANPDLF    		PLL:DRP1D[0]
    PLL:INV.RST
    41----------------------------PLL:DRP1D[2]
    PLL:INV.MANPULF    		PLL:DRP1D[3]
    PLL:INV.REL
    42----------------------------PLL:DRP1D[5]
    PLL:INV.ENOUTSYNC    		PLL:DRP1D[4]
    PLL:INV.CLKBRST
    43----------------------------PLL:DRP1D[6]
    ~PLL:PLL_CLKCNTRL    		PLL:CLKINSEL_MODE
    PLL:DRP1D[7]
    44----------------------------CMT:MUX.OUT10[0]
    PLL:DRP1D[9]    		PLL:DRP1D[8]
    ~PLL:INV.CLKINSEL
    45----------------------------CMT:MUX.OUT10[1]
    PLL:DRP1D[10]    		CMT:MUX.OUT10[2]
    PLL:DRP1D[11]
    46----------------------------PLL:DRP1D[13]
    PLL:INV.SKEWCLKIN2    		PLL:DRP1D[12]
    PLL:INV.SKEWCLKIN1
    47----------------------------PLL:DRP1D[14]
    PLL:INV.SKEWSTB    		PLL:DRP1D[15]
    PLL:INV.SKEWRST
    48----------------------------PLL:DRP1E[1]
    PLL:MUX.CLKIN[1]    		PLL:DRP1E[0]
    PLL:MUX.CLKIN[0]
    49----------------------------PLL:DRP1E[2]
    PLL:MUX.CLKIN[2]    		PLL:DRP1E[3]
    PLL:MUX.CLKIN[3]
    50----------------------------PLL:DRP1E[5]
    PLL:MUX.CLKFBIN[0]    		PLL:CLKINSEL_STATIC
    PLL:DRP1E[4]
    51----------------------------PLL:DRP1E[6]
    PLL:MUX.CLKFBIN[1]    		PLL:DRP1E[7]
    PLL:MUX.CLKFBIN[2]
    52----------------------------PLL:DRP1E[9]
    PLL:MUX.CLKFBIN[4]    		PLL:DRP1E[8]
    PLL:MUX.CLKFBIN[3]
    53----------------------------PLL:DRP1E[10]
    PLL:MUX.CLK_TO_DCM0[2]    		PLL:DRP1E[11]
    PLL:MUX.CLK_TO_DCM0[0]
    54----------------------------PLL:DRP1E[13]
    PLL:MUX.CLK_TO_DCM1[2]    		PLL:DRP1E[12]
    PLL:MUX.CLK_TO_DCM0[1]
    55----------------------------PLL:DRP1E[14]
    PLL:MUX.CLK_TO_DCM1[0]    		PLL:DRP1E[15]
    PLL:MUX.CLK_TO_DCM1[1]
    56----------------------------PLL:DRP1F[1]
    PLL:PLL_DVDD_VBG_SEL[1]    		PLL:DRP1F[0]
    PLL:PLL_DVDD_VBG_SEL[0]
    57----------------------------PLL:DRP1F[2]
    PLL:PLL_DVDD_VBG_SEL[2]    		PLL:DRP1F[3]
    PLL:PLL_DVDD_VBG_SEL[3]
    58----------------------------PLL:DRP1F[5]
    PLL:PLL_DVDD_VBG_PD[1]    		PLL:DRP1F[4]
    PLL:PLL_DVDD_VBG_PD[0]
    59----------------------------PLL:DRP1F[6]
    PLL:PLL_DVDD_COMP_SET[0]    		PLL:DRP1F[7]
    PLL:PLL_DVDD_COMP_SET[1]
    60----------------------------PLL:DRP1F[9]
    PLL:PLL_AVDD_VBG_SEL[1]    		PLL:DRP1F[8]
    PLL:PLL_AVDD_VBG_SEL[0]
    61----------------------------PLL:DRP1F[10]
    PLL:PLL_AVDD_VBG_SEL[2]    		PLL:DRP1F[11]
    PLL:PLL_AVDD_VBG_SEL[3]
    62----------------------------PLL:DRP1F[13]
    PLL:PLL_AVDD_VBG_PD[1]    		PLL:DRP1F[12]
    PLL:PLL_AVDD_VBG_PD[0]
    63----------------------------PLL:DRP1F[14]
    PLL:PLL_AVDD_COMP_SET[0]    		PLL:DRP1F[15]
    PLL:PLL_AVDD_COMP_SET[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 7
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM1:DRP40[1]DCM1:DRP40[0]
    1----------------------------DCM1:DRP40[2]DCM1:DRP40[3]
    2----------------------------DCM1:DRP40[5]DCM1:DRP40[4]
    3----------------------------DCM1:DRP40[6]DCM1:DRP40[7]
    4----------------------------DCM1:DRP40[9]DCM1:DRP40[8]
    5----------------------------DCM1:DRP40[10]DCM1:DRP40[11]
    6----------------------------DCM1:DRP40[13]DCM1:DRP40[12]
    7----------------------------DCM1:DRP40[14]DCM1:DRP40[15]
    8----------------------------DCM1:DFS_OSCILLATOR_MODE
    DCM1:DRP41[1]    		DCM1:DRP41[0]
    9----------------------------DCM1:DFS_FREQUENCY_MODE
    DCM1:DRP41[2]    		DCM1:DFS_CFG_BYPASS
    DCM1:DRP41[3]
    10----------------------------DCM1:DFS_SYNTH_FAST_SYNCH[1]
    DCM1:DRP41[5]    		DCM1:DFS_SYNTH_FAST_SYNCH[0]
    DCM1:DRP41[4]
    11----------------------------DCM1:DFS_AVE_FREQ_GAIN[0]
    DCM1:DRP41[6]    		DCM1:DFS_AVE_FREQ_GAIN[1]
    DCM1:DRP41[7]
    12----------------------------DCM1:DFS_EARLY_LOCK
    DCM1:DRP41[9]    		DCM1:DFS_AVE_FREQ_GAIN[2]
    DCM1:DRP41[8]
    13----------------------------DCM1:DRP41[10]DCM1:DRP41[11]
    14----------------------------DCM1:DRP41[13]DCM1:DRP41[12]
    15----------------------------DCM1:DFS_HARDSYNC_B[0]
    DCM1:DRP41[14]    		DCM1:DFS_HARDSYNC_B[1]
    DCM1:DRP41[15]
    16----------------------------DCM1:DRP42[1]DCM1:DRP42[0]
    17----------------------------DCM1:DRP42[2]DCM1:DFS_JF_LOWER_LIMIT[0]
    DCM1:DRP42[3]
    18----------------------------DCM1:DFS_JF_LOWER_LIMIT[2]
    DCM1:DRP42[5]    		DCM1:DFS_JF_LOWER_LIMIT[1]
    DCM1:DRP42[4]
    19----------------------------DCM1:DFS_JF_LOWER_LIMIT[3]
    DCM1:DRP42[6]    		DCM1:DFS_OSC_ON_FX
    DCM1:DRP42[7]
    20----------------------------DCM1:DFS_HF_TRIM_CAL[0]
    DCM1:DRP42[9]    		DCM1:DFS_REF_ON_FX
    DCM1:DRP42[8]
    21----------------------------DCM1:DFS_HF_TRIM_CAL[1]
    DCM1:DRP42[10]    		DCM1:DFS_HF_TRIM_CAL[2]
    DCM1:DRP42[11]
    22----------------------------~DCM1:DFS_PWRD_REPLY_TIMES_OUT_B
    DCM1:DRP42[13]    		DCM1:DRP42[12]
    23----------------------------~DCM1:DFS_PWRD_CLKIN_STOP_STICKY_B
    DCM1:DRP42[14]    		~DCM1:DFS_PWRD_CLKIN_STOP_B
    DCM1:DRP42[15]
    24----------------------------DCM1:DCM_CLKIN_IODLY_MUXOUT_SEL
    DCM1:DRP43[1]    		DCM1:DCM_CLKFB_IODLY_MUXOUT_SEL
    DCM1:DRP43[0]
    25----------------------------DCM1:DRP43[2]DCM1:DESKEW_ADJUST[0]
    DCM1:DRP43[3]
    26----------------------------DCM1:DESKEW_ADJUST[2]
    DCM1:DRP43[5]    		DCM1:DESKEW_ADJUST[1]
    DCM1:DRP43[4]
    27----------------------------DCM1:DESKEW_ADJUST[3]
    DCM1:DRP43[6]    		DCM1:DESKEW_ADJUST[4]
    DCM1:DRP43[7]
    28----------------------------DCM1:DCM_PLL_RST_DCM
    DCM1:DRP43[9]    		DCM1:DRP43[8]
    29----------------------------DCM1:DCM_COM_PWC_REF_TAP[0]
    DCM1:DRP43[10]    		DCM1:DCM_COM_PWC_REF_TAP[1]
    DCM1:DRP43[11]
    30----------------------------DCM1:DCM_COM_PWC_FB_TAP[0]
    DCM1:DRP43[13]    		DCM1:DCM_COM_PWC_REF_TAP[2]
    DCM1:DRP43[12]
    31----------------------------DCM1:DCM_COM_PWC_FB_TAP[1]
    DCM1:DRP43[14]    		DCM1:DCM_COM_PWC_FB_TAP[2]
    DCM1:DRP43[15]
    32----------------------------DCM1:DCM_COM_PWC_FB_EN
    DCM1:DRP44[1]    		DCM1:DCM_COM_PWC_REF_EN
    DCM1:DRP44[0]
    33----------------------------DCM1:DCM_EXT_FB_EN
    DCM1:DRP44[2]    		DCM1:DCM_USE_REG_READY
    DCM1:DRP44[3]
    34----------------------------DCM1:DLL_SYNTH_CLOCK_SPEED[1]
    DCM1:DRP44[5]    		DCM1:DLL_SYNTH_CLOCK_SPEED[0]
    DCM1:DRP44[4]
    35----------------------------DCM1:DFS_SYNTH_CLOCK_SPEED[0]
    DCM1:DRP44[6]    		DCM1:DFS_SYNTH_CLOCK_SPEED[1]
    DCM1:DRP44[7]
    36----------------------------DCM1:DCM_WAIT_PLL
    DCM1:DRP44[9]    		DCM1:DFS_SYNTH_CLOCK_SPEED[2]
    DCM1:DRP44[8]
    37----------------------------DCM1:CLKIN_DIVIDE_BY_2
    DCM1:DRP44[10]    		DCM1:DCM_CLKIN_IODLY_MUXINSEL
    DCM1:DRP44[11]
    38----------------------------DCM1:DFS_SYNC_TO_DLL
    DCM1:DRP44[13]    		DCM1:DCM_CLKFB_IODLY_MUXINSEL
    DCM1:DRP44[12]
    39----------------------------DCM1:DFS_EN
    DCM1:DRP44[14]    		DCM1:DFS_FAST_UPDATE
    DCM1:DRP44[15]
    40----------------------------DCM1:DFS_TAPTRIM[1]
    DCM1:DRP45[1]    		DCM1:DFS_TAPTRIM[0]
    DCM1:DRP45[0]
    41----------------------------DCM1:DFS_TAPTRIM[2]
    DCM1:DRP45[2]    		DCM1:DFS_TAPTRIM[3]
    DCM1:DRP45[3]
    42----------------------------DCM1:DFS_TAPTRIM[5]
    DCM1:DRP45[5]    		DCM1:DFS_TAPTRIM[4]
    DCM1:DRP45[4]
    43----------------------------DCM1:DFS_TAPTRIM[6]
    DCM1:DRP45[6]    		DCM1:DFS_TAPTRIM[7]
    DCM1:DRP45[7]
    44----------------------------DCM1:DFS_TAPTRIM[9]
    DCM1:DRP45[9]    		DCM1:DFS_TAPTRIM[8]
    DCM1:DRP45[8]
    45----------------------------DCM1:DFS_TAPTRIM[10]
    DCM1:DRP45[10]    		DCM1:DRP45[11]
    46----------------------------DCM1:DRP45[13]DCM1:DRP45[12]
    47----------------------------DCM1:DRP45[14]DCM1:DRP45[15]
    48----------------------------DCM1:DFS_TWEAK[1]
    DCM1:DRP46[1]    		DCM1:DFS_TWEAK[0]
    DCM1:DRP46[0]
    49----------------------------DCM1:DFS_TWEAK[2]
    DCM1:DRP46[2]    		DCM1:DFS_TWEAK[3]
    DCM1:DRP46[3]
    50----------------------------DCM1:DFS_TWEAK[5]
    DCM1:DRP46[5]    		DCM1:DFS_TWEAK[4]
    DCM1:DRP46[4]
    51----------------------------DCM1:DFS_TWEAK[6]
    DCM1:DRP46[6]    		DCM1:DFS_TWEAK[7]
    DCM1:DRP46[7]
    52----------------------------DCM1:DRP46[9]DCM1:DRP46[8]
    53----------------------------DCM1:DRP46[10]DCM1:DRP46[11]
    54----------------------------DCM1:DRP46[13]DCM1:DRP46[12]
    55----------------------------DCM1:DRP46[14]DCM1:DRP46[15]
    56----------------------------DCM1:DRP47[1]
    DCM1:ENABLE.CLKFX180    		DCM1:DRP47[0]
    DCM1:ENABLE.CLKFX
    57----------------------------DCM1:DRP47[2]
    DCM1:ENABLE.CONCUR    		DCM1:DFS_OUTPUT_PSDLY_ON_CONCUR
    DCM1:DRP47[3]
    58----------------------------DCM1:DCM_UNUSED_TAPS_POWERDOWN[0]
    DCM1:DRP47[5]    		~DCM1:DFS_EN_RELRST_B
    DCM1:DRP47[4]
    59----------------------------DCM1:DFS_MPW_LOW
    DCM1:DRP47[6]    		DCM1:DFS_MPW_HIGH
    DCM1:DRP47[7]
    60----------------------------DCM1:DFS_CUSTOM_FAST_SYNC[0]
    DCM1:DRP47[9]    		DCM1:DCM_CLKDV_CLKFX_ALIGNMENT
    DCM1:DRP47[8]
    61----------------------------DCM1:DFS_CUSTOM_FAST_SYNC[1]
    DCM1:DRP47[10]    		DCM1:DFS_CUSTOM_FAST_SYNC[2]
    DCM1:DRP47[11]
    62----------------------------DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[0]
    DCM1:DRP47[13]    		DCM1:DFS_CUSTOM_FAST_SYNC[3]
    DCM1:DRP47[12]
    63----------------------------DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[1]
    DCM1:DRP47[14]    		DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[2]
    DCM1:DRP47[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 8
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM1:DRP48[1]
    DCM1:MUX.CLKIN[1]    		DCM1:DRP48[0]
    DCM1:MUX.CLKIN[0]
    1----------------------------DCM1:DRP48[2]
    DCM1:MUX.CLKIN[2]    		DCM1:DRP48[3]
    DCM1:MUX.CLKIN[3]
    2----------------------------DCM1:DRP48[5]
    DCM1:MUX.CLKFB[0]    		DCM1:DRP48[4]
    DCM1:MUX.CLKIN[4]
    3----------------------------DCM1:DRP48[6]
    DCM1:MUX.CLKFB[1]    		DCM1:DRP48[7]
    DCM1:MUX.CLKFB[2]
    4----------------------------DCM1:DRP48[9]
    DCM1:MUX.CLKFB[4]    		DCM1:DRP48[8]
    DCM1:MUX.CLKFB[3]
    5----------------------------DCM1:DRP48[10]
    DCM1:MUX.CLK_TO_PLL[0]    		DCM1:DRP48[11]
    DCM1:MUX.CLK_TO_PLL[1]
    6----------------------------DCM1:DRP48[13]
    DCM1:MUX.CLK_TO_PLL[3]    		DCM1:DRP48[12]
    DCM1:MUX.CLK_TO_PLL[2]
    7----------------------------DCM1:DRP48[14]
    DCM1:INV.SKEWCLKIN1    		DCM1:DRP48[15]
    DCM1:INV.SKEWCLKIN2
    8----------------------------DCM1:DRP49[1]
    DCM1:MUX.SKEWCLKIN2[1]    		DCM1:DRP49[0]
    DCM1:MUX.SKEWCLKIN2[0]
    9----------------------------DCM1:DRP49[2]
    DCM1:MUX.SKEWCLKIN2[2]    		DCM1:DRP49[3]
    DCM1:MUX.SKEWCLKIN2[3]
    10----------------------------DCM1:DRP49[5]
    DCM1:INV.SKEWRST    		DCM1:DRP49[4]
    DCM1:INV.SKEWIN
    11----------------------------DCM1:CLKIN_CLKFB_ENABLE
    DCM1:DRP49[6]    		DCM1:DRP49[7]
    12----------------------------DCM1:DRP49[9]DCM1:DRP49[8]
    13----------------------------DCM1:DRP49[10]DCM1:DRP49[11]
    14----------------------------DCM1:DRP49[13]DCM1:DRP49[12]
    15----------------------------DCM1:DRP49[14]DCM1:DCM_REG_PWRD_CFG
    DCM1:DRP49[15]
    16----------------------------DCM1:DRP4A[1]DCM1:DRP4A[0]
    17----------------------------DCM1:DRP4A[2]DCM1:DRP4A[3]
    18----------------------------DCM1:DRP4A[5]DCM1:DRP4A[4]
    19----------------------------DCM1:DRP4A[6]DCM1:DRP4A[7]
    20----------------------------DCM1:DRP4A[9]DCM1:DRP4A[8]
    21----------------------------DCM1:DRP4A[10]DCM1:DRP4A[11]
    22----------------------------DCM1:DRP4A[13]DCM1:DRP4A[12]
    23----------------------------DCM1:DRP4A[14]DCM1:DRP4A[15]
    24----------------------------DCM1:DLL_PHASE_SHIFT_CALIBRATION[1]
    DCM1:DRP4B[1]    		DCM1:DLL_PHASE_SHIFT_CALIBRATION[0]
    DCM1:DRP4B[0]
    25----------------------------DCM1:DRP4B[2]
    DCM1:PS_CENTERED    		DCM1:DRP4B[3]
    DCM1:PS_DIRECT
    26----------------------------DCM1:DRP4B[5]
    DCM1:INV.RST    		DCM1:DLL_PHASE_SHIFT_LOCK_BY1
    DCM1:DRP4B[4]
    27----------------------------DCM1:DRP4B[6]
    DCM1:INV.PSINCDEC    		DCM1:DRP4B[7]
    DCM1:INV.PSEN
    28----------------------------DCM1:DRP4B[9]DCM1:DRP4B[8]
    29----------------------------DCM1:DRP4B[10]DCM1:DRP4B[11]
    30----------------------------DCM1:DRP4B[13]DCM1:DRP4B[12]
    31----------------------------DCM1:DRP4B[14]DCM1:DRP4B[15]
    32----------------------------DCM1:DCM_SCANMODE
    DCM1:DRP4C[1]    		DCM1:DCM_UNUSED_TAPS_POWERDOWN[2]
    DCM1:DRP4C[0]
    33----------------------------DCM1:DLL_TAPINIT_CTL[0]
    DCM1:DRP4C[2]    		DCM1:DLL_TAPINIT_CTL[1]
    DCM1:DRP4C[3]
    34----------------------------DCM1:DRP4C[5]DCM1:DLL_TAPINIT_CTL[2]
    DCM1:DRP4C[4]
    35----------------------------~DCM1:DLL_PWRD_ON_SCANMODE_B
    DCM1:DRP4C[6]    		DCM1:DLL_ZD1_PHASE_SEL_INIT[0]
    DCM1:DRP4C[7]
    36----------------------------DCM1:DLL_PERIOD_LOCK_BY1
    DCM1:DRP4C[9]    		DCM1:DLL_ZD1_PHASE_SEL_INIT[1]
    DCM1:DRP4C[8]
    37----------------------------DCM1:DLL_DESKEW_LOCK_BY1
    DCM1:DRP4C[10]    		DCM1:DLL_ZD2_JF_OVERFLOW_HOLD
    DCM1:DRP4C[11]
    38----------------------------DCM1:DLL_ZD1_JF_OVERFLOW_HOLD
    DCM1:DRP4C[13]    		DCM1:DCM_UNUSED_TAPS_POWERDOWN[3]
    DCM1:DRP4C[12]
    39----------------------------DCM1:DCM_UNUSED_TAPS_POWERDOWN[1]
    DCM1:DRP4C[14]    		DCM1:DRP4C[15]
    40----------------------------DCM1:DLL_ZD2_TAP_INIT[1]
    DCM1:DRP4D[1]    		DCM1:DLL_ZD2_TAP_INIT[0]
    DCM1:DRP4D[0]
    41----------------------------DCM1:DLL_ZD2_TAP_INIT[2]
    DCM1:DRP4D[2]    		DCM1:DLL_ZD2_TAP_INIT[3]
    DCM1:DRP4D[3]
    42----------------------------DCM1:DLL_ZD2_TAP_INIT[5]
    DCM1:DRP4D[5]    		DCM1:DLL_ZD2_TAP_INIT[4]
    DCM1:DRP4D[4]
    43----------------------------DCM1:DLL_ZD2_TAP_INIT[6]
    DCM1:DRP4D[6]    		DCM1:DRP4D[7]
    44----------------------------DCM1:DLL_ZD1_TAP_INIT[1]
    DCM1:DRP4D[9]    		DCM1:DLL_ZD1_TAP_INIT[0]
    DCM1:DRP4D[8]
    45----------------------------DCM1:DLL_ZD1_TAP_INIT[2]
    DCM1:DRP4D[10]    		DCM1:DLL_ZD1_TAP_INIT[3]
    DCM1:DRP4D[11]
    46----------------------------DCM1:DLL_ZD1_TAP_INIT[5]
    DCM1:DRP4D[13]    		DCM1:DLL_ZD1_TAP_INIT[4]
    DCM1:DRP4D[12]
    47----------------------------DCM1:DLL_ZD1_TAP_INIT[6]
    DCM1:DRP4D[14]    		DCM1:DLL_ZD1_TAP_INIT[7]
    DCM1:DRP4D[15]
    48----------------------------DCM1:DLL_DESKEW_MINTAP[1]
    DCM1:DRP4E[1]    		DCM1:DLL_DESKEW_MINTAP[0]
    DCM1:DRP4E[0]
    49----------------------------DCM1:DLL_DESKEW_MINTAP[2]
    DCM1:DRP4E[2]    		DCM1:DLL_DESKEW_MINTAP[3]
    DCM1:DRP4E[3]
    50----------------------------DCM1:DLL_DESKEW_MINTAP[5]
    DCM1:DRP4E[5]    		DCM1:DLL_DESKEW_MINTAP[4]
    DCM1:DRP4E[4]
    51----------------------------DCM1:DLL_DESKEW_MINTAP[6]
    DCM1:DRP4E[6]    		DCM1:DLL_DESKEW_MINTAP[7]
    DCM1:DRP4E[7]
    52----------------------------DCM1:DLL_DESKEW_MAXTAP[1]
    DCM1:DRP4E[9]    		DCM1:DLL_DESKEW_MAXTAP[0]
    DCM1:DRP4E[8]
    53----------------------------DCM1:DLL_DESKEW_MAXTAP[2]
    DCM1:DRP4E[10]    		DCM1:DLL_DESKEW_MAXTAP[3]
    DCM1:DRP4E[11]
    54----------------------------DCM1:DLL_DESKEW_MAXTAP[5]
    DCM1:DRP4E[13]    		DCM1:DLL_DESKEW_MAXTAP[4]
    DCM1:DRP4E[12]
    55----------------------------DCM1:DLL_DESKEW_MAXTAP[6]
    DCM1:DRP4E[14]    		DCM1:DLL_DESKEW_MAXTAP[7]
    DCM1:DRP4E[15]
    56----------------------------DCM1:DRP4F[1]
    DCM1:FACTORY_JF[1]    		DCM1:DRP4F[0]
    DCM1:FACTORY_JF[0]
    57----------------------------DCM1:DRP4F[2]
    DCM1:FACTORY_JF[2]    		DCM1:DRP4F[3]
    DCM1:FACTORY_JF[3]
    58----------------------------DCM1:DRP4F[5]
    DCM1:FACTORY_JF[5]    		DCM1:DRP4F[4]
    DCM1:FACTORY_JF[4]
    59----------------------------DCM1:DRP4F[6]
    DCM1:FACTORY_JF[6]    		DCM1:DRP4F[7]
    DCM1:FACTORY_JF[7]
    60----------------------------DCM1:DRP4F[9]
    DCM1:FACTORY_JF[9]    		DCM1:DRP4F[8]
    DCM1:FACTORY_JF[8]
    61----------------------------DCM1:DRP4F[10]
    DCM1:FACTORY_JF[10]    		DCM1:DRP4F[11]
    DCM1:FACTORY_JF[11]
    62----------------------------DCM1:DRP4F[13]
    DCM1:FACTORY_JF[13]    		DCM1:DRP4F[12]
    DCM1:FACTORY_JF[12]
    63----------------------------DCM1:DRP4F[14]
    DCM1:FACTORY_JF[14]    		DCM1:DRP4F[15]
    DCM1:FACTORY_JF[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 9
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------DCM1:CLKFX_DIVIDE[1]
    DCM1:DRP50[1]    		DCM1:CLKFX_DIVIDE[0]
    DCM1:DRP50[0]
    1----------------------------DCM1:CLKFX_DIVIDE[2]
    DCM1:DRP50[2]    		DCM1:CLKFX_DIVIDE[3]
    DCM1:DRP50[3]
    2----------------------------DCM1:CLKFX_DIVIDE[5]
    DCM1:DRP50[5]    		DCM1:CLKFX_DIVIDE[4]
    DCM1:DRP50[4]
    3----------------------------DCM1:CLKFX_DIVIDE[6]
    DCM1:DRP50[6]    		DCM1:CLKFX_DIVIDE[7]
    DCM1:DRP50[7]
    4----------------------------DCM1:CLKFX_MULTIPLY[1]
    DCM1:DRP50[9]    		DCM1:CLKFX_MULTIPLY[0]
    DCM1:DRP50[8]
    5----------------------------DCM1:CLKFX_MULTIPLY[2]
    DCM1:DRP50[10]    		DCM1:CLKFX_MULTIPLY[3]
    DCM1:DRP50[11]
    6----------------------------DCM1:CLKFX_MULTIPLY[5]
    DCM1:DRP50[13]    		DCM1:CLKFX_MULTIPLY[4]
    DCM1:DRP50[12]
    7----------------------------DCM1:CLKFX_MULTIPLY[6]
    DCM1:DRP50[14]    		DCM1:CLKFX_MULTIPLY[7]
    DCM1:DRP50[15]
    8----------------------------~DCM1:DLL_CLKIN_STOPPED_PWRD_EN_B
    DCM1:DRP51[1]    		~DCM1:DLL_CLKFB_STOPPED_PWRD_EN_B
    DCM1:DRP51[0]
    9----------------------------DCM1:DLL_FREQUENCY_MODE[0]
    DCM1:DRP51[2]    		DCM1:DLL_FREQUENCY_MODE[1]
    DCM1:DRP51[3]
    10----------------------------DCM1:DLL_ZD2_EN
    DCM1:DRP51[5]    		DCM1:DRP51[4]
    DCM1:PS_MODE
    11----------------------------DCM1:DLL_ZD1_EN
    DCM1:DRP51[6]    		DCM1:DRP51[7]
    DCM1:PS_ENABLE
    12----------------------------DCM1:DLL_SETTLE_TIME[1]
    DCM1:DRP51[9]    		DCM1:DLL_SETTLE_TIME[0]
    DCM1:DRP51[8]
    13----------------------------DCM1:DLL_SETTLE_TIME[2]
    DCM1:DRP51[10]    		DCM1:DLL_SETTLE_TIME[3]
    DCM1:DRP51[11]
    14----------------------------DCM1:DLL_SETTLE_TIME[5]
    DCM1:DRP51[13]    		DCM1:DLL_SETTLE_TIME[4]
    DCM1:DRP51[12]
    15----------------------------DCM1:DLL_SETTLE_TIME[6]
    DCM1:DRP51[14]    		DCM1:DLL_SETTLE_TIME[7]
    DCM1:DRP51[15]
    16----------------------------DCM1:DLL_LIVE_TIME[1]
    DCM1:DRP52[1]    		DCM1:DLL_LIVE_TIME[0]
    DCM1:DRP52[0]
    17----------------------------DCM1:DLL_LIVE_TIME[2]
    DCM1:DRP52[2]    		DCM1:DLL_LIVE_TIME[3]
    DCM1:DRP52[3]
    18----------------------------DCM1:DLL_LIVE_TIME[5]
    DCM1:DRP52[5]    		DCM1:DLL_LIVE_TIME[4]
    DCM1:DRP52[4]
    19----------------------------DCM1:DLL_LIVE_TIME[6]
    DCM1:DRP52[6]    		DCM1:DLL_LIVE_TIME[7]
    DCM1:DRP52[7]
    20----------------------------DCM1:DLL_DEAD_TIME[1]
    DCM1:DRP52[9]    		DCM1:DLL_DEAD_TIME[0]
    DCM1:DRP52[8]
    21----------------------------DCM1:DLL_DEAD_TIME[2]
    DCM1:DRP52[10]    		DCM1:DLL_DEAD_TIME[3]
    DCM1:DRP52[11]
    22----------------------------DCM1:DLL_DEAD_TIME[5]
    DCM1:DRP52[13]    		DCM1:DLL_DEAD_TIME[4]
    DCM1:DRP52[12]
    23----------------------------DCM1:DLL_DEAD_TIME[6]
    DCM1:DRP52[14]    		DCM1:DLL_DEAD_TIME[7]
    DCM1:DRP52[15]
    24----------------------------DCM1:CLKDV_COUNT_MAX[1]
    DCM1:DRP53[1]    		DCM1:CLKDV_COUNT_MAX[0]
    DCM1:DRP53[0]
    25----------------------------DCM1:CLKDV_COUNT_MAX[2]
    DCM1:DRP53[2]    		DCM1:CLKDV_COUNT_MAX[3]
    DCM1:DRP53[3]
    26----------------------------DCM1:CLKDV_COUNT_FALL[1]
    DCM1:DRP53[5]    		DCM1:CLKDV_COUNT_FALL[0]
    DCM1:DRP53[4]
    27----------------------------DCM1:CLKDV_COUNT_FALL[2]
    DCM1:DRP53[6]    		DCM1:CLKDV_COUNT_FALL[3]
    DCM1:DRP53[7]
    28----------------------------DCM1:CLKDV_COUNT_FALL_2[1]
    DCM1:DRP53[9]    		DCM1:CLKDV_COUNT_FALL_2[0]
    DCM1:DRP53[8]
    29----------------------------DCM1:CLKDV_COUNT_FALL_2[2]
    DCM1:DRP53[10]    		DCM1:CLKDV_COUNT_FALL_2[3]
    DCM1:DRP53[11]
    30----------------------------DCM1:CLKDV_PHASE_RISE[1]
    DCM1:DRP53[13]    		DCM1:CLKDV_PHASE_RISE[0]
    DCM1:DRP53[12]
    31----------------------------DCM1:CLKDV_PHASE_FALL[0]
    DCM1:DRP53[14]    		DCM1:CLKDV_PHASE_FALL[1]
    DCM1:DRP53[15]
    32----------------------------DCM1:DLL_FDBKLOST_EN
    DCM1:DRP54[1]    		DCM1:CLKDV_MODE
    DCM1:DRP54[0]
    33----------------------------DCM1:DCM_CLKLOST_EN
    DCM1:DRP54[2]    		~DCM1:DCM_LOCK_HIGH_B
    DCM1:DRP54[3]
    34----------------------------DCM1:DRP54[5]
    DCM1:ENABLE.CLK90    		DCM1:DRP54[4]
    DCM1:ENABLE.CLK0
    35----------------------------DCM1:DRP54[6]
    DCM1:ENABLE.CLK180    		DCM1:DRP54[7]
    DCM1:ENABLE.CLK270
    36----------------------------DCM1:DRP54[9]
    DCM1:ENABLE.CLK2X180    		DCM1:DRP54[8]
    DCM1:ENABLE.CLK2X
    37----------------------------DCM1:DRP54[10]
    DCM1:ENABLE.CLKDV    		DCM1:DCM_TRIM_CAL[0]
    DCM1:DRP54[11]
    38----------------------------DCM1:DCM_TRIM_CAL[2]
    DCM1:DRP54[13]    		DCM1:DCM_TRIM_CAL[1]
    DCM1:DRP54[12]
    39----------------------------DCM1:DLL_TEST_MUX_SEL[0]
    DCM1:DRP54[14]    		DCM1:DLL_TEST_MUX_SEL[1]
    DCM1:DRP54[15]
    40----------------------------DCM1:DRP55[1]
    DCM1:PHASE_SHIFT[1]    		DCM1:DRP55[0]
    DCM1:PHASE_SHIFT[0]
    41----------------------------DCM1:DRP55[2]
    DCM1:PHASE_SHIFT[2]    		DCM1:DRP55[3]
    DCM1:PHASE_SHIFT[3]
    42----------------------------DCM1:DRP55[5]
    DCM1:PHASE_SHIFT[5]    		DCM1:DRP55[4]
    DCM1:PHASE_SHIFT[4]
    43----------------------------DCM1:DRP55[6]
    DCM1:PHASE_SHIFT[6]    		DCM1:DRP55[7]
    DCM1:PHASE_SHIFT[7]
    44----------------------------DCM1:DRP55[9]
    DCM1:PHASE_SHIFT[9]    		DCM1:DRP55[8]
    DCM1:PHASE_SHIFT[8]
    45----------------------------DCM1:DRP55[10]
    DCM1:PHASE_SHIFT_NEGATIVE    		DCM1:DRP55[11]
    46----------------------------DCM1:DRP55[13]DCM1:DRP55[12]
    47----------------------------DCM1:DRP55[14]DCM1:DRP55[15]
    48----------------------------DCM1:DLL_PHASE_SHIFT_LFC[1]
    DCM1:DRP56[1]    		DCM1:DLL_PHASE_SHIFT_LFC[0]
    DCM1:DRP56[0]
    49----------------------------DCM1:DLL_PHASE_SHIFT_LFC[2]
    DCM1:DRP56[2]    		DCM1:DLL_PHASE_SHIFT_LFC[3]
    DCM1:DRP56[3]
    50----------------------------DCM1:DLL_PHASE_SHIFT_LFC[5]
    DCM1:DRP56[5]    		DCM1:DLL_PHASE_SHIFT_LFC[4]
    DCM1:DRP56[4]
    51----------------------------DCM1:DLL_PHASE_SHIFT_LFC[6]
    DCM1:DRP56[6]    		DCM1:DLL_PHASE_SHIFT_LFC[7]
    DCM1:DRP56[7]
    52----------------------------DCM1:DLL_ZD2_PWC_TAP[0]
    DCM1:DRP56[9]    		DCM1:DLL_PHASE_SHIFT_LFC[8]
    DCM1:DRP56[8]
    53----------------------------DCM1:DLL_ZD2_PWC_TAP[1]
    DCM1:DRP56[10]    		DCM1:DLL_ZD2_PWC_TAP[2]
    DCM1:DRP56[11]
    54----------------------------DCM1:DLL_ZD1_PWC_TAP[1]
    DCM1:DRP56[13]    		DCM1:DLL_ZD1_PWC_TAP[0]
    DCM1:DRP56[12]
    55----------------------------DCM1:DLL_ZD1_PWC_TAP[2]
    DCM1:DRP56[14]    		DCM1:DCM_VREG_ENABLE
    DCM1:DRP56[15]
    56----------------------------DCM1:DLL_ZD1_PWC_EN
    DCM1:DRP57[1]    		DCM1:DCM_VSPLY_VALID_ACC[0]
    DCM1:DRP57[0]
    57----------------------------DCM1:DRP57[2]
    DCM1:STARTUP_WAIT    		DCM1:DCM_VBG_SEL[0]
    DCM1:DRP57[3]
    58----------------------------DCM1:DLL_ETPP_HOLD
    DCM1:DRP57[5]    		DCM1:DCM_VBG_SEL[1]
    DCM1:DRP57[4]
    59----------------------------~DCM1:DLL_PWRD_STICKY_B
    DCM1:DRP57[6]    		DCM1:DCM_VBG_SEL[2]
    DCM1:DRP57[7]
    60----------------------------DCM1:DLL_ZD2_PWC_EN
    DCM1:DRP57[9]    		DCM1:DCM_VBG_SEL[3]
    DCM1:DRP57[8]
    61----------------------------~DCM1:DCM_POWERDOWN_COMMON_EN_B
    DCM1:DRP57[10]    		DCM1:DCM_VBG_PD[0]
    DCM1:DRP57[11]
    62----------------------------DCM1:DCM_COMMON_MSB_SEL[0]
    DCM1:DRP57[13]    		DCM1:DCM_VBG_PD[1]
    DCM1:DRP57[12]
    63----------------------------DCM1:DCM_COMMON_MSB_SEL[1]
    DCM1:DRP57[14]    		DCM1:DCM_VSPLY_VALID_ACC[1]
    DCM1:DRP57[15]
    +
    +
    + + + + + +
    DCM0:DFS_OSCILLATOR_MODE[0, 28, 8]
    DCM1:DFS_OSCILLATOR_MODE[7, 28, 8]
    PHASE_FREQ_LOCK0
    AVE_FREQ_LOCK1
    +
    +
    + + + + + +
    DCM0:DFS_FREQUENCY_MODE[0, 28, 9]
    DCM1:DFS_FREQUENCY_MODE[7, 28, 9]
    LOW0
    HIGH1
    +
    +
    + + + + + + + + + + +
    DCM0:DFS_AVE_FREQ_GAIN[0, 29, 12][0, 29, 11][0, 28, 11]
    DCM1:DFS_AVE_FREQ_GAIN[7, 29, 12][7, 29, 11][7, 28, 11]
    0.125001
    0.25010
    0.5011
    1.0100
    2.0101
    4.0110
    8.0111
    +
    +
    +
    +
    +
    +
    +
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    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:CLKIN_CLKFB_ENABLE[1, 28, 11]
    DCM0:CLKIN_DIVIDE_BY_2[0, 28, 37]
    DCM0:DCM_CLKDV_CLKFX_ALIGNMENT[0, 29, 60]
    DCM0:DCM_CLKLOST_EN[2, 28, 33]
    DCM0:DCM_COM_PWC_FB_EN[0, 28, 32]
    DCM0:DCM_COM_PWC_REF_EN[0, 29, 32]
    DCM0:DCM_EXT_FB_EN[0, 28, 33]
    DCM0:DCM_PLL_RST_DCM[0, 28, 28]
    DCM0:DCM_REG_PWRD_CFG[1, 29, 15]
    DCM0:DCM_SCANMODE[1, 28, 32]
    DCM0:DCM_USE_REG_READY[0, 29, 33]
    DCM0:DCM_VREG_ENABLE[2, 29, 55]
    DCM0:DCM_WAIT_PLL[0, 28, 36]
    DCM0:DFS_CFG_BYPASS[0, 29, 9]
    DCM0:DFS_EARLY_LOCK[0, 28, 12]
    DCM0:DFS_EN[0, 28, 39]
    DCM0:DFS_FAST_UPDATE[0, 29, 39]
    DCM0:DFS_MPW_HIGH[0, 29, 59]
    DCM0:DFS_MPW_LOW[0, 28, 59]
    DCM0:DFS_OSC_ON_FX[0, 29, 19]
    DCM0:DFS_OUTPUT_PSDLY_ON_CONCUR[0, 29, 57]
    DCM0:DFS_REF_ON_FX[0, 29, 20]
    DCM0:DFS_SYNC_TO_DLL[0, 28, 38]
    DCM0:DLL_DESKEW_LOCK_BY1[1, 28, 37]
    DCM0:DLL_ETPP_HOLD[2, 28, 58]
    DCM0:DLL_FDBKLOST_EN[2, 28, 32]
    DCM0:DLL_PERIOD_LOCK_BY1[1, 28, 36]
    DCM0:DLL_PHASE_SHIFT_LOCK_BY1[1, 29, 26]
    DCM0:DLL_ZD1_EN[2, 28, 11]
    DCM0:DLL_ZD1_JF_OVERFLOW_HOLD[1, 28, 38]
    DCM0:DLL_ZD1_PWC_EN[2, 28, 56]
    DCM0:DLL_ZD2_EN[2, 28, 10]
    DCM0:DLL_ZD2_JF_OVERFLOW_HOLD[1, 29, 37]
    DCM0:DLL_ZD2_PWC_EN[2, 28, 60]
    DCM0:ENABLE.CLK0[2, 29, 34]
    DCM0:ENABLE.CLK180[2, 28, 35]
    DCM0:ENABLE.CLK270[2, 29, 35]
    DCM0:ENABLE.CLK2X[2, 29, 36]
    DCM0:ENABLE.CLK2X180[2, 28, 36]
    DCM0:ENABLE.CLK90[2, 28, 34]
    DCM0:ENABLE.CLKDV[2, 28, 37]
    DCM0:ENABLE.CLKFX[0, 29, 56]
    DCM0:ENABLE.CLKFX180[0, 28, 56]
    DCM0:ENABLE.CONCUR[0, 28, 57]
    DCM0:INV.PSEN[1, 29, 27]
    DCM0:INV.PSINCDEC[1, 28, 27]
    DCM0:INV.RST[1, 28, 26]
    DCM0:INV.SKEWCLKIN1[1, 28, 7]
    DCM0:INV.SKEWCLKIN2[1, 29, 7]
    DCM0:INV.SKEWIN[1, 29, 10]
    DCM0:INV.SKEWRST[1, 28, 10]
    DCM0:PHASE_SHIFT_NEGATIVE[2, 28, 45]
    DCM0:PS_CENTERED[1, 28, 25]
    DCM0:PS_DIRECT[1, 29, 25]
    DCM0:PS_ENABLE[2, 29, 11]
    DCM0:STARTUP_WAIT[2, 28, 57]
    DCM1:CLKIN_CLKFB_ENABLE[8, 28, 11]
    DCM1:CLKIN_DIVIDE_BY_2[7, 28, 37]
    DCM1:DCM_CLKDV_CLKFX_ALIGNMENT[7, 29, 60]
    DCM1:DCM_CLKLOST_EN[9, 28, 33]
    DCM1:DCM_COM_PWC_FB_EN[7, 28, 32]
    DCM1:DCM_COM_PWC_REF_EN[7, 29, 32]
    DCM1:DCM_EXT_FB_EN[7, 28, 33]
    DCM1:DCM_PLL_RST_DCM[7, 28, 28]
    DCM1:DCM_REG_PWRD_CFG[8, 29, 15]
    DCM1:DCM_SCANMODE[8, 28, 32]
    DCM1:DCM_USE_REG_READY[7, 29, 33]
    DCM1:DCM_VREG_ENABLE[9, 29, 55]
    DCM1:DCM_WAIT_PLL[7, 28, 36]
    DCM1:DFS_CFG_BYPASS[7, 29, 9]
    DCM1:DFS_EARLY_LOCK[7, 28, 12]
    DCM1:DFS_EN[7, 28, 39]
    DCM1:DFS_FAST_UPDATE[7, 29, 39]
    DCM1:DFS_MPW_HIGH[7, 29, 59]
    DCM1:DFS_MPW_LOW[7, 28, 59]
    DCM1:DFS_OSC_ON_FX[7, 29, 19]
    DCM1:DFS_OUTPUT_PSDLY_ON_CONCUR[7, 29, 57]
    DCM1:DFS_REF_ON_FX[7, 29, 20]
    DCM1:DFS_SYNC_TO_DLL[7, 28, 38]
    DCM1:DLL_DESKEW_LOCK_BY1[8, 28, 37]
    DCM1:DLL_ETPP_HOLD[9, 28, 58]
    DCM1:DLL_FDBKLOST_EN[9, 28, 32]
    DCM1:DLL_PERIOD_LOCK_BY1[8, 28, 36]
    DCM1:DLL_PHASE_SHIFT_LOCK_BY1[8, 29, 26]
    DCM1:DLL_ZD1_EN[9, 28, 11]
    DCM1:DLL_ZD1_JF_OVERFLOW_HOLD[8, 28, 38]
    DCM1:DLL_ZD1_PWC_EN[9, 28, 56]
    DCM1:DLL_ZD2_EN[9, 28, 10]
    DCM1:DLL_ZD2_JF_OVERFLOW_HOLD[8, 29, 37]
    DCM1:DLL_ZD2_PWC_EN[9, 28, 60]
    DCM1:ENABLE.CLK0[9, 29, 34]
    DCM1:ENABLE.CLK180[9, 28, 35]
    DCM1:ENABLE.CLK270[9, 29, 35]
    DCM1:ENABLE.CLK2X[9, 29, 36]
    DCM1:ENABLE.CLK2X180[9, 28, 36]
    DCM1:ENABLE.CLK90[9, 28, 34]
    DCM1:ENABLE.CLKDV[9, 28, 37]
    DCM1:ENABLE.CLKFX[7, 29, 56]
    DCM1:ENABLE.CLKFX180[7, 28, 56]
    DCM1:ENABLE.CONCUR[7, 28, 57]
    DCM1:INV.PSEN[8, 29, 27]
    DCM1:INV.PSINCDEC[8, 28, 27]
    DCM1:INV.RST[8, 28, 26]
    DCM1:INV.SKEWCLKIN1[8, 28, 7]
    DCM1:INV.SKEWCLKIN2[8, 29, 7]
    DCM1:INV.SKEWIN[8, 29, 10]
    DCM1:INV.SKEWRST[8, 28, 10]
    DCM1:PHASE_SHIFT_NEGATIVE[9, 28, 45]
    DCM1:PS_CENTERED[8, 28, 25]
    DCM1:PS_DIRECT[8, 29, 25]
    DCM1:PS_ENABLE[9, 29, 11]
    DCM1:STARTUP_WAIT[9, 28, 57]
    PLL:CLKINSEL_STATIC[6, 29, 50]
    PLL:INV.CLKBRST[6, 29, 42]
    PLL:INV.ENOUTSYNC[6, 28, 42]
    PLL:INV.MANPDLF[6, 28, 40]
    PLL:INV.MANPULF[6, 28, 41]
    PLL:INV.REL[6, 29, 41]
    PLL:INV.RST[6, 29, 40]
    PLL:INV.SKEWCLKIN1[6, 29, 46]
    PLL:INV.SKEWCLKIN2[6, 28, 46]
    PLL:INV.SKEWRST[6, 29, 47]
    PLL:INV.SKEWSTB[6, 28, 47]
    PLL:PLL_CLKBURST_ENABLE[6, 29, 6]
    PLL:PLL_CLKFBOUT2_EDGE[4, 29, 19]
    PLL:PLL_CLKFBOUT2_NOCOUNT[4, 28, 19]
    PLL:PLL_CLKFBOUT_EDGE[4, 29, 43]
    PLL:PLL_CLKFBOUT_EN[4, 29, 38]
    PLL:PLL_CLKFBOUT_NOCOUNT[4, 28, 43]
    PLL:PLL_CLKOUT0_EDGE[6, 29, 35]
    PLL:PLL_CLKOUT0_EN[6, 29, 30]
    PLL:PLL_CLKOUT0_NOCOUNT[6, 28, 35]
    PLL:PLL_CLKOUT1_EDGE[6, 29, 19]
    PLL:PLL_CLKOUT1_EN[6, 29, 14]
    PLL:PLL_CLKOUT1_NOCOUNT[6, 28, 19]
    PLL:PLL_CLKOUT2_EDGE[5, 29, 59]
    PLL:PLL_CLKOUT2_EN[5, 29, 54]
    PLL:PLL_CLKOUT2_NOCOUNT[5, 28, 59]
    PLL:PLL_CLKOUT3_EDGE[5, 29, 43]
    PLL:PLL_CLKOUT3_EN[5, 29, 38]
    PLL:PLL_CLKOUT3_NOCOUNT[5, 28, 43]
    PLL:PLL_CLKOUT4_EDGE[5, 29, 27]
    PLL:PLL_CLKOUT4_EN[5, 29, 22]
    PLL:PLL_CLKOUT4_NOCOUNT[5, 28, 27]
    PLL:PLL_CLKOUT5_EDGE[4, 29, 59]
    PLL:PLL_CLKOUT5_EN[4, 29, 54]
    PLL:PLL_CLKOUT5_NOCOUNT[4, 28, 59]
    PLL:PLL_CP_BIAS_TRIP_SHIFT[3, 28, 7]
    PLL:PLL_DIRECT_PATH_CNTRL[6, 29, 0]
    PLL:PLL_DIVCLK_EDGE[3, 28, 54]
    PLL:PLL_DIVCLK_NOCOUNT[3, 29, 54]
    PLL:PLL_EN[5, 29, 15]
    PLL:PLL_EN_DLY[3, 28, 60]
    PLL:PLL_EN_TCLK0[3, 28, 37]
    PLL:PLL_EN_TCLK1[3, 29, 37]
    PLL:PLL_EN_TCLK2[3, 29, 38]
    PLL:PLL_EN_TCLK3[3, 28, 38]
    PLL:PLL_EN_TCLK4[3, 28, 39]
    PLL:PLL_EN_VCO0[6, 29, 1]
    PLL:PLL_EN_VCO1[6, 29, 2]
    PLL:PLL_EN_VCO2[6, 28, 2]
    PLL:PLL_EN_VCO3[6, 28, 3]
    PLL:PLL_EN_VCO4[6, 29, 3]
    PLL:PLL_EN_VCO5[6, 29, 4]
    PLL:PLL_EN_VCO6[6, 28, 4]
    PLL:PLL_EN_VCO7[6, 28, 5]
    PLL:PLL_EN_VCO_DIV1[6, 28, 0]
    PLL:PLL_EN_VCO_DIV6[6, 28, 1]
    PLL:PLL_INC_FLOCK[3, 29, 29]
    PLL:PLL_INC_SLOCK[3, 28, 29]
    PLL:PLL_LOCK_CNT_RST_FAST[3, 29, 32]
    PLL:PLL_MAN_LF_EN[3, 29, 0]
    PLL:PLL_NBTI_EN[4, 28, 45]
    PLL:PLL_PMCD_MODE[5, 28, 15]
    PLL:PLL_PWRD_CFG[3, 29, 15]
    PLL:PLL_SEL_SLIPD[3, 29, 7]
    PLL:PLL_UNLOCK_CNT_RST_FAST[3, 28, 32]
    PLL:PLL_VLFHIGH_DIS[3, 28, 2]
    Non-inverted[0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
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    +
    +
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    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:CLKDV_PHASE_FALL[2, 29, 31][2, 28, 31]
    DCM0:CLKDV_PHASE_RISE[2, 28, 30][2, 29, 30]
    DCM0:DCM_COMMON_MSB_SEL[2, 28, 63][2, 28, 62]
    DCM0:DCM_VBG_PD[2, 29, 62][2, 29, 61]
    DCM0:DCM_VSPLY_VALID_ACC[2, 29, 63][2, 29, 56]
    DCM0:DFS_HARDSYNC_B[0, 29, 15][0, 28, 15]
    DCM0:DFS_SYNTH_FAST_SYNCH[0, 28, 10][0, 29, 10]
    DCM0:DLL_TEST_MUX_SEL[2, 29, 39][2, 28, 39]
    DCM0:DLL_ZD1_PHASE_SEL_INIT[1, 29, 36][1, 29, 35]
    DCM1:CLKDV_PHASE_FALL[9, 29, 31][9, 28, 31]
    DCM1:CLKDV_PHASE_RISE[9, 28, 30][9, 29, 30]
    DCM1:DCM_COMMON_MSB_SEL[9, 28, 63][9, 28, 62]
    DCM1:DCM_VBG_PD[9, 29, 62][9, 29, 61]
    DCM1:DCM_VSPLY_VALID_ACC[9, 29, 63][9, 29, 56]
    DCM1:DFS_HARDSYNC_B[7, 29, 15][7, 28, 15]
    DCM1:DFS_SYNTH_FAST_SYNCH[7, 28, 10][7, 29, 10]
    DCM1:DLL_TEST_MUX_SEL[9, 29, 39][9, 28, 39]
    DCM1:DLL_ZD1_PHASE_SEL_INIT[8, 29, 36][8, 29, 35]
    PLL:PLL_AVDD_COMP_SET[6, 29, 63][6, 28, 63]
    PLL:PLL_AVDD_VBG_PD[6, 28, 62][6, 29, 62]
    PLL:PLL_CLK0MX[6, 28, 36][6, 29, 36]
    PLL:PLL_CLK1MX[6, 28, 20][6, 29, 20]
    PLL:PLL_CLK2MX[5, 28, 60][5, 29, 60]
    PLL:PLL_CLK3MX[5, 28, 44][5, 29, 44]
    PLL:PLL_CLK4MX[5, 28, 28][5, 29, 28]
    PLL:PLL_CLK5MX[4, 28, 60][4, 29, 60]
    PLL:PLL_CLKFBMX[4, 28, 44][4, 29, 44]
    PLL:PLL_CP_RES[3, 28, 10][3, 29, 10]
    PLL:PLL_DVDD_COMP_SET[6, 29, 59][6, 28, 59]
    PLL:PLL_DVDD_VBG_PD[6, 28, 58][6, 29, 58]
    PLL:PLL_INTFB[3, 28, 36][3, 29, 36]
    PLL:PLL_LFHF[3, 29, 11][3, 28, 11]
    PLL:PLL_LF_NEN[3, 29, 2][3, 29, 1]
    PLL:PLL_LF_PEN[3, 28, 1][3, 28, 0]
    PLL:PLL_PFD_DLY[3, 28, 12][3, 29, 12]
    Non-inverted[1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:DCM_COM_PWC_FB_TAP[0, 29, 31][0, 28, 31][0, 28, 30]
    DCM0:DCM_COM_PWC_REF_TAP[0, 29, 30][0, 29, 29][0, 28, 29]
    DCM0:DCM_TRIM_CAL[2, 28, 38][2, 29, 38][2, 29, 37]
    DCM0:DFS_AVE_FREQ_SAMPLE_INTERVAL[0, 29, 63][0, 28, 63][0, 28, 62]
    DCM0:DFS_HF_TRIM_CAL[0, 29, 21][0, 28, 21][0, 28, 20]
    DCM0:DFS_SYNTH_CLOCK_SPEED[0, 29, 36][0, 29, 35][0, 28, 35]
    DCM0:DLL_TAPINIT_CTL[1, 29, 34][1, 29, 33][1, 28, 33]
    DCM0:DLL_ZD1_PWC_TAP[2, 28, 55][2, 28, 54][2, 29, 54]
    DCM0:DLL_ZD2_PWC_TAP[2, 29, 53][2, 28, 53][2, 28, 52]
    DCM1:DCM_COM_PWC_FB_TAP[7, 29, 31][7, 28, 31][7, 28, 30]
    DCM1:DCM_COM_PWC_REF_TAP[7, 29, 30][7, 29, 29][7, 28, 29]
    DCM1:DCM_TRIM_CAL[9, 28, 38][9, 29, 38][9, 29, 37]
    DCM1:DFS_AVE_FREQ_SAMPLE_INTERVAL[7, 29, 63][7, 28, 63][7, 28, 62]
    DCM1:DFS_HF_TRIM_CAL[7, 29, 21][7, 28, 21][7, 28, 20]
    DCM1:DFS_SYNTH_CLOCK_SPEED[7, 29, 36][7, 29, 35][7, 28, 35]
    DCM1:DLL_TAPINIT_CTL[8, 29, 34][8, 29, 33][8, 28, 33]
    DCM1:DLL_ZD1_PWC_TAP[9, 28, 55][9, 28, 54][9, 29, 54]
    DCM1:DLL_ZD2_PWC_TAP[9, 29, 53][9, 28, 53][9, 28, 52]
    PLL:PLL_CLKBURST_CNT[6, 29, 7][6, 28, 7][6, 28, 6]
    PLL:PLL_CLKFBOUT_PM[4, 29, 39][4, 28, 39][4, 28, 38]
    PLL:PLL_CLKOUT0_PM[6, 29, 31][6, 28, 31][6, 28, 30]
    PLL:PLL_CLKOUT1_PM[6, 29, 15][6, 28, 15][6, 28, 14]
    PLL:PLL_CLKOUT2_PM[5, 29, 55][5, 28, 55][5, 28, 54]
    PLL:PLL_CLKOUT3_PM[5, 29, 39][5, 28, 39][5, 28, 38]
    PLL:PLL_CLKOUT4_PM[5, 29, 23][5, 28, 23][5, 28, 22]
    PLL:PLL_CLKOUT5_PM[4, 29, 55][4, 28, 55][4, 28, 54]
    Non-inverted[2][1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:DCM_LOCK_HIGH_B[2, 29, 33]
    DCM0:DCM_POWERDOWN_COMMON_EN_B[2, 28, 61]
    DCM0:DFS_EN_RELRST_B[0, 29, 58]
    DCM0:DFS_PWRD_CLKIN_STOP_B[0, 29, 23]
    DCM0:DFS_PWRD_CLKIN_STOP_STICKY_B[0, 28, 23]
    DCM0:DFS_PWRD_REPLY_TIMES_OUT_B[0, 28, 22]
    DCM0:DLL_CLKFB_STOPPED_PWRD_EN_B[2, 29, 8]
    DCM0:DLL_CLKIN_STOPPED_PWRD_EN_B[2, 28, 8]
    DCM0:DLL_PWRD_ON_SCANMODE_B[1, 28, 35]
    DCM0:DLL_PWRD_STICKY_B[2, 28, 59]
    DCM1:DCM_LOCK_HIGH_B[9, 29, 33]
    DCM1:DCM_POWERDOWN_COMMON_EN_B[9, 28, 61]
    DCM1:DFS_EN_RELRST_B[7, 29, 58]
    DCM1:DFS_PWRD_CLKIN_STOP_B[7, 29, 23]
    DCM1:DFS_PWRD_CLKIN_STOP_STICKY_B[7, 28, 23]
    DCM1:DFS_PWRD_REPLY_TIMES_OUT_B[7, 28, 22]
    DCM1:DLL_CLKFB_STOPPED_PWRD_EN_B[9, 29, 8]
    DCM1:DLL_CLKIN_STOPPED_PWRD_EN_B[9, 28, 8]
    DCM1:DLL_PWRD_ON_SCANMODE_B[8, 28, 35]
    DCM1:DLL_PWRD_STICKY_B[9, 28, 59]
    PLL:INV.CLKINSEL[6, 29, 44]
    PLL:PLL_CLKCNTRL[6, 28, 43]
    PLL:PLL_TCK4_SEL[3, 29, 39]
    Inverted~[0]
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + +
    DCM0:DCM_CLKFB_IODLY_MUXINSEL[0, 29, 38]
    DCM0:DCM_CLKFB_IODLY_MUXOUT_SEL[0, 29, 24]
    DCM0:DCM_CLKIN_IODLY_MUXINSEL[0, 29, 37]
    DCM0:DCM_CLKIN_IODLY_MUXOUT_SEL[0, 28, 24]
    DCM1:DCM_CLKFB_IODLY_MUXINSEL[7, 29, 38]
    DCM1:DCM_CLKFB_IODLY_MUXOUT_SEL[7, 29, 24]
    DCM1:DCM_CLKIN_IODLY_MUXINSEL[7, 29, 37]
    DCM1:DCM_CLKIN_IODLY_MUXOUT_SEL[7, 28, 24]
    PASS0
    DELAY_LINE1
    +
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    + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:CLKDV_COUNT_FALL[2, 29, 27][2, 28, 27][2, 28, 26][2, 29, 26]
    DCM0:CLKDV_COUNT_FALL_2[2, 29, 29][2, 28, 29][2, 28, 28][2, 29, 28]
    DCM0:CLKDV_COUNT_MAX[2, 29, 25][2, 28, 25][2, 28, 24][2, 29, 24]
    DCM0:DCM_UNUSED_TAPS_POWERDOWN[1, 29, 38][1, 29, 32][1, 28, 39][0, 28, 58]
    DCM0:DCM_VBG_SEL[2, 29, 60][2, 29, 59][2, 29, 58][2, 29, 57]
    DCM0:DFS_CUSTOM_FAST_SYNC[0, 29, 62][0, 29, 61][0, 28, 61][0, 28, 60]
    DCM0:DFS_JF_LOWER_LIMIT[0, 28, 19][0, 28, 18][0, 29, 18][0, 29, 17]
    DCM1:CLKDV_COUNT_FALL[9, 29, 27][9, 28, 27][9, 28, 26][9, 29, 26]
    DCM1:CLKDV_COUNT_FALL_2[9, 29, 29][9, 28, 29][9, 28, 28][9, 29, 28]
    DCM1:CLKDV_COUNT_MAX[9, 29, 25][9, 28, 25][9, 28, 24][9, 29, 24]
    DCM1:DCM_UNUSED_TAPS_POWERDOWN[8, 29, 38][8, 29, 32][8, 28, 39][7, 28, 58]
    DCM1:DCM_VBG_SEL[9, 29, 60][9, 29, 59][9, 29, 58][9, 29, 57]
    DCM1:DFS_CUSTOM_FAST_SYNC[7, 29, 62][7, 29, 61][7, 28, 61][7, 28, 60]
    DCM1:DFS_JF_LOWER_LIMIT[7, 28, 19][7, 28, 18][7, 29, 18][7, 29, 17]
    PLL:PLL_AVDD_VBG_SEL[6, 29, 61][6, 28, 61][6, 28, 60][6, 29, 60]
    PLL:PLL_CP[3, 29, 9][3, 28, 9][3, 28, 8][3, 29, 8]
    PLL:PLL_DVDD_VBG_SEL[6, 29, 57][6, 28, 57][6, 28, 56][6, 29, 56]
    PLL:PLL_MISC[3, 28, 6][3, 29, 6][3, 29, 5][3, 28, 5]
    PLL:PLL_PFD_CNTRL[3, 28, 14][3, 29, 14][3, 29, 13][3, 28, 13]
    PLL:PLL_RES[3, 28, 4][3, 29, 4][3, 29, 3][3, 28, 3]
    PLL:PLL_UNLOCK_CNT[3, 29, 31][3, 28, 31][3, 28, 30][3, 29, 30]
    Non-inverted[3][2][1][0]
    +
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:DRP40[0, 29, 7][0, 28, 7][0, 28, 6][0, 29, 6][0, 29, 5][0, 28, 5][0, 28, 4][0, 29, 4][0, 29, 3][0, 28, 3][0, 28, 2][0, 29, 2][0, 29, 1][0, 28, 1][0, 28, 0][0, 29, 0]
    DCM0:DRP41[0, 29, 15][0, 28, 15][0, 28, 14][0, 29, 14][0, 29, 13][0, 28, 13][0, 28, 12][0, 29, 12][0, 29, 11][0, 28, 11][0, 28, 10][0, 29, 10][0, 29, 9][0, 28, 9][0, 28, 8][0, 29, 8]
    DCM0:DRP42[0, 29, 23][0, 28, 23][0, 28, 22][0, 29, 22][0, 29, 21][0, 28, 21][0, 28, 20][0, 29, 20][0, 29, 19][0, 28, 19][0, 28, 18][0, 29, 18][0, 29, 17][0, 28, 17][0, 28, 16][0, 29, 16]
    DCM0:DRP43[0, 29, 31][0, 28, 31][0, 28, 30][0, 29, 30][0, 29, 29][0, 28, 29][0, 28, 28][0, 29, 28][0, 29, 27][0, 28, 27][0, 28, 26][0, 29, 26][0, 29, 25][0, 28, 25][0, 28, 24][0, 29, 24]
    DCM0:DRP44[0, 29, 39][0, 28, 39][0, 28, 38][0, 29, 38][0, 29, 37][0, 28, 37][0, 28, 36][0, 29, 36][0, 29, 35][0, 28, 35][0, 28, 34][0, 29, 34][0, 29, 33][0, 28, 33][0, 28, 32][0, 29, 32]
    DCM0:DRP45[0, 29, 47][0, 28, 47][0, 28, 46][0, 29, 46][0, 29, 45][0, 28, 45][0, 28, 44][0, 29, 44][0, 29, 43][0, 28, 43][0, 28, 42][0, 29, 42][0, 29, 41][0, 28, 41][0, 28, 40][0, 29, 40]
    DCM0:DRP46[0, 29, 55][0, 28, 55][0, 28, 54][0, 29, 54][0, 29, 53][0, 28, 53][0, 28, 52][0, 29, 52][0, 29, 51][0, 28, 51][0, 28, 50][0, 29, 50][0, 29, 49][0, 28, 49][0, 28, 48][0, 29, 48]
    DCM0:DRP47[0, 29, 63][0, 28, 63][0, 28, 62][0, 29, 62][0, 29, 61][0, 28, 61][0, 28, 60][0, 29, 60][0, 29, 59][0, 28, 59][0, 28, 58][0, 29, 58][0, 29, 57][0, 28, 57][0, 28, 56][0, 29, 56]
    DCM0:DRP48[1, 29, 7][1, 28, 7][1, 28, 6][1, 29, 6][1, 29, 5][1, 28, 5][1, 28, 4][1, 29, 4][1, 29, 3][1, 28, 3][1, 28, 2][1, 29, 2][1, 29, 1][1, 28, 1][1, 28, 0][1, 29, 0]
    DCM0:DRP49[1, 29, 15][1, 28, 15][1, 28, 14][1, 29, 14][1, 29, 13][1, 28, 13][1, 28, 12][1, 29, 12][1, 29, 11][1, 28, 11][1, 28, 10][1, 29, 10][1, 29, 9][1, 28, 9][1, 28, 8][1, 29, 8]
    DCM0:DRP4A[1, 29, 23][1, 28, 23][1, 28, 22][1, 29, 22][1, 29, 21][1, 28, 21][1, 28, 20][1, 29, 20][1, 29, 19][1, 28, 19][1, 28, 18][1, 29, 18][1, 29, 17][1, 28, 17][1, 28, 16][1, 29, 16]
    DCM0:DRP4B[1, 29, 31][1, 28, 31][1, 28, 30][1, 29, 30][1, 29, 29][1, 28, 29][1, 28, 28][1, 29, 28][1, 29, 27][1, 28, 27][1, 28, 26][1, 29, 26][1, 29, 25][1, 28, 25][1, 28, 24][1, 29, 24]
    DCM0:DRP4C[1, 29, 39][1, 28, 39][1, 28, 38][1, 29, 38][1, 29, 37][1, 28, 37][1, 28, 36][1, 29, 36][1, 29, 35][1, 28, 35][1, 28, 34][1, 29, 34][1, 29, 33][1, 28, 33][1, 28, 32][1, 29, 32]
    DCM0:DRP4D[1, 29, 47][1, 28, 47][1, 28, 46][1, 29, 46][1, 29, 45][1, 28, 45][1, 28, 44][1, 29, 44][1, 29, 43][1, 28, 43][1, 28, 42][1, 29, 42][1, 29, 41][1, 28, 41][1, 28, 40][1, 29, 40]
    DCM0:DRP4E[1, 29, 55][1, 28, 55][1, 28, 54][1, 29, 54][1, 29, 53][1, 28, 53][1, 28, 52][1, 29, 52][1, 29, 51][1, 28, 51][1, 28, 50][1, 29, 50][1, 29, 49][1, 28, 49][1, 28, 48][1, 29, 48]
    DCM0:DRP4F[1, 29, 63][1, 28, 63][1, 28, 62][1, 29, 62][1, 29, 61][1, 28, 61][1, 28, 60][1, 29, 60][1, 29, 59][1, 28, 59][1, 28, 58][1, 29, 58][1, 29, 57][1, 28, 57][1, 28, 56][1, 29, 56]
    DCM0:DRP50[2, 29, 7][2, 28, 7][2, 28, 6][2, 29, 6][2, 29, 5][2, 28, 5][2, 28, 4][2, 29, 4][2, 29, 3][2, 28, 3][2, 28, 2][2, 29, 2][2, 29, 1][2, 28, 1][2, 28, 0][2, 29, 0]
    DCM0:DRP51[2, 29, 15][2, 28, 15][2, 28, 14][2, 29, 14][2, 29, 13][2, 28, 13][2, 28, 12][2, 29, 12][2, 29, 11][2, 28, 11][2, 28, 10][2, 29, 10][2, 29, 9][2, 28, 9][2, 28, 8][2, 29, 8]
    DCM0:DRP52[2, 29, 23][2, 28, 23][2, 28, 22][2, 29, 22][2, 29, 21][2, 28, 21][2, 28, 20][2, 29, 20][2, 29, 19][2, 28, 19][2, 28, 18][2, 29, 18][2, 29, 17][2, 28, 17][2, 28, 16][2, 29, 16]
    DCM0:DRP53[2, 29, 31][2, 28, 31][2, 28, 30][2, 29, 30][2, 29, 29][2, 28, 29][2, 28, 28][2, 29, 28][2, 29, 27][2, 28, 27][2, 28, 26][2, 29, 26][2, 29, 25][2, 28, 25][2, 28, 24][2, 29, 24]
    DCM0:DRP54[2, 29, 39][2, 28, 39][2, 28, 38][2, 29, 38][2, 29, 37][2, 28, 37][2, 28, 36][2, 29, 36][2, 29, 35][2, 28, 35][2, 28, 34][2, 29, 34][2, 29, 33][2, 28, 33][2, 28, 32][2, 29, 32]
    DCM0:DRP55[2, 29, 47][2, 28, 47][2, 28, 46][2, 29, 46][2, 29, 45][2, 28, 45][2, 28, 44][2, 29, 44][2, 29, 43][2, 28, 43][2, 28, 42][2, 29, 42][2, 29, 41][2, 28, 41][2, 28, 40][2, 29, 40]
    DCM0:DRP56[2, 29, 55][2, 28, 55][2, 28, 54][2, 29, 54][2, 29, 53][2, 28, 53][2, 28, 52][2, 29, 52][2, 29, 51][2, 28, 51][2, 28, 50][2, 29, 50][2, 29, 49][2, 28, 49][2, 28, 48][2, 29, 48]
    DCM0:DRP57[2, 29, 63][2, 28, 63][2, 28, 62][2, 29, 62][2, 29, 61][2, 28, 61][2, 28, 60][2, 29, 60][2, 29, 59][2, 28, 59][2, 28, 58][2, 29, 58][2, 29, 57][2, 28, 57][2, 28, 56][2, 29, 56]
    DCM0:FACTORY_JF[1, 29, 63][1, 28, 63][1, 28, 62][1, 29, 62][1, 29, 61][1, 28, 61][1, 28, 60][1, 29, 60][1, 29, 59][1, 28, 59][1, 28, 58][1, 29, 58][1, 29, 57][1, 28, 57][1, 28, 56][1, 29, 56]
    DCM1:DRP40[7, 29, 7][7, 28, 7][7, 28, 6][7, 29, 6][7, 29, 5][7, 28, 5][7, 28, 4][7, 29, 4][7, 29, 3][7, 28, 3][7, 28, 2][7, 29, 2][7, 29, 1][7, 28, 1][7, 28, 0][7, 29, 0]
    DCM1:DRP41[7, 29, 15][7, 28, 15][7, 28, 14][7, 29, 14][7, 29, 13][7, 28, 13][7, 28, 12][7, 29, 12][7, 29, 11][7, 28, 11][7, 28, 10][7, 29, 10][7, 29, 9][7, 28, 9][7, 28, 8][7, 29, 8]
    DCM1:DRP42[7, 29, 23][7, 28, 23][7, 28, 22][7, 29, 22][7, 29, 21][7, 28, 21][7, 28, 20][7, 29, 20][7, 29, 19][7, 28, 19][7, 28, 18][7, 29, 18][7, 29, 17][7, 28, 17][7, 28, 16][7, 29, 16]
    DCM1:DRP43[7, 29, 31][7, 28, 31][7, 28, 30][7, 29, 30][7, 29, 29][7, 28, 29][7, 28, 28][7, 29, 28][7, 29, 27][7, 28, 27][7, 28, 26][7, 29, 26][7, 29, 25][7, 28, 25][7, 28, 24][7, 29, 24]
    DCM1:DRP44[7, 29, 39][7, 28, 39][7, 28, 38][7, 29, 38][7, 29, 37][7, 28, 37][7, 28, 36][7, 29, 36][7, 29, 35][7, 28, 35][7, 28, 34][7, 29, 34][7, 29, 33][7, 28, 33][7, 28, 32][7, 29, 32]
    DCM1:DRP45[7, 29, 47][7, 28, 47][7, 28, 46][7, 29, 46][7, 29, 45][7, 28, 45][7, 28, 44][7, 29, 44][7, 29, 43][7, 28, 43][7, 28, 42][7, 29, 42][7, 29, 41][7, 28, 41][7, 28, 40][7, 29, 40]
    DCM1:DRP46[7, 29, 55][7, 28, 55][7, 28, 54][7, 29, 54][7, 29, 53][7, 28, 53][7, 28, 52][7, 29, 52][7, 29, 51][7, 28, 51][7, 28, 50][7, 29, 50][7, 29, 49][7, 28, 49][7, 28, 48][7, 29, 48]
    DCM1:DRP47[7, 29, 63][7, 28, 63][7, 28, 62][7, 29, 62][7, 29, 61][7, 28, 61][7, 28, 60][7, 29, 60][7, 29, 59][7, 28, 59][7, 28, 58][7, 29, 58][7, 29, 57][7, 28, 57][7, 28, 56][7, 29, 56]
    DCM1:DRP48[8, 29, 7][8, 28, 7][8, 28, 6][8, 29, 6][8, 29, 5][8, 28, 5][8, 28, 4][8, 29, 4][8, 29, 3][8, 28, 3][8, 28, 2][8, 29, 2][8, 29, 1][8, 28, 1][8, 28, 0][8, 29, 0]
    DCM1:DRP49[8, 29, 15][8, 28, 15][8, 28, 14][8, 29, 14][8, 29, 13][8, 28, 13][8, 28, 12][8, 29, 12][8, 29, 11][8, 28, 11][8, 28, 10][8, 29, 10][8, 29, 9][8, 28, 9][8, 28, 8][8, 29, 8]
    DCM1:DRP4A[8, 29, 23][8, 28, 23][8, 28, 22][8, 29, 22][8, 29, 21][8, 28, 21][8, 28, 20][8, 29, 20][8, 29, 19][8, 28, 19][8, 28, 18][8, 29, 18][8, 29, 17][8, 28, 17][8, 28, 16][8, 29, 16]
    DCM1:DRP4B[8, 29, 31][8, 28, 31][8, 28, 30][8, 29, 30][8, 29, 29][8, 28, 29][8, 28, 28][8, 29, 28][8, 29, 27][8, 28, 27][8, 28, 26][8, 29, 26][8, 29, 25][8, 28, 25][8, 28, 24][8, 29, 24]
    DCM1:DRP4C[8, 29, 39][8, 28, 39][8, 28, 38][8, 29, 38][8, 29, 37][8, 28, 37][8, 28, 36][8, 29, 36][8, 29, 35][8, 28, 35][8, 28, 34][8, 29, 34][8, 29, 33][8, 28, 33][8, 28, 32][8, 29, 32]
    DCM1:DRP4D[8, 29, 47][8, 28, 47][8, 28, 46][8, 29, 46][8, 29, 45][8, 28, 45][8, 28, 44][8, 29, 44][8, 29, 43][8, 28, 43][8, 28, 42][8, 29, 42][8, 29, 41][8, 28, 41][8, 28, 40][8, 29, 40]
    DCM1:DRP4E[8, 29, 55][8, 28, 55][8, 28, 54][8, 29, 54][8, 29, 53][8, 28, 53][8, 28, 52][8, 29, 52][8, 29, 51][8, 28, 51][8, 28, 50][8, 29, 50][8, 29, 49][8, 28, 49][8, 28, 48][8, 29, 48]
    DCM1:DRP4F[8, 29, 63][8, 28, 63][8, 28, 62][8, 29, 62][8, 29, 61][8, 28, 61][8, 28, 60][8, 29, 60][8, 29, 59][8, 28, 59][8, 28, 58][8, 29, 58][8, 29, 57][8, 28, 57][8, 28, 56][8, 29, 56]
    DCM1:DRP50[9, 29, 7][9, 28, 7][9, 28, 6][9, 29, 6][9, 29, 5][9, 28, 5][9, 28, 4][9, 29, 4][9, 29, 3][9, 28, 3][9, 28, 2][9, 29, 2][9, 29, 1][9, 28, 1][9, 28, 0][9, 29, 0]
    DCM1:DRP51[9, 29, 15][9, 28, 15][9, 28, 14][9, 29, 14][9, 29, 13][9, 28, 13][9, 28, 12][9, 29, 12][9, 29, 11][9, 28, 11][9, 28, 10][9, 29, 10][9, 29, 9][9, 28, 9][9, 28, 8][9, 29, 8]
    DCM1:DRP52[9, 29, 23][9, 28, 23][9, 28, 22][9, 29, 22][9, 29, 21][9, 28, 21][9, 28, 20][9, 29, 20][9, 29, 19][9, 28, 19][9, 28, 18][9, 29, 18][9, 29, 17][9, 28, 17][9, 28, 16][9, 29, 16]
    DCM1:DRP53[9, 29, 31][9, 28, 31][9, 28, 30][9, 29, 30][9, 29, 29][9, 28, 29][9, 28, 28][9, 29, 28][9, 29, 27][9, 28, 27][9, 28, 26][9, 29, 26][9, 29, 25][9, 28, 25][9, 28, 24][9, 29, 24]
    DCM1:DRP54[9, 29, 39][9, 28, 39][9, 28, 38][9, 29, 38][9, 29, 37][9, 28, 37][9, 28, 36][9, 29, 36][9, 29, 35][9, 28, 35][9, 28, 34][9, 29, 34][9, 29, 33][9, 28, 33][9, 28, 32][9, 29, 32]
    DCM1:DRP55[9, 29, 47][9, 28, 47][9, 28, 46][9, 29, 46][9, 29, 45][9, 28, 45][9, 28, 44][9, 29, 44][9, 29, 43][9, 28, 43][9, 28, 42][9, 29, 42][9, 29, 41][9, 28, 41][9, 28, 40][9, 29, 40]
    DCM1:DRP56[9, 29, 55][9, 28, 55][9, 28, 54][9, 29, 54][9, 29, 53][9, 28, 53][9, 28, 52][9, 29, 52][9, 29, 51][9, 28, 51][9, 28, 50][9, 29, 50][9, 29, 49][9, 28, 49][9, 28, 48][9, 29, 48]
    DCM1:DRP57[9, 29, 63][9, 28, 63][9, 28, 62][9, 29, 62][9, 29, 61][9, 28, 61][9, 28, 60][9, 29, 60][9, 29, 59][9, 28, 59][9, 28, 58][9, 29, 58][9, 29, 57][9, 28, 57][9, 28, 56][9, 29, 56]
    DCM1:FACTORY_JF[8, 29, 63][8, 28, 63][8, 28, 62][8, 29, 62][8, 29, 61][8, 28, 61][8, 28, 60][8, 29, 60][8, 29, 59][8, 28, 59][8, 28, 58][8, 29, 58][8, 29, 57][8, 28, 57][8, 28, 56][8, 29, 56]
    PLL:DRP00[3, 29, 7][3, 28, 7][3, 28, 6][3, 29, 6][3, 29, 5][3, 28, 5][3, 28, 4][3, 29, 4][3, 29, 3][3, 28, 3][3, 28, 2][3, 29, 2][3, 29, 1][3, 28, 1][3, 28, 0][3, 29, 0]
    PLL:DRP01[3, 29, 15][3, 28, 15][3, 28, 14][3, 29, 14][3, 29, 13][3, 28, 13][3, 28, 12][3, 29, 12][3, 29, 11][3, 28, 11][3, 28, 10][3, 29, 10][3, 29, 9][3, 28, 9][3, 28, 8][3, 29, 8]
    PLL:DRP02[3, 29, 23][3, 28, 23][3, 28, 22][3, 29, 22][3, 29, 21][3, 28, 21][3, 28, 20][3, 29, 20][3, 29, 19][3, 28, 19][3, 28, 18][3, 29, 18][3, 29, 17][3, 28, 17][3, 28, 16][3, 29, 16]
    PLL:DRP03[3, 29, 31][3, 28, 31][3, 28, 30][3, 29, 30][3, 29, 29][3, 28, 29][3, 28, 28][3, 29, 28][3, 29, 27][3, 28, 27][3, 28, 26][3, 29, 26][3, 29, 25][3, 28, 25][3, 28, 24][3, 29, 24]
    PLL:DRP04[3, 29, 39][3, 28, 39][3, 28, 38][3, 29, 38][3, 29, 37][3, 28, 37][3, 28, 36][3, 29, 36][3, 29, 35][3, 28, 35][3, 28, 34][3, 29, 34][3, 29, 33][3, 28, 33][3, 28, 32][3, 29, 32]
    PLL:DRP05[3, 29, 47][3, 28, 47][3, 28, 46][3, 29, 46][3, 29, 45][3, 28, 45][3, 28, 44][3, 29, 44][3, 29, 43][3, 28, 43][3, 28, 42][3, 29, 42][3, 29, 41][3, 28, 41][3, 28, 40][3, 29, 40]
    PLL:DRP06[3, 29, 55][3, 28, 55][3, 28, 54][3, 29, 54][3, 29, 53][3, 28, 53][3, 28, 52][3, 29, 52][3, 29, 51][3, 28, 51][3, 28, 50][3, 29, 50][3, 29, 49][3, 28, 49][3, 28, 48][3, 29, 48]
    PLL:DRP07[3, 29, 63][3, 28, 63][3, 28, 62][3, 29, 62][3, 29, 61][3, 28, 61][3, 28, 60][3, 29, 60][3, 29, 59][3, 28, 59][3, 28, 58][3, 29, 58][3, 29, 57][3, 28, 57][3, 28, 56][3, 29, 56]
    PLL:DRP08[4, 29, 7][4, 28, 7][4, 28, 6][4, 29, 6][4, 29, 5][4, 28, 5][4, 28, 4][4, 29, 4][4, 29, 3][4, 28, 3][4, 28, 2][4, 29, 2][4, 29, 1][4, 28, 1][4, 28, 0][4, 29, 0]
    PLL:DRP09[4, 29, 15][4, 28, 15][4, 28, 14][4, 29, 14][4, 29, 13][4, 28, 13][4, 28, 12][4, 29, 12][4, 29, 11][4, 28, 11][4, 28, 10][4, 29, 10][4, 29, 9][4, 28, 9][4, 28, 8][4, 29, 8]
    PLL:DRP0A[4, 29, 23][4, 28, 23][4, 28, 22][4, 29, 22][4, 29, 21][4, 28, 21][4, 28, 20][4, 29, 20][4, 29, 19][4, 28, 19][4, 28, 18][4, 29, 18][4, 29, 17][4, 28, 17][4, 28, 16][4, 29, 16]
    PLL:DRP0B[4, 29, 31][4, 28, 31][4, 28, 30][4, 29, 30][4, 29, 29][4, 28, 29][4, 28, 28][4, 29, 28][4, 29, 27][4, 28, 27][4, 28, 26][4, 29, 26][4, 29, 25][4, 28, 25][4, 28, 24][4, 29, 24]
    PLL:DRP0C[4, 29, 39][4, 28, 39][4, 28, 38][4, 29, 38][4, 29, 37][4, 28, 37][4, 28, 36][4, 29, 36][4, 29, 35][4, 28, 35][4, 28, 34][4, 29, 34][4, 29, 33][4, 28, 33][4, 28, 32][4, 29, 32]
    PLL:DRP0D[4, 29, 47][4, 28, 47][4, 28, 46][4, 29, 46][4, 29, 45][4, 28, 45][4, 28, 44][4, 29, 44][4, 29, 43][4, 28, 43][4, 28, 42][4, 29, 42][4, 29, 41][4, 28, 41][4, 28, 40][4, 29, 40]
    PLL:DRP0E[4, 29, 55][4, 28, 55][4, 28, 54][4, 29, 54][4, 29, 53][4, 28, 53][4, 28, 52][4, 29, 52][4, 29, 51][4, 28, 51][4, 28, 50][4, 29, 50][4, 29, 49][4, 28, 49][4, 28, 48][4, 29, 48]
    PLL:DRP0F[4, 29, 63][4, 28, 63][4, 28, 62][4, 29, 62][4, 29, 61][4, 28, 61][4, 28, 60][4, 29, 60][4, 29, 59][4, 28, 59][4, 28, 58][4, 29, 58][4, 29, 57][4, 28, 57][4, 28, 56][4, 29, 56]
    PLL:DRP10[5, 29, 7][5, 28, 7][5, 28, 6][5, 29, 6][5, 29, 5][5, 28, 5][5, 28, 4][5, 29, 4][5, 29, 3][5, 28, 3][5, 28, 2][5, 29, 2][5, 29, 1][5, 28, 1][5, 28, 0][5, 29, 0]
    PLL:DRP11[5, 29, 15][5, 28, 15][5, 28, 14][5, 29, 14][5, 29, 13][5, 28, 13][5, 28, 12][5, 29, 12][5, 29, 11][5, 28, 11][5, 28, 10][5, 29, 10][5, 29, 9][5, 28, 9][5, 28, 8][5, 29, 8]
    PLL:DRP12[5, 29, 23][5, 28, 23][5, 28, 22][5, 29, 22][5, 29, 21][5, 28, 21][5, 28, 20][5, 29, 20][5, 29, 19][5, 28, 19][5, 28, 18][5, 29, 18][5, 29, 17][5, 28, 17][5, 28, 16][5, 29, 16]
    PLL:DRP13[5, 29, 31][5, 28, 31][5, 28, 30][5, 29, 30][5, 29, 29][5, 28, 29][5, 28, 28][5, 29, 28][5, 29, 27][5, 28, 27][5, 28, 26][5, 29, 26][5, 29, 25][5, 28, 25][5, 28, 24][5, 29, 24]
    PLL:DRP14[5, 29, 39][5, 28, 39][5, 28, 38][5, 29, 38][5, 29, 37][5, 28, 37][5, 28, 36][5, 29, 36][5, 29, 35][5, 28, 35][5, 28, 34][5, 29, 34][5, 29, 33][5, 28, 33][5, 28, 32][5, 29, 32]
    PLL:DRP15[5, 29, 47][5, 28, 47][5, 28, 46][5, 29, 46][5, 29, 45][5, 28, 45][5, 28, 44][5, 29, 44][5, 29, 43][5, 28, 43][5, 28, 42][5, 29, 42][5, 29, 41][5, 28, 41][5, 28, 40][5, 29, 40]
    PLL:DRP16[5, 29, 55][5, 28, 55][5, 28, 54][5, 29, 54][5, 29, 53][5, 28, 53][5, 28, 52][5, 29, 52][5, 29, 51][5, 28, 51][5, 28, 50][5, 29, 50][5, 29, 49][5, 28, 49][5, 28, 48][5, 29, 48]
    PLL:DRP17[5, 29, 63][5, 28, 63][5, 28, 62][5, 29, 62][5, 29, 61][5, 28, 61][5, 28, 60][5, 29, 60][5, 29, 59][5, 28, 59][5, 28, 58][5, 29, 58][5, 29, 57][5, 28, 57][5, 28, 56][5, 29, 56]
    PLL:DRP18[6, 29, 7][6, 28, 7][6, 28, 6][6, 29, 6][6, 29, 5][6, 28, 5][6, 28, 4][6, 29, 4][6, 29, 3][6, 28, 3][6, 28, 2][6, 29, 2][6, 29, 1][6, 28, 1][6, 28, 0][6, 29, 0]
    PLL:DRP19[6, 29, 15][6, 28, 15][6, 28, 14][6, 29, 14][6, 29, 13][6, 28, 13][6, 28, 12][6, 29, 12][6, 29, 11][6, 28, 11][6, 28, 10][6, 29, 10][6, 29, 9][6, 28, 9][6, 28, 8][6, 29, 8]
    PLL:DRP1A[6, 29, 23][6, 28, 23][6, 28, 22][6, 29, 22][6, 29, 21][6, 28, 21][6, 28, 20][6, 29, 20][6, 29, 19][6, 28, 19][6, 28, 18][6, 29, 18][6, 29, 17][6, 28, 17][6, 28, 16][6, 29, 16]
    PLL:DRP1B[6, 29, 31][6, 28, 31][6, 28, 30][6, 29, 30][6, 29, 29][6, 28, 29][6, 28, 28][6, 29, 28][6, 29, 27][6, 28, 27][6, 28, 26][6, 29, 26][6, 29, 25][6, 28, 25][6, 28, 24][6, 29, 24]
    PLL:DRP1C[6, 29, 39][6, 28, 39][6, 28, 38][6, 29, 38][6, 29, 37][6, 28, 37][6, 28, 36][6, 29, 36][6, 29, 35][6, 28, 35][6, 28, 34][6, 29, 34][6, 29, 33][6, 28, 33][6, 28, 32][6, 29, 32]
    PLL:DRP1D[6, 29, 47][6, 28, 47][6, 28, 46][6, 29, 46][6, 29, 45][6, 28, 45][6, 28, 44][6, 29, 44][6, 29, 43][6, 28, 43][6, 28, 42][6, 29, 42][6, 29, 41][6, 28, 41][6, 28, 40][6, 29, 40]
    PLL:DRP1E[6, 29, 55][6, 28, 55][6, 28, 54][6, 29, 54][6, 29, 53][6, 28, 53][6, 28, 52][6, 29, 52][6, 29, 51][6, 28, 51][6, 28, 50][6, 29, 50][6, 29, 49][6, 28, 49][6, 28, 48][6, 29, 48]
    PLL:DRP1F[6, 29, 63][6, 28, 63][6, 28, 62][6, 29, 62][6, 29, 61][6, 28, 61][6, 28, 60][6, 29, 60][6, 29, 59][6, 28, 59][6, 28, 58][6, 29, 58][6, 29, 57][6, 28, 57][6, 28, 56][6, 29, 56]
    Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + +
    DCM0:DESKEW_ADJUST[0, 29, 27][0, 28, 27][0, 28, 26][0, 29, 26][0, 29, 25]
    DCM1:DESKEW_ADJUST[7, 29, 27][7, 28, 27][7, 28, 26][7, 29, 26][7, 29, 25]
    PLL:CLKFBOUT_DESKEW_ADJUST[4, 29, 47][4, 28, 47][4, 28, 46][4, 29, 46][4, 29, 45]
    PLL:CLKOUT0_DESKEW_ADJUST[6, 29, 39][6, 28, 39][6, 28, 38][6, 29, 38][6, 29, 37]
    PLL:CLKOUT1_DESKEW_ADJUST[6, 29, 23][6, 28, 23][6, 28, 22][6, 29, 22][6, 29, 21]
    PLL:CLKOUT2_DESKEW_ADJUST[5, 29, 63][5, 28, 63][5, 28, 62][5, 29, 62][5, 29, 61]
    PLL:CLKOUT3_DESKEW_ADJUST[5, 29, 47][5, 28, 47][5, 28, 46][5, 29, 46][5, 29, 45]
    PLL:CLKOUT4_DESKEW_ADJUST[5, 29, 31][5, 28, 31][5, 28, 30][5, 29, 30][5, 29, 29]
    PLL:CLKOUT5_DESKEW_ADJUST[4, 29, 63][4, 28, 63][4, 28, 62][4, 29, 62][4, 29, 61]
    PLL:PLL_IN_DLY_MX_SEL[3, 28, 63][3, 28, 62][3, 29, 62][3, 29, 61][3, 28, 61]
    PLL:PLL_LOCK_FB_P1[3, 29, 26][3, 29, 25][3, 28, 25][3, 28, 24][3, 29, 24]
    PLL:PLL_LOCK_FB_P2[3, 28, 28][3, 29, 28][3, 29, 27][3, 28, 27][3, 28, 26]
    PLL:PLL_LOCK_REF_P1[3, 28, 21][3, 28, 20][3, 29, 20][3, 29, 19][3, 28, 19]
    PLL:PLL_LOCK_REF_P2[3, 29, 23][3, 28, 23][3, 28, 22][3, 29, 22][3, 29, 21]
    Non-inverted[4][3][2][1][0]
    +
    +
    + + + + + + + +
    DCM0:DLL_SYNTH_CLOCK_SPEED[0, 28, 34][0, 29, 34]
    DCM1:DLL_SYNTH_CLOCK_SPEED[7, 28, 34][7, 29, 34]
    NORMAL00
    HALF01
    QUARTER10
    VDD11
    +
    +
    + + + + +
    DCM0:DFS_TAPTRIM[0, 28, 45][0, 28, 44][0, 29, 44][0, 29, 43][0, 28, 43][0, 28, 42][0, 29, 42][0, 29, 41][0, 28, 41][0, 28, 40][0, 29, 40]
    DCM1:DFS_TAPTRIM[7, 28, 45][7, 28, 44][7, 29, 44][7, 29, 43][7, 28, 43][7, 28, 42][7, 29, 42][7, 29, 41][7, 28, 41][7, 28, 40][7, 29, 40]
    Non-inverted[10][9][8][7][6][5][4][3][2][1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + +
    DCM0:CLKFX_DIVIDE[2, 29, 3][2, 28, 3][2, 28, 2][2, 29, 2][2, 29, 1][2, 28, 1][2, 28, 0][2, 29, 0]
    DCM0:CLKFX_MULTIPLY[2, 29, 7][2, 28, 7][2, 28, 6][2, 29, 6][2, 29, 5][2, 28, 5][2, 28, 4][2, 29, 4]
    DCM0:DFS_TWEAK[0, 29, 51][0, 28, 51][0, 28, 50][0, 29, 50][0, 29, 49][0, 28, 49][0, 28, 48][0, 29, 48]
    DCM0:DLL_DEAD_TIME[2, 29, 23][2, 28, 23][2, 28, 22][2, 29, 22][2, 29, 21][2, 28, 21][2, 28, 20][2, 29, 20]
    DCM0:DLL_DESKEW_MAXTAP[1, 29, 55][1, 28, 55][1, 28, 54][1, 29, 54][1, 29, 53][1, 28, 53][1, 28, 52][1, 29, 52]
    DCM0:DLL_DESKEW_MINTAP[1, 29, 51][1, 28, 51][1, 28, 50][1, 29, 50][1, 29, 49][1, 28, 49][1, 28, 48][1, 29, 48]
    DCM0:DLL_LIVE_TIME[2, 29, 19][2, 28, 19][2, 28, 18][2, 29, 18][2, 29, 17][2, 28, 17][2, 28, 16][2, 29, 16]
    DCM0:DLL_SETTLE_TIME[2, 29, 15][2, 28, 15][2, 28, 14][2, 29, 14][2, 29, 13][2, 28, 13][2, 28, 12][2, 29, 12]
    DCM0:DLL_ZD1_TAP_INIT[1, 29, 47][1, 28, 47][1, 28, 46][1, 29, 46][1, 29, 45][1, 28, 45][1, 28, 44][1, 29, 44]
    DCM1:CLKFX_DIVIDE[9, 29, 3][9, 28, 3][9, 28, 2][9, 29, 2][9, 29, 1][9, 28, 1][9, 28, 0][9, 29, 0]
    DCM1:CLKFX_MULTIPLY[9, 29, 7][9, 28, 7][9, 28, 6][9, 29, 6][9, 29, 5][9, 28, 5][9, 28, 4][9, 29, 4]
    DCM1:DFS_TWEAK[7, 29, 51][7, 28, 51][7, 28, 50][7, 29, 50][7, 29, 49][7, 28, 49][7, 28, 48][7, 29, 48]
    DCM1:DLL_DEAD_TIME[9, 29, 23][9, 28, 23][9, 28, 22][9, 29, 22][9, 29, 21][9, 28, 21][9, 28, 20][9, 29, 20]
    DCM1:DLL_DESKEW_MAXTAP[8, 29, 55][8, 28, 55][8, 28, 54][8, 29, 54][8, 29, 53][8, 28, 53][8, 28, 52][8, 29, 52]
    DCM1:DLL_DESKEW_MINTAP[8, 29, 51][8, 28, 51][8, 28, 50][8, 29, 50][8, 29, 49][8, 28, 49][8, 28, 48][8, 29, 48]
    DCM1:DLL_LIVE_TIME[9, 29, 19][9, 28, 19][9, 28, 18][9, 29, 18][9, 29, 17][9, 28, 17][9, 28, 16][9, 29, 16]
    DCM1:DLL_SETTLE_TIME[9, 29, 15][9, 28, 15][9, 28, 14][9, 29, 14][9, 29, 13][9, 28, 13][9, 28, 12][9, 29, 12]
    DCM1:DLL_ZD1_TAP_INIT[8, 29, 47][8, 28, 47][8, 28, 46][8, 29, 46][8, 29, 45][8, 28, 45][8, 28, 44][8, 29, 44]
    Non-inverted[7][6][5][4][3][2][1][0]
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DCM0:MUX.CLKFB[1, 28, 4][1, 29, 4][1, 29, 3][1, 28, 3][1, 28, 2]
    DCM0:MUX.CLKIN[1, 29, 2][1, 29, 1][1, 28, 1][1, 28, 0][1, 29, 0]
    DCM1:MUX.CLKFB[8, 28, 4][8, 29, 4][8, 29, 3][8, 28, 3][8, 28, 2]
    DCM1:MUX.CLKIN[8, 29, 2][8, 29, 1][8, 28, 1][8, 28, 0][8, 29, 0]
    GIOB000000
    GIOB100001
    GIOB200010
    GIOB300011
    GIOB400100
    GIOB500101
    GIOB601000
    GIOB701001
    GIOB801010
    GIOB901011
    HCLK001100
    HCLK101101
    HCLK210000
    HCLK310001
    HCLK410010
    HCLK510011
    HCLK610100
    HCLK710101
    HCLK811000
    HCLK911001
    CKINT011010
    CKINT111011
    CKINT211100
    CLK_FROM_PLL11101
    +
    +
    +
    +
    + + + + + + + + + + + + + + + +
    DCM0:MUX.CLK_TO_PLL[1, 28, 6][1, 29, 6][1, 29, 5][1, 28, 5]
    DCM0:MUX.SKEWCLKIN2[1, 29, 9][1, 28, 9][1, 28, 8][1, 29, 8]
    DCM1:MUX.CLK_TO_PLL[8, 28, 6][8, 29, 6][8, 29, 5][8, 28, 5]
    DCM1:MUX.SKEWCLKIN2[8, 29, 9][8, 28, 9][8, 28, 8][8, 29, 8]
    CLK00000
    CLK900001
    CLK1800010
    CLK2700011
    CLK2X0100
    CLK2X1800101
    CLKDV0110
    CLKFX0111
    CLKFX1801000
    CONCUR1001
    +
    +
    + + + + + + + +
    DCM0:DLL_PHASE_SHIFT_CALIBRATION[1, 28, 24][1, 29, 24]
    DCM1:DLL_PHASE_SHIFT_CALIBRATION[8, 28, 24][8, 29, 24]
    AUTO_DPS00
    CONFIG01
    MASK10
    AUTO_ZD211
    +
    +
    + + + + +
    DCM0:DLL_ZD2_TAP_INIT[1, 28, 43][1, 28, 42][1, 29, 42][1, 29, 41][1, 28, 41][1, 28, 40][1, 29, 40]
    DCM1:DLL_ZD2_TAP_INIT[8, 28, 43][8, 28, 42][8, 29, 42][8, 29, 41][8, 28, 41][8, 28, 40][8, 29, 40]
    Non-inverted[6][5][4][3][2][1][0]
    +
    +
    + + + + + +
    DCM0:DLL_FREQUENCY_MODE[2, 29, 9][2, 28, 9]
    DCM1:DLL_FREQUENCY_MODE[9, 29, 9][9, 28, 9]
    LOW00
    HIGH11
    +
    +
    + + + + + +
    DCM0:PS_MODE[2, 29, 10]
    DCM1:PS_MODE[9, 29, 10]
    CLKFB0
    CLKIN1
    +
    +
    + + + + + +
    DCM0:CLKDV_MODE[2, 29, 32]
    DCM1:CLKDV_MODE[9, 29, 32]
    HALF0
    INT1
    +
    +
    + + + + +
    DCM0:PHASE_SHIFT[2, 28, 44][2, 29, 44][2, 29, 43][2, 28, 43][2, 28, 42][2, 29, 42][2, 29, 41][2, 28, 41][2, 28, 40][2, 29, 40]
    DCM1:PHASE_SHIFT[9, 28, 44][9, 29, 44][9, 29, 43][9, 28, 43][9, 28, 42][9, 29, 42][9, 29, 41][9, 28, 41][9, 28, 40][9, 29, 40]
    Non-inverted[9][8][7][6][5][4][3][2][1][0]
    +
    +
    +
    + + + + + +
    DCM0:DLL_PHASE_SHIFT_LFC[2, 29, 52][2, 29, 51][2, 28, 51][2, 28, 50][2, 29, 50][2, 29, 49][2, 28, 49][2, 28, 48][2, 29, 48]
    DCM1:DLL_PHASE_SHIFT_LFC[9, 29, 52][9, 29, 51][9, 28, 51][9, 28, 50][9, 29, 50][9, 29, 49][9, 28, 49][9, 28, 48][9, 29, 48]
    PLL:PLL_IN_DLY_SET[3, 29, 60][3, 29, 59][3, 28, 59][3, 28, 58][3, 29, 58][3, 29, 57][3, 28, 57][3, 28, 56][3, 29, 56]
    Non-inverted[8][7][6][5][4][3][2][1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    PLL:PLL_CLKFBOUT2_DT[4, 28, 18][4, 29, 18][4, 29, 17][4, 28, 17][4, 28, 16][4, 29, 16]
    PLL:PLL_CLKFBOUT2_HT[4, 29, 13][4, 28, 13][4, 28, 12][4, 29, 12][4, 29, 11][4, 28, 11]
    PLL:PLL_CLKFBOUT2_LT[4, 28, 10][4, 29, 10][4, 29, 9][4, 28, 9][4, 28, 8][4, 29, 8]
    PLL:PLL_CLKFBOUT_DT[4, 28, 42][4, 29, 42][4, 29, 41][4, 28, 41][4, 28, 40][4, 29, 40]
    PLL:PLL_CLKFBOUT_HT[4, 29, 37][4, 28, 37][4, 28, 36][4, 29, 36][4, 29, 35][4, 28, 35]
    PLL:PLL_CLKFBOUT_LT[4, 28, 34][4, 29, 34][4, 29, 33][4, 28, 33][4, 28, 32][4, 29, 32]
    PLL:PLL_CLKOUT0_DT[6, 28, 34][6, 29, 34][6, 29, 33][6, 28, 33][6, 28, 32][6, 29, 32]
    PLL:PLL_CLKOUT0_HT[6, 29, 29][6, 28, 29][6, 28, 28][6, 29, 28][6, 29, 27][6, 28, 27]
    PLL:PLL_CLKOUT0_LT[6, 28, 26][6, 29, 26][6, 29, 25][6, 28, 25][6, 28, 24][6, 29, 24]
    PLL:PLL_CLKOUT1_DT[6, 28, 18][6, 29, 18][6, 29, 17][6, 28, 17][6, 28, 16][6, 29, 16]
    PLL:PLL_CLKOUT1_HT[6, 29, 13][6, 28, 13][6, 28, 12][6, 29, 12][6, 29, 11][6, 28, 11]
    PLL:PLL_CLKOUT1_LT[6, 28, 10][6, 29, 10][6, 29, 9][6, 28, 9][6, 28, 8][6, 29, 8]
    PLL:PLL_CLKOUT2_DT[5, 28, 58][5, 29, 58][5, 29, 57][5, 28, 57][5, 28, 56][5, 29, 56]
    PLL:PLL_CLKOUT2_HT[5, 29, 53][5, 28, 53][5, 28, 52][5, 29, 52][5, 29, 51][5, 28, 51]
    PLL:PLL_CLKOUT2_LT[5, 28, 50][5, 29, 50][5, 29, 49][5, 28, 49][5, 28, 48][5, 29, 48]
    PLL:PLL_CLKOUT3_DT[5, 28, 42][5, 29, 42][5, 29, 41][5, 28, 41][5, 28, 40][5, 29, 40]
    PLL:PLL_CLKOUT3_HT[5, 29, 37][5, 28, 37][5, 28, 36][5, 29, 36][5, 29, 35][5, 28, 35]
    PLL:PLL_CLKOUT3_LT[5, 28, 34][5, 29, 34][5, 29, 33][5, 28, 33][5, 28, 32][5, 29, 32]
    PLL:PLL_CLKOUT4_DT[5, 28, 26][5, 29, 26][5, 29, 25][5, 28, 25][5, 28, 24][5, 29, 24]
    PLL:PLL_CLKOUT4_HT[5, 29, 21][5, 28, 21][5, 28, 20][5, 29, 20][5, 29, 19][5, 28, 19]
    PLL:PLL_CLKOUT4_LT[5, 28, 18][5, 29, 18][5, 29, 17][5, 28, 17][5, 28, 16][5, 29, 16]
    PLL:PLL_CLKOUT5_DT[4, 28, 58][4, 29, 58][4, 29, 57][4, 28, 57][4, 28, 56][4, 29, 56]
    PLL:PLL_CLKOUT5_HT[4, 29, 53][4, 28, 53][4, 28, 52][4, 29, 52][4, 29, 51][4, 28, 51]
    PLL:PLL_CLKOUT5_LT[4, 28, 50][4, 29, 50][4, 29, 49][4, 28, 49][4, 28, 48][4, 29, 48]
    PLL:PLL_DIVCLK_DT[4, 29, 23][4, 28, 23][4, 28, 22][4, 29, 22][4, 29, 21][4, 28, 21]
    PLL:PLL_DIVCLK_HT[3, 29, 53][3, 28, 53][3, 28, 52][3, 29, 52][3, 29, 51][3, 28, 51]
    PLL:PLL_DIVCLK_LT[3, 28, 50][3, 29, 50][3, 29, 49][3, 28, 49][3, 28, 48][3, 29, 48]
    PLL:PLL_FLOCK[3, 29, 35][3, 28, 35][3, 28, 34][3, 29, 34][3, 29, 33][3, 28, 33]
    PLL:PLL_LOCK_CNT[3, 28, 18][3, 29, 18][3, 29, 17][3, 28, 17][3, 28, 16][3, 29, 16]
    Non-inverted[5][4][3][2][1][0]
    +
    + + + +
    PLL:PLL_EN_CNTRL[5, 28, 14][5, 29, 14][5, 29, 13][5, 28, 13][5, 28, 12][5, 29, 12][5, 29, 11][5, 28, 11][5, 28, 10][5, 29, 10][5, 29, 9][5, 28, 9][5, 28, 8][5, 29, 8][5, 29, 7][5, 28, 7][5, 28, 6][5, 29, 6][5, 29, 5][5, 28, 5][5, 28, 4][5, 29, 4][5, 29, 3][5, 28, 3][5, 28, 2][5, 29, 2][5, 29, 1][5, 28, 1][5, 28, 0][5, 29, 0][4, 29, 31][4, 28, 31][4, 28, 30][4, 29, 30][4, 29, 29][4, 28, 29][4, 28, 28][4, 29, 28][4, 29, 27][4, 28, 27][4, 28, 26][4, 29, 26][4, 29, 25][4, 28, 25][4, 28, 24][4, 29, 24][4, 29, 7][4, 28, 7][4, 28, 6][4, 29, 6][4, 29, 5][4, 28, 5][4, 28, 4][4, 29, 4][4, 29, 3][4, 28, 3][4, 28, 2][4, 29, 2][4, 29, 1][4, 28, 1][4, 28, 0][4, 29, 0][3, 29, 47][3, 28, 47][3, 28, 46][3, 29, 46][3, 29, 45][3, 28, 45][3, 28, 44][3, 29, 44][3, 29, 43][3, 28, 43][3, 28, 42][3, 29, 42][3, 29, 41][3, 28, 41][3, 28, 40][3, 29, 40]
    Non-inverted[77][76][75][74][73][72][71][70][69][68][67][66][65][64][63][62][61][60][59][58][57][56][55][54][53][52][51][50][49][48][47][46][45][44][43][42][41][40][39][38][37][36][35][34][33][32][31][30][29][28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    +
    + + + + + + + + + +
    CMT:MUX.OUT10[6, 29, 45][6, 28, 45][6, 28, 44]
    DCM1_CLKIN000
    DCM0_CLKIN001
    DCM1_CLKFB010
    DCM0_CLKFB011
    PLL_CLKIN100
    PLL_CLKINFB101
    NONE111
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + +
    PLL:MUX.CLKFBIN[6, 28, 52][6, 29, 52][6, 29, 51][6, 28, 51][6, 28, 50]
    GIOB000000
    GIOB100001
    GIOB200010
    HCLK000011
    HCLK100100
    HCLK200101
    GIOB301000
    GIOB401001
    HCLK301010
    HCLK401011
    GIOB510000
    GIOB610001
    GIOB710010
    HCLK510011
    HCLK610100
    HCLK710101
    GIOB811000
    GIOB911001
    HCLK811010
    HCLK911011
    CLKFBDCM11100
    CLKFBOUT11101
    CKINT111110
    +
    + + + + + + + + + + +
    PLL:MUX.CLK_TO_DCM1[6, 28, 54][6, 29, 55][6, 28, 55]
    CLKOUTDCM0000
    CLKOUTDCM2001
    CLKOUTDCM4010
    NONE011
    CLKOUTDCM1100
    CLKOUTDCM3101
    CLKOUTDCM5110
    CLKFBDCM111
    +
    + + + + +
    PLL:CLKINSEL_MODE[6, 29, 43]
    STATIC0
    DYNAMIC1
    +
    + + + + + + + + + + + + + + + + +
    PLL:MUX.CLKIN[6, 29, 49][6, 28, 49][6, 28, 48][6, 29, 48]
    GIOB0_GIOB50000
    GIOB1_GIOB60001
    GIOB2_GIOB70010
    HCLK0_HCLK50011
    HCLK1_HCLK60100
    HCLK2_HCLK70101
    GIOB3_GIOB81000
    GIOB4_GIOB91001
    HCLK3_HCLK81010
    HCLK4_HCLK91011
    NONE_CLKFBDCM1100
    CLK_FROM_DCM0_NONE1101
    CLK_FROM_DCM1_NONE1110
    CKINT0_NONE1111
    +
    + + + + + + + + + +
    PLL:MUX.CLK_TO_DCM0[6, 28, 53][6, 29, 54][6, 29, 53]
    CLKOUTDCM0000
    CLKOUTDCM2001
    CLKOUTDCM4010
    NONE011
    CLKOUTDCM1100
    CLKOUTDCM3101
    CLKOUTDCM5110
    +
    +
    +

    Tables

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NamePLL:PLL_CPPLL:PLL_RESPLL:PLL_LFHF
    HIGH:12113
    HIGH:1014143
    HIGH:1115143
    HIGH:1215143
    HIGH:131513
    HIGH:141513
    HIGH:151513
    HIGH:161463
    HIGH:171463
    HIGH:181563
    HIGH:1914103
    HIGH:25153
    HIGH:2014103
    HIGH:2115103
    HIGH:2215103
    HIGH:2315103
    HIGH:2415103
    HIGH:2515103
    HIGH:2615103
    HIGH:2713123
    HIGH:2813123
    HIGH:2913123
    HIGH:312153
    HIGH:3014123
    HIGH:3113123
    HIGH:321223
    HIGH:3315103
    HIGH:34723
    HIGH:35723
    HIGH:36723
    HIGH:37623
    HIGH:38623
    HIGH:39623
    HIGH:415153
    HIGH:40623
    HIGH:41623
    HIGH:42443
    HIGH:43443
    HIGH:44443
    HIGH:45383
    HIGH:46383
    HIGH:47343
    HIGH:48343
    HIGH:49343
    HIGH:51573
    HIGH:50343
    HIGH:51343
    HIGH:52343
    HIGH:53343
    HIGH:54343
    HIGH:55343
    HIGH:56343
    HIGH:57283
    HIGH:58283
    HIGH:59283
    HIGH:615133
    HIGH:60283
    HIGH:61283
    HIGH:62283
    HIGH:63283
    HIGH:64283
    HIGH:71533
    HIGH:81553
    HIGH:91593
    LOW:11133
    LOW:10143
    LOW:11143
    LOW:12143
    LOW:13143
    LOW:14143
    LOW:15143
    LOW:16143
    LOW:17143
    LOW:18143
    LOW:19183
    LOW:21143
    LOW:20183
    LOW:21183
    LOW:22183
    LOW:23183
    LOW:24183
    LOW:25183
    LOW:26183
    LOW:27183
    LOW:28183
    LOW:29183
    LOW:3163
    LOW:30183
    LOW:31243
    LOW:32243
    LOW:33243
    LOW:34243
    LOW:35243
    LOW:36243
    LOW:37243
    LOW:38283
    LOW:39283
    LOW:41103
    LOW:40283
    LOW:41283
    LOW:42283
    LOW:43283
    LOW:44283
    LOW:45283
    LOW:46283
    LOW:47283
    LOW:48283
    LOW:49283
    LOW:51123
    LOW:50283
    LOW:51283
    LOW:52283
    LOW:53283
    LOW:54283
    LOW:55283
    LOW:56283
    LOW:57283
    LOW:58283
    LOW:59283
    LOW:61123
    LOW:60283
    LOW:61283
    LOW:62283
    LOW:63283
    LOW:64283
    LOW:71123
    LOW:8123
    LOW:9123
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DevicePLL:PLL_IN_DLY_SET
    [8][7][6][5][4][3][2][1][0]
    xc5vfx100t000011101
    xc5vfx130t000011110
    xc5vfx200t000011111
    xc5vfx30t000011101
    xc5vfx70t000011101
    xc5vlx110000011101
    xc5vlx110t000011101
    xc5vlx155000011101
    xc5vlx155t000011101
    xc5vlx20t000011010
    xc5vlx220000011111
    xc5vlx220t000011111
    xc5vlx30000011100
    xc5vlx30t000011100
    xc5vlx330000011111
    xc5vlx330t000011111
    xc5vlx50000011100
    xc5vlx50t000011100
    xc5vlx85000011101
    xc5vlx85t000011101
    xc5vsx240t000011111
    xc5vsx35t000011101
    xc5vsx50t000011101
    xc5vsx95t000011111
    xc5vtx150t000011101
    xc5vtx240t000011110
    xq5vfx100t000011101
    xq5vfx130t000011110
    xq5vfx200t000011111
    xq5vfx70t000011101
    xq5vlx110000011101
    xq5vlx110t000011101
    xq5vlx155t000011101
    xq5vlx220t000011111
    xq5vlx30t000011100
    xq5vlx330t000011111
    xq5vlx85000011101
    xq5vsx240t000011111
    xq5vsx50t000011101
    xq5vsx95t000011111
    +
    +
    + + +
    +
    + +
    +
    +
    +
    + + + + \ No newline at end of file diff --git a/xilinx/virtex5/config.html b/xilinx/virtex5/config.html index ba7f84b8..32de1b24 100644 --- a/xilinx/virtex5/config.html +++ b/xilinx/virtex5/config.html @@ -64,6 +64,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/dsp.html b/xilinx/virtex5/dsp.html index 23ecb179..5a60b594 100644 --- a/xilinx/virtex5/dsp.html +++ b/xilinx/virtex5/dsp.html @@ -67,6 +67,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/emac.html b/xilinx/virtex5/emac.html index 04906bbf..7ef27c67 100644 --- a/xilinx/virtex5/emac.html +++ b/xilinx/virtex5/emac.html @@ -64,6 +64,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
    • +
  • Clock management tile +
  • PowerPC cores diff --git a/xilinx/virtex5/interconnect.html b/xilinx/virtex5/interconnect.html index c93cdeb1..872e9db5 100644 --- a/xilinx/virtex5/interconnect.html +++ b/xilinx/virtex5/interconnect.html @@ -69,6 +69,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/io.html b/xilinx/virtex5/io.html index 57bc89c1..c79a28db 100644 --- a/xilinx/virtex5/io.html +++ b/xilinx/virtex5/io.html @@ -68,6 +68,7 @@
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex5/pcie.html b/xilinx/virtex5/pcie.html index 84b53cd8..6e37e34d 100644 --- a/xilinx/virtex5/pcie.html +++ b/xilinx/virtex5/pcie.html @@ -64,6 +64,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • PowerPC cores
  • Ethernet MACs
  • PCI Express cores
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • @@ -136,65 +137,7 @@

    BitstreamCFG bittile 6RowColumn - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
    CFG bittile 7
    RowColumn
    012345678910111213141516171819202122232425262728293031323334353637
    0--------------------------------------
    1--------------------------------------
    2--------------------------------------
    3--------------------------------------
    4--------------------------------------
    5--------------------------------------
    6--------------------------------------
    7--------------------------------------
    8--------------------------------------
    9--------------------------------------
    10--------------------------------------
    11--------------------------------------
    12--------------------------------------
    13--------------------------------------
    14--------------------------------------
    15--------------------------------------
    16--------------------------------------
    17--------------------------------------
    18--------------------------------------
    19--------------------------------------
    20--------------------------------------
    21--------------------------------------
    22--------------------------------------
    23-------------------------------------MISC:DCI_CLK_ENABLE[4]
    24------------------------------------MISC:DCI_CLK_ENABLE[0]-
    25------------------------------------MISC:DCI_CLK_ENABLE[1]-
    26-------------------------------------MISC:DCI_CLK_ENABLE[5]
    27------------------------------------MISC:DCI_CLK_ENABLE[2]-
    28------------------------------------MISC:DCI_CLK_ENABLE[3]-
    CFG bittile 7
    RowColumn
    @@ -334,17 +277,17 @@

    BitstreamDCIRESET:ENABLE[1]

    - + - + - + - + - + - + @@ -981,11 +924,6 @@

    BitstreamMISC:DONEPIN

    CFG bittile 8
    RowColumn
    -
    23--------------------------------------
    -------------------------------------MISC:DCI_CLK_ENABLE[4]
    24--------------------------------------
    ------------------------------------MISC:DCI_CLK_ENABLE[0]-
    25--------------------------------------
    ------------------------------------MISC:DCI_CLK_ENABLE[1]-
    26--------------------------------------
    -------------------------------------MISC:DCI_CLK_ENABLE[5]
    27--------------------------------------
    ------------------------------------MISC:DCI_CLK_ENABLE[2]-
    28--------------------------------------
    ------------------------------------MISC:DCI_CLK_ENABLE[3]-
    29 --------------------------------------
    30
     -
    - - - -
    MISC:DCI_CLK_ENABLE[7, 37, 26][7, 37, 23][7, 36, 28][7, 36, 27][7, 36, 25][7, 36, 24]
    Non-inverted[5][4][3][2][1][0]
    @@ -1065,6 +1003,11 @@

    Bitstream + + + +
    MISC:DCI_CLK_ENABLE[27, 37, 26][27, 37, 23][27, 36, 28][27, 36, 27][27, 36, 25][27, 36, 24]
    Non-inverted[5][4][3][2][1][0]
    diff --git a/xilinx/virtex6/clb.html b/xilinx/virtex6/clb.html index ac407097..a170fdc0 100644 --- a/xilinx/virtex6/clb.html +++ b/xilinx/virtex6/clb.html @@ -69,6 +69,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • diff --git a/xilinx/virtex6/clock.html b/xilinx/virtex6/clock.html index 70eedb54..79312b19 100644 --- a/xilinx/virtex6/clock.html +++ b/xilinx/virtex6/clock.html @@ -19,7 +19,7 @@ - + @@ -71,6 +71,7 @@
  • PMVIOB
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • @@ -148,75 +149,75 @@

    HCLK

    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +
    BSCAN_COMMON:USERID[27, 37, 47][27, 36, 47][27, 37, 46][27, 36, 46][27, 37, 45][27, 36, 45][27, 37, 44][27, 36, 44][27, 37, 43][27, 36, 43][27, 37, 42][27, 36, 42][27, 37, 41][27, 36, 41][27, 37, 40][27, 36, 40][27, 37, 39][27, 36, 39][27, 37, 38][27, 36, 38][27, 37, 37][27, 36, 37][27, 37, 36][27, 36, 36][27, 37, 35][27, 36, 35][27, 37, 34][27, 36, 34][27, 37, 33][27, 36, 33][27, 37, 32][27, 36, 32]
    13 -----------------------HCLK:DRP_MASK_SYSMONHCLK:DRP_MASK_BELOWHCLK:DRP_MASK_ABOVE
    14HCLK:MUX.OUT_D2[0]HCLK:MUX.OUT_D2[1]HCLK:MUX.OUT_D3[1]HCLK:MUX.OUT_D3[0]HCLK:MUX.OUT_D6[0]HCLK:MUX.OUT_D6[1]HCLK:MUX.OUT_D7[1]HCLK:MUX.OUT_D7[0]HCLK:ENABLE.RCLK0-----------------
    HCLK:MUX.LCLK2_D[0]HCLK:MUX.LCLK2_D[1]HCLK:MUX.LCLK3_D[1]HCLK:MUX.LCLK3_D[0]HCLK:MUX.LCLK6_D[0]HCLK:MUX.LCLK6_D[1]HCLK:MUX.LCLK7_D[1]HCLK:MUX.LCLK7_D[0]HCLK:ENABLE.RCLK0-----------------
    15HCLK:MUX.OUT_D2[2]HCLK:MUX.OUT_D2[3]HCLK:MUX.OUT_D3[3]HCLK:MUX.OUT_D3[2]HCLK:MUX.OUT_D6[2]HCLK:MUX.OUT_D6[3]HCLK:MUX.OUT_D7[3]HCLK:MUX.OUT_D7[2]HCLK:ENABLE.RCLK1-----------------
    HCLK:MUX.LCLK2_D[2]HCLK:MUX.LCLK2_D[3]HCLK:MUX.LCLK3_D[3]HCLK:MUX.LCLK3_D[2]HCLK:MUX.LCLK6_D[2]HCLK:MUX.LCLK6_D[3]HCLK:MUX.LCLK7_D[3]HCLK:MUX.LCLK7_D[2]HCLK:ENABLE.RCLK1-----------------
    16HCLK:MUX.OUT_D2[4]HCLK:MUX.OUT_D2[5]HCLK:MUX.OUT_D3[5]HCLK:MUX.OUT_D3[4]HCLK:MUX.OUT_D6[4]HCLK:MUX.OUT_D6[5]HCLK:MUX.OUT_D7[5]HCLK:MUX.OUT_D7[4]HCLK:ENABLE.RCLK2-----------------
    HCLK:MUX.LCLK2_D[4]HCLK:MUX.LCLK2_D[5]HCLK:MUX.LCLK3_D[5]HCLK:MUX.LCLK3_D[4]HCLK:MUX.LCLK6_D[4]HCLK:MUX.LCLK6_D[5]HCLK:MUX.LCLK7_D[5]HCLK:MUX.LCLK7_D[4]HCLK:ENABLE.RCLK2-----------------
    17HCLK:MUX.OUT_D2[8]HCLK:MUX.OUT_D2[6]HCLK:MUX.OUT_D3[6]HCLK:MUX.OUT_D3[8]HCLK:MUX.OUT_D6[8]HCLK:MUX.OUT_D6[6]HCLK:MUX.OUT_D7[6]HCLK:MUX.OUT_D7[8]HCLK:ENABLE.RCLK3-----------------
    HCLK:MUX.LCLK2_D[8]HCLK:MUX.LCLK2_D[6]HCLK:MUX.LCLK3_D[6]HCLK:MUX.LCLK3_D[8]HCLK:MUX.LCLK6_D[8]HCLK:MUX.LCLK6_D[6]HCLK:MUX.LCLK7_D[6]HCLK:MUX.LCLK7_D[8]HCLK:ENABLE.RCLK3-----------------
    18HCLK:MUX.OUT_D2[7]HCLK:MUX.OUT_D0[0]HCLK:MUX.OUT_D1[0]HCLK:MUX.OUT_D3[7]HCLK:MUX.OUT_D6[7]HCLK:MUX.OUT_D4[0]HCLK:MUX.OUT_D5[0]HCLK:MUX.OUT_D7[7]HCLK:ENABLE.RCLK4-----------------
    HCLK:MUX.LCLK2_D[7]HCLK:MUX.LCLK0_D[0]HCLK:MUX.LCLK1_D[0]HCLK:MUX.LCLK3_D[7]HCLK:MUX.LCLK6_D[7]HCLK:MUX.LCLK4_D[0]HCLK:MUX.LCLK5_D[0]HCLK:MUX.LCLK7_D[7]HCLK:ENABLE.RCLK4-----------------
    19HCLK:MUX.OUT_D0[1]HCLK:MUX.OUT_D0[2]HCLK:MUX.OUT_D1[2]HCLK:MUX.OUT_D1[1]HCLK:MUX.OUT_D4[1]HCLK:MUX.OUT_D4[2]HCLK:MUX.OUT_D5[2]HCLK:MUX.OUT_D5[1]HCLK:ENABLE.RCLK5-----------------
    HCLK:MUX.LCLK0_D[1]HCLK:MUX.LCLK0_D[2]HCLK:MUX.LCLK1_D[2]HCLK:MUX.LCLK1_D[1]HCLK:MUX.LCLK4_D[1]HCLK:MUX.LCLK4_D[2]HCLK:MUX.LCLK5_D[2]HCLK:MUX.LCLK5_D[1]HCLK:ENABLE.RCLK5-----------------
    20HCLK:MUX.OUT_D0[3]HCLK:MUX.OUT_D0[4]HCLK:MUX.OUT_D1[4]HCLK:MUX.OUT_D1[3]HCLK:MUX.OUT_D4[3]HCLK:MUX.OUT_D4[4]HCLK:MUX.OUT_D5[4]HCLK:MUX.OUT_D5[3]HCLK:ENABLE.HCLK0-----------------
    HCLK:MUX.LCLK0_D[3]HCLK:MUX.LCLK0_D[4]HCLK:MUX.LCLK1_D[4]HCLK:MUX.LCLK1_D[3]HCLK:MUX.LCLK4_D[3]HCLK:MUX.LCLK4_D[4]HCLK:MUX.LCLK5_D[4]HCLK:MUX.LCLK5_D[3]HCLK:ENABLE.HCLK0-----------------
    21HCLK:MUX.OUT_D0[5]HCLK:MUX.OUT_D0[8]HCLK:MUX.OUT_D1[8]HCLK:MUX.OUT_D1[5]HCLK:MUX.OUT_D4[5]HCLK:MUX.OUT_D4[8]HCLK:MUX.OUT_D5[8]HCLK:MUX.OUT_D5[5]HCLK:ENABLE.HCLK1-----------------
    HCLK:MUX.LCLK0_D[5]HCLK:MUX.LCLK0_D[8]HCLK:MUX.LCLK1_D[8]HCLK:MUX.LCLK1_D[5]HCLK:MUX.LCLK4_D[5]HCLK:MUX.LCLK4_D[8]HCLK:MUX.LCLK5_D[8]HCLK:MUX.LCLK5_D[5]HCLK:ENABLE.HCLK1-----------------
    22HCLK:MUX.OUT_D0[6]HCLK:MUX.OUT_D0[7]HCLK:MUX.OUT_D1[7]HCLK:MUX.OUT_D1[6]HCLK:MUX.OUT_D4[6]HCLK:MUX.OUT_D4[7]HCLK:MUX.OUT_D5[7]HCLK:MUX.OUT_D5[6]HCLK:ENABLE.HCLK2-----------------
    HCLK:MUX.LCLK0_D[6]HCLK:MUX.LCLK0_D[7]HCLK:MUX.LCLK1_D[7]HCLK:MUX.LCLK1_D[6]HCLK:MUX.LCLK4_D[6]HCLK:MUX.LCLK4_D[7]HCLK:MUX.LCLK5_D[7]HCLK:MUX.LCLK5_D[6]HCLK:ENABLE.HCLK2-----------------
    23HCLK:MUX.OUT_U2[0]HCLK:MUX.OUT_U2[1]HCLK:MUX.OUT_U3[1]HCLK:MUX.OUT_U3[0]HCLK:MUX.OUT_U6[0]HCLK:MUX.OUT_U6[1]HCLK:MUX.OUT_U7[1]HCLK:MUX.OUT_U7[0]HCLK:ENABLE.HCLK3-----------------
    HCLK:MUX.LCLK2_U[0]HCLK:MUX.LCLK2_U[1]HCLK:MUX.LCLK3_U[1]HCLK:MUX.LCLK3_U[0]HCLK:MUX.LCLK6_U[0]HCLK:MUX.LCLK6_U[1]HCLK:MUX.LCLK7_U[1]HCLK:MUX.LCLK7_U[0]HCLK:ENABLE.HCLK3-----------------
    24HCLK:MUX.OUT_U2[2]HCLK:MUX.OUT_U2[3]HCLK:MUX.OUT_U3[3]HCLK:MUX.OUT_U3[2]HCLK:MUX.OUT_U6[2]HCLK:MUX.OUT_U6[3]HCLK:MUX.OUT_U7[3]HCLK:MUX.OUT_U7[2]HCLK:ENABLE.HCLK4-----------------
    HCLK:MUX.LCLK2_U[2]HCLK:MUX.LCLK2_U[3]HCLK:MUX.LCLK3_U[3]HCLK:MUX.LCLK3_U[2]HCLK:MUX.LCLK6_U[2]HCLK:MUX.LCLK6_U[3]HCLK:MUX.LCLK7_U[3]HCLK:MUX.LCLK7_U[2]HCLK:ENABLE.HCLK4-----------------
    25HCLK:MUX.OUT_U2[4]HCLK:MUX.OUT_U2[5]HCLK:MUX.OUT_U3[5]HCLK:MUX.OUT_U3[4]HCLK:MUX.OUT_U6[4]HCLK:MUX.OUT_U6[5]HCLK:MUX.OUT_U7[5]HCLK:MUX.OUT_U7[4]HCLK:ENABLE.HCLK5-----------------
    HCLK:MUX.LCLK2_U[4]HCLK:MUX.LCLK2_U[5]HCLK:MUX.LCLK3_U[5]HCLK:MUX.LCLK3_U[4]HCLK:MUX.LCLK6_U[4]HCLK:MUX.LCLK6_U[5]HCLK:MUX.LCLK7_U[5]HCLK:MUX.LCLK7_U[4]HCLK:ENABLE.HCLK5-----------------
    26HCLK:MUX.OUT_U2[8]HCLK:MUX.OUT_U2[6]HCLK:MUX.OUT_U3[6]HCLK:MUX.OUT_U3[8]HCLK:MUX.OUT_U6[8]HCLK:MUX.OUT_U6[6]HCLK:MUX.OUT_U7[6]HCLK:MUX.OUT_U7[8]HCLK:ENABLE.HCLK6-----------------
    HCLK:MUX.LCLK2_U[8]HCLK:MUX.LCLK2_U[6]HCLK:MUX.LCLK3_U[6]HCLK:MUX.LCLK3_U[8]HCLK:MUX.LCLK6_U[8]HCLK:MUX.LCLK6_U[6]HCLK:MUX.LCLK7_U[6]HCLK:MUX.LCLK7_U[8]HCLK:ENABLE.HCLK6-----------------
    27HCLK:MUX.OUT_U2[7]HCLK:MUX.OUT_U0[0]HCLK:MUX.OUT_U1[0]HCLK:MUX.OUT_U3[7]HCLK:MUX.OUT_U6[7]HCLK:MUX.OUT_U4[0]HCLK:MUX.OUT_U5[0]HCLK:MUX.OUT_U7[7]HCLK:ENABLE.HCLK7-----------------
    HCLK:MUX.LCLK2_U[7]HCLK:MUX.LCLK0_U[0]HCLK:MUX.LCLK1_U[0]HCLK:MUX.LCLK3_U[7]HCLK:MUX.LCLK6_U[7]HCLK:MUX.LCLK4_U[0]HCLK:MUX.LCLK5_U[0]HCLK:MUX.LCLK7_U[7]HCLK:ENABLE.HCLK7-----------------
    28HCLK:MUX.OUT_U0[1]HCLK:MUX.OUT_U0[2]HCLK:MUX.OUT_U1[2]HCLK:MUX.OUT_U1[1]HCLK:MUX.OUT_U4[1]HCLK:MUX.OUT_U4[2]HCLK:MUX.OUT_U5[2]HCLK:MUX.OUT_U5[1]HCLK:ENABLE.HCLK8-----------------
    HCLK:MUX.LCLK0_U[1]HCLK:MUX.LCLK0_U[2]HCLK:MUX.LCLK1_U[2]HCLK:MUX.LCLK1_U[1]HCLK:MUX.LCLK4_U[1]HCLK:MUX.LCLK4_U[2]HCLK:MUX.LCLK5_U[2]HCLK:MUX.LCLK5_U[1]HCLK:ENABLE.HCLK8-----------------
    29HCLK:MUX.OUT_U0[3]HCLK:MUX.OUT_U0[4]HCLK:MUX.OUT_U1[4]HCLK:MUX.OUT_U1[3]HCLK:MUX.OUT_U4[3]HCLK:MUX.OUT_U4[4]HCLK:MUX.OUT_U5[4]HCLK:MUX.OUT_U5[3]HCLK:ENABLE.HCLK9-----------------
    HCLK:MUX.LCLK0_U[3]HCLK:MUX.LCLK0_U[4]HCLK:MUX.LCLK1_U[4]HCLK:MUX.LCLK1_U[3]HCLK:MUX.LCLK4_U[3]HCLK:MUX.LCLK4_U[4]HCLK:MUX.LCLK5_U[4]HCLK:MUX.LCLK5_U[3]HCLK:ENABLE.HCLK9-----------------
    30HCLK:MUX.OUT_U0[5]HCLK:MUX.OUT_U0[8]HCLK:MUX.OUT_U1[8]HCLK:MUX.OUT_U1[5]HCLK:MUX.OUT_U4[5]HCLK:MUX.OUT_U4[8]HCLK:MUX.OUT_U5[8]HCLK:MUX.OUT_U5[5]HCLK:ENABLE.HCLK10-----------------
    HCLK:MUX.LCLK0_U[5]HCLK:MUX.LCLK0_U[8]HCLK:MUX.LCLK1_U[8]HCLK:MUX.LCLK1_U[5]HCLK:MUX.LCLK4_U[5]HCLK:MUX.LCLK4_U[8]HCLK:MUX.LCLK5_U[8]HCLK:MUX.LCLK5_U[5]HCLK:ENABLE.HCLK10-----------------
    31HCLK:MUX.OUT_U0[6]HCLK:MUX.OUT_U0[7]HCLK:MUX.OUT_U1[7]HCLK:MUX.OUT_U1[6]HCLK:MUX.OUT_U4[6]HCLK:MUX.OUT_U4[7]HCLK:MUX.OUT_U5[7]HCLK:MUX.OUT_U5[6]HCLK:ENABLE.HCLK11-----------------
    HCLK:MUX.LCLK0_U[6]HCLK:MUX.LCLK0_U[7]HCLK:MUX.LCLK1_U[7]HCLK:MUX.LCLK1_U[6]HCLK:MUX.LCLK4_U[6]HCLK:MUX.LCLK4_U[7]HCLK:MUX.LCLK5_U[7]HCLK:MUX.LCLK5_U[6]HCLK:ENABLE.HCLK11-----------------
     -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -1985,7 +1986,7 @@

    PMVIOB

    HCLK:MUX.OUT_D0[0, 1, 21][0, 1, 22][0, 0, 22][0, 0, 21][0, 1, 20][0, 0, 20][0, 1, 19][0, 0, 19][0, 1, 18]
    HCLK:MUX.OUT_D1[0, 2, 21][0, 2, 22][0, 3, 22][0, 3, 21][0, 2, 20][0, 3, 20][0, 2, 19][0, 3, 19][0, 2, 18]
    HCLK:MUX.OUT_D2[0, 0, 17][0, 0, 18][0, 1, 17][0, 1, 16][0, 0, 16][0, 1, 15][0, 0, 15][0, 1, 14][0, 0, 14]
    HCLK:MUX.OUT_D3[0, 3, 17][0, 3, 18][0, 2, 17][0, 2, 16][0, 3, 16][0, 2, 15][0, 3, 15][0, 2, 14][0, 3, 14]
    HCLK:MUX.OUT_D4[0, 5, 21][0, 5, 22][0, 4, 22][0, 4, 21][0, 5, 20][0, 4, 20][0, 5, 19][0, 4, 19][0, 5, 18]
    HCLK:MUX.OUT_D5[0, 6, 21][0, 6, 22][0, 7, 22][0, 7, 21][0, 6, 20][0, 7, 20][0, 6, 19][0, 7, 19][0, 6, 18]
    HCLK:MUX.OUT_D6[0, 4, 17][0, 4, 18][0, 5, 17][0, 5, 16][0, 4, 16][0, 5, 15][0, 4, 15][0, 5, 14][0, 4, 14]
    HCLK:MUX.OUT_D7[0, 7, 17][0, 7, 18][0, 6, 17][0, 6, 16][0, 7, 16][0, 6, 15][0, 7, 15][0, 6, 14][0, 7, 14]
    HCLK:MUX.OUT_U0[0, 1, 30][0, 1, 31][0, 0, 31][0, 0, 30][0, 1, 29][0, 0, 29][0, 1, 28][0, 0, 28][0, 1, 27]
    HCLK:MUX.OUT_U1[0, 2, 30][0, 2, 31][0, 3, 31][0, 3, 30][0, 2, 29][0, 3, 29][0, 2, 28][0, 3, 28][0, 2, 27]
    HCLK:MUX.OUT_U2[0, 0, 26][0, 0, 27][0, 1, 26][0, 1, 25][0, 0, 25][0, 1, 24][0, 0, 24][0, 1, 23][0, 0, 23]
    HCLK:MUX.OUT_U3[0, 3, 26][0, 3, 27][0, 2, 26][0, 2, 25][0, 3, 25][0, 2, 24][0, 3, 24][0, 2, 23][0, 3, 23]
    HCLK:MUX.OUT_U4[0, 5, 30][0, 5, 31][0, 4, 31][0, 4, 30][0, 5, 29][0, 4, 29][0, 5, 28][0, 4, 28][0, 5, 27]
    HCLK:MUX.OUT_U5[0, 6, 30][0, 6, 31][0, 7, 31][0, 7, 30][0, 6, 29][0, 7, 29][0, 6, 28][0, 7, 28][0, 6, 27]
    HCLK:MUX.OUT_U6[0, 4, 26][0, 4, 27][0, 5, 26][0, 5, 25][0, 4, 25][0, 5, 24][0, 4, 24][0, 5, 23][0, 4, 23]
    HCLK:MUX.OUT_U7[0, 7, 26][0, 7, 27][0, 6, 26][0, 6, 25][0, 7, 25][0, 6, 24][0, 7, 24][0, 6, 23][0, 7, 23]
    HCLK:MUX.LCLK0_D[0, 1, 21][0, 1, 22][0, 0, 22][0, 0, 21][0, 1, 20][0, 0, 20][0, 1, 19][0, 0, 19][0, 1, 18]
    HCLK:MUX.LCLK0_U[0, 1, 30][0, 1, 31][0, 0, 31][0, 0, 30][0, 1, 29][0, 0, 29][0, 1, 28][0, 0, 28][0, 1, 27]
    HCLK:MUX.LCLK1_D[0, 2, 21][0, 2, 22][0, 3, 22][0, 3, 21][0, 2, 20][0, 3, 20][0, 2, 19][0, 3, 19][0, 2, 18]
    HCLK:MUX.LCLK1_U[0, 2, 30][0, 2, 31][0, 3, 31][0, 3, 30][0, 2, 29][0, 3, 29][0, 2, 28][0, 3, 28][0, 2, 27]
    HCLK:MUX.LCLK2_D[0, 0, 17][0, 0, 18][0, 1, 17][0, 1, 16][0, 0, 16][0, 1, 15][0, 0, 15][0, 1, 14][0, 0, 14]
    HCLK:MUX.LCLK2_U[0, 0, 26][0, 0, 27][0, 1, 26][0, 1, 25][0, 0, 25][0, 1, 24][0, 0, 24][0, 1, 23][0, 0, 23]
    HCLK:MUX.LCLK3_D[0, 3, 17][0, 3, 18][0, 2, 17][0, 2, 16][0, 3, 16][0, 2, 15][0, 3, 15][0, 2, 14][0, 3, 14]
    HCLK:MUX.LCLK3_U[0, 3, 26][0, 3, 27][0, 2, 26][0, 2, 25][0, 3, 25][0, 2, 24][0, 3, 24][0, 2, 23][0, 3, 23]
    HCLK:MUX.LCLK4_D[0, 5, 21][0, 5, 22][0, 4, 22][0, 4, 21][0, 5, 20][0, 4, 20][0, 5, 19][0, 4, 19][0, 5, 18]
    HCLK:MUX.LCLK4_U[0, 5, 30][0, 5, 31][0, 4, 31][0, 4, 30][0, 5, 29][0, 4, 29][0, 5, 28][0, 4, 28][0, 5, 27]
    HCLK:MUX.LCLK5_D[0, 6, 21][0, 6, 22][0, 7, 22][0, 7, 21][0, 6, 20][0, 7, 20][0, 6, 19][0, 7, 19][0, 6, 18]
    HCLK:MUX.LCLK5_U[0, 6, 30][0, 6, 31][0, 7, 31][0, 7, 30][0, 6, 29][0, 7, 29][0, 6, 28][0, 7, 28][0, 6, 27]
    HCLK:MUX.LCLK6_D[0, 4, 17][0, 4, 18][0, 5, 17][0, 5, 16][0, 4, 16][0, 5, 15][0, 4, 15][0, 5, 14][0, 4, 14]
    HCLK:MUX.LCLK6_U[0, 4, 26][0, 4, 27][0, 5, 26][0, 5, 25][0, 4, 25][0, 5, 24][0, 4, 24][0, 5, 23][0, 4, 23]
    HCLK:MUX.LCLK7_D[0, 7, 17][0, 7, 18][0, 6, 17][0, 6, 16][0, 7, 16][0, 6, 15][0, 7, 15][0, 6, 14][0, 7, 14]
    HCLK:MUX.LCLK7_U[0, 7, 26][0, 7, 27][0, 6, 26][0, 6, 25][0, 7, 25][0, 6, 24][0, 7, 24][0, 6, 23][0, 7, 23]
    NONE000000000
    HCLK0001000001
    HCLK1001000010
    + +
    CMT bittile 0
    RowColumn
    + + +
    CMT bittile 1
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 2
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP7F[14]MMCM0:DRP7F[15]
    1--------------------------MMCM0:DRP7F[12]MMCM0:DRP7F[13]
    2--------------------------MMCM0:DRP7F[10]MMCM0:DRP7F[11]
    3--------------------------MMCM0:DRP7F[8]MMCM0:DRP7F[9]
    4--------------------------MMCM0:DRP7F[6]MMCM0:DRP7F[7]
    5--------------------------MMCM0:DRP7F[4]MMCM0:DRP7F[5]
    6--------------------------MMCM0:DRP7F[2]MMCM0:DRP7F[3]
    7--------------------------MMCM0:DRP7F[0]MMCM0:DRP7F[1]
    8--------------------------MMCM0:DRP7E[14]MMCM0:DRP7E[15]
    9--------------------------MMCM0:DRP7E[12]MMCM0:DRP7E[13]
    10--------------------------MMCM0:DRP7E[10]MMCM0:DRP7E[11]
    11--------------------------MMCM0:DRP7E[8]MMCM0:DRP7E[9]
    12--------------------------MMCM0:DRP7E[6]MMCM0:DRP7E[7]
    13--------------------------MMCM0:DRP7E[4]MMCM0:DRP7E[5]
    14--------------------------MMCM0:DRP7E[2]MMCM0:DRP7E[3]
    15--------------------------MMCM0:DRP7E[0]MMCM0:DRP7E[1]
    16--------------------------MMCM0:DRP7D[14]MMCM0:DRP7D[15]
    17--------------------------MMCM0:DRP7D[12]MMCM0:DRP7D[13]
    18--------------------------MMCM0:DRP7D[10]MMCM0:DRP7D[11]
    19--------------------------MMCM0:DRP7D[8]MMCM0:DRP7D[9]
    20--------------------------MMCM0:DRP7D[6]MMCM0:DRP7D[7]
    21--------------------------MMCM0:DRP7D[4]MMCM0:DRP7D[5]
    22--------------------------MMCM0:DRP7D[2]MMCM0:DRP7D[3]
    23--------------------------MMCM0:DRP7D[0]MMCM0:DRP7D[1]
    24--------------------------MMCM0:DRP7C[14]MMCM0:DRP7C[15]
    25--------------------------MMCM0:DRP7C[12]MMCM0:DRP7C[13]
    26--------------------------MMCM0:DRP7C[10]MMCM0:DRP7C[11]
    27--------------------------MMCM0:DRP7C[8]MMCM0:DRP7C[9]
    28--------------------------MMCM0:DRP7C[6]MMCM0:DRP7C[7]
    29--------------------------MMCM0:DRP7C[4]MMCM0:DRP7C[5]
    30--------------------------MMCM0:DRP7C[2]MMCM0:DRP7C[3]
    31--------------------------MMCM0:DRP7C[0]MMCM0:DRP7C[1]
    32--------------------------MMCM0:CONTROL_5[14]
    MMCM0:DRP7B[14]    		MMCM0:CONTROL_5[15]
    MMCM0:DRP7B[15]
    33--------------------------MMCM0:CONTROL_5[12]
    MMCM0:DRP7B[12]    		MMCM0:CONTROL_5[13]
    MMCM0:DRP7B[13]
    34--------------------------MMCM0:CONTROL_5[10]
    MMCM0:DRP7B[10]    		MMCM0:CONTROL_5[11]
    MMCM0:DRP7B[11]
    35--------------------------MMCM0:CONTROL_5[8]
    MMCM0:DRP7B[8]    		MMCM0:CONTROL_5[9]
    MMCM0:DRP7B[9]
    36--------------------------MMCM0:CONTROL_5[6]
    MMCM0:DRP7B[6]    		MMCM0:CONTROL_5[7]
    MMCM0:DRP7B[7]
    37--------------------------MMCM0:CONTROL_5[4]
    MMCM0:DRP7B[4]    		MMCM0:CONTROL_5[5]
    MMCM0:DRP7B[5]
    38--------------------------MMCM0:CONTROL_5[2]
    MMCM0:DRP7B[2]    		MMCM0:CONTROL_5[3]
    MMCM0:DRP7B[3]
    39--------------------------MMCM0:CONTROL_5[0]
    MMCM0:DRP7B[0]    		MMCM0:CONTROL_5[1]
    MMCM0:DRP7B[1]
    40--------------------------MMCM0:CONTROL_4[14]
    MMCM0:DRP7A[14]    		MMCM0:CONTROL_4[15]
    MMCM0:DRP7A[15]
    41--------------------------MMCM0:CONTROL_4[12]
    MMCM0:DRP7A[12]    		MMCM0:CONTROL_4[13]
    MMCM0:DRP7A[13]
    42--------------------------MMCM0:CONTROL_4[10]
    MMCM0:DRP7A[10]    		MMCM0:CONTROL_4[11]
    MMCM0:DRP7A[11]
    43--------------------------MMCM0:CONTROL_4[8]
    MMCM0:DRP7A[8]    		MMCM0:CONTROL_4[9]
    MMCM0:DRP7A[9]
    44--------------------------MMCM0:CONTROL_4[6]
    MMCM0:DRP7A[6]    		MMCM0:CONTROL_4[7]
    MMCM0:DRP7A[7]
    45--------------------------MMCM0:CONTROL_4[4]
    MMCM0:DRP7A[4]    		MMCM0:CONTROL_4[5]
    MMCM0:DRP7A[5]
    46--------------------------MMCM0:CONTROL_4[2]
    MMCM0:DRP7A[2]    		MMCM0:CONTROL_4[3]
    MMCM0:DRP7A[3]
    47--------------------------MMCM0:CONTROL_4[0]
    MMCM0:DRP7A[0]    		MMCM0:CONTROL_4[1]
    MMCM0:DRP7A[1]
    48--------------------------MMCM0:CONTROL_3[14]
    MMCM0:DRP79[14]    		MMCM0:CONTROL_3[15]
    MMCM0:DRP79[15]
    49--------------------------MMCM0:CONTROL_3[12]
    MMCM0:DRP79[12]    		MMCM0:CONTROL_3[13]
    MMCM0:DRP79[13]
    50--------------------------MMCM0:CONTROL_3[10]
    MMCM0:DRP79[10]    		MMCM0:CONTROL_3[11]
    MMCM0:DRP79[11]
    51--------------------------MMCM0:CONTROL_3[8]
    MMCM0:DRP79[8]    		MMCM0:CONTROL_3[9]
    MMCM0:DRP79[9]
    52--------------------------MMCM0:CONTROL_3[6]
    MMCM0:DRP79[6]    		MMCM0:CONTROL_3[7]
    MMCM0:DRP79[7]
    53--------------------------MMCM0:CONTROL_3[4]
    MMCM0:DRP79[4]    		MMCM0:CONTROL_3[5]
    MMCM0:DRP79[5]
    54--------------------------MMCM0:CONTROL_3[2]
    MMCM0:DRP79[2]    		MMCM0:CONTROL_3[3]
    MMCM0:DRP79[3]
    55--------------------------MMCM0:CONTROL_3[0]
    MMCM0:DRP79[0]    		MMCM0:CONTROL_3[1]
    MMCM0:DRP79[1]
    56--------------------------MMCM0:CONTROL_2[14]
    MMCM0:DRP78[14]    		MMCM0:CONTROL_2[15]
    MMCM0:DRP78[15]
    57--------------------------MMCM0:CONTROL_2[12]
    MMCM0:DRP78[12]    		MMCM0:CONTROL_2[13]
    MMCM0:DRP78[13]
    58--------------------------MMCM0:CONTROL_2[10]
    MMCM0:DRP78[10]    		MMCM0:CONTROL_2[11]
    MMCM0:DRP78[11]
    59--------------------------MMCM0:CONTROL_2[8]
    MMCM0:DRP78[8]    		MMCM0:CONTROL_2[9]
    MMCM0:DRP78[9]
    60--------------------------MMCM0:CONTROL_2[6]
    MMCM0:DRP78[6]    		MMCM0:CONTROL_2[7]
    MMCM0:DRP78[7]
    61--------------------------MMCM0:CONTROL_2[4]
    MMCM0:DRP78[4]    		MMCM0:CONTROL_2[5]
    MMCM0:DRP78[5]
    62--------------------------MMCM0:CONTROL_2[2]
    MMCM0:DRP78[2]    		MMCM0:CONTROL_2[3]
    MMCM0:DRP78[3]
    63--------------------------MMCM0:CONTROL_2[0]
    MMCM0:DRP78[0]    		MMCM0:CONTROL_2[1]
    MMCM0:DRP78[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 3
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:CONTROL_1[14]
    MMCM0:DRP77[14]    		MMCM0:CONTROL_1[15]
    MMCM0:DRP77[15]
    1--------------------------MMCM0:CONTROL_1[12]
    MMCM0:DRP77[12]    		MMCM0:CONTROL_1[13]
    MMCM0:DRP77[13]
    2--------------------------MMCM0:CONTROL_1[10]
    MMCM0:DRP77[10]    		MMCM0:CONTROL_1[11]
    MMCM0:DRP77[11]
    3--------------------------MMCM0:CONTROL_1[8]
    MMCM0:DRP77[8]    		MMCM0:CONTROL_1[9]
    MMCM0:DRP77[9]
    4--------------------------MMCM0:CONTROL_1[6]
    MMCM0:DRP77[6]    		MMCM0:CONTROL_1[7]
    MMCM0:DRP77[7]
    5--------------------------MMCM0:CONTROL_1[4]
    MMCM0:DRP77[4]    		MMCM0:CONTROL_1[5]
    MMCM0:DRP77[5]
    6--------------------------MMCM0:CONTROL_1[2]
    MMCM0:DRP77[2]    		MMCM0:CONTROL_1[3]
    MMCM0:DRP77[3]
    7--------------------------MMCM0:CONTROL_1[0]
    MMCM0:DRP77[0]    		MMCM0:CONTROL_1[1]
    MMCM0:DRP77[1]
    8--------------------------MMCM0:CONTROL_0[14]
    MMCM0:DRP76[14]    		MMCM0:CONTROL_0[15]
    MMCM0:DRP76[15]
    9--------------------------MMCM0:CONTROL_0[12]
    MMCM0:DRP76[12]    		MMCM0:CONTROL_0[13]
    MMCM0:DRP76[13]
    10--------------------------MMCM0:CONTROL_0[10]
    MMCM0:DRP76[10]    		MMCM0:CONTROL_0[11]
    MMCM0:DRP76[11]
    11--------------------------MMCM0:CONTROL_0[8]
    MMCM0:DRP76[8]    		MMCM0:CONTROL_0[9]
    MMCM0:DRP76[9]
    12--------------------------MMCM0:CONTROL_0[6]
    MMCM0:DRP76[6]    		MMCM0:CONTROL_0[7]
    MMCM0:DRP76[7]
    13--------------------------MMCM0:CONTROL_0[4]
    MMCM0:DRP76[4]    		MMCM0:CONTROL_0[5]
    MMCM0:DRP76[5]
    14--------------------------MMCM0:CONTROL_0[2]
    MMCM0:DRP76[2]    		MMCM0:CONTROL_0[3]
    MMCM0:DRP76[3]
    15--------------------------MMCM0:CONTROL_0[0]
    MMCM0:DRP76[0]    		MMCM0:CONTROL_0[1]
    MMCM0:DRP76[1]
    16--------------------------MMCM0:DRP75[14]MMCM0:DRP75[15]
    17--------------------------MMCM0:DRP75[12]MMCM0:DRP75[13]
    18--------------------------MMCM0:DRP75[10]MMCM0:DRP75[11]
    19--------------------------MMCM0:DRP75[8]MMCM0:DRP75[9]
    20--------------------------MMCM0:DRP75[6]MMCM0:DRP75[7]
    21--------------------------MMCM0:DRP75[4]MMCM0:DRP75[5]
    22--------------------------MMCM0:DRP75[2]MMCM0:DRP75[3]
    23--------------------------MMCM0:DRP75[0]MMCM0:DRP75[1]
    24--------------------------MMCM0:DRP74[14]MMCM0:DRP74[15]
    25--------------------------MMCM0:DRP74[12]MMCM0:DRP74[13]
    26--------------------------MMCM0:DRP74[10]
    MMCM0:FINE_PS_FRAC[5]    		MMCM0:DRP74[11]
    27--------------------------MMCM0:DRP74[8]
    MMCM0:FINE_PS_FRAC[3]    		MMCM0:DRP74[9]
    MMCM0:FINE_PS_FRAC[4]
    28--------------------------MMCM0:DRP74[6]
    MMCM0:FINE_PS_FRAC[1]    		MMCM0:DRP74[7]
    MMCM0:FINE_PS_FRAC[2]
    29--------------------------MMCM0:CASC_LOCK_EN
    MMCM0:DRP74[4]    		MMCM0:DRP74[5]
    MMCM0:FINE_PS_FRAC[0]
    30--------------------------MMCM0:DRP74[2]
    MMCM0:STARTUP_WAIT    		MMCM0:DRP74[3]
    MMCM0:GTS_WAIT
    31--------------------------MMCM0:DRP74[0]
    MMCM0:MMCM_EN    		MMCM0:CLOCK_HOLD
    MMCM0:DRP74[1]
    32--------------------------MMCM0:DRP73[14]MMCM0:DRP73[15]
    33--------------------------MMCM0:DRP73[12]MMCM0:DRP73[13]
    34--------------------------MMCM0:DRP73[10]MMCM0:DRP73[11]
    35--------------------------MMCM0:DRP73[8]MMCM0:DRP73[9]
    36--------------------------MMCM0:DRP73[6]MMCM0:DRP73[7]
    37--------------------------MMCM0:DRP73[4]MMCM0:DRP73[5]
    38--------------------------MMCM0:DRP73[2]MMCM0:DRP73[3]
    39--------------------------MMCM0:DRP73[0]MMCM0:DRP73[1]
    40--------------------------MMCM0:DRP72[14]MMCM0:DRP72[15]
    41--------------------------MMCM0:DRP72[12]MMCM0:DRP72[13]
    42--------------------------MMCM0:DRP72[10]MMCM0:DRP72[11]
    43--------------------------MMCM0:DRP72[8]MMCM0:DRP72[9]
    44--------------------------MMCM0:DRP72[6]MMCM0:DRP72[7]
    45--------------------------MMCM0:DRP72[4]
    MMCM0:INV.CLKINSEL    		MMCM0:DRP72[5]
    46--------------------------MMCM0:DRP72[2]
    MMCM0:INV.PSINCDEC    		MMCM0:DRP72[3]
    MMCM0:INV.PSEN
    47--------------------------MMCM0:DRP72[0]
    MMCM0:INV.RST    		MMCM0:DRP72[1]
    MMCM0:INV.PWRDWN
    48--------------------------MMCM0:DRP71[14]MMCM0:DRP71[15]
    49--------------------------MMCM0:DRP71[12]MMCM0:DRP71[13]
    50--------------------------MMCM0:DRP71[10]MMCM0:DRP71[11]
    51--------------------------MMCM0:DRP71[8]MMCM0:DRP71[9]
    52--------------------------MMCM0:DRP71[6]MMCM0:DRP71[7]
    53--------------------------MMCM0:DRP71[4]MMCM0:DRP71[5]
    54--------------------------MMCM0:DRP71[2]MMCM0:DRP71[3]
    55--------------------------MMCM0:DRP71[0]MMCM0:DRP71[1]
    56--------------------------MMCM0:DRP70[14]MMCM0:DRP70[15]
    57--------------------------MMCM0:DRP70[12]MMCM0:DRP70[13]
    58--------------------------MMCM0:DRP70[10]MMCM0:DRP70[11]
    59--------------------------MMCM0:DRP70[8]MMCM0:DRP70[9]
    60--------------------------MMCM0:DRP70[6]MMCM0:DRP70[7]
    61--------------------------MMCM0:DRP70[4]MMCM0:DRP70[5]
    62--------------------------MMCM0:DRP70[2]MMCM0:DRP70[3]
    63--------------------------MMCM0:DRP70[0]MMCM0:DRP70[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 4
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP6F[14]MMCM0:DRP6F[15]
    1--------------------------MMCM0:DRP6F[12]MMCM0:DRP6F[13]
    2--------------------------MMCM0:DRP6F[10]MMCM0:DRP6F[11]
    3--------------------------MMCM0:DRP6F[8]MMCM0:DRP6F[9]
    4--------------------------MMCM0:DRP6F[6]MMCM0:DRP6F[7]
    5--------------------------MMCM0:DRP6F[4]MMCM0:DRP6F[5]
    6--------------------------MMCM0:DRP6F[2]MMCM0:DRP6F[3]
    7--------------------------MMCM0:DRP6F[0]MMCM0:DRP6F[1]
    8--------------------------MMCM0:DRP6E[14]MMCM0:DRP6E[15]
    9--------------------------MMCM0:DRP6E[12]MMCM0:DRP6E[13]
    10--------------------------MMCM0:DRP6E[10]MMCM0:DRP6E[11]
    11--------------------------MMCM0:DRP6E[8]MMCM0:DRP6E[9]
    12--------------------------MMCM0:DRP6E[6]MMCM0:DRP6E[7]
    13--------------------------MMCM0:DRP6E[4]MMCM0:DRP6E[5]
    14--------------------------MMCM0:DRP6E[2]MMCM0:DRP6E[3]
    15--------------------------MMCM0:DRP6E[0]MMCM0:DRP6E[1]
    16--------------------------MMCM0:DRP6D[14]MMCM0:DRP6D[15]
    17--------------------------MMCM0:DRP6D[12]MMCM0:DRP6D[13]
    18--------------------------MMCM0:DRP6D[10]MMCM0:DRP6D[11]
    19--------------------------MMCM0:DRP6D[8]MMCM0:DRP6D[9]
    20--------------------------MMCM0:DRP6D[6]MMCM0:DRP6D[7]
    21--------------------------MMCM0:DRP6D[4]MMCM0:DRP6D[5]
    22--------------------------MMCM0:DRP6D[2]MMCM0:DRP6D[3]
    23--------------------------MMCM0:DRP6D[0]MMCM0:DRP6D[1]
    24--------------------------MMCM0:DRP6C[14]MMCM0:DRP6C[15]
    25--------------------------MMCM0:DRP6C[12]MMCM0:DRP6C[13]
    26--------------------------MMCM0:DRP6C[10]MMCM0:DRP6C[11]
    27--------------------------MMCM0:DRP6C[8]MMCM0:DRP6C[9]
    28--------------------------MMCM0:DRP6C[6]MMCM0:DRP6C[7]
    29--------------------------MMCM0:DRP6C[4]MMCM0:DRP6C[5]
    30--------------------------MMCM0:DRP6C[2]MMCM0:DRP6C[3]
    31--------------------------MMCM0:DRP6C[0]MMCM0:DRP6C[1]
    32--------------------------MMCM0:DRP6B[14]MMCM0:DRP6B[15]
    33--------------------------MMCM0:DRP6B[12]MMCM0:DRP6B[13]
    34--------------------------MMCM0:DRP6B[10]MMCM0:DRP6B[11]
    35--------------------------MMCM0:DRP6B[8]MMCM0:DRP6B[9]
    36--------------------------MMCM0:DRP6B[6]MMCM0:DRP6B[7]
    37--------------------------MMCM0:DRP6B[4]MMCM0:DRP6B[5]
    38--------------------------MMCM0:DRP6B[2]MMCM0:DRP6B[3]
    39--------------------------MMCM0:DRP6B[0]MMCM0:DRP6B[1]
    40--------------------------MMCM0:DRP6A[14]MMCM0:DRP6A[15]
    41--------------------------MMCM0:DRP6A[12]MMCM0:DRP6A[13]
    42--------------------------MMCM0:DRP6A[10]MMCM0:DRP6A[11]
    43--------------------------MMCM0:DRP6A[8]MMCM0:DRP6A[9]
    44--------------------------MMCM0:DRP6A[6]MMCM0:DRP6A[7]
    45--------------------------MMCM0:DRP6A[4]MMCM0:DRP6A[5]
    46--------------------------MMCM0:DRP6A[2]MMCM0:DRP6A[3]
    47--------------------------MMCM0:DRP6A[0]MMCM0:DRP6A[1]
    48--------------------------MMCM0:DRP69[14]MMCM0:DRP69[15]
    49--------------------------MMCM0:DRP69[12]MMCM0:DRP69[13]
    50--------------------------MMCM0:DRP69[10]MMCM0:DRP69[11]
    51--------------------------MMCM0:DRP69[8]MMCM0:DRP69[9]
    52--------------------------MMCM0:DRP69[6]MMCM0:DRP69[7]
    53--------------------------MMCM0:DRP69[4]MMCM0:DRP69[5]
    54--------------------------MMCM0:DRP69[2]MMCM0:DRP69[3]
    55--------------------------MMCM0:DRP69[0]MMCM0:DRP69[1]
    56--------------------------MMCM0:DRP68[14]MMCM0:DRP68[15]
    57--------------------------MMCM0:DRP68[12]MMCM0:DRP68[13]
    58--------------------------MMCM0:DRP68[10]MMCM0:DRP68[11]
    59--------------------------MMCM0:DRP68[8]MMCM0:DRP68[9]
    60--------------------------MMCM0:DRP68[6]MMCM0:DRP68[7]
    61--------------------------MMCM0:DRP68[4]MMCM0:DRP68[5]
    62--------------------------MMCM0:DRP68[2]MMCM0:DRP68[3]
    63--------------------------MMCM0:DRP68[0]MMCM0:DRP68[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 5
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP67[14]MMCM0:DRP67[15]
    1--------------------------MMCM0:DRP67[12]MMCM0:DRP67[13]
    2--------------------------MMCM0:DRP67[10]MMCM0:DRP67[11]
    3--------------------------MMCM0:DRP67[8]MMCM0:DRP67[9]
    4--------------------------MMCM0:DRP67[6]MMCM0:DRP67[7]
    5--------------------------MMCM0:DRP67[4]MMCM0:DRP67[5]
    6--------------------------MMCM0:DRP67[2]MMCM0:DRP67[3]
    7--------------------------MMCM0:DRP67[0]MMCM0:DRP67[1]
    8--------------------------MMCM0:DRP66[14]MMCM0:DRP66[15]
    9--------------------------MMCM0:DRP66[12]MMCM0:DRP66[13]
    10--------------------------MMCM0:DRP66[10]MMCM0:DRP66[11]
    11--------------------------MMCM0:DRP66[8]MMCM0:DRP66[9]
    12--------------------------MMCM0:DRP66[6]MMCM0:DRP66[7]
    13--------------------------MMCM0:DRP66[4]MMCM0:DRP66[5]
    14--------------------------MMCM0:DRP66[2]MMCM0:DRP66[3]
    15--------------------------MMCM0:DRP66[0]MMCM0:DRP66[1]
    16--------------------------MMCM0:DRP65[14]MMCM0:DRP65[15]
    17--------------------------MMCM0:DRP65[12]MMCM0:DRP65[13]
    18--------------------------MMCM0:DRP65[10]MMCM0:DRP65[11]
    19--------------------------MMCM0:DRP65[8]MMCM0:DRP65[9]
    20--------------------------MMCM0:DRP65[6]MMCM0:DRP65[7]
    21--------------------------MMCM0:DRP65[4]MMCM0:DRP65[5]
    22--------------------------MMCM0:DRP65[2]MMCM0:DRP65[3]
    23--------------------------MMCM0:DRP65[0]MMCM0:DRP65[1]
    24--------------------------MMCM0:DRP64[14]MMCM0:DRP64[15]
    25--------------------------MMCM0:DRP64[12]MMCM0:DRP64[13]
    26--------------------------MMCM0:DRP64[10]MMCM0:DRP64[11]
    27--------------------------MMCM0:DRP64[8]MMCM0:DRP64[9]
    28--------------------------MMCM0:DRP64[6]MMCM0:DRP64[7]
    29--------------------------MMCM0:DRP64[4]MMCM0:DRP64[5]
    30--------------------------MMCM0:DRP64[2]MMCM0:DRP64[3]
    31--------------------------MMCM0:DRP64[0]MMCM0:DRP64[1]
    32--------------------------MMCM0:DRP63[14]MMCM0:DRP63[15]
    33--------------------------MMCM0:DRP63[12]MMCM0:DRP63[13]
    34--------------------------MMCM0:DRP63[10]MMCM0:DRP63[11]
    35--------------------------MMCM0:DRP63[8]MMCM0:DRP63[9]
    36--------------------------MMCM0:DRP63[6]MMCM0:DRP63[7]
    37--------------------------MMCM0:DRP63[4]MMCM0:DRP63[5]
    38--------------------------MMCM0:DRP63[2]MMCM0:DRP63[3]
    39--------------------------MMCM0:DRP63[0]MMCM0:DRP63[1]
    40--------------------------MMCM0:DRP62[14]MMCM0:DRP62[15]
    41--------------------------MMCM0:DRP62[12]MMCM0:DRP62[13]
    42--------------------------MMCM0:DRP62[10]MMCM0:DRP62[11]
    43--------------------------MMCM0:DRP62[8]MMCM0:DRP62[9]
    44--------------------------MMCM0:DRP62[6]MMCM0:DRP62[7]
    45--------------------------MMCM0:DRP62[4]MMCM0:DRP62[5]
    46--------------------------MMCM0:DRP62[2]MMCM0:DRP62[3]
    47--------------------------MMCM0:DRP62[0]MMCM0:DRP62[1]
    48--------------------------MMCM0:DRP61[14]MMCM0:DRP61[15]
    49--------------------------MMCM0:DRP61[12]MMCM0:DRP61[13]
    50--------------------------MMCM0:DRP61[10]MMCM0:DRP61[11]
    51--------------------------MMCM0:DRP61[8]MMCM0:DRP61[9]
    52--------------------------MMCM0:DRP61[6]MMCM0:DRP61[7]
    53--------------------------MMCM0:DRP61[4]MMCM0:DRP61[5]
    54--------------------------MMCM0:DRP61[2]MMCM0:DRP61[3]
    55--------------------------MMCM0:DRP61[0]MMCM0:DRP61[1]
    56--------------------------MMCM0:DRP60[14]MMCM0:DRP60[15]
    57--------------------------MMCM0:DRP60[12]MMCM0:DRP60[13]
    58--------------------------MMCM0:DRP60[10]MMCM0:DRP60[11]
    59--------------------------MMCM0:DRP60[8]MMCM0:DRP60[9]
    60--------------------------MMCM0:DRP60[6]MMCM0:DRP60[7]
    61--------------------------MMCM0:DRP60[4]MMCM0:DRP60[5]
    62--------------------------MMCM0:DRP60[2]MMCM0:DRP60[3]
    63--------------------------MMCM0:DRP60[0]MMCM0:DRP60[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 6
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP5F[14]MMCM0:DRP5F[15]
    1--------------------------MMCM0:DRP5F[12]MMCM0:DRP5F[13]
    2--------------------------MMCM0:DRP5F[10]MMCM0:DRP5F[11]
    3--------------------------MMCM0:DRP5F[8]MMCM0:DRP5F[9]
    4--------------------------MMCM0:DRP5F[6]MMCM0:DRP5F[7]
    5--------------------------MMCM0:DRP5F[4]MMCM0:DRP5F[5]
    6--------------------------MMCM0:DRP5F[2]MMCM0:DRP5F[3]
    7--------------------------MMCM0:DRP5F[0]MMCM0:DRP5F[1]
    8--------------------------MMCM0:DRP5E[14]MMCM0:DRP5E[15]
    9--------------------------MMCM0:DRP5E[12]MMCM0:DRP5E[13]
    10--------------------------MMCM0:DRP5E[10]MMCM0:DRP5E[11]
    11--------------------------MMCM0:DRP5E[8]MMCM0:DRP5E[9]
    12--------------------------MMCM0:DRP5E[6]MMCM0:DRP5E[7]
    13--------------------------MMCM0:DRP5E[4]MMCM0:DRP5E[5]
    14--------------------------MMCM0:DRP5E[2]MMCM0:DRP5E[3]
    15--------------------------MMCM0:DRP5E[0]MMCM0:DRP5E[1]
    16--------------------------MMCM0:DRP5D[14]MMCM0:DRP5D[15]
    17--------------------------MMCM0:DRP5D[12]MMCM0:DRP5D[13]
    18--------------------------MMCM0:DRP5D[10]MMCM0:DRP5D[11]
    19--------------------------MMCM0:DRP5D[8]MMCM0:DRP5D[9]
    20--------------------------MMCM0:DRP5D[6]MMCM0:DRP5D[7]
    21--------------------------MMCM0:DRP5D[4]MMCM0:DRP5D[5]
    22--------------------------MMCM0:DRP5D[2]MMCM0:DRP5D[3]
    23--------------------------MMCM0:DRP5D[0]MMCM0:DRP5D[1]
    24--------------------------MMCM0:DRP5C[14]MMCM0:DRP5C[15]
    25--------------------------MMCM0:DRP5C[12]MMCM0:DRP5C[13]
    26--------------------------MMCM0:DRP5C[10]MMCM0:DRP5C[11]
    27--------------------------MMCM0:DRP5C[8]MMCM0:DRP5C[9]
    28--------------------------MMCM0:DRP5C[6]MMCM0:DRP5C[7]
    29--------------------------MMCM0:DRP5C[4]MMCM0:DRP5C[5]
    30--------------------------MMCM0:DRP5C[2]MMCM0:DRP5C[3]
    31--------------------------MMCM0:DRP5C[0]MMCM0:DRP5C[1]
    32--------------------------MMCM0:DRP5B[14]MMCM0:DRP5B[15]
    33--------------------------MMCM0:DRP5B[12]MMCM0:DRP5B[13]
    34--------------------------MMCM0:DRP5B[10]MMCM0:DRP5B[11]
    35--------------------------MMCM0:DRP5B[8]MMCM0:DRP5B[9]
    36--------------------------MMCM0:DRP5B[6]MMCM0:DRP5B[7]
    37--------------------------MMCM0:DRP5B[4]MMCM0:DRP5B[5]
    38--------------------------MMCM0:DRP5B[2]MMCM0:DRP5B[3]
    39--------------------------MMCM0:DRP5B[0]MMCM0:DRP5B[1]
    40--------------------------MMCM0:DRP5A[14]MMCM0:DRP5A[15]
    41--------------------------MMCM0:DRP5A[12]MMCM0:DRP5A[13]
    42--------------------------MMCM0:DRP5A[10]MMCM0:DRP5A[11]
    43--------------------------MMCM0:DRP5A[8]MMCM0:DRP5A[9]
    44--------------------------MMCM0:DRP5A[6]MMCM0:DRP5A[7]
    45--------------------------MMCM0:DRP5A[4]MMCM0:DRP5A[5]
    46--------------------------MMCM0:DRP5A[2]MMCM0:DRP5A[3]
    47--------------------------MMCM0:DRP5A[0]MMCM0:DRP5A[1]
    48--------------------------MMCM0:DRP59[14]MMCM0:DRP59[15]
    49--------------------------MMCM0:DRP59[12]MMCM0:DRP59[13]
    50--------------------------MMCM0:DRP59[10]MMCM0:DRP59[11]
    51--------------------------MMCM0:DRP59[8]MMCM0:DRP59[9]
    52--------------------------MMCM0:DRP59[6]MMCM0:DRP59[7]
    53--------------------------MMCM0:DRP59[4]MMCM0:DRP59[5]
    54--------------------------MMCM0:DRP59[2]MMCM0:DRP59[3]
    55--------------------------MMCM0:DRP59[0]MMCM0:DRP59[1]
    56--------------------------MMCM0:DRP58[14]MMCM0:DRP58[15]
    57--------------------------MMCM0:DRP58[12]MMCM0:DRP58[13]
    58--------------------------MMCM0:DRP58[10]MMCM0:DRP58[11]
    59--------------------------MMCM0:DRP58[8]MMCM0:DRP58[9]
    60--------------------------MMCM0:DRP58[6]MMCM0:DRP58[7]
    61--------------------------MMCM0:DRP58[4]MMCM0:DRP58[5]
    62--------------------------MMCM0:DRP58[2]MMCM0:DRP58[3]
    63--------------------------MMCM0:DRP58[0]MMCM0:DRP58[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 7
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP57[14]MMCM0:DRP57[15]
    1--------------------------MMCM0:DRP57[12]MMCM0:DRP57[13]
    2--------------------------MMCM0:DRP57[10]MMCM0:DRP57[11]
    3--------------------------MMCM0:DRP57[8]MMCM0:DRP57[9]
    4--------------------------MMCM0:DRP57[6]MMCM0:DRP57[7]
    5--------------------------MMCM0:DRP57[4]MMCM0:DRP57[5]
    6--------------------------MMCM0:DRP57[2]MMCM0:DRP57[3]
    7--------------------------MMCM0:DRP57[0]MMCM0:DRP57[1]
    8--------------------------MMCM0:DRP56[14]MMCM0:DRP56[15]
    9--------------------------MMCM0:DRP56[12]MMCM0:DRP56[13]
    10--------------------------MMCM0:DRP56[10]MMCM0:DRP56[11]
    11--------------------------MMCM0:DRP56[8]MMCM0:DRP56[9]
    12--------------------------MMCM0:DRP56[6]MMCM0:DRP56[7]
    13--------------------------MMCM0:DRP56[4]MMCM0:DRP56[5]
    14--------------------------MMCM0:DRP56[2]MMCM0:DRP56[3]
    15--------------------------MMCM0:DRP56[0]MMCM0:DRP56[1]
    16--------------------------MMCM0:DRP55[14]MMCM0:DRP55[15]
    17--------------------------MMCM0:DRP55[12]MMCM0:DRP55[13]
    18--------------------------MMCM0:DRP55[10]MMCM0:DRP55[11]
    19--------------------------MMCM0:DRP55[8]MMCM0:DRP55[9]
    20--------------------------MMCM0:DRP55[6]MMCM0:DRP55[7]
    21--------------------------MMCM0:DRP55[4]MMCM0:DRP55[5]
    22--------------------------MMCM0:DRP55[2]MMCM0:DRP55[3]
    23--------------------------MMCM0:DRP55[0]MMCM0:DRP55[1]
    24--------------------------MMCM0:DRP54[14]MMCM0:DRP54[15]
    25--------------------------MMCM0:DRP54[12]MMCM0:DRP54[13]
    26--------------------------MMCM0:DRP54[10]MMCM0:DRP54[11]
    27--------------------------MMCM0:DRP54[8]MMCM0:DRP54[9]
    28--------------------------MMCM0:DRP54[6]MMCM0:DRP54[7]
    29--------------------------MMCM0:DRP54[4]MMCM0:DRP54[5]
    30--------------------------MMCM0:DRP54[2]MMCM0:DRP54[3]
    31--------------------------MMCM0:DRP54[0]MMCM0:DRP54[1]
    32--------------------------MMCM0:DRP53[14]MMCM0:DRP53[15]
    33--------------------------MMCM0:DRP53[12]MMCM0:DRP53[13]
    34--------------------------MMCM0:DRP53[10]MMCM0:DRP53[11]
    35--------------------------MMCM0:DRP53[8]MMCM0:DRP53[9]
    36--------------------------MMCM0:DRP53[6]MMCM0:DRP53[7]
    37--------------------------MMCM0:DRP53[4]MMCM0:DRP53[5]
    38--------------------------MMCM0:DRP53[2]MMCM0:DRP53[3]
    39--------------------------MMCM0:DRP53[0]MMCM0:DRP53[1]
    40--------------------------MMCM0:DRP52[14]MMCM0:DRP52[15]
    41--------------------------MMCM0:DRP52[12]MMCM0:DRP52[13]
    42--------------------------MMCM0:DRP52[10]MMCM0:DRP52[11]
    43--------------------------MMCM0:DRP52[8]MMCM0:DRP52[9]
    44--------------------------MMCM0:DRP52[6]MMCM0:DRP52[7]
    45--------------------------MMCM0:DRP52[4]MMCM0:DRP52[5]
    46--------------------------MMCM0:DRP52[2]MMCM0:DRP52[3]
    47--------------------------MMCM0:DRP52[0]MMCM0:DRP52[1]
    48--------------------------MMCM0:DRP51[14]MMCM0:DRP51[15]
    49--------------------------MMCM0:DRP51[12]MMCM0:DRP51[13]
    50--------------------------MMCM0:DRP51[10]MMCM0:DRP51[11]
    51--------------------------MMCM0:DRP51[8]MMCM0:DRP51[9]
    52--------------------------MMCM0:DRP51[6]MMCM0:DRP51[7]
    53--------------------------MMCM0:DRP51[4]MMCM0:DRP51[5]
    54--------------------------MMCM0:DRP51[2]MMCM0:DRP51[3]
    55--------------------------MMCM0:DRP51[0]MMCM0:DRP51[1]
    56--------------------------MMCM0:DRP50[14]MMCM0:DRP50[15]
    57--------------------------MMCM0:DRP50[12]MMCM0:DRP50[13]
    58--------------------------MMCM0:DRP50[10]MMCM0:DRP50[11]
    59--------------------------MMCM0:DRP50[8]MMCM0:DRP50[9]
    60--------------------------MMCM0:DRP50[6]MMCM0:DRP50[7]
    61--------------------------MMCM0:DRP50[4]MMCM0:DRP50[5]
    62--------------------------MMCM0:DRP50[2]MMCM0:DRP50[3]
    63--------------------------MMCM0:DRP50[0]MMCM0:DRP50[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 8
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP4F[14]MMCM0:DRP4F[15]
    MMCM0:RES[3]
    1--------------------------MMCM0:DRP4F[12]
    MMCM0:RES[2]    		MMCM0:DRP4F[13]
    2--------------------------MMCM0:DRP4F[10]MMCM0:DRP4F[11]
    MMCM0:RES[1]
    3--------------------------MMCM0:DRP4F[8]
    MMCM0:RES[0]    		MMCM0:DRP4F[9]
    4--------------------------MMCM0:DRP4F[6]MMCM0:DRP4F[7]
    MMCM0:LFHF[1]
    5--------------------------MMCM0:DRP4F[4]
    MMCM0:LFHF[0]    		MMCM0:DRP4F[5]
    6--------------------------MMCM0:DRP4F[2]MMCM0:DRP4F[3]
    7--------------------------MMCM0:DRP4F[0]MMCM0:DRP4F[1]
    8--------------------------MMCM0:DRP4E[14]MMCM0:CP[3]
    MMCM0:DRP4E[15]
    9--------------------------MMCM0:CP[2]
    MMCM0:DRP4E[12]    		MMCM0:DRP4E[13]
    10--------------------------MMCM0:DRP4E[10]MMCM0:CP[1]
    MMCM0:DRP4E[11]
    11--------------------------MMCM0:CP[0]
    MMCM0:DRP4E[8]    		MMCM0:DRP4E[9]
    12--------------------------MMCM0:DRP4E[6]MMCM0:CP_BIAS_TRIP_SET
    MMCM0:DRP4E[7]
    13--------------------------MMCM0:CP_RES[1]
    MMCM0:DRP4E[4]    		MMCM0:DRP4E[5]
    14--------------------------MMCM0:DRP4E[2]MMCM0:CP_RES[0]
    MMCM0:DRP4E[3]
    15--------------------------MMCM0:DRP4E[0]MMCM0:DRP4E[1]
    16--------------------------MMCM0:DRP4D[14]MMCM0:DRP4D[15]
    17--------------------------MMCM0:DRP4D[12]MMCM0:DRP4D[13]
    18--------------------------MMCM0:DRP4D[10]MMCM0:DRP4D[11]
    19--------------------------MMCM0:DRP4D[8]MMCM0:DRP4D[9]
    20--------------------------MMCM0:DRP4D[6]MMCM0:DRP4D[7]
    21--------------------------MMCM0:DRP4D[4]MMCM0:DRP4D[5]
    22--------------------------MMCM0:DRP4D[2]MMCM0:DRP4D[3]
    23--------------------------MMCM0:DRP4D[0]MMCM0:DRP4D[1]
    24--------------------------MMCM0:DRP4C[14]MMCM0:DRP4C[15]
    25--------------------------MMCM0:DRP4C[12]MMCM0:DRP4C[13]
    26--------------------------MMCM0:DRP4C[10]MMCM0:DRP4C[11]
    27--------------------------MMCM0:DRP4C[8]MMCM0:DRP4C[9]
    28--------------------------MMCM0:DRP4C[6]MMCM0:DRP4C[7]
    29--------------------------MMCM0:DRP4C[4]MMCM0:DRP4C[5]
    30--------------------------MMCM0:DRP4C[2]MMCM0:DRP4C[3]
    31--------------------------MMCM0:DRP4C[0]MMCM0:DRP4C[1]
    32--------------------------MMCM0:DRP4B[14]MMCM0:DRP4B[15]
    33--------------------------MMCM0:DRP4B[12]MMCM0:DRP4B[13]
    34--------------------------MMCM0:DRP4B[10]MMCM0:DRP4B[11]
    35--------------------------MMCM0:DRP4B[8]MMCM0:DRP4B[9]
    36--------------------------MMCM0:DRP4B[6]MMCM0:DRP4B[7]
    37--------------------------MMCM0:DRP4B[4]MMCM0:DRP4B[5]
    38--------------------------MMCM0:DRP4B[2]MMCM0:DRP4B[3]
    39--------------------------MMCM0:DRP4B[0]MMCM0:DRP4B[1]
    40--------------------------MMCM0:DRP4A[14]MMCM0:DRP4A[15]
    41--------------------------MMCM0:DRP4A[12]MMCM0:DRP4A[13]
    42--------------------------MMCM0:DRP4A[10]MMCM0:DRP4A[11]
    43--------------------------MMCM0:AVDD_COMP_SET[1]
    MMCM0:DRP4A[8]    		MMCM0:DRP4A[9]
    44--------------------------MMCM0:AVDD_VBG_PD[2]
    MMCM0:DRP4A[6]    		MMCM0:AVDD_COMP_SET[0]
    MMCM0:DRP4A[7]
    45--------------------------MMCM0:AVDD_VBG_PD[0]
    MMCM0:DRP4A[4]    		MMCM0:AVDD_VBG_PD[1]
    MMCM0:DRP4A[5]
    46--------------------------MMCM0:AVDD_VBG_SEL[2]
    MMCM0:DRP4A[2]    		MMCM0:AVDD_VBG_SEL[3]
    MMCM0:DRP4A[3]
    47--------------------------MMCM0:AVDD_VBG_SEL[0]
    MMCM0:DRP4A[0]    		MMCM0:AVDD_VBG_SEL[1]
    MMCM0:DRP4A[1]
    48--------------------------MMCM0:DRP49[14]MMCM0:DRP49[15]
    49--------------------------MMCM0:DRP49[12]MMCM0:DRP49[13]
    50--------------------------MMCM0:DRP49[10]MMCM0:DRP49[11]
    51--------------------------MMCM0:DRP49[8]MMCM0:DRP49[9]
    52--------------------------MMCM0:DRP49[6]MMCM0:DRP49[7]
    53--------------------------MMCM0:DRP49[4]MMCM0:DRP49[5]
    54--------------------------MMCM0:DRP49[2]MMCM0:DRP49[3]
    55--------------------------MMCM0:DRP49[0]MMCM0:DRP49[1]
    56--------------------------MMCM0:DRP48[14]MMCM0:DRP48[15]
    57--------------------------MMCM0:DRP48[12]MMCM0:DRP48[13]
    58--------------------------MMCM0:DRP48[10]MMCM0:DRP48[11]
    59--------------------------MMCM0:DRP48[8]MMCM0:DRP48[9]
    60--------------------------MMCM0:DRP48[6]MMCM0:DRP48[7]
    61--------------------------MMCM0:DRP48[4]MMCM0:DRP48[5]
    62--------------------------MMCM0:DRP48[2]MMCM0:DRP48[3]
    63--------------------------MMCM0:DRP48[0]MMCM0:DRP48[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 9
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP47[14]MMCM0:DRP47[15]
    1--------------------------MMCM0:DRP47[12]MMCM0:DRP47[13]
    2--------------------------MMCM0:DRP47[10]MMCM0:DRP47[11]
    3--------------------------MMCM0:DRP47[8]MMCM0:DRP47[9]
    4--------------------------MMCM0:DRP47[6]MMCM0:DRP47[7]
    5--------------------------MMCM0:DRP47[4]MMCM0:DRP47[5]
    6--------------------------MMCM0:DRP47[2]MMCM0:DRP47[3]
    7--------------------------MMCM0:DRP47[0]MMCM0:DRP47[1]
    8--------------------------MMCM0:DRP46[14]MMCM0:DRP46[15]
    9--------------------------MMCM0:DRP46[12]MMCM0:DRP46[13]
    10--------------------------MMCM0:DRP46[10]MMCM0:DRP46[11]
    11--------------------------MMCM0:DRP46[8]MMCM0:DRP46[9]
    12--------------------------MMCM0:DRP46[6]MMCM0:DRP46[7]
    13--------------------------MMCM0:DRP46[4]MMCM0:DRP46[5]
    14--------------------------MMCM0:DRP46[2]MMCM0:DRP46[3]
    15--------------------------MMCM0:DRP46[0]
    MMCM0:VLF_HIGH_PWDN_B    		MMCM0:DRP46[1]
    16--------------------------MMCM0:DRP45[14]MMCM0:DRP45[15]
    17--------------------------MMCM0:DRP45[12]MMCM0:DRP45[13]
    18--------------------------MMCM0:DRP45[10]MMCM0:DRP45[11]
    19--------------------------MMCM0:DRP45[8]MMCM0:DRP45[9]
    20--------------------------MMCM0:DRP45[6]MMCM0:DRP45[7]
    21--------------------------MMCM0:DRP45[4]MMCM0:DRP45[5]
    22--------------------------MMCM0:DRP45[2]MMCM0:DRP45[3]
    23--------------------------MMCM0:DRP45[0]MMCM0:DRP45[1]
    24--------------------------MMCM0:DRP44[14]MMCM0:DRP44[15]
    25--------------------------MMCM0:DRP44[12]MMCM0:DRP44[13]
    26--------------------------MMCM0:DRP44[10]MMCM0:DRP44[11]
    27--------------------------MMCM0:DRP44[8]MMCM0:DRP44[9]
    28--------------------------MMCM0:DRP44[6]MMCM0:DRP44[7]
    29--------------------------MMCM0:DRP44[4]MMCM0:DRP44[5]
    30--------------------------MMCM0:DRP44[2]MMCM0:DRP44[3]
    31--------------------------MMCM0:DRP44[0]MMCM0:DRP44[1]
    32--------------------------MMCM0:DRP43[14]MMCM0:DRP43[15]
    33--------------------------MMCM0:DRP43[12]MMCM0:DRP43[13]
    34--------------------------MMCM0:DRP43[10]MMCM0:DRP43[11]
    35--------------------------MMCM0:DRP43[8]MMCM0:DRP43[9]
    36--------------------------MMCM0:DRP43[6]MMCM0:DRP43[7]
    37--------------------------MMCM0:DRP43[4]MMCM0:DRP43[5]
    38--------------------------MMCM0:DRP43[2]MMCM0:DRP43[3]
    39--------------------------MMCM0:DRP43[0]MMCM0:DRP43[1]
    40--------------------------MMCM0:DRP42[14]MMCM0:DRP42[15]
    MMCM0:LF_NEN[1]
    41--------------------------MMCM0:DRP42[12]
    MMCM0:LF_NEN[0]    		MMCM0:DRP42[13]
    42--------------------------MMCM0:DRP42[10]MMCM0:DRP42[11]
    MMCM0:LF_PEN[1]
    43--------------------------MMCM0:DRP42[8]
    MMCM0:LF_PEN[0]    		MMCM0:DRP42[9]
    44--------------------------MMCM0:DRP42[6]MMCM0:DRP42[7]
    MMCM0:VLF_HIGH_DIS_B
    45--------------------------MMCM0:DRP42[4]
    MMCM0:MAN_LF[2]    		MMCM0:DRP42[5]
    46--------------------------MMCM0:DRP42[2]MMCM0:DRP42[3]
    MMCM0:MAN_LF[1]
    47--------------------------MMCM0:DRP42[0]
    MMCM0:MAN_LF[0]    		MMCM0:DRP42[1]
    48--------------------------MMCM0:DRP41[14]MMCM0:DRP41[15]
    49--------------------------MMCM0:DRP41[12]MMCM0:DRP41[13]
    50--------------------------MMCM0:DRP41[10]MMCM0:DRP41[11]
    51--------------------------MMCM0:DRP41[8]MMCM0:DRP41[9]
    52--------------------------MMCM0:DRP41[6]MMCM0:DRP41[7]
    53--------------------------MMCM0:DRP41[4]MMCM0:DRP41[5]
    54--------------------------MMCM0:DRP41[2]MMCM0:DRP41[3]
    55--------------------------MMCM0:DRP41[0]MMCM0:DRP41[1]
    56--------------------------MMCM0:DRP40[14]MMCM0:DRP40[15]
    57--------------------------MMCM0:DRP40[12]MMCM0:DRP40[13]
    58--------------------------MMCM0:DRP40[10]MMCM0:DRP40[11]
    59--------------------------MMCM0:DRP40[8]MMCM0:DRP40[9]
    60--------------------------MMCM0:DRP40[6]MMCM0:DRP40[7]
    61--------------------------MMCM0:DRP40[4]MMCM0:DRP40[5]
    62--------------------------MMCM0:DRP40[2]MMCM0:DRP40[3]
    63--------------------------MMCM0:DRP40[0]MMCM0:DRP40[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 10
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP3F[14]MMCM0:DRP3F[15]
    1--------------------------MMCM0:DRP3F[12]MMCM0:DRP3F[13]
    2--------------------------MMCM0:DRP3F[10]MMCM0:DRP3F[11]
    3--------------------------MMCM0:DRP3F[8]MMCM0:DRP3F[9]
    4--------------------------MMCM0:DRP3F[6]MMCM0:DRP3F[7]
    5--------------------------MMCM0:DRP3F[4]MMCM0:DRP3F[5]
    6--------------------------MMCM0:DRP3F[2]MMCM0:DRP3F[3]
    7--------------------------MMCM0:DRP3F[0]MMCM0:DRP3F[1]
    8--------------------------MMCM0:DRP3E[14]MMCM0:DRP3E[15]
    9--------------------------MMCM0:DRP3E[12]MMCM0:DRP3E[13]
    10--------------------------MMCM0:DRP3E[10]MMCM0:DRP3E[11]
    11--------------------------MMCM0:DRP3E[8]MMCM0:DRP3E[9]
    12--------------------------MMCM0:DRP3E[6]MMCM0:DRP3E[7]
    13--------------------------MMCM0:DRP3E[4]MMCM0:DRP3E[5]
    14--------------------------MMCM0:DRP3E[2]MMCM0:DRP3E[3]
    15--------------------------MMCM0:DRP3E[0]MMCM0:DRP3E[1]
    16--------------------------MMCM0:DRP3D[14]MMCM0:DRP3D[15]
    17--------------------------MMCM0:DRP3D[12]MMCM0:DRP3D[13]
    18--------------------------MMCM0:DRP3D[10]MMCM0:DRP3D[11]
    19--------------------------MMCM0:DRP3D[8]MMCM0:DRP3D[9]
    20--------------------------MMCM0:DRP3D[6]MMCM0:DRP3D[7]
    21--------------------------MMCM0:DRP3D[4]MMCM0:DRP3D[5]
    22--------------------------MMCM0:DRP3D[2]MMCM0:DRP3D[3]
    23--------------------------MMCM0:DRP3D[0]MMCM0:DRP3D[1]
    24--------------------------MMCM0:DRP3C[14]MMCM0:DRP3C[15]
    25--------------------------MMCM0:DRP3C[12]MMCM0:DRP3C[13]
    26--------------------------MMCM0:DRP3C[10]MMCM0:DRP3C[11]
    27--------------------------MMCM0:DRP3C[8]MMCM0:DRP3C[9]
    28--------------------------MMCM0:DRP3C[6]MMCM0:DRP3C[7]
    29--------------------------MMCM0:DRP3C[4]MMCM0:DRP3C[5]
    30--------------------------MMCM0:DRP3C[2]MMCM0:DRP3C[3]
    31--------------------------MMCM0:DRP3C[0]MMCM0:DRP3C[1]
    32--------------------------MMCM0:DRP3B[14]MMCM0:DRP3B[15]
    33--------------------------MMCM0:DRP3B[12]MMCM0:DRP3B[13]
    34--------------------------MMCM0:DRP3B[10]MMCM0:DRP3B[11]
    35--------------------------MMCM0:DRP3B[8]MMCM0:DRP3B[9]
    36--------------------------MMCM0:DRP3B[6]MMCM0:DRP3B[7]
    37--------------------------MMCM0:DRP3B[4]MMCM0:DRP3B[5]
    38--------------------------MMCM0:DRP3B[2]MMCM0:DRP3B[3]
    39--------------------------MMCM0:DRP3B[0]MMCM0:DRP3B[1]
    40--------------------------MMCM0:DRP3A[14]MMCM0:DRP3A[15]
    41--------------------------MMCM0:DRP3A[12]MMCM0:DRP3A[13]
    42--------------------------MMCM0:DRP3A[10]MMCM0:DRP3A[11]
    43--------------------------MMCM0:DRP3A[8]MMCM0:DRP3A[9]
    44--------------------------MMCM0:DRP3A[6]MMCM0:DRP3A[7]
    45--------------------------MMCM0:DRP3A[4]MMCM0:DRP3A[5]
    46--------------------------MMCM0:DRP3A[2]MMCM0:DRP3A[3]
    47--------------------------MMCM0:DRP3A[0]MMCM0:DRP3A[1]
    48--------------------------MMCM0:DRP39[14]MMCM0:DRP39[15]
    49--------------------------MMCM0:DRP39[12]MMCM0:DRP39[13]
    50--------------------------MMCM0:DRP39[10]MMCM0:DRP39[11]
    51--------------------------MMCM0:DRP39[8]MMCM0:DRP39[9]
    52--------------------------MMCM0:DRP39[6]MMCM0:DRP39[7]
    53--------------------------MMCM0:DRP39[4]MMCM0:DRP39[5]
    54--------------------------MMCM0:DRP39[2]MMCM0:DRP39[3]
    55--------------------------MMCM0:DRP39[0]MMCM0:DRP39[1]
    56--------------------------MMCM0:DRP38[14]MMCM0:DRP38[15]
    57--------------------------MMCM0:DRP38[12]MMCM0:DRP38[13]
    58--------------------------MMCM0:DRP38[10]MMCM0:DRP38[11]
    59--------------------------MMCM0:DRP38[8]MMCM0:DRP38[9]
    60--------------------------MMCM0:DRP38[6]MMCM0:DRP38[7]
    61--------------------------MMCM0:DRP38[4]MMCM0:DRP38[5]
    62--------------------------MMCM0:DRP38[2]MMCM0:DRP38[3]
    63--------------------------MMCM0:DRP38[0]MMCM0:DRP38[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 11
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP37[14]MMCM0:DRP37[15]
    1--------------------------MMCM0:DRP37[12]MMCM0:DRP37[13]
    2--------------------------MMCM0:DRP37[10]MMCM0:DRP37[11]
    3--------------------------MMCM0:DRP37[8]MMCM0:DRP37[9]
    4--------------------------MMCM0:DRP37[6]MMCM0:DRP37[7]
    5--------------------------MMCM0:DRP37[4]MMCM0:DRP37[5]
    6--------------------------MMCM0:DRP37[2]MMCM0:DRP37[3]
    7--------------------------MMCM0:DRP37[0]MMCM0:DRP37[1]
    8--------------------------MMCM0:DRP36[14]MMCM0:DRP36[15]
    9--------------------------MMCM0:DRP36[12]MMCM0:DRP36[13]
    10--------------------------MMCM0:DRP36[10]MMCM0:DRP36[11]
    11--------------------------MMCM0:DRP36[8]MMCM0:DRP36[9]
    12--------------------------MMCM0:DRP36[6]MMCM0:DRP36[7]
    13--------------------------MMCM0:DRP36[4]MMCM0:DRP36[5]
    14--------------------------MMCM0:DRP36[2]MMCM0:DRP36[3]
    15--------------------------MMCM0:DRP36[0]MMCM0:DRP36[1]
    16--------------------------MMCM0:DRP35[14]MMCM0:DRP35[15]
    17--------------------------MMCM0:DRP35[12]MMCM0:DRP35[13]
    18--------------------------MMCM0:DRP35[10]MMCM0:DRP35[11]
    19--------------------------MMCM0:DRP35[8]MMCM0:DRP35[9]
    20--------------------------MMCM0:DRP35[6]MMCM0:DRP35[7]
    21--------------------------MMCM0:DRP35[4]MMCM0:DRP35[5]
    22--------------------------MMCM0:DRP35[2]MMCM0:DRP35[3]
    23--------------------------MMCM0:DRP35[0]MMCM0:DRP35[1]
    24--------------------------MMCM0:DRP34[14]MMCM0:DRP34[15]
    25--------------------------MMCM0:DRP34[12]MMCM0:DRP34[13]
    26--------------------------MMCM0:DRP34[10]MMCM0:DRP34[11]
    27--------------------------MMCM0:DRP34[8]MMCM0:DRP34[9]
    28--------------------------MMCM0:DRP34[6]MMCM0:DRP34[7]
    29--------------------------MMCM0:DRP34[4]MMCM0:DRP34[5]
    30--------------------------MMCM0:DRP34[2]MMCM0:DRP34[3]
    31--------------------------MMCM0:DRP34[0]MMCM0:DRP34[1]
    32--------------------------MMCM0:DRP33[14]MMCM0:DRP33[15]
    33--------------------------MMCM0:DRP33[12]MMCM0:DRP33[13]
    34--------------------------MMCM0:DRP33[10]MMCM0:DRP33[11]
    35--------------------------MMCM0:DRP33[8]MMCM0:DRP33[9]
    36--------------------------MMCM0:DRP33[6]MMCM0:DRP33[7]
    37--------------------------MMCM0:DRP33[4]MMCM0:DRP33[5]
    38--------------------------MMCM0:DRP33[2]MMCM0:DRP33[3]
    39--------------------------MMCM0:DRP33[0]MMCM0:DRP33[1]
    40--------------------------MMCM0:DRP32[14]MMCM0:DRP32[15]
    41--------------------------MMCM0:DRP32[12]MMCM0:DRP32[13]
    42--------------------------MMCM0:DRP32[10]MMCM0:DRP32[11]
    43--------------------------MMCM0:DRP32[8]MMCM0:DRP32[9]
    44--------------------------MMCM0:DRP32[6]MMCM0:DRP32[7]
    45--------------------------MMCM0:DRP32[4]MMCM0:DRP32[5]
    46--------------------------MMCM0:DRP32[2]MMCM0:DRP32[3]
    47--------------------------MMCM0:DRP32[0]MMCM0:DRP32[1]
    48--------------------------MMCM0:DRP31[14]MMCM0:DRP31[15]
    49--------------------------MMCM0:DRP31[12]MMCM0:DRP31[13]
    50--------------------------MMCM0:DRP31[10]MMCM0:DRP31[11]
    51--------------------------MMCM0:DRP31[8]MMCM0:DRP31[9]
    52--------------------------MMCM0:DRP31[6]MMCM0:DRP31[7]
    53--------------------------MMCM0:DRP31[4]MMCM0:DRP31[5]
    54--------------------------MMCM0:DRP31[2]MMCM0:DRP31[3]
    55--------------------------MMCM0:DRP31[0]MMCM0:DRP31[1]
    56--------------------------MMCM0:DRP30[14]MMCM0:DRP30[15]
    57--------------------------MMCM0:DRP30[12]MMCM0:DRP30[13]
    58--------------------------MMCM0:DRP30[10]MMCM0:DRP30[11]
    59--------------------------MMCM0:DRP30[8]MMCM0:DRP30[9]
    60--------------------------MMCM0:DRP30[6]MMCM0:DRP30[7]
    61--------------------------MMCM0:DRP30[4]MMCM0:DRP30[5]
    62--------------------------MMCM0:DRP30[2]MMCM0:DRP30[3]
    63--------------------------MMCM0:DRP30[0]MMCM0:DRP30[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 12
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP2F[14]MMCM0:DRP2F[15]
    1--------------------------MMCM0:DRP2F[12]MMCM0:DRP2F[13]
    2--------------------------MMCM0:DRP2F[10]MMCM0:DRP2F[11]
    3--------------------------MMCM0:DRP2F[8]MMCM0:DRP2F[9]
    4--------------------------MMCM0:DRP2F[6]MMCM0:DRP2F[7]
    5--------------------------MMCM0:DRP2F[4]MMCM0:DRP2F[5]
    6--------------------------MMCM0:DRP2F[2]MMCM0:DRP2F[3]
    7--------------------------MMCM0:DRP2F[0]MMCM0:DRP2F[1]
    8--------------------------MMCM0:DRP2E[14]MMCM0:DRP2E[15]
    9--------------------------MMCM0:DRP2E[12]MMCM0:DRP2E[13]
    10--------------------------MMCM0:DRP2E[10]MMCM0:DRP2E[11]
    11--------------------------MMCM0:DRP2E[8]MMCM0:DRP2E[9]
    12--------------------------MMCM0:DRP2E[6]MMCM0:DRP2E[7]
    13--------------------------MMCM0:DRP2E[4]MMCM0:DRP2E[5]
    14--------------------------MMCM0:DRP2E[2]MMCM0:DRP2E[3]
    15--------------------------MMCM0:DRP2E[0]MMCM0:DRP2E[1]
    16--------------------------MMCM0:DRP2D[14]MMCM0:DRP2D[15]
    17--------------------------MMCM0:DRP2D[12]MMCM0:DRP2D[13]
    18--------------------------MMCM0:DRP2D[10]MMCM0:DRP2D[11]
    19--------------------------MMCM0:DRP2D[8]MMCM0:DRP2D[9]
    20--------------------------MMCM0:DRP2D[6]MMCM0:DRP2D[7]
    21--------------------------MMCM0:DRP2D[4]MMCM0:DRP2D[5]
    22--------------------------MMCM0:DRP2D[2]MMCM0:DRP2D[3]
    23--------------------------MMCM0:DRP2D[0]MMCM0:DRP2D[1]
    24--------------------------MMCM0:DRP2C[14]MMCM0:DRP2C[15]
    25--------------------------MMCM0:DRP2C[12]MMCM0:DRP2C[13]
    26--------------------------MMCM0:DRP2C[10]MMCM0:DRP2C[11]
    27--------------------------MMCM0:DRP2C[8]MMCM0:DRP2C[9]
    28--------------------------MMCM0:DRP2C[6]MMCM0:DRP2C[7]
    29--------------------------MMCM0:DRP2C[4]MMCM0:DRP2C[5]
    30--------------------------MMCM0:DRP2C[2]MMCM0:DRP2C[3]
    31--------------------------MMCM0:DRP2C[0]MMCM0:DRP2C[1]
    32--------------------------MMCM0:DRP2B[14]MMCM0:DRP2B[15]
    33--------------------------MMCM0:DRP2B[12]MMCM0:DRP2B[13]
    34--------------------------MMCM0:DRP2B[10]MMCM0:DRP2B[11]
    35--------------------------MMCM0:DRP2B[8]MMCM0:DRP2B[9]
    36--------------------------MMCM0:DRP2B[6]MMCM0:DRP2B[7]
    37--------------------------MMCM0:DRP2B[4]MMCM0:DRP2B[5]
    38--------------------------MMCM0:DRP2B[2]MMCM0:DRP2B[3]
    39--------------------------MMCM0:DRP2B[0]MMCM0:DRP2B[1]
    40--------------------------MMCM0:DRP2A[14]MMCM0:DRP2A[15]
    41--------------------------MMCM0:DRP2A[12]MMCM0:DRP2A[13]
    42--------------------------MMCM0:DRP2A[10]MMCM0:DRP2A[11]
    43--------------------------MMCM0:DRP2A[8]MMCM0:DRP2A[9]
    44--------------------------MMCM0:DRP2A[6]MMCM0:DRP2A[7]
    45--------------------------MMCM0:DRP2A[4]MMCM0:DRP2A[5]
    46--------------------------MMCM0:DRP2A[2]MMCM0:DRP2A[3]
    47--------------------------MMCM0:DRP2A[0]MMCM0:DRP2A[1]
    48--------------------------MMCM0:DRP29[14]MMCM0:DRP29[15]
    49--------------------------MMCM0:DRP29[12]MMCM0:DRP29[13]
    50--------------------------MMCM0:DRP29[10]MMCM0:DRP29[11]
    51--------------------------MMCM0:DRP29[8]MMCM0:DRP29[9]
    52--------------------------MMCM0:DRP29[6]MMCM0:DRP29[7]
    53--------------------------MMCM0:DRP29[4]MMCM0:DRP29[5]
    54--------------------------MMCM0:DRP29[2]MMCM0:DRP29[3]
    55--------------------------MMCM0:DRP29[0]MMCM0:DRP29[1]
    56--------------------------MMCM0:DRP28[14]MMCM0:DRP28[15]
    MMCM0:INTERP_EN[7]
    57--------------------------MMCM0:DRP28[12]
    MMCM0:INTERP_EN[6]    		MMCM0:DRP28[13]
    58--------------------------MMCM0:DRP28[10]MMCM0:DRP28[11]
    MMCM0:INTERP_EN[5]
    59--------------------------MMCM0:DRP28[8]
    MMCM0:INTERP_EN[4]    		MMCM0:DRP28[9]
    60--------------------------MMCM0:DRP28[6]MMCM0:DRP28[7]
    MMCM0:INTERP_EN[3]
    61--------------------------MMCM0:DRP28[4]
    MMCM0:INTERP_EN[2]    		MMCM0:DRP28[5]
    62--------------------------MMCM0:DRP28[2]MMCM0:DRP28[3]
    MMCM0:INTERP_EN[1]
    63--------------------------MMCM0:DRP28[0]
    MMCM0:INTERP_EN[0]    		MMCM0:DRP28[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 13
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP27[14]MMCM0:DRP27[15]
    1--------------------------MMCM0:DRP27[12]MMCM0:DRP27[13]
    2--------------------------MMCM0:DRP27[10]MMCM0:DRP27[11]
    3--------------------------MMCM0:DRP27[8]MMCM0:DRP27[9]
    4--------------------------MMCM0:DRP27[6]MMCM0:DRP27[7]
    5--------------------------MMCM0:DRP27[4]MMCM0:DRP27[5]
    6--------------------------MMCM0:DRP27[2]MMCM0:DRP27[3]
    7--------------------------MMCM0:DRP27[0]MMCM0:DRP27[1]
    8--------------------------MMCM0:DRP26[14]MMCM0:DRP26[15]
    9--------------------------MMCM0:DRP26[12]MMCM0:DRP26[13]
    10--------------------------MMCM0:DRP26[10]MMCM0:DRP26[11]
    11--------------------------MMCM0:ANALOG_MISC[3]
    MMCM0:DRP26[8]    		MMCM0:DRP26[9]
    12--------------------------MMCM0:DRP26[6]MMCM0:ANALOG_MISC[2]
    MMCM0:DRP26[7]
    13--------------------------MMCM0:ANALOG_MISC[1]
    MMCM0:DRP26[4]    		MMCM0:DRP26[5]
    14--------------------------MMCM0:DRP26[2]MMCM0:ANALOG_MISC[0]
    MMCM0:DRP26[3]
    15--------------------------MMCM0:DRP26[0]MMCM0:DRP26[1]
    16--------------------------MMCM0:DRP25[14]MMCM0:DRP25[15]
    17--------------------------MMCM0:DRP25[12]MMCM0:DRP25[13]
    18--------------------------MMCM0:DRP25[10]MMCM0:DRP25[11]
    19--------------------------MMCM0:DRP25[8]MMCM0:DRP25[9]
    20--------------------------MMCM0:DRP25[6]MMCM0:DRP25[7]
    21--------------------------MMCM0:DRP25[4]MMCM0:DRP25[5]
    22--------------------------MMCM0:DRP25[2]MMCM0:DRP25[3]
    23--------------------------MMCM0:DRP25[0]MMCM0:DRP25[1]
    24--------------------------MMCM0:DRP24[14]MMCM0:DRP24[15]
    25--------------------------MMCM0:DRP24[12]MMCM0:DRP24[13]
    26--------------------------MMCM0:DRP24[10]MMCM0:DRP24[11]
    27--------------------------MMCM0:DRP24[8]MMCM0:DRP24[9]
    28--------------------------MMCM0:DRP24[6]MMCM0:DRP24[7]
    29--------------------------MMCM0:DRP24[4]MMCM0:DRP24[5]
    30--------------------------MMCM0:DRP24[2]MMCM0:DRP24[3]
    31--------------------------MMCM0:DRP24[0]MMCM0:DRP24[1]
    32--------------------------MMCM0:DRP23[14]MMCM0:DRP23[15]
    33--------------------------MMCM0:DRP23[12]MMCM0:DRP23[13]
    34--------------------------MMCM0:DRP23[10]MMCM0:DRP23[11]
    35--------------------------MMCM0:DRP23[8]MMCM0:DRP23[9]
    36--------------------------MMCM0:DRP23[6]MMCM0:DRP23[7]
    37--------------------------MMCM0:DRP23[4]MMCM0:DRP23[5]
    38--------------------------MMCM0:DRP23[2]MMCM0:DRP23[3]
    39--------------------------MMCM0:DRP23[0]MMCM0:DRP23[1]
    40--------------------------MMCM0:DRP22[14]MMCM0:DRP22[15]
    41--------------------------MMCM0:DRP22[12]MMCM0:DRP22[13]
    42--------------------------MMCM0:DRP22[10]MMCM0:DRP22[11]
    43--------------------------MMCM0:DRP22[8]MMCM0:DRP22[9]
    44--------------------------MMCM0:DRP22[6]MMCM0:DRP22[7]
    45--------------------------MMCM0:DRP22[4]MMCM0:DRP22[5]
    46--------------------------MMCM0:DRP22[2]MMCM0:DRP22[3]
    47--------------------------MMCM0:DRP22[0]
    MMCM0:EN_VCO_DIV6    		MMCM0:DRP22[1]
    MMCM0:EN_VCO_DIV1
    48--------------------------MMCM0:DRP21[14]MMCM0:DRP21[15]
    49--------------------------MMCM0:DRP21[12]MMCM0:DRP21[13]
    50--------------------------MMCM0:DRP21[10]MMCM0:DRP21[11]
    51--------------------------MMCM0:DRP21[8]MMCM0:DRP21[9]
    52--------------------------MMCM0:DRP21[6]MMCM0:DRP21[7]
    53--------------------------MMCM0:DRP21[4]MMCM0:DRP21[5]
    54--------------------------MMCM0:DRP21[2]MMCM0:DRP21[3]
    55--------------------------MMCM0:DRP21[0]MMCM0:DRP21[1]
    56--------------------------MMCM0:DRP20[14]MMCM0:DRP20[15]
    57--------------------------MMCM0:DRP20[12]MMCM0:DRP20[13]
    58--------------------------MMCM0:DRP20[10]MMCM0:DRP20[11]
    59--------------------------MMCM0:DRP20[8]MMCM0:DRP20[9]
    60--------------------------MMCM0:DRP20[6]MMCM0:DRP20[7]
    61--------------------------MMCM0:DRP20[4]MMCM0:DRP20[5]
    62--------------------------MMCM0:DRP20[2]MMCM0:DRP20[3]
    63--------------------------MMCM0:DRP20[0]MMCM0:DRP20[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 14
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP1F[14]MMCM0:DRP1F[15]
    1--------------------------MMCM0:DRP1F[12]MMCM0:DRP1F[13]
    2--------------------------MMCM0:DRP1F[10]MMCM0:DRP1F[11]
    3--------------------------MMCM0:DRP1F[8]
    MMCM0:DVDD_COMP_SET[1]    		MMCM0:DRP1F[9]
    4--------------------------MMCM0:DRP1F[6]
    MMCM0:DVDD_VBG_PD[2]    		MMCM0:DRP1F[7]
    MMCM0:DVDD_COMP_SET[0]
    5--------------------------MMCM0:DRP1F[4]
    MMCM0:DVDD_VBG_PD[0]    		MMCM0:DRP1F[5]
    MMCM0:DVDD_VBG_PD[1]
    6--------------------------MMCM0:DRP1F[2]
    MMCM0:DVDD_VBG_SEL[2]    		MMCM0:DRP1F[3]
    MMCM0:DVDD_VBG_SEL[3]
    7--------------------------MMCM0:DRP1F[0]
    MMCM0:DVDD_VBG_SEL[0]    		MMCM0:DRP1F[1]
    MMCM0:DVDD_VBG_SEL[1]
    8--------------------------MMCM0:DRP1E[14]MMCM0:DRP1E[15]
    9--------------------------MMCM0:DRP1E[12]MMCM0:DRP1E[13]
    10--------------------------MMCM0:DRP1E[10]MMCM0:DRP1E[11]
    11--------------------------MMCM0:DRP1E[8]MMCM0:DRP1E[9]
    12--------------------------MMCM0:DRP1E[6]MMCM0:DRP1E[7]
    13--------------------------MMCM0:DRP1E[4]MMCM0:DRP1E[5]
    14--------------------------MMCM0:DRP1E[2]MMCM0:DRP1E[3]
    15--------------------------MMCM0:DRP1E[0]MMCM0:DRP1E[1]
    16--------------------------MMCM0:DRP1D[14]MMCM0:DRP1D[15]
    17--------------------------MMCM0:DRP1D[12]MMCM0:DRP1D[13]
    18--------------------------MMCM0:DRP1D[10]
    MMCM0:PFD[6]    		MMCM0:DRP1D[11]
    19--------------------------MMCM0:DRP1D[8]
    MMCM0:PFD[4]    		MMCM0:DRP1D[9]
    MMCM0:PFD[5]
    20--------------------------MMCM0:DRP1D[6]
    MMCM0:PFD[2]    		MMCM0:DRP1D[7]
    MMCM0:PFD[3]
    21--------------------------MMCM0:DRP1D[4]
    MMCM0:PFD[0]    		MMCM0:DRP1D[5]
    MMCM0:PFD[1]
    22--------------------------MMCM0:DRP1D[2]MMCM0:DRP1D[3]
    23--------------------------MMCM0:DRP1D[0]MMCM0:DRP1D[1]
    24--------------------------MMCM0:DRP1C[14]MMCM0:DRP1C[15]
    25--------------------------MMCM0:DRP1C[12]MMCM0:DRP1C[13]
    26--------------------------MMCM0:DRP1C[10]MMCM0:DRP1C[11]
    27--------------------------MMCM0:DRP1C[8]MMCM0:DRP1C[9]
    28--------------------------MMCM0:DRP1C[6]MMCM0:DRP1C[7]
    29--------------------------MMCM0:DRP1C[4]MMCM0:DRP1C[5]
    30--------------------------MMCM0:DRP1C[2]MMCM0:DRP1C[3]
    31--------------------------MMCM0:DRP1C[0]MMCM0:DRP1C[1]
    32--------------------------MMCM0:DRP1B[14]MMCM0:DRP1B[15]
    33--------------------------MMCM0:DRP1B[12]MMCM0:DRP1B[13]
    34--------------------------MMCM0:DRP1B[10]MMCM0:DRP1B[11]
    35--------------------------MMCM0:DRP1B[8]MMCM0:DRP1B[9]
    36--------------------------MMCM0:DRP1B[6]
    MMCM0:HVLF_STEP    		MMCM0:DRP1B[7]
    MMCM0:HVLF_CNT_TEST_EN
    37--------------------------MMCM0:DRP1B[4]
    MMCM0:HVLF_CNT_TEST[4]    		MMCM0:DRP1B[5]
    MMCM0:HVLF_CNT_TEST[5]
    38--------------------------MMCM0:DRP1B[2]
    MMCM0:HVLF_CNT_TEST[2]    		MMCM0:DRP1B[3]
    MMCM0:HVLF_CNT_TEST[3]
    39--------------------------MMCM0:DRP1B[0]
    MMCM0:HVLF_CNT_TEST[0]    		MMCM0:DRP1B[1]
    MMCM0:HVLF_CNT_TEST[1]
    40--------------------------MMCM0:DRP1A[14]
    MMCM0:LOCK_REF_DLY[4]    		MMCM0:DRP1A[15]
    41--------------------------MMCM0:DRP1A[12]
    MMCM0:LOCK_REF_DLY[2]    		MMCM0:DRP1A[13]
    MMCM0:LOCK_REF_DLY[3]
    42--------------------------MMCM0:DRP1A[10]
    MMCM0:LOCK_REF_DLY[0]    		MMCM0:DRP1A[11]
    MMCM0:LOCK_REF_DLY[1]
    43--------------------------MMCM0:DRP1A[8]
    MMCM0:LOCK_SAT_HIGH[8]    		MMCM0:DRP1A[9]
    MMCM0:LOCK_SAT_HIGH[9]
    44--------------------------MMCM0:DRP1A[6]
    MMCM0:LOCK_SAT_HIGH[6]    		MMCM0:DRP1A[7]
    MMCM0:LOCK_SAT_HIGH[7]
    45--------------------------MMCM0:DRP1A[4]
    MMCM0:LOCK_SAT_HIGH[4]    		MMCM0:DRP1A[5]
    MMCM0:LOCK_SAT_HIGH[5]
    46--------------------------MMCM0:DRP1A[2]
    MMCM0:LOCK_SAT_HIGH[2]    		MMCM0:DRP1A[3]
    MMCM0:LOCK_SAT_HIGH[3]
    47--------------------------MMCM0:DRP1A[0]
    MMCM0:LOCK_SAT_HIGH[0]    		MMCM0:DRP1A[1]
    MMCM0:LOCK_SAT_HIGH[1]
    48--------------------------MMCM0:DRP19[14]
    MMCM0:LOCK_FB_DLY[4]    		MMCM0:DRP19[15]
    49--------------------------MMCM0:DRP19[12]
    MMCM0:LOCK_FB_DLY[2]    		MMCM0:DRP19[13]
    MMCM0:LOCK_FB_DLY[3]
    50--------------------------MMCM0:DRP19[10]
    MMCM0:LOCK_FB_DLY[0]    		MMCM0:DRP19[11]
    MMCM0:LOCK_FB_DLY[1]
    51--------------------------MMCM0:DRP19[8]
    MMCM0:UNLOCK_CNT[8]    		MMCM0:DRP19[9]
    MMCM0:UNLOCK_CNT[9]
    52--------------------------MMCM0:DRP19[6]
    MMCM0:UNLOCK_CNT[6]    		MMCM0:DRP19[7]
    MMCM0:UNLOCK_CNT[7]
    53--------------------------MMCM0:DRP19[4]
    MMCM0:UNLOCK_CNT[4]    		MMCM0:DRP19[5]
    MMCM0:UNLOCK_CNT[5]
    54--------------------------MMCM0:DRP19[2]
    MMCM0:UNLOCK_CNT[2]    		MMCM0:DRP19[3]
    MMCM0:UNLOCK_CNT[3]
    55--------------------------MMCM0:DRP19[0]
    MMCM0:UNLOCK_CNT[0]    		MMCM0:DRP19[1]
    MMCM0:UNLOCK_CNT[1]
    56--------------------------MMCM0:DRP18[14]MMCM0:DRP18[15]
    57--------------------------MMCM0:DRP18[12]MMCM0:DRP18[13]
    58--------------------------MMCM0:DRP18[10]MMCM0:DRP18[11]
    59--------------------------MMCM0:DRP18[8]
    MMCM0:LOCK_CNT[8]    		MMCM0:DRP18[9]
    MMCM0:LOCK_CNT[9]
    60--------------------------MMCM0:DRP18[6]
    MMCM0:LOCK_CNT[6]    		MMCM0:DRP18[7]
    MMCM0:LOCK_CNT[7]
    61--------------------------MMCM0:DRP18[4]
    MMCM0:LOCK_CNT[4]    		MMCM0:DRP18[5]
    MMCM0:LOCK_CNT[5]
    62--------------------------MMCM0:DRP18[2]
    MMCM0:LOCK_CNT[2]    		MMCM0:DRP18[3]
    MMCM0:LOCK_CNT[3]
    63--------------------------MMCM0:DRP18[0]
    MMCM0:LOCK_CNT[0]    		MMCM0:DRP18[1]
    MMCM0:LOCK_CNT[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 15
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP17[14]MMCM0:DRP17[15]
    1--------------------------MMCM0:CLKFBIN_NOCOUNT
    MMCM0:DRP17[12]    		MMCM0:CLKFBIN_EDGE
    MMCM0:DRP17[13]
    2--------------------------MMCM0:CLKFBIN_HT[4]
    MMCM0:DRP17[10]    		MMCM0:CLKFBIN_HT[5]
    MMCM0:DRP17[11]
    3--------------------------MMCM0:CLKFBIN_HT[2]
    MMCM0:DRP17[8]    		MMCM0:CLKFBIN_HT[3]
    MMCM0:DRP17[9]
    4--------------------------MMCM0:CLKFBIN_HT[0]
    MMCM0:DRP17[6]    		MMCM0:CLKFBIN_HT[1]
    MMCM0:DRP17[7]
    5--------------------------MMCM0:CLKFBIN_LT[4]
    MMCM0:DRP17[4]    		MMCM0:CLKFBIN_LT[5]
    MMCM0:DRP17[5]
    6--------------------------MMCM0:CLKFBIN_LT[2]
    MMCM0:DRP17[2]    		MMCM0:CLKFBIN_LT[3]
    MMCM0:DRP17[3]
    7--------------------------MMCM0:CLKFBIN_LT[0]
    MMCM0:DRP17[0]    		MMCM0:CLKFBIN_LT[1]
    MMCM0:DRP17[1]
    8--------------------------MMCM0:DRP16[14]MMCM0:DRP16[15]
    9--------------------------MMCM0:DIVCLK_NOCOUNT
    MMCM0:DRP16[12]    		MMCM0:DIVCLK_EDGE
    MMCM0:DRP16[13]
    10--------------------------MMCM0:DIVCLK_HT[4]
    MMCM0:DRP16[10]    		MMCM0:DIVCLK_HT[5]
    MMCM0:DRP16[11]
    11--------------------------MMCM0:DIVCLK_HT[2]
    MMCM0:DRP16[8]    		MMCM0:DIVCLK_HT[3]
    MMCM0:DRP16[9]
    12--------------------------MMCM0:DIVCLK_HT[0]
    MMCM0:DRP16[6]    		MMCM0:DIVCLK_HT[1]
    MMCM0:DRP16[7]
    13--------------------------MMCM0:DIVCLK_LT[4]
    MMCM0:DRP16[4]    		MMCM0:DIVCLK_LT[5]
    MMCM0:DRP16[5]
    14--------------------------MMCM0:DIVCLK_LT[2]
    MMCM0:DRP16[2]    		MMCM0:DIVCLK_LT[3]
    MMCM0:DRP16[3]
    15--------------------------MMCM0:DIVCLK_LT[0]
    MMCM0:DRP16[0]    		MMCM0:DIVCLK_LT[1]
    MMCM0:DRP16[1]
    16--------------------------MMCM0:CLKFBOUT_FRAC[2]
    MMCM0:DRP15[14]    		MMCM0:DRP15[15]
    17--------------------------MMCM0:CLKFBOUT_FRAC[0]
    MMCM0:DRP15[12]    		MMCM0:CLKFBOUT_FRAC[1]
    MMCM0:DRP15[13]
    18--------------------------MMCM0:CLKFBOUT_FRAC_WF
    MMCM0:DRP15[10]    		MMCM0:CLKFBOUT_FRAC_EN
    MMCM0:DRP15[11]
    19--------------------------MMCM0:CLKFBOUT_MX[0]
    MMCM0:CLKFBOUT_USE_FINE_PS
    MMCM0:DRP15[8]    		MMCM0:CLKFBOUT_MX[1]
    MMCM0:DRP15[9]
    20--------------------------MMCM0:CLKFBOUT_NOCOUNT
    MMCM0:DRP15[6]    		MMCM0:CLKFBOUT_EDGE
    MMCM0:DRP15[7]
    21--------------------------MMCM0:CLKFBOUT_DT[4]
    MMCM0:DRP15[4]    		MMCM0:CLKFBOUT_DT[5]
    MMCM0:DRP15[5]
    22--------------------------MMCM0:CLKFBOUT_DT[2]
    MMCM0:DRP15[2]    		MMCM0:CLKFBOUT_DT[3]
    MMCM0:DRP15[3]
    23--------------------------MMCM0:CLKFBOUT_DT[0]
    MMCM0:DRP15[0]    		MMCM0:CLKFBOUT_DT[1]
    MMCM0:DRP15[1]
    24--------------------------MMCM0:CLKFBOUT_PM[1]
    MMCM0:DRP14[14]    		MMCM0:CLKFBOUT_PM[2]
    MMCM0:DRP14[15]
    25--------------------------MMCM0:CLKFBOUT_EN
    MMCM0:DRP14[12]    		MMCM0:CLKFBOUT_PM[0]
    MMCM0:DRP14[13]
    26--------------------------MMCM0:CLKFBOUT_HT[4]
    MMCM0:DRP14[10]    		MMCM0:CLKFBOUT_HT[5]
    MMCM0:DRP14[11]
    27--------------------------MMCM0:CLKFBOUT_HT[2]
    MMCM0:DRP14[8]    		MMCM0:CLKFBOUT_HT[3]
    MMCM0:DRP14[9]
    28--------------------------MMCM0:CLKFBOUT_HT[0]
    MMCM0:DRP14[6]    		MMCM0:CLKFBOUT_HT[1]
    MMCM0:DRP14[7]
    29--------------------------MMCM0:CLKFBOUT_LT[4]
    MMCM0:DRP14[4]    		MMCM0:CLKFBOUT_LT[5]
    MMCM0:DRP14[5]
    30--------------------------MMCM0:CLKFBOUT_LT[2]
    MMCM0:DRP14[2]    		MMCM0:CLKFBOUT_LT[3]
    MMCM0:DRP14[3]
    31--------------------------MMCM0:CLKFBOUT_LT[0]
    MMCM0:DRP14[0]    		MMCM0:CLKFBOUT_LT[1]
    MMCM0:DRP14[1]
    32--------------------------MMCM0:DRP13[14]MMCM0:DRP13[15]
    33--------------------------MMCM0:DRP13[12]MMCM0:DRP13[13]
    34--------------------------MMCM0:CLKOUT6_FRAC_WF
    MMCM0:DRP13[10]    		MMCM0:DRP13[11]
    35--------------------------MMCM0:CLKOUT6_MX[0]
    MMCM0:CLKOUT6_USE_FINE_PS
    MMCM0:DRP13[8]    		MMCM0:CLKOUT6_MX[1]
    MMCM0:DRP13[9]
    36--------------------------MMCM0:CLKOUT6_NOCOUNT
    MMCM0:DRP13[6]    		MMCM0:CLKOUT6_EDGE
    MMCM0:DRP13[7]
    37--------------------------MMCM0:CLKOUT6_DT[4]
    MMCM0:DRP13[4]    		MMCM0:CLKOUT6_DT[5]
    MMCM0:DRP13[5]
    38--------------------------MMCM0:CLKOUT6_DT[2]
    MMCM0:DRP13[2]    		MMCM0:CLKOUT6_DT[3]
    MMCM0:DRP13[3]
    39--------------------------MMCM0:CLKOUT6_DT[0]
    MMCM0:DRP13[0]    		MMCM0:CLKOUT6_DT[1]
    MMCM0:DRP13[1]
    40--------------------------MMCM0:CLKOUT6_PM[1]
    MMCM0:DRP12[14]    		MMCM0:CLKOUT6_PM[2]
    MMCM0:DRP12[15]
    41--------------------------MMCM0:CLKOUT6_EN
    MMCM0:DRP12[12]    		MMCM0:CLKOUT6_PM[0]
    MMCM0:DRP12[13]
    42--------------------------MMCM0:CLKOUT6_HT[4]
    MMCM0:DRP12[10]    		MMCM0:CLKOUT6_HT[5]
    MMCM0:DRP12[11]
    43--------------------------MMCM0:CLKOUT6_HT[2]
    MMCM0:DRP12[8]    		MMCM0:CLKOUT6_HT[3]
    MMCM0:DRP12[9]
    44--------------------------MMCM0:CLKOUT6_HT[0]
    MMCM0:DRP12[6]    		MMCM0:CLKOUT6_HT[1]
    MMCM0:DRP12[7]
    45--------------------------MMCM0:CLKOUT6_LT[4]
    MMCM0:DRP12[4]    		MMCM0:CLKOUT6_LT[5]
    MMCM0:DRP12[5]
    46--------------------------MMCM0:CLKOUT6_LT[2]
    MMCM0:DRP12[2]    		MMCM0:CLKOUT6_LT[3]
    MMCM0:DRP12[3]
    47--------------------------MMCM0:CLKOUT6_LT[0]
    MMCM0:DRP12[0]    		MMCM0:CLKOUT6_LT[1]
    MMCM0:DRP12[1]
    48--------------------------MMCM0:DRP11[14]MMCM0:DRP11[15]
    49--------------------------MMCM0:DRP11[12]MMCM0:DRP11[13]
    50--------------------------MMCM0:DRP11[10]MMCM0:DRP11[11]
    51--------------------------MMCM0:CLKOUT4_MX[0]
    MMCM0:CLKOUT4_USE_FINE_PS
    MMCM0:DRP11[8]    		MMCM0:CLKOUT4_CASCADE
    MMCM0:CLKOUT4_MX[1]
    MMCM0:DRP11[9]
    52--------------------------MMCM0:CLKOUT4_NOCOUNT
    MMCM0:DRP11[6]    		MMCM0:CLKOUT4_EDGE
    MMCM0:DRP11[7]
    53--------------------------MMCM0:CLKOUT4_DT[4]
    MMCM0:DRP11[4]    		MMCM0:CLKOUT4_DT[5]
    MMCM0:DRP11[5]
    54--------------------------MMCM0:CLKOUT4_DT[2]
    MMCM0:DRP11[2]    		MMCM0:CLKOUT4_DT[3]
    MMCM0:DRP11[3]
    55--------------------------MMCM0:CLKOUT4_DT[0]
    MMCM0:DRP11[0]    		MMCM0:CLKOUT4_DT[1]
    MMCM0:DRP11[1]
    56--------------------------MMCM0:CLKOUT4_PM[1]
    MMCM0:DRP10[14]    		MMCM0:CLKOUT4_PM[2]
    MMCM0:DRP10[15]
    57--------------------------MMCM0:CLKOUT4_EN
    MMCM0:DRP10[12]    		MMCM0:CLKOUT4_PM[0]
    MMCM0:DRP10[13]
    58--------------------------MMCM0:CLKOUT4_HT[4]
    MMCM0:DRP10[10]    		MMCM0:CLKOUT4_HT[5]
    MMCM0:DRP10[11]
    59--------------------------MMCM0:CLKOUT4_HT[2]
    MMCM0:DRP10[8]    		MMCM0:CLKOUT4_HT[3]
    MMCM0:DRP10[9]
    60--------------------------MMCM0:CLKOUT4_HT[0]
    MMCM0:DRP10[6]    		MMCM0:CLKOUT4_HT[1]
    MMCM0:DRP10[7]
    61--------------------------MMCM0:CLKOUT4_LT[4]
    MMCM0:DRP10[4]    		MMCM0:CLKOUT4_LT[5]
    MMCM0:DRP10[5]
    62--------------------------MMCM0:CLKOUT4_LT[2]
    MMCM0:DRP10[2]    		MMCM0:CLKOUT4_LT[3]
    MMCM0:DRP10[3]
    63--------------------------MMCM0:CLKOUT4_LT[0]
    MMCM0:DRP10[0]    		MMCM0:CLKOUT4_LT[1]
    MMCM0:DRP10[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 16
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP0F[14]MMCM0:DRP0F[15]
    1--------------------------MMCM0:DRP0F[12]MMCM0:DRP0F[13]
    2--------------------------MMCM0:DRP0F[10]MMCM0:DRP0F[11]
    3--------------------------MMCM0:CLKOUT3_MX[0]
    MMCM0:CLKOUT3_USE_FINE_PS
    MMCM0:DRP0F[8]    		MMCM0:CLKOUT3_MX[1]
    MMCM0:DRP0F[9]
    4--------------------------MMCM0:CLKOUT3_NOCOUNT
    MMCM0:DRP0F[6]    		MMCM0:CLKOUT3_EDGE
    MMCM0:DRP0F[7]
    5--------------------------MMCM0:CLKOUT3_DT[4]
    MMCM0:DRP0F[4]    		MMCM0:CLKOUT3_DT[5]
    MMCM0:DRP0F[5]
    6--------------------------MMCM0:CLKOUT3_DT[2]
    MMCM0:DRP0F[2]    		MMCM0:CLKOUT3_DT[3]
    MMCM0:DRP0F[3]
    7--------------------------MMCM0:CLKOUT3_DT[0]
    MMCM0:DRP0F[0]    		MMCM0:CLKOUT3_DT[1]
    MMCM0:DRP0F[1]
    8--------------------------MMCM0:CLKOUT3_PM[1]
    MMCM0:DRP0E[14]    		MMCM0:CLKOUT3_PM[2]
    MMCM0:DRP0E[15]
    9--------------------------MMCM0:CLKOUT3_EN
    MMCM0:DRP0E[12]    		MMCM0:CLKOUT3_PM[0]
    MMCM0:DRP0E[13]
    10--------------------------MMCM0:CLKOUT3_HT[4]
    MMCM0:DRP0E[10]    		MMCM0:CLKOUT3_HT[5]
    MMCM0:DRP0E[11]
    11--------------------------MMCM0:CLKOUT3_HT[2]
    MMCM0:DRP0E[8]    		MMCM0:CLKOUT3_HT[3]
    MMCM0:DRP0E[9]
    12--------------------------MMCM0:CLKOUT3_HT[0]
    MMCM0:DRP0E[6]    		MMCM0:CLKOUT3_HT[1]
    MMCM0:DRP0E[7]
    13--------------------------MMCM0:CLKOUT3_LT[4]
    MMCM0:DRP0E[4]    		MMCM0:CLKOUT3_LT[5]
    MMCM0:DRP0E[5]
    14--------------------------MMCM0:CLKOUT3_LT[2]
    MMCM0:DRP0E[2]    		MMCM0:CLKOUT3_LT[3]
    MMCM0:DRP0E[3]
    15--------------------------MMCM0:CLKOUT3_LT[0]
    MMCM0:DRP0E[0]    		MMCM0:CLKOUT3_LT[1]
    MMCM0:DRP0E[1]
    16--------------------------MMCM0:DRP0D[14]MMCM0:DRP0D[15]
    17--------------------------MMCM0:DRP0D[12]MMCM0:DRP0D[13]
    18--------------------------MMCM0:DRP0D[10]MMCM0:DRP0D[11]
    19--------------------------MMCM0:CLKOUT2_MX[0]
    MMCM0:CLKOUT2_USE_FINE_PS
    MMCM0:DRP0D[8]    		MMCM0:CLKOUT2_MX[1]
    MMCM0:DRP0D[9]
    20--------------------------MMCM0:CLKOUT2_NOCOUNT
    MMCM0:DRP0D[6]    		MMCM0:CLKOUT2_EDGE
    MMCM0:DRP0D[7]
    21--------------------------MMCM0:CLKOUT2_DT[4]
    MMCM0:DRP0D[4]    		MMCM0:CLKOUT2_DT[5]
    MMCM0:DRP0D[5]
    22--------------------------MMCM0:CLKOUT2_DT[2]
    MMCM0:DRP0D[2]    		MMCM0:CLKOUT2_DT[3]
    MMCM0:DRP0D[3]
    23--------------------------MMCM0:CLKOUT2_DT[0]
    MMCM0:DRP0D[0]    		MMCM0:CLKOUT2_DT[1]
    MMCM0:DRP0D[1]
    24--------------------------MMCM0:CLKOUT2_PM[1]
    MMCM0:DRP0C[14]    		MMCM0:CLKOUT2_PM[2]
    MMCM0:DRP0C[15]
    25--------------------------MMCM0:CLKOUT2_EN
    MMCM0:DRP0C[12]    		MMCM0:CLKOUT2_PM[0]
    MMCM0:DRP0C[13]
    26--------------------------MMCM0:CLKOUT2_HT[4]
    MMCM0:DRP0C[10]    		MMCM0:CLKOUT2_HT[5]
    MMCM0:DRP0C[11]
    27--------------------------MMCM0:CLKOUT2_HT[2]
    MMCM0:DRP0C[8]    		MMCM0:CLKOUT2_HT[3]
    MMCM0:DRP0C[9]
    28--------------------------MMCM0:CLKOUT2_HT[0]
    MMCM0:DRP0C[6]    		MMCM0:CLKOUT2_HT[1]
    MMCM0:DRP0C[7]
    29--------------------------MMCM0:CLKOUT2_LT[4]
    MMCM0:DRP0C[4]    		MMCM0:CLKOUT2_LT[5]
    MMCM0:DRP0C[5]
    30--------------------------MMCM0:CLKOUT2_LT[2]
    MMCM0:DRP0C[2]    		MMCM0:CLKOUT2_LT[3]
    MMCM0:DRP0C[3]
    31--------------------------MMCM0:CLKOUT2_LT[0]
    MMCM0:DRP0C[0]    		MMCM0:CLKOUT2_LT[1]
    MMCM0:DRP0C[1]
    32--------------------------MMCM0:DRP0B[14]MMCM0:DRP0B[15]
    33--------------------------MMCM0:DRP0B[12]MMCM0:DRP0B[13]
    34--------------------------MMCM0:DRP0B[10]MMCM0:DRP0B[11]
    35--------------------------MMCM0:CLKOUT1_MX[0]
    MMCM0:CLKOUT1_USE_FINE_PS
    MMCM0:DRP0B[8]    		MMCM0:CLKOUT1_MX[1]
    MMCM0:DRP0B[9]
    36--------------------------MMCM0:CLKOUT1_NOCOUNT
    MMCM0:DRP0B[6]    		MMCM0:CLKOUT1_EDGE
    MMCM0:DRP0B[7]
    37--------------------------MMCM0:CLKOUT1_DT[4]
    MMCM0:DRP0B[4]    		MMCM0:CLKOUT1_DT[5]
    MMCM0:DRP0B[5]
    38--------------------------MMCM0:CLKOUT1_DT[2]
    MMCM0:DRP0B[2]    		MMCM0:CLKOUT1_DT[3]
    MMCM0:DRP0B[3]
    39--------------------------MMCM0:CLKOUT1_DT[0]
    MMCM0:DRP0B[0]    		MMCM0:CLKOUT1_DT[1]
    MMCM0:DRP0B[1]
    40--------------------------MMCM0:CLKOUT1_PM[1]
    MMCM0:DRP0A[14]    		MMCM0:CLKOUT1_PM[2]
    MMCM0:DRP0A[15]
    41--------------------------MMCM0:CLKOUT1_EN
    MMCM0:DRP0A[12]    		MMCM0:CLKOUT1_PM[0]
    MMCM0:DRP0A[13]
    42--------------------------MMCM0:CLKOUT1_HT[4]
    MMCM0:DRP0A[10]    		MMCM0:CLKOUT1_HT[5]
    MMCM0:DRP0A[11]
    43--------------------------MMCM0:CLKOUT1_HT[2]
    MMCM0:DRP0A[8]    		MMCM0:CLKOUT1_HT[3]
    MMCM0:DRP0A[9]
    44--------------------------MMCM0:CLKOUT1_HT[0]
    MMCM0:DRP0A[6]    		MMCM0:CLKOUT1_HT[1]
    MMCM0:DRP0A[7]
    45--------------------------MMCM0:CLKOUT1_LT[4]
    MMCM0:DRP0A[4]    		MMCM0:CLKOUT1_LT[5]
    MMCM0:DRP0A[5]
    46--------------------------MMCM0:CLKOUT1_LT[2]
    MMCM0:DRP0A[2]    		MMCM0:CLKOUT1_LT[3]
    MMCM0:DRP0A[3]
    47--------------------------MMCM0:CLKOUT1_LT[0]
    MMCM0:DRP0A[0]    		MMCM0:CLKOUT1_LT[1]
    MMCM0:DRP0A[1]
    48--------------------------MMCM0:CLKOUT0_FRAC[2]
    MMCM0:DRP09[14]    		MMCM0:DRP09[15]
    49--------------------------MMCM0:CLKOUT0_FRAC[0]
    MMCM0:DRP09[12]    		MMCM0:CLKOUT0_FRAC[1]
    MMCM0:DRP09[13]
    50--------------------------MMCM0:CLKOUT0_FRAC_WF
    MMCM0:DRP09[10]    		MMCM0:CLKOUT0_FRAC_EN
    MMCM0:DRP09[11]
    51--------------------------MMCM0:CLKOUT0_MX[0]
    MMCM0:CLKOUT0_USE_FINE_PS
    MMCM0:DRP09[8]    		MMCM0:CLKOUT0_MX[1]
    MMCM0:DRP09[9]
    52--------------------------MMCM0:CLKOUT0_NOCOUNT
    MMCM0:DRP09[6]    		MMCM0:CLKOUT0_EDGE
    MMCM0:DRP09[7]
    53--------------------------MMCM0:CLKOUT0_DT[4]
    MMCM0:DRP09[4]    		MMCM0:CLKOUT0_DT[5]
    MMCM0:DRP09[5]
    54--------------------------MMCM0:CLKOUT0_DT[2]
    MMCM0:DRP09[2]    		MMCM0:CLKOUT0_DT[3]
    MMCM0:DRP09[3]
    55--------------------------MMCM0:CLKOUT0_DT[0]
    MMCM0:DRP09[0]    		MMCM0:CLKOUT0_DT[1]
    MMCM0:DRP09[1]
    56--------------------------MMCM0:CLKOUT0_PM[1]
    MMCM0:DRP08[14]    		MMCM0:CLKOUT0_PM[2]
    MMCM0:DRP08[15]
    57--------------------------MMCM0:CLKOUT0_EN
    MMCM0:DRP08[12]    		MMCM0:CLKOUT0_PM[0]
    MMCM0:DRP08[13]
    58--------------------------MMCM0:CLKOUT0_HT[4]
    MMCM0:DRP08[10]    		MMCM0:CLKOUT0_HT[5]
    MMCM0:DRP08[11]
    59--------------------------MMCM0:CLKOUT0_HT[2]
    MMCM0:DRP08[8]    		MMCM0:CLKOUT0_HT[3]
    MMCM0:DRP08[9]
    60--------------------------MMCM0:CLKOUT0_HT[0]
    MMCM0:DRP08[6]    		MMCM0:CLKOUT0_HT[1]
    MMCM0:DRP08[7]
    61--------------------------MMCM0:CLKOUT0_LT[4]
    MMCM0:DRP08[4]    		MMCM0:CLKOUT0_LT[5]
    MMCM0:DRP08[5]
    62--------------------------MMCM0:CLKOUT0_LT[2]
    MMCM0:DRP08[2]    		MMCM0:CLKOUT0_LT[3]
    MMCM0:DRP08[3]
    63--------------------------MMCM0:CLKOUT0_LT[0]
    MMCM0:DRP08[0]    		MMCM0:CLKOUT0_LT[1]
    MMCM0:DRP08[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 17
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM0:DRP07[14]MMCM0:DRP07[15]
    1--------------------------MMCM0:DRP07[12]MMCM0:DRP07[13]
    2--------------------------MMCM0:CLKOUT5_FRAC_WF
    MMCM0:DRP07[10]    		MMCM0:DRP07[11]
    3--------------------------MMCM0:CLKOUT5_MX[0]
    MMCM0:CLKOUT5_USE_FINE_PS
    MMCM0:DRP07[8]    		MMCM0:CLKOUT5_MX[1]
    MMCM0:DRP07[9]
    4--------------------------MMCM0:CLKOUT5_NOCOUNT
    MMCM0:DRP07[6]    		MMCM0:CLKOUT5_EDGE
    MMCM0:DRP07[7]
    5--------------------------MMCM0:CLKOUT5_DT[4]
    MMCM0:DRP07[4]    		MMCM0:CLKOUT5_DT[5]
    MMCM0:DRP07[5]
    6--------------------------MMCM0:CLKOUT5_DT[2]
    MMCM0:DRP07[2]    		MMCM0:CLKOUT5_DT[3]
    MMCM0:DRP07[3]
    7--------------------------MMCM0:CLKOUT5_DT[0]
    MMCM0:DRP07[0]    		MMCM0:CLKOUT5_DT[1]
    MMCM0:DRP07[1]
    8--------------------------MMCM0:CLKOUT5_PM[1]
    MMCM0:DRP06[14]    		MMCM0:CLKOUT5_PM[2]
    MMCM0:DRP06[15]
    9--------------------------MMCM0:CLKOUT5_EN
    MMCM0:DRP06[12]    		MMCM0:CLKOUT5_PM[0]
    MMCM0:DRP06[13]
    10--------------------------MMCM0:CLKOUT5_HT[4]
    MMCM0:DRP06[10]    		MMCM0:CLKOUT5_HT[5]
    MMCM0:DRP06[11]
    11--------------------------MMCM0:CLKOUT5_HT[2]
    MMCM0:DRP06[8]    		MMCM0:CLKOUT5_HT[3]
    MMCM0:DRP06[9]
    12--------------------------MMCM0:CLKOUT5_HT[0]
    MMCM0:DRP06[6]    		MMCM0:CLKOUT5_HT[1]
    MMCM0:DRP06[7]
    13--------------------------MMCM0:CLKOUT5_LT[4]
    MMCM0:DRP06[4]    		MMCM0:CLKOUT5_LT[5]
    MMCM0:DRP06[5]
    14--------------------------MMCM0:CLKOUT5_LT[2]
    MMCM0:DRP06[2]    		MMCM0:CLKOUT5_LT[3]
    MMCM0:DRP06[3]
    15--------------------------MMCM0:CLKOUT5_LT[0]
    MMCM0:DRP06[0]    		MMCM0:CLKOUT5_LT[1]
    MMCM0:DRP06[1]
    16--------------------------MMCM0:DRP05[14]
    MMCM0:IN_DLY_SET[4]    		MMCM0:DRP05[15]
    MMCM0:IN_DLY_EN
    17--------------------------MMCM0:DRP05[12]
    MMCM0:IN_DLY_SET[2]    		MMCM0:DRP05[13]
    MMCM0:IN_DLY_SET[3]
    18--------------------------MMCM0:DRP05[10]
    MMCM0:IN_DLY_SET[0]    		MMCM0:DRP05[11]
    MMCM0:IN_DLY_SET[1]
    19--------------------------MMCM0:DRP05[8]
    MMCM0:IN_DLY_MX_DVDD[4]    		MMCM0:DRP05[9]
    MMCM0:IN_DLY_MX_DVDD[5]
    20--------------------------MMCM0:DRP05[6]
    MMCM0:IN_DLY_MX_DVDD[2]    		MMCM0:DRP05[7]
    MMCM0:IN_DLY_MX_DVDD[3]
    21--------------------------MMCM0:DRP05[4]
    MMCM0:IN_DLY_MX_DVDD[0]    		MMCM0:DRP05[5]
    MMCM0:IN_DLY_MX_DVDD[1]
    22--------------------------MMCM0:DRP05[2]
    MMCM0:MUX.CASC_OUT[2]    		MMCM0:DIRECT_PATH_CNTRL
    MMCM0:DRP05[3]
    23--------------------------MMCM0:DRP05[0]
    MMCM0:MUX.CASC_OUT[0]    		MMCM0:DRP05[1]
    MMCM0:MUX.CASC_OUT[1]
    24--------------------------MMCM0:DRP04[14]
    MMCM0:TMUX_MUX_SEL[0]    		MMCM0:DRP04[15]
    MMCM0:TMUX_MUX_SEL[1]
    25--------------------------MMCM0:CLKBURST_ENABLE
    MMCM0:DRP04[12]    		MMCM0:CLKBURST_REPEAT
    MMCM0:DRP04[13]
    26--------------------------MMCM0:CLKBURST_CNT[2]
    MMCM0:DRP04[10]    		MMCM0:CLKBURST_CNT[3]
    MMCM0:DRP04[11]
    27--------------------------MMCM0:CLKBURST_CNT[0]
    MMCM0:DRP04[8]    		MMCM0:CLKBURST_CNT[1]
    MMCM0:DRP04[9]
    28--------------------------MMCM0:DRP04[6]
    MMCM0:MUX.PERF3[1]    		MMCM0:DRP04[7]
    MMCM0:MUX.PERF3[2]
    29--------------------------MMCM0:DRP04[4]
    MMCM0:MUX.PERF2[1]    		MMCM0:DRP04[5]
    MMCM0:MUX.PERF2[2]
    30--------------------------MMCM0:DRP04[2]
    MMCM0:MUX.PERF1[1]    		MMCM0:DRP04[3]
    MMCM0:MUX.PERF1[2]
    31--------------------------MMCM0:DRP04[0]
    MMCM0:MUX.PERF0[1]    		MMCM0:DRP04[1]
    MMCM0:MUX.PERF0[2]
    32--------------------------MMCM0:DRP03[14]
    MMCM0:MUX.PERF2[0]    		MMCM0:DRP03[15]
    MMCM0:MUX.PERF3[0]
    33--------------------------MMCM0:DRP03[12]
    MMCM0:MUX.PERF0[0]    		MMCM0:DRP03[13]
    MMCM0:MUX.PERF1[0]
    34--------------------------MMCM0:DRP03[10]MMCM0:DRP03[11]
    35--------------------------MMCM0:DRP03[8]MMCM0:DRP03[9]
    36--------------------------MMCM0:DRP03[6]MMCM0:DRP03[7]
    37--------------------------MMCM0:DRP03[4]MMCM0:DRP03[5]
    38--------------------------MMCM0:DRP03[2]MMCM0:DRP03[3]
    39--------------------------MMCM0:DRP03[0]MMCM0:DRP03[1]
    40--------------------------MMCM0:DRP02[14]MMCM0:DRP02[15]
    41--------------------------MMCM0:DRP02[12]MMCM0:DRP02[13]
    42--------------------------MMCM0:DRP02[10]MMCM0:DRP02[11]
    43--------------------------MMCM0:DRP02[8]MMCM0:DRP02[9]
    44--------------------------MMCM0:DRP02[6]MMCM0:DRP02[7]
    45--------------------------MMCM0:DRP02[4]MMCM0:DRP02[5]
    46--------------------------MMCM0:DRP02[2]MMCM0:DRP02[3]
    47--------------------------MMCM0:DRP02[0]
    MMCM0:SYNTH_CLK_DIV[0]    		MMCM0:DRP02[1]
    MMCM0:SYNTH_CLK_DIV[1]
    48--------------------------MMCM0:BUF.PERF3_IL
    MMCM0:DRP01[14]    		MMCM0:BUF.PERF2_OL
    MMCM0:DRP01[15]
    49--------------------------MMCM0:BUF.PERF2_OR
    MMCM0:DRP01[12]    		MMCM0:BUF.PERF3_IR
    MMCM0:DRP01[13]
    50--------------------------MMCM0:BUF.PERF2_IL
    MMCM0:DRP01[10]    		MMCM0:BUF.PERF3_OL
    MMCM0:DRP01[11]
    51--------------------------MMCM0:BUF.PERF3_OR
    MMCM0:DRP01[8]    		MMCM0:BUF.PERF2_IR
    MMCM0:DRP01[9]
    52--------------------------MMCM0:BUF.PERF1_IL
    MMCM0:DRP01[6]    		MMCM0:BUF.PERF0_OL
    MMCM0:DRP01[7]
    53--------------------------MMCM0:BUF.PERF0_OR
    MMCM0:DRP01[4]    		MMCM0:BUF.PERF1_IR
    MMCM0:DRP01[5]
    54--------------------------MMCM0:BUF.PERF0_IL
    MMCM0:DRP01[2]    		MMCM0:BUF.PERF1_OL
    MMCM0:DRP01[3]
    55--------------------------MMCM0:BUF.PERF1_OR
    MMCM0:DRP01[0]    		MMCM0:BUF.PERF0_IR
    MMCM0:DRP01[1]
    56--------------------------MMCM0:DRP00[14]
    MMCM0:HROW_DLY_SET[2]    		MMCM0:DRP00[15]
    57--------------------------MMCM0:DRP00[12]
    MMCM0:HROW_DLY_SET[0]    		MMCM0:DRP00[13]
    MMCM0:HROW_DLY_SET[1]
    58--------------------------MMCM0:DRP00[10]
    MMCM0:IN_DLY_MX_CVDD[4]    		MMCM0:DRP00[11]
    MMCM0:IN_DLY_MX_CVDD[5]
    59--------------------------MMCM0:DRP00[8]
    MMCM0:IN_DLY_MX_CVDD[2]    		MMCM0:DRP00[9]
    MMCM0:IN_DLY_MX_CVDD[3]
    60--------------------------MMCM0:DRP00[6]
    MMCM0:IN_DLY_MX_CVDD[0]    		MMCM0:DRP00[7]
    MMCM0:IN_DLY_MX_CVDD[1]
    61--------------------------MMCM0:DRP00[4]
    MMCM0:MUX.CLKIN2[0]    		MMCM0:DRP00[5]
    MMCM0:MUX.CLKIN2[1]
    62--------------------------MMCM0:DRP00[2]
    MMCM0:MUX.CLKIN1[0]    		MMCM0:DRP00[3]
    MMCM0:MUX.CLKIN1[1]
    63--------------------------MMCM0:DRP00[0]
    MMCM0:MUX.CLKFBIN[0]    		MMCM0:DRP00[1]
    MMCM0:MUX.CLKFBIN[1]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 18
    RowColumn
    0123456789101112131415161718192021222324252627282930313233
    0----------------------------------
    1----------------------------------
    2----------------------------------
    3----------------------------------
    4----------------------------------
    5----------------------------------
    6----------------------------------
    7----------------------------------
    8----------------------------------
    9----------------------------------
    10----------------------------------
    11----------------------------------
    12----------------------------------
    13----------------------------------
    14----------------------------------
    15----------------------------------
    16----------------------------------
    17----------------------------MMCM0:MUX.CLKFBIN_IO[6]MMCM0:MUX.CLKFBIN_IO[7]----
    18--------------------------BUFHCE_L0:INIT_OUT-MMCM0:MUX.CLKFBIN_IO[8]BUFHCE_L1:INIT_OUTBUFHCE_R0:INIT_OUT--BUFHCE_R1:INIT_OUT
    19--------------------------BUFHCE_L0:MUX.I[3]~BUFHCE_L0:INV.CE~BUFHCE_L1:INV.CEBUFHCE_L1:MUX.I[3]BUFHCE_R0:MUX.I[3]~BUFHCE_R0:INV.CE~BUFHCE_R1:INV.CEBUFHCE_R1:MUX.I[3]
    20--------------------------BUFHCE_L0:MUX.I[2]BUFHCE_L0:MUX.I[1]BUFHCE_L1:MUX.I[1]BUFHCE_L1:MUX.I[2]BUFHCE_R0:MUX.I[2]BUFHCE_R0:MUX.I[1]BUFHCE_R1:MUX.I[1]BUFHCE_R1:MUX.I[2]
    21--------------------------BUFHCE_L0:MUX.I[7]BUFHCE_L0:MUX.I[0]BUFHCE_L1:MUX.I[0]BUFHCE_L1:MUX.I[7]BUFHCE_R0:MUX.I[7]BUFHCE_R0:MUX.I[0]BUFHCE_R1:MUX.I[0]BUFHCE_R1:MUX.I[7]
    22--------------------------BUFHCE_L0:MUX.I[5]BUFHCE_L0:MUX.I[6]BUFHCE_L1:MUX.I[6]BUFHCE_L1:MUX.I[5]BUFHCE_R0:MUX.I[5]BUFHCE_R0:MUX.I[6]BUFHCE_R1:MUX.I[6]BUFHCE_R1:MUX.I[5]
    23--------------------------BUFHCE_L0:MUX.I[8]BUFHCE_L0:MUX.I[4]BUFHCE_L1:MUX.I[4]BUFHCE_L1:MUX.I[8]BUFHCE_R0:MUX.I[8]BUFHCE_R0:MUX.I[4]BUFHCE_R1:MUX.I[4]BUFHCE_R1:MUX.I[8]
    24--------------------------BUFHCE_L0:MUX.I[15]BUFHCE_L0:MUX.I[16]BUFHCE_L1:MUX.I[16]BUFHCE_L1:MUX.I[15]BUFHCE_R0:MUX.I[15]BUFHCE_R0:MUX.I[16]BUFHCE_R1:MUX.I[16]BUFHCE_R1:MUX.I[15]
    25----------------------------MMCM0:MUX.CLKFBIN_IO[2]MMCM0:MUX.CLKFBIN_IO[0]----
    26--------------------------BUFHCE_L0:MUX.I[14]-MMCM0:MUX.CLKFBIN_IO[5]BUFHCE_L1:MUX.I[14]BUFHCE_R0:MUX.I[14]--BUFHCE_R1:MUX.I[14]
    27---------------------------BUFHCE_L0:MUX.I[13]BUFHCE_L1:MUX.I[13]MMCM0:MUX.CLKFBIN_IO[4]-BUFHCE_R0:MUX.I[13]BUFHCE_R1:MUX.I[13]-
    28--------------------------BUFHCE_L0:MUX.I[12]-MMCM0:MUX.CLKFBIN_IO[3]BUFHCE_L1:MUX.I[12]BUFHCE_R0:MUX.I[12]--BUFHCE_R1:MUX.I[12]
    29---------------------------BUFHCE_L0:MUX.I[11]BUFHCE_L1:MUX.I[11]MMCM0:MUX.CLKFBIN_IO[1]-BUFHCE_R0:MUX.I[11]BUFHCE_R1:MUX.I[11]-
    30--------------------------BUFHCE_L0:MUX.I[10]BUFHCE_L0:ENABLEBUFHCE_L1:ENABLEBUFHCE_L1:MUX.I[10]BUFHCE_R0:MUX.I[10]BUFHCE_R0:ENABLEBUFHCE_R1:ENABLEBUFHCE_R1:MUX.I[10]
    31---------------------------BUFHCE_L0:MUX.I[9]BUFHCE_L1:MUX.I[9]--BUFHCE_R0:MUX.I[9]BUFHCE_R1:MUX.I[9]-
    32----------------------------------
    33----------------------------MMCM0:MUX.CLKIN1_IO[6]MMCM0:MUX.CLKIN1_IO[7]MMCM0:MUX.CLKIN2_IO[7]MMCM0:MUX.CLKIN2_IO[6]--
    34--------------------------BUFHCE_L2:INIT_OUT-MMCM0:MUX.CLKIN1_IO[8]BUFHCE_L3:INIT_OUTBUFHCE_R2:INIT_OUTMMCM0:MUX.CLKIN2_IO[8]-BUFHCE_R3:INIT_OUT
    35--------------------------BUFHCE_L2:MUX.I[3]~BUFHCE_L2:INV.CE~BUFHCE_L3:INV.CEBUFHCE_L3:MUX.I[3]BUFHCE_R2:MUX.I[3]~BUFHCE_R2:INV.CE~BUFHCE_R3:INV.CEBUFHCE_R3:MUX.I[3]
    36--------------------------BUFHCE_L2:MUX.I[2]BUFHCE_L2:MUX.I[1]BUFHCE_L3:MUX.I[1]BUFHCE_L3:MUX.I[2]BUFHCE_R2:MUX.I[2]BUFHCE_R2:MUX.I[1]BUFHCE_R3:MUX.I[1]BUFHCE_R3:MUX.I[2]
    37--------------------------BUFHCE_L2:MUX.I[7]BUFHCE_L2:MUX.I[0]BUFHCE_L3:MUX.I[0]BUFHCE_L3:MUX.I[7]BUFHCE_R2:MUX.I[7]BUFHCE_R2:MUX.I[0]BUFHCE_R3:MUX.I[0]BUFHCE_R3:MUX.I[7]
    38--------------------------BUFHCE_L2:MUX.I[5]BUFHCE_L2:MUX.I[6]BUFHCE_L3:MUX.I[6]BUFHCE_L3:MUX.I[5]BUFHCE_R2:MUX.I[5]BUFHCE_R2:MUX.I[6]BUFHCE_R3:MUX.I[6]BUFHCE_R3:MUX.I[5]
    39--------------------------BUFHCE_L2:MUX.I[8]BUFHCE_L2:MUX.I[4]BUFHCE_L3:MUX.I[4]BUFHCE_L3:MUX.I[8]BUFHCE_R2:MUX.I[8]BUFHCE_R2:MUX.I[4]BUFHCE_R3:MUX.I[4]BUFHCE_R3:MUX.I[8]
    40--------------------------BUFHCE_L2:MUX.I[15]BUFHCE_L2:MUX.I[16]BUFHCE_L3:MUX.I[16]BUFHCE_L3:MUX.I[15]BUFHCE_R2:MUX.I[15]BUFHCE_R2:MUX.I[16]BUFHCE_R3:MUX.I[16]BUFHCE_R3:MUX.I[15]
    41----------------------------MMCM0:MUX.CLKIN1_IO[2]MMCM0:MUX.CLKIN1_IO[0]MMCM0:MUX.CLKIN2_IO[0]MMCM0:MUX.CLKIN2_IO[2]--
    42--------------------------BUFHCE_L2:MUX.I[14]-MMCM0:MUX.CLKIN1_IO[5]BUFHCE_L3:MUX.I[14]BUFHCE_R2:MUX.I[14]MMCM0:MUX.CLKIN2_IO[5]-BUFHCE_R3:MUX.I[14]
    43---------------------------BUFHCE_L2:MUX.I[13]BUFHCE_L3:MUX.I[13]MMCM0:MUX.CLKIN1_IO[4]MMCM0:MUX.CLKIN2_IO[4]BUFHCE_R2:MUX.I[13]BUFHCE_R3:MUX.I[13]-
    44--------------------------BUFHCE_L2:MUX.I[12]-MMCM0:MUX.CLKIN1_IO[3]BUFHCE_L3:MUX.I[12]BUFHCE_R2:MUX.I[12]MMCM0:MUX.CLKIN2_IO[3]-BUFHCE_R3:MUX.I[12]
    45---------------------------BUFHCE_L2:MUX.I[11]BUFHCE_L3:MUX.I[11]MMCM0:MUX.CLKIN1_IO[1]MMCM0:MUX.CLKIN2_IO[1]BUFHCE_R2:MUX.I[11]BUFHCE_R3:MUX.I[11]-
    46--------------------------BUFHCE_L2:MUX.I[10]BUFHCE_L2:ENABLEBUFHCE_L3:ENABLEBUFHCE_L3:MUX.I[10]BUFHCE_R2:MUX.I[10]BUFHCE_R2:ENABLEBUFHCE_R3:ENABLEBUFHCE_R3:MUX.I[10]
    47---------------------------BUFHCE_L2:MUX.I[9]BUFHCE_L3:MUX.I[9]--BUFHCE_R2:MUX.I[9]BUFHCE_R3:MUX.I[9]-
    48-----------------------------MMCM0:MUX.CLKIN1_MGT[6]MMCM0:MUX.CLKIN2_MGT[6]---
    49----------------------------MMCM0:MUX.CLKIN1_MGT[8]MMCM0:MUX.CLKIN1_MGT[7]MMCM0:MUX.CLKIN2_MGT[7]MMCM0:MUX.CLKIN2_MGT[8]--
    50--------------------------BUFHCE_L4:INIT_OUT-MMCM0:MUX.CLKIN1_MGT[9]BUFHCE_L5:INIT_OUTBUFHCE_R4:INIT_OUTMMCM0:MUX.CLKIN2_MGT[9]-BUFHCE_R5:INIT_OUT
    51--------------------------BUFHCE_L4:MUX.I[3]~BUFHCE_L4:INV.CE~BUFHCE_L5:INV.CEBUFHCE_L5:MUX.I[3]BUFHCE_R4:MUX.I[3]~BUFHCE_R4:INV.CE~BUFHCE_R5:INV.CEBUFHCE_R5:MUX.I[3]
    52--------------------------BUFHCE_L4:MUX.I[2]BUFHCE_L4:MUX.I[1]BUFHCE_L5:MUX.I[1]BUFHCE_L5:MUX.I[2]BUFHCE_R4:MUX.I[2]BUFHCE_R4:MUX.I[1]BUFHCE_R5:MUX.I[1]BUFHCE_R5:MUX.I[2]
    53--------------------------BUFHCE_L4:MUX.I[7]BUFHCE_L4:MUX.I[0]BUFHCE_L5:MUX.I[0]BUFHCE_L5:MUX.I[7]BUFHCE_R4:MUX.I[7]BUFHCE_R4:MUX.I[0]BUFHCE_R5:MUX.I[0]BUFHCE_R5:MUX.I[7]
    54--------------------------BUFHCE_L4:MUX.I[5]BUFHCE_L4:MUX.I[6]BUFHCE_L5:MUX.I[6]BUFHCE_L5:MUX.I[5]BUFHCE_R4:MUX.I[5]BUFHCE_R4:MUX.I[6]BUFHCE_R5:MUX.I[6]BUFHCE_R5:MUX.I[5]
    55--------------------------BUFHCE_L4:MUX.I[8]BUFHCE_L4:MUX.I[4]BUFHCE_L5:MUX.I[4]BUFHCE_L5:MUX.I[8]BUFHCE_R4:MUX.I[8]BUFHCE_R4:MUX.I[4]BUFHCE_R5:MUX.I[4]BUFHCE_R5:MUX.I[8]
    56--------------------------BUFHCE_L4:MUX.I[15]BUFHCE_L4:MUX.I[16]BUFHCE_L5:MUX.I[16]BUFHCE_L5:MUX.I[15]BUFHCE_R4:MUX.I[15]BUFHCE_R4:MUX.I[16]BUFHCE_R5:MUX.I[16]BUFHCE_R5:MUX.I[15]
    57----------------------------MMCM0:MUX.CLKIN1_MGT[2]MMCM0:MUX.CLKIN1_MGT[0]MMCM0:MUX.CLKIN2_MGT[0]MMCM0:MUX.CLKIN2_MGT[2]--
    58--------------------------BUFHCE_L4:MUX.I[14]-MMCM0:MUX.CLKIN1_MGT[5]BUFHCE_L5:MUX.I[14]BUFHCE_R4:MUX.I[14]MMCM0:MUX.CLKIN2_MGT[5]-BUFHCE_R5:MUX.I[14]
    59---------------------------BUFHCE_L4:MUX.I[13]BUFHCE_L5:MUX.I[13]MMCM0:MUX.CLKIN1_MGT[4]MMCM0:MUX.CLKIN2_MGT[4]BUFHCE_R4:MUX.I[13]BUFHCE_R5:MUX.I[13]-
    60--------------------------BUFHCE_L4:MUX.I[12]-MMCM0:MUX.CLKIN1_MGT[3]BUFHCE_L5:MUX.I[12]BUFHCE_R4:MUX.I[12]MMCM0:MUX.CLKIN2_MGT[3]-BUFHCE_R5:MUX.I[12]
    61---------------------------BUFHCE_L4:MUX.I[11]BUFHCE_L5:MUX.I[11]MMCM0:MUX.CLKIN1_MGT[1]MMCM0:MUX.CLKIN2_MGT[1]BUFHCE_R4:MUX.I[11]BUFHCE_R5:MUX.I[11]-
    62--------------------------BUFHCE_L4:MUX.I[10]BUFHCE_L4:ENABLEBUFHCE_L5:ENABLEBUFHCE_L5:MUX.I[10]BUFHCE_R4:MUX.I[10]BUFHCE_R4:ENABLEBUFHCE_R5:ENABLEBUFHCE_R5:MUX.I[10]
    63---------------------------BUFHCE_L4:MUX.I[9]BUFHCE_L5:MUX.I[9]--BUFHCE_R4:MUX.I[9]BUFHCE_R5:MUX.I[9]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 19
    RowColumn
    0123456789101112131415161718192021222324252627282930313233
    0---------------------------CMT:INV.GCLK0_TESTCMT:INV.GCLK1_TEST-MMCM0:MUX.CLKIN1_HCLKCMT:INV.GCLK3_TESTCMT:INV.GCLK2_TEST-
    1----------------------------MMCM0:MUX.CLKIN1_HCLK_L[8]MMCM0:MUX.CLKIN1_HCLK_L[6]MMCM1:MUX.CLKIN1_HCLK_L[6]MMCM1:MUX.CLKIN1_HCLK_L[8]--
    2--------------------------CMT:MUX.CASCO0[0]-MMCM0:MUX.CLKIN1_HCLK_L[7]-CMT:MUX.CASCO3[0]MMCM1:MUX.CLKIN1_HCLK_L[7]--
    3--------------------------CMT:MUX.CASCO0[9]CMT:MUX.CASCO1[0]-CMT:MUX.CASCO1[9]CMT:MUX.CASCO3[9]CMT:MUX.CASCO2[0]-CMT:MUX.CASCO2[9]
    4--------------------------CMT:MUX.CASCO0[8]CMT:MUX.CASCO0[7]CMT:MUX.CASCO1[7]CMT:MUX.CASCO1[8]CMT:MUX.CASCO3[8]CMT:MUX.CASCO3[7]CMT:MUX.CASCO2[7]CMT:MUX.CASCO2[8]
    5--------------------------CMT:MUX.CASCO0[1]CMT:MUX.CASCO0[6]CMT:MUX.CASCO1[6]CMT:MUX.CASCO1[1]CMT:MUX.CASCO3[1]CMT:MUX.CASCO3[6]CMT:MUX.CASCO2[6]CMT:MUX.CASCO2[1]
    6--------------------------CMT:MUX.CASCO0[4]CMT:MUX.CASCO0[2]CMT:MUX.CASCO1[2]CMT:MUX.CASCO1[4]CMT:MUX.CASCO3[4]CMT:MUX.CASCO3[2]CMT:MUX.CASCO2[2]CMT:MUX.CASCO2[4]
    7--------------------------CMT:MUX.CASCO0[3]CMT:MUX.CASCO0[5]CMT:MUX.CASCO1[5]CMT:MUX.CASCO1[3]CMT:MUX.CASCO3[3]CMT:MUX.CASCO3[5]CMT:MUX.CASCO2[5]CMT:MUX.CASCO2[3]
    8--------------------------CMT:MUX.CASCO0[16]CMT:MUX.CASCO0[17]CMT:MUX.CASCO1[17]CMT:MUX.CASCO1[16]CMT:MUX.CASCO3[16]CMT:MUX.CASCO3[17]CMT:MUX.CASCO2[17]CMT:MUX.CASCO2[16]
    9----------------------------MMCM0:MUX.CLKIN1_HCLK_L[5]MMCM0:MUX.CLKIN1_HCLK_L[4]MMCM1:MUX.CLKIN1_HCLK_L[4]MMCM1:MUX.CLKIN1_HCLK_L[5]--
    10--------------------------CMT:MUX.CASCO0[15]-MMCM0:MUX.CLKIN1_HCLK_L[3]CMT:MUX.CASCO1[15]CMT:MUX.CASCO3[15]MMCM1:MUX.CLKIN1_HCLK_L[3]-CMT:MUX.CASCO2[15]
    11---------------------------CMT:MUX.CASCO0[14]CMT:MUX.CASCO1[14]MMCM0:MUX.CLKIN1_HCLK_L[2]MMCM1:MUX.CLKIN1_HCLK_L[2]CMT:MUX.CASCO3[14]CMT:MUX.CASCO2[14]-
    12--------------------------CMT:MUX.CASCO0[13]-MMCM0:MUX.CLKIN1_HCLK_L[1]CMT:MUX.CASCO1[13]CMT:MUX.CASCO3[13]MMCM1:MUX.CLKIN1_HCLK_L[1]-CMT:MUX.CASCO2[13]
    13---------------------------CMT:MUX.CASCO0[12]CMT:MUX.CASCO1[12]MMCM0:MUX.CLKIN1_HCLK_L[0]MMCM1:MUX.CLKIN1_HCLK_L[0]CMT:MUX.CASCO3[12]CMT:MUX.CASCO2[12]-
    14--------------------------CMT:MUX.CASCO0[11]CMT:BUF.GCLK0_TESTCMT:BUF.GCLK1_TESTCMT:MUX.CASCO1[11]CMT:MUX.CASCO3[11]CMT:BUF.GCLK3_TESTCMT:BUF.GCLK2_TESTCMT:MUX.CASCO2[11]
    15---------------------------CMT:MUX.CASCO0[10]CMT:MUX.CASCO1[10]--CMT:MUX.CASCO3[10]CMT:MUX.CASCO2[10]-
    16---------------------------CMT:INV.GCLK4_TESTCMT:INV.GCLK5_TEST-MMCM0:MUX.CLKIN2_HCLKCMT:INV.GCLK7_TESTCMT:INV.GCLK6_TEST-
    17----------------------------MMCM0:MUX.CLKIN2_HCLK_L[8]MMCM0:MUX.CLKIN2_HCLK_L[6]MMCM1:MUX.CLKIN2_HCLK_L[6]MMCM1:MUX.CLKIN2_HCLK_L[8]--
    18--------------------------CMT:MUX.CASCO4[0]-MMCM0:MUX.CLKIN2_HCLK_L[7]-CMT:MUX.CASCO7[0]MMCM1:MUX.CLKIN2_HCLK_L[7]--
    19--------------------------CMT:MUX.CASCO4[9]CMT:MUX.CASCO5[0]-CMT:MUX.CASCO5[9]CMT:MUX.CASCO7[9]CMT:MUX.CASCO6[0]-CMT:MUX.CASCO6[9]
    20--------------------------CMT:MUX.CASCO4[8]CMT:MUX.CASCO4[7]CMT:MUX.CASCO5[7]CMT:MUX.CASCO5[8]CMT:MUX.CASCO7[8]CMT:MUX.CASCO7[7]CMT:MUX.CASCO6[7]CMT:MUX.CASCO6[8]
    21--------------------------CMT:MUX.CASCO4[1]CMT:MUX.CASCO4[6]CMT:MUX.CASCO5[6]CMT:MUX.CASCO5[1]CMT:MUX.CASCO7[1]CMT:MUX.CASCO7[6]CMT:MUX.CASCO6[6]CMT:MUX.CASCO6[1]
    22--------------------------CMT:MUX.CASCO4[4]CMT:MUX.CASCO4[2]CMT:MUX.CASCO5[2]CMT:MUX.CASCO5[4]CMT:MUX.CASCO7[4]CMT:MUX.CASCO7[2]CMT:MUX.CASCO6[2]CMT:MUX.CASCO6[4]
    23--------------------------CMT:MUX.CASCO4[3]CMT:MUX.CASCO4[5]CMT:MUX.CASCO5[5]CMT:MUX.CASCO5[3]CMT:MUX.CASCO7[3]CMT:MUX.CASCO7[5]CMT:MUX.CASCO6[5]CMT:MUX.CASCO6[3]
    24--------------------------CMT:MUX.CASCO4[16]CMT:MUX.CASCO4[17]CMT:MUX.CASCO5[17]CMT:MUX.CASCO5[16]CMT:MUX.CASCO7[16]CMT:MUX.CASCO7[17]CMT:MUX.CASCO6[17]CMT:MUX.CASCO6[16]
    25----------------------------MMCM0:MUX.CLKIN2_HCLK_L[5]MMCM0:MUX.CLKIN2_HCLK_L[4]MMCM1:MUX.CLKIN2_HCLK_L[4]MMCM1:MUX.CLKIN2_HCLK_L[5]--
    26--------------------------CMT:MUX.CASCO4[15]-MMCM0:MUX.CLKIN2_HCLK_L[3]CMT:MUX.CASCO5[15]CMT:MUX.CASCO7[15]MMCM1:MUX.CLKIN2_HCLK_L[3]-CMT:MUX.CASCO6[15]
    27---------------------------CMT:MUX.CASCO4[14]CMT:MUX.CASCO5[14]MMCM0:MUX.CLKIN2_HCLK_L[2]MMCM1:MUX.CLKIN2_HCLK_L[2]CMT:MUX.CASCO7[14]CMT:MUX.CASCO6[14]-
    28--------------------------CMT:MUX.CASCO4[13]-MMCM0:MUX.CLKIN2_HCLK_L[1]CMT:MUX.CASCO5[13]CMT:MUX.CASCO7[13]MMCM1:MUX.CLKIN2_HCLK_L[1]-CMT:MUX.CASCO6[13]
    29---------------------------CMT:MUX.CASCO4[12]CMT:MUX.CASCO5[12]MMCM0:MUX.CLKIN2_HCLK_L[0]MMCM1:MUX.CLKIN2_HCLK_L[0]CMT:MUX.CASCO7[12]CMT:MUX.CASCO6[12]-
    30--------------------------CMT:MUX.CASCO4[11]CMT:BUF.GCLK4_TESTCMT:BUF.GCLK5_TESTCMT:MUX.CASCO5[11]CMT:MUX.CASCO7[11]CMT:BUF.GCLK7_TESTCMT:BUF.GCLK6_TESTCMT:MUX.CASCO6[11]
    31---------------------------CMT:MUX.CASCO4[10]CMT:MUX.CASCO5[10]--CMT:MUX.CASCO7[10]CMT:MUX.CASCO6[10]-
    32---------------------------CMT:INV.GCLK8_TESTCMT:INV.GCLK9_TEST-MMCM0:MUX.CLKFBIN_HCLKCMT:INV.GCLK11_TESTCMT:INV.GCLK10_TEST-
    33----------------------------MMCM0:MUX.CLKFBIN_HCLK_L[8]MMCM0:MUX.CLKFBIN_HCLK_L[6]MMCM1:MUX.CLKFBIN_HCLK_L[6]MMCM1:MUX.CLKFBIN_HCLK_L[8]--
    34--------------------------CMT:MUX.CASCO8[0]-MMCM0:MUX.CLKFBIN_HCLK_L[7]-CMT:MUX.CASCO11[0]MMCM1:MUX.CLKFBIN_HCLK_L[7]--
    35--------------------------CMT:MUX.CASCO8[9]CMT:MUX.CASCO9[0]-CMT:MUX.CASCO9[9]CMT:MUX.CASCO11[9]CMT:MUX.CASCO10[0]-CMT:MUX.CASCO10[9]
    36--------------------------CMT:MUX.CASCO8[8]CMT:MUX.CASCO8[7]CMT:MUX.CASCO9[7]CMT:MUX.CASCO9[8]CMT:MUX.CASCO11[8]CMT:MUX.CASCO11[7]CMT:MUX.CASCO10[7]CMT:MUX.CASCO10[8]
    37--------------------------CMT:MUX.CASCO8[1]CMT:MUX.CASCO8[6]CMT:MUX.CASCO9[6]CMT:MUX.CASCO9[1]CMT:MUX.CASCO11[1]CMT:MUX.CASCO11[6]CMT:MUX.CASCO10[6]CMT:MUX.CASCO10[1]
    38--------------------------CMT:MUX.CASCO8[4]CMT:MUX.CASCO8[2]CMT:MUX.CASCO9[2]CMT:MUX.CASCO9[4]CMT:MUX.CASCO11[4]CMT:MUX.CASCO11[2]CMT:MUX.CASCO10[2]CMT:MUX.CASCO10[4]
    39--------------------------CMT:MUX.CASCO8[3]CMT:MUX.CASCO8[5]CMT:MUX.CASCO9[5]CMT:MUX.CASCO9[3]CMT:MUX.CASCO11[3]CMT:MUX.CASCO11[5]CMT:MUX.CASCO10[5]CMT:MUX.CASCO10[3]
    40--------------------------CMT:MUX.CASCO8[16]CMT:MUX.CASCO8[17]CMT:MUX.CASCO9[17]CMT:MUX.CASCO9[16]CMT:MUX.CASCO11[16]CMT:MUX.CASCO11[17]CMT:MUX.CASCO10[17]CMT:MUX.CASCO10[16]
    41----------------------------MMCM0:MUX.CLKFBIN_HCLK_L[5]MMCM0:MUX.CLKFBIN_HCLK_L[4]MMCM1:MUX.CLKFBIN_HCLK_L[4]MMCM1:MUX.CLKFBIN_HCLK_L[5]--
    42--------------------------CMT:MUX.CASCO8[15]-MMCM0:MUX.CLKFBIN_HCLK_L[3]CMT:MUX.CASCO9[15]CMT:MUX.CASCO11[15]MMCM1:MUX.CLKFBIN_HCLK_L[3]-CMT:MUX.CASCO10[15]
    43---------------------------CMT:MUX.CASCO8[14]CMT:MUX.CASCO9[14]MMCM0:MUX.CLKFBIN_HCLK_L[2]MMCM1:MUX.CLKFBIN_HCLK_L[2]CMT:MUX.CASCO11[14]CMT:MUX.CASCO10[14]-
    44--------------------------CMT:MUX.CASCO8[13]-MMCM0:MUX.CLKFBIN_HCLK_L[1]CMT:MUX.CASCO9[13]CMT:MUX.CASCO11[13]MMCM1:MUX.CLKFBIN_HCLK_L[1]-CMT:MUX.CASCO10[13]
    45---------------------------CMT:MUX.CASCO8[12]CMT:MUX.CASCO9[12]MMCM0:MUX.CLKFBIN_HCLK_L[0]MMCM1:MUX.CLKFBIN_HCLK_L[0]CMT:MUX.CASCO11[12]CMT:MUX.CASCO10[12]-
    46--------------------------CMT:MUX.CASCO8[11]CMT:BUF.GCLK8_TESTCMT:BUF.GCLK9_TESTCMT:MUX.CASCO9[11]CMT:MUX.CASCO11[11]CMT:BUF.GCLK11_TESTCMT:BUF.GCLK10_TESTCMT:MUX.CASCO10[11]
    47---------------------------CMT:MUX.CASCO8[10]CMT:MUX.CASCO9[10]--CMT:MUX.CASCO11[10]CMT:MUX.CASCO10[10]-
    48---------------------------CMT:INV.GCLK12_TESTCMT:INV.GCLK13_TEST-CMT:INV.BUFH_TEST_LCMT:INV.GCLK15_TESTCMT:INV.GCLK14_TEST-
    49----------------------------CMT:MUX.BUFH_TEST_L[8]CMT:MUX.BUFH_TEST_L[6]----
    50--------------------------CMT:MUX.CASCO12[0]-CMT:MUX.BUFH_TEST_L[7]-CMT:MUX.CASCO15[0]---
    51--------------------------CMT:MUX.CASCO12[9]CMT:MUX.CASCO13[0]-CMT:MUX.CASCO13[9]CMT:MUX.CASCO15[9]CMT:MUX.CASCO14[0]-CMT:MUX.CASCO14[9]
    52--------------------------CMT:MUX.CASCO12[8]CMT:MUX.CASCO12[7]CMT:MUX.CASCO13[7]CMT:MUX.CASCO13[8]CMT:MUX.CASCO15[8]CMT:MUX.CASCO15[7]CMT:MUX.CASCO14[7]CMT:MUX.CASCO14[8]
    53--------------------------CMT:MUX.CASCO12[1]CMT:MUX.CASCO12[6]CMT:MUX.CASCO13[6]CMT:MUX.CASCO13[1]CMT:MUX.CASCO15[1]CMT:MUX.CASCO15[6]CMT:MUX.CASCO14[6]CMT:MUX.CASCO14[1]
    54--------------------------CMT:MUX.CASCO12[4]CMT:MUX.CASCO12[2]CMT:MUX.CASCO13[2]CMT:MUX.CASCO13[4]CMT:MUX.CASCO15[4]CMT:MUX.CASCO15[2]CMT:MUX.CASCO14[2]CMT:MUX.CASCO14[4]
    55--------------------------CMT:MUX.CASCO12[3]CMT:MUX.CASCO12[5]CMT:MUX.CASCO13[5]CMT:MUX.CASCO13[3]CMT:MUX.CASCO15[3]CMT:MUX.CASCO15[5]CMT:MUX.CASCO14[5]CMT:MUX.CASCO14[3]
    56--------------------------CMT:MUX.CASCO12[16]CMT:MUX.CASCO12[17]CMT:MUX.CASCO13[17]CMT:MUX.CASCO13[16]CMT:MUX.CASCO15[16]CMT:MUX.CASCO15[17]CMT:MUX.CASCO14[17]CMT:MUX.CASCO14[16]
    57----------------------------CMT:MUX.BUFH_TEST_L[5]CMT:MUX.BUFH_TEST_L[4]----
    58--------------------------CMT:MUX.CASCO12[15]-CMT:MUX.BUFH_TEST_L[3]CMT:MUX.CASCO13[15]CMT:MUX.CASCO15[15]--CMT:MUX.CASCO14[15]
    59---------------------------CMT:MUX.CASCO12[14]CMT:MUX.CASCO13[14]CMT:MUX.BUFH_TEST_L[2]-CMT:MUX.CASCO15[14]CMT:MUX.CASCO14[14]-
    60--------------------------CMT:MUX.CASCO12[13]-CMT:MUX.BUFH_TEST_L[1]CMT:MUX.CASCO13[13]CMT:MUX.CASCO15[13]--CMT:MUX.CASCO14[13]
    61---------------------------CMT:MUX.CASCO12[12]CMT:MUX.CASCO13[12]CMT:MUX.BUFH_TEST_L[0]-CMT:MUX.CASCO15[12]CMT:MUX.CASCO14[12]-
    62--------------------------CMT:MUX.CASCO12[11]CMT:BUF.GCLK12_TESTCMT:BUF.GCLK13_TESTCMT:MUX.CASCO13[11]CMT:MUX.CASCO15[11]CMT:BUF.GCLK15_TESTCMT:BUF.GCLK14_TESTCMT:MUX.CASCO14[11]
    63---------------------------CMT:MUX.CASCO12[10]CMT:MUX.CASCO13[10]--CMT:MUX.CASCO15[10]CMT:MUX.CASCO14[10]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 20
    RowColumn
    0123456789101112131415161718192021222324252627282930313233
    0---------------------------CMT:INV.GCLK16_TESTCMT:INV.GCLK17_TEST-CMT:INV.BUFH_TEST_RCMT:INV.GCLK19_TESTCMT:INV.GCLK18_TEST-
    1----------------------------CMT:MUX.BUFH_TEST_R[8]CMT:MUX.BUFH_TEST_R[6]----
    2--------------------------CMT:MUX.CASCO16[0]-CMT:MUX.BUFH_TEST_R[7]-CMT:MUX.CASCO19[0]---
    3--------------------------CMT:MUX.CASCO16[9]CMT:MUX.CASCO17[0]-CMT:MUX.CASCO17[9]CMT:MUX.CASCO19[9]CMT:MUX.CASCO18[0]-CMT:MUX.CASCO18[9]
    4--------------------------CMT:MUX.CASCO16[8]CMT:MUX.CASCO16[7]CMT:MUX.CASCO17[7]CMT:MUX.CASCO17[8]CMT:MUX.CASCO19[8]CMT:MUX.CASCO19[7]CMT:MUX.CASCO18[7]CMT:MUX.CASCO18[8]
    5--------------------------CMT:MUX.CASCO16[1]CMT:MUX.CASCO16[6]CMT:MUX.CASCO17[6]CMT:MUX.CASCO17[1]CMT:MUX.CASCO19[1]CMT:MUX.CASCO19[6]CMT:MUX.CASCO18[6]CMT:MUX.CASCO18[1]
    6--------------------------CMT:MUX.CASCO16[4]CMT:MUX.CASCO16[2]CMT:MUX.CASCO17[2]CMT:MUX.CASCO17[4]CMT:MUX.CASCO19[4]CMT:MUX.CASCO19[2]CMT:MUX.CASCO18[2]CMT:MUX.CASCO18[4]
    7--------------------------CMT:MUX.CASCO16[3]CMT:MUX.CASCO16[5]CMT:MUX.CASCO17[5]CMT:MUX.CASCO17[3]CMT:MUX.CASCO19[3]CMT:MUX.CASCO19[5]CMT:MUX.CASCO18[5]CMT:MUX.CASCO18[3]
    8--------------------------CMT:MUX.CASCO16[16]CMT:MUX.CASCO16[17]CMT:MUX.CASCO17[17]CMT:MUX.CASCO17[16]CMT:MUX.CASCO19[16]CMT:MUX.CASCO19[17]CMT:MUX.CASCO18[17]CMT:MUX.CASCO18[16]
    9----------------------------CMT:MUX.BUFH_TEST_R[5]CMT:MUX.BUFH_TEST_R[4]----
    10--------------------------CMT:MUX.CASCO16[15]-CMT:MUX.BUFH_TEST_R[3]CMT:MUX.CASCO17[15]CMT:MUX.CASCO19[15]--CMT:MUX.CASCO18[15]
    11---------------------------CMT:MUX.CASCO16[14]CMT:MUX.CASCO17[14]CMT:MUX.BUFH_TEST_R[2]-CMT:MUX.CASCO19[14]CMT:MUX.CASCO18[14]-
    12--------------------------CMT:MUX.CASCO16[13]-CMT:MUX.BUFH_TEST_R[1]CMT:MUX.CASCO17[13]CMT:MUX.CASCO19[13]--CMT:MUX.CASCO18[13]
    13---------------------------CMT:MUX.CASCO16[12]CMT:MUX.CASCO17[12]CMT:MUX.BUFH_TEST_R[0]-CMT:MUX.CASCO19[12]CMT:MUX.CASCO18[12]-
    14--------------------------CMT:MUX.CASCO16[11]CMT:BUF.GCLK16_TESTCMT:BUF.GCLK17_TESTCMT:MUX.CASCO17[11]CMT:MUX.CASCO19[11]CMT:BUF.GCLK19_TESTCMT:BUF.GCLK18_TESTCMT:MUX.CASCO18[11]
    15---------------------------CMT:MUX.CASCO16[10]CMT:MUX.CASCO17[10]--CMT:MUX.CASCO19[10]CMT:MUX.CASCO18[10]-
    16---------------------------CMT:INV.GCLK20_TESTCMT:INV.GCLK21_TEST-MMCM1:MUX.CLKFBIN_HCLKCMT:INV.GCLK23_TESTCMT:INV.GCLK22_TEST-
    17----------------------------MMCM1:MUX.CLKFBIN_HCLK_R[8]MMCM1:MUX.CLKFBIN_HCLK_R[6]MMCM0:MUX.CLKFBIN_HCLK_R[6]MMCM0:MUX.CLKFBIN_HCLK_R[8]--
    18--------------------------CMT:MUX.CASCO20[0]-MMCM1:MUX.CLKFBIN_HCLK_R[7]-CMT:MUX.CASCO23[0]MMCM0:MUX.CLKFBIN_HCLK_R[7]--
    19--------------------------CMT:MUX.CASCO20[9]CMT:MUX.CASCO21[0]-CMT:MUX.CASCO21[9]CMT:MUX.CASCO23[9]CMT:MUX.CASCO22[0]-CMT:MUX.CASCO22[9]
    20--------------------------CMT:MUX.CASCO20[8]CMT:MUX.CASCO20[7]CMT:MUX.CASCO21[7]CMT:MUX.CASCO21[8]CMT:MUX.CASCO23[8]CMT:MUX.CASCO23[7]CMT:MUX.CASCO22[7]CMT:MUX.CASCO22[8]
    21--------------------------CMT:MUX.CASCO20[1]CMT:MUX.CASCO20[6]CMT:MUX.CASCO21[6]CMT:MUX.CASCO21[1]CMT:MUX.CASCO23[1]CMT:MUX.CASCO23[6]CMT:MUX.CASCO22[6]CMT:MUX.CASCO22[1]
    22--------------------------CMT:MUX.CASCO20[4]CMT:MUX.CASCO20[2]CMT:MUX.CASCO21[2]CMT:MUX.CASCO21[4]CMT:MUX.CASCO23[4]CMT:MUX.CASCO23[2]CMT:MUX.CASCO22[2]CMT:MUX.CASCO22[4]
    23--------------------------CMT:MUX.CASCO20[3]CMT:MUX.CASCO20[5]CMT:MUX.CASCO21[5]CMT:MUX.CASCO21[3]CMT:MUX.CASCO23[3]CMT:MUX.CASCO23[5]CMT:MUX.CASCO22[5]CMT:MUX.CASCO22[3]
    24--------------------------CMT:MUX.CASCO20[16]CMT:MUX.CASCO20[17]CMT:MUX.CASCO21[17]CMT:MUX.CASCO21[16]CMT:MUX.CASCO23[16]CMT:MUX.CASCO23[17]CMT:MUX.CASCO22[17]CMT:MUX.CASCO22[16]
    25----------------------------MMCM1:MUX.CLKFBIN_HCLK_R[5]MMCM1:MUX.CLKFBIN_HCLK_R[4]MMCM0:MUX.CLKFBIN_HCLK_R[4]MMCM0:MUX.CLKFBIN_HCLK_R[5]--
    26--------------------------CMT:MUX.CASCO20[15]-MMCM1:MUX.CLKFBIN_HCLK_R[3]CMT:MUX.CASCO21[15]CMT:MUX.CASCO23[15]MMCM0:MUX.CLKFBIN_HCLK_R[3]-CMT:MUX.CASCO22[15]
    27---------------------------CMT:MUX.CASCO20[14]CMT:MUX.CASCO21[14]MMCM1:MUX.CLKFBIN_HCLK_R[2]MMCM0:MUX.CLKFBIN_HCLK_R[2]CMT:MUX.CASCO23[14]CMT:MUX.CASCO22[14]-
    28--------------------------CMT:MUX.CASCO20[13]-MMCM1:MUX.CLKFBIN_HCLK_R[1]CMT:MUX.CASCO21[13]CMT:MUX.CASCO23[13]MMCM0:MUX.CLKFBIN_HCLK_R[1]-CMT:MUX.CASCO22[13]
    29---------------------------CMT:MUX.CASCO20[12]CMT:MUX.CASCO21[12]MMCM1:MUX.CLKFBIN_HCLK_R[0]MMCM0:MUX.CLKFBIN_HCLK_R[0]CMT:MUX.CASCO23[12]CMT:MUX.CASCO22[12]-
    30--------------------------CMT:MUX.CASCO20[11]CMT:BUF.GCLK20_TESTCMT:BUF.GCLK21_TESTCMT:MUX.CASCO21[11]CMT:MUX.CASCO23[11]CMT:BUF.GCLK23_TESTCMT:BUF.GCLK22_TESTCMT:MUX.CASCO22[11]
    31---------------------------CMT:MUX.CASCO20[10]CMT:MUX.CASCO21[10]--CMT:MUX.CASCO23[10]CMT:MUX.CASCO22[10]-
    32---------------------------CMT:INV.GCLK24_TESTCMT:INV.GCLK25_TEST-MMCM1:MUX.CLKIN2_HCLKCMT:INV.GCLK27_TESTCMT:INV.GCLK26_TEST-
    33----------------------------MMCM1:MUX.CLKIN2_HCLK_R[8]MMCM1:MUX.CLKIN2_HCLK_R[6]MMCM0:MUX.CLKIN2_HCLK_R[6]MMCM0:MUX.CLKIN2_HCLK_R[8]--
    34--------------------------CMT:MUX.CASCO24[0]-MMCM1:MUX.CLKIN2_HCLK_R[7]-CMT:MUX.CASCO27[0]MMCM0:MUX.CLKIN2_HCLK_R[7]--
    35--------------------------CMT:MUX.CASCO24[9]CMT:MUX.CASCO25[0]-CMT:MUX.CASCO25[9]CMT:MUX.CASCO27[9]CMT:MUX.CASCO26[0]-CMT:MUX.CASCO26[9]
    36--------------------------CMT:MUX.CASCO24[8]CMT:MUX.CASCO24[7]CMT:MUX.CASCO25[7]CMT:MUX.CASCO25[8]CMT:MUX.CASCO27[8]CMT:MUX.CASCO27[7]CMT:MUX.CASCO26[7]CMT:MUX.CASCO26[8]
    37--------------------------CMT:MUX.CASCO24[1]CMT:MUX.CASCO24[6]CMT:MUX.CASCO25[6]CMT:MUX.CASCO25[1]CMT:MUX.CASCO27[1]CMT:MUX.CASCO27[6]CMT:MUX.CASCO26[6]CMT:MUX.CASCO26[1]
    38--------------------------CMT:MUX.CASCO24[4]CMT:MUX.CASCO24[2]CMT:MUX.CASCO25[2]CMT:MUX.CASCO25[4]CMT:MUX.CASCO27[4]CMT:MUX.CASCO27[2]CMT:MUX.CASCO26[2]CMT:MUX.CASCO26[4]
    39--------------------------CMT:MUX.CASCO24[3]CMT:MUX.CASCO24[5]CMT:MUX.CASCO25[5]CMT:MUX.CASCO25[3]CMT:MUX.CASCO27[3]CMT:MUX.CASCO27[5]CMT:MUX.CASCO26[5]CMT:MUX.CASCO26[3]
    40--------------------------CMT:MUX.CASCO24[16]CMT:MUX.CASCO24[17]CMT:MUX.CASCO25[17]CMT:MUX.CASCO25[16]CMT:MUX.CASCO27[16]CMT:MUX.CASCO27[17]CMT:MUX.CASCO26[17]CMT:MUX.CASCO26[16]
    41----------------------------MMCM1:MUX.CLKIN2_HCLK_R[5]MMCM1:MUX.CLKIN2_HCLK_R[4]MMCM0:MUX.CLKIN2_HCLK_R[4]MMCM0:MUX.CLKIN2_HCLK_R[5]--
    42--------------------------CMT:MUX.CASCO24[15]-MMCM1:MUX.CLKIN2_HCLK_R[3]CMT:MUX.CASCO25[15]CMT:MUX.CASCO27[15]MMCM0:MUX.CLKIN2_HCLK_R[3]-CMT:MUX.CASCO26[15]
    43---------------------------CMT:MUX.CASCO24[14]CMT:MUX.CASCO25[14]MMCM1:MUX.CLKIN2_HCLK_R[2]MMCM0:MUX.CLKIN2_HCLK_R[2]CMT:MUX.CASCO27[14]CMT:MUX.CASCO26[14]-
    44--------------------------CMT:MUX.CASCO24[13]-MMCM1:MUX.CLKIN2_HCLK_R[1]CMT:MUX.CASCO25[13]CMT:MUX.CASCO27[13]MMCM0:MUX.CLKIN2_HCLK_R[1]-CMT:MUX.CASCO26[13]
    45---------------------------CMT:MUX.CASCO24[12]CMT:MUX.CASCO25[12]MMCM1:MUX.CLKIN2_HCLK_R[0]MMCM0:MUX.CLKIN2_HCLK_R[0]CMT:MUX.CASCO27[12]CMT:MUX.CASCO26[12]-
    46--------------------------CMT:MUX.CASCO24[11]CMT:BUF.GCLK24_TESTCMT:BUF.GCLK25_TESTCMT:MUX.CASCO25[11]CMT:MUX.CASCO27[11]CMT:BUF.GCLK27_TESTCMT:BUF.GCLK26_TESTCMT:MUX.CASCO26[11]
    47---------------------------CMT:MUX.CASCO24[10]CMT:MUX.CASCO25[10]--CMT:MUX.CASCO27[10]CMT:MUX.CASCO26[10]-
    48---------------------------CMT:INV.GCLK28_TESTCMT:INV.GCLK29_TEST-MMCM1:MUX.CLKIN1_HCLKCMT:INV.GCLK31_TESTCMT:INV.GCLK30_TEST-
    49----------------------------MMCM1:MUX.CLKIN1_HCLK_R[8]MMCM1:MUX.CLKIN1_HCLK_R[6]MMCM0:MUX.CLKIN1_HCLK_R[6]MMCM0:MUX.CLKIN1_HCLK_R[8]--
    50--------------------------CMT:MUX.CASCO28[0]-MMCM1:MUX.CLKIN1_HCLK_R[7]-CMT:MUX.CASCO31[0]MMCM0:MUX.CLKIN1_HCLK_R[7]--
    51--------------------------CMT:MUX.CASCO28[9]CMT:MUX.CASCO29[0]-CMT:MUX.CASCO29[9]CMT:MUX.CASCO31[9]CMT:MUX.CASCO30[0]-CMT:MUX.CASCO30[9]
    52--------------------------CMT:MUX.CASCO28[8]CMT:MUX.CASCO28[7]CMT:MUX.CASCO29[7]CMT:MUX.CASCO29[8]CMT:MUX.CASCO31[8]CMT:MUX.CASCO31[7]CMT:MUX.CASCO30[7]CMT:MUX.CASCO30[8]
    53--------------------------CMT:MUX.CASCO28[1]CMT:MUX.CASCO28[6]CMT:MUX.CASCO29[6]CMT:MUX.CASCO29[1]CMT:MUX.CASCO31[1]CMT:MUX.CASCO31[6]CMT:MUX.CASCO30[6]CMT:MUX.CASCO30[1]
    54--------------------------CMT:MUX.CASCO28[4]CMT:MUX.CASCO28[2]CMT:MUX.CASCO29[2]CMT:MUX.CASCO29[4]CMT:MUX.CASCO31[4]CMT:MUX.CASCO31[2]CMT:MUX.CASCO30[2]CMT:MUX.CASCO30[4]
    55--------------------------CMT:MUX.CASCO28[3]CMT:MUX.CASCO28[5]CMT:MUX.CASCO29[5]CMT:MUX.CASCO29[3]CMT:MUX.CASCO31[3]CMT:MUX.CASCO31[5]CMT:MUX.CASCO30[5]CMT:MUX.CASCO30[3]
    56--------------------------CMT:MUX.CASCO28[16]CMT:MUX.CASCO28[17]CMT:MUX.CASCO29[17]CMT:MUX.CASCO29[16]CMT:MUX.CASCO31[16]CMT:MUX.CASCO31[17]CMT:MUX.CASCO30[17]CMT:MUX.CASCO30[16]
    57----------------------------MMCM1:MUX.CLKIN1_HCLK_R[5]MMCM1:MUX.CLKIN1_HCLK_R[4]MMCM0:MUX.CLKIN1_HCLK_R[4]MMCM0:MUX.CLKIN1_HCLK_R[5]--
    58--------------------------CMT:MUX.CASCO28[15]-MMCM1:MUX.CLKIN1_HCLK_R[3]CMT:MUX.CASCO29[15]CMT:MUX.CASCO31[15]MMCM0:MUX.CLKIN1_HCLK_R[3]-CMT:MUX.CASCO30[15]
    59---------------------------CMT:MUX.CASCO28[14]CMT:MUX.CASCO29[14]MMCM1:MUX.CLKIN1_HCLK_R[2]MMCM0:MUX.CLKIN1_HCLK_R[2]CMT:MUX.CASCO31[14]CMT:MUX.CASCO30[14]-
    60--------------------------CMT:MUX.CASCO28[13]-MMCM1:MUX.CLKIN1_HCLK_R[1]CMT:MUX.CASCO29[13]CMT:MUX.CASCO31[13]MMCM0:MUX.CLKIN1_HCLK_R[1]-CMT:MUX.CASCO30[13]
    61---------------------------CMT:MUX.CASCO28[12]CMT:MUX.CASCO29[12]MMCM1:MUX.CLKIN1_HCLK_R[0]MMCM0:MUX.CLKIN1_HCLK_R[0]CMT:MUX.CASCO31[12]CMT:MUX.CASCO30[12]-
    62--------------------------CMT:MUX.CASCO28[11]CMT:BUF.GCLK28_TESTCMT:BUF.GCLK29_TESTCMT:MUX.CASCO29[11]CMT:MUX.CASCO31[11]CMT:BUF.GCLK31_TESTCMT:BUF.GCLK30_TESTCMT:MUX.CASCO30[11]
    63---------------------------CMT:MUX.CASCO28[10]CMT:MUX.CASCO29[10]--CMT:MUX.CASCO31[10]CMT:MUX.CASCO30[10]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 21
    RowColumn
    0123456789101112131415161718192021222324252627282930313233
    0-----------------------------MMCM1:MUX.CLKIN1_MGT[6]MMCM1:MUX.CLKIN2_MGT[6]---
    1----------------------------MMCM1:MUX.CLKIN1_MGT[8]MMCM1:MUX.CLKIN1_MGT[7]MMCM1:MUX.CLKIN2_MGT[7]MMCM1:MUX.CLKIN2_MGT[8]--
    2--------------------------BUFHCE_L6:INIT_OUT-MMCM1:MUX.CLKIN1_MGT[9]BUFHCE_L7:INIT_OUTBUFHCE_R6:INIT_OUTMMCM1:MUX.CLKIN2_MGT[9]-BUFHCE_R7:INIT_OUT
    3--------------------------BUFHCE_L6:MUX.I[3]~BUFHCE_L6:INV.CE~BUFHCE_L7:INV.CEBUFHCE_L7:MUX.I[3]BUFHCE_R6:MUX.I[3]~BUFHCE_R6:INV.CE~BUFHCE_R7:INV.CEBUFHCE_R7:MUX.I[3]
    4--------------------------BUFHCE_L6:MUX.I[2]BUFHCE_L6:MUX.I[1]BUFHCE_L7:MUX.I[1]BUFHCE_L7:MUX.I[2]BUFHCE_R6:MUX.I[2]BUFHCE_R6:MUX.I[1]BUFHCE_R7:MUX.I[1]BUFHCE_R7:MUX.I[2]
    5--------------------------BUFHCE_L6:MUX.I[7]BUFHCE_L6:MUX.I[0]BUFHCE_L7:MUX.I[0]BUFHCE_L7:MUX.I[7]BUFHCE_R6:MUX.I[7]BUFHCE_R6:MUX.I[0]BUFHCE_R7:MUX.I[0]BUFHCE_R7:MUX.I[7]
    6--------------------------BUFHCE_L6:MUX.I[5]BUFHCE_L6:MUX.I[6]BUFHCE_L7:MUX.I[6]BUFHCE_L7:MUX.I[5]BUFHCE_R6:MUX.I[5]BUFHCE_R6:MUX.I[6]BUFHCE_R7:MUX.I[6]BUFHCE_R7:MUX.I[5]
    7--------------------------BUFHCE_L6:MUX.I[8]BUFHCE_L6:MUX.I[4]BUFHCE_L7:MUX.I[4]BUFHCE_L7:MUX.I[8]BUFHCE_R6:MUX.I[8]BUFHCE_R6:MUX.I[4]BUFHCE_R7:MUX.I[4]BUFHCE_R7:MUX.I[8]
    8--------------------------BUFHCE_L6:MUX.I[15]BUFHCE_L6:MUX.I[16]BUFHCE_L7:MUX.I[16]BUFHCE_L7:MUX.I[15]BUFHCE_R6:MUX.I[15]BUFHCE_R6:MUX.I[16]BUFHCE_R7:MUX.I[16]BUFHCE_R7:MUX.I[15]
    9----------------------------MMCM1:MUX.CLKIN1_MGT[2]MMCM1:MUX.CLKIN1_MGT[0]MMCM1:MUX.CLKIN2_MGT[0]MMCM1:MUX.CLKIN2_MGT[2]--
    10--------------------------BUFHCE_L6:MUX.I[14]-MMCM1:MUX.CLKIN1_MGT[5]BUFHCE_L7:MUX.I[14]BUFHCE_R6:MUX.I[14]MMCM1:MUX.CLKIN2_MGT[5]-BUFHCE_R7:MUX.I[14]
    11---------------------------BUFHCE_L6:MUX.I[13]BUFHCE_L7:MUX.I[13]MMCM1:MUX.CLKIN1_MGT[4]MMCM1:MUX.CLKIN2_MGT[4]BUFHCE_R6:MUX.I[13]BUFHCE_R7:MUX.I[13]-
    12--------------------------BUFHCE_L6:MUX.I[12]-MMCM1:MUX.CLKIN1_MGT[3]BUFHCE_L7:MUX.I[12]BUFHCE_R6:MUX.I[12]MMCM1:MUX.CLKIN2_MGT[3]-BUFHCE_R7:MUX.I[12]
    13---------------------------BUFHCE_L6:MUX.I[11]BUFHCE_L7:MUX.I[11]MMCM1:MUX.CLKIN1_MGT[1]MMCM1:MUX.CLKIN2_MGT[1]BUFHCE_R6:MUX.I[11]BUFHCE_R7:MUX.I[11]-
    14--------------------------BUFHCE_L6:MUX.I[10]BUFHCE_L6:ENABLEBUFHCE_L7:ENABLEBUFHCE_L7:MUX.I[10]BUFHCE_R6:MUX.I[10]BUFHCE_R6:ENABLEBUFHCE_R7:ENABLEBUFHCE_R7:MUX.I[10]
    15---------------------------BUFHCE_L6:MUX.I[9]BUFHCE_L7:MUX.I[9]--BUFHCE_R6:MUX.I[9]BUFHCE_R7:MUX.I[9]-
    16----------------------------------
    17----------------------------MMCM1:MUX.CLKIN1_IO[6]MMCM1:MUX.CLKIN1_IO[7]MMCM1:MUX.CLKIN2_IO[7]MMCM1:MUX.CLKIN2_IO[6]--
    18--------------------------BUFHCE_L8:INIT_OUT-MMCM1:MUX.CLKIN1_IO[8]BUFHCE_L9:INIT_OUTBUFHCE_R8:INIT_OUTMMCM1:MUX.CLKIN2_IO[8]-BUFHCE_R9:INIT_OUT
    19--------------------------BUFHCE_L8:MUX.I[3]~BUFHCE_L8:INV.CE~BUFHCE_L9:INV.CEBUFHCE_L9:MUX.I[3]BUFHCE_R8:MUX.I[3]~BUFHCE_R8:INV.CE~BUFHCE_R9:INV.CEBUFHCE_R9:MUX.I[3]
    20--------------------------BUFHCE_L8:MUX.I[2]BUFHCE_L8:MUX.I[1]BUFHCE_L9:MUX.I[1]BUFHCE_L9:MUX.I[2]BUFHCE_R8:MUX.I[2]BUFHCE_R8:MUX.I[1]BUFHCE_R9:MUX.I[1]BUFHCE_R9:MUX.I[2]
    21--------------------------BUFHCE_L8:MUX.I[7]BUFHCE_L8:MUX.I[0]BUFHCE_L9:MUX.I[0]BUFHCE_L9:MUX.I[7]BUFHCE_R8:MUX.I[7]BUFHCE_R8:MUX.I[0]BUFHCE_R9:MUX.I[0]BUFHCE_R9:MUX.I[7]
    22--------------------------BUFHCE_L8:MUX.I[5]BUFHCE_L8:MUX.I[6]BUFHCE_L9:MUX.I[6]BUFHCE_L9:MUX.I[5]BUFHCE_R8:MUX.I[5]BUFHCE_R8:MUX.I[6]BUFHCE_R9:MUX.I[6]BUFHCE_R9:MUX.I[5]
    23--------------------------BUFHCE_L8:MUX.I[8]BUFHCE_L8:MUX.I[4]BUFHCE_L9:MUX.I[4]BUFHCE_L9:MUX.I[8]BUFHCE_R8:MUX.I[8]BUFHCE_R8:MUX.I[4]BUFHCE_R9:MUX.I[4]BUFHCE_R9:MUX.I[8]
    24--------------------------BUFHCE_L8:MUX.I[15]BUFHCE_L8:MUX.I[16]BUFHCE_L9:MUX.I[16]BUFHCE_L9:MUX.I[15]BUFHCE_R8:MUX.I[15]BUFHCE_R8:MUX.I[16]BUFHCE_R9:MUX.I[16]BUFHCE_R9:MUX.I[15]
    25----------------------------MMCM1:MUX.CLKIN1_IO[2]MMCM1:MUX.CLKIN1_IO[0]MMCM1:MUX.CLKIN2_IO[0]MMCM1:MUX.CLKIN2_IO[2]--
    26--------------------------BUFHCE_L8:MUX.I[14]-MMCM1:MUX.CLKIN1_IO[5]BUFHCE_L9:MUX.I[14]BUFHCE_R8:MUX.I[14]MMCM1:MUX.CLKIN2_IO[5]-BUFHCE_R9:MUX.I[14]
    27---------------------------BUFHCE_L8:MUX.I[13]BUFHCE_L9:MUX.I[13]MMCM1:MUX.CLKIN1_IO[4]MMCM1:MUX.CLKIN2_IO[4]BUFHCE_R8:MUX.I[13]BUFHCE_R9:MUX.I[13]-
    28--------------------------BUFHCE_L8:MUX.I[12]-MMCM1:MUX.CLKIN1_IO[3]BUFHCE_L9:MUX.I[12]BUFHCE_R8:MUX.I[12]MMCM1:MUX.CLKIN2_IO[3]-BUFHCE_R9:MUX.I[12]
    29---------------------------BUFHCE_L8:MUX.I[11]BUFHCE_L9:MUX.I[11]MMCM1:MUX.CLKIN1_IO[1]MMCM1:MUX.CLKIN2_IO[1]BUFHCE_R8:MUX.I[11]BUFHCE_R9:MUX.I[11]-
    30--------------------------BUFHCE_L8:MUX.I[10]BUFHCE_L8:ENABLEBUFHCE_L9:ENABLEBUFHCE_L9:MUX.I[10]BUFHCE_R8:MUX.I[10]BUFHCE_R8:ENABLEBUFHCE_R9:ENABLEBUFHCE_R9:MUX.I[10]
    31---------------------------BUFHCE_L8:MUX.I[9]BUFHCE_L9:MUX.I[9]--BUFHCE_R8:MUX.I[9]BUFHCE_R9:MUX.I[9]-
    32----------------------------------
    33----------------------------MMCM1:MUX.CLKFBIN_IO[6]MMCM1:MUX.CLKFBIN_IO[7]----
    34--------------------------BUFHCE_L10:INIT_OUT-MMCM1:MUX.CLKFBIN_IO[8]BUFHCE_L11:INIT_OUTBUFHCE_R10:INIT_OUT--BUFHCE_R11:INIT_OUT
    35--------------------------BUFHCE_L10:MUX.I[3]~BUFHCE_L10:INV.CE~BUFHCE_L11:INV.CEBUFHCE_L11:MUX.I[3]BUFHCE_R10:MUX.I[3]~BUFHCE_R10:INV.CE~BUFHCE_R11:INV.CEBUFHCE_R11:MUX.I[3]
    36--------------------------BUFHCE_L10:MUX.I[2]BUFHCE_L10:MUX.I[1]BUFHCE_L11:MUX.I[1]BUFHCE_L11:MUX.I[2]BUFHCE_R10:MUX.I[2]BUFHCE_R10:MUX.I[1]BUFHCE_R11:MUX.I[1]BUFHCE_R11:MUX.I[2]
    37--------------------------BUFHCE_L10:MUX.I[7]BUFHCE_L10:MUX.I[0]BUFHCE_L11:MUX.I[0]BUFHCE_L11:MUX.I[7]BUFHCE_R10:MUX.I[7]BUFHCE_R10:MUX.I[0]BUFHCE_R11:MUX.I[0]BUFHCE_R11:MUX.I[7]
    38--------------------------BUFHCE_L10:MUX.I[5]BUFHCE_L10:MUX.I[6]BUFHCE_L11:MUX.I[6]BUFHCE_L11:MUX.I[5]BUFHCE_R10:MUX.I[5]BUFHCE_R10:MUX.I[6]BUFHCE_R11:MUX.I[6]BUFHCE_R11:MUX.I[5]
    39--------------------------BUFHCE_L10:MUX.I[8]BUFHCE_L10:MUX.I[4]BUFHCE_L11:MUX.I[4]BUFHCE_L11:MUX.I[8]BUFHCE_R10:MUX.I[8]BUFHCE_R10:MUX.I[4]BUFHCE_R11:MUX.I[4]BUFHCE_R11:MUX.I[8]
    40--------------------------BUFHCE_L10:MUX.I[15]BUFHCE_L10:MUX.I[16]BUFHCE_L11:MUX.I[16]BUFHCE_L11:MUX.I[15]BUFHCE_R10:MUX.I[15]BUFHCE_R10:MUX.I[16]BUFHCE_R11:MUX.I[16]BUFHCE_R11:MUX.I[15]
    41----------------------------MMCM1:MUX.CLKFBIN_IO[2]MMCM1:MUX.CLKFBIN_IO[0]----
    42--------------------------BUFHCE_L10:MUX.I[14]-MMCM1:MUX.CLKFBIN_IO[5]BUFHCE_L11:MUX.I[14]BUFHCE_R10:MUX.I[14]--BUFHCE_R11:MUX.I[14]
    43---------------------------BUFHCE_L10:MUX.I[13]BUFHCE_L11:MUX.I[13]MMCM1:MUX.CLKFBIN_IO[4]-BUFHCE_R10:MUX.I[13]BUFHCE_R11:MUX.I[13]-
    44--------------------------BUFHCE_L10:MUX.I[12]-MMCM1:MUX.CLKFBIN_IO[3]BUFHCE_L11:MUX.I[12]BUFHCE_R10:MUX.I[12]--BUFHCE_R11:MUX.I[12]
    45---------------------------BUFHCE_L10:MUX.I[11]BUFHCE_L11:MUX.I[11]MMCM1:MUX.CLKFBIN_IO[1]-BUFHCE_R10:MUX.I[11]BUFHCE_R11:MUX.I[11]-
    46--------------------------BUFHCE_L10:MUX.I[10]BUFHCE_L10:ENABLEBUFHCE_L11:ENABLEBUFHCE_L11:MUX.I[10]BUFHCE_R10:MUX.I[10]BUFHCE_R10:ENABLEBUFHCE_R11:ENABLEBUFHCE_R11:MUX.I[10]
    47---------------------------BUFHCE_L10:MUX.I[9]BUFHCE_L11:MUX.I[9]--BUFHCE_R10:MUX.I[9]BUFHCE_R11:MUX.I[9]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 22
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP00[0]
    MMCM1:MUX.CLKFBIN[0]    		MMCM1:DRP00[1]
    MMCM1:MUX.CLKFBIN[1]
    1--------------------------MMCM1:DRP00[2]
    MMCM1:MUX.CLKIN1[0]    		MMCM1:DRP00[3]
    MMCM1:MUX.CLKIN1[1]
    2--------------------------MMCM1:DRP00[4]
    MMCM1:MUX.CLKIN2[0]    		MMCM1:DRP00[5]
    MMCM1:MUX.CLKIN2[1]
    3--------------------------MMCM1:DRP00[6]
    MMCM1:IN_DLY_MX_CVDD[0]    		MMCM1:DRP00[7]
    MMCM1:IN_DLY_MX_CVDD[1]
    4--------------------------MMCM1:DRP00[8]
    MMCM1:IN_DLY_MX_CVDD[2]    		MMCM1:DRP00[9]
    MMCM1:IN_DLY_MX_CVDD[3]
    5--------------------------MMCM1:DRP00[10]
    MMCM1:IN_DLY_MX_CVDD[4]    		MMCM1:DRP00[11]
    MMCM1:IN_DLY_MX_CVDD[5]
    6--------------------------MMCM1:DRP00[12]
    MMCM1:HROW_DLY_SET[0]    		MMCM1:DRP00[13]
    MMCM1:HROW_DLY_SET[1]
    7--------------------------MMCM1:DRP00[14]
    MMCM1:HROW_DLY_SET[2]    		MMCM1:DRP00[15]
    8--------------------------MMCM1:BUF.PERF1_OR
    MMCM1:DRP01[0]    		MMCM1:BUF.PERF0_IR
    MMCM1:DRP01[1]
    9--------------------------MMCM1:BUF.PERF0_IL
    MMCM1:DRP01[2]    		MMCM1:BUF.PERF1_OL
    MMCM1:DRP01[3]
    10--------------------------MMCM1:BUF.PERF0_OR
    MMCM1:DRP01[4]    		MMCM1:BUF.PERF1_IR
    MMCM1:DRP01[5]
    11--------------------------MMCM1:BUF.PERF1_IL
    MMCM1:DRP01[6]    		MMCM1:BUF.PERF0_OL
    MMCM1:DRP01[7]
    12--------------------------MMCM1:BUF.PERF3_OR
    MMCM1:DRP01[8]    		MMCM1:BUF.PERF2_IR
    MMCM1:DRP01[9]
    13--------------------------MMCM1:BUF.PERF2_IL
    MMCM1:DRP01[10]    		MMCM1:BUF.PERF3_OL
    MMCM1:DRP01[11]
    14--------------------------MMCM1:BUF.PERF2_OR
    MMCM1:DRP01[12]    		MMCM1:BUF.PERF3_IR
    MMCM1:DRP01[13]
    15--------------------------MMCM1:BUF.PERF3_IL
    MMCM1:DRP01[14]    		MMCM1:BUF.PERF2_OL
    MMCM1:DRP01[15]
    16--------------------------MMCM1:DRP02[0]
    MMCM1:SYNTH_CLK_DIV[0]    		MMCM1:DRP02[1]
    MMCM1:SYNTH_CLK_DIV[1]
    17--------------------------MMCM1:DRP02[2]MMCM1:DRP02[3]
    18--------------------------MMCM1:DRP02[4]MMCM1:DRP02[5]
    19--------------------------MMCM1:DRP02[6]MMCM1:DRP02[7]
    20--------------------------MMCM1:DRP02[8]MMCM1:DRP02[9]
    21--------------------------MMCM1:DRP02[10]MMCM1:DRP02[11]
    22--------------------------MMCM1:DRP02[12]MMCM1:DRP02[13]
    23--------------------------MMCM1:DRP02[14]MMCM1:DRP02[15]
    24--------------------------MMCM1:DRP03[0]MMCM1:DRP03[1]
    25--------------------------MMCM1:DRP03[2]MMCM1:DRP03[3]
    26--------------------------MMCM1:DRP03[4]MMCM1:DRP03[5]
    27--------------------------MMCM1:DRP03[6]MMCM1:DRP03[7]
    28--------------------------MMCM1:DRP03[8]MMCM1:DRP03[9]
    29--------------------------MMCM1:DRP03[10]MMCM1:DRP03[11]
    30--------------------------MMCM1:DRP03[12]
    MMCM1:MUX.PERF0[0]    		MMCM1:DRP03[13]
    MMCM1:MUX.PERF1[0]
    31--------------------------MMCM1:DRP03[14]
    MMCM1:MUX.PERF2[0]    		MMCM1:DRP03[15]
    MMCM1:MUX.PERF3[0]
    32--------------------------MMCM1:DRP04[0]
    MMCM1:MUX.PERF0[1]    		MMCM1:DRP04[1]
    MMCM1:MUX.PERF0[2]
    33--------------------------MMCM1:DRP04[2]
    MMCM1:MUX.PERF1[1]    		MMCM1:DRP04[3]
    MMCM1:MUX.PERF1[2]
    34--------------------------MMCM1:DRP04[4]
    MMCM1:MUX.PERF2[1]    		MMCM1:DRP04[5]
    MMCM1:MUX.PERF2[2]
    35--------------------------MMCM1:DRP04[6]
    MMCM1:MUX.PERF3[1]    		MMCM1:DRP04[7]
    MMCM1:MUX.PERF3[2]
    36--------------------------MMCM1:CLKBURST_CNT[0]
    MMCM1:DRP04[8]    		MMCM1:CLKBURST_CNT[1]
    MMCM1:DRP04[9]
    37--------------------------MMCM1:CLKBURST_CNT[2]
    MMCM1:DRP04[10]    		MMCM1:CLKBURST_CNT[3]
    MMCM1:DRP04[11]
    38--------------------------MMCM1:CLKBURST_ENABLE
    MMCM1:DRP04[12]    		MMCM1:CLKBURST_REPEAT
    MMCM1:DRP04[13]
    39--------------------------MMCM1:DRP04[14]
    MMCM1:TMUX_MUX_SEL[0]    		MMCM1:DRP04[15]
    MMCM1:TMUX_MUX_SEL[1]
    40--------------------------MMCM1:DRP05[0]
    MMCM1:MUX.CASC_OUT[0]    		MMCM1:DRP05[1]
    MMCM1:MUX.CASC_OUT[1]
    41--------------------------MMCM1:DRP05[2]
    MMCM1:MUX.CASC_OUT[2]    		MMCM1:DIRECT_PATH_CNTRL
    MMCM1:DRP05[3]
    42--------------------------MMCM1:DRP05[4]
    MMCM1:IN_DLY_MX_DVDD[0]    		MMCM1:DRP05[5]
    MMCM1:IN_DLY_MX_DVDD[1]
    43--------------------------MMCM1:DRP05[6]
    MMCM1:IN_DLY_MX_DVDD[2]    		MMCM1:DRP05[7]
    MMCM1:IN_DLY_MX_DVDD[3]
    44--------------------------MMCM1:DRP05[8]
    MMCM1:IN_DLY_MX_DVDD[4]    		MMCM1:DRP05[9]
    MMCM1:IN_DLY_MX_DVDD[5]
    45--------------------------MMCM1:DRP05[10]
    MMCM1:IN_DLY_SET[0]    		MMCM1:DRP05[11]
    MMCM1:IN_DLY_SET[1]
    46--------------------------MMCM1:DRP05[12]
    MMCM1:IN_DLY_SET[2]    		MMCM1:DRP05[13]
    MMCM1:IN_DLY_SET[3]
    47--------------------------MMCM1:DRP05[14]
    MMCM1:IN_DLY_SET[4]    		MMCM1:DRP05[15]
    MMCM1:IN_DLY_EN
    48--------------------------MMCM1:CLKOUT5_LT[0]
    MMCM1:DRP06[0]    		MMCM1:CLKOUT5_LT[1]
    MMCM1:DRP06[1]
    49--------------------------MMCM1:CLKOUT5_LT[2]
    MMCM1:DRP06[2]    		MMCM1:CLKOUT5_LT[3]
    MMCM1:DRP06[3]
    50--------------------------MMCM1:CLKOUT5_LT[4]
    MMCM1:DRP06[4]    		MMCM1:CLKOUT5_LT[5]
    MMCM1:DRP06[5]
    51--------------------------MMCM1:CLKOUT5_HT[0]
    MMCM1:DRP06[6]    		MMCM1:CLKOUT5_HT[1]
    MMCM1:DRP06[7]
    52--------------------------MMCM1:CLKOUT5_HT[2]
    MMCM1:DRP06[8]    		MMCM1:CLKOUT5_HT[3]
    MMCM1:DRP06[9]
    53--------------------------MMCM1:CLKOUT5_HT[4]
    MMCM1:DRP06[10]    		MMCM1:CLKOUT5_HT[5]
    MMCM1:DRP06[11]
    54--------------------------MMCM1:CLKOUT5_EN
    MMCM1:DRP06[12]    		MMCM1:CLKOUT5_PM[0]
    MMCM1:DRP06[13]
    55--------------------------MMCM1:CLKOUT5_PM[1]
    MMCM1:DRP06[14]    		MMCM1:CLKOUT5_PM[2]
    MMCM1:DRP06[15]
    56--------------------------MMCM1:CLKOUT5_DT[0]
    MMCM1:DRP07[0]    		MMCM1:CLKOUT5_DT[1]
    MMCM1:DRP07[1]
    57--------------------------MMCM1:CLKOUT5_DT[2]
    MMCM1:DRP07[2]    		MMCM1:CLKOUT5_DT[3]
    MMCM1:DRP07[3]
    58--------------------------MMCM1:CLKOUT5_DT[4]
    MMCM1:DRP07[4]    		MMCM1:CLKOUT5_DT[5]
    MMCM1:DRP07[5]
    59--------------------------MMCM1:CLKOUT5_NOCOUNT
    MMCM1:DRP07[6]    		MMCM1:CLKOUT5_EDGE
    MMCM1:DRP07[7]
    60--------------------------MMCM1:CLKOUT5_MX[0]
    MMCM1:CLKOUT5_USE_FINE_PS
    MMCM1:DRP07[8]    		MMCM1:CLKOUT5_MX[1]
    MMCM1:DRP07[9]
    61--------------------------MMCM1:CLKOUT5_FRAC_WF
    MMCM1:DRP07[10]    		MMCM1:DRP07[11]
    62--------------------------MMCM1:DRP07[12]MMCM1:DRP07[13]
    63--------------------------MMCM1:DRP07[14]MMCM1:DRP07[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 23
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:CLKOUT0_LT[0]
    MMCM1:DRP08[0]    		MMCM1:CLKOUT0_LT[1]
    MMCM1:DRP08[1]
    1--------------------------MMCM1:CLKOUT0_LT[2]
    MMCM1:DRP08[2]    		MMCM1:CLKOUT0_LT[3]
    MMCM1:DRP08[3]
    2--------------------------MMCM1:CLKOUT0_LT[4]
    MMCM1:DRP08[4]    		MMCM1:CLKOUT0_LT[5]
    MMCM1:DRP08[5]
    3--------------------------MMCM1:CLKOUT0_HT[0]
    MMCM1:DRP08[6]    		MMCM1:CLKOUT0_HT[1]
    MMCM1:DRP08[7]
    4--------------------------MMCM1:CLKOUT0_HT[2]
    MMCM1:DRP08[8]    		MMCM1:CLKOUT0_HT[3]
    MMCM1:DRP08[9]
    5--------------------------MMCM1:CLKOUT0_HT[4]
    MMCM1:DRP08[10]    		MMCM1:CLKOUT0_HT[5]
    MMCM1:DRP08[11]
    6--------------------------MMCM1:CLKOUT0_EN
    MMCM1:DRP08[12]    		MMCM1:CLKOUT0_PM[0]
    MMCM1:DRP08[13]
    7--------------------------MMCM1:CLKOUT0_PM[1]
    MMCM1:DRP08[14]    		MMCM1:CLKOUT0_PM[2]
    MMCM1:DRP08[15]
    8--------------------------MMCM1:CLKOUT0_DT[0]
    MMCM1:DRP09[0]    		MMCM1:CLKOUT0_DT[1]
    MMCM1:DRP09[1]
    9--------------------------MMCM1:CLKOUT0_DT[2]
    MMCM1:DRP09[2]    		MMCM1:CLKOUT0_DT[3]
    MMCM1:DRP09[3]
    10--------------------------MMCM1:CLKOUT0_DT[4]
    MMCM1:DRP09[4]    		MMCM1:CLKOUT0_DT[5]
    MMCM1:DRP09[5]
    11--------------------------MMCM1:CLKOUT0_NOCOUNT
    MMCM1:DRP09[6]    		MMCM1:CLKOUT0_EDGE
    MMCM1:DRP09[7]
    12--------------------------MMCM1:CLKOUT0_MX[0]
    MMCM1:CLKOUT0_USE_FINE_PS
    MMCM1:DRP09[8]    		MMCM1:CLKOUT0_MX[1]
    MMCM1:DRP09[9]
    13--------------------------MMCM1:CLKOUT0_FRAC_WF
    MMCM1:DRP09[10]    		MMCM1:CLKOUT0_FRAC_EN
    MMCM1:DRP09[11]
    14--------------------------MMCM1:CLKOUT0_FRAC[0]
    MMCM1:DRP09[12]    		MMCM1:CLKOUT0_FRAC[1]
    MMCM1:DRP09[13]
    15--------------------------MMCM1:CLKOUT0_FRAC[2]
    MMCM1:DRP09[14]    		MMCM1:DRP09[15]
    16--------------------------MMCM1:CLKOUT1_LT[0]
    MMCM1:DRP0A[0]    		MMCM1:CLKOUT1_LT[1]
    MMCM1:DRP0A[1]
    17--------------------------MMCM1:CLKOUT1_LT[2]
    MMCM1:DRP0A[2]    		MMCM1:CLKOUT1_LT[3]
    MMCM1:DRP0A[3]
    18--------------------------MMCM1:CLKOUT1_LT[4]
    MMCM1:DRP0A[4]    		MMCM1:CLKOUT1_LT[5]
    MMCM1:DRP0A[5]
    19--------------------------MMCM1:CLKOUT1_HT[0]
    MMCM1:DRP0A[6]    		MMCM1:CLKOUT1_HT[1]
    MMCM1:DRP0A[7]
    20--------------------------MMCM1:CLKOUT1_HT[2]
    MMCM1:DRP0A[8]    		MMCM1:CLKOUT1_HT[3]
    MMCM1:DRP0A[9]
    21--------------------------MMCM1:CLKOUT1_HT[4]
    MMCM1:DRP0A[10]    		MMCM1:CLKOUT1_HT[5]
    MMCM1:DRP0A[11]
    22--------------------------MMCM1:CLKOUT1_EN
    MMCM1:DRP0A[12]    		MMCM1:CLKOUT1_PM[0]
    MMCM1:DRP0A[13]
    23--------------------------MMCM1:CLKOUT1_PM[1]
    MMCM1:DRP0A[14]    		MMCM1:CLKOUT1_PM[2]
    MMCM1:DRP0A[15]
    24--------------------------MMCM1:CLKOUT1_DT[0]
    MMCM1:DRP0B[0]    		MMCM1:CLKOUT1_DT[1]
    MMCM1:DRP0B[1]
    25--------------------------MMCM1:CLKOUT1_DT[2]
    MMCM1:DRP0B[2]    		MMCM1:CLKOUT1_DT[3]
    MMCM1:DRP0B[3]
    26--------------------------MMCM1:CLKOUT1_DT[4]
    MMCM1:DRP0B[4]    		MMCM1:CLKOUT1_DT[5]
    MMCM1:DRP0B[5]
    27--------------------------MMCM1:CLKOUT1_NOCOUNT
    MMCM1:DRP0B[6]    		MMCM1:CLKOUT1_EDGE
    MMCM1:DRP0B[7]
    28--------------------------MMCM1:CLKOUT1_MX[0]
    MMCM1:CLKOUT1_USE_FINE_PS
    MMCM1:DRP0B[8]    		MMCM1:CLKOUT1_MX[1]
    MMCM1:DRP0B[9]
    29--------------------------MMCM1:DRP0B[10]MMCM1:DRP0B[11]
    30--------------------------MMCM1:DRP0B[12]MMCM1:DRP0B[13]
    31--------------------------MMCM1:DRP0B[14]MMCM1:DRP0B[15]
    32--------------------------MMCM1:CLKOUT2_LT[0]
    MMCM1:DRP0C[0]    		MMCM1:CLKOUT2_LT[1]
    MMCM1:DRP0C[1]
    33--------------------------MMCM1:CLKOUT2_LT[2]
    MMCM1:DRP0C[2]    		MMCM1:CLKOUT2_LT[3]
    MMCM1:DRP0C[3]
    34--------------------------MMCM1:CLKOUT2_LT[4]
    MMCM1:DRP0C[4]    		MMCM1:CLKOUT2_LT[5]
    MMCM1:DRP0C[5]
    35--------------------------MMCM1:CLKOUT2_HT[0]
    MMCM1:DRP0C[6]    		MMCM1:CLKOUT2_HT[1]
    MMCM1:DRP0C[7]
    36--------------------------MMCM1:CLKOUT2_HT[2]
    MMCM1:DRP0C[8]    		MMCM1:CLKOUT2_HT[3]
    MMCM1:DRP0C[9]
    37--------------------------MMCM1:CLKOUT2_HT[4]
    MMCM1:DRP0C[10]    		MMCM1:CLKOUT2_HT[5]
    MMCM1:DRP0C[11]
    38--------------------------MMCM1:CLKOUT2_EN
    MMCM1:DRP0C[12]    		MMCM1:CLKOUT2_PM[0]
    MMCM1:DRP0C[13]
    39--------------------------MMCM1:CLKOUT2_PM[1]
    MMCM1:DRP0C[14]    		MMCM1:CLKOUT2_PM[2]
    MMCM1:DRP0C[15]
    40--------------------------MMCM1:CLKOUT2_DT[0]
    MMCM1:DRP0D[0]    		MMCM1:CLKOUT2_DT[1]
    MMCM1:DRP0D[1]
    41--------------------------MMCM1:CLKOUT2_DT[2]
    MMCM1:DRP0D[2]    		MMCM1:CLKOUT2_DT[3]
    MMCM1:DRP0D[3]
    42--------------------------MMCM1:CLKOUT2_DT[4]
    MMCM1:DRP0D[4]    		MMCM1:CLKOUT2_DT[5]
    MMCM1:DRP0D[5]
    43--------------------------MMCM1:CLKOUT2_NOCOUNT
    MMCM1:DRP0D[6]    		MMCM1:CLKOUT2_EDGE
    MMCM1:DRP0D[7]
    44--------------------------MMCM1:CLKOUT2_MX[0]
    MMCM1:CLKOUT2_USE_FINE_PS
    MMCM1:DRP0D[8]    		MMCM1:CLKOUT2_MX[1]
    MMCM1:DRP0D[9]
    45--------------------------MMCM1:DRP0D[10]MMCM1:DRP0D[11]
    46--------------------------MMCM1:DRP0D[12]MMCM1:DRP0D[13]
    47--------------------------MMCM1:DRP0D[14]MMCM1:DRP0D[15]
    48--------------------------MMCM1:CLKOUT3_LT[0]
    MMCM1:DRP0E[0]    		MMCM1:CLKOUT3_LT[1]
    MMCM1:DRP0E[1]
    49--------------------------MMCM1:CLKOUT3_LT[2]
    MMCM1:DRP0E[2]    		MMCM1:CLKOUT3_LT[3]
    MMCM1:DRP0E[3]
    50--------------------------MMCM1:CLKOUT3_LT[4]
    MMCM1:DRP0E[4]    		MMCM1:CLKOUT3_LT[5]
    MMCM1:DRP0E[5]
    51--------------------------MMCM1:CLKOUT3_HT[0]
    MMCM1:DRP0E[6]    		MMCM1:CLKOUT3_HT[1]
    MMCM1:DRP0E[7]
    52--------------------------MMCM1:CLKOUT3_HT[2]
    MMCM1:DRP0E[8]    		MMCM1:CLKOUT3_HT[3]
    MMCM1:DRP0E[9]
    53--------------------------MMCM1:CLKOUT3_HT[4]
    MMCM1:DRP0E[10]    		MMCM1:CLKOUT3_HT[5]
    MMCM1:DRP0E[11]
    54--------------------------MMCM1:CLKOUT3_EN
    MMCM1:DRP0E[12]    		MMCM1:CLKOUT3_PM[0]
    MMCM1:DRP0E[13]
    55--------------------------MMCM1:CLKOUT3_PM[1]
    MMCM1:DRP0E[14]    		MMCM1:CLKOUT3_PM[2]
    MMCM1:DRP0E[15]
    56--------------------------MMCM1:CLKOUT3_DT[0]
    MMCM1:DRP0F[0]    		MMCM1:CLKOUT3_DT[1]
    MMCM1:DRP0F[1]
    57--------------------------MMCM1:CLKOUT3_DT[2]
    MMCM1:DRP0F[2]    		MMCM1:CLKOUT3_DT[3]
    MMCM1:DRP0F[3]
    58--------------------------MMCM1:CLKOUT3_DT[4]
    MMCM1:DRP0F[4]    		MMCM1:CLKOUT3_DT[5]
    MMCM1:DRP0F[5]
    59--------------------------MMCM1:CLKOUT3_NOCOUNT
    MMCM1:DRP0F[6]    		MMCM1:CLKOUT3_EDGE
    MMCM1:DRP0F[7]
    60--------------------------MMCM1:CLKOUT3_MX[0]
    MMCM1:CLKOUT3_USE_FINE_PS
    MMCM1:DRP0F[8]    		MMCM1:CLKOUT3_MX[1]
    MMCM1:DRP0F[9]
    61--------------------------MMCM1:DRP0F[10]MMCM1:DRP0F[11]
    62--------------------------MMCM1:DRP0F[12]MMCM1:DRP0F[13]
    63--------------------------MMCM1:DRP0F[14]MMCM1:DRP0F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 24
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:CLKOUT4_LT[0]
    MMCM1:DRP10[0]    		MMCM1:CLKOUT4_LT[1]
    MMCM1:DRP10[1]
    1--------------------------MMCM1:CLKOUT4_LT[2]
    MMCM1:DRP10[2]    		MMCM1:CLKOUT4_LT[3]
    MMCM1:DRP10[3]
    2--------------------------MMCM1:CLKOUT4_LT[4]
    MMCM1:DRP10[4]    		MMCM1:CLKOUT4_LT[5]
    MMCM1:DRP10[5]
    3--------------------------MMCM1:CLKOUT4_HT[0]
    MMCM1:DRP10[6]    		MMCM1:CLKOUT4_HT[1]
    MMCM1:DRP10[7]
    4--------------------------MMCM1:CLKOUT4_HT[2]
    MMCM1:DRP10[8]    		MMCM1:CLKOUT4_HT[3]
    MMCM1:DRP10[9]
    5--------------------------MMCM1:CLKOUT4_HT[4]
    MMCM1:DRP10[10]    		MMCM1:CLKOUT4_HT[5]
    MMCM1:DRP10[11]
    6--------------------------MMCM1:CLKOUT4_EN
    MMCM1:DRP10[12]    		MMCM1:CLKOUT4_PM[0]
    MMCM1:DRP10[13]
    7--------------------------MMCM1:CLKOUT4_PM[1]
    MMCM1:DRP10[14]    		MMCM1:CLKOUT4_PM[2]
    MMCM1:DRP10[15]
    8--------------------------MMCM1:CLKOUT4_DT[0]
    MMCM1:DRP11[0]    		MMCM1:CLKOUT4_DT[1]
    MMCM1:DRP11[1]
    9--------------------------MMCM1:CLKOUT4_DT[2]
    MMCM1:DRP11[2]    		MMCM1:CLKOUT4_DT[3]
    MMCM1:DRP11[3]
    10--------------------------MMCM1:CLKOUT4_DT[4]
    MMCM1:DRP11[4]    		MMCM1:CLKOUT4_DT[5]
    MMCM1:DRP11[5]
    11--------------------------MMCM1:CLKOUT4_NOCOUNT
    MMCM1:DRP11[6]    		MMCM1:CLKOUT4_EDGE
    MMCM1:DRP11[7]
    12--------------------------MMCM1:CLKOUT4_MX[0]
    MMCM1:CLKOUT4_USE_FINE_PS
    MMCM1:DRP11[8]    		MMCM1:CLKOUT4_CASCADE
    MMCM1:CLKOUT4_MX[1]
    MMCM1:DRP11[9]
    13--------------------------MMCM1:DRP11[10]MMCM1:DRP11[11]
    14--------------------------MMCM1:DRP11[12]MMCM1:DRP11[13]
    15--------------------------MMCM1:DRP11[14]MMCM1:DRP11[15]
    16--------------------------MMCM1:CLKOUT6_LT[0]
    MMCM1:DRP12[0]    		MMCM1:CLKOUT6_LT[1]
    MMCM1:DRP12[1]
    17--------------------------MMCM1:CLKOUT6_LT[2]
    MMCM1:DRP12[2]    		MMCM1:CLKOUT6_LT[3]
    MMCM1:DRP12[3]
    18--------------------------MMCM1:CLKOUT6_LT[4]
    MMCM1:DRP12[4]    		MMCM1:CLKOUT6_LT[5]
    MMCM1:DRP12[5]
    19--------------------------MMCM1:CLKOUT6_HT[0]
    MMCM1:DRP12[6]    		MMCM1:CLKOUT6_HT[1]
    MMCM1:DRP12[7]
    20--------------------------MMCM1:CLKOUT6_HT[2]
    MMCM1:DRP12[8]    		MMCM1:CLKOUT6_HT[3]
    MMCM1:DRP12[9]
    21--------------------------MMCM1:CLKOUT6_HT[4]
    MMCM1:DRP12[10]    		MMCM1:CLKOUT6_HT[5]
    MMCM1:DRP12[11]
    22--------------------------MMCM1:CLKOUT6_EN
    MMCM1:DRP12[12]    		MMCM1:CLKOUT6_PM[0]
    MMCM1:DRP12[13]
    23--------------------------MMCM1:CLKOUT6_PM[1]
    MMCM1:DRP12[14]    		MMCM1:CLKOUT6_PM[2]
    MMCM1:DRP12[15]
    24--------------------------MMCM1:CLKOUT6_DT[0]
    MMCM1:DRP13[0]    		MMCM1:CLKOUT6_DT[1]
    MMCM1:DRP13[1]
    25--------------------------MMCM1:CLKOUT6_DT[2]
    MMCM1:DRP13[2]    		MMCM1:CLKOUT6_DT[3]
    MMCM1:DRP13[3]
    26--------------------------MMCM1:CLKOUT6_DT[4]
    MMCM1:DRP13[4]    		MMCM1:CLKOUT6_DT[5]
    MMCM1:DRP13[5]
    27--------------------------MMCM1:CLKOUT6_NOCOUNT
    MMCM1:DRP13[6]    		MMCM1:CLKOUT6_EDGE
    MMCM1:DRP13[7]
    28--------------------------MMCM1:CLKOUT6_MX[0]
    MMCM1:CLKOUT6_USE_FINE_PS
    MMCM1:DRP13[8]    		MMCM1:CLKOUT6_MX[1]
    MMCM1:DRP13[9]
    29--------------------------MMCM1:CLKOUT6_FRAC_WF
    MMCM1:DRP13[10]    		MMCM1:DRP13[11]
    30--------------------------MMCM1:DRP13[12]MMCM1:DRP13[13]
    31--------------------------MMCM1:DRP13[14]MMCM1:DRP13[15]
    32--------------------------MMCM1:CLKFBOUT_LT[0]
    MMCM1:DRP14[0]    		MMCM1:CLKFBOUT_LT[1]
    MMCM1:DRP14[1]
    33--------------------------MMCM1:CLKFBOUT_LT[2]
    MMCM1:DRP14[2]    		MMCM1:CLKFBOUT_LT[3]
    MMCM1:DRP14[3]
    34--------------------------MMCM1:CLKFBOUT_LT[4]
    MMCM1:DRP14[4]    		MMCM1:CLKFBOUT_LT[5]
    MMCM1:DRP14[5]
    35--------------------------MMCM1:CLKFBOUT_HT[0]
    MMCM1:DRP14[6]    		MMCM1:CLKFBOUT_HT[1]
    MMCM1:DRP14[7]
    36--------------------------MMCM1:CLKFBOUT_HT[2]
    MMCM1:DRP14[8]    		MMCM1:CLKFBOUT_HT[3]
    MMCM1:DRP14[9]
    37--------------------------MMCM1:CLKFBOUT_HT[4]
    MMCM1:DRP14[10]    		MMCM1:CLKFBOUT_HT[5]
    MMCM1:DRP14[11]
    38--------------------------MMCM1:CLKFBOUT_EN
    MMCM1:DRP14[12]    		MMCM1:CLKFBOUT_PM[0]
    MMCM1:DRP14[13]
    39--------------------------MMCM1:CLKFBOUT_PM[1]
    MMCM1:DRP14[14]    		MMCM1:CLKFBOUT_PM[2]
    MMCM1:DRP14[15]
    40--------------------------MMCM1:CLKFBOUT_DT[0]
    MMCM1:DRP15[0]    		MMCM1:CLKFBOUT_DT[1]
    MMCM1:DRP15[1]
    41--------------------------MMCM1:CLKFBOUT_DT[2]
    MMCM1:DRP15[2]    		MMCM1:CLKFBOUT_DT[3]
    MMCM1:DRP15[3]
    42--------------------------MMCM1:CLKFBOUT_DT[4]
    MMCM1:DRP15[4]    		MMCM1:CLKFBOUT_DT[5]
    MMCM1:DRP15[5]
    43--------------------------MMCM1:CLKFBOUT_NOCOUNT
    MMCM1:DRP15[6]    		MMCM1:CLKFBOUT_EDGE
    MMCM1:DRP15[7]
    44--------------------------MMCM1:CLKFBOUT_MX[0]
    MMCM1:CLKFBOUT_USE_FINE_PS
    MMCM1:DRP15[8]    		MMCM1:CLKFBOUT_MX[1]
    MMCM1:DRP15[9]
    45--------------------------MMCM1:CLKFBOUT_FRAC_WF
    MMCM1:DRP15[10]    		MMCM1:CLKFBOUT_FRAC_EN
    MMCM1:DRP15[11]
    46--------------------------MMCM1:CLKFBOUT_FRAC[0]
    MMCM1:DRP15[12]    		MMCM1:CLKFBOUT_FRAC[1]
    MMCM1:DRP15[13]
    47--------------------------MMCM1:CLKFBOUT_FRAC[2]
    MMCM1:DRP15[14]    		MMCM1:DRP15[15]
    48--------------------------MMCM1:DIVCLK_LT[0]
    MMCM1:DRP16[0]    		MMCM1:DIVCLK_LT[1]
    MMCM1:DRP16[1]
    49--------------------------MMCM1:DIVCLK_LT[2]
    MMCM1:DRP16[2]    		MMCM1:DIVCLK_LT[3]
    MMCM1:DRP16[3]
    50--------------------------MMCM1:DIVCLK_LT[4]
    MMCM1:DRP16[4]    		MMCM1:DIVCLK_LT[5]
    MMCM1:DRP16[5]
    51--------------------------MMCM1:DIVCLK_HT[0]
    MMCM1:DRP16[6]    		MMCM1:DIVCLK_HT[1]
    MMCM1:DRP16[7]
    52--------------------------MMCM1:DIVCLK_HT[2]
    MMCM1:DRP16[8]    		MMCM1:DIVCLK_HT[3]
    MMCM1:DRP16[9]
    53--------------------------MMCM1:DIVCLK_HT[4]
    MMCM1:DRP16[10]    		MMCM1:DIVCLK_HT[5]
    MMCM1:DRP16[11]
    54--------------------------MMCM1:DIVCLK_NOCOUNT
    MMCM1:DRP16[12]    		MMCM1:DIVCLK_EDGE
    MMCM1:DRP16[13]
    55--------------------------MMCM1:DRP16[14]MMCM1:DRP16[15]
    56--------------------------MMCM1:CLKFBIN_LT[0]
    MMCM1:DRP17[0]    		MMCM1:CLKFBIN_LT[1]
    MMCM1:DRP17[1]
    57--------------------------MMCM1:CLKFBIN_LT[2]
    MMCM1:DRP17[2]    		MMCM1:CLKFBIN_LT[3]
    MMCM1:DRP17[3]
    58--------------------------MMCM1:CLKFBIN_LT[4]
    MMCM1:DRP17[4]    		MMCM1:CLKFBIN_LT[5]
    MMCM1:DRP17[5]
    59--------------------------MMCM1:CLKFBIN_HT[0]
    MMCM1:DRP17[6]    		MMCM1:CLKFBIN_HT[1]
    MMCM1:DRP17[7]
    60--------------------------MMCM1:CLKFBIN_HT[2]
    MMCM1:DRP17[8]    		MMCM1:CLKFBIN_HT[3]
    MMCM1:DRP17[9]
    61--------------------------MMCM1:CLKFBIN_HT[4]
    MMCM1:DRP17[10]    		MMCM1:CLKFBIN_HT[5]
    MMCM1:DRP17[11]
    62--------------------------MMCM1:CLKFBIN_NOCOUNT
    MMCM1:DRP17[12]    		MMCM1:CLKFBIN_EDGE
    MMCM1:DRP17[13]
    63--------------------------MMCM1:DRP17[14]MMCM1:DRP17[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 25
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP18[0]
    MMCM1:LOCK_CNT[0]    		MMCM1:DRP18[1]
    MMCM1:LOCK_CNT[1]
    1--------------------------MMCM1:DRP18[2]
    MMCM1:LOCK_CNT[2]    		MMCM1:DRP18[3]
    MMCM1:LOCK_CNT[3]
    2--------------------------MMCM1:DRP18[4]
    MMCM1:LOCK_CNT[4]    		MMCM1:DRP18[5]
    MMCM1:LOCK_CNT[5]
    3--------------------------MMCM1:DRP18[6]
    MMCM1:LOCK_CNT[6]    		MMCM1:DRP18[7]
    MMCM1:LOCK_CNT[7]
    4--------------------------MMCM1:DRP18[8]
    MMCM1:LOCK_CNT[8]    		MMCM1:DRP18[9]
    MMCM1:LOCK_CNT[9]
    5--------------------------MMCM1:DRP18[10]MMCM1:DRP18[11]
    6--------------------------MMCM1:DRP18[12]MMCM1:DRP18[13]
    7--------------------------MMCM1:DRP18[14]MMCM1:DRP18[15]
    8--------------------------MMCM1:DRP19[0]
    MMCM1:UNLOCK_CNT[0]    		MMCM1:DRP19[1]
    MMCM1:UNLOCK_CNT[1]
    9--------------------------MMCM1:DRP19[2]
    MMCM1:UNLOCK_CNT[2]    		MMCM1:DRP19[3]
    MMCM1:UNLOCK_CNT[3]
    10--------------------------MMCM1:DRP19[4]
    MMCM1:UNLOCK_CNT[4]    		MMCM1:DRP19[5]
    MMCM1:UNLOCK_CNT[5]
    11--------------------------MMCM1:DRP19[6]
    MMCM1:UNLOCK_CNT[6]    		MMCM1:DRP19[7]
    MMCM1:UNLOCK_CNT[7]
    12--------------------------MMCM1:DRP19[8]
    MMCM1:UNLOCK_CNT[8]    		MMCM1:DRP19[9]
    MMCM1:UNLOCK_CNT[9]
    13--------------------------MMCM1:DRP19[10]
    MMCM1:LOCK_FB_DLY[0]    		MMCM1:DRP19[11]
    MMCM1:LOCK_FB_DLY[1]
    14--------------------------MMCM1:DRP19[12]
    MMCM1:LOCK_FB_DLY[2]    		MMCM1:DRP19[13]
    MMCM1:LOCK_FB_DLY[3]
    15--------------------------MMCM1:DRP19[14]
    MMCM1:LOCK_FB_DLY[4]    		MMCM1:DRP19[15]
    16--------------------------MMCM1:DRP1A[0]
    MMCM1:LOCK_SAT_HIGH[0]    		MMCM1:DRP1A[1]
    MMCM1:LOCK_SAT_HIGH[1]
    17--------------------------MMCM1:DRP1A[2]
    MMCM1:LOCK_SAT_HIGH[2]    		MMCM1:DRP1A[3]
    MMCM1:LOCK_SAT_HIGH[3]
    18--------------------------MMCM1:DRP1A[4]
    MMCM1:LOCK_SAT_HIGH[4]    		MMCM1:DRP1A[5]
    MMCM1:LOCK_SAT_HIGH[5]
    19--------------------------MMCM1:DRP1A[6]
    MMCM1:LOCK_SAT_HIGH[6]    		MMCM1:DRP1A[7]
    MMCM1:LOCK_SAT_HIGH[7]
    20--------------------------MMCM1:DRP1A[8]
    MMCM1:LOCK_SAT_HIGH[8]    		MMCM1:DRP1A[9]
    MMCM1:LOCK_SAT_HIGH[9]
    21--------------------------MMCM1:DRP1A[10]
    MMCM1:LOCK_REF_DLY[0]    		MMCM1:DRP1A[11]
    MMCM1:LOCK_REF_DLY[1]
    22--------------------------MMCM1:DRP1A[12]
    MMCM1:LOCK_REF_DLY[2]    		MMCM1:DRP1A[13]
    MMCM1:LOCK_REF_DLY[3]
    23--------------------------MMCM1:DRP1A[14]
    MMCM1:LOCK_REF_DLY[4]    		MMCM1:DRP1A[15]
    24--------------------------MMCM1:DRP1B[0]
    MMCM1:HVLF_CNT_TEST[0]    		MMCM1:DRP1B[1]
    MMCM1:HVLF_CNT_TEST[1]
    25--------------------------MMCM1:DRP1B[2]
    MMCM1:HVLF_CNT_TEST[2]    		MMCM1:DRP1B[3]
    MMCM1:HVLF_CNT_TEST[3]
    26--------------------------MMCM1:DRP1B[4]
    MMCM1:HVLF_CNT_TEST[4]    		MMCM1:DRP1B[5]
    MMCM1:HVLF_CNT_TEST[5]
    27--------------------------MMCM1:DRP1B[6]
    MMCM1:HVLF_STEP    		MMCM1:DRP1B[7]
    MMCM1:HVLF_CNT_TEST_EN
    28--------------------------MMCM1:DRP1B[8]MMCM1:DRP1B[9]
    29--------------------------MMCM1:DRP1B[10]MMCM1:DRP1B[11]
    30--------------------------MMCM1:DRP1B[12]MMCM1:DRP1B[13]
    31--------------------------MMCM1:DRP1B[14]MMCM1:DRP1B[15]
    32--------------------------MMCM1:DRP1C[0]MMCM1:DRP1C[1]
    33--------------------------MMCM1:DRP1C[2]MMCM1:DRP1C[3]
    34--------------------------MMCM1:DRP1C[4]MMCM1:DRP1C[5]
    35--------------------------MMCM1:DRP1C[6]MMCM1:DRP1C[7]
    36--------------------------MMCM1:DRP1C[8]MMCM1:DRP1C[9]
    37--------------------------MMCM1:DRP1C[10]MMCM1:DRP1C[11]
    38--------------------------MMCM1:DRP1C[12]MMCM1:DRP1C[13]
    39--------------------------MMCM1:DRP1C[14]MMCM1:DRP1C[15]
    40--------------------------MMCM1:DRP1D[0]MMCM1:DRP1D[1]
    41--------------------------MMCM1:DRP1D[2]MMCM1:DRP1D[3]
    42--------------------------MMCM1:DRP1D[4]
    MMCM1:PFD[0]    		MMCM1:DRP1D[5]
    MMCM1:PFD[1]
    43--------------------------MMCM1:DRP1D[6]
    MMCM1:PFD[2]    		MMCM1:DRP1D[7]
    MMCM1:PFD[3]
    44--------------------------MMCM1:DRP1D[8]
    MMCM1:PFD[4]    		MMCM1:DRP1D[9]
    MMCM1:PFD[5]
    45--------------------------MMCM1:DRP1D[10]
    MMCM1:PFD[6]    		MMCM1:DRP1D[11]
    46--------------------------MMCM1:DRP1D[12]MMCM1:DRP1D[13]
    47--------------------------MMCM1:DRP1D[14]MMCM1:DRP1D[15]
    48--------------------------MMCM1:DRP1E[0]MMCM1:DRP1E[1]
    49--------------------------MMCM1:DRP1E[2]MMCM1:DRP1E[3]
    50--------------------------MMCM1:DRP1E[4]MMCM1:DRP1E[5]
    51--------------------------MMCM1:DRP1E[6]MMCM1:DRP1E[7]
    52--------------------------MMCM1:DRP1E[8]MMCM1:DRP1E[9]
    53--------------------------MMCM1:DRP1E[10]MMCM1:DRP1E[11]
    54--------------------------MMCM1:DRP1E[12]MMCM1:DRP1E[13]
    55--------------------------MMCM1:DRP1E[14]MMCM1:DRP1E[15]
    56--------------------------MMCM1:DRP1F[0]
    MMCM1:DVDD_VBG_SEL[0]    		MMCM1:DRP1F[1]
    MMCM1:DVDD_VBG_SEL[1]
    57--------------------------MMCM1:DRP1F[2]
    MMCM1:DVDD_VBG_SEL[2]    		MMCM1:DRP1F[3]
    MMCM1:DVDD_VBG_SEL[3]
    58--------------------------MMCM1:DRP1F[4]
    MMCM1:DVDD_VBG_PD[0]    		MMCM1:DRP1F[5]
    MMCM1:DVDD_VBG_PD[1]
    59--------------------------MMCM1:DRP1F[6]
    MMCM1:DVDD_VBG_PD[2]    		MMCM1:DRP1F[7]
    MMCM1:DVDD_COMP_SET[0]
    60--------------------------MMCM1:DRP1F[8]
    MMCM1:DVDD_COMP_SET[1]    		MMCM1:DRP1F[9]
    61--------------------------MMCM1:DRP1F[10]MMCM1:DRP1F[11]
    62--------------------------MMCM1:DRP1F[12]MMCM1:DRP1F[13]
    63--------------------------MMCM1:DRP1F[14]MMCM1:DRP1F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 26
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP20[0]MMCM1:DRP20[1]
    1--------------------------MMCM1:DRP20[2]MMCM1:DRP20[3]
    2--------------------------MMCM1:DRP20[4]MMCM1:DRP20[5]
    3--------------------------MMCM1:DRP20[6]MMCM1:DRP20[7]
    4--------------------------MMCM1:DRP20[8]MMCM1:DRP20[9]
    5--------------------------MMCM1:DRP20[10]MMCM1:DRP20[11]
    6--------------------------MMCM1:DRP20[12]MMCM1:DRP20[13]
    7--------------------------MMCM1:DRP20[14]MMCM1:DRP20[15]
    8--------------------------MMCM1:DRP21[0]MMCM1:DRP21[1]
    9--------------------------MMCM1:DRP21[2]MMCM1:DRP21[3]
    10--------------------------MMCM1:DRP21[4]MMCM1:DRP21[5]
    11--------------------------MMCM1:DRP21[6]MMCM1:DRP21[7]
    12--------------------------MMCM1:DRP21[8]MMCM1:DRP21[9]
    13--------------------------MMCM1:DRP21[10]MMCM1:DRP21[11]
    14--------------------------MMCM1:DRP21[12]MMCM1:DRP21[13]
    15--------------------------MMCM1:DRP21[14]MMCM1:DRP21[15]
    16--------------------------MMCM1:DRP22[0]
    MMCM1:EN_VCO_DIV6    		MMCM1:DRP22[1]
    MMCM1:EN_VCO_DIV1
    17--------------------------MMCM1:DRP22[2]MMCM1:DRP22[3]
    18--------------------------MMCM1:DRP22[4]MMCM1:DRP22[5]
    19--------------------------MMCM1:DRP22[6]MMCM1:DRP22[7]
    20--------------------------MMCM1:DRP22[8]MMCM1:DRP22[9]
    21--------------------------MMCM1:DRP22[10]MMCM1:DRP22[11]
    22--------------------------MMCM1:DRP22[12]MMCM1:DRP22[13]
    23--------------------------MMCM1:DRP22[14]MMCM1:DRP22[15]
    24--------------------------MMCM1:DRP23[0]MMCM1:DRP23[1]
    25--------------------------MMCM1:DRP23[2]MMCM1:DRP23[3]
    26--------------------------MMCM1:DRP23[4]MMCM1:DRP23[5]
    27--------------------------MMCM1:DRP23[6]MMCM1:DRP23[7]
    28--------------------------MMCM1:DRP23[8]MMCM1:DRP23[9]
    29--------------------------MMCM1:DRP23[10]MMCM1:DRP23[11]
    30--------------------------MMCM1:DRP23[12]MMCM1:DRP23[13]
    31--------------------------MMCM1:DRP23[14]MMCM1:DRP23[15]
    32--------------------------MMCM1:DRP24[0]MMCM1:DRP24[1]
    33--------------------------MMCM1:DRP24[2]MMCM1:DRP24[3]
    34--------------------------MMCM1:DRP24[4]MMCM1:DRP24[5]
    35--------------------------MMCM1:DRP24[6]MMCM1:DRP24[7]
    36--------------------------MMCM1:DRP24[8]MMCM1:DRP24[9]
    37--------------------------MMCM1:DRP24[10]MMCM1:DRP24[11]
    38--------------------------MMCM1:DRP24[12]MMCM1:DRP24[13]
    39--------------------------MMCM1:DRP24[14]MMCM1:DRP24[15]
    40--------------------------MMCM1:DRP25[0]MMCM1:DRP25[1]
    41--------------------------MMCM1:DRP25[2]MMCM1:DRP25[3]
    42--------------------------MMCM1:DRP25[4]MMCM1:DRP25[5]
    43--------------------------MMCM1:DRP25[6]MMCM1:DRP25[7]
    44--------------------------MMCM1:DRP25[8]MMCM1:DRP25[9]
    45--------------------------MMCM1:DRP25[10]MMCM1:DRP25[11]
    46--------------------------MMCM1:DRP25[12]MMCM1:DRP25[13]
    47--------------------------MMCM1:DRP25[14]MMCM1:DRP25[15]
    48--------------------------MMCM1:DRP26[0]MMCM1:DRP26[1]
    49--------------------------MMCM1:DRP26[2]MMCM1:ANALOG_MISC[0]
    MMCM1:DRP26[3]
    50--------------------------MMCM1:ANALOG_MISC[1]
    MMCM1:DRP26[4]    		MMCM1:DRP26[5]
    51--------------------------MMCM1:DRP26[6]MMCM1:ANALOG_MISC[2]
    MMCM1:DRP26[7]
    52--------------------------MMCM1:ANALOG_MISC[3]
    MMCM1:DRP26[8]    		MMCM1:DRP26[9]
    53--------------------------MMCM1:DRP26[10]MMCM1:DRP26[11]
    54--------------------------MMCM1:DRP26[12]MMCM1:DRP26[13]
    55--------------------------MMCM1:DRP26[14]MMCM1:DRP26[15]
    56--------------------------MMCM1:DRP27[0]MMCM1:DRP27[1]
    57--------------------------MMCM1:DRP27[2]MMCM1:DRP27[3]
    58--------------------------MMCM1:DRP27[4]MMCM1:DRP27[5]
    59--------------------------MMCM1:DRP27[6]MMCM1:DRP27[7]
    60--------------------------MMCM1:DRP27[8]MMCM1:DRP27[9]
    61--------------------------MMCM1:DRP27[10]MMCM1:DRP27[11]
    62--------------------------MMCM1:DRP27[12]MMCM1:DRP27[13]
    63--------------------------MMCM1:DRP27[14]MMCM1:DRP27[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 27
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP28[0]
    MMCM1:INTERP_EN[0]    		MMCM1:DRP28[1]
    1--------------------------MMCM1:DRP28[2]MMCM1:DRP28[3]
    MMCM1:INTERP_EN[1]
    2--------------------------MMCM1:DRP28[4]
    MMCM1:INTERP_EN[2]    		MMCM1:DRP28[5]
    3--------------------------MMCM1:DRP28[6]MMCM1:DRP28[7]
    MMCM1:INTERP_EN[3]
    4--------------------------MMCM1:DRP28[8]
    MMCM1:INTERP_EN[4]    		MMCM1:DRP28[9]
    5--------------------------MMCM1:DRP28[10]MMCM1:DRP28[11]
    MMCM1:INTERP_EN[5]
    6--------------------------MMCM1:DRP28[12]
    MMCM1:INTERP_EN[6]    		MMCM1:DRP28[13]
    7--------------------------MMCM1:DRP28[14]MMCM1:DRP28[15]
    MMCM1:INTERP_EN[7]
    8--------------------------MMCM1:DRP29[0]MMCM1:DRP29[1]
    9--------------------------MMCM1:DRP29[2]MMCM1:DRP29[3]
    10--------------------------MMCM1:DRP29[4]MMCM1:DRP29[5]
    11--------------------------MMCM1:DRP29[6]MMCM1:DRP29[7]
    12--------------------------MMCM1:DRP29[8]MMCM1:DRP29[9]
    13--------------------------MMCM1:DRP29[10]MMCM1:DRP29[11]
    14--------------------------MMCM1:DRP29[12]MMCM1:DRP29[13]
    15--------------------------MMCM1:DRP29[14]MMCM1:DRP29[15]
    16--------------------------MMCM1:DRP2A[0]MMCM1:DRP2A[1]
    17--------------------------MMCM1:DRP2A[2]MMCM1:DRP2A[3]
    18--------------------------MMCM1:DRP2A[4]MMCM1:DRP2A[5]
    19--------------------------MMCM1:DRP2A[6]MMCM1:DRP2A[7]
    20--------------------------MMCM1:DRP2A[8]MMCM1:DRP2A[9]
    21--------------------------MMCM1:DRP2A[10]MMCM1:DRP2A[11]
    22--------------------------MMCM1:DRP2A[12]MMCM1:DRP2A[13]
    23--------------------------MMCM1:DRP2A[14]MMCM1:DRP2A[15]
    24--------------------------MMCM1:DRP2B[0]MMCM1:DRP2B[1]
    25--------------------------MMCM1:DRP2B[2]MMCM1:DRP2B[3]
    26--------------------------MMCM1:DRP2B[4]MMCM1:DRP2B[5]
    27--------------------------MMCM1:DRP2B[6]MMCM1:DRP2B[7]
    28--------------------------MMCM1:DRP2B[8]MMCM1:DRP2B[9]
    29--------------------------MMCM1:DRP2B[10]MMCM1:DRP2B[11]
    30--------------------------MMCM1:DRP2B[12]MMCM1:DRP2B[13]
    31--------------------------MMCM1:DRP2B[14]MMCM1:DRP2B[15]
    32--------------------------MMCM1:DRP2C[0]MMCM1:DRP2C[1]
    33--------------------------MMCM1:DRP2C[2]MMCM1:DRP2C[3]
    34--------------------------MMCM1:DRP2C[4]MMCM1:DRP2C[5]
    35--------------------------MMCM1:DRP2C[6]MMCM1:DRP2C[7]
    36--------------------------MMCM1:DRP2C[8]MMCM1:DRP2C[9]
    37--------------------------MMCM1:DRP2C[10]MMCM1:DRP2C[11]
    38--------------------------MMCM1:DRP2C[12]MMCM1:DRP2C[13]
    39--------------------------MMCM1:DRP2C[14]MMCM1:DRP2C[15]
    40--------------------------MMCM1:DRP2D[0]MMCM1:DRP2D[1]
    41--------------------------MMCM1:DRP2D[2]MMCM1:DRP2D[3]
    42--------------------------MMCM1:DRP2D[4]MMCM1:DRP2D[5]
    43--------------------------MMCM1:DRP2D[6]MMCM1:DRP2D[7]
    44--------------------------MMCM1:DRP2D[8]MMCM1:DRP2D[9]
    45--------------------------MMCM1:DRP2D[10]MMCM1:DRP2D[11]
    46--------------------------MMCM1:DRP2D[12]MMCM1:DRP2D[13]
    47--------------------------MMCM1:DRP2D[14]MMCM1:DRP2D[15]
    48--------------------------MMCM1:DRP2E[0]MMCM1:DRP2E[1]
    49--------------------------MMCM1:DRP2E[2]MMCM1:DRP2E[3]
    50--------------------------MMCM1:DRP2E[4]MMCM1:DRP2E[5]
    51--------------------------MMCM1:DRP2E[6]MMCM1:DRP2E[7]
    52--------------------------MMCM1:DRP2E[8]MMCM1:DRP2E[9]
    53--------------------------MMCM1:DRP2E[10]MMCM1:DRP2E[11]
    54--------------------------MMCM1:DRP2E[12]MMCM1:DRP2E[13]
    55--------------------------MMCM1:DRP2E[14]MMCM1:DRP2E[15]
    56--------------------------MMCM1:DRP2F[0]MMCM1:DRP2F[1]
    57--------------------------MMCM1:DRP2F[2]MMCM1:DRP2F[3]
    58--------------------------MMCM1:DRP2F[4]MMCM1:DRP2F[5]
    59--------------------------MMCM1:DRP2F[6]MMCM1:DRP2F[7]
    60--------------------------MMCM1:DRP2F[8]MMCM1:DRP2F[9]
    61--------------------------MMCM1:DRP2F[10]MMCM1:DRP2F[11]
    62--------------------------MMCM1:DRP2F[12]MMCM1:DRP2F[13]
    63--------------------------MMCM1:DRP2F[14]MMCM1:DRP2F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 28
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP30[0]MMCM1:DRP30[1]
    1--------------------------MMCM1:DRP30[2]MMCM1:DRP30[3]
    2--------------------------MMCM1:DRP30[4]MMCM1:DRP30[5]
    3--------------------------MMCM1:DRP30[6]MMCM1:DRP30[7]
    4--------------------------MMCM1:DRP30[8]MMCM1:DRP30[9]
    5--------------------------MMCM1:DRP30[10]MMCM1:DRP30[11]
    6--------------------------MMCM1:DRP30[12]MMCM1:DRP30[13]
    7--------------------------MMCM1:DRP30[14]MMCM1:DRP30[15]
    8--------------------------MMCM1:DRP31[0]MMCM1:DRP31[1]
    9--------------------------MMCM1:DRP31[2]MMCM1:DRP31[3]
    10--------------------------MMCM1:DRP31[4]MMCM1:DRP31[5]
    11--------------------------MMCM1:DRP31[6]MMCM1:DRP31[7]
    12--------------------------MMCM1:DRP31[8]MMCM1:DRP31[9]
    13--------------------------MMCM1:DRP31[10]MMCM1:DRP31[11]
    14--------------------------MMCM1:DRP31[12]MMCM1:DRP31[13]
    15--------------------------MMCM1:DRP31[14]MMCM1:DRP31[15]
    16--------------------------MMCM1:DRP32[0]MMCM1:DRP32[1]
    17--------------------------MMCM1:DRP32[2]MMCM1:DRP32[3]
    18--------------------------MMCM1:DRP32[4]MMCM1:DRP32[5]
    19--------------------------MMCM1:DRP32[6]MMCM1:DRP32[7]
    20--------------------------MMCM1:DRP32[8]MMCM1:DRP32[9]
    21--------------------------MMCM1:DRP32[10]MMCM1:DRP32[11]
    22--------------------------MMCM1:DRP32[12]MMCM1:DRP32[13]
    23--------------------------MMCM1:DRP32[14]MMCM1:DRP32[15]
    24--------------------------MMCM1:DRP33[0]MMCM1:DRP33[1]
    25--------------------------MMCM1:DRP33[2]MMCM1:DRP33[3]
    26--------------------------MMCM1:DRP33[4]MMCM1:DRP33[5]
    27--------------------------MMCM1:DRP33[6]MMCM1:DRP33[7]
    28--------------------------MMCM1:DRP33[8]MMCM1:DRP33[9]
    29--------------------------MMCM1:DRP33[10]MMCM1:DRP33[11]
    30--------------------------MMCM1:DRP33[12]MMCM1:DRP33[13]
    31--------------------------MMCM1:DRP33[14]MMCM1:DRP33[15]
    32--------------------------MMCM1:DRP34[0]MMCM1:DRP34[1]
    33--------------------------MMCM1:DRP34[2]MMCM1:DRP34[3]
    34--------------------------MMCM1:DRP34[4]MMCM1:DRP34[5]
    35--------------------------MMCM1:DRP34[6]MMCM1:DRP34[7]
    36--------------------------MMCM1:DRP34[8]MMCM1:DRP34[9]
    37--------------------------MMCM1:DRP34[10]MMCM1:DRP34[11]
    38--------------------------MMCM1:DRP34[12]MMCM1:DRP34[13]
    39--------------------------MMCM1:DRP34[14]MMCM1:DRP34[15]
    40--------------------------MMCM1:DRP35[0]MMCM1:DRP35[1]
    41--------------------------MMCM1:DRP35[2]MMCM1:DRP35[3]
    42--------------------------MMCM1:DRP35[4]MMCM1:DRP35[5]
    43--------------------------MMCM1:DRP35[6]MMCM1:DRP35[7]
    44--------------------------MMCM1:DRP35[8]MMCM1:DRP35[9]
    45--------------------------MMCM1:DRP35[10]MMCM1:DRP35[11]
    46--------------------------MMCM1:DRP35[12]MMCM1:DRP35[13]
    47--------------------------MMCM1:DRP35[14]MMCM1:DRP35[15]
    48--------------------------MMCM1:DRP36[0]MMCM1:DRP36[1]
    49--------------------------MMCM1:DRP36[2]MMCM1:DRP36[3]
    50--------------------------MMCM1:DRP36[4]MMCM1:DRP36[5]
    51--------------------------MMCM1:DRP36[6]MMCM1:DRP36[7]
    52--------------------------MMCM1:DRP36[8]MMCM1:DRP36[9]
    53--------------------------MMCM1:DRP36[10]MMCM1:DRP36[11]
    54--------------------------MMCM1:DRP36[12]MMCM1:DRP36[13]
    55--------------------------MMCM1:DRP36[14]MMCM1:DRP36[15]
    56--------------------------MMCM1:DRP37[0]MMCM1:DRP37[1]
    57--------------------------MMCM1:DRP37[2]MMCM1:DRP37[3]
    58--------------------------MMCM1:DRP37[4]MMCM1:DRP37[5]
    59--------------------------MMCM1:DRP37[6]MMCM1:DRP37[7]
    60--------------------------MMCM1:DRP37[8]MMCM1:DRP37[9]
    61--------------------------MMCM1:DRP37[10]MMCM1:DRP37[11]
    62--------------------------MMCM1:DRP37[12]MMCM1:DRP37[13]
    63--------------------------MMCM1:DRP37[14]MMCM1:DRP37[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 29
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP38[0]MMCM1:DRP38[1]
    1--------------------------MMCM1:DRP38[2]MMCM1:DRP38[3]
    2--------------------------MMCM1:DRP38[4]MMCM1:DRP38[5]
    3--------------------------MMCM1:DRP38[6]MMCM1:DRP38[7]
    4--------------------------MMCM1:DRP38[8]MMCM1:DRP38[9]
    5--------------------------MMCM1:DRP38[10]MMCM1:DRP38[11]
    6--------------------------MMCM1:DRP38[12]MMCM1:DRP38[13]
    7--------------------------MMCM1:DRP38[14]MMCM1:DRP38[15]
    8--------------------------MMCM1:DRP39[0]MMCM1:DRP39[1]
    9--------------------------MMCM1:DRP39[2]MMCM1:DRP39[3]
    10--------------------------MMCM1:DRP39[4]MMCM1:DRP39[5]
    11--------------------------MMCM1:DRP39[6]MMCM1:DRP39[7]
    12--------------------------MMCM1:DRP39[8]MMCM1:DRP39[9]
    13--------------------------MMCM1:DRP39[10]MMCM1:DRP39[11]
    14--------------------------MMCM1:DRP39[12]MMCM1:DRP39[13]
    15--------------------------MMCM1:DRP39[14]MMCM1:DRP39[15]
    16--------------------------MMCM1:DRP3A[0]MMCM1:DRP3A[1]
    17--------------------------MMCM1:DRP3A[2]MMCM1:DRP3A[3]
    18--------------------------MMCM1:DRP3A[4]MMCM1:DRP3A[5]
    19--------------------------MMCM1:DRP3A[6]MMCM1:DRP3A[7]
    20--------------------------MMCM1:DRP3A[8]MMCM1:DRP3A[9]
    21--------------------------MMCM1:DRP3A[10]MMCM1:DRP3A[11]
    22--------------------------MMCM1:DRP3A[12]MMCM1:DRP3A[13]
    23--------------------------MMCM1:DRP3A[14]MMCM1:DRP3A[15]
    24--------------------------MMCM1:DRP3B[0]MMCM1:DRP3B[1]
    25--------------------------MMCM1:DRP3B[2]MMCM1:DRP3B[3]
    26--------------------------MMCM1:DRP3B[4]MMCM1:DRP3B[5]
    27--------------------------MMCM1:DRP3B[6]MMCM1:DRP3B[7]
    28--------------------------MMCM1:DRP3B[8]MMCM1:DRP3B[9]
    29--------------------------MMCM1:DRP3B[10]MMCM1:DRP3B[11]
    30--------------------------MMCM1:DRP3B[12]MMCM1:DRP3B[13]
    31--------------------------MMCM1:DRP3B[14]MMCM1:DRP3B[15]
    32--------------------------MMCM1:DRP3C[0]MMCM1:DRP3C[1]
    33--------------------------MMCM1:DRP3C[2]MMCM1:DRP3C[3]
    34--------------------------MMCM1:DRP3C[4]MMCM1:DRP3C[5]
    35--------------------------MMCM1:DRP3C[6]MMCM1:DRP3C[7]
    36--------------------------MMCM1:DRP3C[8]MMCM1:DRP3C[9]
    37--------------------------MMCM1:DRP3C[10]MMCM1:DRP3C[11]
    38--------------------------MMCM1:DRP3C[12]MMCM1:DRP3C[13]
    39--------------------------MMCM1:DRP3C[14]MMCM1:DRP3C[15]
    40--------------------------MMCM1:DRP3D[0]MMCM1:DRP3D[1]
    41--------------------------MMCM1:DRP3D[2]MMCM1:DRP3D[3]
    42--------------------------MMCM1:DRP3D[4]MMCM1:DRP3D[5]
    43--------------------------MMCM1:DRP3D[6]MMCM1:DRP3D[7]
    44--------------------------MMCM1:DRP3D[8]MMCM1:DRP3D[9]
    45--------------------------MMCM1:DRP3D[10]MMCM1:DRP3D[11]
    46--------------------------MMCM1:DRP3D[12]MMCM1:DRP3D[13]
    47--------------------------MMCM1:DRP3D[14]MMCM1:DRP3D[15]
    48--------------------------MMCM1:DRP3E[0]MMCM1:DRP3E[1]
    49--------------------------MMCM1:DRP3E[2]MMCM1:DRP3E[3]
    50--------------------------MMCM1:DRP3E[4]MMCM1:DRP3E[5]
    51--------------------------MMCM1:DRP3E[6]MMCM1:DRP3E[7]
    52--------------------------MMCM1:DRP3E[8]MMCM1:DRP3E[9]
    53--------------------------MMCM1:DRP3E[10]MMCM1:DRP3E[11]
    54--------------------------MMCM1:DRP3E[12]MMCM1:DRP3E[13]
    55--------------------------MMCM1:DRP3E[14]MMCM1:DRP3E[15]
    56--------------------------MMCM1:DRP3F[0]MMCM1:DRP3F[1]
    57--------------------------MMCM1:DRP3F[2]MMCM1:DRP3F[3]
    58--------------------------MMCM1:DRP3F[4]MMCM1:DRP3F[5]
    59--------------------------MMCM1:DRP3F[6]MMCM1:DRP3F[7]
    60--------------------------MMCM1:DRP3F[8]MMCM1:DRP3F[9]
    61--------------------------MMCM1:DRP3F[10]MMCM1:DRP3F[11]
    62--------------------------MMCM1:DRP3F[12]MMCM1:DRP3F[13]
    63--------------------------MMCM1:DRP3F[14]MMCM1:DRP3F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 30
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP40[0]MMCM1:DRP40[1]
    1--------------------------MMCM1:DRP40[2]MMCM1:DRP40[3]
    2--------------------------MMCM1:DRP40[4]MMCM1:DRP40[5]
    3--------------------------MMCM1:DRP40[6]MMCM1:DRP40[7]
    4--------------------------MMCM1:DRP40[8]MMCM1:DRP40[9]
    5--------------------------MMCM1:DRP40[10]MMCM1:DRP40[11]
    6--------------------------MMCM1:DRP40[12]MMCM1:DRP40[13]
    7--------------------------MMCM1:DRP40[14]MMCM1:DRP40[15]
    8--------------------------MMCM1:DRP41[0]MMCM1:DRP41[1]
    9--------------------------MMCM1:DRP41[2]MMCM1:DRP41[3]
    10--------------------------MMCM1:DRP41[4]MMCM1:DRP41[5]
    11--------------------------MMCM1:DRP41[6]MMCM1:DRP41[7]
    12--------------------------MMCM1:DRP41[8]MMCM1:DRP41[9]
    13--------------------------MMCM1:DRP41[10]MMCM1:DRP41[11]
    14--------------------------MMCM1:DRP41[12]MMCM1:DRP41[13]
    15--------------------------MMCM1:DRP41[14]MMCM1:DRP41[15]
    16--------------------------MMCM1:DRP42[0]
    MMCM1:MAN_LF[0]    		MMCM1:DRP42[1]
    17--------------------------MMCM1:DRP42[2]MMCM1:DRP42[3]
    MMCM1:MAN_LF[1]
    18--------------------------MMCM1:DRP42[4]
    MMCM1:MAN_LF[2]    		MMCM1:DRP42[5]
    19--------------------------MMCM1:DRP42[6]MMCM1:DRP42[7]
    MMCM1:VLF_HIGH_DIS_B
    20--------------------------MMCM1:DRP42[8]
    MMCM1:LF_PEN[0]    		MMCM1:DRP42[9]
    21--------------------------MMCM1:DRP42[10]MMCM1:DRP42[11]
    MMCM1:LF_PEN[1]
    22--------------------------MMCM1:DRP42[12]
    MMCM1:LF_NEN[0]    		MMCM1:DRP42[13]
    23--------------------------MMCM1:DRP42[14]MMCM1:DRP42[15]
    MMCM1:LF_NEN[1]
    24--------------------------MMCM1:DRP43[0]MMCM1:DRP43[1]
    25--------------------------MMCM1:DRP43[2]MMCM1:DRP43[3]
    26--------------------------MMCM1:DRP43[4]MMCM1:DRP43[5]
    27--------------------------MMCM1:DRP43[6]MMCM1:DRP43[7]
    28--------------------------MMCM1:DRP43[8]MMCM1:DRP43[9]
    29--------------------------MMCM1:DRP43[10]MMCM1:DRP43[11]
    30--------------------------MMCM1:DRP43[12]MMCM1:DRP43[13]
    31--------------------------MMCM1:DRP43[14]MMCM1:DRP43[15]
    32--------------------------MMCM1:DRP44[0]MMCM1:DRP44[1]
    33--------------------------MMCM1:DRP44[2]MMCM1:DRP44[3]
    34--------------------------MMCM1:DRP44[4]MMCM1:DRP44[5]
    35--------------------------MMCM1:DRP44[6]MMCM1:DRP44[7]
    36--------------------------MMCM1:DRP44[8]MMCM1:DRP44[9]
    37--------------------------MMCM1:DRP44[10]MMCM1:DRP44[11]
    38--------------------------MMCM1:DRP44[12]MMCM1:DRP44[13]
    39--------------------------MMCM1:DRP44[14]MMCM1:DRP44[15]
    40--------------------------MMCM1:DRP45[0]MMCM1:DRP45[1]
    41--------------------------MMCM1:DRP45[2]MMCM1:DRP45[3]
    42--------------------------MMCM1:DRP45[4]MMCM1:DRP45[5]
    43--------------------------MMCM1:DRP45[6]MMCM1:DRP45[7]
    44--------------------------MMCM1:DRP45[8]MMCM1:DRP45[9]
    45--------------------------MMCM1:DRP45[10]MMCM1:DRP45[11]
    46--------------------------MMCM1:DRP45[12]MMCM1:DRP45[13]
    47--------------------------MMCM1:DRP45[14]MMCM1:DRP45[15]
    48--------------------------MMCM1:DRP46[0]
    MMCM1:VLF_HIGH_PWDN_B    		MMCM1:DRP46[1]
    49--------------------------MMCM1:DRP46[2]MMCM1:DRP46[3]
    50--------------------------MMCM1:DRP46[4]MMCM1:DRP46[5]
    51--------------------------MMCM1:DRP46[6]MMCM1:DRP46[7]
    52--------------------------MMCM1:DRP46[8]MMCM1:DRP46[9]
    53--------------------------MMCM1:DRP46[10]MMCM1:DRP46[11]
    54--------------------------MMCM1:DRP46[12]MMCM1:DRP46[13]
    55--------------------------MMCM1:DRP46[14]MMCM1:DRP46[15]
    56--------------------------MMCM1:DRP47[0]MMCM1:DRP47[1]
    57--------------------------MMCM1:DRP47[2]MMCM1:DRP47[3]
    58--------------------------MMCM1:DRP47[4]MMCM1:DRP47[5]
    59--------------------------MMCM1:DRP47[6]MMCM1:DRP47[7]
    60--------------------------MMCM1:DRP47[8]MMCM1:DRP47[9]
    61--------------------------MMCM1:DRP47[10]MMCM1:DRP47[11]
    62--------------------------MMCM1:DRP47[12]MMCM1:DRP47[13]
    63--------------------------MMCM1:DRP47[14]MMCM1:DRP47[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 31
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP48[0]MMCM1:DRP48[1]
    1--------------------------MMCM1:DRP48[2]MMCM1:DRP48[3]
    2--------------------------MMCM1:DRP48[4]MMCM1:DRP48[5]
    3--------------------------MMCM1:DRP48[6]MMCM1:DRP48[7]
    4--------------------------MMCM1:DRP48[8]MMCM1:DRP48[9]
    5--------------------------MMCM1:DRP48[10]MMCM1:DRP48[11]
    6--------------------------MMCM1:DRP48[12]MMCM1:DRP48[13]
    7--------------------------MMCM1:DRP48[14]MMCM1:DRP48[15]
    8--------------------------MMCM1:DRP49[0]MMCM1:DRP49[1]
    9--------------------------MMCM1:DRP49[2]MMCM1:DRP49[3]
    10--------------------------MMCM1:DRP49[4]MMCM1:DRP49[5]
    11--------------------------MMCM1:DRP49[6]MMCM1:DRP49[7]
    12--------------------------MMCM1:DRP49[8]MMCM1:DRP49[9]
    13--------------------------MMCM1:DRP49[10]MMCM1:DRP49[11]
    14--------------------------MMCM1:DRP49[12]MMCM1:DRP49[13]
    15--------------------------MMCM1:DRP49[14]MMCM1:DRP49[15]
    16--------------------------MMCM1:AVDD_VBG_SEL[0]
    MMCM1:DRP4A[0]    		MMCM1:AVDD_VBG_SEL[1]
    MMCM1:DRP4A[1]
    17--------------------------MMCM1:AVDD_VBG_SEL[2]
    MMCM1:DRP4A[2]    		MMCM1:AVDD_VBG_SEL[3]
    MMCM1:DRP4A[3]
    18--------------------------MMCM1:AVDD_VBG_PD[0]
    MMCM1:DRP4A[4]    		MMCM1:AVDD_VBG_PD[1]
    MMCM1:DRP4A[5]
    19--------------------------MMCM1:AVDD_VBG_PD[2]
    MMCM1:DRP4A[6]    		MMCM1:AVDD_COMP_SET[0]
    MMCM1:DRP4A[7]
    20--------------------------MMCM1:AVDD_COMP_SET[1]
    MMCM1:DRP4A[8]    		MMCM1:DRP4A[9]
    21--------------------------MMCM1:DRP4A[10]MMCM1:DRP4A[11]
    22--------------------------MMCM1:DRP4A[12]MMCM1:DRP4A[13]
    23--------------------------MMCM1:DRP4A[14]MMCM1:DRP4A[15]
    24--------------------------MMCM1:DRP4B[0]MMCM1:DRP4B[1]
    25--------------------------MMCM1:DRP4B[2]MMCM1:DRP4B[3]
    26--------------------------MMCM1:DRP4B[4]MMCM1:DRP4B[5]
    27--------------------------MMCM1:DRP4B[6]MMCM1:DRP4B[7]
    28--------------------------MMCM1:DRP4B[8]MMCM1:DRP4B[9]
    29--------------------------MMCM1:DRP4B[10]MMCM1:DRP4B[11]
    30--------------------------MMCM1:DRP4B[12]MMCM1:DRP4B[13]
    31--------------------------MMCM1:DRP4B[14]MMCM1:DRP4B[15]
    32--------------------------MMCM1:DRP4C[0]MMCM1:DRP4C[1]
    33--------------------------MMCM1:DRP4C[2]MMCM1:DRP4C[3]
    34--------------------------MMCM1:DRP4C[4]MMCM1:DRP4C[5]
    35--------------------------MMCM1:DRP4C[6]MMCM1:DRP4C[7]
    36--------------------------MMCM1:DRP4C[8]MMCM1:DRP4C[9]
    37--------------------------MMCM1:DRP4C[10]MMCM1:DRP4C[11]
    38--------------------------MMCM1:DRP4C[12]MMCM1:DRP4C[13]
    39--------------------------MMCM1:DRP4C[14]MMCM1:DRP4C[15]
    40--------------------------MMCM1:DRP4D[0]MMCM1:DRP4D[1]
    41--------------------------MMCM1:DRP4D[2]MMCM1:DRP4D[3]
    42--------------------------MMCM1:DRP4D[4]MMCM1:DRP4D[5]
    43--------------------------MMCM1:DRP4D[6]MMCM1:DRP4D[7]
    44--------------------------MMCM1:DRP4D[8]MMCM1:DRP4D[9]
    45--------------------------MMCM1:DRP4D[10]MMCM1:DRP4D[11]
    46--------------------------MMCM1:DRP4D[12]MMCM1:DRP4D[13]
    47--------------------------MMCM1:DRP4D[14]MMCM1:DRP4D[15]
    48--------------------------MMCM1:DRP4E[0]MMCM1:DRP4E[1]
    49--------------------------MMCM1:DRP4E[2]MMCM1:CP_RES[0]
    MMCM1:DRP4E[3]
    50--------------------------MMCM1:CP_RES[1]
    MMCM1:DRP4E[4]    		MMCM1:DRP4E[5]
    51--------------------------MMCM1:DRP4E[6]MMCM1:CP_BIAS_TRIP_SET
    MMCM1:DRP4E[7]
    52--------------------------MMCM1:CP[0]
    MMCM1:DRP4E[8]    		MMCM1:DRP4E[9]
    53--------------------------MMCM1:DRP4E[10]MMCM1:CP[1]
    MMCM1:DRP4E[11]
    54--------------------------MMCM1:CP[2]
    MMCM1:DRP4E[12]    		MMCM1:DRP4E[13]
    55--------------------------MMCM1:DRP4E[14]MMCM1:CP[3]
    MMCM1:DRP4E[15]
    56--------------------------MMCM1:DRP4F[0]MMCM1:DRP4F[1]
    57--------------------------MMCM1:DRP4F[2]MMCM1:DRP4F[3]
    58--------------------------MMCM1:DRP4F[4]
    MMCM1:LFHF[0]    		MMCM1:DRP4F[5]
    59--------------------------MMCM1:DRP4F[6]MMCM1:DRP4F[7]
    MMCM1:LFHF[1]
    60--------------------------MMCM1:DRP4F[8]
    MMCM1:RES[0]    		MMCM1:DRP4F[9]
    61--------------------------MMCM1:DRP4F[10]MMCM1:DRP4F[11]
    MMCM1:RES[1]
    62--------------------------MMCM1:DRP4F[12]
    MMCM1:RES[2]    		MMCM1:DRP4F[13]
    63--------------------------MMCM1:DRP4F[14]MMCM1:DRP4F[15]
    MMCM1:RES[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 32
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP50[0]MMCM1:DRP50[1]
    1--------------------------MMCM1:DRP50[2]MMCM1:DRP50[3]
    2--------------------------MMCM1:DRP50[4]MMCM1:DRP50[5]
    3--------------------------MMCM1:DRP50[6]MMCM1:DRP50[7]
    4--------------------------MMCM1:DRP50[8]MMCM1:DRP50[9]
    5--------------------------MMCM1:DRP50[10]MMCM1:DRP50[11]
    6--------------------------MMCM1:DRP50[12]MMCM1:DRP50[13]
    7--------------------------MMCM1:DRP50[14]MMCM1:DRP50[15]
    8--------------------------MMCM1:DRP51[0]MMCM1:DRP51[1]
    9--------------------------MMCM1:DRP51[2]MMCM1:DRP51[3]
    10--------------------------MMCM1:DRP51[4]MMCM1:DRP51[5]
    11--------------------------MMCM1:DRP51[6]MMCM1:DRP51[7]
    12--------------------------MMCM1:DRP51[8]MMCM1:DRP51[9]
    13--------------------------MMCM1:DRP51[10]MMCM1:DRP51[11]
    14--------------------------MMCM1:DRP51[12]MMCM1:DRP51[13]
    15--------------------------MMCM1:DRP51[14]MMCM1:DRP51[15]
    16--------------------------MMCM1:DRP52[0]MMCM1:DRP52[1]
    17--------------------------MMCM1:DRP52[2]MMCM1:DRP52[3]
    18--------------------------MMCM1:DRP52[4]MMCM1:DRP52[5]
    19--------------------------MMCM1:DRP52[6]MMCM1:DRP52[7]
    20--------------------------MMCM1:DRP52[8]MMCM1:DRP52[9]
    21--------------------------MMCM1:DRP52[10]MMCM1:DRP52[11]
    22--------------------------MMCM1:DRP52[12]MMCM1:DRP52[13]
    23--------------------------MMCM1:DRP52[14]MMCM1:DRP52[15]
    24--------------------------MMCM1:DRP53[0]MMCM1:DRP53[1]
    25--------------------------MMCM1:DRP53[2]MMCM1:DRP53[3]
    26--------------------------MMCM1:DRP53[4]MMCM1:DRP53[5]
    27--------------------------MMCM1:DRP53[6]MMCM1:DRP53[7]
    28--------------------------MMCM1:DRP53[8]MMCM1:DRP53[9]
    29--------------------------MMCM1:DRP53[10]MMCM1:DRP53[11]
    30--------------------------MMCM1:DRP53[12]MMCM1:DRP53[13]
    31--------------------------MMCM1:DRP53[14]MMCM1:DRP53[15]
    32--------------------------MMCM1:DRP54[0]MMCM1:DRP54[1]
    33--------------------------MMCM1:DRP54[2]MMCM1:DRP54[3]
    34--------------------------MMCM1:DRP54[4]MMCM1:DRP54[5]
    35--------------------------MMCM1:DRP54[6]MMCM1:DRP54[7]
    36--------------------------MMCM1:DRP54[8]MMCM1:DRP54[9]
    37--------------------------MMCM1:DRP54[10]MMCM1:DRP54[11]
    38--------------------------MMCM1:DRP54[12]MMCM1:DRP54[13]
    39--------------------------MMCM1:DRP54[14]MMCM1:DRP54[15]
    40--------------------------MMCM1:DRP55[0]MMCM1:DRP55[1]
    41--------------------------MMCM1:DRP55[2]MMCM1:DRP55[3]
    42--------------------------MMCM1:DRP55[4]MMCM1:DRP55[5]
    43--------------------------MMCM1:DRP55[6]MMCM1:DRP55[7]
    44--------------------------MMCM1:DRP55[8]MMCM1:DRP55[9]
    45--------------------------MMCM1:DRP55[10]MMCM1:DRP55[11]
    46--------------------------MMCM1:DRP55[12]MMCM1:DRP55[13]
    47--------------------------MMCM1:DRP55[14]MMCM1:DRP55[15]
    48--------------------------MMCM1:DRP56[0]MMCM1:DRP56[1]
    49--------------------------MMCM1:DRP56[2]MMCM1:DRP56[3]
    50--------------------------MMCM1:DRP56[4]MMCM1:DRP56[5]
    51--------------------------MMCM1:DRP56[6]MMCM1:DRP56[7]
    52--------------------------MMCM1:DRP56[8]MMCM1:DRP56[9]
    53--------------------------MMCM1:DRP56[10]MMCM1:DRP56[11]
    54--------------------------MMCM1:DRP56[12]MMCM1:DRP56[13]
    55--------------------------MMCM1:DRP56[14]MMCM1:DRP56[15]
    56--------------------------MMCM1:DRP57[0]MMCM1:DRP57[1]
    57--------------------------MMCM1:DRP57[2]MMCM1:DRP57[3]
    58--------------------------MMCM1:DRP57[4]MMCM1:DRP57[5]
    59--------------------------MMCM1:DRP57[6]MMCM1:DRP57[7]
    60--------------------------MMCM1:DRP57[8]MMCM1:DRP57[9]
    61--------------------------MMCM1:DRP57[10]MMCM1:DRP57[11]
    62--------------------------MMCM1:DRP57[12]MMCM1:DRP57[13]
    63--------------------------MMCM1:DRP57[14]MMCM1:DRP57[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 33
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP58[0]MMCM1:DRP58[1]
    1--------------------------MMCM1:DRP58[2]MMCM1:DRP58[3]
    2--------------------------MMCM1:DRP58[4]MMCM1:DRP58[5]
    3--------------------------MMCM1:DRP58[6]MMCM1:DRP58[7]
    4--------------------------MMCM1:DRP58[8]MMCM1:DRP58[9]
    5--------------------------MMCM1:DRP58[10]MMCM1:DRP58[11]
    6--------------------------MMCM1:DRP58[12]MMCM1:DRP58[13]
    7--------------------------MMCM1:DRP58[14]MMCM1:DRP58[15]
    8--------------------------MMCM1:DRP59[0]MMCM1:DRP59[1]
    9--------------------------MMCM1:DRP59[2]MMCM1:DRP59[3]
    10--------------------------MMCM1:DRP59[4]MMCM1:DRP59[5]
    11--------------------------MMCM1:DRP59[6]MMCM1:DRP59[7]
    12--------------------------MMCM1:DRP59[8]MMCM1:DRP59[9]
    13--------------------------MMCM1:DRP59[10]MMCM1:DRP59[11]
    14--------------------------MMCM1:DRP59[12]MMCM1:DRP59[13]
    15--------------------------MMCM1:DRP59[14]MMCM1:DRP59[15]
    16--------------------------MMCM1:DRP5A[0]MMCM1:DRP5A[1]
    17--------------------------MMCM1:DRP5A[2]MMCM1:DRP5A[3]
    18--------------------------MMCM1:DRP5A[4]MMCM1:DRP5A[5]
    19--------------------------MMCM1:DRP5A[6]MMCM1:DRP5A[7]
    20--------------------------MMCM1:DRP5A[8]MMCM1:DRP5A[9]
    21--------------------------MMCM1:DRP5A[10]MMCM1:DRP5A[11]
    22--------------------------MMCM1:DRP5A[12]MMCM1:DRP5A[13]
    23--------------------------MMCM1:DRP5A[14]MMCM1:DRP5A[15]
    24--------------------------MMCM1:DRP5B[0]MMCM1:DRP5B[1]
    25--------------------------MMCM1:DRP5B[2]MMCM1:DRP5B[3]
    26--------------------------MMCM1:DRP5B[4]MMCM1:DRP5B[5]
    27--------------------------MMCM1:DRP5B[6]MMCM1:DRP5B[7]
    28--------------------------MMCM1:DRP5B[8]MMCM1:DRP5B[9]
    29--------------------------MMCM1:DRP5B[10]MMCM1:DRP5B[11]
    30--------------------------MMCM1:DRP5B[12]MMCM1:DRP5B[13]
    31--------------------------MMCM1:DRP5B[14]MMCM1:DRP5B[15]
    32--------------------------MMCM1:DRP5C[0]MMCM1:DRP5C[1]
    33--------------------------MMCM1:DRP5C[2]MMCM1:DRP5C[3]
    34--------------------------MMCM1:DRP5C[4]MMCM1:DRP5C[5]
    35--------------------------MMCM1:DRP5C[6]MMCM1:DRP5C[7]
    36--------------------------MMCM1:DRP5C[8]MMCM1:DRP5C[9]
    37--------------------------MMCM1:DRP5C[10]MMCM1:DRP5C[11]
    38--------------------------MMCM1:DRP5C[12]MMCM1:DRP5C[13]
    39--------------------------MMCM1:DRP5C[14]MMCM1:DRP5C[15]
    40--------------------------MMCM1:DRP5D[0]MMCM1:DRP5D[1]
    41--------------------------MMCM1:DRP5D[2]MMCM1:DRP5D[3]
    42--------------------------MMCM1:DRP5D[4]MMCM1:DRP5D[5]
    43--------------------------MMCM1:DRP5D[6]MMCM1:DRP5D[7]
    44--------------------------MMCM1:DRP5D[8]MMCM1:DRP5D[9]
    45--------------------------MMCM1:DRP5D[10]MMCM1:DRP5D[11]
    46--------------------------MMCM1:DRP5D[12]MMCM1:DRP5D[13]
    47--------------------------MMCM1:DRP5D[14]MMCM1:DRP5D[15]
    48--------------------------MMCM1:DRP5E[0]MMCM1:DRP5E[1]
    49--------------------------MMCM1:DRP5E[2]MMCM1:DRP5E[3]
    50--------------------------MMCM1:DRP5E[4]MMCM1:DRP5E[5]
    51--------------------------MMCM1:DRP5E[6]MMCM1:DRP5E[7]
    52--------------------------MMCM1:DRP5E[8]MMCM1:DRP5E[9]
    53--------------------------MMCM1:DRP5E[10]MMCM1:DRP5E[11]
    54--------------------------MMCM1:DRP5E[12]MMCM1:DRP5E[13]
    55--------------------------MMCM1:DRP5E[14]MMCM1:DRP5E[15]
    56--------------------------MMCM1:DRP5F[0]MMCM1:DRP5F[1]
    57--------------------------MMCM1:DRP5F[2]MMCM1:DRP5F[3]
    58--------------------------MMCM1:DRP5F[4]MMCM1:DRP5F[5]
    59--------------------------MMCM1:DRP5F[6]MMCM1:DRP5F[7]
    60--------------------------MMCM1:DRP5F[8]MMCM1:DRP5F[9]
    61--------------------------MMCM1:DRP5F[10]MMCM1:DRP5F[11]
    62--------------------------MMCM1:DRP5F[12]MMCM1:DRP5F[13]
    63--------------------------MMCM1:DRP5F[14]MMCM1:DRP5F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 34
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP60[0]MMCM1:DRP60[1]
    1--------------------------MMCM1:DRP60[2]MMCM1:DRP60[3]
    2--------------------------MMCM1:DRP60[4]MMCM1:DRP60[5]
    3--------------------------MMCM1:DRP60[6]MMCM1:DRP60[7]
    4--------------------------MMCM1:DRP60[8]MMCM1:DRP60[9]
    5--------------------------MMCM1:DRP60[10]MMCM1:DRP60[11]
    6--------------------------MMCM1:DRP60[12]MMCM1:DRP60[13]
    7--------------------------MMCM1:DRP60[14]MMCM1:DRP60[15]
    8--------------------------MMCM1:DRP61[0]MMCM1:DRP61[1]
    9--------------------------MMCM1:DRP61[2]MMCM1:DRP61[3]
    10--------------------------MMCM1:DRP61[4]MMCM1:DRP61[5]
    11--------------------------MMCM1:DRP61[6]MMCM1:DRP61[7]
    12--------------------------MMCM1:DRP61[8]MMCM1:DRP61[9]
    13--------------------------MMCM1:DRP61[10]MMCM1:DRP61[11]
    14--------------------------MMCM1:DRP61[12]MMCM1:DRP61[13]
    15--------------------------MMCM1:DRP61[14]MMCM1:DRP61[15]
    16--------------------------MMCM1:DRP62[0]MMCM1:DRP62[1]
    17--------------------------MMCM1:DRP62[2]MMCM1:DRP62[3]
    18--------------------------MMCM1:DRP62[4]MMCM1:DRP62[5]
    19--------------------------MMCM1:DRP62[6]MMCM1:DRP62[7]
    20--------------------------MMCM1:DRP62[8]MMCM1:DRP62[9]
    21--------------------------MMCM1:DRP62[10]MMCM1:DRP62[11]
    22--------------------------MMCM1:DRP62[12]MMCM1:DRP62[13]
    23--------------------------MMCM1:DRP62[14]MMCM1:DRP62[15]
    24--------------------------MMCM1:DRP63[0]MMCM1:DRP63[1]
    25--------------------------MMCM1:DRP63[2]MMCM1:DRP63[3]
    26--------------------------MMCM1:DRP63[4]MMCM1:DRP63[5]
    27--------------------------MMCM1:DRP63[6]MMCM1:DRP63[7]
    28--------------------------MMCM1:DRP63[8]MMCM1:DRP63[9]
    29--------------------------MMCM1:DRP63[10]MMCM1:DRP63[11]
    30--------------------------MMCM1:DRP63[12]MMCM1:DRP63[13]
    31--------------------------MMCM1:DRP63[14]MMCM1:DRP63[15]
    32--------------------------MMCM1:DRP64[0]MMCM1:DRP64[1]
    33--------------------------MMCM1:DRP64[2]MMCM1:DRP64[3]
    34--------------------------MMCM1:DRP64[4]MMCM1:DRP64[5]
    35--------------------------MMCM1:DRP64[6]MMCM1:DRP64[7]
    36--------------------------MMCM1:DRP64[8]MMCM1:DRP64[9]
    37--------------------------MMCM1:DRP64[10]MMCM1:DRP64[11]
    38--------------------------MMCM1:DRP64[12]MMCM1:DRP64[13]
    39--------------------------MMCM1:DRP64[14]MMCM1:DRP64[15]
    40--------------------------MMCM1:DRP65[0]MMCM1:DRP65[1]
    41--------------------------MMCM1:DRP65[2]MMCM1:DRP65[3]
    42--------------------------MMCM1:DRP65[4]MMCM1:DRP65[5]
    43--------------------------MMCM1:DRP65[6]MMCM1:DRP65[7]
    44--------------------------MMCM1:DRP65[8]MMCM1:DRP65[9]
    45--------------------------MMCM1:DRP65[10]MMCM1:DRP65[11]
    46--------------------------MMCM1:DRP65[12]MMCM1:DRP65[13]
    47--------------------------MMCM1:DRP65[14]MMCM1:DRP65[15]
    48--------------------------MMCM1:DRP66[0]MMCM1:DRP66[1]
    49--------------------------MMCM1:DRP66[2]MMCM1:DRP66[3]
    50--------------------------MMCM1:DRP66[4]MMCM1:DRP66[5]
    51--------------------------MMCM1:DRP66[6]MMCM1:DRP66[7]
    52--------------------------MMCM1:DRP66[8]MMCM1:DRP66[9]
    53--------------------------MMCM1:DRP66[10]MMCM1:DRP66[11]
    54--------------------------MMCM1:DRP66[12]MMCM1:DRP66[13]
    55--------------------------MMCM1:DRP66[14]MMCM1:DRP66[15]
    56--------------------------MMCM1:DRP67[0]MMCM1:DRP67[1]
    57--------------------------MMCM1:DRP67[2]MMCM1:DRP67[3]
    58--------------------------MMCM1:DRP67[4]MMCM1:DRP67[5]
    59--------------------------MMCM1:DRP67[6]MMCM1:DRP67[7]
    60--------------------------MMCM1:DRP67[8]MMCM1:DRP67[9]
    61--------------------------MMCM1:DRP67[10]MMCM1:DRP67[11]
    62--------------------------MMCM1:DRP67[12]MMCM1:DRP67[13]
    63--------------------------MMCM1:DRP67[14]MMCM1:DRP67[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 35
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP68[0]MMCM1:DRP68[1]
    1--------------------------MMCM1:DRP68[2]MMCM1:DRP68[3]
    2--------------------------MMCM1:DRP68[4]MMCM1:DRP68[5]
    3--------------------------MMCM1:DRP68[6]MMCM1:DRP68[7]
    4--------------------------MMCM1:DRP68[8]MMCM1:DRP68[9]
    5--------------------------MMCM1:DRP68[10]MMCM1:DRP68[11]
    6--------------------------MMCM1:DRP68[12]MMCM1:DRP68[13]
    7--------------------------MMCM1:DRP68[14]MMCM1:DRP68[15]
    8--------------------------MMCM1:DRP69[0]MMCM1:DRP69[1]
    9--------------------------MMCM1:DRP69[2]MMCM1:DRP69[3]
    10--------------------------MMCM1:DRP69[4]MMCM1:DRP69[5]
    11--------------------------MMCM1:DRP69[6]MMCM1:DRP69[7]
    12--------------------------MMCM1:DRP69[8]MMCM1:DRP69[9]
    13--------------------------MMCM1:DRP69[10]MMCM1:DRP69[11]
    14--------------------------MMCM1:DRP69[12]MMCM1:DRP69[13]
    15--------------------------MMCM1:DRP69[14]MMCM1:DRP69[15]
    16--------------------------MMCM1:DRP6A[0]MMCM1:DRP6A[1]
    17--------------------------MMCM1:DRP6A[2]MMCM1:DRP6A[3]
    18--------------------------MMCM1:DRP6A[4]MMCM1:DRP6A[5]
    19--------------------------MMCM1:DRP6A[6]MMCM1:DRP6A[7]
    20--------------------------MMCM1:DRP6A[8]MMCM1:DRP6A[9]
    21--------------------------MMCM1:DRP6A[10]MMCM1:DRP6A[11]
    22--------------------------MMCM1:DRP6A[12]MMCM1:DRP6A[13]
    23--------------------------MMCM1:DRP6A[14]MMCM1:DRP6A[15]
    24--------------------------MMCM1:DRP6B[0]MMCM1:DRP6B[1]
    25--------------------------MMCM1:DRP6B[2]MMCM1:DRP6B[3]
    26--------------------------MMCM1:DRP6B[4]MMCM1:DRP6B[5]
    27--------------------------MMCM1:DRP6B[6]MMCM1:DRP6B[7]
    28--------------------------MMCM1:DRP6B[8]MMCM1:DRP6B[9]
    29--------------------------MMCM1:DRP6B[10]MMCM1:DRP6B[11]
    30--------------------------MMCM1:DRP6B[12]MMCM1:DRP6B[13]
    31--------------------------MMCM1:DRP6B[14]MMCM1:DRP6B[15]
    32--------------------------MMCM1:DRP6C[0]MMCM1:DRP6C[1]
    33--------------------------MMCM1:DRP6C[2]MMCM1:DRP6C[3]
    34--------------------------MMCM1:DRP6C[4]MMCM1:DRP6C[5]
    35--------------------------MMCM1:DRP6C[6]MMCM1:DRP6C[7]
    36--------------------------MMCM1:DRP6C[8]MMCM1:DRP6C[9]
    37--------------------------MMCM1:DRP6C[10]MMCM1:DRP6C[11]
    38--------------------------MMCM1:DRP6C[12]MMCM1:DRP6C[13]
    39--------------------------MMCM1:DRP6C[14]MMCM1:DRP6C[15]
    40--------------------------MMCM1:DRP6D[0]MMCM1:DRP6D[1]
    41--------------------------MMCM1:DRP6D[2]MMCM1:DRP6D[3]
    42--------------------------MMCM1:DRP6D[4]MMCM1:DRP6D[5]
    43--------------------------MMCM1:DRP6D[6]MMCM1:DRP6D[7]
    44--------------------------MMCM1:DRP6D[8]MMCM1:DRP6D[9]
    45--------------------------MMCM1:DRP6D[10]MMCM1:DRP6D[11]
    46--------------------------MMCM1:DRP6D[12]MMCM1:DRP6D[13]
    47--------------------------MMCM1:DRP6D[14]MMCM1:DRP6D[15]
    48--------------------------MMCM1:DRP6E[0]MMCM1:DRP6E[1]
    49--------------------------MMCM1:DRP6E[2]MMCM1:DRP6E[3]
    50--------------------------MMCM1:DRP6E[4]MMCM1:DRP6E[5]
    51--------------------------MMCM1:DRP6E[6]MMCM1:DRP6E[7]
    52--------------------------MMCM1:DRP6E[8]MMCM1:DRP6E[9]
    53--------------------------MMCM1:DRP6E[10]MMCM1:DRP6E[11]
    54--------------------------MMCM1:DRP6E[12]MMCM1:DRP6E[13]
    55--------------------------MMCM1:DRP6E[14]MMCM1:DRP6E[15]
    56--------------------------MMCM1:DRP6F[0]MMCM1:DRP6F[1]
    57--------------------------MMCM1:DRP6F[2]MMCM1:DRP6F[3]
    58--------------------------MMCM1:DRP6F[4]MMCM1:DRP6F[5]
    59--------------------------MMCM1:DRP6F[6]MMCM1:DRP6F[7]
    60--------------------------MMCM1:DRP6F[8]MMCM1:DRP6F[9]
    61--------------------------MMCM1:DRP6F[10]MMCM1:DRP6F[11]
    62--------------------------MMCM1:DRP6F[12]MMCM1:DRP6F[13]
    63--------------------------MMCM1:DRP6F[14]MMCM1:DRP6F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 36
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:DRP70[0]MMCM1:DRP70[1]
    1--------------------------MMCM1:DRP70[2]MMCM1:DRP70[3]
    2--------------------------MMCM1:DRP70[4]MMCM1:DRP70[5]
    3--------------------------MMCM1:DRP70[6]MMCM1:DRP70[7]
    4--------------------------MMCM1:DRP70[8]MMCM1:DRP70[9]
    5--------------------------MMCM1:DRP70[10]MMCM1:DRP70[11]
    6--------------------------MMCM1:DRP70[12]MMCM1:DRP70[13]
    7--------------------------MMCM1:DRP70[14]MMCM1:DRP70[15]
    8--------------------------MMCM1:DRP71[0]MMCM1:DRP71[1]
    9--------------------------MMCM1:DRP71[2]MMCM1:DRP71[3]
    10--------------------------MMCM1:DRP71[4]MMCM1:DRP71[5]
    11--------------------------MMCM1:DRP71[6]MMCM1:DRP71[7]
    12--------------------------MMCM1:DRP71[8]MMCM1:DRP71[9]
    13--------------------------MMCM1:DRP71[10]MMCM1:DRP71[11]
    14--------------------------MMCM1:DRP71[12]MMCM1:DRP71[13]
    15--------------------------MMCM1:DRP71[14]MMCM1:DRP71[15]
    16--------------------------MMCM1:DRP72[0]
    MMCM1:INV.RST    		MMCM1:DRP72[1]
    MMCM1:INV.PWRDWN
    17--------------------------MMCM1:DRP72[2]
    MMCM1:INV.PSINCDEC    		MMCM1:DRP72[3]
    MMCM1:INV.PSEN
    18--------------------------MMCM1:DRP72[4]
    MMCM1:INV.CLKINSEL    		MMCM1:DRP72[5]
    19--------------------------MMCM1:DRP72[6]MMCM1:DRP72[7]
    20--------------------------MMCM1:DRP72[8]MMCM1:DRP72[9]
    21--------------------------MMCM1:DRP72[10]MMCM1:DRP72[11]
    22--------------------------MMCM1:DRP72[12]MMCM1:DRP72[13]
    23--------------------------MMCM1:DRP72[14]MMCM1:DRP72[15]
    24--------------------------MMCM1:DRP73[0]MMCM1:DRP73[1]
    25--------------------------MMCM1:DRP73[2]MMCM1:DRP73[3]
    26--------------------------MMCM1:DRP73[4]MMCM1:DRP73[5]
    27--------------------------MMCM1:DRP73[6]MMCM1:DRP73[7]
    28--------------------------MMCM1:DRP73[8]MMCM1:DRP73[9]
    29--------------------------MMCM1:DRP73[10]MMCM1:DRP73[11]
    30--------------------------MMCM1:DRP73[12]MMCM1:DRP73[13]
    31--------------------------MMCM1:DRP73[14]MMCM1:DRP73[15]
    32--------------------------MMCM1:DRP74[0]
    MMCM1:MMCM_EN    		MMCM1:CLOCK_HOLD
    MMCM1:DRP74[1]
    33--------------------------MMCM1:DRP74[2]
    MMCM1:STARTUP_WAIT    		MMCM1:DRP74[3]
    MMCM1:GTS_WAIT
    34--------------------------MMCM1:CASC_LOCK_EN
    MMCM1:DRP74[4]    		MMCM1:DRP74[5]
    MMCM1:FINE_PS_FRAC[0]
    35--------------------------MMCM1:DRP74[6]
    MMCM1:FINE_PS_FRAC[1]    		MMCM1:DRP74[7]
    MMCM1:FINE_PS_FRAC[2]
    36--------------------------MMCM1:DRP74[8]
    MMCM1:FINE_PS_FRAC[3]    		MMCM1:DRP74[9]
    MMCM1:FINE_PS_FRAC[4]
    37--------------------------MMCM1:DRP74[10]
    MMCM1:FINE_PS_FRAC[5]    		MMCM1:DRP74[11]
    38--------------------------MMCM1:DRP74[12]MMCM1:DRP74[13]
    39--------------------------MMCM1:DRP74[14]MMCM1:DRP74[15]
    40--------------------------MMCM1:DRP75[0]MMCM1:DRP75[1]
    41--------------------------MMCM1:DRP75[2]MMCM1:DRP75[3]
    42--------------------------MMCM1:DRP75[4]MMCM1:DRP75[5]
    43--------------------------MMCM1:DRP75[6]MMCM1:DRP75[7]
    44--------------------------MMCM1:DRP75[8]MMCM1:DRP75[9]
    45--------------------------MMCM1:DRP75[10]MMCM1:DRP75[11]
    46--------------------------MMCM1:DRP75[12]MMCM1:DRP75[13]
    47--------------------------MMCM1:DRP75[14]MMCM1:DRP75[15]
    48--------------------------MMCM1:CONTROL_0[0]
    MMCM1:DRP76[0]    		MMCM1:CONTROL_0[1]
    MMCM1:DRP76[1]
    49--------------------------MMCM1:CONTROL_0[2]
    MMCM1:DRP76[2]    		MMCM1:CONTROL_0[3]
    MMCM1:DRP76[3]
    50--------------------------MMCM1:CONTROL_0[4]
    MMCM1:DRP76[4]    		MMCM1:CONTROL_0[5]
    MMCM1:DRP76[5]
    51--------------------------MMCM1:CONTROL_0[6]
    MMCM1:DRP76[6]    		MMCM1:CONTROL_0[7]
    MMCM1:DRP76[7]
    52--------------------------MMCM1:CONTROL_0[8]
    MMCM1:DRP76[8]    		MMCM1:CONTROL_0[9]
    MMCM1:DRP76[9]
    53--------------------------MMCM1:CONTROL_0[10]
    MMCM1:DRP76[10]    		MMCM1:CONTROL_0[11]
    MMCM1:DRP76[11]
    54--------------------------MMCM1:CONTROL_0[12]
    MMCM1:DRP76[12]    		MMCM1:CONTROL_0[13]
    MMCM1:DRP76[13]
    55--------------------------MMCM1:CONTROL_0[14]
    MMCM1:DRP76[14]    		MMCM1:CONTROL_0[15]
    MMCM1:DRP76[15]
    56--------------------------MMCM1:CONTROL_1[0]
    MMCM1:DRP77[0]    		MMCM1:CONTROL_1[1]
    MMCM1:DRP77[1]
    57--------------------------MMCM1:CONTROL_1[2]
    MMCM1:DRP77[2]    		MMCM1:CONTROL_1[3]
    MMCM1:DRP77[3]
    58--------------------------MMCM1:CONTROL_1[4]
    MMCM1:DRP77[4]    		MMCM1:CONTROL_1[5]
    MMCM1:DRP77[5]
    59--------------------------MMCM1:CONTROL_1[6]
    MMCM1:DRP77[6]    		MMCM1:CONTROL_1[7]
    MMCM1:DRP77[7]
    60--------------------------MMCM1:CONTROL_1[8]
    MMCM1:DRP77[8]    		MMCM1:CONTROL_1[9]
    MMCM1:DRP77[9]
    61--------------------------MMCM1:CONTROL_1[10]
    MMCM1:DRP77[10]    		MMCM1:CONTROL_1[11]
    MMCM1:DRP77[11]
    62--------------------------MMCM1:CONTROL_1[12]
    MMCM1:DRP77[12]    		MMCM1:CONTROL_1[13]
    MMCM1:DRP77[13]
    63--------------------------MMCM1:CONTROL_1[14]
    MMCM1:DRP77[14]    		MMCM1:CONTROL_1[15]
    MMCM1:DRP77[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 37
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------MMCM1:CONTROL_2[0]
    MMCM1:DRP78[0]    		MMCM1:CONTROL_2[1]
    MMCM1:DRP78[1]
    1--------------------------MMCM1:CONTROL_2[2]
    MMCM1:DRP78[2]    		MMCM1:CONTROL_2[3]
    MMCM1:DRP78[3]
    2--------------------------MMCM1:CONTROL_2[4]
    MMCM1:DRP78[4]    		MMCM1:CONTROL_2[5]
    MMCM1:DRP78[5]
    3--------------------------MMCM1:CONTROL_2[6]
    MMCM1:DRP78[6]    		MMCM1:CONTROL_2[7]
    MMCM1:DRP78[7]
    4--------------------------MMCM1:CONTROL_2[8]
    MMCM1:DRP78[8]    		MMCM1:CONTROL_2[9]
    MMCM1:DRP78[9]
    5--------------------------MMCM1:CONTROL_2[10]
    MMCM1:DRP78[10]    		MMCM1:CONTROL_2[11]
    MMCM1:DRP78[11]
    6--------------------------MMCM1:CONTROL_2[12]
    MMCM1:DRP78[12]    		MMCM1:CONTROL_2[13]
    MMCM1:DRP78[13]
    7--------------------------MMCM1:CONTROL_2[14]
    MMCM1:DRP78[14]    		MMCM1:CONTROL_2[15]
    MMCM1:DRP78[15]
    8--------------------------MMCM1:CONTROL_3[0]
    MMCM1:DRP79[0]    		MMCM1:CONTROL_3[1]
    MMCM1:DRP79[1]
    9--------------------------MMCM1:CONTROL_3[2]
    MMCM1:DRP79[2]    		MMCM1:CONTROL_3[3]
    MMCM1:DRP79[3]
    10--------------------------MMCM1:CONTROL_3[4]
    MMCM1:DRP79[4]    		MMCM1:CONTROL_3[5]
    MMCM1:DRP79[5]
    11--------------------------MMCM1:CONTROL_3[6]
    MMCM1:DRP79[6]    		MMCM1:CONTROL_3[7]
    MMCM1:DRP79[7]
    12--------------------------MMCM1:CONTROL_3[8]
    MMCM1:DRP79[8]    		MMCM1:CONTROL_3[9]
    MMCM1:DRP79[9]
    13--------------------------MMCM1:CONTROL_3[10]
    MMCM1:DRP79[10]    		MMCM1:CONTROL_3[11]
    MMCM1:DRP79[11]
    14--------------------------MMCM1:CONTROL_3[12]
    MMCM1:DRP79[12]    		MMCM1:CONTROL_3[13]
    MMCM1:DRP79[13]
    15--------------------------MMCM1:CONTROL_3[14]
    MMCM1:DRP79[14]    		MMCM1:CONTROL_3[15]
    MMCM1:DRP79[15]
    16--------------------------MMCM1:CONTROL_4[0]
    MMCM1:DRP7A[0]    		MMCM1:CONTROL_4[1]
    MMCM1:DRP7A[1]
    17--------------------------MMCM1:CONTROL_4[2]
    MMCM1:DRP7A[2]    		MMCM1:CONTROL_4[3]
    MMCM1:DRP7A[3]
    18--------------------------MMCM1:CONTROL_4[4]
    MMCM1:DRP7A[4]    		MMCM1:CONTROL_4[5]
    MMCM1:DRP7A[5]
    19--------------------------MMCM1:CONTROL_4[6]
    MMCM1:DRP7A[6]    		MMCM1:CONTROL_4[7]
    MMCM1:DRP7A[7]
    20--------------------------MMCM1:CONTROL_4[8]
    MMCM1:DRP7A[8]    		MMCM1:CONTROL_4[9]
    MMCM1:DRP7A[9]
    21--------------------------MMCM1:CONTROL_4[10]
    MMCM1:DRP7A[10]    		MMCM1:CONTROL_4[11]
    MMCM1:DRP7A[11]
    22--------------------------MMCM1:CONTROL_4[12]
    MMCM1:DRP7A[12]    		MMCM1:CONTROL_4[13]
    MMCM1:DRP7A[13]
    23--------------------------MMCM1:CONTROL_4[14]
    MMCM1:DRP7A[14]    		MMCM1:CONTROL_4[15]
    MMCM1:DRP7A[15]
    24--------------------------MMCM1:CONTROL_5[0]
    MMCM1:DRP7B[0]    		MMCM1:CONTROL_5[1]
    MMCM1:DRP7B[1]
    25--------------------------MMCM1:CONTROL_5[2]
    MMCM1:DRP7B[2]    		MMCM1:CONTROL_5[3]
    MMCM1:DRP7B[3]
    26--------------------------MMCM1:CONTROL_5[4]
    MMCM1:DRP7B[4]    		MMCM1:CONTROL_5[5]
    MMCM1:DRP7B[5]
    27--------------------------MMCM1:CONTROL_5[6]
    MMCM1:DRP7B[6]    		MMCM1:CONTROL_5[7]
    MMCM1:DRP7B[7]
    28--------------------------MMCM1:CONTROL_5[8]
    MMCM1:DRP7B[8]    		MMCM1:CONTROL_5[9]
    MMCM1:DRP7B[9]
    29--------------------------MMCM1:CONTROL_5[10]
    MMCM1:DRP7B[10]    		MMCM1:CONTROL_5[11]
    MMCM1:DRP7B[11]
    30--------------------------MMCM1:CONTROL_5[12]
    MMCM1:DRP7B[12]    		MMCM1:CONTROL_5[13]
    MMCM1:DRP7B[13]
    31--------------------------MMCM1:CONTROL_5[14]
    MMCM1:DRP7B[14]    		MMCM1:CONTROL_5[15]
    MMCM1:DRP7B[15]
    32--------------------------MMCM1:DRP7C[0]MMCM1:DRP7C[1]
    33--------------------------MMCM1:DRP7C[2]MMCM1:DRP7C[3]
    34--------------------------MMCM1:DRP7C[4]MMCM1:DRP7C[5]
    35--------------------------MMCM1:DRP7C[6]MMCM1:DRP7C[7]
    36--------------------------MMCM1:DRP7C[8]MMCM1:DRP7C[9]
    37--------------------------MMCM1:DRP7C[10]MMCM1:DRP7C[11]
    38--------------------------MMCM1:DRP7C[12]MMCM1:DRP7C[13]
    39--------------------------MMCM1:DRP7C[14]MMCM1:DRP7C[15]
    40--------------------------MMCM1:DRP7D[0]MMCM1:DRP7D[1]
    41--------------------------MMCM1:DRP7D[2]MMCM1:DRP7D[3]
    42--------------------------MMCM1:DRP7D[4]MMCM1:DRP7D[5]
    43--------------------------MMCM1:DRP7D[6]MMCM1:DRP7D[7]
    44--------------------------MMCM1:DRP7D[8]MMCM1:DRP7D[9]
    45--------------------------MMCM1:DRP7D[10]MMCM1:DRP7D[11]
    46--------------------------MMCM1:DRP7D[12]MMCM1:DRP7D[13]
    47--------------------------MMCM1:DRP7D[14]MMCM1:DRP7D[15]
    48--------------------------MMCM1:DRP7E[0]MMCM1:DRP7E[1]
    49--------------------------MMCM1:DRP7E[2]MMCM1:DRP7E[3]
    50--------------------------MMCM1:DRP7E[4]MMCM1:DRP7E[5]
    51--------------------------MMCM1:DRP7E[6]MMCM1:DRP7E[7]
    52--------------------------MMCM1:DRP7E[8]MMCM1:DRP7E[9]
    53--------------------------MMCM1:DRP7E[10]MMCM1:DRP7E[11]
    54--------------------------MMCM1:DRP7E[12]MMCM1:DRP7E[13]
    55--------------------------MMCM1:DRP7E[14]MMCM1:DRP7E[15]
    56--------------------------MMCM1:DRP7F[0]MMCM1:DRP7F[1]
    57--------------------------MMCM1:DRP7F[2]MMCM1:DRP7F[3]
    58--------------------------MMCM1:DRP7F[4]MMCM1:DRP7F[5]
    59--------------------------MMCM1:DRP7F[6]MMCM1:DRP7F[7]
    60--------------------------MMCM1:DRP7F[8]MMCM1:DRP7F[9]
    61--------------------------MMCM1:DRP7F[10]MMCM1:DRP7F[11]
    62--------------------------MMCM1:DRP7F[12]MMCM1:DRP7F[13]
    63--------------------------MMCM1:DRP7F[14]MMCM1:DRP7F[15]
    + + +
    CMT bittile 38
    RowColumn
    + + +
    CMT bittile 39
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 40
    RowColumn
    01234567891011121314151617181920212223242526272829303132
    0---------------------------------
    1---------------------------------
    2---------------------------------
    3---------------------------------
    4---------------------------------
    5---------------------------------
    6---------------------------------
    7---------------------------------
    8---------------------------------
    9---------------------------------
    10---------------------------------
    11---------------------------------
    12---------------------------------
    13---------------------------------
    14--------------------------CMT:ENABLE.GCLK16-CMT:ENABLE.MGT0_LCMT:ENABLE.RCLK0_LCMT:ENABLE.MGT0_RCMT:ENABLE.RCLK0_RCMT:ENABLE.GCLK31
    15--------------------------CMT:ENABLE.GCLK18-CMT:ENABLE.MGT1_LCMT:ENABLE.RCLK1_LCMT:ENABLE.MGT1_RCMT:ENABLE.RCLK1_RCMT:ENABLE.GCLK29
    16--------------------------CMT:ENABLE.GCLK20-CMT:ENABLE.MGT2_LCMT:ENABLE.RCLK2_LCMT:ENABLE.MGT2_RCMT:ENABLE.RCLK2_RCMT:ENABLE.GCLK27
    17--------------------------CMT:ENABLE.GCLK22-CMT:ENABLE.MGT3_LCMT:ENABLE.RCLK3_LCMT:ENABLE.MGT3_RCMT:ENABLE.RCLK3_RCMT:ENABLE.GCLK25
    18--------------------------CMT:ENABLE.GCLK24-CMT:ENABLE.GIO0CMT:ENABLE.RCLK4_LCMT:ENABLE.GIO1CMT:ENABLE.RCLK4_RCMT:ENABLE.GCLK23
    19--------------------------CMT:ENABLE.GCLK26-CMT:ENABLE.GIO2CMT:ENABLE.RCLK5_LCMT:ENABLE.GIO3CMT:ENABLE.RCLK5_RCMT:ENABLE.GCLK21
    20--------------------------CMT:ENABLE.GCLK28-CMT:ENABLE.GIO4CMT:ENABLE.HCLK0_LCMT:ENABLE.GIO5CMT:ENABLE.HCLK0_RCMT:ENABLE.GCLK19
    21--------------------------CMT:ENABLE.GCLK30-CMT:ENABLE.GIO6CMT:ENABLE.HCLK1_LCMT:ENABLE.GIO7CMT:ENABLE.HCLK1_RCMT:ENABLE.GCLK17
    22--------------------------CMT:ENABLE.GCLK14-CMT:ENABLE.MGT4_LCMT:ENABLE.HCLK2_LCMT:ENABLE.MGT4_RCMT:ENABLE.HCLK2_RCMT:ENABLE.GCLK1
    23--------------------------CMT:ENABLE.GCLK12-CMT:ENABLE.MGT5_LCMT:ENABLE.HCLK3_LCMT:ENABLE.MGT5_RCMT:ENABLE.HCLK3_RCMT:ENABLE.GCLK3
    24--------------------------CMT:ENABLE.GCLK10-CMT:ENABLE.CCIO0_LCMT:ENABLE.HCLK4_LCMT:ENABLE.CCIO0_RCMT:ENABLE.HCLK4_RCMT:ENABLE.GCLK5
    25--------------------------CMT:ENABLE.GCLK8-CMT:ENABLE.CCIO1_LCMT:ENABLE.HCLK5_LCMT:ENABLE.CCIO1_RCMT:ENABLE.HCLK5_RCMT:ENABLE.GCLK7
    26--------------------------CMT:ENABLE.GCLK6-CMT:ENABLE.CCIO2_LCMT:ENABLE.HCLK6_LCMT:ENABLE.CCIO2_RCMT:ENABLE.HCLK6_RCMT:ENABLE.GCLK9
    27--------------------------CMT:ENABLE.GCLK4-CMT:ENABLE.CCIO3_LCMT:ENABLE.HCLK7_LCMT:ENABLE.CCIO3_RCMT:ENABLE.HCLK7_RCMT:ENABLE.GCLK11
    28--------------------------CMT:ENABLE.GCLK2-CMT:ENABLE.MGT6_LCMT:ENABLE.HCLK8_LCMT:ENABLE.MGT6_RCMT:ENABLE.HCLK8_RCMT:ENABLE.GCLK13
    29--------------------------CMT:ENABLE.GCLK0-CMT:ENABLE.MGT7_LCMT:ENABLE.HCLK9_LCMT:ENABLE.MGT7_RCMT:ENABLE.HCLK9_RCMT:ENABLE.GCLK15
    30--------------------------CMT:ENABLE.BUFHCE_L_CKINT0-CMT:ENABLE.MGT8_LCMT:ENABLE.HCLK10_LCMT:ENABLE.MGT8_RCMT:ENABLE.HCLK10_RCMT:ENABLE.BUFHCE_R_CKINT0
    31--------------------------CMT:ENABLE.BUFHCE_L_CKINT1-CMT:ENABLE.MGT9_LCMT:ENABLE.HCLK11_LCMT:ENABLE.MGT9_RCMT:ENABLE.HCLK11_RCMT:ENABLE.BUFHCE_R_CKINT1
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    MMCM0:CONTROL_0[3, 27, 8][3, 26, 8][3, 27, 9][3, 26, 9][3, 27, 10][3, 26, 10][3, 27, 11][3, 26, 11][3, 27, 12][3, 26, 12][3, 27, 13][3, 26, 13][3, 27, 14][3, 26, 14][3, 27, 15][3, 26, 15]
    MMCM0:CONTROL_1[3, 27, 0][3, 26, 0][3, 27, 1][3, 26, 1][3, 27, 2][3, 26, 2][3, 27, 3][3, 26, 3][3, 27, 4][3, 26, 4][3, 27, 5][3, 26, 5][3, 27, 6][3, 26, 6][3, 27, 7][3, 26, 7]
    MMCM0:CONTROL_2[2, 27, 56][2, 26, 56][2, 27, 57][2, 26, 57][2, 27, 58][2, 26, 58][2, 27, 59][2, 26, 59][2, 27, 60][2, 26, 60][2, 27, 61][2, 26, 61][2, 27, 62][2, 26, 62][2, 27, 63][2, 26, 63]
    MMCM0:CONTROL_3[2, 27, 48][2, 26, 48][2, 27, 49][2, 26, 49][2, 27, 50][2, 26, 50][2, 27, 51][2, 26, 51][2, 27, 52][2, 26, 52][2, 27, 53][2, 26, 53][2, 27, 54][2, 26, 54][2, 27, 55][2, 26, 55]
    MMCM0:CONTROL_4[2, 27, 40][2, 26, 40][2, 27, 41][2, 26, 41][2, 27, 42][2, 26, 42][2, 27, 43][2, 26, 43][2, 27, 44][2, 26, 44][2, 27, 45][2, 26, 45][2, 27, 46][2, 26, 46][2, 27, 47][2, 26, 47]
    MMCM0:CONTROL_5[2, 27, 32][2, 26, 32][2, 27, 33][2, 26, 33][2, 27, 34][2, 26, 34][2, 27, 35][2, 26, 35][2, 27, 36][2, 26, 36][2, 27, 37][2, 26, 37][2, 27, 38][2, 26, 38][2, 27, 39][2, 26, 39]
    MMCM0:DRP00[17, 27, 56][17, 26, 56][17, 27, 57][17, 26, 57][17, 27, 58][17, 26, 58][17, 27, 59][17, 26, 59][17, 27, 60][17, 26, 60][17, 27, 61][17, 26, 61][17, 27, 62][17, 26, 62][17, 27, 63][17, 26, 63]
    MMCM0:DRP01[17, 27, 48][17, 26, 48][17, 27, 49][17, 26, 49][17, 27, 50][17, 26, 50][17, 27, 51][17, 26, 51][17, 27, 52][17, 26, 52][17, 27, 53][17, 26, 53][17, 27, 54][17, 26, 54][17, 27, 55][17, 26, 55]
    MMCM0:DRP02[17, 27, 40][17, 26, 40][17, 27, 41][17, 26, 41][17, 27, 42][17, 26, 42][17, 27, 43][17, 26, 43][17, 27, 44][17, 26, 44][17, 27, 45][17, 26, 45][17, 27, 46][17, 26, 46][17, 27, 47][17, 26, 47]
    MMCM0:DRP03[17, 27, 32][17, 26, 32][17, 27, 33][17, 26, 33][17, 27, 34][17, 26, 34][17, 27, 35][17, 26, 35][17, 27, 36][17, 26, 36][17, 27, 37][17, 26, 37][17, 27, 38][17, 26, 38][17, 27, 39][17, 26, 39]
    MMCM0:DRP04[17, 27, 24][17, 26, 24][17, 27, 25][17, 26, 25][17, 27, 26][17, 26, 26][17, 27, 27][17, 26, 27][17, 27, 28][17, 26, 28][17, 27, 29][17, 26, 29][17, 27, 30][17, 26, 30][17, 27, 31][17, 26, 31]
    MMCM0:DRP05[17, 27, 16][17, 26, 16][17, 27, 17][17, 26, 17][17, 27, 18][17, 26, 18][17, 27, 19][17, 26, 19][17, 27, 20][17, 26, 20][17, 27, 21][17, 26, 21][17, 27, 22][17, 26, 22][17, 27, 23][17, 26, 23]
    MMCM0:DRP06[17, 27, 8][17, 26, 8][17, 27, 9][17, 26, 9][17, 27, 10][17, 26, 10][17, 27, 11][17, 26, 11][17, 27, 12][17, 26, 12][17, 27, 13][17, 26, 13][17, 27, 14][17, 26, 14][17, 27, 15][17, 26, 15]
    MMCM0:DRP07[17, 27, 0][17, 26, 0][17, 27, 1][17, 26, 1][17, 27, 2][17, 26, 2][17, 27, 3][17, 26, 3][17, 27, 4][17, 26, 4][17, 27, 5][17, 26, 5][17, 27, 6][17, 26, 6][17, 27, 7][17, 26, 7]
    MMCM0:DRP08[16, 27, 56][16, 26, 56][16, 27, 57][16, 26, 57][16, 27, 58][16, 26, 58][16, 27, 59][16, 26, 59][16, 27, 60][16, 26, 60][16, 27, 61][16, 26, 61][16, 27, 62][16, 26, 62][16, 27, 63][16, 26, 63]
    MMCM0:DRP09[16, 27, 48][16, 26, 48][16, 27, 49][16, 26, 49][16, 27, 50][16, 26, 50][16, 27, 51][16, 26, 51][16, 27, 52][16, 26, 52][16, 27, 53][16, 26, 53][16, 27, 54][16, 26, 54][16, 27, 55][16, 26, 55]
    MMCM0:DRP0A[16, 27, 40][16, 26, 40][16, 27, 41][16, 26, 41][16, 27, 42][16, 26, 42][16, 27, 43][16, 26, 43][16, 27, 44][16, 26, 44][16, 27, 45][16, 26, 45][16, 27, 46][16, 26, 46][16, 27, 47][16, 26, 47]
    MMCM0:DRP0B[16, 27, 32][16, 26, 32][16, 27, 33][16, 26, 33][16, 27, 34][16, 26, 34][16, 27, 35][16, 26, 35][16, 27, 36][16, 26, 36][16, 27, 37][16, 26, 37][16, 27, 38][16, 26, 38][16, 27, 39][16, 26, 39]
    MMCM0:DRP0C[16, 27, 24][16, 26, 24][16, 27, 25][16, 26, 25][16, 27, 26][16, 26, 26][16, 27, 27][16, 26, 27][16, 27, 28][16, 26, 28][16, 27, 29][16, 26, 29][16, 27, 30][16, 26, 30][16, 27, 31][16, 26, 31]
    MMCM0:DRP0D[16, 27, 16][16, 26, 16][16, 27, 17][16, 26, 17][16, 27, 18][16, 26, 18][16, 27, 19][16, 26, 19][16, 27, 20][16, 26, 20][16, 27, 21][16, 26, 21][16, 27, 22][16, 26, 22][16, 27, 23][16, 26, 23]
    MMCM0:DRP0E[16, 27, 8][16, 26, 8][16, 27, 9][16, 26, 9][16, 27, 10][16, 26, 10][16, 27, 11][16, 26, 11][16, 27, 12][16, 26, 12][16, 27, 13][16, 26, 13][16, 27, 14][16, 26, 14][16, 27, 15][16, 26, 15]
    MMCM0:DRP0F[16, 27, 0][16, 26, 0][16, 27, 1][16, 26, 1][16, 27, 2][16, 26, 2][16, 27, 3][16, 26, 3][16, 27, 4][16, 26, 4][16, 27, 5][16, 26, 5][16, 27, 6][16, 26, 6][16, 27, 7][16, 26, 7]
    MMCM0:DRP10[15, 27, 56][15, 26, 56][15, 27, 57][15, 26, 57][15, 27, 58][15, 26, 58][15, 27, 59][15, 26, 59][15, 27, 60][15, 26, 60][15, 27, 61][15, 26, 61][15, 27, 62][15, 26, 62][15, 27, 63][15, 26, 63]
    MMCM0:DRP11[15, 27, 48][15, 26, 48][15, 27, 49][15, 26, 49][15, 27, 50][15, 26, 50][15, 27, 51][15, 26, 51][15, 27, 52][15, 26, 52][15, 27, 53][15, 26, 53][15, 27, 54][15, 26, 54][15, 27, 55][15, 26, 55]
    MMCM0:DRP12[15, 27, 40][15, 26, 40][15, 27, 41][15, 26, 41][15, 27, 42][15, 26, 42][15, 27, 43][15, 26, 43][15, 27, 44][15, 26, 44][15, 27, 45][15, 26, 45][15, 27, 46][15, 26, 46][15, 27, 47][15, 26, 47]
    MMCM0:DRP13[15, 27, 32][15, 26, 32][15, 27, 33][15, 26, 33][15, 27, 34][15, 26, 34][15, 27, 35][15, 26, 35][15, 27, 36][15, 26, 36][15, 27, 37][15, 26, 37][15, 27, 38][15, 26, 38][15, 27, 39][15, 26, 39]
    MMCM0:DRP14[15, 27, 24][15, 26, 24][15, 27, 25][15, 26, 25][15, 27, 26][15, 26, 26][15, 27, 27][15, 26, 27][15, 27, 28][15, 26, 28][15, 27, 29][15, 26, 29][15, 27, 30][15, 26, 30][15, 27, 31][15, 26, 31]
    MMCM0:DRP15[15, 27, 16][15, 26, 16][15, 27, 17][15, 26, 17][15, 27, 18][15, 26, 18][15, 27, 19][15, 26, 19][15, 27, 20][15, 26, 20][15, 27, 21][15, 26, 21][15, 27, 22][15, 26, 22][15, 27, 23][15, 26, 23]
    MMCM0:DRP16[15, 27, 8][15, 26, 8][15, 27, 9][15, 26, 9][15, 27, 10][15, 26, 10][15, 27, 11][15, 26, 11][15, 27, 12][15, 26, 12][15, 27, 13][15, 26, 13][15, 27, 14][15, 26, 14][15, 27, 15][15, 26, 15]
    MMCM0:DRP17[15, 27, 0][15, 26, 0][15, 27, 1][15, 26, 1][15, 27, 2][15, 26, 2][15, 27, 3][15, 26, 3][15, 27, 4][15, 26, 4][15, 27, 5][15, 26, 5][15, 27, 6][15, 26, 6][15, 27, 7][15, 26, 7]
    MMCM0:DRP18[14, 27, 56][14, 26, 56][14, 27, 57][14, 26, 57][14, 27, 58][14, 26, 58][14, 27, 59][14, 26, 59][14, 27, 60][14, 26, 60][14, 27, 61][14, 26, 61][14, 27, 62][14, 26, 62][14, 27, 63][14, 26, 63]
    MMCM0:DRP19[14, 27, 48][14, 26, 48][14, 27, 49][14, 26, 49][14, 27, 50][14, 26, 50][14, 27, 51][14, 26, 51][14, 27, 52][14, 26, 52][14, 27, 53][14, 26, 53][14, 27, 54][14, 26, 54][14, 27, 55][14, 26, 55]
    MMCM0:DRP1A[14, 27, 40][14, 26, 40][14, 27, 41][14, 26, 41][14, 27, 42][14, 26, 42][14, 27, 43][14, 26, 43][14, 27, 44][14, 26, 44][14, 27, 45][14, 26, 45][14, 27, 46][14, 26, 46][14, 27, 47][14, 26, 47]
    MMCM0:DRP1B[14, 27, 32][14, 26, 32][14, 27, 33][14, 26, 33][14, 27, 34][14, 26, 34][14, 27, 35][14, 26, 35][14, 27, 36][14, 26, 36][14, 27, 37][14, 26, 37][14, 27, 38][14, 26, 38][14, 27, 39][14, 26, 39]
    MMCM0:DRP1C[14, 27, 24][14, 26, 24][14, 27, 25][14, 26, 25][14, 27, 26][14, 26, 26][14, 27, 27][14, 26, 27][14, 27, 28][14, 26, 28][14, 27, 29][14, 26, 29][14, 27, 30][14, 26, 30][14, 27, 31][14, 26, 31]
    MMCM0:DRP1D[14, 27, 16][14, 26, 16][14, 27, 17][14, 26, 17][14, 27, 18][14, 26, 18][14, 27, 19][14, 26, 19][14, 27, 20][14, 26, 20][14, 27, 21][14, 26, 21][14, 27, 22][14, 26, 22][14, 27, 23][14, 26, 23]
    MMCM0:DRP1E[14, 27, 8][14, 26, 8][14, 27, 9][14, 26, 9][14, 27, 10][14, 26, 10][14, 27, 11][14, 26, 11][14, 27, 12][14, 26, 12][14, 27, 13][14, 26, 13][14, 27, 14][14, 26, 14][14, 27, 15][14, 26, 15]
    MMCM0:DRP1F[14, 27, 0][14, 26, 0][14, 27, 1][14, 26, 1][14, 27, 2][14, 26, 2][14, 27, 3][14, 26, 3][14, 27, 4][14, 26, 4][14, 27, 5][14, 26, 5][14, 27, 6][14, 26, 6][14, 27, 7][14, 26, 7]
    MMCM0:DRP20[13, 27, 56][13, 26, 56][13, 27, 57][13, 26, 57][13, 27, 58][13, 26, 58][13, 27, 59][13, 26, 59][13, 27, 60][13, 26, 60][13, 27, 61][13, 26, 61][13, 27, 62][13, 26, 62][13, 27, 63][13, 26, 63]
    MMCM0:DRP21[13, 27, 48][13, 26, 48][13, 27, 49][13, 26, 49][13, 27, 50][13, 26, 50][13, 27, 51][13, 26, 51][13, 27, 52][13, 26, 52][13, 27, 53][13, 26, 53][13, 27, 54][13, 26, 54][13, 27, 55][13, 26, 55]
    MMCM0:DRP22[13, 27, 40][13, 26, 40][13, 27, 41][13, 26, 41][13, 27, 42][13, 26, 42][13, 27, 43][13, 26, 43][13, 27, 44][13, 26, 44][13, 27, 45][13, 26, 45][13, 27, 46][13, 26, 46][13, 27, 47][13, 26, 47]
    MMCM0:DRP23[13, 27, 32][13, 26, 32][13, 27, 33][13, 26, 33][13, 27, 34][13, 26, 34][13, 27, 35][13, 26, 35][13, 27, 36][13, 26, 36][13, 27, 37][13, 26, 37][13, 27, 38][13, 26, 38][13, 27, 39][13, 26, 39]
    MMCM0:DRP24[13, 27, 24][13, 26, 24][13, 27, 25][13, 26, 25][13, 27, 26][13, 26, 26][13, 27, 27][13, 26, 27][13, 27, 28][13, 26, 28][13, 27, 29][13, 26, 29][13, 27, 30][13, 26, 30][13, 27, 31][13, 26, 31]
    MMCM0:DRP25[13, 27, 16][13, 26, 16][13, 27, 17][13, 26, 17][13, 27, 18][13, 26, 18][13, 27, 19][13, 26, 19][13, 27, 20][13, 26, 20][13, 27, 21][13, 26, 21][13, 27, 22][13, 26, 22][13, 27, 23][13, 26, 23]
    MMCM0:DRP26[13, 27, 8][13, 26, 8][13, 27, 9][13, 26, 9][13, 27, 10][13, 26, 10][13, 27, 11][13, 26, 11][13, 27, 12][13, 26, 12][13, 27, 13][13, 26, 13][13, 27, 14][13, 26, 14][13, 27, 15][13, 26, 15]
    MMCM0:DRP27[13, 27, 0][13, 26, 0][13, 27, 1][13, 26, 1][13, 27, 2][13, 26, 2][13, 27, 3][13, 26, 3][13, 27, 4][13, 26, 4][13, 27, 5][13, 26, 5][13, 27, 6][13, 26, 6][13, 27, 7][13, 26, 7]
    MMCM0:DRP28[12, 27, 56][12, 26, 56][12, 27, 57][12, 26, 57][12, 27, 58][12, 26, 58][12, 27, 59][12, 26, 59][12, 27, 60][12, 26, 60][12, 27, 61][12, 26, 61][12, 27, 62][12, 26, 62][12, 27, 63][12, 26, 63]
    MMCM0:DRP29[12, 27, 48][12, 26, 48][12, 27, 49][12, 26, 49][12, 27, 50][12, 26, 50][12, 27, 51][12, 26, 51][12, 27, 52][12, 26, 52][12, 27, 53][12, 26, 53][12, 27, 54][12, 26, 54][12, 27, 55][12, 26, 55]
    MMCM0:DRP2A[12, 27, 40][12, 26, 40][12, 27, 41][12, 26, 41][12, 27, 42][12, 26, 42][12, 27, 43][12, 26, 43][12, 27, 44][12, 26, 44][12, 27, 45][12, 26, 45][12, 27, 46][12, 26, 46][12, 27, 47][12, 26, 47]
    MMCM0:DRP2B[12, 27, 32][12, 26, 32][12, 27, 33][12, 26, 33][12, 27, 34][12, 26, 34][12, 27, 35][12, 26, 35][12, 27, 36][12, 26, 36][12, 27, 37][12, 26, 37][12, 27, 38][12, 26, 38][12, 27, 39][12, 26, 39]
    MMCM0:DRP2C[12, 27, 24][12, 26, 24][12, 27, 25][12, 26, 25][12, 27, 26][12, 26, 26][12, 27, 27][12, 26, 27][12, 27, 28][12, 26, 28][12, 27, 29][12, 26, 29][12, 27, 30][12, 26, 30][12, 27, 31][12, 26, 31]
    MMCM0:DRP2D[12, 27, 16][12, 26, 16][12, 27, 17][12, 26, 17][12, 27, 18][12, 26, 18][12, 27, 19][12, 26, 19][12, 27, 20][12, 26, 20][12, 27, 21][12, 26, 21][12, 27, 22][12, 26, 22][12, 27, 23][12, 26, 23]
    MMCM0:DRP2E[12, 27, 8][12, 26, 8][12, 27, 9][12, 26, 9][12, 27, 10][12, 26, 10][12, 27, 11][12, 26, 11][12, 27, 12][12, 26, 12][12, 27, 13][12, 26, 13][12, 27, 14][12, 26, 14][12, 27, 15][12, 26, 15]
    MMCM0:DRP2F[12, 27, 0][12, 26, 0][12, 27, 1][12, 26, 1][12, 27, 2][12, 26, 2][12, 27, 3][12, 26, 3][12, 27, 4][12, 26, 4][12, 27, 5][12, 26, 5][12, 27, 6][12, 26, 6][12, 27, 7][12, 26, 7]
    MMCM0:DRP30[11, 27, 56][11, 26, 56][11, 27, 57][11, 26, 57][11, 27, 58][11, 26, 58][11, 27, 59][11, 26, 59][11, 27, 60][11, 26, 60][11, 27, 61][11, 26, 61][11, 27, 62][11, 26, 62][11, 27, 63][11, 26, 63]
    MMCM0:DRP31[11, 27, 48][11, 26, 48][11, 27, 49][11, 26, 49][11, 27, 50][11, 26, 50][11, 27, 51][11, 26, 51][11, 27, 52][11, 26, 52][11, 27, 53][11, 26, 53][11, 27, 54][11, 26, 54][11, 27, 55][11, 26, 55]
    MMCM0:DRP32[11, 27, 40][11, 26, 40][11, 27, 41][11, 26, 41][11, 27, 42][11, 26, 42][11, 27, 43][11, 26, 43][11, 27, 44][11, 26, 44][11, 27, 45][11, 26, 45][11, 27, 46][11, 26, 46][11, 27, 47][11, 26, 47]
    MMCM0:DRP33[11, 27, 32][11, 26, 32][11, 27, 33][11, 26, 33][11, 27, 34][11, 26, 34][11, 27, 35][11, 26, 35][11, 27, 36][11, 26, 36][11, 27, 37][11, 26, 37][11, 27, 38][11, 26, 38][11, 27, 39][11, 26, 39]
    MMCM0:DRP34[11, 27, 24][11, 26, 24][11, 27, 25][11, 26, 25][11, 27, 26][11, 26, 26][11, 27, 27][11, 26, 27][11, 27, 28][11, 26, 28][11, 27, 29][11, 26, 29][11, 27, 30][11, 26, 30][11, 27, 31][11, 26, 31]
    MMCM0:DRP35[11, 27, 16][11, 26, 16][11, 27, 17][11, 26, 17][11, 27, 18][11, 26, 18][11, 27, 19][11, 26, 19][11, 27, 20][11, 26, 20][11, 27, 21][11, 26, 21][11, 27, 22][11, 26, 22][11, 27, 23][11, 26, 23]
    MMCM0:DRP36[11, 27, 8][11, 26, 8][11, 27, 9][11, 26, 9][11, 27, 10][11, 26, 10][11, 27, 11][11, 26, 11][11, 27, 12][11, 26, 12][11, 27, 13][11, 26, 13][11, 27, 14][11, 26, 14][11, 27, 15][11, 26, 15]
    MMCM0:DRP37[11, 27, 0][11, 26, 0][11, 27, 1][11, 26, 1][11, 27, 2][11, 26, 2][11, 27, 3][11, 26, 3][11, 27, 4][11, 26, 4][11, 27, 5][11, 26, 5][11, 27, 6][11, 26, 6][11, 27, 7][11, 26, 7]
    MMCM0:DRP38[10, 27, 56][10, 26, 56][10, 27, 57][10, 26, 57][10, 27, 58][10, 26, 58][10, 27, 59][10, 26, 59][10, 27, 60][10, 26, 60][10, 27, 61][10, 26, 61][10, 27, 62][10, 26, 62][10, 27, 63][10, 26, 63]
    MMCM0:DRP39[10, 27, 48][10, 26, 48][10, 27, 49][10, 26, 49][10, 27, 50][10, 26, 50][10, 27, 51][10, 26, 51][10, 27, 52][10, 26, 52][10, 27, 53][10, 26, 53][10, 27, 54][10, 26, 54][10, 27, 55][10, 26, 55]
    MMCM0:DRP3A[10, 27, 40][10, 26, 40][10, 27, 41][10, 26, 41][10, 27, 42][10, 26, 42][10, 27, 43][10, 26, 43][10, 27, 44][10, 26, 44][10, 27, 45][10, 26, 45][10, 27, 46][10, 26, 46][10, 27, 47][10, 26, 47]
    MMCM0:DRP3B[10, 27, 32][10, 26, 32][10, 27, 33][10, 26, 33][10, 27, 34][10, 26, 34][10, 27, 35][10, 26, 35][10, 27, 36][10, 26, 36][10, 27, 37][10, 26, 37][10, 27, 38][10, 26, 38][10, 27, 39][10, 26, 39]
    MMCM0:DRP3C[10, 27, 24][10, 26, 24][10, 27, 25][10, 26, 25][10, 27, 26][10, 26, 26][10, 27, 27][10, 26, 27][10, 27, 28][10, 26, 28][10, 27, 29][10, 26, 29][10, 27, 30][10, 26, 30][10, 27, 31][10, 26, 31]
    MMCM0:DRP3D[10, 27, 16][10, 26, 16][10, 27, 17][10, 26, 17][10, 27, 18][10, 26, 18][10, 27, 19][10, 26, 19][10, 27, 20][10, 26, 20][10, 27, 21][10, 26, 21][10, 27, 22][10, 26, 22][10, 27, 23][10, 26, 23]
    MMCM0:DRP3E[10, 27, 8][10, 26, 8][10, 27, 9][10, 26, 9][10, 27, 10][10, 26, 10][10, 27, 11][10, 26, 11][10, 27, 12][10, 26, 12][10, 27, 13][10, 26, 13][10, 27, 14][10, 26, 14][10, 27, 15][10, 26, 15]
    MMCM0:DRP3F[10, 27, 0][10, 26, 0][10, 27, 1][10, 26, 1][10, 27, 2][10, 26, 2][10, 27, 3][10, 26, 3][10, 27, 4][10, 26, 4][10, 27, 5][10, 26, 5][10, 27, 6][10, 26, 6][10, 27, 7][10, 26, 7]
    MMCM0:DRP40[9, 27, 56][9, 26, 56][9, 27, 57][9, 26, 57][9, 27, 58][9, 26, 58][9, 27, 59][9, 26, 59][9, 27, 60][9, 26, 60][9, 27, 61][9, 26, 61][9, 27, 62][9, 26, 62][9, 27, 63][9, 26, 63]
    MMCM0:DRP41[9, 27, 48][9, 26, 48][9, 27, 49][9, 26, 49][9, 27, 50][9, 26, 50][9, 27, 51][9, 26, 51][9, 27, 52][9, 26, 52][9, 27, 53][9, 26, 53][9, 27, 54][9, 26, 54][9, 27, 55][9, 26, 55]
    MMCM0:DRP42[9, 27, 40][9, 26, 40][9, 27, 41][9, 26, 41][9, 27, 42][9, 26, 42][9, 27, 43][9, 26, 43][9, 27, 44][9, 26, 44][9, 27, 45][9, 26, 45][9, 27, 46][9, 26, 46][9, 27, 47][9, 26, 47]
    MMCM0:DRP43[9, 27, 32][9, 26, 32][9, 27, 33][9, 26, 33][9, 27, 34][9, 26, 34][9, 27, 35][9, 26, 35][9, 27, 36][9, 26, 36][9, 27, 37][9, 26, 37][9, 27, 38][9, 26, 38][9, 27, 39][9, 26, 39]
    MMCM0:DRP44[9, 27, 24][9, 26, 24][9, 27, 25][9, 26, 25][9, 27, 26][9, 26, 26][9, 27, 27][9, 26, 27][9, 27, 28][9, 26, 28][9, 27, 29][9, 26, 29][9, 27, 30][9, 26, 30][9, 27, 31][9, 26, 31]
    MMCM0:DRP45[9, 27, 16][9, 26, 16][9, 27, 17][9, 26, 17][9, 27, 18][9, 26, 18][9, 27, 19][9, 26, 19][9, 27, 20][9, 26, 20][9, 27, 21][9, 26, 21][9, 27, 22][9, 26, 22][9, 27, 23][9, 26, 23]
    MMCM0:DRP46[9, 27, 8][9, 26, 8][9, 27, 9][9, 26, 9][9, 27, 10][9, 26, 10][9, 27, 11][9, 26, 11][9, 27, 12][9, 26, 12][9, 27, 13][9, 26, 13][9, 27, 14][9, 26, 14][9, 27, 15][9, 26, 15]
    MMCM0:DRP47[9, 27, 0][9, 26, 0][9, 27, 1][9, 26, 1][9, 27, 2][9, 26, 2][9, 27, 3][9, 26, 3][9, 27, 4][9, 26, 4][9, 27, 5][9, 26, 5][9, 27, 6][9, 26, 6][9, 27, 7][9, 26, 7]
    MMCM0:DRP48[8, 27, 56][8, 26, 56][8, 27, 57][8, 26, 57][8, 27, 58][8, 26, 58][8, 27, 59][8, 26, 59][8, 27, 60][8, 26, 60][8, 27, 61][8, 26, 61][8, 27, 62][8, 26, 62][8, 27, 63][8, 26, 63]
    MMCM0:DRP49[8, 27, 48][8, 26, 48][8, 27, 49][8, 26, 49][8, 27, 50][8, 26, 50][8, 27, 51][8, 26, 51][8, 27, 52][8, 26, 52][8, 27, 53][8, 26, 53][8, 27, 54][8, 26, 54][8, 27, 55][8, 26, 55]
    MMCM0:DRP4A[8, 27, 40][8, 26, 40][8, 27, 41][8, 26, 41][8, 27, 42][8, 26, 42][8, 27, 43][8, 26, 43][8, 27, 44][8, 26, 44][8, 27, 45][8, 26, 45][8, 27, 46][8, 26, 46][8, 27, 47][8, 26, 47]
    MMCM0:DRP4B[8, 27, 32][8, 26, 32][8, 27, 33][8, 26, 33][8, 27, 34][8, 26, 34][8, 27, 35][8, 26, 35][8, 27, 36][8, 26, 36][8, 27, 37][8, 26, 37][8, 27, 38][8, 26, 38][8, 27, 39][8, 26, 39]
    MMCM0:DRP4C[8, 27, 24][8, 26, 24][8, 27, 25][8, 26, 25][8, 27, 26][8, 26, 26][8, 27, 27][8, 26, 27][8, 27, 28][8, 26, 28][8, 27, 29][8, 26, 29][8, 27, 30][8, 26, 30][8, 27, 31][8, 26, 31]
    MMCM0:DRP4D[8, 27, 16][8, 26, 16][8, 27, 17][8, 26, 17][8, 27, 18][8, 26, 18][8, 27, 19][8, 26, 19][8, 27, 20][8, 26, 20][8, 27, 21][8, 26, 21][8, 27, 22][8, 26, 22][8, 27, 23][8, 26, 23]
    MMCM0:DRP4E[8, 27, 8][8, 26, 8][8, 27, 9][8, 26, 9][8, 27, 10][8, 26, 10][8, 27, 11][8, 26, 11][8, 27, 12][8, 26, 12][8, 27, 13][8, 26, 13][8, 27, 14][8, 26, 14][8, 27, 15][8, 26, 15]
    MMCM0:DRP4F[8, 27, 0][8, 26, 0][8, 27, 1][8, 26, 1][8, 27, 2][8, 26, 2][8, 27, 3][8, 26, 3][8, 27, 4][8, 26, 4][8, 27, 5][8, 26, 5][8, 27, 6][8, 26, 6][8, 27, 7][8, 26, 7]
    MMCM0:DRP50[7, 27, 56][7, 26, 56][7, 27, 57][7, 26, 57][7, 27, 58][7, 26, 58][7, 27, 59][7, 26, 59][7, 27, 60][7, 26, 60][7, 27, 61][7, 26, 61][7, 27, 62][7, 26, 62][7, 27, 63][7, 26, 63]
    MMCM0:DRP51[7, 27, 48][7, 26, 48][7, 27, 49][7, 26, 49][7, 27, 50][7, 26, 50][7, 27, 51][7, 26, 51][7, 27, 52][7, 26, 52][7, 27, 53][7, 26, 53][7, 27, 54][7, 26, 54][7, 27, 55][7, 26, 55]
    MMCM0:DRP52[7, 27, 40][7, 26, 40][7, 27, 41][7, 26, 41][7, 27, 42][7, 26, 42][7, 27, 43][7, 26, 43][7, 27, 44][7, 26, 44][7, 27, 45][7, 26, 45][7, 27, 46][7, 26, 46][7, 27, 47][7, 26, 47]
    MMCM0:DRP53[7, 27, 32][7, 26, 32][7, 27, 33][7, 26, 33][7, 27, 34][7, 26, 34][7, 27, 35][7, 26, 35][7, 27, 36][7, 26, 36][7, 27, 37][7, 26, 37][7, 27, 38][7, 26, 38][7, 27, 39][7, 26, 39]
    MMCM0:DRP54[7, 27, 24][7, 26, 24][7, 27, 25][7, 26, 25][7, 27, 26][7, 26, 26][7, 27, 27][7, 26, 27][7, 27, 28][7, 26, 28][7, 27, 29][7, 26, 29][7, 27, 30][7, 26, 30][7, 27, 31][7, 26, 31]
    MMCM0:DRP55[7, 27, 16][7, 26, 16][7, 27, 17][7, 26, 17][7, 27, 18][7, 26, 18][7, 27, 19][7, 26, 19][7, 27, 20][7, 26, 20][7, 27, 21][7, 26, 21][7, 27, 22][7, 26, 22][7, 27, 23][7, 26, 23]
    MMCM0:DRP56[7, 27, 8][7, 26, 8][7, 27, 9][7, 26, 9][7, 27, 10][7, 26, 10][7, 27, 11][7, 26, 11][7, 27, 12][7, 26, 12][7, 27, 13][7, 26, 13][7, 27, 14][7, 26, 14][7, 27, 15][7, 26, 15]
    MMCM0:DRP57[7, 27, 0][7, 26, 0][7, 27, 1][7, 26, 1][7, 27, 2][7, 26, 2][7, 27, 3][7, 26, 3][7, 27, 4][7, 26, 4][7, 27, 5][7, 26, 5][7, 27, 6][7, 26, 6][7, 27, 7][7, 26, 7]
    MMCM0:DRP58[6, 27, 56][6, 26, 56][6, 27, 57][6, 26, 57][6, 27, 58][6, 26, 58][6, 27, 59][6, 26, 59][6, 27, 60][6, 26, 60][6, 27, 61][6, 26, 61][6, 27, 62][6, 26, 62][6, 27, 63][6, 26, 63]
    MMCM0:DRP59[6, 27, 48][6, 26, 48][6, 27, 49][6, 26, 49][6, 27, 50][6, 26, 50][6, 27, 51][6, 26, 51][6, 27, 52][6, 26, 52][6, 27, 53][6, 26, 53][6, 27, 54][6, 26, 54][6, 27, 55][6, 26, 55]
    MMCM0:DRP5A[6, 27, 40][6, 26, 40][6, 27, 41][6, 26, 41][6, 27, 42][6, 26, 42][6, 27, 43][6, 26, 43][6, 27, 44][6, 26, 44][6, 27, 45][6, 26, 45][6, 27, 46][6, 26, 46][6, 27, 47][6, 26, 47]
    MMCM0:DRP5B[6, 27, 32][6, 26, 32][6, 27, 33][6, 26, 33][6, 27, 34][6, 26, 34][6, 27, 35][6, 26, 35][6, 27, 36][6, 26, 36][6, 27, 37][6, 26, 37][6, 27, 38][6, 26, 38][6, 27, 39][6, 26, 39]
    MMCM0:DRP5C[6, 27, 24][6, 26, 24][6, 27, 25][6, 26, 25][6, 27, 26][6, 26, 26][6, 27, 27][6, 26, 27][6, 27, 28][6, 26, 28][6, 27, 29][6, 26, 29][6, 27, 30][6, 26, 30][6, 27, 31][6, 26, 31]
    MMCM0:DRP5D[6, 27, 16][6, 26, 16][6, 27, 17][6, 26, 17][6, 27, 18][6, 26, 18][6, 27, 19][6, 26, 19][6, 27, 20][6, 26, 20][6, 27, 21][6, 26, 21][6, 27, 22][6, 26, 22][6, 27, 23][6, 26, 23]
    MMCM0:DRP5E[6, 27, 8][6, 26, 8][6, 27, 9][6, 26, 9][6, 27, 10][6, 26, 10][6, 27, 11][6, 26, 11][6, 27, 12][6, 26, 12][6, 27, 13][6, 26, 13][6, 27, 14][6, 26, 14][6, 27, 15][6, 26, 15]
    MMCM0:DRP5F[6, 27, 0][6, 26, 0][6, 27, 1][6, 26, 1][6, 27, 2][6, 26, 2][6, 27, 3][6, 26, 3][6, 27, 4][6, 26, 4][6, 27, 5][6, 26, 5][6, 27, 6][6, 26, 6][6, 27, 7][6, 26, 7]
    MMCM0:DRP60[5, 27, 56][5, 26, 56][5, 27, 57][5, 26, 57][5, 27, 58][5, 26, 58][5, 27, 59][5, 26, 59][5, 27, 60][5, 26, 60][5, 27, 61][5, 26, 61][5, 27, 62][5, 26, 62][5, 27, 63][5, 26, 63]
    MMCM0:DRP61[5, 27, 48][5, 26, 48][5, 27, 49][5, 26, 49][5, 27, 50][5, 26, 50][5, 27, 51][5, 26, 51][5, 27, 52][5, 26, 52][5, 27, 53][5, 26, 53][5, 27, 54][5, 26, 54][5, 27, 55][5, 26, 55]
    MMCM0:DRP62[5, 27, 40][5, 26, 40][5, 27, 41][5, 26, 41][5, 27, 42][5, 26, 42][5, 27, 43][5, 26, 43][5, 27, 44][5, 26, 44][5, 27, 45][5, 26, 45][5, 27, 46][5, 26, 46][5, 27, 47][5, 26, 47]
    MMCM0:DRP63[5, 27, 32][5, 26, 32][5, 27, 33][5, 26, 33][5, 27, 34][5, 26, 34][5, 27, 35][5, 26, 35][5, 27, 36][5, 26, 36][5, 27, 37][5, 26, 37][5, 27, 38][5, 26, 38][5, 27, 39][5, 26, 39]
    MMCM0:DRP64[5, 27, 24][5, 26, 24][5, 27, 25][5, 26, 25][5, 27, 26][5, 26, 26][5, 27, 27][5, 26, 27][5, 27, 28][5, 26, 28][5, 27, 29][5, 26, 29][5, 27, 30][5, 26, 30][5, 27, 31][5, 26, 31]
    MMCM0:DRP65[5, 27, 16][5, 26, 16][5, 27, 17][5, 26, 17][5, 27, 18][5, 26, 18][5, 27, 19][5, 26, 19][5, 27, 20][5, 26, 20][5, 27, 21][5, 26, 21][5, 27, 22][5, 26, 22][5, 27, 23][5, 26, 23]
    MMCM0:DRP66[5, 27, 8][5, 26, 8][5, 27, 9][5, 26, 9][5, 27, 10][5, 26, 10][5, 27, 11][5, 26, 11][5, 27, 12][5, 26, 12][5, 27, 13][5, 26, 13][5, 27, 14][5, 26, 14][5, 27, 15][5, 26, 15]
    MMCM0:DRP67[5, 27, 0][5, 26, 0][5, 27, 1][5, 26, 1][5, 27, 2][5, 26, 2][5, 27, 3][5, 26, 3][5, 27, 4][5, 26, 4][5, 27, 5][5, 26, 5][5, 27, 6][5, 26, 6][5, 27, 7][5, 26, 7]
    MMCM0:DRP68[4, 27, 56][4, 26, 56][4, 27, 57][4, 26, 57][4, 27, 58][4, 26, 58][4, 27, 59][4, 26, 59][4, 27, 60][4, 26, 60][4, 27, 61][4, 26, 61][4, 27, 62][4, 26, 62][4, 27, 63][4, 26, 63]
    MMCM0:DRP69[4, 27, 48][4, 26, 48][4, 27, 49][4, 26, 49][4, 27, 50][4, 26, 50][4, 27, 51][4, 26, 51][4, 27, 52][4, 26, 52][4, 27, 53][4, 26, 53][4, 27, 54][4, 26, 54][4, 27, 55][4, 26, 55]
    MMCM0:DRP6A[4, 27, 40][4, 26, 40][4, 27, 41][4, 26, 41][4, 27, 42][4, 26, 42][4, 27, 43][4, 26, 43][4, 27, 44][4, 26, 44][4, 27, 45][4, 26, 45][4, 27, 46][4, 26, 46][4, 27, 47][4, 26, 47]
    MMCM0:DRP6B[4, 27, 32][4, 26, 32][4, 27, 33][4, 26, 33][4, 27, 34][4, 26, 34][4, 27, 35][4, 26, 35][4, 27, 36][4, 26, 36][4, 27, 37][4, 26, 37][4, 27, 38][4, 26, 38][4, 27, 39][4, 26, 39]
    MMCM0:DRP6C[4, 27, 24][4, 26, 24][4, 27, 25][4, 26, 25][4, 27, 26][4, 26, 26][4, 27, 27][4, 26, 27][4, 27, 28][4, 26, 28][4, 27, 29][4, 26, 29][4, 27, 30][4, 26, 30][4, 27, 31][4, 26, 31]
    MMCM0:DRP6D[4, 27, 16][4, 26, 16][4, 27, 17][4, 26, 17][4, 27, 18][4, 26, 18][4, 27, 19][4, 26, 19][4, 27, 20][4, 26, 20][4, 27, 21][4, 26, 21][4, 27, 22][4, 26, 22][4, 27, 23][4, 26, 23]
    MMCM0:DRP6E[4, 27, 8][4, 26, 8][4, 27, 9][4, 26, 9][4, 27, 10][4, 26, 10][4, 27, 11][4, 26, 11][4, 27, 12][4, 26, 12][4, 27, 13][4, 26, 13][4, 27, 14][4, 26, 14][4, 27, 15][4, 26, 15]
    MMCM0:DRP6F[4, 27, 0][4, 26, 0][4, 27, 1][4, 26, 1][4, 27, 2][4, 26, 2][4, 27, 3][4, 26, 3][4, 27, 4][4, 26, 4][4, 27, 5][4, 26, 5][4, 27, 6][4, 26, 6][4, 27, 7][4, 26, 7]
    MMCM0:DRP70[3, 27, 56][3, 26, 56][3, 27, 57][3, 26, 57][3, 27, 58][3, 26, 58][3, 27, 59][3, 26, 59][3, 27, 60][3, 26, 60][3, 27, 61][3, 26, 61][3, 27, 62][3, 26, 62][3, 27, 63][3, 26, 63]
    MMCM0:DRP71[3, 27, 48][3, 26, 48][3, 27, 49][3, 26, 49][3, 27, 50][3, 26, 50][3, 27, 51][3, 26, 51][3, 27, 52][3, 26, 52][3, 27, 53][3, 26, 53][3, 27, 54][3, 26, 54][3, 27, 55][3, 26, 55]
    MMCM0:DRP72[3, 27, 40][3, 26, 40][3, 27, 41][3, 26, 41][3, 27, 42][3, 26, 42][3, 27, 43][3, 26, 43][3, 27, 44][3, 26, 44][3, 27, 45][3, 26, 45][3, 27, 46][3, 26, 46][3, 27, 47][3, 26, 47]
    MMCM0:DRP73[3, 27, 32][3, 26, 32][3, 27, 33][3, 26, 33][3, 27, 34][3, 26, 34][3, 27, 35][3, 26, 35][3, 27, 36][3, 26, 36][3, 27, 37][3, 26, 37][3, 27, 38][3, 26, 38][3, 27, 39][3, 26, 39]
    MMCM0:DRP74[3, 27, 24][3, 26, 24][3, 27, 25][3, 26, 25][3, 27, 26][3, 26, 26][3, 27, 27][3, 26, 27][3, 27, 28][3, 26, 28][3, 27, 29][3, 26, 29][3, 27, 30][3, 26, 30][3, 27, 31][3, 26, 31]
    MMCM0:DRP75[3, 27, 16][3, 26, 16][3, 27, 17][3, 26, 17][3, 27, 18][3, 26, 18][3, 27, 19][3, 26, 19][3, 27, 20][3, 26, 20][3, 27, 21][3, 26, 21][3, 27, 22][3, 26, 22][3, 27, 23][3, 26, 23]
    MMCM0:DRP76[3, 27, 8][3, 26, 8][3, 27, 9][3, 26, 9][3, 27, 10][3, 26, 10][3, 27, 11][3, 26, 11][3, 27, 12][3, 26, 12][3, 27, 13][3, 26, 13][3, 27, 14][3, 26, 14][3, 27, 15][3, 26, 15]
    MMCM0:DRP77[3, 27, 0][3, 26, 0][3, 27, 1][3, 26, 1][3, 27, 2][3, 26, 2][3, 27, 3][3, 26, 3][3, 27, 4][3, 26, 4][3, 27, 5][3, 26, 5][3, 27, 6][3, 26, 6][3, 27, 7][3, 26, 7]
    MMCM0:DRP78[2, 27, 56][2, 26, 56][2, 27, 57][2, 26, 57][2, 27, 58][2, 26, 58][2, 27, 59][2, 26, 59][2, 27, 60][2, 26, 60][2, 27, 61][2, 26, 61][2, 27, 62][2, 26, 62][2, 27, 63][2, 26, 63]
    MMCM0:DRP79[2, 27, 48][2, 26, 48][2, 27, 49][2, 26, 49][2, 27, 50][2, 26, 50][2, 27, 51][2, 26, 51][2, 27, 52][2, 26, 52][2, 27, 53][2, 26, 53][2, 27, 54][2, 26, 54][2, 27, 55][2, 26, 55]
    MMCM0:DRP7A[2, 27, 40][2, 26, 40][2, 27, 41][2, 26, 41][2, 27, 42][2, 26, 42][2, 27, 43][2, 26, 43][2, 27, 44][2, 26, 44][2, 27, 45][2, 26, 45][2, 27, 46][2, 26, 46][2, 27, 47][2, 26, 47]
    MMCM0:DRP7B[2, 27, 32][2, 26, 32][2, 27, 33][2, 26, 33][2, 27, 34][2, 26, 34][2, 27, 35][2, 26, 35][2, 27, 36][2, 26, 36][2, 27, 37][2, 26, 37][2, 27, 38][2, 26, 38][2, 27, 39][2, 26, 39]
    MMCM0:DRP7C[2, 27, 24][2, 26, 24][2, 27, 25][2, 26, 25][2, 27, 26][2, 26, 26][2, 27, 27][2, 26, 27][2, 27, 28][2, 26, 28][2, 27, 29][2, 26, 29][2, 27, 30][2, 26, 30][2, 27, 31][2, 26, 31]
    MMCM0:DRP7D[2, 27, 16][2, 26, 16][2, 27, 17][2, 26, 17][2, 27, 18][2, 26, 18][2, 27, 19][2, 26, 19][2, 27, 20][2, 26, 20][2, 27, 21][2, 26, 21][2, 27, 22][2, 26, 22][2, 27, 23][2, 26, 23]
    MMCM0:DRP7E[2, 27, 8][2, 26, 8][2, 27, 9][2, 26, 9][2, 27, 10][2, 26, 10][2, 27, 11][2, 26, 11][2, 27, 12][2, 26, 12][2, 27, 13][2, 26, 13][2, 27, 14][2, 26, 14][2, 27, 15][2, 26, 15]
    MMCM0:DRP7F[2, 27, 0][2, 26, 0][2, 27, 1][2, 26, 1][2, 27, 2][2, 26, 2][2, 27, 3][2, 26, 3][2, 27, 4][2, 26, 4][2, 27, 5][2, 26, 5][2, 27, 6][2, 26, 6][2, 27, 7][2, 26, 7]
    MMCM1:CONTROL_0[36, 27, 55][36, 26, 55][36, 27, 54][36, 26, 54][36, 27, 53][36, 26, 53][36, 27, 52][36, 26, 52][36, 27, 51][36, 26, 51][36, 27, 50][36, 26, 50][36, 27, 49][36, 26, 49][36, 27, 48][36, 26, 48]
    MMCM1:CONTROL_1[36, 27, 63][36, 26, 63][36, 27, 62][36, 26, 62][36, 27, 61][36, 26, 61][36, 27, 60][36, 26, 60][36, 27, 59][36, 26, 59][36, 27, 58][36, 26, 58][36, 27, 57][36, 26, 57][36, 27, 56][36, 26, 56]
    MMCM1:CONTROL_2[37, 27, 7][37, 26, 7][37, 27, 6][37, 26, 6][37, 27, 5][37, 26, 5][37, 27, 4][37, 26, 4][37, 27, 3][37, 26, 3][37, 27, 2][37, 26, 2][37, 27, 1][37, 26, 1][37, 27, 0][37, 26, 0]
    MMCM1:CONTROL_3[37, 27, 15][37, 26, 15][37, 27, 14][37, 26, 14][37, 27, 13][37, 26, 13][37, 27, 12][37, 26, 12][37, 27, 11][37, 26, 11][37, 27, 10][37, 26, 10][37, 27, 9][37, 26, 9][37, 27, 8][37, 26, 8]
    MMCM1:CONTROL_4[37, 27, 23][37, 26, 23][37, 27, 22][37, 26, 22][37, 27, 21][37, 26, 21][37, 27, 20][37, 26, 20][37, 27, 19][37, 26, 19][37, 27, 18][37, 26, 18][37, 27, 17][37, 26, 17][37, 27, 16][37, 26, 16]
    MMCM1:CONTROL_5[37, 27, 31][37, 26, 31][37, 27, 30][37, 26, 30][37, 27, 29][37, 26, 29][37, 27, 28][37, 26, 28][37, 27, 27][37, 26, 27][37, 27, 26][37, 26, 26][37, 27, 25][37, 26, 25][37, 27, 24][37, 26, 24]
    MMCM1:DRP00[22, 27, 7][22, 26, 7][22, 27, 6][22, 26, 6][22, 27, 5][22, 26, 5][22, 27, 4][22, 26, 4][22, 27, 3][22, 26, 3][22, 27, 2][22, 26, 2][22, 27, 1][22, 26, 1][22, 27, 0][22, 26, 0]
    MMCM1:DRP01[22, 27, 15][22, 26, 15][22, 27, 14][22, 26, 14][22, 27, 13][22, 26, 13][22, 27, 12][22, 26, 12][22, 27, 11][22, 26, 11][22, 27, 10][22, 26, 10][22, 27, 9][22, 26, 9][22, 27, 8][22, 26, 8]
    MMCM1:DRP02[22, 27, 23][22, 26, 23][22, 27, 22][22, 26, 22][22, 27, 21][22, 26, 21][22, 27, 20][22, 26, 20][22, 27, 19][22, 26, 19][22, 27, 18][22, 26, 18][22, 27, 17][22, 26, 17][22, 27, 16][22, 26, 16]
    MMCM1:DRP03[22, 27, 31][22, 26, 31][22, 27, 30][22, 26, 30][22, 27, 29][22, 26, 29][22, 27, 28][22, 26, 28][22, 27, 27][22, 26, 27][22, 27, 26][22, 26, 26][22, 27, 25][22, 26, 25][22, 27, 24][22, 26, 24]
    MMCM1:DRP04[22, 27, 39][22, 26, 39][22, 27, 38][22, 26, 38][22, 27, 37][22, 26, 37][22, 27, 36][22, 26, 36][22, 27, 35][22, 26, 35][22, 27, 34][22, 26, 34][22, 27, 33][22, 26, 33][22, 27, 32][22, 26, 32]
    MMCM1:DRP05[22, 27, 47][22, 26, 47][22, 27, 46][22, 26, 46][22, 27, 45][22, 26, 45][22, 27, 44][22, 26, 44][22, 27, 43][22, 26, 43][22, 27, 42][22, 26, 42][22, 27, 41][22, 26, 41][22, 27, 40][22, 26, 40]
    MMCM1:DRP06[22, 27, 55][22, 26, 55][22, 27, 54][22, 26, 54][22, 27, 53][22, 26, 53][22, 27, 52][22, 26, 52][22, 27, 51][22, 26, 51][22, 27, 50][22, 26, 50][22, 27, 49][22, 26, 49][22, 27, 48][22, 26, 48]
    MMCM1:DRP07[22, 27, 63][22, 26, 63][22, 27, 62][22, 26, 62][22, 27, 61][22, 26, 61][22, 27, 60][22, 26, 60][22, 27, 59][22, 26, 59][22, 27, 58][22, 26, 58][22, 27, 57][22, 26, 57][22, 27, 56][22, 26, 56]
    MMCM1:DRP08[23, 27, 7][23, 26, 7][23, 27, 6][23, 26, 6][23, 27, 5][23, 26, 5][23, 27, 4][23, 26, 4][23, 27, 3][23, 26, 3][23, 27, 2][23, 26, 2][23, 27, 1][23, 26, 1][23, 27, 0][23, 26, 0]
    MMCM1:DRP09[23, 27, 15][23, 26, 15][23, 27, 14][23, 26, 14][23, 27, 13][23, 26, 13][23, 27, 12][23, 26, 12][23, 27, 11][23, 26, 11][23, 27, 10][23, 26, 10][23, 27, 9][23, 26, 9][23, 27, 8][23, 26, 8]
    MMCM1:DRP0A[23, 27, 23][23, 26, 23][23, 27, 22][23, 26, 22][23, 27, 21][23, 26, 21][23, 27, 20][23, 26, 20][23, 27, 19][23, 26, 19][23, 27, 18][23, 26, 18][23, 27, 17][23, 26, 17][23, 27, 16][23, 26, 16]
    MMCM1:DRP0B[23, 27, 31][23, 26, 31][23, 27, 30][23, 26, 30][23, 27, 29][23, 26, 29][23, 27, 28][23, 26, 28][23, 27, 27][23, 26, 27][23, 27, 26][23, 26, 26][23, 27, 25][23, 26, 25][23, 27, 24][23, 26, 24]
    MMCM1:DRP0C[23, 27, 39][23, 26, 39][23, 27, 38][23, 26, 38][23, 27, 37][23, 26, 37][23, 27, 36][23, 26, 36][23, 27, 35][23, 26, 35][23, 27, 34][23, 26, 34][23, 27, 33][23, 26, 33][23, 27, 32][23, 26, 32]
    MMCM1:DRP0D[23, 27, 47][23, 26, 47][23, 27, 46][23, 26, 46][23, 27, 45][23, 26, 45][23, 27, 44][23, 26, 44][23, 27, 43][23, 26, 43][23, 27, 42][23, 26, 42][23, 27, 41][23, 26, 41][23, 27, 40][23, 26, 40]
    MMCM1:DRP0E[23, 27, 55][23, 26, 55][23, 27, 54][23, 26, 54][23, 27, 53][23, 26, 53][23, 27, 52][23, 26, 52][23, 27, 51][23, 26, 51][23, 27, 50][23, 26, 50][23, 27, 49][23, 26, 49][23, 27, 48][23, 26, 48]
    MMCM1:DRP0F[23, 27, 63][23, 26, 63][23, 27, 62][23, 26, 62][23, 27, 61][23, 26, 61][23, 27, 60][23, 26, 60][23, 27, 59][23, 26, 59][23, 27, 58][23, 26, 58][23, 27, 57][23, 26, 57][23, 27, 56][23, 26, 56]
    MMCM1:DRP10[24, 27, 7][24, 26, 7][24, 27, 6][24, 26, 6][24, 27, 5][24, 26, 5][24, 27, 4][24, 26, 4][24, 27, 3][24, 26, 3][24, 27, 2][24, 26, 2][24, 27, 1][24, 26, 1][24, 27, 0][24, 26, 0]
    MMCM1:DRP11[24, 27, 15][24, 26, 15][24, 27, 14][24, 26, 14][24, 27, 13][24, 26, 13][24, 27, 12][24, 26, 12][24, 27, 11][24, 26, 11][24, 27, 10][24, 26, 10][24, 27, 9][24, 26, 9][24, 27, 8][24, 26, 8]
    MMCM1:DRP12[24, 27, 23][24, 26, 23][24, 27, 22][24, 26, 22][24, 27, 21][24, 26, 21][24, 27, 20][24, 26, 20][24, 27, 19][24, 26, 19][24, 27, 18][24, 26, 18][24, 27, 17][24, 26, 17][24, 27, 16][24, 26, 16]
    MMCM1:DRP13[24, 27, 31][24, 26, 31][24, 27, 30][24, 26, 30][24, 27, 29][24, 26, 29][24, 27, 28][24, 26, 28][24, 27, 27][24, 26, 27][24, 27, 26][24, 26, 26][24, 27, 25][24, 26, 25][24, 27, 24][24, 26, 24]
    MMCM1:DRP14[24, 27, 39][24, 26, 39][24, 27, 38][24, 26, 38][24, 27, 37][24, 26, 37][24, 27, 36][24, 26, 36][24, 27, 35][24, 26, 35][24, 27, 34][24, 26, 34][24, 27, 33][24, 26, 33][24, 27, 32][24, 26, 32]
    MMCM1:DRP15[24, 27, 47][24, 26, 47][24, 27, 46][24, 26, 46][24, 27, 45][24, 26, 45][24, 27, 44][24, 26, 44][24, 27, 43][24, 26, 43][24, 27, 42][24, 26, 42][24, 27, 41][24, 26, 41][24, 27, 40][24, 26, 40]
    MMCM1:DRP16[24, 27, 55][24, 26, 55][24, 27, 54][24, 26, 54][24, 27, 53][24, 26, 53][24, 27, 52][24, 26, 52][24, 27, 51][24, 26, 51][24, 27, 50][24, 26, 50][24, 27, 49][24, 26, 49][24, 27, 48][24, 26, 48]
    MMCM1:DRP17[24, 27, 63][24, 26, 63][24, 27, 62][24, 26, 62][24, 27, 61][24, 26, 61][24, 27, 60][24, 26, 60][24, 27, 59][24, 26, 59][24, 27, 58][24, 26, 58][24, 27, 57][24, 26, 57][24, 27, 56][24, 26, 56]
    MMCM1:DRP18[25, 27, 7][25, 26, 7][25, 27, 6][25, 26, 6][25, 27, 5][25, 26, 5][25, 27, 4][25, 26, 4][25, 27, 3][25, 26, 3][25, 27, 2][25, 26, 2][25, 27, 1][25, 26, 1][25, 27, 0][25, 26, 0]
    MMCM1:DRP19[25, 27, 15][25, 26, 15][25, 27, 14][25, 26, 14][25, 27, 13][25, 26, 13][25, 27, 12][25, 26, 12][25, 27, 11][25, 26, 11][25, 27, 10][25, 26, 10][25, 27, 9][25, 26, 9][25, 27, 8][25, 26, 8]
    MMCM1:DRP1A[25, 27, 23][25, 26, 23][25, 27, 22][25, 26, 22][25, 27, 21][25, 26, 21][25, 27, 20][25, 26, 20][25, 27, 19][25, 26, 19][25, 27, 18][25, 26, 18][25, 27, 17][25, 26, 17][25, 27, 16][25, 26, 16]
    MMCM1:DRP1B[25, 27, 31][25, 26, 31][25, 27, 30][25, 26, 30][25, 27, 29][25, 26, 29][25, 27, 28][25, 26, 28][25, 27, 27][25, 26, 27][25, 27, 26][25, 26, 26][25, 27, 25][25, 26, 25][25, 27, 24][25, 26, 24]
    MMCM1:DRP1C[25, 27, 39][25, 26, 39][25, 27, 38][25, 26, 38][25, 27, 37][25, 26, 37][25, 27, 36][25, 26, 36][25, 27, 35][25, 26, 35][25, 27, 34][25, 26, 34][25, 27, 33][25, 26, 33][25, 27, 32][25, 26, 32]
    MMCM1:DRP1D[25, 27, 47][25, 26, 47][25, 27, 46][25, 26, 46][25, 27, 45][25, 26, 45][25, 27, 44][25, 26, 44][25, 27, 43][25, 26, 43][25, 27, 42][25, 26, 42][25, 27, 41][25, 26, 41][25, 27, 40][25, 26, 40]
    MMCM1:DRP1E[25, 27, 55][25, 26, 55][25, 27, 54][25, 26, 54][25, 27, 53][25, 26, 53][25, 27, 52][25, 26, 52][25, 27, 51][25, 26, 51][25, 27, 50][25, 26, 50][25, 27, 49][25, 26, 49][25, 27, 48][25, 26, 48]
    MMCM1:DRP1F[25, 27, 63][25, 26, 63][25, 27, 62][25, 26, 62][25, 27, 61][25, 26, 61][25, 27, 60][25, 26, 60][25, 27, 59][25, 26, 59][25, 27, 58][25, 26, 58][25, 27, 57][25, 26, 57][25, 27, 56][25, 26, 56]
    MMCM1:DRP20[26, 27, 7][26, 26, 7][26, 27, 6][26, 26, 6][26, 27, 5][26, 26, 5][26, 27, 4][26, 26, 4][26, 27, 3][26, 26, 3][26, 27, 2][26, 26, 2][26, 27, 1][26, 26, 1][26, 27, 0][26, 26, 0]
    MMCM1:DRP21[26, 27, 15][26, 26, 15][26, 27, 14][26, 26, 14][26, 27, 13][26, 26, 13][26, 27, 12][26, 26, 12][26, 27, 11][26, 26, 11][26, 27, 10][26, 26, 10][26, 27, 9][26, 26, 9][26, 27, 8][26, 26, 8]
    MMCM1:DRP22[26, 27, 23][26, 26, 23][26, 27, 22][26, 26, 22][26, 27, 21][26, 26, 21][26, 27, 20][26, 26, 20][26, 27, 19][26, 26, 19][26, 27, 18][26, 26, 18][26, 27, 17][26, 26, 17][26, 27, 16][26, 26, 16]
    MMCM1:DRP23[26, 27, 31][26, 26, 31][26, 27, 30][26, 26, 30][26, 27, 29][26, 26, 29][26, 27, 28][26, 26, 28][26, 27, 27][26, 26, 27][26, 27, 26][26, 26, 26][26, 27, 25][26, 26, 25][26, 27, 24][26, 26, 24]
    MMCM1:DRP24[26, 27, 39][26, 26, 39][26, 27, 38][26, 26, 38][26, 27, 37][26, 26, 37][26, 27, 36][26, 26, 36][26, 27, 35][26, 26, 35][26, 27, 34][26, 26, 34][26, 27, 33][26, 26, 33][26, 27, 32][26, 26, 32]
    MMCM1:DRP25[26, 27, 47][26, 26, 47][26, 27, 46][26, 26, 46][26, 27, 45][26, 26, 45][26, 27, 44][26, 26, 44][26, 27, 43][26, 26, 43][26, 27, 42][26, 26, 42][26, 27, 41][26, 26, 41][26, 27, 40][26, 26, 40]
    MMCM1:DRP26[26, 27, 55][26, 26, 55][26, 27, 54][26, 26, 54][26, 27, 53][26, 26, 53][26, 27, 52][26, 26, 52][26, 27, 51][26, 26, 51][26, 27, 50][26, 26, 50][26, 27, 49][26, 26, 49][26, 27, 48][26, 26, 48]
    MMCM1:DRP27[26, 27, 63][26, 26, 63][26, 27, 62][26, 26, 62][26, 27, 61][26, 26, 61][26, 27, 60][26, 26, 60][26, 27, 59][26, 26, 59][26, 27, 58][26, 26, 58][26, 27, 57][26, 26, 57][26, 27, 56][26, 26, 56]
    MMCM1:DRP28[27, 27, 7][27, 26, 7][27, 27, 6][27, 26, 6][27, 27, 5][27, 26, 5][27, 27, 4][27, 26, 4][27, 27, 3][27, 26, 3][27, 27, 2][27, 26, 2][27, 27, 1][27, 26, 1][27, 27, 0][27, 26, 0]
    MMCM1:DRP29[27, 27, 15][27, 26, 15][27, 27, 14][27, 26, 14][27, 27, 13][27, 26, 13][27, 27, 12][27, 26, 12][27, 27, 11][27, 26, 11][27, 27, 10][27, 26, 10][27, 27, 9][27, 26, 9][27, 27, 8][27, 26, 8]
    MMCM1:DRP2A[27, 27, 23][27, 26, 23][27, 27, 22][27, 26, 22][27, 27, 21][27, 26, 21][27, 27, 20][27, 26, 20][27, 27, 19][27, 26, 19][27, 27, 18][27, 26, 18][27, 27, 17][27, 26, 17][27, 27, 16][27, 26, 16]
    MMCM1:DRP2B[27, 27, 31][27, 26, 31][27, 27, 30][27, 26, 30][27, 27, 29][27, 26, 29][27, 27, 28][27, 26, 28][27, 27, 27][27, 26, 27][27, 27, 26][27, 26, 26][27, 27, 25][27, 26, 25][27, 27, 24][27, 26, 24]
    MMCM1:DRP2C[27, 27, 39][27, 26, 39][27, 27, 38][27, 26, 38][27, 27, 37][27, 26, 37][27, 27, 36][27, 26, 36][27, 27, 35][27, 26, 35][27, 27, 34][27, 26, 34][27, 27, 33][27, 26, 33][27, 27, 32][27, 26, 32]
    MMCM1:DRP2D[27, 27, 47][27, 26, 47][27, 27, 46][27, 26, 46][27, 27, 45][27, 26, 45][27, 27, 44][27, 26, 44][27, 27, 43][27, 26, 43][27, 27, 42][27, 26, 42][27, 27, 41][27, 26, 41][27, 27, 40][27, 26, 40]
    MMCM1:DRP2E[27, 27, 55][27, 26, 55][27, 27, 54][27, 26, 54][27, 27, 53][27, 26, 53][27, 27, 52][27, 26, 52][27, 27, 51][27, 26, 51][27, 27, 50][27, 26, 50][27, 27, 49][27, 26, 49][27, 27, 48][27, 26, 48]
    MMCM1:DRP2F[27, 27, 63][27, 26, 63][27, 27, 62][27, 26, 62][27, 27, 61][27, 26, 61][27, 27, 60][27, 26, 60][27, 27, 59][27, 26, 59][27, 27, 58][27, 26, 58][27, 27, 57][27, 26, 57][27, 27, 56][27, 26, 56]
    MMCM1:DRP30[28, 27, 7][28, 26, 7][28, 27, 6][28, 26, 6][28, 27, 5][28, 26, 5][28, 27, 4][28, 26, 4][28, 27, 3][28, 26, 3][28, 27, 2][28, 26, 2][28, 27, 1][28, 26, 1][28, 27, 0][28, 26, 0]
    MMCM1:DRP31[28, 27, 15][28, 26, 15][28, 27, 14][28, 26, 14][28, 27, 13][28, 26, 13][28, 27, 12][28, 26, 12][28, 27, 11][28, 26, 11][28, 27, 10][28, 26, 10][28, 27, 9][28, 26, 9][28, 27, 8][28, 26, 8]
    MMCM1:DRP32[28, 27, 23][28, 26, 23][28, 27, 22][28, 26, 22][28, 27, 21][28, 26, 21][28, 27, 20][28, 26, 20][28, 27, 19][28, 26, 19][28, 27, 18][28, 26, 18][28, 27, 17][28, 26, 17][28, 27, 16][28, 26, 16]
    MMCM1:DRP33[28, 27, 31][28, 26, 31][28, 27, 30][28, 26, 30][28, 27, 29][28, 26, 29][28, 27, 28][28, 26, 28][28, 27, 27][28, 26, 27][28, 27, 26][28, 26, 26][28, 27, 25][28, 26, 25][28, 27, 24][28, 26, 24]
    MMCM1:DRP34[28, 27, 39][28, 26, 39][28, 27, 38][28, 26, 38][28, 27, 37][28, 26, 37][28, 27, 36][28, 26, 36][28, 27, 35][28, 26, 35][28, 27, 34][28, 26, 34][28, 27, 33][28, 26, 33][28, 27, 32][28, 26, 32]
    MMCM1:DRP35[28, 27, 47][28, 26, 47][28, 27, 46][28, 26, 46][28, 27, 45][28, 26, 45][28, 27, 44][28, 26, 44][28, 27, 43][28, 26, 43][28, 27, 42][28, 26, 42][28, 27, 41][28, 26, 41][28, 27, 40][28, 26, 40]
    MMCM1:DRP36[28, 27, 55][28, 26, 55][28, 27, 54][28, 26, 54][28, 27, 53][28, 26, 53][28, 27, 52][28, 26, 52][28, 27, 51][28, 26, 51][28, 27, 50][28, 26, 50][28, 27, 49][28, 26, 49][28, 27, 48][28, 26, 48]
    MMCM1:DRP37[28, 27, 63][28, 26, 63][28, 27, 62][28, 26, 62][28, 27, 61][28, 26, 61][28, 27, 60][28, 26, 60][28, 27, 59][28, 26, 59][28, 27, 58][28, 26, 58][28, 27, 57][28, 26, 57][28, 27, 56][28, 26, 56]
    MMCM1:DRP38[29, 27, 7][29, 26, 7][29, 27, 6][29, 26, 6][29, 27, 5][29, 26, 5][29, 27, 4][29, 26, 4][29, 27, 3][29, 26, 3][29, 27, 2][29, 26, 2][29, 27, 1][29, 26, 1][29, 27, 0][29, 26, 0]
    MMCM1:DRP39[29, 27, 15][29, 26, 15][29, 27, 14][29, 26, 14][29, 27, 13][29, 26, 13][29, 27, 12][29, 26, 12][29, 27, 11][29, 26, 11][29, 27, 10][29, 26, 10][29, 27, 9][29, 26, 9][29, 27, 8][29, 26, 8]
    MMCM1:DRP3A[29, 27, 23][29, 26, 23][29, 27, 22][29, 26, 22][29, 27, 21][29, 26, 21][29, 27, 20][29, 26, 20][29, 27, 19][29, 26, 19][29, 27, 18][29, 26, 18][29, 27, 17][29, 26, 17][29, 27, 16][29, 26, 16]
    MMCM1:DRP3B[29, 27, 31][29, 26, 31][29, 27, 30][29, 26, 30][29, 27, 29][29, 26, 29][29, 27, 28][29, 26, 28][29, 27, 27][29, 26, 27][29, 27, 26][29, 26, 26][29, 27, 25][29, 26, 25][29, 27, 24][29, 26, 24]
    MMCM1:DRP3C[29, 27, 39][29, 26, 39][29, 27, 38][29, 26, 38][29, 27, 37][29, 26, 37][29, 27, 36][29, 26, 36][29, 27, 35][29, 26, 35][29, 27, 34][29, 26, 34][29, 27, 33][29, 26, 33][29, 27, 32][29, 26, 32]
    MMCM1:DRP3D[29, 27, 47][29, 26, 47][29, 27, 46][29, 26, 46][29, 27, 45][29, 26, 45][29, 27, 44][29, 26, 44][29, 27, 43][29, 26, 43][29, 27, 42][29, 26, 42][29, 27, 41][29, 26, 41][29, 27, 40][29, 26, 40]
    MMCM1:DRP3E[29, 27, 55][29, 26, 55][29, 27, 54][29, 26, 54][29, 27, 53][29, 26, 53][29, 27, 52][29, 26, 52][29, 27, 51][29, 26, 51][29, 27, 50][29, 26, 50][29, 27, 49][29, 26, 49][29, 27, 48][29, 26, 48]
    MMCM1:DRP3F[29, 27, 63][29, 26, 63][29, 27, 62][29, 26, 62][29, 27, 61][29, 26, 61][29, 27, 60][29, 26, 60][29, 27, 59][29, 26, 59][29, 27, 58][29, 26, 58][29, 27, 57][29, 26, 57][29, 27, 56][29, 26, 56]
    MMCM1:DRP40[30, 27, 7][30, 26, 7][30, 27, 6][30, 26, 6][30, 27, 5][30, 26, 5][30, 27, 4][30, 26, 4][30, 27, 3][30, 26, 3][30, 27, 2][30, 26, 2][30, 27, 1][30, 26, 1][30, 27, 0][30, 26, 0]
    MMCM1:DRP41[30, 27, 15][30, 26, 15][30, 27, 14][30, 26, 14][30, 27, 13][30, 26, 13][30, 27, 12][30, 26, 12][30, 27, 11][30, 26, 11][30, 27, 10][30, 26, 10][30, 27, 9][30, 26, 9][30, 27, 8][30, 26, 8]
    MMCM1:DRP42[30, 27, 23][30, 26, 23][30, 27, 22][30, 26, 22][30, 27, 21][30, 26, 21][30, 27, 20][30, 26, 20][30, 27, 19][30, 26, 19][30, 27, 18][30, 26, 18][30, 27, 17][30, 26, 17][30, 27, 16][30, 26, 16]
    MMCM1:DRP43[30, 27, 31][30, 26, 31][30, 27, 30][30, 26, 30][30, 27, 29][30, 26, 29][30, 27, 28][30, 26, 28][30, 27, 27][30, 26, 27][30, 27, 26][30, 26, 26][30, 27, 25][30, 26, 25][30, 27, 24][30, 26, 24]
    MMCM1:DRP44[30, 27, 39][30, 26, 39][30, 27, 38][30, 26, 38][30, 27, 37][30, 26, 37][30, 27, 36][30, 26, 36][30, 27, 35][30, 26, 35][30, 27, 34][30, 26, 34][30, 27, 33][30, 26, 33][30, 27, 32][30, 26, 32]
    MMCM1:DRP45[30, 27, 47][30, 26, 47][30, 27, 46][30, 26, 46][30, 27, 45][30, 26, 45][30, 27, 44][30, 26, 44][30, 27, 43][30, 26, 43][30, 27, 42][30, 26, 42][30, 27, 41][30, 26, 41][30, 27, 40][30, 26, 40]
    MMCM1:DRP46[30, 27, 55][30, 26, 55][30, 27, 54][30, 26, 54][30, 27, 53][30, 26, 53][30, 27, 52][30, 26, 52][30, 27, 51][30, 26, 51][30, 27, 50][30, 26, 50][30, 27, 49][30, 26, 49][30, 27, 48][30, 26, 48]
    MMCM1:DRP47[30, 27, 63][30, 26, 63][30, 27, 62][30, 26, 62][30, 27, 61][30, 26, 61][30, 27, 60][30, 26, 60][30, 27, 59][30, 26, 59][30, 27, 58][30, 26, 58][30, 27, 57][30, 26, 57][30, 27, 56][30, 26, 56]
    MMCM1:DRP48[31, 27, 7][31, 26, 7][31, 27, 6][31, 26, 6][31, 27, 5][31, 26, 5][31, 27, 4][31, 26, 4][31, 27, 3][31, 26, 3][31, 27, 2][31, 26, 2][31, 27, 1][31, 26, 1][31, 27, 0][31, 26, 0]
    MMCM1:DRP49[31, 27, 15][31, 26, 15][31, 27, 14][31, 26, 14][31, 27, 13][31, 26, 13][31, 27, 12][31, 26, 12][31, 27, 11][31, 26, 11][31, 27, 10][31, 26, 10][31, 27, 9][31, 26, 9][31, 27, 8][31, 26, 8]
    MMCM1:DRP4A[31, 27, 23][31, 26, 23][31, 27, 22][31, 26, 22][31, 27, 21][31, 26, 21][31, 27, 20][31, 26, 20][31, 27, 19][31, 26, 19][31, 27, 18][31, 26, 18][31, 27, 17][31, 26, 17][31, 27, 16][31, 26, 16]
    MMCM1:DRP4B[31, 27, 31][31, 26, 31][31, 27, 30][31, 26, 30][31, 27, 29][31, 26, 29][31, 27, 28][31, 26, 28][31, 27, 27][31, 26, 27][31, 27, 26][31, 26, 26][31, 27, 25][31, 26, 25][31, 27, 24][31, 26, 24]
    MMCM1:DRP4C[31, 27, 39][31, 26, 39][31, 27, 38][31, 26, 38][31, 27, 37][31, 26, 37][31, 27, 36][31, 26, 36][31, 27, 35][31, 26, 35][31, 27, 34][31, 26, 34][31, 27, 33][31, 26, 33][31, 27, 32][31, 26, 32]
    MMCM1:DRP4D[31, 27, 47][31, 26, 47][31, 27, 46][31, 26, 46][31, 27, 45][31, 26, 45][31, 27, 44][31, 26, 44][31, 27, 43][31, 26, 43][31, 27, 42][31, 26, 42][31, 27, 41][31, 26, 41][31, 27, 40][31, 26, 40]
    MMCM1:DRP4E[31, 27, 55][31, 26, 55][31, 27, 54][31, 26, 54][31, 27, 53][31, 26, 53][31, 27, 52][31, 26, 52][31, 27, 51][31, 26, 51][31, 27, 50][31, 26, 50][31, 27, 49][31, 26, 49][31, 27, 48][31, 26, 48]
    MMCM1:DRP4F[31, 27, 63][31, 26, 63][31, 27, 62][31, 26, 62][31, 27, 61][31, 26, 61][31, 27, 60][31, 26, 60][31, 27, 59][31, 26, 59][31, 27, 58][31, 26, 58][31, 27, 57][31, 26, 57][31, 27, 56][31, 26, 56]
    MMCM1:DRP50[32, 27, 7][32, 26, 7][32, 27, 6][32, 26, 6][32, 27, 5][32, 26, 5][32, 27, 4][32, 26, 4][32, 27, 3][32, 26, 3][32, 27, 2][32, 26, 2][32, 27, 1][32, 26, 1][32, 27, 0][32, 26, 0]
    MMCM1:DRP51[32, 27, 15][32, 26, 15][32, 27, 14][32, 26, 14][32, 27, 13][32, 26, 13][32, 27, 12][32, 26, 12][32, 27, 11][32, 26, 11][32, 27, 10][32, 26, 10][32, 27, 9][32, 26, 9][32, 27, 8][32, 26, 8]
    MMCM1:DRP52[32, 27, 23][32, 26, 23][32, 27, 22][32, 26, 22][32, 27, 21][32, 26, 21][32, 27, 20][32, 26, 20][32, 27, 19][32, 26, 19][32, 27, 18][32, 26, 18][32, 27, 17][32, 26, 17][32, 27, 16][32, 26, 16]
    MMCM1:DRP53[32, 27, 31][32, 26, 31][32, 27, 30][32, 26, 30][32, 27, 29][32, 26, 29][32, 27, 28][32, 26, 28][32, 27, 27][32, 26, 27][32, 27, 26][32, 26, 26][32, 27, 25][32, 26, 25][32, 27, 24][32, 26, 24]
    MMCM1:DRP54[32, 27, 39][32, 26, 39][32, 27, 38][32, 26, 38][32, 27, 37][32, 26, 37][32, 27, 36][32, 26, 36][32, 27, 35][32, 26, 35][32, 27, 34][32, 26, 34][32, 27, 33][32, 26, 33][32, 27, 32][32, 26, 32]
    MMCM1:DRP55[32, 27, 47][32, 26, 47][32, 27, 46][32, 26, 46][32, 27, 45][32, 26, 45][32, 27, 44][32, 26, 44][32, 27, 43][32, 26, 43][32, 27, 42][32, 26, 42][32, 27, 41][32, 26, 41][32, 27, 40][32, 26, 40]
    MMCM1:DRP56[32, 27, 55][32, 26, 55][32, 27, 54][32, 26, 54][32, 27, 53][32, 26, 53][32, 27, 52][32, 26, 52][32, 27, 51][32, 26, 51][32, 27, 50][32, 26, 50][32, 27, 49][32, 26, 49][32, 27, 48][32, 26, 48]
    MMCM1:DRP57[32, 27, 63][32, 26, 63][32, 27, 62][32, 26, 62][32, 27, 61][32, 26, 61][32, 27, 60][32, 26, 60][32, 27, 59][32, 26, 59][32, 27, 58][32, 26, 58][32, 27, 57][32, 26, 57][32, 27, 56][32, 26, 56]
    MMCM1:DRP58[33, 27, 7][33, 26, 7][33, 27, 6][33, 26, 6][33, 27, 5][33, 26, 5][33, 27, 4][33, 26, 4][33, 27, 3][33, 26, 3][33, 27, 2][33, 26, 2][33, 27, 1][33, 26, 1][33, 27, 0][33, 26, 0]
    MMCM1:DRP59[33, 27, 15][33, 26, 15][33, 27, 14][33, 26, 14][33, 27, 13][33, 26, 13][33, 27, 12][33, 26, 12][33, 27, 11][33, 26, 11][33, 27, 10][33, 26, 10][33, 27, 9][33, 26, 9][33, 27, 8][33, 26, 8]
    MMCM1:DRP5A[33, 27, 23][33, 26, 23][33, 27, 22][33, 26, 22][33, 27, 21][33, 26, 21][33, 27, 20][33, 26, 20][33, 27, 19][33, 26, 19][33, 27, 18][33, 26, 18][33, 27, 17][33, 26, 17][33, 27, 16][33, 26, 16]
    MMCM1:DRP5B[33, 27, 31][33, 26, 31][33, 27, 30][33, 26, 30][33, 27, 29][33, 26, 29][33, 27, 28][33, 26, 28][33, 27, 27][33, 26, 27][33, 27, 26][33, 26, 26][33, 27, 25][33, 26, 25][33, 27, 24][33, 26, 24]
    MMCM1:DRP5C[33, 27, 39][33, 26, 39][33, 27, 38][33, 26, 38][33, 27, 37][33, 26, 37][33, 27, 36][33, 26, 36][33, 27, 35][33, 26, 35][33, 27, 34][33, 26, 34][33, 27, 33][33, 26, 33][33, 27, 32][33, 26, 32]
    MMCM1:DRP5D[33, 27, 47][33, 26, 47][33, 27, 46][33, 26, 46][33, 27, 45][33, 26, 45][33, 27, 44][33, 26, 44][33, 27, 43][33, 26, 43][33, 27, 42][33, 26, 42][33, 27, 41][33, 26, 41][33, 27, 40][33, 26, 40]
    MMCM1:DRP5E[33, 27, 55][33, 26, 55][33, 27, 54][33, 26, 54][33, 27, 53][33, 26, 53][33, 27, 52][33, 26, 52][33, 27, 51][33, 26, 51][33, 27, 50][33, 26, 50][33, 27, 49][33, 26, 49][33, 27, 48][33, 26, 48]
    MMCM1:DRP5F[33, 27, 63][33, 26, 63][33, 27, 62][33, 26, 62][33, 27, 61][33, 26, 61][33, 27, 60][33, 26, 60][33, 27, 59][33, 26, 59][33, 27, 58][33, 26, 58][33, 27, 57][33, 26, 57][33, 27, 56][33, 26, 56]
    MMCM1:DRP60[34, 27, 7][34, 26, 7][34, 27, 6][34, 26, 6][34, 27, 5][34, 26, 5][34, 27, 4][34, 26, 4][34, 27, 3][34, 26, 3][34, 27, 2][34, 26, 2][34, 27, 1][34, 26, 1][34, 27, 0][34, 26, 0]
    MMCM1:DRP61[34, 27, 15][34, 26, 15][34, 27, 14][34, 26, 14][34, 27, 13][34, 26, 13][34, 27, 12][34, 26, 12][34, 27, 11][34, 26, 11][34, 27, 10][34, 26, 10][34, 27, 9][34, 26, 9][34, 27, 8][34, 26, 8]
    MMCM1:DRP62[34, 27, 23][34, 26, 23][34, 27, 22][34, 26, 22][34, 27, 21][34, 26, 21][34, 27, 20][34, 26, 20][34, 27, 19][34, 26, 19][34, 27, 18][34, 26, 18][34, 27, 17][34, 26, 17][34, 27, 16][34, 26, 16]
    MMCM1:DRP63[34, 27, 31][34, 26, 31][34, 27, 30][34, 26, 30][34, 27, 29][34, 26, 29][34, 27, 28][34, 26, 28][34, 27, 27][34, 26, 27][34, 27, 26][34, 26, 26][34, 27, 25][34, 26, 25][34, 27, 24][34, 26, 24]
    MMCM1:DRP64[34, 27, 39][34, 26, 39][34, 27, 38][34, 26, 38][34, 27, 37][34, 26, 37][34, 27, 36][34, 26, 36][34, 27, 35][34, 26, 35][34, 27, 34][34, 26, 34][34, 27, 33][34, 26, 33][34, 27, 32][34, 26, 32]
    MMCM1:DRP65[34, 27, 47][34, 26, 47][34, 27, 46][34, 26, 46][34, 27, 45][34, 26, 45][34, 27, 44][34, 26, 44][34, 27, 43][34, 26, 43][34, 27, 42][34, 26, 42][34, 27, 41][34, 26, 41][34, 27, 40][34, 26, 40]
    MMCM1:DRP66[34, 27, 55][34, 26, 55][34, 27, 54][34, 26, 54][34, 27, 53][34, 26, 53][34, 27, 52][34, 26, 52][34, 27, 51][34, 26, 51][34, 27, 50][34, 26, 50][34, 27, 49][34, 26, 49][34, 27, 48][34, 26, 48]
    MMCM1:DRP67[34, 27, 63][34, 26, 63][34, 27, 62][34, 26, 62][34, 27, 61][34, 26, 61][34, 27, 60][34, 26, 60][34, 27, 59][34, 26, 59][34, 27, 58][34, 26, 58][34, 27, 57][34, 26, 57][34, 27, 56][34, 26, 56]
    MMCM1:DRP68[35, 27, 7][35, 26, 7][35, 27, 6][35, 26, 6][35, 27, 5][35, 26, 5][35, 27, 4][35, 26, 4][35, 27, 3][35, 26, 3][35, 27, 2][35, 26, 2][35, 27, 1][35, 26, 1][35, 27, 0][35, 26, 0]
    MMCM1:DRP69[35, 27, 15][35, 26, 15][35, 27, 14][35, 26, 14][35, 27, 13][35, 26, 13][35, 27, 12][35, 26, 12][35, 27, 11][35, 26, 11][35, 27, 10][35, 26, 10][35, 27, 9][35, 26, 9][35, 27, 8][35, 26, 8]
    MMCM1:DRP6A[35, 27, 23][35, 26, 23][35, 27, 22][35, 26, 22][35, 27, 21][35, 26, 21][35, 27, 20][35, 26, 20][35, 27, 19][35, 26, 19][35, 27, 18][35, 26, 18][35, 27, 17][35, 26, 17][35, 27, 16][35, 26, 16]
    MMCM1:DRP6B[35, 27, 31][35, 26, 31][35, 27, 30][35, 26, 30][35, 27, 29][35, 26, 29][35, 27, 28][35, 26, 28][35, 27, 27][35, 26, 27][35, 27, 26][35, 26, 26][35, 27, 25][35, 26, 25][35, 27, 24][35, 26, 24]
    MMCM1:DRP6C[35, 27, 39][35, 26, 39][35, 27, 38][35, 26, 38][35, 27, 37][35, 26, 37][35, 27, 36][35, 26, 36][35, 27, 35][35, 26, 35][35, 27, 34][35, 26, 34][35, 27, 33][35, 26, 33][35, 27, 32][35, 26, 32]
    MMCM1:DRP6D[35, 27, 47][35, 26, 47][35, 27, 46][35, 26, 46][35, 27, 45][35, 26, 45][35, 27, 44][35, 26, 44][35, 27, 43][35, 26, 43][35, 27, 42][35, 26, 42][35, 27, 41][35, 26, 41][35, 27, 40][35, 26, 40]
    MMCM1:DRP6E[35, 27, 55][35, 26, 55][35, 27, 54][35, 26, 54][35, 27, 53][35, 26, 53][35, 27, 52][35, 26, 52][35, 27, 51][35, 26, 51][35, 27, 50][35, 26, 50][35, 27, 49][35, 26, 49][35, 27, 48][35, 26, 48]
    MMCM1:DRP6F[35, 27, 63][35, 26, 63][35, 27, 62][35, 26, 62][35, 27, 61][35, 26, 61][35, 27, 60][35, 26, 60][35, 27, 59][35, 26, 59][35, 27, 58][35, 26, 58][35, 27, 57][35, 26, 57][35, 27, 56][35, 26, 56]
    MMCM1:DRP70[36, 27, 7][36, 26, 7][36, 27, 6][36, 26, 6][36, 27, 5][36, 26, 5][36, 27, 4][36, 26, 4][36, 27, 3][36, 26, 3][36, 27, 2][36, 26, 2][36, 27, 1][36, 26, 1][36, 27, 0][36, 26, 0]
    MMCM1:DRP71[36, 27, 15][36, 26, 15][36, 27, 14][36, 26, 14][36, 27, 13][36, 26, 13][36, 27, 12][36, 26, 12][36, 27, 11][36, 26, 11][36, 27, 10][36, 26, 10][36, 27, 9][36, 26, 9][36, 27, 8][36, 26, 8]
    MMCM1:DRP72[36, 27, 23][36, 26, 23][36, 27, 22][36, 26, 22][36, 27, 21][36, 26, 21][36, 27, 20][36, 26, 20][36, 27, 19][36, 26, 19][36, 27, 18][36, 26, 18][36, 27, 17][36, 26, 17][36, 27, 16][36, 26, 16]
    MMCM1:DRP73[36, 27, 31][36, 26, 31][36, 27, 30][36, 26, 30][36, 27, 29][36, 26, 29][36, 27, 28][36, 26, 28][36, 27, 27][36, 26, 27][36, 27, 26][36, 26, 26][36, 27, 25][36, 26, 25][36, 27, 24][36, 26, 24]
    MMCM1:DRP74[36, 27, 39][36, 26, 39][36, 27, 38][36, 26, 38][36, 27, 37][36, 26, 37][36, 27, 36][36, 26, 36][36, 27, 35][36, 26, 35][36, 27, 34][36, 26, 34][36, 27, 33][36, 26, 33][36, 27, 32][36, 26, 32]
    MMCM1:DRP75[36, 27, 47][36, 26, 47][36, 27, 46][36, 26, 46][36, 27, 45][36, 26, 45][36, 27, 44][36, 26, 44][36, 27, 43][36, 26, 43][36, 27, 42][36, 26, 42][36, 27, 41][36, 26, 41][36, 27, 40][36, 26, 40]
    MMCM1:DRP76[36, 27, 55][36, 26, 55][36, 27, 54][36, 26, 54][36, 27, 53][36, 26, 53][36, 27, 52][36, 26, 52][36, 27, 51][36, 26, 51][36, 27, 50][36, 26, 50][36, 27, 49][36, 26, 49][36, 27, 48][36, 26, 48]
    MMCM1:DRP77[36, 27, 63][36, 26, 63][36, 27, 62][36, 26, 62][36, 27, 61][36, 26, 61][36, 27, 60][36, 26, 60][36, 27, 59][36, 26, 59][36, 27, 58][36, 26, 58][36, 27, 57][36, 26, 57][36, 27, 56][36, 26, 56]
    MMCM1:DRP78[37, 27, 7][37, 26, 7][37, 27, 6][37, 26, 6][37, 27, 5][37, 26, 5][37, 27, 4][37, 26, 4][37, 27, 3][37, 26, 3][37, 27, 2][37, 26, 2][37, 27, 1][37, 26, 1][37, 27, 0][37, 26, 0]
    MMCM1:DRP79[37, 27, 15][37, 26, 15][37, 27, 14][37, 26, 14][37, 27, 13][37, 26, 13][37, 27, 12][37, 26, 12][37, 27, 11][37, 26, 11][37, 27, 10][37, 26, 10][37, 27, 9][37, 26, 9][37, 27, 8][37, 26, 8]
    MMCM1:DRP7A[37, 27, 23][37, 26, 23][37, 27, 22][37, 26, 22][37, 27, 21][37, 26, 21][37, 27, 20][37, 26, 20][37, 27, 19][37, 26, 19][37, 27, 18][37, 26, 18][37, 27, 17][37, 26, 17][37, 27, 16][37, 26, 16]
    MMCM1:DRP7B[37, 27, 31][37, 26, 31][37, 27, 30][37, 26, 30][37, 27, 29][37, 26, 29][37, 27, 28][37, 26, 28][37, 27, 27][37, 26, 27][37, 27, 26][37, 26, 26][37, 27, 25][37, 26, 25][37, 27, 24][37, 26, 24]
    MMCM1:DRP7C[37, 27, 39][37, 26, 39][37, 27, 38][37, 26, 38][37, 27, 37][37, 26, 37][37, 27, 36][37, 26, 36][37, 27, 35][37, 26, 35][37, 27, 34][37, 26, 34][37, 27, 33][37, 26, 33][37, 27, 32][37, 26, 32]
    MMCM1:DRP7D[37, 27, 47][37, 26, 47][37, 27, 46][37, 26, 46][37, 27, 45][37, 26, 45][37, 27, 44][37, 26, 44][37, 27, 43][37, 26, 43][37, 27, 42][37, 26, 42][37, 27, 41][37, 26, 41][37, 27, 40][37, 26, 40]
    MMCM1:DRP7E[37, 27, 55][37, 26, 55][37, 27, 54][37, 26, 54][37, 27, 53][37, 26, 53][37, 27, 52][37, 26, 52][37, 27, 51][37, 26, 51][37, 27, 50][37, 26, 50][37, 27, 49][37, 26, 49][37, 27, 48][37, 26, 48]
    MMCM1:DRP7F[37, 27, 63][37, 26, 63][37, 27, 62][37, 26, 62][37, 27, 61][37, 26, 61][37, 27, 60][37, 26, 60][37, 27, 59][37, 26, 59][37, 27, 58][37, 26, 58][37, 27, 57][37, 26, 57][37, 27, 56][37, 26, 56]
    Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:ENABLE[18, 27, 30]
    BUFHCE_L0:INIT_OUT[18, 26, 18]
    BUFHCE_L10:ENABLE[21, 27, 46]
    BUFHCE_L10:INIT_OUT[21, 26, 34]
    BUFHCE_L11:ENABLE[21, 28, 46]
    BUFHCE_L11:INIT_OUT[21, 29, 34]
    BUFHCE_L1:ENABLE[18, 28, 30]
    BUFHCE_L1:INIT_OUT[18, 29, 18]
    BUFHCE_L2:ENABLE[18, 27, 46]
    BUFHCE_L2:INIT_OUT[18, 26, 34]
    BUFHCE_L3:ENABLE[18, 28, 46]
    BUFHCE_L3:INIT_OUT[18, 29, 34]
    BUFHCE_L4:ENABLE[18, 27, 62]
    BUFHCE_L4:INIT_OUT[18, 26, 50]
    BUFHCE_L5:ENABLE[18, 28, 62]
    BUFHCE_L5:INIT_OUT[18, 29, 50]
    BUFHCE_L6:ENABLE[21, 27, 14]
    BUFHCE_L6:INIT_OUT[21, 26, 2]
    BUFHCE_L7:ENABLE[21, 28, 14]
    BUFHCE_L7:INIT_OUT[21, 29, 2]
    BUFHCE_L8:ENABLE[21, 27, 30]
    BUFHCE_L8:INIT_OUT[21, 26, 18]
    BUFHCE_L9:ENABLE[21, 28, 30]
    BUFHCE_L9:INIT_OUT[21, 29, 18]
    BUFHCE_R0:ENABLE[18, 31, 30]
    BUFHCE_R0:INIT_OUT[18, 30, 18]
    BUFHCE_R10:ENABLE[21, 31, 46]
    BUFHCE_R10:INIT_OUT[21, 30, 34]
    BUFHCE_R11:ENABLE[21, 32, 46]
    BUFHCE_R11:INIT_OUT[21, 33, 34]
    BUFHCE_R1:ENABLE[18, 32, 30]
    BUFHCE_R1:INIT_OUT[18, 33, 18]
    BUFHCE_R2:ENABLE[18, 31, 46]
    BUFHCE_R2:INIT_OUT[18, 30, 34]
    BUFHCE_R3:ENABLE[18, 32, 46]
    BUFHCE_R3:INIT_OUT[18, 33, 34]
    BUFHCE_R4:ENABLE[18, 31, 62]
    BUFHCE_R4:INIT_OUT[18, 30, 50]
    BUFHCE_R5:ENABLE[18, 32, 62]
    BUFHCE_R5:INIT_OUT[18, 33, 50]
    BUFHCE_R6:ENABLE[21, 31, 14]
    BUFHCE_R6:INIT_OUT[21, 30, 2]
    BUFHCE_R7:ENABLE[21, 32, 14]
    BUFHCE_R7:INIT_OUT[21, 33, 2]
    BUFHCE_R8:ENABLE[21, 31, 30]
    BUFHCE_R8:INIT_OUT[21, 30, 18]
    BUFHCE_R9:ENABLE[21, 32, 30]
    BUFHCE_R9:INIT_OUT[21, 33, 18]
    CMT:BUF.GCLK0_TEST[19, 27, 14]
    CMT:BUF.GCLK10_TEST[19, 32, 46]
    CMT:BUF.GCLK11_TEST[19, 31, 46]
    CMT:BUF.GCLK12_TEST[19, 27, 62]
    CMT:BUF.GCLK13_TEST[19, 28, 62]
    CMT:BUF.GCLK14_TEST[19, 32, 62]
    CMT:BUF.GCLK15_TEST[19, 31, 62]
    CMT:BUF.GCLK16_TEST[20, 27, 14]
    CMT:BUF.GCLK17_TEST[20, 28, 14]
    CMT:BUF.GCLK18_TEST[20, 32, 14]
    CMT:BUF.GCLK19_TEST[20, 31, 14]
    CMT:BUF.GCLK1_TEST[19, 28, 14]
    CMT:BUF.GCLK20_TEST[20, 27, 30]
    CMT:BUF.GCLK21_TEST[20, 28, 30]
    CMT:BUF.GCLK22_TEST[20, 32, 30]
    CMT:BUF.GCLK23_TEST[20, 31, 30]
    CMT:BUF.GCLK24_TEST[20, 27, 46]
    CMT:BUF.GCLK25_TEST[20, 28, 46]
    CMT:BUF.GCLK26_TEST[20, 32, 46]
    CMT:BUF.GCLK27_TEST[20, 31, 46]
    CMT:BUF.GCLK28_TEST[20, 27, 62]
    CMT:BUF.GCLK29_TEST[20, 28, 62]
    CMT:BUF.GCLK2_TEST[19, 32, 14]
    CMT:BUF.GCLK30_TEST[20, 32, 62]
    CMT:BUF.GCLK31_TEST[20, 31, 62]
    CMT:BUF.GCLK3_TEST[19, 31, 14]
    CMT:BUF.GCLK4_TEST[19, 27, 30]
    CMT:BUF.GCLK5_TEST[19, 28, 30]
    CMT:BUF.GCLK6_TEST[19, 32, 30]
    CMT:BUF.GCLK7_TEST[19, 31, 30]
    CMT:BUF.GCLK8_TEST[19, 27, 46]
    CMT:BUF.GCLK9_TEST[19, 28, 46]
    CMT:ENABLE.BUFHCE_L_CKINT0[40, 26, 30]
    CMT:ENABLE.BUFHCE_L_CKINT1[40, 26, 31]
    CMT:ENABLE.BUFHCE_R_CKINT0[40, 32, 30]
    CMT:ENABLE.BUFHCE_R_CKINT1[40, 32, 31]
    CMT:ENABLE.CCIO0_L[40, 28, 24]
    CMT:ENABLE.CCIO0_R[40, 30, 24]
    CMT:ENABLE.CCIO1_L[40, 28, 25]
    CMT:ENABLE.CCIO1_R[40, 30, 25]
    CMT:ENABLE.CCIO2_L[40, 28, 26]
    CMT:ENABLE.CCIO2_R[40, 30, 26]
    CMT:ENABLE.CCIO3_L[40, 28, 27]
    CMT:ENABLE.CCIO3_R[40, 30, 27]
    CMT:ENABLE.GCLK0[40, 26, 29]
    CMT:ENABLE.GCLK1[40, 32, 22]
    CMT:ENABLE.GCLK10[40, 26, 24]
    CMT:ENABLE.GCLK11[40, 32, 27]
    CMT:ENABLE.GCLK12[40, 26, 23]
    CMT:ENABLE.GCLK13[40, 32, 28]
    CMT:ENABLE.GCLK14[40, 26, 22]
    CMT:ENABLE.GCLK15[40, 32, 29]
    CMT:ENABLE.GCLK16[40, 26, 14]
    CMT:ENABLE.GCLK17[40, 32, 21]
    CMT:ENABLE.GCLK18[40, 26, 15]
    CMT:ENABLE.GCLK19[40, 32, 20]
    CMT:ENABLE.GCLK2[40, 26, 28]
    CMT:ENABLE.GCLK20[40, 26, 16]
    CMT:ENABLE.GCLK21[40, 32, 19]
    CMT:ENABLE.GCLK22[40, 26, 17]
    CMT:ENABLE.GCLK23[40, 32, 18]
    CMT:ENABLE.GCLK24[40, 26, 18]
    CMT:ENABLE.GCLK25[40, 32, 17]
    CMT:ENABLE.GCLK26[40, 26, 19]
    CMT:ENABLE.GCLK27[40, 32, 16]
    CMT:ENABLE.GCLK28[40, 26, 20]
    CMT:ENABLE.GCLK29[40, 32, 15]
    CMT:ENABLE.GCLK3[40, 32, 23]
    CMT:ENABLE.GCLK30[40, 26, 21]
    CMT:ENABLE.GCLK31[40, 32, 14]
    CMT:ENABLE.GCLK4[40, 26, 27]
    CMT:ENABLE.GCLK5[40, 32, 24]
    CMT:ENABLE.GCLK6[40, 26, 26]
    CMT:ENABLE.GCLK7[40, 32, 25]
    CMT:ENABLE.GCLK8[40, 26, 25]
    CMT:ENABLE.GCLK9[40, 32, 26]
    CMT:ENABLE.GIO0[40, 28, 18]
    CMT:ENABLE.GIO1[40, 30, 18]
    CMT:ENABLE.GIO2[40, 28, 19]
    CMT:ENABLE.GIO3[40, 30, 19]
    CMT:ENABLE.GIO4[40, 28, 20]
    CMT:ENABLE.GIO5[40, 30, 20]
    CMT:ENABLE.GIO6[40, 28, 21]
    CMT:ENABLE.GIO7[40, 30, 21]
    CMT:ENABLE.HCLK0_L[40, 29, 20]
    CMT:ENABLE.HCLK0_R[40, 31, 20]
    CMT:ENABLE.HCLK10_L[40, 29, 30]
    CMT:ENABLE.HCLK10_R[40, 31, 30]
    CMT:ENABLE.HCLK11_L[40, 29, 31]
    CMT:ENABLE.HCLK11_R[40, 31, 31]
    CMT:ENABLE.HCLK1_L[40, 29, 21]
    CMT:ENABLE.HCLK1_R[40, 31, 21]
    CMT:ENABLE.HCLK2_L[40, 29, 22]
    CMT:ENABLE.HCLK2_R[40, 31, 22]
    CMT:ENABLE.HCLK3_L[40, 29, 23]
    CMT:ENABLE.HCLK3_R[40, 31, 23]
    CMT:ENABLE.HCLK4_L[40, 29, 24]
    CMT:ENABLE.HCLK4_R[40, 31, 24]
    CMT:ENABLE.HCLK5_L[40, 29, 25]
    CMT:ENABLE.HCLK5_R[40, 31, 25]
    CMT:ENABLE.HCLK6_L[40, 29, 26]
    CMT:ENABLE.HCLK6_R[40, 31, 26]
    CMT:ENABLE.HCLK7_L[40, 29, 27]
    CMT:ENABLE.HCLK7_R[40, 31, 27]
    CMT:ENABLE.HCLK8_L[40, 29, 28]
    CMT:ENABLE.HCLK8_R[40, 31, 28]
    CMT:ENABLE.HCLK9_L[40, 29, 29]
    CMT:ENABLE.HCLK9_R[40, 31, 29]
    CMT:ENABLE.MGT0_L[40, 28, 14]
    CMT:ENABLE.MGT0_R[40, 30, 14]
    CMT:ENABLE.MGT1_L[40, 28, 15]
    CMT:ENABLE.MGT1_R[40, 30, 15]
    CMT:ENABLE.MGT2_L[40, 28, 16]
    CMT:ENABLE.MGT2_R[40, 30, 16]
    CMT:ENABLE.MGT3_L[40, 28, 17]
    CMT:ENABLE.MGT3_R[40, 30, 17]
    CMT:ENABLE.MGT4_L[40, 28, 22]
    CMT:ENABLE.MGT4_R[40, 30, 22]
    CMT:ENABLE.MGT5_L[40, 28, 23]
    CMT:ENABLE.MGT5_R[40, 30, 23]
    CMT:ENABLE.MGT6_L[40, 28, 28]
    CMT:ENABLE.MGT6_R[40, 30, 28]
    CMT:ENABLE.MGT7_L[40, 28, 29]
    CMT:ENABLE.MGT7_R[40, 30, 29]
    CMT:ENABLE.MGT8_L[40, 28, 30]
    CMT:ENABLE.MGT8_R[40, 30, 30]
    CMT:ENABLE.MGT9_L[40, 28, 31]
    CMT:ENABLE.MGT9_R[40, 30, 31]
    CMT:ENABLE.RCLK0_L[40, 29, 14]
    CMT:ENABLE.RCLK0_R[40, 31, 14]
    CMT:ENABLE.RCLK1_L[40, 29, 15]
    CMT:ENABLE.RCLK1_R[40, 31, 15]
    CMT:ENABLE.RCLK2_L[40, 29, 16]
    CMT:ENABLE.RCLK2_R[40, 31, 16]
    CMT:ENABLE.RCLK3_L[40, 29, 17]
    CMT:ENABLE.RCLK3_R[40, 31, 17]
    CMT:ENABLE.RCLK4_L[40, 29, 18]
    CMT:ENABLE.RCLK4_R[40, 31, 18]
    CMT:ENABLE.RCLK5_L[40, 29, 19]
    CMT:ENABLE.RCLK5_R[40, 31, 19]
    CMT:INV.BUFH_TEST_L[19, 30, 48]
    CMT:INV.BUFH_TEST_R[20, 30, 0]
    CMT:INV.GCLK0_TEST[19, 27, 0]
    CMT:INV.GCLK10_TEST[19, 32, 32]
    CMT:INV.GCLK11_TEST[19, 31, 32]
    CMT:INV.GCLK12_TEST[19, 27, 48]
    CMT:INV.GCLK13_TEST[19, 28, 48]
    CMT:INV.GCLK14_TEST[19, 32, 48]
    CMT:INV.GCLK15_TEST[19, 31, 48]
    CMT:INV.GCLK16_TEST[20, 27, 0]
    CMT:INV.GCLK17_TEST[20, 28, 0]
    CMT:INV.GCLK18_TEST[20, 32, 0]
    CMT:INV.GCLK19_TEST[20, 31, 0]
    CMT:INV.GCLK1_TEST[19, 28, 0]
    CMT:INV.GCLK20_TEST[20, 27, 16]
    CMT:INV.GCLK21_TEST[20, 28, 16]
    CMT:INV.GCLK22_TEST[20, 32, 16]
    CMT:INV.GCLK23_TEST[20, 31, 16]
    CMT:INV.GCLK24_TEST[20, 27, 32]
    CMT:INV.GCLK25_TEST[20, 28, 32]
    CMT:INV.GCLK26_TEST[20, 32, 32]
    CMT:INV.GCLK27_TEST[20, 31, 32]
    CMT:INV.GCLK28_TEST[20, 27, 48]
    CMT:INV.GCLK29_TEST[20, 28, 48]
    CMT:INV.GCLK2_TEST[19, 32, 0]
    CMT:INV.GCLK30_TEST[20, 32, 48]
    CMT:INV.GCLK31_TEST[20, 31, 48]
    CMT:INV.GCLK3_TEST[19, 31, 0]
    CMT:INV.GCLK4_TEST[19, 27, 16]
    CMT:INV.GCLK5_TEST[19, 28, 16]
    CMT:INV.GCLK6_TEST[19, 32, 16]
    CMT:INV.GCLK7_TEST[19, 31, 16]
    CMT:INV.GCLK8_TEST[19, 27, 32]
    CMT:INV.GCLK9_TEST[19, 28, 32]
    MMCM0:BUF.PERF0_IL[17, 26, 54]
    MMCM0:BUF.PERF0_IR[17, 27, 55]
    MMCM0:BUF.PERF0_OL[17, 27, 52]
    MMCM0:BUF.PERF0_OR[17, 26, 53]
    MMCM0:BUF.PERF1_IL[17, 26, 52]
    MMCM0:BUF.PERF1_IR[17, 27, 53]
    MMCM0:BUF.PERF1_OL[17, 27, 54]
    MMCM0:BUF.PERF1_OR[17, 26, 55]
    MMCM0:BUF.PERF2_IL[17, 26, 50]
    MMCM0:BUF.PERF2_IR[17, 27, 51]
    MMCM0:BUF.PERF2_OL[17, 27, 48]
    MMCM0:BUF.PERF2_OR[17, 26, 49]
    MMCM0:BUF.PERF3_IL[17, 26, 48]
    MMCM0:BUF.PERF3_IR[17, 27, 49]
    MMCM0:BUF.PERF3_OL[17, 27, 50]
    MMCM0:BUF.PERF3_OR[17, 26, 51]
    MMCM0:CASC_LOCK_EN[3, 26, 29]
    MMCM0:CLKBURST_ENABLE[17, 26, 25]
    MMCM0:CLKBURST_REPEAT[17, 27, 25]
    MMCM0:CLKFBIN_EDGE[15, 27, 1]
    MMCM0:CLKFBIN_NOCOUNT[15, 26, 1]
    MMCM0:CLKFBOUT_EDGE[15, 27, 20]
    MMCM0:CLKFBOUT_EN[15, 26, 25]
    MMCM0:CLKFBOUT_FRAC_EN[15, 27, 18]
    MMCM0:CLKFBOUT_FRAC_WF[15, 26, 18]
    MMCM0:CLKFBOUT_NOCOUNT[15, 26, 20]
    MMCM0:CLKFBOUT_USE_FINE_PS[15, 26, 19]
    MMCM0:CLKOUT0_EDGE[16, 27, 52]
    MMCM0:CLKOUT0_EN[16, 26, 57]
    MMCM0:CLKOUT0_FRAC_EN[16, 27, 50]
    MMCM0:CLKOUT0_FRAC_WF[16, 26, 50]
    MMCM0:CLKOUT0_NOCOUNT[16, 26, 52]
    MMCM0:CLKOUT0_USE_FINE_PS[16, 26, 51]
    MMCM0:CLKOUT1_EDGE[16, 27, 36]
    MMCM0:CLKOUT1_EN[16, 26, 41]
    MMCM0:CLKOUT1_NOCOUNT[16, 26, 36]
    MMCM0:CLKOUT1_USE_FINE_PS[16, 26, 35]
    MMCM0:CLKOUT2_EDGE[16, 27, 20]
    MMCM0:CLKOUT2_EN[16, 26, 25]
    MMCM0:CLKOUT2_NOCOUNT[16, 26, 20]
    MMCM0:CLKOUT2_USE_FINE_PS[16, 26, 19]
    MMCM0:CLKOUT3_EDGE[16, 27, 4]
    MMCM0:CLKOUT3_EN[16, 26, 9]
    MMCM0:CLKOUT3_NOCOUNT[16, 26, 4]
    MMCM0:CLKOUT3_USE_FINE_PS[16, 26, 3]
    MMCM0:CLKOUT4_CASCADE[15, 27, 51]
    MMCM0:CLKOUT4_EDGE[15, 27, 52]
    MMCM0:CLKOUT4_EN[15, 26, 57]
    MMCM0:CLKOUT4_NOCOUNT[15, 26, 52]
    MMCM0:CLKOUT4_USE_FINE_PS[15, 26, 51]
    MMCM0:CLKOUT5_EDGE[17, 27, 4]
    MMCM0:CLKOUT5_EN[17, 26, 9]
    MMCM0:CLKOUT5_FRAC_WF[17, 26, 2]
    MMCM0:CLKOUT5_NOCOUNT[17, 26, 4]
    MMCM0:CLKOUT5_USE_FINE_PS[17, 26, 3]
    MMCM0:CLKOUT6_EDGE[15, 27, 36]
    MMCM0:CLKOUT6_EN[15, 26, 41]
    MMCM0:CLKOUT6_FRAC_WF[15, 26, 34]
    MMCM0:CLKOUT6_NOCOUNT[15, 26, 36]
    MMCM0:CLKOUT6_USE_FINE_PS[15, 26, 35]
    MMCM0:CLOCK_HOLD[3, 27, 31]
    MMCM0:CP_BIAS_TRIP_SET[8, 27, 12]
    MMCM0:DIRECT_PATH_CNTRL[17, 27, 22]
    MMCM0:DIVCLK_EDGE[15, 27, 9]
    MMCM0:DIVCLK_NOCOUNT[15, 26, 9]
    MMCM0:EN_VCO_DIV1[13, 27, 47]
    MMCM0:EN_VCO_DIV6[13, 26, 47]
    MMCM0:GTS_WAIT[3, 27, 30]
    MMCM0:HVLF_CNT_TEST_EN[14, 27, 36]
    MMCM0:HVLF_STEP[14, 26, 36]
    MMCM0:INV.CLKINSEL[3, 26, 45]
    MMCM0:INV.PSEN[3, 27, 46]
    MMCM0:INV.PSINCDEC[3, 26, 46]
    MMCM0:INV.PWRDWN[3, 27, 47]
    MMCM0:INV.RST[3, 26, 47]
    MMCM0:IN_DLY_EN[17, 27, 16]
    MMCM0:MMCM_EN[3, 26, 31]
    MMCM0:STARTUP_WAIT[3, 26, 30]
    MMCM0:VLF_HIGH_DIS_B[9, 27, 44]
    MMCM0:VLF_HIGH_PWDN_B[9, 26, 15]
    MMCM1:BUF.PERF0_IL[22, 26, 9]
    MMCM1:BUF.PERF0_IR[22, 27, 8]
    MMCM1:BUF.PERF0_OL[22, 27, 11]
    MMCM1:BUF.PERF0_OR[22, 26, 10]
    MMCM1:BUF.PERF1_IL[22, 26, 11]
    MMCM1:BUF.PERF1_IR[22, 27, 10]
    MMCM1:BUF.PERF1_OL[22, 27, 9]
    MMCM1:BUF.PERF1_OR[22, 26, 8]
    MMCM1:BUF.PERF2_IL[22, 26, 13]
    MMCM1:BUF.PERF2_IR[22, 27, 12]
    MMCM1:BUF.PERF2_OL[22, 27, 15]
    MMCM1:BUF.PERF2_OR[22, 26, 14]
    MMCM1:BUF.PERF3_IL[22, 26, 15]
    MMCM1:BUF.PERF3_IR[22, 27, 14]
    MMCM1:BUF.PERF3_OL[22, 27, 13]
    MMCM1:BUF.PERF3_OR[22, 26, 12]
    MMCM1:CASC_LOCK_EN[36, 26, 34]
    MMCM1:CLKBURST_ENABLE[22, 26, 38]
    MMCM1:CLKBURST_REPEAT[22, 27, 38]
    MMCM1:CLKFBIN_EDGE[24, 27, 62]
    MMCM1:CLKFBIN_NOCOUNT[24, 26, 62]
    MMCM1:CLKFBOUT_EDGE[24, 27, 43]
    MMCM1:CLKFBOUT_EN[24, 26, 38]
    MMCM1:CLKFBOUT_FRAC_EN[24, 27, 45]
    MMCM1:CLKFBOUT_FRAC_WF[24, 26, 45]
    MMCM1:CLKFBOUT_NOCOUNT[24, 26, 43]
    MMCM1:CLKFBOUT_USE_FINE_PS[24, 26, 44]
    MMCM1:CLKOUT0_EDGE[23, 27, 11]
    MMCM1:CLKOUT0_EN[23, 26, 6]
    MMCM1:CLKOUT0_FRAC_EN[23, 27, 13]
    MMCM1:CLKOUT0_FRAC_WF[23, 26, 13]
    MMCM1:CLKOUT0_NOCOUNT[23, 26, 11]
    MMCM1:CLKOUT0_USE_FINE_PS[23, 26, 12]
    MMCM1:CLKOUT1_EDGE[23, 27, 27]
    MMCM1:CLKOUT1_EN[23, 26, 22]
    MMCM1:CLKOUT1_NOCOUNT[23, 26, 27]
    MMCM1:CLKOUT1_USE_FINE_PS[23, 26, 28]
    MMCM1:CLKOUT2_EDGE[23, 27, 43]
    MMCM1:CLKOUT2_EN[23, 26, 38]
    MMCM1:CLKOUT2_NOCOUNT[23, 26, 43]
    MMCM1:CLKOUT2_USE_FINE_PS[23, 26, 44]
    MMCM1:CLKOUT3_EDGE[23, 27, 59]
    MMCM1:CLKOUT3_EN[23, 26, 54]
    MMCM1:CLKOUT3_NOCOUNT[23, 26, 59]
    MMCM1:CLKOUT3_USE_FINE_PS[23, 26, 60]
    MMCM1:CLKOUT4_CASCADE[24, 27, 12]
    MMCM1:CLKOUT4_EDGE[24, 27, 11]
    MMCM1:CLKOUT4_EN[24, 26, 6]
    MMCM1:CLKOUT4_NOCOUNT[24, 26, 11]
    MMCM1:CLKOUT4_USE_FINE_PS[24, 26, 12]
    MMCM1:CLKOUT5_EDGE[22, 27, 59]
    MMCM1:CLKOUT5_EN[22, 26, 54]
    MMCM1:CLKOUT5_FRAC_WF[22, 26, 61]
    MMCM1:CLKOUT5_NOCOUNT[22, 26, 59]
    MMCM1:CLKOUT5_USE_FINE_PS[22, 26, 60]
    MMCM1:CLKOUT6_EDGE[24, 27, 27]
    MMCM1:CLKOUT6_EN[24, 26, 22]
    MMCM1:CLKOUT6_FRAC_WF[24, 26, 29]
    MMCM1:CLKOUT6_NOCOUNT[24, 26, 27]
    MMCM1:CLKOUT6_USE_FINE_PS[24, 26, 28]
    MMCM1:CLOCK_HOLD[36, 27, 32]
    MMCM1:CP_BIAS_TRIP_SET[31, 27, 51]
    MMCM1:DIRECT_PATH_CNTRL[22, 27, 41]
    MMCM1:DIVCLK_EDGE[24, 27, 54]
    MMCM1:DIVCLK_NOCOUNT[24, 26, 54]
    MMCM1:EN_VCO_DIV1[26, 27, 16]
    MMCM1:EN_VCO_DIV6[26, 26, 16]
    MMCM1:GTS_WAIT[36, 27, 33]
    MMCM1:HVLF_CNT_TEST_EN[25, 27, 27]
    MMCM1:HVLF_STEP[25, 26, 27]
    MMCM1:INV.CLKINSEL[36, 26, 18]
    MMCM1:INV.PSEN[36, 27, 17]
    MMCM1:INV.PSINCDEC[36, 26, 17]
    MMCM1:INV.PWRDWN[36, 27, 16]
    MMCM1:INV.RST[36, 26, 16]
    MMCM1:IN_DLY_EN[22, 27, 47]
    MMCM1:MMCM_EN[36, 26, 32]
    MMCM1:STARTUP_WAIT[36, 26, 33]
    MMCM1:VLF_HIGH_DIS_B[30, 27, 19]
    MMCM1:VLF_HIGH_PWDN_B[30, 26, 48]
    Non-inverted[0]
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM0:CLKFBIN_HT[15, 27, 2][15, 26, 2][15, 27, 3][15, 26, 3][15, 27, 4][15, 26, 4]
    MMCM0:CLKFBIN_LT[15, 27, 5][15, 26, 5][15, 27, 6][15, 26, 6][15, 27, 7][15, 26, 7]
    MMCM0:CLKFBOUT_DT[15, 27, 21][15, 26, 21][15, 27, 22][15, 26, 22][15, 27, 23][15, 26, 23]
    MMCM0:CLKFBOUT_HT[15, 27, 26][15, 26, 26][15, 27, 27][15, 26, 27][15, 27, 28][15, 26, 28]
    MMCM0:CLKFBOUT_LT[15, 27, 29][15, 26, 29][15, 27, 30][15, 26, 30][15, 27, 31][15, 26, 31]
    MMCM0:CLKOUT0_DT[16, 27, 53][16, 26, 53][16, 27, 54][16, 26, 54][16, 27, 55][16, 26, 55]
    MMCM0:CLKOUT0_HT[16, 27, 58][16, 26, 58][16, 27, 59][16, 26, 59][16, 27, 60][16, 26, 60]
    MMCM0:CLKOUT0_LT[16, 27, 61][16, 26, 61][16, 27, 62][16, 26, 62][16, 27, 63][16, 26, 63]
    MMCM0:CLKOUT1_DT[16, 27, 37][16, 26, 37][16, 27, 38][16, 26, 38][16, 27, 39][16, 26, 39]
    MMCM0:CLKOUT1_HT[16, 27, 42][16, 26, 42][16, 27, 43][16, 26, 43][16, 27, 44][16, 26, 44]
    MMCM0:CLKOUT1_LT[16, 27, 45][16, 26, 45][16, 27, 46][16, 26, 46][16, 27, 47][16, 26, 47]
    MMCM0:CLKOUT2_DT[16, 27, 21][16, 26, 21][16, 27, 22][16, 26, 22][16, 27, 23][16, 26, 23]
    MMCM0:CLKOUT2_HT[16, 27, 26][16, 26, 26][16, 27, 27][16, 26, 27][16, 27, 28][16, 26, 28]
    MMCM0:CLKOUT2_LT[16, 27, 29][16, 26, 29][16, 27, 30][16, 26, 30][16, 27, 31][16, 26, 31]
    MMCM0:CLKOUT3_DT[16, 27, 5][16, 26, 5][16, 27, 6][16, 26, 6][16, 27, 7][16, 26, 7]
    MMCM0:CLKOUT3_HT[16, 27, 10][16, 26, 10][16, 27, 11][16, 26, 11][16, 27, 12][16, 26, 12]
    MMCM0:CLKOUT3_LT[16, 27, 13][16, 26, 13][16, 27, 14][16, 26, 14][16, 27, 15][16, 26, 15]
    MMCM0:CLKOUT4_DT[15, 27, 53][15, 26, 53][15, 27, 54][15, 26, 54][15, 27, 55][15, 26, 55]
    MMCM0:CLKOUT4_HT[15, 27, 58][15, 26, 58][15, 27, 59][15, 26, 59][15, 27, 60][15, 26, 60]
    MMCM0:CLKOUT4_LT[15, 27, 61][15, 26, 61][15, 27, 62][15, 26, 62][15, 27, 63][15, 26, 63]
    MMCM0:CLKOUT5_DT[17, 27, 5][17, 26, 5][17, 27, 6][17, 26, 6][17, 27, 7][17, 26, 7]
    MMCM0:CLKOUT5_HT[17, 27, 10][17, 26, 10][17, 27, 11][17, 26, 11][17, 27, 12][17, 26, 12]
    MMCM0:CLKOUT5_LT[17, 27, 13][17, 26, 13][17, 27, 14][17, 26, 14][17, 27, 15][17, 26, 15]
    MMCM0:CLKOUT6_DT[15, 27, 37][15, 26, 37][15, 27, 38][15, 26, 38][15, 27, 39][15, 26, 39]
    MMCM0:CLKOUT6_HT[15, 27, 42][15, 26, 42][15, 27, 43][15, 26, 43][15, 27, 44][15, 26, 44]
    MMCM0:CLKOUT6_LT[15, 27, 45][15, 26, 45][15, 27, 46][15, 26, 46][15, 27, 47][15, 26, 47]
    MMCM0:DIVCLK_HT[15, 27, 10][15, 26, 10][15, 27, 11][15, 26, 11][15, 27, 12][15, 26, 12]
    MMCM0:DIVCLK_LT[15, 27, 13][15, 26, 13][15, 27, 14][15, 26, 14][15, 27, 15][15, 26, 15]
    MMCM0:FINE_PS_FRAC[3, 26, 26][3, 27, 27][3, 26, 27][3, 27, 28][3, 26, 28][3, 27, 29]
    MMCM0:HVLF_CNT_TEST[14, 27, 37][14, 26, 37][14, 27, 38][14, 26, 38][14, 27, 39][14, 26, 39]
    MMCM0:IN_DLY_MX_CVDD[17, 27, 58][17, 26, 58][17, 27, 59][17, 26, 59][17, 27, 60][17, 26, 60]
    MMCM0:IN_DLY_MX_DVDD[17, 27, 19][17, 26, 19][17, 27, 20][17, 26, 20][17, 27, 21][17, 26, 21]
    MMCM1:CLKFBIN_HT[24, 27, 61][24, 26, 61][24, 27, 60][24, 26, 60][24, 27, 59][24, 26, 59]
    MMCM1:CLKFBIN_LT[24, 27, 58][24, 26, 58][24, 27, 57][24, 26, 57][24, 27, 56][24, 26, 56]
    MMCM1:CLKFBOUT_DT[24, 27, 42][24, 26, 42][24, 27, 41][24, 26, 41][24, 27, 40][24, 26, 40]
    MMCM1:CLKFBOUT_HT[24, 27, 37][24, 26, 37][24, 27, 36][24, 26, 36][24, 27, 35][24, 26, 35]
    MMCM1:CLKFBOUT_LT[24, 27, 34][24, 26, 34][24, 27, 33][24, 26, 33][24, 27, 32][24, 26, 32]
    MMCM1:CLKOUT0_DT[23, 27, 10][23, 26, 10][23, 27, 9][23, 26, 9][23, 27, 8][23, 26, 8]
    MMCM1:CLKOUT0_HT[23, 27, 5][23, 26, 5][23, 27, 4][23, 26, 4][23, 27, 3][23, 26, 3]
    MMCM1:CLKOUT0_LT[23, 27, 2][23, 26, 2][23, 27, 1][23, 26, 1][23, 27, 0][23, 26, 0]
    MMCM1:CLKOUT1_DT[23, 27, 26][23, 26, 26][23, 27, 25][23, 26, 25][23, 27, 24][23, 26, 24]
    MMCM1:CLKOUT1_HT[23, 27, 21][23, 26, 21][23, 27, 20][23, 26, 20][23, 27, 19][23, 26, 19]
    MMCM1:CLKOUT1_LT[23, 27, 18][23, 26, 18][23, 27, 17][23, 26, 17][23, 27, 16][23, 26, 16]
    MMCM1:CLKOUT2_DT[23, 27, 42][23, 26, 42][23, 27, 41][23, 26, 41][23, 27, 40][23, 26, 40]
    MMCM1:CLKOUT2_HT[23, 27, 37][23, 26, 37][23, 27, 36][23, 26, 36][23, 27, 35][23, 26, 35]
    MMCM1:CLKOUT2_LT[23, 27, 34][23, 26, 34][23, 27, 33][23, 26, 33][23, 27, 32][23, 26, 32]
    MMCM1:CLKOUT3_DT[23, 27, 58][23, 26, 58][23, 27, 57][23, 26, 57][23, 27, 56][23, 26, 56]
    MMCM1:CLKOUT3_HT[23, 27, 53][23, 26, 53][23, 27, 52][23, 26, 52][23, 27, 51][23, 26, 51]
    MMCM1:CLKOUT3_LT[23, 27, 50][23, 26, 50][23, 27, 49][23, 26, 49][23, 27, 48][23, 26, 48]
    MMCM1:CLKOUT4_DT[24, 27, 10][24, 26, 10][24, 27, 9][24, 26, 9][24, 27, 8][24, 26, 8]
    MMCM1:CLKOUT4_HT[24, 27, 5][24, 26, 5][24, 27, 4][24, 26, 4][24, 27, 3][24, 26, 3]
    MMCM1:CLKOUT4_LT[24, 27, 2][24, 26, 2][24, 27, 1][24, 26, 1][24, 27, 0][24, 26, 0]
    MMCM1:CLKOUT5_DT[22, 27, 58][22, 26, 58][22, 27, 57][22, 26, 57][22, 27, 56][22, 26, 56]
    MMCM1:CLKOUT5_HT[22, 27, 53][22, 26, 53][22, 27, 52][22, 26, 52][22, 27, 51][22, 26, 51]
    MMCM1:CLKOUT5_LT[22, 27, 50][22, 26, 50][22, 27, 49][22, 26, 49][22, 27, 48][22, 26, 48]
    MMCM1:CLKOUT6_DT[24, 27, 26][24, 26, 26][24, 27, 25][24, 26, 25][24, 27, 24][24, 26, 24]
    MMCM1:CLKOUT6_HT[24, 27, 21][24, 26, 21][24, 27, 20][24, 26, 20][24, 27, 19][24, 26, 19]
    MMCM1:CLKOUT6_LT[24, 27, 18][24, 26, 18][24, 27, 17][24, 26, 17][24, 27, 16][24, 26, 16]
    MMCM1:DIVCLK_HT[24, 27, 53][24, 26, 53][24, 27, 52][24, 26, 52][24, 27, 51][24, 26, 51]
    MMCM1:DIVCLK_LT[24, 27, 50][24, 26, 50][24, 27, 49][24, 26, 49][24, 27, 48][24, 26, 48]
    MMCM1:FINE_PS_FRAC[36, 26, 37][36, 27, 36][36, 26, 36][36, 27, 35][36, 26, 35][36, 27, 34]
    MMCM1:HVLF_CNT_TEST[25, 27, 26][25, 26, 26][25, 27, 25][25, 26, 25][25, 27, 24][25, 26, 24]
    MMCM1:IN_DLY_MX_CVDD[22, 27, 5][22, 26, 5][22, 27, 4][22, 26, 4][22, 27, 3][22, 26, 3]
    MMCM1:IN_DLY_MX_DVDD[22, 27, 44][22, 26, 44][22, 27, 43][22, 26, 43][22, 27, 42][22, 26, 42]
    Non-inverted[5][4][3][2][1][0]
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    MMCM0:ANALOG_MISC[13, 26, 11][13, 27, 12][13, 26, 13][13, 27, 14]
    MMCM0:AVDD_VBG_SEL[8, 27, 46][8, 26, 46][8, 27, 47][8, 26, 47]
    MMCM0:CLKBURST_CNT[17, 27, 26][17, 26, 26][17, 27, 27][17, 26, 27]
    MMCM0:CP[8, 27, 8][8, 26, 9][8, 27, 10][8, 26, 11]
    MMCM0:DVDD_VBG_SEL[14, 27, 6][14, 26, 6][14, 27, 7][14, 26, 7]
    MMCM0:RES[8, 27, 0][8, 26, 1][8, 27, 2][8, 26, 3]
    MMCM1:ANALOG_MISC[26, 26, 52][26, 27, 51][26, 26, 50][26, 27, 49]
    MMCM1:AVDD_VBG_SEL[31, 27, 17][31, 26, 17][31, 27, 16][31, 26, 16]
    MMCM1:CLKBURST_CNT[22, 27, 37][22, 26, 37][22, 27, 36][22, 26, 36]
    MMCM1:CP[31, 27, 55][31, 26, 54][31, 27, 53][31, 26, 52]
    MMCM1:DVDD_VBG_SEL[25, 27, 57][25, 26, 57][25, 27, 56][25, 26, 56]
    MMCM1:RES[31, 27, 63][31, 26, 62][31, 27, 61][31, 26, 60]
    Non-inverted[3][2][1][0]
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    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM0:AVDD_COMP_SET[8, 26, 43][8, 27, 44]
    MMCM0:CLKFBOUT_MX[15, 27, 19][15, 26, 19]
    MMCM0:CLKOUT0_MX[16, 27, 51][16, 26, 51]
    MMCM0:CLKOUT1_MX[16, 27, 35][16, 26, 35]
    MMCM0:CLKOUT2_MX[16, 27, 19][16, 26, 19]
    MMCM0:CLKOUT3_MX[16, 27, 3][16, 26, 3]
    MMCM0:CLKOUT4_MX[15, 27, 51][15, 26, 51]
    MMCM0:CLKOUT5_MX[17, 27, 3][17, 26, 3]
    MMCM0:CLKOUT6_MX[15, 27, 35][15, 26, 35]
    MMCM0:CP_RES[8, 26, 13][8, 27, 14]
    MMCM0:DVDD_COMP_SET[14, 26, 3][14, 27, 4]
    MMCM0:LFHF[8, 27, 4][8, 26, 5]
    MMCM0:LF_NEN[9, 27, 40][9, 26, 41]
    MMCM0:LF_PEN[9, 27, 42][9, 26, 43]
    MMCM0:SYNTH_CLK_DIV[17, 27, 47][17, 26, 47]
    MMCM0:TMUX_MUX_SEL[17, 27, 24][17, 26, 24]
    MMCM1:AVDD_COMP_SET[31, 26, 20][31, 27, 19]
    MMCM1:CLKFBOUT_MX[24, 27, 44][24, 26, 44]
    MMCM1:CLKOUT0_MX[23, 27, 12][23, 26, 12]
    MMCM1:CLKOUT1_MX[23, 27, 28][23, 26, 28]
    MMCM1:CLKOUT2_MX[23, 27, 44][23, 26, 44]
    MMCM1:CLKOUT3_MX[23, 27, 60][23, 26, 60]
    MMCM1:CLKOUT4_MX[24, 27, 12][24, 26, 12]
    MMCM1:CLKOUT5_MX[22, 27, 60][22, 26, 60]
    MMCM1:CLKOUT6_MX[24, 27, 28][24, 26, 28]
    MMCM1:CP_RES[31, 26, 50][31, 27, 49]
    MMCM1:DVDD_COMP_SET[25, 26, 60][25, 27, 59]
    MMCM1:LFHF[31, 27, 59][31, 26, 58]
    MMCM1:LF_NEN[30, 27, 23][30, 26, 22]
    MMCM1:LF_PEN[30, 27, 21][30, 26, 20]
    MMCM1:SYNTH_CLK_DIV[22, 27, 16][22, 26, 16]
    MMCM1:TMUX_MUX_SEL[22, 27, 39][22, 26, 39]
    Non-inverted[1][0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM0:AVDD_VBG_PD[8, 26, 44][8, 27, 45][8, 26, 45]
    MMCM0:CLKFBOUT_FRAC[15, 26, 16][15, 27, 17][15, 26, 17]
    MMCM0:CLKFBOUT_PM[15, 27, 24][15, 26, 24][15, 27, 25]
    MMCM0:CLKOUT0_FRAC[16, 26, 48][16, 27, 49][16, 26, 49]
    MMCM0:CLKOUT0_PM[16, 27, 56][16, 26, 56][16, 27, 57]
    MMCM0:CLKOUT1_PM[16, 27, 40][16, 26, 40][16, 27, 41]
    MMCM0:CLKOUT2_PM[16, 27, 24][16, 26, 24][16, 27, 25]
    MMCM0:CLKOUT3_PM[16, 27, 8][16, 26, 8][16, 27, 9]
    MMCM0:CLKOUT4_PM[15, 27, 56][15, 26, 56][15, 27, 57]
    MMCM0:CLKOUT5_PM[17, 27, 8][17, 26, 8][17, 27, 9]
    MMCM0:CLKOUT6_PM[15, 27, 40][15, 26, 40][15, 27, 41]
    MMCM0:DVDD_VBG_PD[14, 26, 4][14, 27, 5][14, 26, 5]
    MMCM0:HROW_DLY_SET[17, 26, 56][17, 27, 57][17, 26, 57]
    MMCM0:MAN_LF[9, 26, 45][9, 27, 46][9, 26, 47]
    MMCM1:AVDD_VBG_PD[31, 26, 19][31, 27, 18][31, 26, 18]
    MMCM1:CLKFBOUT_FRAC[24, 26, 47][24, 27, 46][24, 26, 46]
    MMCM1:CLKFBOUT_PM[24, 27, 39][24, 26, 39][24, 27, 38]
    MMCM1:CLKOUT0_FRAC[23, 26, 15][23, 27, 14][23, 26, 14]
    MMCM1:CLKOUT0_PM[23, 27, 7][23, 26, 7][23, 27, 6]
    MMCM1:CLKOUT1_PM[23, 27, 23][23, 26, 23][23, 27, 22]
    MMCM1:CLKOUT2_PM[23, 27, 39][23, 26, 39][23, 27, 38]
    MMCM1:CLKOUT3_PM[23, 27, 55][23, 26, 55][23, 27, 54]
    MMCM1:CLKOUT4_PM[24, 27, 7][24, 26, 7][24, 27, 6]
    MMCM1:CLKOUT5_PM[22, 27, 55][22, 26, 55][22, 27, 54]
    MMCM1:CLKOUT6_PM[24, 27, 23][24, 26, 23][24, 27, 22]
    MMCM1:DVDD_VBG_PD[25, 26, 59][25, 27, 58][25, 26, 58]
    MMCM1:HROW_DLY_SET[22, 26, 7][22, 27, 6][22, 26, 6]
    MMCM1:MAN_LF[30, 26, 18][30, 27, 17][30, 26, 16]
    Non-inverted[2][1][0]
    +
    +
    + + + + +
    MMCM0:INTERP_EN[12, 27, 56][12, 26, 57][12, 27, 58][12, 26, 59][12, 27, 60][12, 26, 61][12, 27, 62][12, 26, 63]
    MMCM1:INTERP_EN[27, 27, 7][27, 26, 6][27, 27, 5][27, 26, 4][27, 27, 3][27, 26, 2][27, 27, 1][27, 26, 0]
    Non-inverted[7][6][5][4][3][2][1][0]
    +
    +
    + + + + +
    MMCM0:PFD[14, 26, 18][14, 27, 19][14, 26, 19][14, 27, 20][14, 26, 20][14, 27, 21][14, 26, 21]
    MMCM1:PFD[25, 26, 45][25, 27, 44][25, 26, 44][25, 27, 43][25, 26, 43][25, 27, 42][25, 26, 42]
    Non-inverted[6][5][4][3][2][1][0]
    +
    +
    +
    +
    +
    +
    + + + + + + + + +
    MMCM0:IN_DLY_SET[17, 26, 16][17, 27, 17][17, 26, 17][17, 27, 18][17, 26, 18]
    MMCM0:LOCK_FB_DLY[14, 26, 48][14, 27, 49][14, 26, 49][14, 27, 50][14, 26, 50]
    MMCM0:LOCK_REF_DLY[14, 26, 40][14, 27, 41][14, 26, 41][14, 27, 42][14, 26, 42]
    MMCM1:IN_DLY_SET[22, 26, 47][22, 27, 46][22, 26, 46][22, 27, 45][22, 26, 45]
    MMCM1:LOCK_FB_DLY[25, 26, 15][25, 27, 14][25, 26, 14][25, 27, 13][25, 26, 13]
    MMCM1:LOCK_REF_DLY[25, 26, 23][25, 27, 22][25, 26, 22][25, 27, 21][25, 26, 21]
    Non-inverted[4][3][2][1][0]
    +
    +
    +
    +
    +
    +
    + + + + + + + + +
    MMCM0:LOCK_CNT[14, 27, 59][14, 26, 59][14, 27, 60][14, 26, 60][14, 27, 61][14, 26, 61][14, 27, 62][14, 26, 62][14, 27, 63][14, 26, 63]
    MMCM0:LOCK_SAT_HIGH[14, 27, 43][14, 26, 43][14, 27, 44][14, 26, 44][14, 27, 45][14, 26, 45][14, 27, 46][14, 26, 46][14, 27, 47][14, 26, 47]
    MMCM0:UNLOCK_CNT[14, 27, 51][14, 26, 51][14, 27, 52][14, 26, 52][14, 27, 53][14, 26, 53][14, 27, 54][14, 26, 54][14, 27, 55][14, 26, 55]
    MMCM1:LOCK_CNT[25, 27, 4][25, 26, 4][25, 27, 3][25, 26, 3][25, 27, 2][25, 26, 2][25, 27, 1][25, 26, 1][25, 27, 0][25, 26, 0]
    MMCM1:LOCK_SAT_HIGH[25, 27, 20][25, 26, 20][25, 27, 19][25, 26, 19][25, 27, 18][25, 26, 18][25, 27, 17][25, 26, 17][25, 27, 16][25, 26, 16]
    MMCM1:UNLOCK_CNT[25, 27, 12][25, 26, 12][25, 27, 11][25, 26, 11][25, 27, 10][25, 26, 10][25, 27, 9][25, 26, 9][25, 27, 8][25, 26, 8]
    Non-inverted[9][8][7][6][5][4][3][2][1][0]
    +
    +
    + + + + + + + + + + + +
    MMCM0:MUX.CASC_OUT[17, 26, 22][17, 27, 23][17, 26, 23]
    MMCM1:MUX.CASC_OUT[22, 26, 41][22, 27, 40][22, 26, 40]
    CLKOUT0000
    CLKOUT1001
    CLKOUT2010
    CLKOUT3011
    CLKOUT4100
    CLKOUT5101
    CLKOUT6110
    CLKFBOUT111
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + +
    MMCM0:MUX.PERF0[17, 27, 31][17, 26, 31][17, 26, 33]
    MMCM0:MUX.PERF1[17, 27, 30][17, 26, 30][17, 27, 33]
    MMCM0:MUX.PERF2[17, 27, 29][17, 26, 29][17, 26, 32]
    MMCM0:MUX.PERF3[17, 27, 28][17, 26, 28][17, 27, 32]
    MMCM1:MUX.PERF0[22, 27, 32][22, 26, 32][22, 26, 30]
    MMCM1:MUX.PERF1[22, 27, 33][22, 26, 33][22, 27, 30]
    MMCM1:MUX.PERF2[22, 27, 34][22, 26, 34][22, 26, 31]
    MMCM1:MUX.PERF3[22, 27, 35][22, 26, 35][22, 27, 31]
    NONE000
    CLKOUT0001
    CLKOUT1011
    CLKOUT2101
    CLKOUT3111
    +
    +
    + + + + + + + +
    MMCM0:MUX.CLKIN2[17, 27, 61][17, 26, 61]
    MMCM1:MUX.CLKIN2[22, 27, 2][22, 26, 2]
    CLKIN2_IO00
    CLKIN2_HCLK01
    CLKIN2_MGT10
    CLKIN2_CKINT11
    +
    +
    + + + + + + + +
    MMCM0:MUX.CLKIN1[17, 27, 62][17, 26, 62]
    MMCM1:MUX.CLKIN1[22, 27, 1][22, 26, 1]
    CLKIN1_IO00
    CLKIN1_HCLK01
    CLKIN1_MGT10
    CLKIN1_CKINT11
    +
    +
    + + + + + + +
    MMCM0:MUX.CLKFBIN[17, 27, 63][17, 26, 63]
    MMCM1:MUX.CLKFBIN[22, 27, 0][22, 26, 0]
    CLKFBIN_IO00
    CLKFBIN_HCLK01
    CLKFBIN_CKINT11
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:INV.CE[18, 27, 19]
    BUFHCE_L10:INV.CE[21, 27, 35]
    BUFHCE_L11:INV.CE[21, 28, 35]
    BUFHCE_L1:INV.CE[18, 28, 19]
    BUFHCE_L2:INV.CE[18, 27, 35]
    BUFHCE_L3:INV.CE[18, 28, 35]
    BUFHCE_L4:INV.CE[18, 27, 51]
    BUFHCE_L5:INV.CE[18, 28, 51]
    BUFHCE_L6:INV.CE[21, 27, 3]
    BUFHCE_L7:INV.CE[21, 28, 3]
    BUFHCE_L8:INV.CE[21, 27, 19]
    BUFHCE_L9:INV.CE[21, 28, 19]
    BUFHCE_R0:INV.CE[18, 31, 19]
    BUFHCE_R10:INV.CE[21, 31, 35]
    BUFHCE_R11:INV.CE[21, 32, 35]
    BUFHCE_R1:INV.CE[18, 32, 19]
    BUFHCE_R2:INV.CE[18, 31, 35]
    BUFHCE_R3:INV.CE[18, 32, 35]
    BUFHCE_R4:INV.CE[18, 31, 51]
    BUFHCE_R5:INV.CE[18, 32, 51]
    BUFHCE_R6:INV.CE[21, 31, 3]
    BUFHCE_R7:INV.CE[21, 32, 3]
    BUFHCE_R8:INV.CE[21, 31, 19]
    BUFHCE_R9:INV.CE[21, 32, 19]
    Inverted~[0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:MUX.I[18, 27, 24][18, 26, 24][18, 26, 26][18, 27, 27][18, 26, 28][18, 27, 29][18, 26, 30][18, 27, 31][18, 26, 23][18, 26, 21][18, 27, 22][18, 26, 22][18, 27, 23][18, 26, 19][18, 26, 20][18, 27, 20][18, 27, 21]
    BUFHCE_L10:MUX.I[21, 27, 40][21, 26, 40][21, 26, 42][21, 27, 43][21, 26, 44][21, 27, 45][21, 26, 46][21, 27, 47][21, 26, 39][21, 26, 37][21, 27, 38][21, 26, 38][21, 27, 39][21, 26, 35][21, 26, 36][21, 27, 36][21, 27, 37]
    BUFHCE_L11:MUX.I[21, 28, 40][21, 29, 40][21, 29, 42][21, 28, 43][21, 29, 44][21, 28, 45][21, 29, 46][21, 28, 47][21, 29, 39][21, 29, 37][21, 28, 38][21, 29, 38][21, 28, 39][21, 29, 35][21, 29, 36][21, 28, 36][21, 28, 37]
    BUFHCE_L1:MUX.I[18, 28, 24][18, 29, 24][18, 29, 26][18, 28, 27][18, 29, 28][18, 28, 29][18, 29, 30][18, 28, 31][18, 29, 23][18, 29, 21][18, 28, 22][18, 29, 22][18, 28, 23][18, 29, 19][18, 29, 20][18, 28, 20][18, 28, 21]
    BUFHCE_L2:MUX.I[18, 27, 40][18, 26, 40][18, 26, 42][18, 27, 43][18, 26, 44][18, 27, 45][18, 26, 46][18, 27, 47][18, 26, 39][18, 26, 37][18, 27, 38][18, 26, 38][18, 27, 39][18, 26, 35][18, 26, 36][18, 27, 36][18, 27, 37]
    BUFHCE_L3:MUX.I[18, 28, 40][18, 29, 40][18, 29, 42][18, 28, 43][18, 29, 44][18, 28, 45][18, 29, 46][18, 28, 47][18, 29, 39][18, 29, 37][18, 28, 38][18, 29, 38][18, 28, 39][18, 29, 35][18, 29, 36][18, 28, 36][18, 28, 37]
    BUFHCE_L4:MUX.I[18, 27, 56][18, 26, 56][18, 26, 58][18, 27, 59][18, 26, 60][18, 27, 61][18, 26, 62][18, 27, 63][18, 26, 55][18, 26, 53][18, 27, 54][18, 26, 54][18, 27, 55][18, 26, 51][18, 26, 52][18, 27, 52][18, 27, 53]
    BUFHCE_L5:MUX.I[18, 28, 56][18, 29, 56][18, 29, 58][18, 28, 59][18, 29, 60][18, 28, 61][18, 29, 62][18, 28, 63][18, 29, 55][18, 29, 53][18, 28, 54][18, 29, 54][18, 28, 55][18, 29, 51][18, 29, 52][18, 28, 52][18, 28, 53]
    BUFHCE_L6:MUX.I[21, 27, 8][21, 26, 8][21, 26, 10][21, 27, 11][21, 26, 12][21, 27, 13][21, 26, 14][21, 27, 15][21, 26, 7][21, 26, 5][21, 27, 6][21, 26, 6][21, 27, 7][21, 26, 3][21, 26, 4][21, 27, 4][21, 27, 5]
    BUFHCE_L7:MUX.I[21, 28, 8][21, 29, 8][21, 29, 10][21, 28, 11][21, 29, 12][21, 28, 13][21, 29, 14][21, 28, 15][21, 29, 7][21, 29, 5][21, 28, 6][21, 29, 6][21, 28, 7][21, 29, 3][21, 29, 4][21, 28, 4][21, 28, 5]
    BUFHCE_L8:MUX.I[21, 27, 24][21, 26, 24][21, 26, 26][21, 27, 27][21, 26, 28][21, 27, 29][21, 26, 30][21, 27, 31][21, 26, 23][21, 26, 21][21, 27, 22][21, 26, 22][21, 27, 23][21, 26, 19][21, 26, 20][21, 27, 20][21, 27, 21]
    BUFHCE_L9:MUX.I[21, 28, 24][21, 29, 24][21, 29, 26][21, 28, 27][21, 29, 28][21, 28, 29][21, 29, 30][21, 28, 31][21, 29, 23][21, 29, 21][21, 28, 22][21, 29, 22][21, 28, 23][21, 29, 19][21, 29, 20][21, 28, 20][21, 28, 21]
    BUFHCE_R0:MUX.I[18, 31, 24][18, 30, 24][18, 30, 26][18, 31, 27][18, 30, 28][18, 31, 29][18, 30, 30][18, 31, 31][18, 30, 23][18, 30, 21][18, 31, 22][18, 30, 22][18, 31, 23][18, 30, 19][18, 30, 20][18, 31, 20][18, 31, 21]
    BUFHCE_R10:MUX.I[21, 31, 40][21, 30, 40][21, 30, 42][21, 31, 43][21, 30, 44][21, 31, 45][21, 30, 46][21, 31, 47][21, 30, 39][21, 30, 37][21, 31, 38][21, 30, 38][21, 31, 39][21, 30, 35][21, 30, 36][21, 31, 36][21, 31, 37]
    BUFHCE_R11:MUX.I[21, 32, 40][21, 33, 40][21, 33, 42][21, 32, 43][21, 33, 44][21, 32, 45][21, 33, 46][21, 32, 47][21, 33, 39][21, 33, 37][21, 32, 38][21, 33, 38][21, 32, 39][21, 33, 35][21, 33, 36][21, 32, 36][21, 32, 37]
    BUFHCE_R1:MUX.I[18, 32, 24][18, 33, 24][18, 33, 26][18, 32, 27][18, 33, 28][18, 32, 29][18, 33, 30][18, 32, 31][18, 33, 23][18, 33, 21][18, 32, 22][18, 33, 22][18, 32, 23][18, 33, 19][18, 33, 20][18, 32, 20][18, 32, 21]
    BUFHCE_R2:MUX.I[18, 31, 40][18, 30, 40][18, 30, 42][18, 31, 43][18, 30, 44][18, 31, 45][18, 30, 46][18, 31, 47][18, 30, 39][18, 30, 37][18, 31, 38][18, 30, 38][18, 31, 39][18, 30, 35][18, 30, 36][18, 31, 36][18, 31, 37]
    BUFHCE_R3:MUX.I[18, 32, 40][18, 33, 40][18, 33, 42][18, 32, 43][18, 33, 44][18, 32, 45][18, 33, 46][18, 32, 47][18, 33, 39][18, 33, 37][18, 32, 38][18, 33, 38][18, 32, 39][18, 33, 35][18, 33, 36][18, 32, 36][18, 32, 37]
    BUFHCE_R4:MUX.I[18, 31, 56][18, 30, 56][18, 30, 58][18, 31, 59][18, 30, 60][18, 31, 61][18, 30, 62][18, 31, 63][18, 30, 55][18, 30, 53][18, 31, 54][18, 30, 54][18, 31, 55][18, 30, 51][18, 30, 52][18, 31, 52][18, 31, 53]
    BUFHCE_R5:MUX.I[18, 32, 56][18, 33, 56][18, 33, 58][18, 32, 59][18, 33, 60][18, 32, 61][18, 33, 62][18, 32, 63][18, 33, 55][18, 33, 53][18, 32, 54][18, 33, 54][18, 32, 55][18, 33, 51][18, 33, 52][18, 32, 52][18, 32, 53]
    BUFHCE_R6:MUX.I[21, 31, 8][21, 30, 8][21, 30, 10][21, 31, 11][21, 30, 12][21, 31, 13][21, 30, 14][21, 31, 15][21, 30, 7][21, 30, 5][21, 31, 6][21, 30, 6][21, 31, 7][21, 30, 3][21, 30, 4][21, 31, 4][21, 31, 5]
    BUFHCE_R7:MUX.I[21, 32, 8][21, 33, 8][21, 33, 10][21, 32, 11][21, 33, 12][21, 32, 13][21, 33, 14][21, 32, 15][21, 33, 7][21, 33, 5][21, 32, 6][21, 33, 6][21, 32, 7][21, 33, 3][21, 33, 4][21, 32, 4][21, 32, 5]
    BUFHCE_R8:MUX.I[21, 31, 24][21, 30, 24][21, 30, 26][21, 31, 27][21, 30, 28][21, 31, 29][21, 30, 30][21, 31, 31][21, 30, 23][21, 30, 21][21, 31, 22][21, 30, 22][21, 31, 23][21, 30, 19][21, 30, 20][21, 31, 20][21, 31, 21]
    BUFHCE_R9:MUX.I[21, 32, 24][21, 33, 24][21, 33, 26][21, 32, 27][21, 33, 28][21, 32, 29][21, 33, 30][21, 32, 31][21, 33, 23][21, 33, 21][21, 32, 22][21, 33, 22][21, 32, 23][21, 33, 19][21, 33, 20][21, 32, 20][21, 32, 21]
    NONE00000000000000000
    GCLK000000001000000001
    GCLK800000001000000010
    GCLK1600000001000000100
    GCLK2400000001000001000
    CCIO0_L00000001000010000
    CKINT000000001000100000
    BUFH_TEST_R00000001001000000
    MMCM0_CLKOUT000000001010000000
    MMCM1_CLKOUT000000001100000000
    GCLK100000010000000001
    GCLK900000010000000010
    GCLK1700000010000000100
    GCLK2500000010000001000
    CCIO1_L00000010000010000
    CKINT100000010000100000
    BUFH_TEST_L00000010001000000
    MMCM0_CLKOUT0B00000010010000000
    MMCM1_CLKOUT0B00000010100000000
    GCLK200000100000000001
    GCLK1000000100000000010
    GCLK1800000100000000100
    GCLK2600000100000001000
    CCIO2_L00000100000010000
    MMCM1_CLKOUT400000100000100000
    MMCM0_CLKOUT400000100001000000
    MMCM0_CLKOUT100000100010000000
    MMCM1_CLKOUT100000100100000000
    GCLK300001000000000001
    GCLK1100001000000000010
    GCLK1900001000000000100
    GCLK2700001000000001000
    CCIO3_L00001000000010000
    MMCM1_CLKOUT500001000000100000
    MMCM0_CLKOUT500001000001000000
    MMCM0_CLKOUT1B00001000010000000
    MMCM1_CLKOUT1B00001000100000000
    GCLK400010000000000001
    GCLK1200010000000000010
    GCLK2000010000000000100
    GCLK2800010000000001000
    CCIO0_R00010000000010000
    MMCM1_CLKOUT600010000000100000
    MMCM0_CLKOUT600010000001000000
    MMCM0_CLKOUT200010000010000000
    MMCM1_CLKOUT200010000100000000
    GCLK500100000000000001
    GCLK1300100000000000010
    GCLK2100100000000000100
    GCLK2900100000000001000
    CCIO1_R00100000000010000
    MMCM1_CLKFBOUT00100000000100000
    MMCM0_CLKFBOUT00100000001000000
    MMCM0_CLKOUT2B00100000010000000
    MMCM1_CLKOUT2B00100000100000000
    GCLK601000000000000001
    GCLK1401000000000000010
    GCLK2201000000000000100
    GCLK3001000000000001000
    CCIO2_R01000000000010000
    MMCM1_CLKFBOUTB01000000000100000
    MMCM0_CLKFBOUTB01000000001000000
    MMCM0_CLKOUT301000000010000000
    MMCM1_CLKOUT301000000100000000
    GCLK710000000000000001
    GCLK1510000000000000010
    GCLK2310000000000000100
    GCLK3110000000000001000
    CCIO3_R10000000000010000
    MMCM1_TMUXOUT10000000000100000
    MMCM0_TMUXOUT10000000001000000
    MMCM0_CLKOUT3B10000000010000000
    MMCM1_CLKOUT3B10000000100000000
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM0:MUX.CLKFBIN_IO[18, 28, 18][18, 29, 17][18, 28, 17][18, 28, 26][18, 29, 27][18, 28, 28][18, 28, 25][18, 29, 29][18, 29, 25]
    MMCM0:MUX.CLKIN1_IO[18, 28, 34][18, 29, 33][18, 28, 33][18, 28, 42][18, 29, 43][18, 28, 44][18, 28, 41][18, 29, 45][18, 29, 41]
    MMCM0:MUX.CLKIN2_IO[18, 31, 34][18, 30, 33][18, 31, 33][18, 31, 42][18, 30, 43][18, 31, 44][18, 31, 41][18, 30, 45][18, 30, 41]
    MMCM1:MUX.CLKFBIN_IO[21, 28, 34][21, 29, 33][21, 28, 33][21, 28, 42][21, 29, 43][21, 28, 44][21, 28, 41][21, 29, 45][21, 29, 41]
    MMCM1:MUX.CLKIN1_IO[21, 28, 18][21, 29, 17][21, 28, 17][21, 28, 26][21, 29, 27][21, 28, 28][21, 28, 25][21, 29, 29][21, 29, 25]
    MMCM1:MUX.CLKIN2_IO[21, 31, 18][21, 30, 17][21, 31, 17][21, 31, 26][21, 30, 27][21, 31, 28][21, 31, 25][21, 30, 29][21, 30, 25]
    NONE000000000
    GIO0001000001
    GIO1001000010
    GIO2001000100
    GIO3001001000
    GIO5001010000
    GIO7001100000
    CCIO2_L010000001
    GIO4010000010
    CCIO3_L010000100
    GIO6010001000
    CCIO0_L010010000
    CCIO1_L010100000
    CCIO0_R100000010
    CCIO1_R100001000
    CCIO2_R100010000
    CCIO3_R100100000
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM0:MUX.CLKIN1_MGT[18, 28, 50][18, 28, 49][18, 29, 49][18, 29, 48][18, 28, 58][18, 29, 59][18, 28, 60][18, 28, 57][18, 29, 61][18, 29, 57]
    MMCM0:MUX.CLKIN2_MGT[18, 31, 50][18, 31, 49][18, 30, 49][18, 30, 48][18, 31, 58][18, 30, 59][18, 31, 60][18, 31, 57][18, 30, 61][18, 30, 57]
    MMCM1:MUX.CLKIN1_MGT[21, 28, 2][21, 28, 1][21, 29, 1][21, 29, 0][21, 28, 10][21, 29, 11][21, 28, 12][21, 28, 9][21, 29, 13][21, 29, 9]
    MMCM1:MUX.CLKIN2_MGT[21, 31, 2][21, 31, 1][21, 30, 1][21, 30, 0][21, 31, 10][21, 30, 11][21, 31, 12][21, 31, 9][21, 30, 13][21, 30, 9]
    NONE0000000000
    MGT0_L0010000001
    MGT6_R0010000010
    MGT1_L0010000100
    MGT7_R0010001000
    MGT8_R0010010000
    MGT9_R0010100000
    MGT9_L0011000000
    MGT4_R0100000001
    MGT0_R0100000010
    MGT5_R0100000100
    MGT1_R0100001000
    MGT2_R0100010000
    MGT3_R0100100000
    MGT8_L0101000000
    MGT6_L1000000001
    MGT2_L1000000010
    MGT7_L1000000100
    MGT3_L1000001000
    MGT4_L1000010000
    MGT5_L1000100000
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT:MUX.CASCO0[19, 27, 8][19, 26, 8][19, 26, 10][19, 27, 11][19, 26, 12][19, 27, 13][19, 26, 14][19, 27, 15][19, 26, 3][19, 26, 4][19, 27, 4][19, 27, 5][19, 27, 7][19, 26, 6][19, 26, 7][19, 27, 6][19, 26, 5][19, 26, 2]
    CMT:MUX.CASCO11[19, 31, 40][19, 30, 40][19, 30, 42][19, 31, 43][19, 30, 44][19, 31, 45][19, 30, 46][19, 31, 47][19, 30, 35][19, 30, 36][19, 31, 36][19, 31, 37][19, 31, 39][19, 30, 38][19, 30, 39][19, 31, 38][19, 30, 37][19, 30, 34]
    CMT:MUX.CASCO12[19, 27, 56][19, 26, 56][19, 26, 58][19, 27, 59][19, 26, 60][19, 27, 61][19, 26, 62][19, 27, 63][19, 26, 51][19, 26, 52][19, 27, 52][19, 27, 53][19, 27, 55][19, 26, 54][19, 26, 55][19, 27, 54][19, 26, 53][19, 26, 50]
    CMT:MUX.CASCO15[19, 31, 56][19, 30, 56][19, 30, 58][19, 31, 59][19, 30, 60][19, 31, 61][19, 30, 62][19, 31, 63][19, 30, 51][19, 30, 52][19, 31, 52][19, 31, 53][19, 31, 55][19, 30, 54][19, 30, 55][19, 31, 54][19, 30, 53][19, 30, 50]
    CMT:MUX.CASCO16[20, 27, 8][20, 26, 8][20, 26, 10][20, 27, 11][20, 26, 12][20, 27, 13][20, 26, 14][20, 27, 15][20, 26, 3][20, 26, 4][20, 27, 4][20, 27, 5][20, 27, 7][20, 26, 6][20, 26, 7][20, 27, 6][20, 26, 5][20, 26, 2]
    CMT:MUX.CASCO19[20, 31, 8][20, 30, 8][20, 30, 10][20, 31, 11][20, 30, 12][20, 31, 13][20, 30, 14][20, 31, 15][20, 30, 3][20, 30, 4][20, 31, 4][20, 31, 5][20, 31, 7][20, 30, 6][20, 30, 7][20, 31, 6][20, 30, 5][20, 30, 2]
    CMT:MUX.CASCO20[20, 27, 24][20, 26, 24][20, 26, 26][20, 27, 27][20, 26, 28][20, 27, 29][20, 26, 30][20, 27, 31][20, 26, 19][20, 26, 20][20, 27, 20][20, 27, 21][20, 27, 23][20, 26, 22][20, 26, 23][20, 27, 22][20, 26, 21][20, 26, 18]
    CMT:MUX.CASCO23[20, 31, 24][20, 30, 24][20, 30, 26][20, 31, 27][20, 30, 28][20, 31, 29][20, 30, 30][20, 31, 31][20, 30, 19][20, 30, 20][20, 31, 20][20, 31, 21][20, 31, 23][20, 30, 22][20, 30, 23][20, 31, 22][20, 30, 21][20, 30, 18]
    CMT:MUX.CASCO24[20, 27, 40][20, 26, 40][20, 26, 42][20, 27, 43][20, 26, 44][20, 27, 45][20, 26, 46][20, 27, 47][20, 26, 35][20, 26, 36][20, 27, 36][20, 27, 37][20, 27, 39][20, 26, 38][20, 26, 39][20, 27, 38][20, 26, 37][20, 26, 34]
    CMT:MUX.CASCO27[20, 31, 40][20, 30, 40][20, 30, 42][20, 31, 43][20, 30, 44][20, 31, 45][20, 30, 46][20, 31, 47][20, 30, 35][20, 30, 36][20, 31, 36][20, 31, 37][20, 31, 39][20, 30, 38][20, 30, 39][20, 31, 38][20, 30, 37][20, 30, 34]
    CMT:MUX.CASCO28[20, 27, 56][20, 26, 56][20, 26, 58][20, 27, 59][20, 26, 60][20, 27, 61][20, 26, 62][20, 27, 63][20, 26, 51][20, 26, 52][20, 27, 52][20, 27, 53][20, 27, 55][20, 26, 54][20, 26, 55][20, 27, 54][20, 26, 53][20, 26, 50]
    CMT:MUX.CASCO3[19, 31, 8][19, 30, 8][19, 30, 10][19, 31, 11][19, 30, 12][19, 31, 13][19, 30, 14][19, 31, 15][19, 30, 3][19, 30, 4][19, 31, 4][19, 31, 5][19, 31, 7][19, 30, 6][19, 30, 7][19, 31, 6][19, 30, 5][19, 30, 2]
    CMT:MUX.CASCO31[20, 31, 56][20, 30, 56][20, 30, 58][20, 31, 59][20, 30, 60][20, 31, 61][20, 30, 62][20, 31, 63][20, 30, 51][20, 30, 52][20, 31, 52][20, 31, 53][20, 31, 55][20, 30, 54][20, 30, 55][20, 31, 54][20, 30, 53][20, 30, 50]
    CMT:MUX.CASCO4[19, 27, 24][19, 26, 24][19, 26, 26][19, 27, 27][19, 26, 28][19, 27, 29][19, 26, 30][19, 27, 31][19, 26, 19][19, 26, 20][19, 27, 20][19, 27, 21][19, 27, 23][19, 26, 22][19, 26, 23][19, 27, 22][19, 26, 21][19, 26, 18]
    CMT:MUX.CASCO7[19, 31, 24][19, 30, 24][19, 30, 26][19, 31, 27][19, 30, 28][19, 31, 29][19, 30, 30][19, 31, 31][19, 30, 19][19, 30, 20][19, 31, 20][19, 31, 21][19, 31, 23][19, 30, 22][19, 30, 23][19, 31, 22][19, 30, 21][19, 30, 18]
    CMT:MUX.CASCO8[19, 27, 40][19, 26, 40][19, 26, 42][19, 27, 43][19, 26, 44][19, 27, 45][19, 26, 46][19, 27, 47][19, 26, 35][19, 26, 36][19, 27, 36][19, 27, 37][19, 27, 39][19, 26, 38][19, 26, 39][19, 27, 38][19, 26, 37][19, 26, 34]
    NONE000000000000000000
    CASCI000000000000000001
    MMCM0_CLKOUT0000000010000000010
    BUFH_TEST_L000000010000000100
    MMCM1_CLKOUT0000000010000001000
    GCLK_TEST000000010000010000
    CCIO0_L000000010000100000
    MGT0_L000000010001000000
    MGT8_L000000010010000000
    MGT0_R000000010100000000
    MGT8_R000000011000000000
    MMCM0_CLKOUT0B000000100000000010
    BUFH_TEST_R000000100000000100
    MMCM1_CLKOUT0B000000100000001000
    CCIO1_L000000100000100000
    MGT1_L000000100001000000
    MGT9_L000000100010000000
    MGT1_R000000100100000000
    MGT9_R000000101000000000
    MMCM0_CLKOUT1000001000000000010
    MMCM0_CLKOUT4000001000000000100
    MMCM1_CLKOUT1000001000000001000
    MMCM1_CLKOUT4000001000000010000
    CCIO2_L000001000000100000
    MGT2_L000001000001000000
    RCLK0_L000001000010000000
    MGT2_R000001000100000000
    RCLK0_R000001001000000000
    MMCM0_CLKOUT1B000010000000000010
    MMCM0_CLKOUT5000010000000000100
    MMCM1_CLKOUT1B000010000000001000
    MMCM1_CLKOUT5000010000000010000
    CCIO3_L000010000000100000
    MGT3_L000010000001000000
    RCLK1_L000010000010000000
    MGT3_R000010000100000000
    RCLK1_R000010001000000000
    MMCM0_CLKOUT2000100000000000010
    MMCM0_CLKOUT6000100000000000100
    MMCM1_CLKOUT2000100000000001000
    MMCM1_CLKOUT6000100000000010000
    CCIO0_R000100000000100000
    MGT4_L000100000001000000
    RCLK2_L000100000010000000
    MGT4_R000100000100000000
    RCLK2_R000100001000000000
    MMCM0_CLKOUT2B001000000000000010
    MMCM0_CLKFBOUT001000000000000100
    MMCM1_CLKOUT2B001000000000001000
    MMCM1_CLKFBOUT001000000000010000
    CCIO1_R001000000000100000
    MGT5_L001000000001000000
    RCLK3_L001000000010000000
    MGT5_R001000000100000000
    RCLK3_R001000001000000000
    MMCM0_CLKOUT3010000000000000010
    MMCM0_CLKFBOUTB010000000000000100
    MMCM1_CLKOUT3010000000000001000
    MMCM1_CLKFBOUTB010000000000010000
    CCIO2_R010000000000100000
    MGT6_L010000000001000000
    RCLK4_L010000000010000000
    MGT6_R010000000100000000
    RCLK4_R010000001000000000
    MMCM0_CLKOUT3B100000000000000010
    MMCM0_TMUXOUT100000000000000100
    MMCM1_CLKOUT3B100000000000001000
    MMCM1_TMUXOUT100000000000010000
    CCIO3_R100000000000100000
    MGT7_L100000000001000000
    RCLK5_L100000000010000000
    MGT7_R100000000100000000
    RCLK5_R100000001000000000
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT:MUX.CASCO1[19, 28, 8][19, 29, 8][19, 29, 10][19, 28, 11][19, 29, 12][19, 28, 13][19, 29, 14][19, 28, 15][19, 29, 3][19, 29, 4][19, 28, 4][19, 28, 5][19, 28, 7][19, 29, 6][19, 29, 7][19, 28, 6][19, 29, 5][19, 27, 3]
    CMT:MUX.CASCO10[19, 32, 40][19, 33, 40][19, 33, 42][19, 32, 43][19, 33, 44][19, 32, 45][19, 33, 46][19, 32, 47][19, 33, 35][19, 33, 36][19, 32, 36][19, 32, 37][19, 32, 39][19, 33, 38][19, 33, 39][19, 32, 38][19, 33, 37][19, 31, 35]
    CMT:MUX.CASCO13[19, 28, 56][19, 29, 56][19, 29, 58][19, 28, 59][19, 29, 60][19, 28, 61][19, 29, 62][19, 28, 63][19, 29, 51][19, 29, 52][19, 28, 52][19, 28, 53][19, 28, 55][19, 29, 54][19, 29, 55][19, 28, 54][19, 29, 53][19, 27, 51]
    CMT:MUX.CASCO14[19, 32, 56][19, 33, 56][19, 33, 58][19, 32, 59][19, 33, 60][19, 32, 61][19, 33, 62][19, 32, 63][19, 33, 51][19, 33, 52][19, 32, 52][19, 32, 53][19, 32, 55][19, 33, 54][19, 33, 55][19, 32, 54][19, 33, 53][19, 31, 51]
    CMT:MUX.CASCO17[20, 28, 8][20, 29, 8][20, 29, 10][20, 28, 11][20, 29, 12][20, 28, 13][20, 29, 14][20, 28, 15][20, 29, 3][20, 29, 4][20, 28, 4][20, 28, 5][20, 28, 7][20, 29, 6][20, 29, 7][20, 28, 6][20, 29, 5][20, 27, 3]
    CMT:MUX.CASCO18[20, 32, 8][20, 33, 8][20, 33, 10][20, 32, 11][20, 33, 12][20, 32, 13][20, 33, 14][20, 32, 15][20, 33, 3][20, 33, 4][20, 32, 4][20, 32, 5][20, 32, 7][20, 33, 6][20, 33, 7][20, 32, 6][20, 33, 5][20, 31, 3]
    CMT:MUX.CASCO2[19, 32, 8][19, 33, 8][19, 33, 10][19, 32, 11][19, 33, 12][19, 32, 13][19, 33, 14][19, 32, 15][19, 33, 3][19, 33, 4][19, 32, 4][19, 32, 5][19, 32, 7][19, 33, 6][19, 33, 7][19, 32, 6][19, 33, 5][19, 31, 3]
    CMT:MUX.CASCO21[20, 28, 24][20, 29, 24][20, 29, 26][20, 28, 27][20, 29, 28][20, 28, 29][20, 29, 30][20, 28, 31][20, 29, 19][20, 29, 20][20, 28, 20][20, 28, 21][20, 28, 23][20, 29, 22][20, 29, 23][20, 28, 22][20, 29, 21][20, 27, 19]
    CMT:MUX.CASCO22[20, 32, 24][20, 33, 24][20, 33, 26][20, 32, 27][20, 33, 28][20, 32, 29][20, 33, 30][20, 32, 31][20, 33, 19][20, 33, 20][20, 32, 20][20, 32, 21][20, 32, 23][20, 33, 22][20, 33, 23][20, 32, 22][20, 33, 21][20, 31, 19]
    CMT:MUX.CASCO25[20, 28, 40][20, 29, 40][20, 29, 42][20, 28, 43][20, 29, 44][20, 28, 45][20, 29, 46][20, 28, 47][20, 29, 35][20, 29, 36][20, 28, 36][20, 28, 37][20, 28, 39][20, 29, 38][20, 29, 39][20, 28, 38][20, 29, 37][20, 27, 35]
    CMT:MUX.CASCO26[20, 32, 40][20, 33, 40][20, 33, 42][20, 32, 43][20, 33, 44][20, 32, 45][20, 33, 46][20, 32, 47][20, 33, 35][20, 33, 36][20, 32, 36][20, 32, 37][20, 32, 39][20, 33, 38][20, 33, 39][20, 32, 38][20, 33, 37][20, 31, 35]
    CMT:MUX.CASCO29[20, 28, 56][20, 29, 56][20, 29, 58][20, 28, 59][20, 29, 60][20, 28, 61][20, 29, 62][20, 28, 63][20, 29, 51][20, 29, 52][20, 28, 52][20, 28, 53][20, 28, 55][20, 29, 54][20, 29, 55][20, 28, 54][20, 29, 53][20, 27, 51]
    CMT:MUX.CASCO30[20, 32, 56][20, 33, 56][20, 33, 58][20, 32, 59][20, 33, 60][20, 32, 61][20, 33, 62][20, 32, 63][20, 33, 51][20, 33, 52][20, 32, 52][20, 32, 53][20, 32, 55][20, 33, 54][20, 33, 55][20, 32, 54][20, 33, 53][20, 31, 51]
    CMT:MUX.CASCO5[19, 28, 24][19, 29, 24][19, 29, 26][19, 28, 27][19, 29, 28][19, 28, 29][19, 29, 30][19, 28, 31][19, 29, 19][19, 29, 20][19, 28, 20][19, 28, 21][19, 28, 23][19, 29, 22][19, 29, 23][19, 28, 22][19, 29, 21][19, 27, 19]
    CMT:MUX.CASCO6[19, 32, 24][19, 33, 24][19, 33, 26][19, 32, 27][19, 33, 28][19, 32, 29][19, 33, 30][19, 32, 31][19, 33, 19][19, 33, 20][19, 32, 20][19, 32, 21][19, 32, 23][19, 33, 22][19, 33, 23][19, 32, 22][19, 33, 21][19, 31, 19]
    CMT:MUX.CASCO9[19, 28, 40][19, 29, 40][19, 29, 42][19, 28, 43][19, 29, 44][19, 28, 45][19, 29, 46][19, 28, 47][19, 29, 35][19, 29, 36][19, 28, 36][19, 28, 37][19, 28, 39][19, 29, 38][19, 29, 39][19, 28, 38][19, 29, 37][19, 27, 35]
    NONE000000000000000000
    CASCI000000000000000001
    MMCM0_CLKOUT0000000010000000010
    BUFH_TEST_L000000010000000100
    MMCM1_CLKOUT0000000010000001000
    CCIO0_L000000010000100000
    MGT0_L000000010001000000
    MGT8_L000000010010000000
    MGT0_R000000010100000000
    MGT8_R000000011000000000
    MMCM0_CLKOUT0B000000100000000010
    BUFH_TEST_R000000100000000100
    MMCM1_CLKOUT0B000000100000001000
    GCLK_TEST000000100000010000
    CCIO1_L000000100000100000
    MGT1_L000000100001000000
    MGT9_L000000100010000000
    MGT1_R000000100100000000
    MGT9_R000000101000000000
    MMCM0_CLKOUT1000001000000000010
    MMCM0_CLKOUT4000001000000000100
    MMCM1_CLKOUT1000001000000001000
    MMCM1_CLKOUT4000001000000010000
    CCIO2_L000001000000100000
    MGT2_L000001000001000000
    RCLK0_L000001000010000000
    MGT2_R000001000100000000
    RCLK0_R000001001000000000
    MMCM0_CLKOUT1B000010000000000010
    MMCM0_CLKOUT5000010000000000100
    MMCM1_CLKOUT1B000010000000001000
    MMCM1_CLKOUT5000010000000010000
    CCIO3_L000010000000100000
    MGT3_L000010000001000000
    RCLK1_L000010000010000000
    MGT3_R000010000100000000
    RCLK1_R000010001000000000
    MMCM0_CLKOUT2000100000000000010
    MMCM0_CLKOUT6000100000000000100
    MMCM1_CLKOUT2000100000000001000
    MMCM1_CLKOUT6000100000000010000
    CCIO0_R000100000000100000
    MGT4_L000100000001000000
    RCLK2_L000100000010000000
    MGT4_R000100000100000000
    RCLK2_R000100001000000000
    MMCM0_CLKOUT2B001000000000000010
    MMCM0_CLKFBOUT001000000000000100
    MMCM1_CLKOUT2B001000000000001000
    MMCM1_CLKFBOUT001000000000010000
    CCIO1_R001000000000100000
    MGT5_L001000000001000000
    RCLK3_L001000000010000000
    MGT5_R001000000100000000
    RCLK3_R001000001000000000
    MMCM0_CLKOUT3010000000000000010
    MMCM0_CLKFBOUTB010000000000000100
    MMCM1_CLKOUT3010000000000001000
    MMCM1_CLKFBOUTB010000000000010000
    CCIO2_R010000000000100000
    MGT6_L010000000001000000
    RCLK4_L010000000010000000
    MGT6_R010000000100000000
    RCLK4_R010000001000000000
    MMCM0_CLKOUT3B100000000000000010
    MMCM0_TMUXOUT100000000000000100
    MMCM1_CLKOUT3B100000000000001000
    MMCM1_TMUXOUT100000000000010000
    CCIO3_R100000000000100000
    MGT7_L100000000001000000
    RCLK5_L100000000010000000
    MGT7_R100000000100000000
    RCLK5_R100000001000000000
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT:MUX.BUFH_TEST_L[19, 28, 49][19, 28, 50][19, 29, 49][19, 28, 57][19, 29, 57][19, 28, 58][19, 29, 59][19, 28, 60][19, 29, 61]
    MMCM0:MUX.CLKFBIN_HCLK_L[19, 28, 33][19, 28, 34][19, 29, 33][19, 28, 41][19, 29, 41][19, 28, 42][19, 29, 43][19, 28, 44][19, 29, 45]
    MMCM0:MUX.CLKIN1_HCLK_L[19, 28, 1][19, 28, 2][19, 29, 1][19, 28, 9][19, 29, 9][19, 28, 10][19, 29, 11][19, 28, 12][19, 29, 13]
    MMCM0:MUX.CLKIN2_HCLK_L[19, 28, 17][19, 28, 18][19, 29, 17][19, 28, 25][19, 29, 25][19, 28, 26][19, 29, 27][19, 28, 28][19, 29, 29]
    MMCM1:MUX.CLKFBIN_HCLK_L[19, 31, 33][19, 31, 34][19, 30, 33][19, 31, 41][19, 30, 41][19, 31, 42][19, 30, 43][19, 31, 44][19, 30, 45]
    MMCM1:MUX.CLKIN1_HCLK_L[19, 31, 1][19, 31, 2][19, 30, 1][19, 31, 9][19, 30, 9][19, 31, 10][19, 30, 11][19, 31, 12][19, 30, 13]
    MMCM1:MUX.CLKIN2_HCLK_L[19, 31, 17][19, 31, 18][19, 30, 17][19, 31, 25][19, 30, 25][19, 31, 26][19, 30, 27][19, 31, 28][19, 30, 29]
    NONE000000000
    HCLK0_L001000001
    HCLK1_L001000010
    HCLK2_L001000100
    HCLK3_L001001000
    HCLK4_L001010000
    HCLK5_L001100000
    HCLK6_L010000001
    HCLK7_L010000010
    HCLK8_L010000100
    HCLK9_L010001000
    HCLK10_L010010000
    HCLK11_L010100000
    RCLK0_L100000001
    RCLK1_L100000010
    RCLK2_L100000100
    RCLK3_L100001000
    RCLK4_L100010000
    RCLK5_L100100000
    +
    + + + + +
    MMCM0:MUX.CLKIN1_HCLK[19, 30, 0]
    CLKIN1_HCLK_L0
    CLKIN1_HCLK_R1
    +
    + + + + +
    MMCM0:MUX.CLKIN2_HCLK[19, 30, 16]
    CLKIN2_HCLK_L0
    CLKIN2_HCLK_R1
    +
    + + + + +
    MMCM0:MUX.CLKFBIN_HCLK[19, 30, 32]
    CLKFBIN_HCLK_L0
    CLKFBIN_HCLK_R1
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT:MUX.BUFH_TEST_R[20, 28, 1][20, 28, 2][20, 29, 1][20, 28, 9][20, 29, 9][20, 28, 10][20, 29, 11][20, 28, 12][20, 29, 13]
    MMCM0:MUX.CLKFBIN_HCLK_R[20, 31, 17][20, 31, 18][20, 30, 17][20, 31, 25][20, 30, 25][20, 31, 26][20, 30, 27][20, 31, 28][20, 30, 29]
    MMCM0:MUX.CLKIN1_HCLK_R[20, 31, 49][20, 31, 50][20, 30, 49][20, 31, 57][20, 30, 57][20, 31, 58][20, 30, 59][20, 31, 60][20, 30, 61]
    MMCM0:MUX.CLKIN2_HCLK_R[20, 31, 33][20, 31, 34][20, 30, 33][20, 31, 41][20, 30, 41][20, 31, 42][20, 30, 43][20, 31, 44][20, 30, 45]
    MMCM1:MUX.CLKFBIN_HCLK_R[20, 28, 17][20, 28, 18][20, 29, 17][20, 28, 25][20, 29, 25][20, 28, 26][20, 29, 27][20, 28, 28][20, 29, 29]
    MMCM1:MUX.CLKIN1_HCLK_R[20, 28, 49][20, 28, 50][20, 29, 49][20, 28, 57][20, 29, 57][20, 28, 58][20, 29, 59][20, 28, 60][20, 29, 61]
    MMCM1:MUX.CLKIN2_HCLK_R[20, 28, 33][20, 28, 34][20, 29, 33][20, 28, 41][20, 29, 41][20, 28, 42][20, 29, 43][20, 28, 44][20, 29, 45]
    NONE000000000
    HCLK0_R001000001
    HCLK1_R001000010
    HCLK2_R001000100
    HCLK3_R001001000
    HCLK4_R001010000
    HCLK5_R001100000
    HCLK6_R010000001
    HCLK7_R010000010
    HCLK8_R010000100
    HCLK9_R010001000
    HCLK10_R010010000
    HCLK11_R010100000
    RCLK0_R100000001
    RCLK1_R100000010
    RCLK2_R100000100
    RCLK3_R100001000
    RCLK4_R100010000
    RCLK5_R100100000
    +
    + + + + +
    MMCM1:MUX.CLKFBIN_HCLK[20, 30, 16]
    CLKFBIN_HCLK_R0
    CLKFBIN_HCLK_L1
    +
    + + + + +
    MMCM1:MUX.CLKIN2_HCLK[20, 30, 32]
    CLKIN2_HCLK_R0
    CLKIN2_HCLK_L1
    +
    + + + + +
    MMCM1:MUX.CLKIN1_HCLK[20, 30, 48]
    CLKIN1_HCLK_R0
    CLKIN1_HCLK_L1
    + +
    +

    Tables

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameMMCM:CPMMCM:RESMMCM:LFHF
    HIGH:15150
    HIGH:1015100
    HIGH:1115100
    HIGH:1214120
    HIGH:1315120
    HIGH:1415120
    HIGH:1515120
    HIGH:1615120
    HIGH:1715120
    HIGH:1815120
    HIGH:1915120
    HIGH:215150
    HIGH:2015120
    HIGH:2114120
    HIGH:2214120
    HIGH:2314120
    HIGH:2415100
    HIGH:2513120
    HIGH:261220
    HIGH:2713120
    HIGH:2813120
    HIGH:2915100
    HIGH:315130
    HIGH:3015100
    HIGH:3115100
    HIGH:32720
    HIGH:3312120
    HIGH:3412120
    HIGH:3514100
    HIGH:36620
    HIGH:37620
    HIGH:38620
    HIGH:397120
    HIGH:41590
    HIGH:40620
    HIGH:41440
    HIGH:42440
    HIGH:43440
    HIGH:44440
    HIGH:45440
    HIGH:46440
    HIGH:47380
    HIGH:48380
    HIGH:49380
    HIGH:515140
    HIGH:50380
    HIGH:51380
    HIGH:52380
    HIGH:53380
    HIGH:54380
    HIGH:55380
    HIGH:56380
    HIGH:57380
    HIGH:58380
    HIGH:59380
    HIGH:61510
    HIGH:60380
    HIGH:61380
    HIGH:62380
    HIGH:63380
    HIGH:64380
    HIGH:71510
    HIGH:81560
    HIGH:915100
    LOW:1173
    LOW:10123
    LOW:11123
    LOW:12123
    LOW:132123
    LOW:14143
    LOW:15143
    LOW:16143
    LOW:17143
    LOW:18143
    LOW:19143
    LOW:2153
    LOW:20143
    LOW:21143
    LOW:22143
    LOW:23143
    LOW:24183
    LOW:25183
    LOW:26183
    LOW:27183
    LOW:28183
    LOW:29183
    LOW:31143
    LOW:30183
    LOW:31183
    LOW:32183
    LOW:33183
    LOW:34183
    LOW:35183
    LOW:36183
    LOW:37183
    LOW:38243
    LOW:39243
    LOW:4163
    LOW:40243
    LOW:41243
    LOW:42243
    LOW:43243
    LOW:44243
    LOW:45243
    LOW:46243
    LOW:47243
    LOW:48283
    LOW:49283
    LOW:51103
    LOW:50283
    LOW:51283
    LOW:52283
    LOW:53283
    LOW:54283
    LOW:55283
    LOW:56283
    LOW:57283
    LOW:58283
    LOW:59283
    LOW:61123
    LOW:60283
    LOW:61283
    LOW:62283
    LOW:63283
    LOW:64283
    LOW:71123
    LOW:81123
    LOW:91123
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameMMCM:LOCK_REF_DLYMMCM:LOCK_FB_DLYMMCM:LOCK_CNTMMCM:LOCK_SAT_HIGHMMCM:UNLOCK_CNT
    166100010011
    102828100010011
    11313190010011
    12313182510011
    13313175010011
    14313170010011
    15313165010011
    16313162510011
    17313157510011
    18313155010011
    19313152510011
    266100010011
    20313150010011
    21313147510011
    22313145010011
    23313142510011
    24313140010011
    25313140010011
    26313137510011
    27313135010011
    28313135010011
    29313132510011
    388100010011
    30313132510011
    31313130010011
    32313130010011
    33313130010011
    34313127510011
    35313127510011
    36313127510011
    37313125010011
    38313125010011
    39313125010011
    41111100010011
    40313125010011
    41313125010011
    42313125010011
    43313125010011
    44313125010011
    45313125010011
    46313125010011
    47313125010011
    48313125010011
    49313125010011
    51414100010011
    50313125010011
    51313125010011
    52313125010011
    53313125010011
    54313125010011
    55313125010011
    56313125010011
    57313125010011
    58313125010011
    59313125010011
    61717100010011
    60313125010011
    61313125010011
    62313125010011
    63313125010011
    64313125010011
    71919100010011
    82222100010011
    92525100010011
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    DeviceMMCM:IN_DLY_SET
    [4][3][2][1][0]
    xc6vcx130t11000
    xc6vcx195t11000
    xc6vcx240t11000
    xc6vcx75t11000
    xc6vhx250t11000
    xc6vhx255t11000
    xc6vhx380t11000
    xc6vhx565t11000
    xc6vlx130t11000
    xc6vlx130tl11000
    xc6vlx195t11000
    xc6vlx195tl11000
    xc6vlx240t11000
    xc6vlx240tl11000
    xc6vlx365t11000
    xc6vlx365tl11000
    xc6vlx550t11000
    xc6vlx550tl11000
    xc6vlx75t11000
    xc6vlx75tl11000
    xc6vlx76011111
    xc6vlx760l11111
    xc6vsx315t11000
    xc6vsx315tl11000
    xc6vsx475t11000
    xc6vsx475tl11000
    xq6vlx130t11000
    xq6vlx130tl11000
    xq6vlx240t11000
    xq6vlx240tl11000
    xq6vlx550t11000
    xq6vlx550tl11000
    xq6vsx315t11000
    xq6vsx315tl11000
    xq6vsx475t11000
    xq6vsx475tl11000
    +
    + + + + + + + + + + + + + + \ No newline at end of file diff --git a/xilinx/virtex6/config.html b/xilinx/virtex6/config.html index 88002153..abda1c9f 100644 --- a/xilinx/virtex6/config.html +++ b/xilinx/virtex6/config.html @@ -65,6 +65,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • diff --git a/xilinx/virtex6/dsp.html b/xilinx/virtex6/dsp.html index fcfaa4eb..58ca20f0 100644 --- a/xilinx/virtex6/dsp.html +++ b/xilinx/virtex6/dsp.html @@ -68,6 +68,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • diff --git a/xilinx/virtex6/emac.html b/xilinx/virtex6/emac.html index facdbf70..ecdd99d8 100644 --- a/xilinx/virtex6/emac.html +++ b/xilinx/virtex6/emac.html @@ -20,7 +20,7 @@ - + @@ -65,6 +65,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs @@ -1408,7 +1409,7 @@

    Bitstream - + diff --git a/xilinx/virtex6/geometry.html b/xilinx/virtex6/geometry.html index 059ef54a..04a4ce24 100644 --- a/xilinx/virtex6/geometry.html +++ b/xilinx/virtex6/geometry.html @@ -69,6 +69,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • diff --git a/xilinx/virtex6/gth.html b/xilinx/virtex6/gth.html index 3065e65d..0740a402 100644 --- a/xilinx/virtex6/gth.html +++ b/xilinx/virtex6/gth.html @@ -65,6 +65,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • diff --git a/xilinx/virtex6/gtx.html b/xilinx/virtex6/gtx.html index e7c85231..3bbaf202 100644 --- a/xilinx/virtex6/gtx.html +++ b/xilinx/virtex6/gtx.html @@ -65,6 +65,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • +
  • Clock management tile +
  • Ethernet MACs diff --git a/xilinx/virtex6/interconnect.html b/xilinx/virtex6/interconnect.html index 9db11c31..8122871a 100644 --- a/xilinx/virtex6/interconnect.html +++ b/xilinx/virtex6/interconnect.html @@ -70,6 +70,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • @@ -3007,17 +3008,17 @@

    BitstreamConfiguration Center

  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
  • GTX transceivers
    • @@ -915,41 +916,271 @@

    Bitstream — H 13 -------------------------------------------- 14 -----------------------------------------DCI:PREF_TERM_VCC[0]DCI:PREF_OUTPUT[0]LVDS:LVDSBIAS[15]DCI:PMASK_TERM_VCC[0] +-----------------------------HCLK_IOI:BUF.RCLK0--HCLK_IOI:MUX.RCLK0[2]---HCLK_IOI:BUF.PERF2HCLK_IOI:BUF.PERF3--DCI:PREF_TERM_VCC[0]DCI:PREF_OUTPUT[0]LVDS:LVDSBIAS[15]DCI:PMASK_TERM_VCC[0] 15 -----------------------------------------DCI:PREF_TERM_VCC[1]DCI:PREF_OUTPUT[1]LVDS:LVDSBIAS[14]DCI:NMASK_TERM_SPLIT[0] +-----------------------------HCLK_IOI:BUF.RCLK1--HCLK_IOI:MUX.RCLK0[1]----HCLK_IOI:BUF.PERF1--DCI:PREF_TERM_VCC[1]DCI:PREF_OUTPUT[1]LVDS:LVDSBIAS[14]DCI:NMASK_TERM_SPLIT[0] 16 -----------------------------------------DCI:NREF_OUTPUT[0]DCI:PREF_OUTPUT_HALF[0]LVDS:LVDSBIAS[13]DCI:NMASK_TERM_SPLIT[1] +-----------------------------HCLK_IOI:BUF.RCLK2BUFR0:MUX.I[8]BUFR0:MUX.I[0]HCLK_IOI:MUX.RCLK0[3]---HCLK_IOI:DELAY.IOCLK6HCLK_IOI:BUF.IOCLK6--DCI:NREF_OUTPUT[0]DCI:PREF_OUTPUT_HALF[0]LVDS:LVDSBIAS[13]DCI:NMASK_TERM_SPLIT[1] 17 -----------------------------------------DCI:NREF_OUTPUT[1]DCI:PREF_OUTPUT_HALF[1]LVDS:LVDSBIAS[12]DCI:NMASK_TERM_SPLIT[2] +-----------------------------HCLK_IOI:BUF.RCLK3BUFR0:MUX.I[9]BUFR0:MUX.I[1]HCLK_IOI:MUX.RCLK1[2]----BUFIODQS2:ENABLE--DCI:NREF_OUTPUT[1]DCI:PREF_OUTPUT_HALF[1]LVDS:LVDSBIAS[12]DCI:NMASK_TERM_SPLIT[2] 18 -----------------------------------------DCI:NREF_OUTPUT_HALF[0]DCI:PREF_OUTPUT_HALF[2]LVDS:LVDSBIAS[11]DCI:NMASK_TERM_SPLIT[3] +-----------------------------HCLK_IOI:BUF.RCLK4BUFR0:MUX.I[10]BUFR0:MUX.I[2]HCLK_IOI:MUX.RCLK1[1]BUFR0:BUFR_DIVIDE[1]--HCLK_IOI:DELAY.IOCLK2BUFIODQS2:DQSMASK_ENABLE--DCI:NREF_OUTPUT_HALF[0]DCI:PREF_OUTPUT_HALF[2]LVDS:LVDSBIAS[11]DCI:NMASK_TERM_SPLIT[3] 19 -----------------------------------------DCI:NREF_OUTPUT_HALF[1]DCI:PREF_TERM_SPLIT[0]LVDS:LVDSBIAS[10]DCI:NMASK_TERM_SPLIT[4] +-----------------------------HCLK_IOI:BUF.RCLK5BUFR0:MUX.I[11]BUFR0:MUX.I[3]HCLK_IOI:MUX.RCLK1[3]BUFR0:BUFR_DIVIDE[2]---BUFIODQS3:DQSMASK_ENABLE--DCI:NREF_OUTPUT_HALF[1]DCI:PREF_TERM_SPLIT[0]LVDS:LVDSBIAS[10]DCI:NMASK_TERM_SPLIT[4] 20 -----------------------------------------DCI:NREF_OUTPUT_HALF[2]DCI:PREF_TERM_SPLIT[1]LVDS:LVDSBIAS[9]DCI:NMASK_TERM_SPLIT[5] +---------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.RCLK0[0]HCLK_IOI:BUF.HCLK0BUFR0:MUX.I[12]BUFR0:MUX.I[4]HCLK_IOI:MUX.RCLK2[2]BUFR0:BUFR_DIVIDE[3]--HCLK_IOI:DELAY.IOCLK3BUFIODQS2:MUX.I--DCI:NREF_OUTPUT_HALF[2]DCI:PREF_TERM_SPLIT[1]LVDS:LVDSBIAS[9]DCI:NMASK_TERM_SPLIT[5] 21 ------------------------------------------DCI:PREF_TERM_SPLIT[2]LVDS:LVDSBIAS[8]DCI:PMASK_TERM_SPLIT[0] +---------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.RCLK1[0]HCLK_IOI:BUF.HCLK1BUFR0:MUX.I[13]BUFR0:MUX.I[5]HCLK_IOI:MUX.RCLK2[1]BUFR0:BUFR_DIVIDE[0]---BUFIODQS3:MUX.I---DCI:PREF_TERM_SPLIT[2]LVDS:LVDSBIAS[8]DCI:PMASK_TERM_SPLIT[0] 22 -------------------------------------------LVDS:LVDSBIAS[7]DCI:PMASK_TERM_SPLIT[1] +---------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.RCLK2[0]HCLK_IOI:BUF.HCLK2BUFR0:MUX.I[15]BUFR0:MUX.I[6]HCLK_IOI:MUX.RCLK2[3]BUFR0:ENABLE--HCLK_IOI:DELAY.IOCLK7BUFIODQS3:ENABLE-BUFO0:MUX.I[0]--LVDS:LVDSBIAS[7]DCI:PMASK_TERM_SPLIT[1] 23 -----------------------------------------DCI:NREF_TERM_SPLIT[0]DCI:TEST_ENABLE[1]LVDS:LVDSBIAS[6]DCI:PMASK_TERM_SPLIT[2] +---------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.RCLK3[0]HCLK_IOI:BUF.HCLK3BUFR0:MUX.I[14]BUFR0:MUX.I[7]HCLK_IOI:MUX.RCLK3[2]---HCLK_IOI:BUF.PERF0HCLK_IOI:BUF.IOCLK7-BUFO0:MUX.I[2]DCI:NREF_TERM_SPLIT[0]DCI:TEST_ENABLE[1]LVDS:LVDSBIAS[6]DCI:PMASK_TERM_SPLIT[2] 24 -----------------------------------------DCI:NREF_TERM_SPLIT[1]INTERNAL_VREF:VREF[2]LVDS:LVDSBIAS[5]DCI:PMASK_TERM_SPLIT[3] +---------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.RCLK4[0]HCLK_IOI:BUF.HCLK4BUFR1:MUX.I[8]BUFR1:MUX.I[0]HCLK_IOI:MUX.RCLK3[1]----HCLK_IOI:BUF.IOCLK4-BUFO0:MUX.I[3]DCI:NREF_TERM_SPLIT[1]INTERNAL_VREF:VREF[2]LVDS:LVDSBIAS[5]DCI:PMASK_TERM_SPLIT[3] 25 -----------------------------------------DCI:NREF_TERM_SPLIT[2]-LVDS:LVDSBIAS[4]DCI:PMASK_TERM_SPLIT[4] +---------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.RCLK5[0]HCLK_IOI:BUF.HCLK5BUFR1:MUX.I[9]BUFR1:MUX.I[1]HCLK_IOI:MUX.RCLK3[3]---HCLK_IOI:DELAY.IOCLK4BUFIODQS0:ENABLE-BUFO1:MUX.I[2]DCI:NREF_TERM_SPLIT[2]-LVDS:LVDSBIAS[4]DCI:PMASK_TERM_SPLIT[4] 26 -----------------------------------------INTERNAL_VREF:VREF[0]-LVDS:LVDSBIAS[3]DCI:PMASK_TERM_SPLIT[5] +---------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:UNUSED.RCLK0HCLK_IOI:BUF.HCLK6BUFR1:MUX.I[10]BUFR1:MUX.I[2]HCLK_IOI:MUX.RCLK4[2]----BUFIODQS0:DQSMASK_ENABLE-BUFO1:MUX.I[0]INTERNAL_VREF:VREF[0]-LVDS:LVDSBIAS[3]DCI:PMASK_TERM_SPLIT[5] 27 -----------------------------------------DCI:CASCADE_FROM_ABOVE-LVDS:LVDSBIAS[2]DCI:PMASK_TERM_VCC[1] +---------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:UNUSED.RCLK1HCLK_IOI:BUF.HCLK7BUFR1:MUX.I[11]BUFR1:MUX.I[3]HCLK_IOI:MUX.RCLK4[1]BUFR1:ENABLE--HCLK_IOI:DELAY.IOCLK0BUFIODQS1:DQSMASK_ENABLE-BUFO1:MUX.I[3]DCI:CASCADE_FROM_ABOVE-LVDS:LVDSBIAS[2]DCI:PMASK_TERM_VCC[1] 28 -----------------------------------------DCI:CASCADE_FROM_BELOWLVDS:LVDSBIAS[16]LVDS:LVDSBIAS[1]DCI:PMASK_TERM_VCC[2] +---------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:UNUSED.RCLK2HCLK_IOI:BUF.HCLK8BUFR1:MUX.I[12]BUFR1:MUX.I[4]HCLK_IOI:MUX.RCLK4[3]BUFR1:BUFR_DIVIDE[1]---BUFIODQS0:MUX.I-HCLK_IOI:BUF.VOCLK0DCI:CASCADE_FROM_BELOWLVDS:LVDSBIAS[16]LVDS:LVDSBIAS[1]DCI:PMASK_TERM_VCC[2] 29 -----------------------------------------INTERNAL_VREF:VREF[4]INTERNAL_VREF:VREF[3]DCI:DYNAMIC_ENABLEDCI:PMASK_TERM_VCC[3] +---------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:UNUSED.RCLK3HCLK_IOI:BUF.HCLK9BUFR1:MUX.I[13]BUFR1:MUX.I[5]HCLK_IOI:MUX.RCLK5[2]BUFR1:BUFR_DIVIDE[2]--HCLK_IOI:DELAY.IOCLK1BUFIODQS1:MUX.I-HCLK_IOI:BUF.VOCLK1INTERNAL_VREF:VREF[4]INTERNAL_VREF:VREF[3]DCI:DYNAMIC_ENABLEDCI:PMASK_TERM_VCC[3] 30 -----------------------------------------INTERNAL_VREF:VREF[5]INTERNAL_VREF:VREF[1]LVDS:LVDSBIAS[0]DCI:PMASK_TERM_VCC[4] +---------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:UNUSED.RCLK4HCLK_IOI:BUF.HCLK10BUFR1:MUX.I[15]BUFR1:MUX.I[6]HCLK_IOI:MUX.RCLK5[1]BUFR1:BUFR_DIVIDE[3]---BUFIODQS1:ENABLE-BUFO0:MUX.I[1]INTERNAL_VREF:VREF[5]INTERNAL_VREF:VREF[1]LVDS:LVDSBIAS[0]DCI:PMASK_TERM_VCC[4] 31 -----------------------------------------DCI:TEST_ENABLE[0]DCI:QUIETDCI:ENABLEDCI:PMASK_TERM_VCC[5] +---------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:UNUSED.RCLK5HCLK_IOI:BUF.HCLK11BUFR1:MUX.I[14]BUFR1:MUX.I[7]HCLK_IOI:MUX.RCLK5[3]BUFR1:BUFR_DIVIDE[0]--HCLK_IOI:DELAY.IOCLK5HCLK_IOI:BUF.IOCLK5-BUFO1:MUX.I[1]DCI:TEST_ENABLE[0]DCI:QUIETDCI:ENABLEDCI:PMASK_TERM_VCC[5] + +
    + + + + + + + + + + + + + + +
    IDELAYCTRL:MUX.REFCLK[0, 27, 20][0, 27, 21][0, 27, 22][0, 27, 23][0, 27, 24][0, 27, 25][0, 27, 26][0, 27, 27][0, 27, 28][0, 27, 29][0, 27, 30][0, 27, 31]
    HCLK0000000000001
    HCLK1000000000010
    HCLK2000000000100
    HCLK3000000001000
    HCLK4000000010000
    HCLK5000000100000
    HCLK6000001000000
    HCLK7000010000000
    HCLK8000100000000
    HCLK9001000000000
    HCLK10010000000000
    HCLK11100000000000
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + +
    HCLK_IOI:MUX.RCLK0[0, 32, 16][0, 32, 14][0, 32, 15][0, 28, 20]
    HCLK_IOI:MUX.RCLK1[0, 32, 19][0, 32, 17][0, 32, 18][0, 28, 21]
    HCLK_IOI:MUX.RCLK2[0, 32, 22][0, 32, 20][0, 32, 21][0, 28, 22]
    HCLK_IOI:MUX.RCLK3[0, 32, 25][0, 32, 23][0, 32, 24][0, 28, 23]
    HCLK_IOI:MUX.RCLK4[0, 32, 28][0, 32, 26][0, 32, 27][0, 28, 24]
    HCLK_IOI:MUX.RCLK5[0, 32, 31][0, 32, 29][0, 32, 30][0, 28, 25]
    NONE0000
    VRCLK0_N0001
    VRCLK00011
    VRCLK1_N0101
    VRCLK10111
    VRCLK0_S1001
    VRCLK1_S1101
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFIODQS0:DQSMASK_ENABLE[0, 37, 26]
    BUFIODQS0:ENABLE[0, 37, 25]
    BUFIODQS1:DQSMASK_ENABLE[0, 37, 27]
    BUFIODQS1:ENABLE[0, 37, 30]
    BUFIODQS2:DQSMASK_ENABLE[0, 37, 18]
    BUFIODQS2:ENABLE[0, 37, 17]
    BUFIODQS3:DQSMASK_ENABLE[0, 37, 19]
    BUFIODQS3:ENABLE[0, 37, 22]
    BUFR0:ENABLE[0, 33, 22]
    BUFR1:ENABLE[0, 33, 27]
    DCI:CASCADE_FROM_ABOVE[0, 40, 27]
    DCI:CASCADE_FROM_BELOW[0, 40, 28]
    DCI:DYNAMIC_ENABLE[0, 42, 29]
    DCI:ENABLE[0, 42, 31]
    DCI:QUIET[0, 41, 31]
    HCLK_IOI:BUF.HCLK0[0, 29, 20]
    HCLK_IOI:BUF.HCLK1[0, 29, 21]
    HCLK_IOI:BUF.HCLK10[0, 29, 30]
    HCLK_IOI:BUF.HCLK11[0, 29, 31]
    HCLK_IOI:BUF.HCLK2[0, 29, 22]
    HCLK_IOI:BUF.HCLK3[0, 29, 23]
    HCLK_IOI:BUF.HCLK4[0, 29, 24]
    HCLK_IOI:BUF.HCLK5[0, 29, 25]
    HCLK_IOI:BUF.HCLK6[0, 29, 26]
    HCLK_IOI:BUF.HCLK7[0, 29, 27]
    HCLK_IOI:BUF.HCLK8[0, 29, 28]
    HCLK_IOI:BUF.HCLK9[0, 29, 29]
    HCLK_IOI:BUF.IOCLK4[0, 37, 24]
    HCLK_IOI:BUF.IOCLK5[0, 37, 31]
    HCLK_IOI:BUF.IOCLK6[0, 37, 16]
    HCLK_IOI:BUF.IOCLK7[0, 37, 23]
    HCLK_IOI:BUF.PERF0[0, 36, 23]
    HCLK_IOI:BUF.PERF1[0, 37, 15]
    HCLK_IOI:BUF.PERF2[0, 36, 14]
    HCLK_IOI:BUF.PERF3[0, 37, 14]
    HCLK_IOI:BUF.RCLK0[0, 29, 14]
    HCLK_IOI:BUF.RCLK1[0, 29, 15]
    HCLK_IOI:BUF.RCLK2[0, 29, 16]
    HCLK_IOI:BUF.RCLK3[0, 29, 17]
    HCLK_IOI:BUF.RCLK4[0, 29, 18]
    HCLK_IOI:BUF.RCLK5[0, 29, 19]
    HCLK_IOI:BUF.VOCLK0[0, 39, 28]
    HCLK_IOI:BUF.VOCLK1[0, 39, 29]
    HCLK_IOI:DELAY.IOCLK0[0, 36, 27]
    HCLK_IOI:DELAY.IOCLK1[0, 36, 29]
    HCLK_IOI:DELAY.IOCLK2[0, 36, 18]
    HCLK_IOI:DELAY.IOCLK3[0, 36, 20]
    HCLK_IOI:DELAY.IOCLK4[0, 36, 25]
    HCLK_IOI:DELAY.IOCLK5[0, 36, 31]
    HCLK_IOI:DELAY.IOCLK6[0, 36, 16]
    HCLK_IOI:DELAY.IOCLK7[0, 36, 22]
    HCLK_IOI:UNUSED.RCLK0[0, 28, 26]
    HCLK_IOI:UNUSED.RCLK1[0, 28, 27]
    HCLK_IOI:UNUSED.RCLK2[0, 28, 28]
    HCLK_IOI:UNUSED.RCLK3[0, 28, 29]
    HCLK_IOI:UNUSED.RCLK4[0, 28, 30]
    HCLK_IOI:UNUSED.RCLK5[0, 28, 31]
    Non-inverted[0]
    +
    +
    + + + + + + + + + + + + + + + + + + + + +
    BUFR0:MUX.I[0, 30, 22][0, 30, 23][0, 30, 21][0, 30, 20][0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 31, 23][0, 31, 22][0, 31, 21][0, 31, 20][0, 31, 19][0, 31, 18][0, 31, 17][0, 31, 16]
    BUFR1:MUX.I[0, 30, 30][0, 30, 31][0, 30, 29][0, 30, 28][0, 30, 27][0, 30, 26][0, 30, 25][0, 30, 24][0, 31, 31][0, 31, 30][0, 31, 29][0, 31, 28][0, 31, 27][0, 31, 26][0, 31, 25][0, 31, 24]
    NONE0000000000000000
    BUFIO0_I0000000000000001
    BUFIO1_I0000000000000010
    BUFIO2_I0000000000000100
    BUFIO3_I0000000000001000
    MGT00000000000010000
    MGT10000000000100000
    MGT20000000001000000
    MGT30000000010000000
    MGT40000000100000000
    MGT50000001000000000
    MGT60000010000000000
    MGT70000100000000000
    MGT80001000000000000
    MGT90010000000000000
    CKINT00100000000000000
    CKINT11000000000000000
    +
    +
    + + + + + + + + + + + + +
    BUFR0:BUFR_DIVIDE[0, 33, 20][0, 33, 19][0, 33, 18][0, 33, 21]
    BUFR1:BUFR_DIVIDE[0, 33, 30][0, 33, 29][0, 33, 28][0, 33, 31]
    BYPASS0000
    10001
    20011
    30101
    40111
    51001
    61011
    71101
    81111
    +
    + + + + +
    BUFIODQS2:MUX.I[0, 37, 20]
    CCIO0
    PERF31
    +
    + + + + +
    BUFIODQS3:MUX.I[0, 37, 21]
    CCIO0
    PERF21
    +
    + + + + +
    BUFIODQS0:MUX.I[0, 37, 28]
    CCIO0
    PERF11
    +
    + + + + +
    BUFIODQS1:MUX.I[0, 37, 29]
    CCIO0
    PERF01
    +
    + + + + + +
    BUFO0:MUX.I[0, 39, 24][0, 39, 23][0, 39, 30][0, 39, 22]
    VOCLK00000
    VOCLK0_S0011
    VOCLK0_N1100
    +
    + + + + +
    BUFO1:MUX.I[0, 39, 27][0, 39, 25][0, 39, 31][0, 39, 26]
    VOCLK10000
    VOCLK1_S0011
    VOCLK1_N1100
    @@ -983,19 +1214,6 @@

    Bitstream — H 1100010001 1250100001 -
    -
    -
    -
    -
    - - - - - - - -
    DCI:CASCADE_FROM_ABOVE[0, 40, 27]
    DCI:CASCADE_FROM_BELOW[0, 40, 28]
    DCI:DYNAMIC_ENABLE[0, 42, 29]
    DCI:ENABLE[0, 42, 31]
    DCI:QUIET[0, 41, 31]
    Non-inverted[0]
    diff --git a/xilinx/virtex6/pcie.html b/xilinx/virtex6/pcie.html index 84379084..902f6639 100644 --- a/xilinx/virtex6/pcie.html +++ b/xilinx/virtex6/pcie.html @@ -65,6 +65,7 @@
  • Input/Output
  • Configuration Center
  • Clock interconnect
    • +
  • Clock management tile
  • Ethernet MACs
  • PCI Express cores
    • diff --git a/xilinx/virtex7/center.html b/xilinx/virtex7/center.html new file mode 100644 index 00000000..22da3b5c --- /dev/null +++ b/xilinx/virtex7/center.html @@ -0,0 +1,1399 @@ + + + + + + + Configuration Center — Project Combine documentation + + + + + + + + + + + + + + + + + +
    + + +
    + +
    +
    +
    + +
    +
    +
    +
    + +
    +

    Configuration Center

    +
    +

    Todo

    +

    document

    +
    +
    +

    Bitstream

    +
    LVDS:LVDSBIAS[0, 41, 28][0, 42, 14][0, 42, 15][0, 42, 16][0, 42, 17][0, 42, 18][0, 42, 19][0, 42, 20][0, 42, 21][0, 42, 22][0, 42, 23][0, 42, 24][0, 42, 25][0, 42, 26][0, 42, 27][0, 42, 28][0, 42, 30]
    + +
    CFG bittile 0
    RowColumn
    + + +
    CFG bittile 1
    RowColumn
    + + +
    CFG bittile 2
    RowColumn
    + + +
    CFG bittile 3
    RowColumn
    + + +
    CFG bittile 4
    RowColumn
    + + +
    CFG bittile 5
    RowColumn
    + + +
    CFG bittile 6
    RowColumn
    + + +
    CFG bittile 7
    RowColumn
    + + +
    CFG bittile 8
    RowColumn
    + + +
    CFG bittile 9
    RowColumn
    + + +
    CFG bittile 10
    RowColumn
    + + +
    CFG bittile 11
    RowColumn
    + + +
    CFG bittile 12
    RowColumn
    + + +
    CFG bittile 13
    RowColumn
    + + +
    CFG bittile 14
    RowColumn
    + + +
    CFG bittile 15
    RowColumn
    + + +
    CFG bittile 16
    RowColumn
    + + +
    CFG bittile 17
    RowColumn
    + + +
    CFG bittile 18
    RowColumn
    + + +
    CFG bittile 19
    RowColumn
    + + +
    CFG bittile 20
    RowColumn
    + + +
    CFG bittile 21
    RowColumn
    + + +
    CFG bittile 22
    RowColumn
    + + +
    CFG bittile 23
    RowColumn
    + + +
    CFG bittile 24
    RowColumn
    + + +
    CFG bittile 25
    RowColumn
    + + +
    CFG bittile 26
    RowColumn
    + + +
    CFG bittile 27
    RowColumn
    + + +
    CFG bittile 28
    RowColumn
    + + +
    CFG bittile 29
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CFG bittile 30
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1----------------------------
    2----------------------------
    3----------------------------
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16----------------------------
    17----------------------------
    18----------------------------
    19----------------------------
    20----------------------------
    21----------------------------
    22----------------------------
    23----------------------------
    24----------------------------
    25----------------------------
    26----------------------------
    27----------------------------
    28----------------------------
    29----------------------------
    30----------------------------
    31----------------------------
    32----------------------------
    33----------------------------
    34----------------------------
    35----------------------------
    36----------------------------
    37----------------------------
    38----------------------------
    39----------------------------
    40----------------------------
    41----------------------------
    42----------------------------
    43----------------------------
    44----------------------------
    45----------------------------
    46----------------------------
    47----------------------------
    48----------------------------
    49----------------------------
    50---------------------------MISC:M0PIN[1]
    51----------------------------
    52----------------------------
    53--------------------------MISC:M0PIN[0]-
    54----------------------------
    55---------------------------MISC:M1PIN[1]
    56----------------------------
    57----------------------------
    58--------------------------MISC:M1PIN[0]-
    59----------------------------
    60---------------------------MISC:M2PIN[1]
    61----------------------------
    62----------------------------
    63---------------------------MISC:M2PIN[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CFG bittile 31
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1----------------------------
    2----------------------------
    3----------------------------
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16----------------------------
    17----------------------------
    18----------------------------
    19----------------------------
    20----------------------------
    21----------------------------
    22----------------------------
    23----------------------------
    24----------------------------
    25----------------------------
    26----------------------------
    27----------------------------
    28----------------------------
    29----------------------------
    30----------------------------
    31----------------------------
    32----------------------------
    33----------------------------
    34----------------------------
    35----------------------------
    36----------------------------
    37----------------------------
    38----------------------------
    39----------------------------
    40----------------------------
    41----------------------------
    42--------------------------MISC:PROGPIN-
    43----------------------------
    44---------------------------MISC:INITPIN
    45----------------------------
    46----------------------------
    47---------------------------MISC:DONEPIN
    48----------------------------
    49----------------------------
    50---------------------------MISC:TDIPIN[1]
    51----------------------------
    52----------------------------
    53--------------------------MISC:TDIPIN[0]-
    54----------------------------
    55---------------------------MISC:TMSPIN[1]
    56----------------------------
    57----------------------------
    58--------------------------MISC:TMSPIN[0]-
    59----------------------------
    60---------------------------MISC:TDOPIN[1]
    61----------------------------
    62----------------------------
    63---------------------------MISC:TDOPIN[0]
    + + +
    CFG bittile 32
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CFG bittile 33
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1----------------------------
    2----------------------------
    3----------------------------
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13--------------------------STARTUP:KEY_CLEAR_ENABLE[0]-
    14---------------------------STARTUP:KEY_CLEAR_ENABLE[1]
    15---------------------------STARTUP:KEY_CLEAR_ENABLE[2]
    16----------------------------
    17--------------------------STARTUP:GTS_SYNCSTARTUP:GSR_SYNC
    18--------------------------BSCAN0:ENABLEBSCAN1:ENABLE
    19--------------------------BSCAN2:ENABLEBSCAN3:ENABLE
    20---------------------------DCIRESET:ENABLE[2]
    21--------------------------DCIRESET:ENABLE[0]-
    22--------------------------DCIRESET:ENABLE[1]-
    23----------------------------
    24----------------------------
    25----------------------------
    26----------------------------
    27----------------------------
    28----------------------------
    29----------------------------
    30----------------------------
    31----------------------------
    32--------------------------~BSCAN_COMMON:USERID[0]~BSCAN_COMMON:USERID[1]
    33--------------------------~BSCAN_COMMON:USERID[2]~BSCAN_COMMON:USERID[3]
    34--------------------------~BSCAN_COMMON:USERID[4]~BSCAN_COMMON:USERID[5]
    35--------------------------~BSCAN_COMMON:USERID[6]~BSCAN_COMMON:USERID[7]
    36--------------------------~BSCAN_COMMON:USERID[8]~BSCAN_COMMON:USERID[9]
    37--------------------------~BSCAN_COMMON:USERID[10]~BSCAN_COMMON:USERID[11]
    38--------------------------~BSCAN_COMMON:USERID[12]~BSCAN_COMMON:USERID[13]
    39--------------------------~BSCAN_COMMON:USERID[14]~BSCAN_COMMON:USERID[15]
    40--------------------------~BSCAN_COMMON:USERID[16]~BSCAN_COMMON:USERID[17]
    41--------------------------~BSCAN_COMMON:USERID[18]~BSCAN_COMMON:USERID[19]
    42--------------------------~BSCAN_COMMON:USERID[20]~BSCAN_COMMON:USERID[21]
    43--------------------------~BSCAN_COMMON:USERID[22]~BSCAN_COMMON:USERID[23]
    44--------------------------~BSCAN_COMMON:USERID[24]~BSCAN_COMMON:USERID[25]
    45--------------------------~BSCAN_COMMON:USERID[26]~BSCAN_COMMON:USERID[27]
    46--------------------------~BSCAN_COMMON:USERID[28]~BSCAN_COMMON:USERID[29]
    47--------------------------~BSCAN_COMMON:USERID[30]~BSCAN_COMMON:USERID[31]
    48----------------------------
    49---------------------------CFG_IO_ACCESS:ENABLE[2]
    50--------------------------CFG_IO_ACCESS:ENABLE[0]-
    51--------------------------CFG_IO_ACCESS:ENABLE[1]-
    52--------------------------STARTUP:USRCCLK_ENABLE[0]STARTUP:PROG_USR[2]
    53--------------------------STARTUP:PROG_USR[0]STARTUP:USRCCLK_ENABLE[1]
    54--------------------------STARTUP:PROG_USR[1]STARTUP:USRCCLK_ENABLE[2]
    55--------------------------ICAP_COMMON:ICAP_WIDTH[3]STARTUP:GTS_GSR_ENABLE[2]
    56--------------------------STARTUP:GTS_GSR_ENABLE[0]ICAP_COMMON:ICAP_WIDTH[4]
    57--------------------------STARTUP:GTS_GSR_ENABLE[1]ICAP_COMMON:ICAP_WIDTH[5]
    58--------------------------BSCAN_COMMON:DISABLE_JTAG[0]ICAP_COMMON:ICAP_WIDTH[2]
    59--------------------------ICAP_COMMON:ICAP_WIDTH[0]BSCAN_COMMON:DISABLE_JTAG[1]
    60--------------------------ICAP_COMMON:ICAP_WIDTH[1]BSCAN_COMMON:DISABLE_JTAG[2]
    61--------------------------ICAP0:ENABLE[0]ICAP1:ENABLE[2]
    62--------------------------ICAP1:ENABLE[0]ICAP0:ENABLE[1]
    63--------------------------ICAP1:ENABLE[1]ICAP0:ENABLE[2]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CFG bittile 34
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1----------------------------
    2---------------------------DNA_PORT:ENABLE[1]
    3----------------------------
    4----------------------------
    5--------------------------DNA_PORT:ENABLE[0]-
    6----------------------------
    7---------------------------DNA_PORT:ENABLE[2]
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16----------------------------
    17----------------------------
    18----------------------------
    19----------------------------
    20----------------------------
    21----------------------------
    22----------------------------
    23----------------------------
    24----------------------------
    25--------------------------MISC:TCKPIN[1]-
    26----------------------------
    27---------------------------MISC:TCKPIN[0]
    28----------------------------
    29----------------------------
    30----------------------------
    31---------------------------MISC:CCLKPIN
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + +
    MISC:M0PIN[30, 27, 50][30, 26, 53]
    MISC:M1PIN[30, 27, 55][30, 26, 58]
    MISC:M2PIN[30, 27, 60][30, 27, 63]
    MISC:TCKPIN[34, 26, 25][34, 27, 27]
    MISC:TDIPIN[31, 27, 50][31, 26, 53]
    MISC:TDOPIN[31, 27, 60][31, 27, 63]
    MISC:TMSPIN[31, 27, 55][31, 26, 58]
    PULLUP00
    PULLNONE01
    PULLDOWN11
    +
    +
    +
    +
    + + + + + + + +
    MISC:CCLKPIN[34, 27, 31]
    MISC:DONEPIN[31, 27, 47]
    MISC:INITPIN[31, 27, 44]
    MISC:PROGPIN[31, 26, 42]
    PULLUP0
    PULLNONE1
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + +
    BSCAN_COMMON:DISABLE_JTAG[33, 27, 60][33, 27, 59][33, 26, 58]
    CFG_IO_ACCESS:ENABLE[33, 27, 49][33, 26, 51][33, 26, 50]
    DCIRESET:ENABLE[33, 27, 20][33, 26, 22][33, 26, 21]
    DNA_PORT:ENABLE[34, 27, 7][34, 27, 2][34, 26, 5]
    ICAP0:ENABLE[33, 27, 63][33, 27, 62][33, 26, 61]
    ICAP1:ENABLE[33, 27, 61][33, 26, 63][33, 26, 62]
    STARTUP:GTS_GSR_ENABLE[33, 27, 55][33, 26, 57][33, 26, 56]
    STARTUP:KEY_CLEAR_ENABLE[33, 27, 15][33, 27, 14][33, 26, 13]
    STARTUP:PROG_USR[33, 27, 52][33, 26, 54][33, 26, 53]
    STARTUP:USRCCLK_ENABLE[33, 27, 54][33, 27, 53][33, 26, 52]
    Non-inverted[2][1][0]
    +
    +
    +
    +
    +
    +
    + + + + + + + + +
    BSCAN0:ENABLE[33, 26, 18]
    BSCAN1:ENABLE[33, 27, 18]
    BSCAN2:ENABLE[33, 26, 19]
    BSCAN3:ENABLE[33, 27, 19]
    STARTUP:GSR_SYNC[33, 27, 17]
    STARTUP:GTS_SYNC[33, 26, 17]
    Non-inverted[0]
    +
    + + + +
    BSCAN_COMMON:USERID[33, 27, 47][33, 26, 47][33, 27, 46][33, 26, 46][33, 27, 45][33, 26, 45][33, 27, 44][33, 26, 44][33, 27, 43][33, 26, 43][33, 27, 42][33, 26, 42][33, 27, 41][33, 26, 41][33, 27, 40][33, 26, 40][33, 27, 39][33, 26, 39][33, 27, 38][33, 26, 38][33, 27, 37][33, 26, 37][33, 27, 36][33, 26, 36][33, 27, 35][33, 26, 35][33, 27, 34][33, 26, 34][33, 27, 33][33, 26, 33][33, 27, 32][33, 26, 32]
    Inverted~[31]~[30]~[29]~[28]~[27]~[26]~[25]~[24]~[23]~[22]~[21]~[20]~[19]~[18]~[17]~[16]~[15]~[14]~[13]~[12]~[11]~[10]~[9]~[8]~[7]~[6]~[5]~[4]~[3]~[2]~[1]~[0]
    +
    + + + + + +
    ICAP_COMMON:ICAP_WIDTH[33, 27, 57][33, 27, 56][33, 26, 55][33, 27, 58][33, 26, 60][33, 26, 59]
    X32000000
    X8000111
    X16111000
    + +
    +

    XADC

    + + +
    XADC bittile 0
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    XADC bittile 1
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------XADC:INIT_40[0]XADC:INIT_40[1]
    1----------------------------XADC:INIT_40[2]XADC:INIT_40[3]
    2----------------------------XADC:INIT_40[4]XADC:INIT_40[5]
    3----------------------------XADC:INIT_40[6]XADC:INIT_40[7]
    4----------------------------XADC:INIT_40[8]XADC:INIT_40[9]
    5----------------------------XADC:INIT_40[10]XADC:INIT_40[11]
    6----------------------------XADC:INIT_40[12]XADC:INIT_40[13]
    7----------------------------XADC:INIT_40[14]XADC:INIT_40[15]
    8----------------------------XADC:INIT_41[0]XADC:INIT_41[1]
    9----------------------------XADC:INIT_41[2]XADC:INIT_41[3]
    10----------------------------XADC:INIT_41[4]XADC:INIT_41[5]
    11----------------------------XADC:INIT_41[6]XADC:INIT_41[7]
    12----------------------------XADC:INIT_41[8]XADC:INIT_41[9]
    13----------------------------XADC:INIT_41[10]XADC:INIT_41[11]
    14----------------------------XADC:INIT_41[12]XADC:INIT_41[13]
    15----------------------------XADC:INIT_41[14]XADC:INIT_41[15]
    16----------------------------XADC:INIT_42[0]XADC:INIT_42[1]
    17----------------------------XADC:INIT_42[2]XADC:INIT_42[3]
    18----------------------------XADC:INIT_42[4]XADC:INIT_42[5]
    19----------------------------XADC:INIT_42[6]XADC:INIT_42[7]
    20----------------------------XADC:INIT_42[8]XADC:INIT_42[9]
    21----------------------------XADC:INIT_42[10]XADC:INIT_42[11]
    22----------------------------XADC:INIT_42[12]XADC:INIT_42[13]
    23----------------------------XADC:INIT_42[14]XADC:INIT_42[15]
    24----------------------------XADC:INIT_43[0]XADC:INIT_43[1]
    25----------------------------XADC:INIT_43[2]XADC:INIT_43[3]
    26----------------------------XADC:INIT_43[4]XADC:INIT_43[5]
    27----------------------------XADC:INIT_43[6]XADC:INIT_43[7]
    28----------------------------XADC:INIT_43[8]XADC:INIT_43[9]
    29----------------------------XADC:INIT_43[10]XADC:INIT_43[11]
    30----------------------------XADC:INIT_43[12]XADC:INIT_43[13]
    31----------------------------XADC:INIT_43[14]XADC:INIT_43[15]
    32----------------------------XADC:INIT_44[0]XADC:INIT_44[1]
    33----------------------------XADC:INIT_44[2]XADC:INIT_44[3]
    34----------------------------XADC:INIT_44[4]XADC:INIT_44[5]
    35----------------------------XADC:INIT_44[6]XADC:INIT_44[7]
    36----------------------------XADC:INIT_44[8]XADC:INIT_44[9]
    37----------------------------XADC:INIT_44[10]XADC:INIT_44[11]
    38----------------------------XADC:INIT_44[12]XADC:INIT_44[13]
    39----------------------------XADC:INIT_44[14]XADC:INIT_44[15]
    40----------------------------XADC:INIT_45[0]XADC:INIT_45[1]
    41----------------------------XADC:INIT_45[2]XADC:INIT_45[3]
    42----------------------------XADC:INIT_45[4]XADC:INIT_45[5]
    43----------------------------XADC:INIT_45[6]XADC:INIT_45[7]
    44----------------------------XADC:INIT_45[8]XADC:INIT_45[9]
    45----------------------------XADC:INIT_45[10]XADC:INIT_45[11]
    46----------------------------XADC:INIT_45[12]XADC:INIT_45[13]
    47----------------------------XADC:INIT_45[14]XADC:INIT_45[15]
    48----------------------------XADC:INIT_46[0]XADC:INIT_46[1]
    49----------------------------XADC:INIT_46[2]XADC:INIT_46[3]
    50----------------------------XADC:INIT_46[4]XADC:INIT_46[5]
    51----------------------------XADC:INIT_46[6]XADC:INIT_46[7]
    52----------------------------XADC:INIT_46[8]XADC:INIT_46[9]
    53----------------------------XADC:INIT_46[10]XADC:INIT_46[11]
    54----------------------------XADC:INIT_46[12]XADC:INIT_46[13]
    55----------------------------XADC:INIT_46[14]XADC:INIT_46[15]
    56----------------------------XADC:INIT_47[0]XADC:INIT_47[1]
    57----------------------------XADC:INIT_47[2]XADC:INIT_47[3]
    58----------------------------XADC:INIT_47[4]XADC:INIT_47[5]
    59----------------------------XADC:INIT_47[6]XADC:INIT_47[7]
    60----------------------------XADC:INIT_47[8]XADC:INIT_47[9]
    61----------------------------XADC:INIT_47[10]XADC:INIT_47[11]
    62----------------------------XADC:INIT_47[12]XADC:INIT_47[13]
    63----------------------------XADC:INIT_47[14]XADC:INIT_47[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    XADC bittile 2
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------XADC:INIT_48[0]XADC:INIT_48[1]
    1----------------------------XADC:INIT_48[2]XADC:INIT_48[3]
    2----------------------------XADC:INIT_48[4]XADC:INIT_48[5]
    3----------------------------XADC:INIT_48[6]XADC:INIT_48[7]
    4----------------------------XADC:INIT_48[8]XADC:INIT_48[9]
    5----------------------------XADC:INIT_48[10]XADC:INIT_48[11]
    6----------------------------XADC:INIT_48[12]XADC:INIT_48[13]
    7----------------------------XADC:INIT_48[14]XADC:INIT_48[15]
    8----------------------------XADC:INIT_49[0]XADC:INIT_49[1]
    9----------------------------XADC:INIT_49[2]XADC:INIT_49[3]
    10----------------------------XADC:INIT_49[4]XADC:INIT_49[5]
    11----------------------------XADC:INIT_49[6]XADC:INIT_49[7]
    12----------------------------XADC:INIT_49[8]XADC:INIT_49[9]
    13----------------------------XADC:INIT_49[10]XADC:INIT_49[11]
    14----------------------------XADC:INIT_49[12]XADC:INIT_49[13]
    15----------------------------XADC:INIT_49[14]XADC:INIT_49[15]
    16----------------------------XADC:INIT_4A[0]XADC:INIT_4A[1]
    17----------------------------XADC:INIT_4A[2]XADC:INIT_4A[3]
    18----------------------------XADC:INIT_4A[4]XADC:INIT_4A[5]
    19----------------------------XADC:INIT_4A[6]XADC:INIT_4A[7]
    20----------------------------XADC:INIT_4A[8]XADC:INIT_4A[9]
    21----------------------------XADC:INIT_4A[10]XADC:INIT_4A[11]
    22----------------------------XADC:INIT_4A[12]XADC:INIT_4A[13]
    23----------------------------XADC:INIT_4A[14]XADC:INIT_4A[15]
    24----------------------------XADC:INIT_4B[0]XADC:INIT_4B[1]
    25----------------------------XADC:INIT_4B[2]XADC:INIT_4B[3]
    26----------------------------XADC:INIT_4B[4]XADC:INIT_4B[5]
    27----------------------------XADC:INIT_4B[6]XADC:INIT_4B[7]
    28----------------------------XADC:INIT_4B[8]XADC:INIT_4B[9]
    29----------------------------XADC:INIT_4B[10]XADC:INIT_4B[11]
    30----------------------------XADC:INIT_4B[12]XADC:INIT_4B[13]
    31----------------------------XADC:INIT_4B[14]XADC:INIT_4B[15]
    32----------------------------XADC:INIT_4C[0]XADC:INIT_4C[1]
    33----------------------------XADC:INIT_4C[2]XADC:INIT_4C[3]
    34----------------------------XADC:INIT_4C[4]XADC:INIT_4C[5]
    35----------------------------XADC:INIT_4C[6]XADC:INIT_4C[7]
    36----------------------------XADC:INIT_4C[8]XADC:INIT_4C[9]
    37----------------------------XADC:INIT_4C[10]XADC:INIT_4C[11]
    38----------------------------XADC:INIT_4C[12]XADC:INIT_4C[13]
    39----------------------------XADC:INIT_4C[14]XADC:INIT_4C[15]
    40----------------------------XADC:INIT_4D[0]XADC:INIT_4D[1]
    41----------------------------XADC:INIT_4D[2]XADC:INIT_4D[3]
    42----------------------------XADC:INIT_4D[4]XADC:INIT_4D[5]
    43----------------------------XADC:INIT_4D[6]XADC:INIT_4D[7]
    44----------------------------XADC:INIT_4D[8]XADC:INIT_4D[9]
    45----------------------------XADC:INIT_4D[10]XADC:INIT_4D[11]
    46----------------------------XADC:INIT_4D[12]XADC:INIT_4D[13]
    47----------------------------XADC:INIT_4D[14]XADC:INIT_4D[15]
    48----------------------------XADC:INIT_4E[0]XADC:INIT_4E[1]
    49----------------------------XADC:INIT_4E[2]XADC:INIT_4E[3]
    50----------------------------XADC:INIT_4E[4]XADC:INIT_4E[5]
    51----------------------------XADC:INIT_4E[6]XADC:INIT_4E[7]
    52----------------------------XADC:INIT_4E[8]XADC:INIT_4E[9]
    53----------------------------XADC:INIT_4E[10]XADC:INIT_4E[11]
    54----------------------------XADC:INIT_4E[12]XADC:INIT_4E[13]
    55----------------------------XADC:INIT_4E[14]XADC:INIT_4E[15]
    56----------------------------XADC:INIT_4F[0]XADC:INIT_4F[1]
    57----------------------------XADC:INIT_4F[2]XADC:INIT_4F[3]
    58----------------------------XADC:INIT_4F[4]XADC:INIT_4F[5]
    59----------------------------XADC:INIT_4F[6]XADC:INIT_4F[7]
    60----------------------------XADC:INIT_4F[8]XADC:INIT_4F[9]
    61----------------------------XADC:INIT_4F[10]XADC:INIT_4F[11]
    62----------------------------XADC:INIT_4F[12]XADC:INIT_4F[13]
    63----------------------------XADC:INIT_4F[14]XADC:INIT_4F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    XADC bittile 3
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------XADC:INIT_50[0]XADC:INIT_50[1]
    1----------------------------XADC:INIT_50[2]XADC:INIT_50[3]
    2----------------------------XADC:INIT_50[4]XADC:INIT_50[5]
    3----------------------------XADC:INIT_50[6]XADC:INIT_50[7]
    4----------------------------XADC:INIT_50[8]XADC:INIT_50[9]
    5----------------------------XADC:INIT_50[10]XADC:INIT_50[11]
    6----------------------------XADC:INIT_50[12]XADC:INIT_50[13]
    7----------------------------XADC:INIT_50[14]XADC:INIT_50[15]
    8----------------------------XADC:INIT_51[0]XADC:INIT_51[1]
    9----------------------------XADC:INIT_51[2]XADC:INIT_51[3]
    10----------------------------XADC:INIT_51[4]XADC:INIT_51[5]
    11----------------------------XADC:INIT_51[6]XADC:INIT_51[7]
    12----------------------------XADC:INIT_51[8]XADC:INIT_51[9]
    13----------------------------XADC:INIT_51[10]XADC:INIT_51[11]
    14----------------------------XADC:INIT_51[12]XADC:INIT_51[13]
    15----------------------------XADC:INIT_51[14]XADC:INIT_51[15]
    16----------------------------XADC:INIT_52[0]XADC:INIT_52[1]
    17----------------------------XADC:INIT_52[2]XADC:INIT_52[3]
    18----------------------------XADC:INIT_52[4]XADC:INIT_52[5]
    19----------------------------XADC:INIT_52[6]XADC:INIT_52[7]
    20----------------------------XADC:INIT_52[8]XADC:INIT_52[9]
    21----------------------------XADC:INIT_52[10]XADC:INIT_52[11]
    22----------------------------XADC:INIT_52[12]XADC:INIT_52[13]
    23----------------------------XADC:INIT_52[14]XADC:INIT_52[15]
    24----------------------------XADC:INIT_53[0]XADC:INIT_53[1]
    25----------------------------XADC:INIT_53[2]XADC:INIT_53[3]
    26----------------------------XADC:INIT_53[4]XADC:INIT_53[5]
    27----------------------------XADC:INIT_53[6]XADC:INIT_53[7]
    28----------------------------XADC:INIT_53[8]XADC:INIT_53[9]
    29----------------------------XADC:INIT_53[10]XADC:INIT_53[11]
    30----------------------------XADC:INIT_53[12]XADC:INIT_53[13]
    31----------------------------XADC:INIT_53[14]XADC:INIT_53[15]
    32----------------------------XADC:INIT_54[0]XADC:INIT_54[1]
    33----------------------------XADC:INIT_54[2]XADC:INIT_54[3]
    34----------------------------XADC:INIT_54[4]XADC:INIT_54[5]
    35----------------------------XADC:INIT_54[6]XADC:INIT_54[7]
    36----------------------------XADC:INIT_54[8]XADC:INIT_54[9]
    37----------------------------XADC:INIT_54[10]XADC:INIT_54[11]
    38----------------------------XADC:INIT_54[12]XADC:INIT_54[13]
    39----------------------------XADC:INIT_54[14]XADC:INIT_54[15]
    40----------------------------XADC:INIT_55[0]XADC:INIT_55[1]
    41----------------------------XADC:INIT_55[2]XADC:INIT_55[3]
    42----------------------------XADC:INIT_55[4]XADC:INIT_55[5]
    43----------------------------XADC:INIT_55[6]XADC:INIT_55[7]
    44----------------------------XADC:INIT_55[8]XADC:INIT_55[9]
    45----------------------------XADC:INIT_55[10]XADC:INIT_55[11]
    46----------------------------XADC:INIT_55[12]XADC:INIT_55[13]
    47----------------------------XADC:INIT_55[14]XADC:INIT_55[15]
    48----------------------------XADC:INIT_56[0]XADC:INIT_56[1]
    49----------------------------XADC:INIT_56[2]XADC:INIT_56[3]
    50----------------------------XADC:INIT_56[4]XADC:INIT_56[5]
    51----------------------------XADC:INIT_56[6]XADC:INIT_56[7]
    52----------------------------XADC:INIT_56[8]XADC:INIT_56[9]
    53----------------------------XADC:INIT_56[10]XADC:INIT_56[11]
    54----------------------------XADC:INIT_56[12]XADC:INIT_56[13]
    55----------------------------XADC:INIT_56[14]XADC:INIT_56[15]
    56----------------------------XADC:INIT_57[0]XADC:INIT_57[1]
    57----------------------------XADC:INIT_57[2]XADC:INIT_57[3]
    58----------------------------XADC:INIT_57[4]XADC:INIT_57[5]
    59----------------------------XADC:INIT_57[6]XADC:INIT_57[7]
    60----------------------------XADC:INIT_57[8]XADC:INIT_57[9]
    61----------------------------XADC:INIT_57[10]XADC:INIT_57[11]
    62----------------------------XADC:INIT_57[12]XADC:INIT_57[13]
    63----------------------------XADC:INIT_57[14]XADC:INIT_57[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    XADC bittile 4
    RowColumn
    01234567891011121314151617181920212223242526272829
    0--------------------------XADC:SYSMON_TEST_A[0]XADC:SYSMON_TEST_A[1]XADC:INIT_58[0]XADC:INIT_58[1]
    1--------------------------XADC:SYSMON_TEST_A[2]XADC:SYSMON_TEST_A[3]XADC:INIT_58[2]XADC:INIT_58[3]
    2--------------------------XADC:SYSMON_TEST_A[4]XADC:SYSMON_TEST_A[5]XADC:INIT_58[4]XADC:INIT_58[5]
    3--------------------------XADC:SYSMON_TEST_A[6]XADC:SYSMON_TEST_A[7]XADC:INIT_58[6]XADC:INIT_58[7]
    4--------------------------XADC:SYSMON_TEST_A[8]XADC:SYSMON_TEST_A[9]XADC:INIT_58[8]XADC:INIT_58[9]
    5--------------------------XADC:SYSMON_TEST_A[10]XADC:SYSMON_TEST_A[11]XADC:INIT_58[10]XADC:INIT_58[11]
    6--------------------------XADC:SYSMON_TEST_A[12]XADC:SYSMON_TEST_A[13]XADC:INIT_58[12]XADC:INIT_58[13]
    7--------------------------XADC:SYSMON_TEST_A[14]XADC:SYSMON_TEST_A[15]XADC:INIT_58[14]XADC:INIT_58[15]
    8--------------------------XADC:SYSMON_TEST_B[0]XADC:SYSMON_TEST_B[1]XADC:INIT_59[0]XADC:INIT_59[1]
    9--------------------------XADC:SYSMON_TEST_B[2]XADC:SYSMON_TEST_B[3]XADC:INIT_59[2]XADC:INIT_59[3]
    10--------------------------XADC:SYSMON_TEST_B[4]XADC:SYSMON_TEST_B[5]XADC:INIT_59[4]XADC:INIT_59[5]
    11--------------------------XADC:SYSMON_TEST_B[6]XADC:SYSMON_TEST_B[7]XADC:INIT_59[6]XADC:INIT_59[7]
    12--------------------------XADC:SYSMON_TEST_B[8]XADC:SYSMON_TEST_B[9]XADC:INIT_59[8]XADC:INIT_59[9]
    13--------------------------XADC:SYSMON_TEST_B[10]XADC:SYSMON_TEST_B[11]XADC:INIT_59[10]XADC:INIT_59[11]
    14--------------------------XADC:SYSMON_TEST_B[12]XADC:SYSMON_TEST_B[13]XADC:INIT_59[12]XADC:INIT_59[13]
    15--------------------------XADC:SYSMON_TEST_B[14]XADC:SYSMON_TEST_B[15]XADC:INIT_59[14]XADC:INIT_59[15]
    16--------------------------XADC:SYSMON_TEST_C[0]XADC:SYSMON_TEST_C[1]XADC:INIT_5A[0]XADC:INIT_5A[1]
    17--------------------------XADC:SYSMON_TEST_C[2]XADC:SYSMON_TEST_C[3]XADC:INIT_5A[2]XADC:INIT_5A[3]
    18--------------------------XADC:SYSMON_TEST_C[4]XADC:SYSMON_TEST_C[5]XADC:INIT_5A[4]XADC:INIT_5A[5]
    19--------------------------XADC:SYSMON_TEST_C[6]XADC:SYSMON_TEST_C[7]XADC:INIT_5A[6]XADC:INIT_5A[7]
    20--------------------------XADC:SYSMON_TEST_C[8]XADC:SYSMON_TEST_C[9]XADC:INIT_5A[8]XADC:INIT_5A[9]
    21--------------------------XADC:SYSMON_TEST_C[10]XADC:SYSMON_TEST_C[11]XADC:INIT_5A[10]XADC:INIT_5A[11]
    22--------------------------XADC:SYSMON_TEST_C[12]XADC:SYSMON_TEST_C[13]XADC:INIT_5A[12]XADC:INIT_5A[13]
    23--------------------------XADC:SYSMON_TEST_C[14]XADC:SYSMON_TEST_C[15]XADC:INIT_5A[14]XADC:INIT_5A[15]
    24--------------------------XADC:SYSMON_TEST_D[0]XADC:SYSMON_TEST_D[1]XADC:INIT_5B[0]XADC:INIT_5B[1]
    25--------------------------XADC:SYSMON_TEST_D[2]XADC:SYSMON_TEST_D[3]XADC:INIT_5B[2]XADC:INIT_5B[3]
    26--------------------------XADC:SYSMON_TEST_D[4]XADC:SYSMON_TEST_D[5]XADC:INIT_5B[4]XADC:INIT_5B[5]
    27--------------------------XADC:SYSMON_TEST_D[6]XADC:SYSMON_TEST_D[7]XADC:INIT_5B[6]XADC:INIT_5B[7]
    28--------------------------XADC:SYSMON_TEST_D[8]XADC:SYSMON_TEST_D[9]XADC:INIT_5B[8]XADC:INIT_5B[9]
    29--------------------------XADC:SYSMON_TEST_D[10]XADC:SYSMON_TEST_D[11]XADC:INIT_5B[10]XADC:INIT_5B[11]
    30--------------------------XADC:SYSMON_TEST_D[12]XADC:SYSMON_TEST_D[13]XADC:INIT_5B[12]XADC:INIT_5B[13]
    31--------------------------XADC:SYSMON_TEST_D[14]XADC:SYSMON_TEST_D[15]XADC:INIT_5B[14]XADC:INIT_5B[15]
    32--------------------------XADC:SYSMON_TEST_E[0]XADC:SYSMON_TEST_E[1]XADC:INIT_5C[0]XADC:INIT_5C[1]
    33--------------------------XADC:SYSMON_TEST_E[2]XADC:SYSMON_TEST_E[3]XADC:INIT_5C[2]XADC:INIT_5C[3]
    34--------------------------XADC:SYSMON_TEST_E[4]XADC:SYSMON_TEST_E[5]XADC:INIT_5C[4]XADC:INIT_5C[5]
    35--------------------------XADC:SYSMON_TEST_E[6]XADC:SYSMON_TEST_E[7]XADC:INIT_5C[6]XADC:INIT_5C[7]
    36--------------------------XADC:SYSMON_TEST_E[8]XADC:SYSMON_TEST_E[9]XADC:INIT_5C[8]XADC:INIT_5C[9]
    37--------------------------XADC:SYSMON_TEST_E[10]XADC:SYSMON_TEST_E[11]XADC:INIT_5C[10]XADC:INIT_5C[11]
    38--------------------------XADC:SYSMON_TEST_E[12]XADC:SYSMON_TEST_E[13]XADC:INIT_5C[12]XADC:INIT_5C[13]
    39--------------------------XADC:SYSMON_TEST_E[14]XADC:SYSMON_TEST_E[15]XADC:INIT_5C[14]XADC:INIT_5C[15]
    40--------------------------~XADC:INV.CONVSTCLK~XADC:INV.DCLKXADC:INIT_5D[0]XADC:INIT_5D[1]
    41----------------------------XADC:INIT_5D[2]XADC:INIT_5D[3]
    42----------------------------XADC:INIT_5D[4]XADC:INIT_5D[5]
    43----------------------------XADC:INIT_5D[6]XADC:INIT_5D[7]
    44----------------------------XADC:INIT_5D[8]XADC:INIT_5D[9]
    45----------------------------XADC:INIT_5D[10]XADC:INIT_5D[11]
    46----------------------------XADC:INIT_5D[12]XADC:INIT_5D[13]
    47----------------------------XADC:INIT_5D[14]XADC:INIT_5D[15]
    48----------------------------XADC:INIT_5E[0]XADC:INIT_5E[1]
    49----------------------------XADC:INIT_5E[2]XADC:INIT_5E[3]
    50----------------------------XADC:INIT_5E[4]XADC:INIT_5E[5]
    51----------------------------XADC:INIT_5E[6]XADC:INIT_5E[7]
    52----------------------------XADC:INIT_5E[8]XADC:INIT_5E[9]
    53----------------------------XADC:INIT_5E[10]XADC:INIT_5E[11]
    54----------------------------XADC:INIT_5E[12]XADC:INIT_5E[13]
    55----------------------------XADC:INIT_5E[14]XADC:INIT_5E[15]
    56----------------------------XADC:INIT_5F[0]XADC:INIT_5F[1]
    57----------------------------XADC:INIT_5F[2]XADC:INIT_5F[3]
    58----------------------------XADC:INIT_5F[4]XADC:INIT_5F[5]
    59----------------------------XADC:INIT_5F[6]XADC:INIT_5F[7]
    60----------------------------XADC:INIT_5F[8]XADC:INIT_5F[9]
    61----------------------------XADC:INIT_5F[10]XADC:INIT_5F[11]
    62----------------------------XADC:INIT_5F[12]XADC:INIT_5F[13]
    63----------------------------XADC:INIT_5F[14]XADC:INIT_5F[15]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    XADC:INIT_40[1, 29, 7][1, 28, 7][1, 29, 6][1, 28, 6][1, 29, 5][1, 28, 5][1, 29, 4][1, 28, 4][1, 29, 3][1, 28, 3][1, 29, 2][1, 28, 2][1, 29, 1][1, 28, 1][1, 29, 0][1, 28, 0]
    XADC:INIT_41[1, 29, 15][1, 28, 15][1, 29, 14][1, 28, 14][1, 29, 13][1, 28, 13][1, 29, 12][1, 28, 12][1, 29, 11][1, 28, 11][1, 29, 10][1, 28, 10][1, 29, 9][1, 28, 9][1, 29, 8][1, 28, 8]
    XADC:INIT_42[1, 29, 23][1, 28, 23][1, 29, 22][1, 28, 22][1, 29, 21][1, 28, 21][1, 29, 20][1, 28, 20][1, 29, 19][1, 28, 19][1, 29, 18][1, 28, 18][1, 29, 17][1, 28, 17][1, 29, 16][1, 28, 16]
    XADC:INIT_43[1, 29, 31][1, 28, 31][1, 29, 30][1, 28, 30][1, 29, 29][1, 28, 29][1, 29, 28][1, 28, 28][1, 29, 27][1, 28, 27][1, 29, 26][1, 28, 26][1, 29, 25][1, 28, 25][1, 29, 24][1, 28, 24]
    XADC:INIT_44[1, 29, 39][1, 28, 39][1, 29, 38][1, 28, 38][1, 29, 37][1, 28, 37][1, 29, 36][1, 28, 36][1, 29, 35][1, 28, 35][1, 29, 34][1, 28, 34][1, 29, 33][1, 28, 33][1, 29, 32][1, 28, 32]
    XADC:INIT_45[1, 29, 47][1, 28, 47][1, 29, 46][1, 28, 46][1, 29, 45][1, 28, 45][1, 29, 44][1, 28, 44][1, 29, 43][1, 28, 43][1, 29, 42][1, 28, 42][1, 29, 41][1, 28, 41][1, 29, 40][1, 28, 40]
    XADC:INIT_46[1, 29, 55][1, 28, 55][1, 29, 54][1, 28, 54][1, 29, 53][1, 28, 53][1, 29, 52][1, 28, 52][1, 29, 51][1, 28, 51][1, 29, 50][1, 28, 50][1, 29, 49][1, 28, 49][1, 29, 48][1, 28, 48]
    XADC:INIT_47[1, 29, 63][1, 28, 63][1, 29, 62][1, 28, 62][1, 29, 61][1, 28, 61][1, 29, 60][1, 28, 60][1, 29, 59][1, 28, 59][1, 29, 58][1, 28, 58][1, 29, 57][1, 28, 57][1, 29, 56][1, 28, 56]
    XADC:INIT_48[2, 29, 7][2, 28, 7][2, 29, 6][2, 28, 6][2, 29, 5][2, 28, 5][2, 29, 4][2, 28, 4][2, 29, 3][2, 28, 3][2, 29, 2][2, 28, 2][2, 29, 1][2, 28, 1][2, 29, 0][2, 28, 0]
    XADC:INIT_49[2, 29, 15][2, 28, 15][2, 29, 14][2, 28, 14][2, 29, 13][2, 28, 13][2, 29, 12][2, 28, 12][2, 29, 11][2, 28, 11][2, 29, 10][2, 28, 10][2, 29, 9][2, 28, 9][2, 29, 8][2, 28, 8]
    XADC:INIT_4A[2, 29, 23][2, 28, 23][2, 29, 22][2, 28, 22][2, 29, 21][2, 28, 21][2, 29, 20][2, 28, 20][2, 29, 19][2, 28, 19][2, 29, 18][2, 28, 18][2, 29, 17][2, 28, 17][2, 29, 16][2, 28, 16]
    XADC:INIT_4B[2, 29, 31][2, 28, 31][2, 29, 30][2, 28, 30][2, 29, 29][2, 28, 29][2, 29, 28][2, 28, 28][2, 29, 27][2, 28, 27][2, 29, 26][2, 28, 26][2, 29, 25][2, 28, 25][2, 29, 24][2, 28, 24]
    XADC:INIT_4C[2, 29, 39][2, 28, 39][2, 29, 38][2, 28, 38][2, 29, 37][2, 28, 37][2, 29, 36][2, 28, 36][2, 29, 35][2, 28, 35][2, 29, 34][2, 28, 34][2, 29, 33][2, 28, 33][2, 29, 32][2, 28, 32]
    XADC:INIT_4D[2, 29, 47][2, 28, 47][2, 29, 46][2, 28, 46][2, 29, 45][2, 28, 45][2, 29, 44][2, 28, 44][2, 29, 43][2, 28, 43][2, 29, 42][2, 28, 42][2, 29, 41][2, 28, 41][2, 29, 40][2, 28, 40]
    XADC:INIT_4E[2, 29, 55][2, 28, 55][2, 29, 54][2, 28, 54][2, 29, 53][2, 28, 53][2, 29, 52][2, 28, 52][2, 29, 51][2, 28, 51][2, 29, 50][2, 28, 50][2, 29, 49][2, 28, 49][2, 29, 48][2, 28, 48]
    XADC:INIT_4F[2, 29, 63][2, 28, 63][2, 29, 62][2, 28, 62][2, 29, 61][2, 28, 61][2, 29, 60][2, 28, 60][2, 29, 59][2, 28, 59][2, 29, 58][2, 28, 58][2, 29, 57][2, 28, 57][2, 29, 56][2, 28, 56]
    XADC:INIT_50[3, 29, 7][3, 28, 7][3, 29, 6][3, 28, 6][3, 29, 5][3, 28, 5][3, 29, 4][3, 28, 4][3, 29, 3][3, 28, 3][3, 29, 2][3, 28, 2][3, 29, 1][3, 28, 1][3, 29, 0][3, 28, 0]
    XADC:INIT_51[3, 29, 15][3, 28, 15][3, 29, 14][3, 28, 14][3, 29, 13][3, 28, 13][3, 29, 12][3, 28, 12][3, 29, 11][3, 28, 11][3, 29, 10][3, 28, 10][3, 29, 9][3, 28, 9][3, 29, 8][3, 28, 8]
    XADC:INIT_52[3, 29, 23][3, 28, 23][3, 29, 22][3, 28, 22][3, 29, 21][3, 28, 21][3, 29, 20][3, 28, 20][3, 29, 19][3, 28, 19][3, 29, 18][3, 28, 18][3, 29, 17][3, 28, 17][3, 29, 16][3, 28, 16]
    XADC:INIT_53[3, 29, 31][3, 28, 31][3, 29, 30][3, 28, 30][3, 29, 29][3, 28, 29][3, 29, 28][3, 28, 28][3, 29, 27][3, 28, 27][3, 29, 26][3, 28, 26][3, 29, 25][3, 28, 25][3, 29, 24][3, 28, 24]
    XADC:INIT_54[3, 29, 39][3, 28, 39][3, 29, 38][3, 28, 38][3, 29, 37][3, 28, 37][3, 29, 36][3, 28, 36][3, 29, 35][3, 28, 35][3, 29, 34][3, 28, 34][3, 29, 33][3, 28, 33][3, 29, 32][3, 28, 32]
    XADC:INIT_55[3, 29, 47][3, 28, 47][3, 29, 46][3, 28, 46][3, 29, 45][3, 28, 45][3, 29, 44][3, 28, 44][3, 29, 43][3, 28, 43][3, 29, 42][3, 28, 42][3, 29, 41][3, 28, 41][3, 29, 40][3, 28, 40]
    XADC:INIT_56[3, 29, 55][3, 28, 55][3, 29, 54][3, 28, 54][3, 29, 53][3, 28, 53][3, 29, 52][3, 28, 52][3, 29, 51][3, 28, 51][3, 29, 50][3, 28, 50][3, 29, 49][3, 28, 49][3, 29, 48][3, 28, 48]
    XADC:INIT_57[3, 29, 63][3, 28, 63][3, 29, 62][3, 28, 62][3, 29, 61][3, 28, 61][3, 29, 60][3, 28, 60][3, 29, 59][3, 28, 59][3, 29, 58][3, 28, 58][3, 29, 57][3, 28, 57][3, 29, 56][3, 28, 56]
    XADC:INIT_58[4, 29, 7][4, 28, 7][4, 29, 6][4, 28, 6][4, 29, 5][4, 28, 5][4, 29, 4][4, 28, 4][4, 29, 3][4, 28, 3][4, 29, 2][4, 28, 2][4, 29, 1][4, 28, 1][4, 29, 0][4, 28, 0]
    XADC:INIT_59[4, 29, 15][4, 28, 15][4, 29, 14][4, 28, 14][4, 29, 13][4, 28, 13][4, 29, 12][4, 28, 12][4, 29, 11][4, 28, 11][4, 29, 10][4, 28, 10][4, 29, 9][4, 28, 9][4, 29, 8][4, 28, 8]
    XADC:INIT_5A[4, 29, 23][4, 28, 23][4, 29, 22][4, 28, 22][4, 29, 21][4, 28, 21][4, 29, 20][4, 28, 20][4, 29, 19][4, 28, 19][4, 29, 18][4, 28, 18][4, 29, 17][4, 28, 17][4, 29, 16][4, 28, 16]
    XADC:INIT_5B[4, 29, 31][4, 28, 31][4, 29, 30][4, 28, 30][4, 29, 29][4, 28, 29][4, 29, 28][4, 28, 28][4, 29, 27][4, 28, 27][4, 29, 26][4, 28, 26][4, 29, 25][4, 28, 25][4, 29, 24][4, 28, 24]
    XADC:INIT_5C[4, 29, 39][4, 28, 39][4, 29, 38][4, 28, 38][4, 29, 37][4, 28, 37][4, 29, 36][4, 28, 36][4, 29, 35][4, 28, 35][4, 29, 34][4, 28, 34][4, 29, 33][4, 28, 33][4, 29, 32][4, 28, 32]
    XADC:INIT_5D[4, 29, 47][4, 28, 47][4, 29, 46][4, 28, 46][4, 29, 45][4, 28, 45][4, 29, 44][4, 28, 44][4, 29, 43][4, 28, 43][4, 29, 42][4, 28, 42][4, 29, 41][4, 28, 41][4, 29, 40][4, 28, 40]
    XADC:INIT_5E[4, 29, 55][4, 28, 55][4, 29, 54][4, 28, 54][4, 29, 53][4, 28, 53][4, 29, 52][4, 28, 52][4, 29, 51][4, 28, 51][4, 29, 50][4, 28, 50][4, 29, 49][4, 28, 49][4, 29, 48][4, 28, 48]
    XADC:INIT_5F[4, 29, 63][4, 28, 63][4, 29, 62][4, 28, 62][4, 29, 61][4, 28, 61][4, 29, 60][4, 28, 60][4, 29, 59][4, 28, 59][4, 29, 58][4, 28, 58][4, 29, 57][4, 28, 57][4, 29, 56][4, 28, 56]
    XADC:SYSMON_TEST_A[4, 27, 7][4, 26, 7][4, 27, 6][4, 26, 6][4, 27, 5][4, 26, 5][4, 27, 4][4, 26, 4][4, 27, 3][4, 26, 3][4, 27, 2][4, 26, 2][4, 27, 1][4, 26, 1][4, 27, 0][4, 26, 0]
    XADC:SYSMON_TEST_B[4, 27, 15][4, 26, 15][4, 27, 14][4, 26, 14][4, 27, 13][4, 26, 13][4, 27, 12][4, 26, 12][4, 27, 11][4, 26, 11][4, 27, 10][4, 26, 10][4, 27, 9][4, 26, 9][4, 27, 8][4, 26, 8]
    XADC:SYSMON_TEST_C[4, 27, 23][4, 26, 23][4, 27, 22][4, 26, 22][4, 27, 21][4, 26, 21][4, 27, 20][4, 26, 20][4, 27, 19][4, 26, 19][4, 27, 18][4, 26, 18][4, 27, 17][4, 26, 17][4, 27, 16][4, 26, 16]
    XADC:SYSMON_TEST_D[4, 27, 31][4, 26, 31][4, 27, 30][4, 26, 30][4, 27, 29][4, 26, 29][4, 27, 28][4, 26, 28][4, 27, 27][4, 26, 27][4, 27, 26][4, 26, 26][4, 27, 25][4, 26, 25][4, 27, 24][4, 26, 24]
    XADC:SYSMON_TEST_E[4, 27, 39][4, 26, 39][4, 27, 38][4, 26, 38][4, 27, 37][4, 26, 37][4, 27, 36][4, 26, 36][4, 27, 35][4, 26, 35][4, 27, 34][4, 26, 34][4, 27, 33][4, 26, 33][4, 27, 32][4, 26, 32]
    Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    +
    +
    + + + + +
    XADC:INV.CONVSTCLK[4, 26, 40]
    XADC:INV.DCLK[4, 27, 40]
    Inverted~[0]
    +
    + + + + + + + + + + + + + + \ No newline at end of file diff --git a/xilinx/virtex7/clb.html b/xilinx/virtex7/clb.html index 743b3830..060db708 100644 --- a/xilinx/virtex7/clb.html +++ b/xilinx/virtex7/clb.html @@ -68,10 +68,12 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • diff --git a/xilinx/virtex7/clock.html b/xilinx/virtex7/clock.html index 51b7b8c8..51de3b2a 100644 --- a/xilinx/virtex7/clock.html +++ b/xilinx/virtex7/clock.html @@ -20,7 +20,7 @@ - + @@ -64,6 +64,7 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
    • @@ -116,139 +118,142 @@

    HCLK

    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +
    HCLK bittile 0
    RowColumn
    012345
    HCLK bittile 0
    RowColumn
    012345678910111213141516171819202122232425
    0------
    --------------------------
    1------
    --------------------------
    2------
    --------------------------
    3------
    --------------------------
    4------
    --------------------------
    5------
    --------------------------
    6------
    --------------------------
    7------
    --------------------------
    8------
    --------------------------
    9------
    --------------------------
    10------
    --------------------------
    11------
    --------------------------
    12------
    --------------------------
    13------
    ------------------------HCLK:DRP_MASK_BELOW_LHCLK:DRP_MASK_ABOVE_L
    14HCLK:ENABLE.HCLK8HCLK:MUX.OUT_D6[0]HCLK:MUX.OUT_D7[4]HCLK:MUX.OUT_D6[5]HCLK:MUX.OUT_D6[4]HCLK:MUX.OUT_D7[5]
    HCLK:ENABLE.HCLK8HCLK:MUX.LCLK6_D[0]HCLK:MUX.LCLK7_D[4]HCLK:MUX.LCLK6_D[5]HCLK:MUX.LCLK6_D[4]HCLK:MUX.LCLK7_D[5]--------------------
    15HCLK:MUX.OUT_D6[1]HCLK:MUX.OUT_D6[2]HCLK:MUX.OUT_D7[6]HCLK:MUX.OUT_D6[7]HCLK:MUX.OUT_D6[6]HCLK:MUX.OUT_D7[7]
    HCLK:MUX.LCLK6_D[1]HCLK:MUX.LCLK6_D[2]HCLK:MUX.LCLK7_D[6]HCLK:MUX.LCLK6_D[7]HCLK:MUX.LCLK6_D[6]HCLK:MUX.LCLK7_D[7]--------------------
    16HCLK:MUX.OUT_D6[3]HCLK:MUX.OUT_D8[3]HCLK:MUX.OUT_D7[3]HCLK:MUX.OUT_D7[0]HCLK:MUX.OUT_D7[2]HCLK:MUX.OUT_D7[1]
    HCLK:MUX.LCLK6_D[3]HCLK:MUX.LCLK8_D[3]HCLK:MUX.LCLK7_D[3]HCLK:MUX.LCLK7_D[0]HCLK:MUX.LCLK7_D[2]HCLK:MUX.LCLK7_D[1]--------------------
    17HCLK:MUX.OUT_D8[2]HCLK:MUX.OUT_D8[1]HCLK:MUX.OUT_D9[0]HCLK:MUX.OUT_D9[3]HCLK:MUX.OUT_D9[1]HCLK:MUX.OUT_D9[2]
    HCLK:MUX.LCLK8_D[2]HCLK:MUX.LCLK8_D[1]HCLK:MUX.LCLK9_D[0]HCLK:MUX.LCLK9_D[3]HCLK:MUX.LCLK9_D[1]HCLK:MUX.LCLK9_D[2]--------------------
    18HCLK:MUX.OUT_D8[0]-HCLK:MUX.OUT_D8[7]HCLK:MUX.OUT_D9[6]HCLK:MUX.OUT_D9[7]HCLK:MUX.OUT_D8[6]
    HCLK:MUX.LCLK8_D[0]-HCLK:MUX.LCLK8_D[7]HCLK:MUX.LCLK9_D[6]HCLK:MUX.LCLK9_D[7]HCLK:MUX.LCLK8_D[6]--------------------
    19-HCLK:ENABLE.HCLK9HCLK:MUX.OUT_D8[5]HCLK:MUX.OUT_D9[4]HCLK:MUX.OUT_D9[5]HCLK:MUX.OUT_D8[4]
    -HCLK:ENABLE.HCLK9HCLK:MUX.LCLK8_D[5]HCLK:MUX.LCLK9_D[4]HCLK:MUX.LCLK9_D[5]HCLK:MUX.LCLK8_D[4]--------------------
    20HCLK:MUX.OUT_D10[0]HCLK:MUX.OUT_D10[1]HCLK:MUX.OUT_D11[4]HCLK:MUX.OUT_D10[5]HCLK:MUX.OUT_D10[4]HCLK:MUX.OUT_D11[5]
    HCLK:MUX.LCLK10_D[0]HCLK:MUX.LCLK10_D[1]HCLK:MUX.LCLK11_D[4]HCLK:MUX.LCLK10_D[5]HCLK:MUX.LCLK10_D[4]HCLK:MUX.LCLK11_D[5]--------------------
    21HCLK:MUX.OUT_D10[2]HCLK:MUX.OUT_D10[3]HCLK:MUX.OUT_D11[6]HCLK:MUX.OUT_D10[7]HCLK:MUX.OUT_D10[6]HCLK:MUX.OUT_D11[7]
    HCLK:MUX.LCLK10_D[2]HCLK:MUX.LCLK10_D[3]HCLK:MUX.LCLK11_D[6]HCLK:MUX.LCLK10_D[7]HCLK:MUX.LCLK10_D[6]HCLK:MUX.LCLK11_D[7]--------------------
    22HCLK:ENABLE.HCLK10HCLK:ENABLE.HCLK11HCLK:MUX.OUT_D11[3]HCLK:MUX.OUT_D11[0]HCLK:MUX.OUT_D11[2]HCLK:MUX.OUT_D11[1]
    HCLK:ENABLE.HCLK10HCLK:ENABLE.HCLK11HCLK:MUX.LCLK11_D[3]HCLK:MUX.LCLK11_D[0]HCLK:MUX.LCLK11_D[2]HCLK:MUX.LCLK11_D[1]--------------------
    23HCLK:ENABLE.RCLK0HCLK:ENABLE.RCLK1HCLK:MUX.OUT_U11[0]HCLK:MUX.OUT_U11[3]HCLK:MUX.OUT_U11[1]HCLK:MUX.OUT_U11[2]
    HCLK:ENABLE.RCLK0HCLK:ENABLE.RCLK1HCLK:MUX.LCLK11_U[0]HCLK:MUX.LCLK11_U[3]HCLK:MUX.LCLK11_U[1]HCLK:MUX.LCLK11_U[2]--------------------
    24HCLK:MUX.OUT_U10[3]HCLK:MUX.OUT_U10[2]HCLK:MUX.OUT_U10[7]HCLK:MUX.OUT_U11[6]HCLK:MUX.OUT_U11[7]HCLK:MUX.OUT_U10[6]
    HCLK:MUX.LCLK10_U[3]HCLK:MUX.LCLK10_U[2]HCLK:MUX.LCLK10_U[7]HCLK:MUX.LCLK11_U[6]HCLK:MUX.LCLK11_U[7]HCLK:MUX.LCLK10_U[6]--------------------
    25HCLK:MUX.OUT_U10[1]HCLK:MUX.OUT_U10[0]HCLK:MUX.OUT_U10[5]HCLK:MUX.OUT_U11[4]HCLK:MUX.OUT_U11[5]HCLK:MUX.OUT_U10[4]
    HCLK:MUX.LCLK10_U[1]HCLK:MUX.LCLK10_U[0]HCLK:MUX.LCLK10_U[5]HCLK:MUX.LCLK11_U[4]HCLK:MUX.LCLK11_U[5]HCLK:MUX.LCLK10_U[4]--------------------
    26HCLK:MUX.OUT_U8[0]HCLK:MUX.OUT_U8[1]HCLK:MUX.OUT_U9[4]HCLK:MUX.OUT_U8[5]HCLK:MUX.OUT_U8[4]HCLK:MUX.OUT_U9[5]
    HCLK:MUX.LCLK8_U[0]HCLK:MUX.LCLK8_U[1]HCLK:MUX.LCLK9_U[4]HCLK:MUX.LCLK8_U[5]HCLK:MUX.LCLK8_U[4]HCLK:MUX.LCLK9_U[5]--------------------
    27--HCLK:MUX.OUT_U9[6]HCLK:MUX.OUT_U8[7]HCLK:MUX.OUT_U8[6]HCLK:MUX.OUT_U9[7]
    --HCLK:MUX.LCLK9_U[6]HCLK:MUX.LCLK8_U[7]HCLK:MUX.LCLK8_U[6]HCLK:MUX.LCLK9_U[7]--------------------
    28HCLK:MUX.OUT_U8[2]HCLK:MUX.OUT_U8[3]HCLK:MUX.OUT_U9[3]HCLK:MUX.OUT_U9[0]HCLK:MUX.OUT_U9[2]HCLK:MUX.OUT_U9[1]
    HCLK:MUX.LCLK8_U[2]HCLK:MUX.LCLK8_U[3]HCLK:MUX.LCLK9_U[3]HCLK:MUX.LCLK9_U[0]HCLK:MUX.LCLK9_U[2]HCLK:MUX.LCLK9_U[1]--------------------
    29HCLK:MUX.OUT_U6[3]HCLK:MUX.OUT_U6[2]HCLK:MUX.OUT_U7[0]HCLK:MUX.OUT_U7[3]HCLK:MUX.OUT_U7[1]HCLK:MUX.OUT_U7[2]
    HCLK:MUX.LCLK6_U[3]HCLK:MUX.LCLK6_U[2]HCLK:MUX.LCLK7_U[0]HCLK:MUX.LCLK7_U[3]HCLK:MUX.LCLK7_U[1]HCLK:MUX.LCLK7_U[2]--------------------
    30HCLK:MUX.OUT_U6[1]HCLK:MUX.OUT_U6[0]HCLK:MUX.OUT_U6[7]HCLK:MUX.OUT_U7[6]HCLK:MUX.OUT_U7[7]HCLK:MUX.OUT_U6[6]
    HCLK:MUX.LCLK6_U[1]HCLK:MUX.LCLK6_U[0]HCLK:MUX.LCLK6_U[7]HCLK:MUX.LCLK7_U[6]HCLK:MUX.LCLK7_U[7]HCLK:MUX.LCLK6_U[6]--------------------
    31HCLK:ENABLE.RCLK2HCLK:ENABLE.RCLK3HCLK:MUX.OUT_U6[5]HCLK:MUX.OUT_U7[4]HCLK:MUX.OUT_U7[5]HCLK:MUX.OUT_U6[4]
    HCLK:ENABLE.RCLK2HCLK:ENABLE.RCLK3HCLK:MUX.LCLK6_U[5]HCLK:MUX.LCLK7_U[4]HCLK:MUX.LCLK7_U[5]HCLK:MUX.LCLK6_U[4]--------------------
    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +
    HCLK bittile 1
    RowColumn
    0123456789101112131415161718192021222324
    HCLK bittile 1
    RowColumn
    012345678910111213141516171819202122232425
    0-------------------------
    --------------------------
    1-------------------------
    --------------------------
    2-------------------------
    --------------------------
    3-------------------------
    --------------------------
    4-------------------------
    --------------------------
    5-------------------------
    --------------------------
    6-------------------------
    --------------------------
    7-------------------------
    --------------------------
    8-------------------------
    --------------------------
    9-------------------------
    --------------------------
    10-------------------------
    --------------------------
    11-------------------------
    --------------------------
    12-------------------------
    --------------------------
    13------------------------HCLK:DRP_MASK_BELOW_R
    ------------------------HCLK:DRP_MASK_BELOW_RHCLK:DRP_MASK_ABOVE_R
    14HCLK:ENABLE.HCLK0HCLK:MUX.OUT_D0[0]HCLK:MUX.OUT_D1[4]HCLK:MUX.OUT_D0[5]HCLK:MUX.OUT_D0[4]HCLK:MUX.OUT_D1[5]-------------------
    HCLK:ENABLE.HCLK0HCLK:MUX.LCLK0_D[0]HCLK:MUX.LCLK1_D[4]HCLK:MUX.LCLK0_D[5]HCLK:MUX.LCLK0_D[4]HCLK:MUX.LCLK1_D[5]--------------------
    15HCLK:MUX.OUT_D0[1]HCLK:MUX.OUT_D0[2]HCLK:MUX.OUT_D1[6]HCLK:MUX.OUT_D0[7]HCLK:MUX.OUT_D0[6]HCLK:MUX.OUT_D1[7]-------------------
    HCLK:MUX.LCLK0_D[1]HCLK:MUX.LCLK0_D[2]HCLK:MUX.LCLK1_D[6]HCLK:MUX.LCLK0_D[7]HCLK:MUX.LCLK0_D[6]HCLK:MUX.LCLK1_D[7]--------------------
    16HCLK:MUX.OUT_D0[3]HCLK:MUX.OUT_D2[3]HCLK:MUX.OUT_D1[3]HCLK:MUX.OUT_D1[0]HCLK:MUX.OUT_D1[2]HCLK:MUX.OUT_D1[1]-------------------
    HCLK:MUX.LCLK0_D[3]HCLK:MUX.LCLK2_D[3]HCLK:MUX.LCLK1_D[3]HCLK:MUX.LCLK1_D[0]HCLK:MUX.LCLK1_D[2]HCLK:MUX.LCLK1_D[1]--------------------
    17HCLK:MUX.OUT_D2[2]HCLK:MUX.OUT_D2[1]HCLK:MUX.OUT_D3[0]HCLK:MUX.OUT_D3[3]HCLK:MUX.OUT_D3[1]HCLK:MUX.OUT_D3[2]-------------------
    HCLK:MUX.LCLK2_D[2]HCLK:MUX.LCLK2_D[1]HCLK:MUX.LCLK3_D[0]HCLK:MUX.LCLK3_D[3]HCLK:MUX.LCLK3_D[1]HCLK:MUX.LCLK3_D[2]--------------------
    18HCLK:MUX.OUT_D2[0]-HCLK:MUX.OUT_D2[7]HCLK:MUX.OUT_D3[6]HCLK:MUX.OUT_D3[7]HCLK:MUX.OUT_D2[6]-------------------
    HCLK:MUX.LCLK2_D[0]-HCLK:MUX.LCLK2_D[7]HCLK:MUX.LCLK3_D[6]HCLK:MUX.LCLK3_D[7]HCLK:MUX.LCLK2_D[6]--------------------
    19-HCLK:ENABLE.HCLK1HCLK:MUX.OUT_D2[5]HCLK:MUX.OUT_D3[4]HCLK:MUX.OUT_D3[5]HCLK:MUX.OUT_D2[4]-------------------
    -HCLK:ENABLE.HCLK1HCLK:MUX.LCLK2_D[5]HCLK:MUX.LCLK3_D[4]HCLK:MUX.LCLK3_D[5]HCLK:MUX.LCLK2_D[4]--------------------
    20HCLK:MUX.OUT_D4[0]HCLK:MUX.OUT_D4[1]HCLK:MUX.OUT_D5[4]HCLK:MUX.OUT_D4[5]HCLK:MUX.OUT_D4[4]HCLK:MUX.OUT_D5[5]-------------------
    HCLK:MUX.LCLK4_D[0]HCLK:MUX.LCLK4_D[1]HCLK:MUX.LCLK5_D[4]HCLK:MUX.LCLK4_D[5]HCLK:MUX.LCLK4_D[4]HCLK:MUX.LCLK5_D[5]--------------------
    21HCLK:MUX.OUT_D4[2]HCLK:MUX.OUT_D4[3]HCLK:MUX.OUT_D5[6]HCLK:MUX.OUT_D4[7]HCLK:MUX.OUT_D4[6]HCLK:MUX.OUT_D5[7]-------------------
    HCLK:MUX.LCLK4_D[2]HCLK:MUX.LCLK4_D[3]HCLK:MUX.LCLK5_D[6]HCLK:MUX.LCLK4_D[7]HCLK:MUX.LCLK4_D[6]HCLK:MUX.LCLK5_D[7]--------------------
    22HCLK:ENABLE.HCLK2HCLK:ENABLE.HCLK3HCLK:MUX.OUT_D5[3]HCLK:MUX.OUT_D5[0]HCLK:MUX.OUT_D5[2]HCLK:MUX.OUT_D5[1]-------------------
    HCLK:ENABLE.HCLK2HCLK:ENABLE.HCLK3HCLK:MUX.LCLK5_D[3]HCLK:MUX.LCLK5_D[0]HCLK:MUX.LCLK5_D[2]HCLK:MUX.LCLK5_D[1]--------------------
    23HCLK:ENABLE.HCLK4HCLK:ENABLE.HCLK5HCLK:MUX.OUT_U5[0]HCLK:MUX.OUT_U5[3]HCLK:MUX.OUT_U5[1]HCLK:MUX.OUT_U5[2]-------------------
    HCLK:ENABLE.HCLK4HCLK:ENABLE.HCLK5HCLK:MUX.LCLK5_U[0]HCLK:MUX.LCLK5_U[3]HCLK:MUX.LCLK5_U[1]HCLK:MUX.LCLK5_U[2]--------------------
    24HCLK:MUX.OUT_U4[3]HCLK:MUX.OUT_U4[2]HCLK:MUX.OUT_U4[7]HCLK:MUX.OUT_U5[6]HCLK:MUX.OUT_U5[7]HCLK:MUX.OUT_U4[6]-------------------
    HCLK:MUX.LCLK4_U[3]HCLK:MUX.LCLK4_U[2]HCLK:MUX.LCLK4_U[7]HCLK:MUX.LCLK5_U[6]HCLK:MUX.LCLK5_U[7]HCLK:MUX.LCLK4_U[6]--------------------
    25HCLK:MUX.OUT_U4[1]HCLK:MUX.OUT_U4[0]HCLK:MUX.OUT_U4[5]HCLK:MUX.OUT_U5[4]HCLK:MUX.OUT_U5[5]HCLK:MUX.OUT_U4[4]-------------------
    HCLK:MUX.LCLK4_U[1]HCLK:MUX.LCLK4_U[0]HCLK:MUX.LCLK4_U[5]HCLK:MUX.LCLK5_U[4]HCLK:MUX.LCLK5_U[5]HCLK:MUX.LCLK4_U[4]--------------------
    26HCLK:MUX.OUT_U2[0]HCLK:MUX.OUT_U2[1]HCLK:MUX.OUT_U3[4]HCLK:MUX.OUT_U2[5]HCLK:MUX.OUT_U2[4]HCLK:MUX.OUT_U3[5]-------------------
    HCLK:MUX.LCLK2_U[0]HCLK:MUX.LCLK2_U[1]HCLK:MUX.LCLK3_U[4]HCLK:MUX.LCLK2_U[5]HCLK:MUX.LCLK2_U[4]HCLK:MUX.LCLK3_U[5]--------------------
    27--HCLK:MUX.OUT_U3[6]HCLK:MUX.OUT_U2[7]HCLK:MUX.OUT_U2[6]HCLK:MUX.OUT_U3[7]-------------------
    --HCLK:MUX.LCLK3_U[6]HCLK:MUX.LCLK2_U[7]HCLK:MUX.LCLK2_U[6]HCLK:MUX.LCLK3_U[7]--------------------
    28HCLK:MUX.OUT_U2[2]HCLK:MUX.OUT_U2[3]HCLK:MUX.OUT_U3[3]HCLK:MUX.OUT_U3[0]HCLK:MUX.OUT_U3[2]HCLK:MUX.OUT_U3[1]-------------------
    HCLK:MUX.LCLK2_U[2]HCLK:MUX.LCLK2_U[3]HCLK:MUX.LCLK3_U[3]HCLK:MUX.LCLK3_U[0]HCLK:MUX.LCLK3_U[2]HCLK:MUX.LCLK3_U[1]--------------------
    29HCLK:MUX.OUT_U0[3]HCLK:MUX.OUT_U0[2]HCLK:MUX.OUT_U1[0]HCLK:MUX.OUT_U1[3]HCLK:MUX.OUT_U1[1]HCLK:MUX.OUT_U1[2]-------------------
    HCLK:MUX.LCLK0_U[3]HCLK:MUX.LCLK0_U[2]HCLK:MUX.LCLK1_U[0]HCLK:MUX.LCLK1_U[3]HCLK:MUX.LCLK1_U[1]HCLK:MUX.LCLK1_U[2]--------------------
    30HCLK:MUX.OUT_U0[1]HCLK:MUX.OUT_U0[0]HCLK:MUX.OUT_U0[7]HCLK:MUX.OUT_U1[6]HCLK:MUX.OUT_U1[7]HCLK:MUX.OUT_U0[6]-------------------
    HCLK:MUX.LCLK0_U[1]HCLK:MUX.LCLK0_U[0]HCLK:MUX.LCLK0_U[7]HCLK:MUX.LCLK1_U[6]HCLK:MUX.LCLK1_U[7]HCLK:MUX.LCLK0_U[6]--------------------
    31HCLK:ENABLE.HCLK6HCLK:ENABLE.HCLK7HCLK:MUX.OUT_U0[5]HCLK:MUX.OUT_U1[4]HCLK:MUX.OUT_U1[5]HCLK:MUX.OUT_U0[4]-------------------
    HCLK:ENABLE.HCLK6HCLK:ENABLE.HCLK7HCLK:MUX.LCLK0_U[5]HCLK:MUX.LCLK1_U[4]HCLK:MUX.LCLK1_U[5]HCLK:MUX.LCLK0_U[4]--------------------
    +
    +
    +
    @@ -267,6 +272,9 @@

    HCLK
    + + + @@ -286,55 +294,55 @@

    HCLK

    HCLK:DRP_MASK_ABOVE_L[0, 25, 13]
    HCLK:DRP_MASK_ABOVE_R[1, 25, 13]
    HCLK:DRP_MASK_BELOW_L[0, 24, 13]
    HCLK:DRP_MASK_BELOW_R[1, 24, 13]
    HCLK:ENABLE.HCLK0[1, 0, 14]
    HCLK:ENABLE.HCLK1[1, 1, 19]
    HCLK:ENABLE.RCLK3[0, 1, 31]
    Non-inverted[0]
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + @@ -5645,7 +5653,7 @@

    CLK_BALI_REBUF<

    HCLK:MUX.OUT_D0[1, 3, 15][1, 4, 15][1, 3, 14][1, 4, 14][1, 0, 16][1, 1, 15][1, 0, 15][1, 1, 14]
    HCLK:MUX.OUT_D1[1, 5, 15][1, 2, 15][1, 5, 14][1, 2, 14][1, 2, 16][1, 4, 16][1, 5, 16][1, 3, 16]
    HCLK:MUX.OUT_D10[0, 3, 21][0, 4, 21][0, 3, 20][0, 4, 20][0, 1, 21][0, 0, 21][0, 1, 20][0, 0, 20]
    HCLK:MUX.OUT_D11[0, 5, 21][0, 2, 21][0, 5, 20][0, 2, 20][0, 2, 22][0, 4, 22][0, 5, 22][0, 3, 22]
    HCLK:MUX.OUT_D2[1, 2, 18][1, 5, 18][1, 2, 19][1, 5, 19][1, 1, 16][1, 0, 17][1, 1, 17][1, 0, 18]
    HCLK:MUX.OUT_D3[1, 4, 18][1, 3, 18][1, 4, 19][1, 3, 19][1, 3, 17][1, 5, 17][1, 4, 17][1, 2, 17]
    HCLK:MUX.OUT_D4[1, 3, 21][1, 4, 21][1, 3, 20][1, 4, 20][1, 1, 21][1, 0, 21][1, 1, 20][1, 0, 20]
    HCLK:MUX.OUT_D5[1, 5, 21][1, 2, 21][1, 5, 20][1, 2, 20][1, 2, 22][1, 4, 22][1, 5, 22][1, 3, 22]
    HCLK:MUX.OUT_D6[0, 3, 15][0, 4, 15][0, 3, 14][0, 4, 14][0, 0, 16][0, 1, 15][0, 0, 15][0, 1, 14]
    HCLK:MUX.OUT_D7[0, 5, 15][0, 2, 15][0, 5, 14][0, 2, 14][0, 2, 16][0, 4, 16][0, 5, 16][0, 3, 16]
    HCLK:MUX.OUT_D8[0, 2, 18][0, 5, 18][0, 2, 19][0, 5, 19][0, 1, 16][0, 0, 17][0, 1, 17][0, 0, 18]
    HCLK:MUX.OUT_D9[0, 4, 18][0, 3, 18][0, 4, 19][0, 3, 19][0, 3, 17][0, 5, 17][0, 4, 17][0, 2, 17]
    HCLK:MUX.OUT_U0[1, 2, 30][1, 5, 30][1, 2, 31][1, 5, 31][1, 0, 29][1, 1, 29][1, 0, 30][1, 1, 30]
    HCLK:MUX.OUT_U1[1, 4, 30][1, 3, 30][1, 4, 31][1, 3, 31][1, 3, 29][1, 5, 29][1, 4, 29][1, 2, 29]
    HCLK:MUX.OUT_U10[0, 2, 24][0, 5, 24][0, 2, 25][0, 5, 25][0, 0, 24][0, 1, 24][0, 0, 25][0, 1, 25]
    HCLK:MUX.OUT_U11[0, 4, 24][0, 3, 24][0, 4, 25][0, 3, 25][0, 3, 23][0, 5, 23][0, 4, 23][0, 2, 23]
    HCLK:MUX.OUT_U2[1, 3, 27][1, 4, 27][1, 3, 26][1, 4, 26][1, 1, 28][1, 0, 28][1, 1, 26][1, 0, 26]
    HCLK:MUX.OUT_U3[1, 5, 27][1, 2, 27][1, 5, 26][1, 2, 26][1, 2, 28][1, 4, 28][1, 5, 28][1, 3, 28]
    HCLK:MUX.OUT_U4[1, 2, 24][1, 5, 24][1, 2, 25][1, 5, 25][1, 0, 24][1, 1, 24][1, 0, 25][1, 1, 25]
    HCLK:MUX.OUT_U5[1, 4, 24][1, 3, 24][1, 4, 25][1, 3, 25][1, 3, 23][1, 5, 23][1, 4, 23][1, 2, 23]
    HCLK:MUX.OUT_U6[0, 2, 30][0, 5, 30][0, 2, 31][0, 5, 31][0, 0, 29][0, 1, 29][0, 0, 30][0, 1, 30]
    HCLK:MUX.OUT_U7[0, 4, 30][0, 3, 30][0, 4, 31][0, 3, 31][0, 3, 29][0, 5, 29][0, 4, 29][0, 2, 29]
    HCLK:MUX.OUT_U8[0, 3, 27][0, 4, 27][0, 3, 26][0, 4, 26][0, 1, 28][0, 0, 28][0, 1, 26][0, 0, 26]
    HCLK:MUX.OUT_U9[0, 5, 27][0, 2, 27][0, 5, 26][0, 2, 26][0, 2, 28][0, 4, 28][0, 5, 28][0, 3, 28]
    HCLK:MUX.LCLK0_D[1, 3, 15][1, 4, 15][1, 3, 14][1, 4, 14][1, 0, 16][1, 1, 15][1, 0, 15][1, 1, 14]
    HCLK:MUX.LCLK0_U[1, 2, 30][1, 5, 30][1, 2, 31][1, 5, 31][1, 0, 29][1, 1, 29][1, 0, 30][1, 1, 30]
    HCLK:MUX.LCLK10_D[0, 3, 21][0, 4, 21][0, 3, 20][0, 4, 20][0, 1, 21][0, 0, 21][0, 1, 20][0, 0, 20]
    HCLK:MUX.LCLK10_U[0, 2, 24][0, 5, 24][0, 2, 25][0, 5, 25][0, 0, 24][0, 1, 24][0, 0, 25][0, 1, 25]
    HCLK:MUX.LCLK11_D[0, 5, 21][0, 2, 21][0, 5, 20][0, 2, 20][0, 2, 22][0, 4, 22][0, 5, 22][0, 3, 22]
    HCLK:MUX.LCLK11_U[0, 4, 24][0, 3, 24][0, 4, 25][0, 3, 25][0, 3, 23][0, 5, 23][0, 4, 23][0, 2, 23]
    HCLK:MUX.LCLK1_D[1, 5, 15][1, 2, 15][1, 5, 14][1, 2, 14][1, 2, 16][1, 4, 16][1, 5, 16][1, 3, 16]
    HCLK:MUX.LCLK1_U[1, 4, 30][1, 3, 30][1, 4, 31][1, 3, 31][1, 3, 29][1, 5, 29][1, 4, 29][1, 2, 29]
    HCLK:MUX.LCLK2_D[1, 2, 18][1, 5, 18][1, 2, 19][1, 5, 19][1, 1, 16][1, 0, 17][1, 1, 17][1, 0, 18]
    HCLK:MUX.LCLK2_U[1, 3, 27][1, 4, 27][1, 3, 26][1, 4, 26][1, 1, 28][1, 0, 28][1, 1, 26][1, 0, 26]
    HCLK:MUX.LCLK3_D[1, 4, 18][1, 3, 18][1, 4, 19][1, 3, 19][1, 3, 17][1, 5, 17][1, 4, 17][1, 2, 17]
    HCLK:MUX.LCLK3_U[1, 5, 27][1, 2, 27][1, 5, 26][1, 2, 26][1, 2, 28][1, 4, 28][1, 5, 28][1, 3, 28]
    HCLK:MUX.LCLK4_D[1, 3, 21][1, 4, 21][1, 3, 20][1, 4, 20][1, 1, 21][1, 0, 21][1, 1, 20][1, 0, 20]
    HCLK:MUX.LCLK4_U[1, 2, 24][1, 5, 24][1, 2, 25][1, 5, 25][1, 0, 24][1, 1, 24][1, 0, 25][1, 1, 25]
    HCLK:MUX.LCLK5_D[1, 5, 21][1, 2, 21][1, 5, 20][1, 2, 20][1, 2, 22][1, 4, 22][1, 5, 22][1, 3, 22]
    HCLK:MUX.LCLK5_U[1, 4, 24][1, 3, 24][1, 4, 25][1, 3, 25][1, 3, 23][1, 5, 23][1, 4, 23][1, 2, 23]
    HCLK:MUX.LCLK6_D[0, 3, 15][0, 4, 15][0, 3, 14][0, 4, 14][0, 0, 16][0, 1, 15][0, 0, 15][0, 1, 14]
    HCLK:MUX.LCLK6_U[0, 2, 30][0, 5, 30][0, 2, 31][0, 5, 31][0, 0, 29][0, 1, 29][0, 0, 30][0, 1, 30]
    HCLK:MUX.LCLK7_D[0, 5, 15][0, 2, 15][0, 5, 14][0, 2, 14][0, 2, 16][0, 4, 16][0, 5, 16][0, 3, 16]
    HCLK:MUX.LCLK7_U[0, 4, 30][0, 3, 30][0, 4, 31][0, 3, 31][0, 3, 29][0, 5, 29][0, 4, 29][0, 2, 29]
    HCLK:MUX.LCLK8_D[0, 2, 18][0, 5, 18][0, 2, 19][0, 5, 19][0, 1, 16][0, 0, 17][0, 1, 17][0, 0, 18]
    HCLK:MUX.LCLK8_U[0, 3, 27][0, 4, 27][0, 3, 26][0, 4, 26][0, 1, 28][0, 0, 28][0, 1, 26][0, 0, 26]
    HCLK:MUX.LCLK9_D[0, 4, 18][0, 3, 18][0, 4, 19][0, 3, 19][0, 3, 17][0, 5, 17][0, 4, 17][0, 2, 17]
    HCLK:MUX.LCLK9_U[0, 5, 27][0, 2, 27][0, 5, 26][0, 2, 26][0, 2, 28][0, 4, 28][0, 5, 28][0, 3, 28]
    NONE00000000
    HCLK000010001
    HCLK400010010
    - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 0
    RowColumn
    CMT bittile 0
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP7F[15]MMCM:DRP7F[14]
    1----------------------------MMCM:DRP7F[13]MMCM:DRP7F[12]
    2----------------------------MMCM:DRP7F[11]MMCM:DRP7F[10]
    3----------------------------MMCM:DRP7F[9]MMCM:DRP7F[8]
    4----------------------------MMCM:DRP7F[7]MMCM:DRP7F[6]
    5----------------------------MMCM:DRP7F[5]MMCM:DRP7F[4]
    6----------------------------MMCM:DRP7F[3]MMCM:DRP7F[2]
    7----------------------------MMCM:DRP7F[1]MMCM:DRP7F[0]
    8----------------------------MMCM:DRP7E[15]MMCM:DRP7E[14]
    9----------------------------MMCM:DRP7E[13]MMCM:DRP7E[12]
    10----------------------------MMCM:DRP7E[11]MMCM:DRP7E[10]
    11----------------------------MMCM:DRP7E[9]MMCM:DRP7E[8]
    12----------------------------MMCM:DRP7E[7]MMCM:DRP7E[6]
    13----------------------------MMCM:DRP7E[5]MMCM:DRP7E[4]
    14----------------------------MMCM:DRP7E[3]MMCM:DRP7E[2]
    15----------------------------MMCM:DRP7E[1]MMCM:DRP7E[0]
    16----------------------------MMCM:CONTROL_7[15]
    MMCM:DRP7D[15]    		MMCM:CONTROL_7[14]
    MMCM:DRP7D[14]
    17----------------------------MMCM:CONTROL_7[13]
    MMCM:DRP7D[13]    		MMCM:CONTROL_7[12]
    MMCM:DRP7D[12]
    18----------------------------MMCM:CONTROL_7[11]
    MMCM:DRP7D[11]    		MMCM:CONTROL_7[10]
    MMCM:DRP7D[10]
    19----------------------------MMCM:CONTROL_7[9]
    MMCM:DRP7D[9]    		MMCM:CONTROL_7[8]
    MMCM:DRP7D[8]
    20----------------------------MMCM:CONTROL_7[7]
    MMCM:DRP7D[7]    		MMCM:CONTROL_7[6]
    MMCM:DRP7D[6]
    21----------------------------MMCM:CONTROL_7[5]
    MMCM:DRP7D[5]    		MMCM:CONTROL_7[4]
    MMCM:DRP7D[4]
    22----------------------------MMCM:CONTROL_7[3]
    MMCM:DRP7D[3]    		MMCM:CONTROL_7[2]
    MMCM:DRP7D[2]
    23----------------------------MMCM:CONTROL_7[1]
    MMCM:DRP7D[1]    		MMCM:CONTROL_7[0]
    MMCM:DRP7D[0]
    24----------------------------MMCM:CONTROL_6[15]
    MMCM:DRP7C[15]    		MMCM:CONTROL_6[14]
    MMCM:DRP7C[14]
    25----------------------------MMCM:CONTROL_6[13]
    MMCM:DRP7C[13]    		MMCM:CONTROL_6[12]
    MMCM:DRP7C[12]
    26----------------------------MMCM:CONTROL_6[11]
    MMCM:DRP7C[11]    		MMCM:CONTROL_6[10]
    MMCM:DRP7C[10]
    27----------------------------MMCM:CONTROL_6[9]
    MMCM:DRP7C[9]    		MMCM:CONTROL_6[8]
    MMCM:DRP7C[8]
    28----------------------------MMCM:CONTROL_6[7]
    MMCM:DRP7C[7]    		MMCM:CONTROL_6[6]
    MMCM:DRP7C[6]
    29----------------------------MMCM:CONTROL_6[5]
    MMCM:DRP7C[5]    		MMCM:CONTROL_6[4]
    MMCM:DRP7C[4]
    30----------------------------MMCM:CONTROL_6[3]
    MMCM:DRP7C[3]    		MMCM:CONTROL_6[2]
    MMCM:DRP7C[2]
    31----------------------------MMCM:CONTROL_6[1]
    MMCM:DRP7C[1]    		MMCM:CONTROL_6[0]
    MMCM:DRP7C[0]
    32----------------------------MMCM:CONTROL_5[15]
    MMCM:DRP7B[15]    		MMCM:CONTROL_5[14]
    MMCM:DRP7B[14]
    33----------------------------MMCM:CONTROL_5[13]
    MMCM:DRP7B[13]    		MMCM:CONTROL_5[12]
    MMCM:DRP7B[12]
    34----------------------------MMCM:CONTROL_5[11]
    MMCM:DRP7B[11]    		MMCM:CONTROL_5[10]
    MMCM:DRP7B[10]
    35----------------------------MMCM:CONTROL_5[9]
    MMCM:DRP7B[9]    		MMCM:CONTROL_5[8]
    MMCM:DRP7B[8]
    36----------------------------MMCM:CONTROL_5[7]
    MMCM:DRP7B[7]    		MMCM:CONTROL_5[6]
    MMCM:DRP7B[6]
    37----------------------------MMCM:CONTROL_5[5]
    MMCM:DRP7B[5]    		MMCM:CONTROL_5[4]
    MMCM:DRP7B[4]
    38----------------------------MMCM:CONTROL_5[3]
    MMCM:DRP7B[3]    		MMCM:CONTROL_5[2]
    MMCM:DRP7B[2]
    39----------------------------MMCM:CONTROL_5[1]
    MMCM:DRP7B[1]    		MMCM:CONTROL_5[0]
    MMCM:DRP7B[0]
    40----------------------------MMCM:CONTROL_4[15]
    MMCM:DRP7A[15]    		MMCM:CONTROL_4[14]
    MMCM:DRP7A[14]
    41----------------------------MMCM:CONTROL_4[13]
    MMCM:DRP7A[13]    		MMCM:CONTROL_4[12]
    MMCM:DRP7A[12]
    42----------------------------MMCM:CONTROL_4[11]
    MMCM:DRP7A[11]    		MMCM:CONTROL_4[10]
    MMCM:DRP7A[10]
    43----------------------------MMCM:CONTROL_4[9]
    MMCM:DRP7A[9]    		MMCM:CONTROL_4[8]
    MMCM:DRP7A[8]
    44----------------------------MMCM:CONTROL_4[7]
    MMCM:DRP7A[7]    		MMCM:CONTROL_4[6]
    MMCM:DRP7A[6]
    45----------------------------MMCM:CONTROL_4[5]
    MMCM:DRP7A[5]    		MMCM:CONTROL_4[4]
    MMCM:DRP7A[4]
    46----------------------------MMCM:CONTROL_4[3]
    MMCM:DRP7A[3]    		MMCM:CONTROL_4[2]
    MMCM:DRP7A[2]
    47----------------------------MMCM:CONTROL_4[1]
    MMCM:DRP7A[1]    		MMCM:CONTROL_4[0]
    MMCM:DRP7A[0]
    48----------------------------MMCM:CONTROL_3[15]
    MMCM:DRP79[15]    		MMCM:CONTROL_3[14]
    MMCM:DRP79[14]
    49----------------------------MMCM:CONTROL_3[13]
    MMCM:DRP79[13]    		MMCM:CONTROL_3[12]
    MMCM:DRP79[12]
    50----------------------------MMCM:CONTROL_3[11]
    MMCM:DRP79[11]    		MMCM:CONTROL_3[10]
    MMCM:DRP79[10]
    51----------------------------MMCM:CONTROL_3[9]
    MMCM:DRP79[9]    		MMCM:CONTROL_3[8]
    MMCM:DRP79[8]
    52----------------------------MMCM:CONTROL_3[7]
    MMCM:DRP79[7]    		MMCM:CONTROL_3[6]
    MMCM:DRP79[6]
    53----------------------------MMCM:CONTROL_3[5]
    MMCM:DRP79[5]    		MMCM:CONTROL_3[4]
    MMCM:DRP79[4]
    54----------------------------MMCM:CONTROL_3[3]
    MMCM:DRP79[3]    		MMCM:CONTROL_3[2]
    MMCM:DRP79[2]
    55----------------------------MMCM:CONTROL_3[1]
    MMCM:DRP79[1]    		MMCM:CONTROL_3[0]
    MMCM:DRP79[0]
    56----------------------------MMCM:CONTROL_2[15]
    MMCM:DRP78[15]    		MMCM:CONTROL_2[14]
    MMCM:DRP78[14]
    57----------------------------MMCM:CONTROL_2[13]
    MMCM:DRP78[13]    		MMCM:CONTROL_2[12]
    MMCM:DRP78[12]
    58----------------------------MMCM:CONTROL_2[11]
    MMCM:DRP78[11]    		MMCM:CONTROL_2[10]
    MMCM:DRP78[10]
    59----------------------------MMCM:CONTROL_2[9]
    MMCM:DRP78[9]    		MMCM:CONTROL_2[8]
    MMCM:DRP78[8]
    60----------------------------MMCM:CONTROL_2[7]
    MMCM:DRP78[7]    		MMCM:CONTROL_2[6]
    MMCM:DRP78[6]
    61----------------------------MMCM:CONTROL_2[5]
    MMCM:DRP78[5]    		MMCM:CONTROL_2[4]
    MMCM:DRP78[4]
    62----------------------------MMCM:CONTROL_2[3]
    MMCM:DRP78[3]    		MMCM:CONTROL_2[2]
    MMCM:DRP78[2]
    63----------------------------MMCM:CONTROL_2[1]
    MMCM:DRP78[1]    		MMCM:CONTROL_2[0]
    MMCM:DRP78[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 1
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:CONTROL_1[15]
    MMCM:DRP77[15]    		MMCM:CONTROL_1[14]
    MMCM:DRP77[14]
    1----------------------------MMCM:CONTROL_1[13]
    MMCM:DRP77[13]    		MMCM:CONTROL_1[12]
    MMCM:DRP77[12]
    2----------------------------MMCM:CONTROL_1[11]
    MMCM:DRP77[11]    		MMCM:CONTROL_1[10]
    MMCM:DRP77[10]
    3----------------------------MMCM:CONTROL_1[9]
    MMCM:DRP77[9]    		MMCM:CONTROL_1[8]
    MMCM:DRP77[8]
    4----------------------------MMCM:CONTROL_1[7]
    MMCM:DRP77[7]    		MMCM:CONTROL_1[6]
    MMCM:DRP77[6]
    5----------------------------MMCM:CONTROL_1[5]
    MMCM:DRP77[5]    		MMCM:CONTROL_1[4]
    MMCM:DRP77[4]
    6----------------------------MMCM:CONTROL_1[3]
    MMCM:DRP77[3]    		MMCM:CONTROL_1[2]
    MMCM:DRP77[2]
    7----------------------------MMCM:CONTROL_1[1]
    MMCM:DRP77[1]    		MMCM:CONTROL_1[0]
    MMCM:DRP77[0]
    8----------------------------MMCM:CONTROL_0[15]
    MMCM:DRP76[15]    		MMCM:CONTROL_0[14]
    MMCM:DRP76[14]
    9----------------------------MMCM:CONTROL_0[13]
    MMCM:DRP76[13]    		MMCM:CONTROL_0[12]
    MMCM:DRP76[12]
    10----------------------------MMCM:CONTROL_0[11]
    MMCM:DRP76[11]    		MMCM:CONTROL_0[10]
    MMCM:DRP76[10]
    11----------------------------MMCM:CONTROL_0[9]
    MMCM:DRP76[9]    		MMCM:CONTROL_0[8]
    MMCM:DRP76[8]
    12----------------------------MMCM:CONTROL_0[7]
    MMCM:DRP76[7]    		MMCM:CONTROL_0[6]
    MMCM:DRP76[6]
    13----------------------------MMCM:CONTROL_0[5]
    MMCM:DRP76[5]    		MMCM:CONTROL_0[4]
    MMCM:DRP76[4]
    14----------------------------MMCM:CONTROL_0[3]
    MMCM:DRP76[3]    		MMCM:CONTROL_0[2]
    MMCM:DRP76[2]
    15----------------------------MMCM:CONTROL_0[1]
    MMCM:DRP76[1]    		MMCM:CONTROL_0[0]
    MMCM:DRP76[0]
    16----------------------------MMCM:DRP75[15]MMCM:DRP75[14]
    17----------------------------MMCM:DRP75[13]MMCM:DRP75[12]
    18----------------------------MMCM:DRP75[11]MMCM:DRP75[10]
    19----------------------------MMCM:DRP75[9]MMCM:DRP75[8]
    20----------------------------MMCM:DRP75[7]MMCM:DRP75[6]
    21----------------------------MMCM:DRP75[5]MMCM:DRP75[4]
    22----------------------------MMCM:DRP75[3]MMCM:DRP75[2]
    23----------------------------MMCM:DRP75[1]MMCM:DRP75[0]
    24----------------------------MMCM:DRP74[15]MMCM:DRP74[14]
    25----------------------------MMCM:DRP74[13]MMCM:DRP74[12]
    26----------------------------MMCM:DRP74[11]MMCM:DRP74[10]
    MMCM:FINE_PS_FRAC[5]
    27----------------------------MMCM:DRP74[9]
    MMCM:FINE_PS_FRAC[4]    		MMCM:DRP74[8]
    MMCM:FINE_PS_FRAC[3]
    28----------------------------MMCM:DRP74[7]
    MMCM:FINE_PS_FRAC[2]    		MMCM:DRP74[6]
    MMCM:FINE_PS_FRAC[1]
    29----------------------------MMCM:DRP74[5]
    MMCM:FINE_PS_FRAC[0]    		MMCM:DRP74[4]
    30----------------------------MMCM:DRP74[3]
    MMCM:GTS_WAIT    		MMCM:DRP74[2]
    MMCM:STARTUP_WAIT
    31----------------------------MMCM:DRP74[1]
    MMCM:SS_EN    		MMCM:DRP74[0]
    MMCM:MMCM_EN
    32----------------------------MMCM:DRP73[15]MMCM:DRP73[14]
    33----------------------------MMCM:DRP73[13]MMCM:DRP73[12]
    34----------------------------MMCM:DRP73[11]MMCM:DRP73[10]
    35----------------------------MMCM:DRP73[9]MMCM:DRP73[8]
    36----------------------------MMCM:DRP73[7]MMCM:DRP73[6]
    37----------------------------MMCM:DRP73[5]MMCM:DRP73[4]
    38----------------------------MMCM:DRP73[3]MMCM:DRP73[2]
    39----------------------------MMCM:DRP73[1]MMCM:DRP73[0]
    40----------------------------MMCM:DRP72[15]MMCM:DRP72[14]
    41----------------------------MMCM:DRP72[13]MMCM:DRP72[12]
    42----------------------------MMCM:DRP72[11]MMCM:DRP72[10]
    43----------------------------MMCM:DRP72[9]MMCM:DRP72[8]
    44----------------------------MMCM:DRP72[7]MMCM:DRP72[6]
    45----------------------------MMCM:DRP72[5]MMCM:DRP72[4]
    MMCM:INV.CLKINSEL
    46----------------------------MMCM:DRP72[3]
    MMCM:INV.PSEN    		MMCM:DRP72[2]
    MMCM:INV.PSINCDEC
    47----------------------------MMCM:DRP72[1]
    MMCM:INV.PWRDWN    		MMCM:DRP72[0]
    MMCM:INV.RST
    48----------------------------MMCM:DRP71[15]MMCM:DRP71[14]
    49----------------------------MMCM:DRP71[13]MMCM:DRP71[12]
    50----------------------------MMCM:DRP71[11]MMCM:DRP71[10]
    51----------------------------MMCM:DRP71[9]MMCM:DRP71[8]
    52----------------------------MMCM:DRP71[7]MMCM:DRP71[6]
    53----------------------------MMCM:DRP71[5]MMCM:DRP71[4]
    54----------------------------MMCM:DRP71[3]MMCM:DRP71[2]
    55----------------------------MMCM:DRP71[1]MMCM:DRP71[0]
    56----------------------------MMCM:DRP70[15]MMCM:DRP70[14]
    57----------------------------MMCM:DRP70[13]MMCM:DRP70[12]
    58----------------------------MMCM:DRP70[11]MMCM:DRP70[10]
    59----------------------------MMCM:DRP70[9]MMCM:DRP70[8]
    60----------------------------MMCM:DRP70[7]MMCM:DRP70[6]
    61----------------------------MMCM:DRP70[5]MMCM:DRP70[4]
    62----------------------------MMCM:DRP70[3]MMCM:DRP70[2]
    63----------------------------MMCM:DRP70[1]MMCM:DRP70[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 2
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP6F[15]MMCM:DRP6F[14]
    1----------------------------MMCM:DRP6F[13]MMCM:DRP6F[12]
    2----------------------------MMCM:DRP6F[11]MMCM:DRP6F[10]
    3----------------------------MMCM:DRP6F[9]MMCM:DRP6F[8]
    4----------------------------MMCM:DRP6F[7]MMCM:DRP6F[6]
    5----------------------------MMCM:DRP6F[5]MMCM:DRP6F[4]
    6----------------------------MMCM:DRP6F[3]MMCM:DRP6F[2]
    7----------------------------MMCM:DRP6F[1]MMCM:DRP6F[0]
    8----------------------------MMCM:DRP6E[15]MMCM:DRP6E[14]
    9----------------------------MMCM:DRP6E[13]MMCM:DRP6E[12]
    10----------------------------MMCM:DRP6E[11]MMCM:DRP6E[10]
    11----------------------------MMCM:DRP6E[9]MMCM:DRP6E[8]
    12----------------------------MMCM:DRP6E[7]MMCM:DRP6E[6]
    13----------------------------MMCM:DRP6E[5]MMCM:DRP6E[4]
    14----------------------------MMCM:DRP6E[3]MMCM:DRP6E[2]
    15----------------------------MMCM:DRP6E[1]MMCM:DRP6E[0]
    16----------------------------MMCM:DRP6D[15]MMCM:DRP6D[14]
    17----------------------------MMCM:DRP6D[13]MMCM:DRP6D[12]
    18----------------------------MMCM:DRP6D[11]MMCM:DRP6D[10]
    19----------------------------MMCM:DRP6D[9]MMCM:DRP6D[8]
    20----------------------------MMCM:DRP6D[7]MMCM:DRP6D[6]
    21----------------------------MMCM:DRP6D[5]MMCM:DRP6D[4]
    22----------------------------MMCM:DRP6D[3]MMCM:DRP6D[2]
    23----------------------------MMCM:DRP6D[1]MMCM:DRP6D[0]
    24----------------------------MMCM:DRP6C[15]MMCM:DRP6C[14]
    25----------------------------MMCM:DRP6C[13]MMCM:DRP6C[12]
    26----------------------------MMCM:DRP6C[11]MMCM:DRP6C[10]
    27----------------------------MMCM:DRP6C[9]MMCM:DRP6C[8]
    28----------------------------MMCM:DRP6C[7]MMCM:DRP6C[6]
    29----------------------------MMCM:DRP6C[5]MMCM:DRP6C[4]
    30----------------------------MMCM:DRP6C[3]MMCM:DRP6C[2]
    31----------------------------MMCM:DRP6C[1]MMCM:DRP6C[0]
    32----------------------------MMCM:DRP6B[15]MMCM:DRP6B[14]
    33----------------------------MMCM:DRP6B[13]MMCM:DRP6B[12]
    34----------------------------MMCM:DRP6B[11]MMCM:DRP6B[10]
    35----------------------------MMCM:DRP6B[9]MMCM:DRP6B[8]
    36----------------------------MMCM:DRP6B[7]MMCM:DRP6B[6]
    37----------------------------MMCM:DRP6B[5]MMCM:DRP6B[4]
    38----------------------------MMCM:DRP6B[3]MMCM:DRP6B[2]
    39----------------------------MMCM:DRP6B[1]MMCM:DRP6B[0]
    40----------------------------MMCM:DRP6A[15]MMCM:DRP6A[14]
    41----------------------------MMCM:DRP6A[13]MMCM:DRP6A[12]
    42----------------------------MMCM:DRP6A[11]MMCM:DRP6A[10]
    43----------------------------MMCM:DRP6A[9]MMCM:DRP6A[8]
    44----------------------------MMCM:DRP6A[7]MMCM:DRP6A[6]
    45----------------------------MMCM:DRP6A[5]MMCM:DRP6A[4]
    46----------------------------MMCM:DRP6A[3]MMCM:DRP6A[2]
    47----------------------------MMCM:DRP6A[1]MMCM:DRP6A[0]
    48----------------------------MMCM:DRP69[15]MMCM:DRP69[14]
    49----------------------------MMCM:DRP69[13]MMCM:DRP69[12]
    50----------------------------MMCM:DRP69[11]MMCM:DRP69[10]
    51----------------------------MMCM:DRP69[9]MMCM:DRP69[8]
    52----------------------------MMCM:DRP69[7]MMCM:DRP69[6]
    53----------------------------MMCM:DRP69[5]MMCM:DRP69[4]
    54----------------------------MMCM:DRP69[3]MMCM:DRP69[2]
    55----------------------------MMCM:DRP69[1]MMCM:DRP69[0]
    56----------------------------MMCM:DRP68[15]MMCM:DRP68[14]
    57----------------------------MMCM:DRP68[13]MMCM:DRP68[12]
    58----------------------------MMCM:DRP68[11]MMCM:DRP68[10]
    59----------------------------MMCM:DRP68[9]MMCM:DRP68[8]
    60----------------------------MMCM:DRP68[7]MMCM:DRP68[6]
    61----------------------------MMCM:DRP68[5]MMCM:DRP68[4]
    62----------------------------MMCM:DRP68[3]MMCM:DRP68[2]
    63----------------------------MMCM:DRP68[1]MMCM:DRP68[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 3
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP67[15]MMCM:DRP67[14]
    1----------------------------MMCM:DRP67[13]MMCM:DRP67[12]
    2----------------------------MMCM:DRP67[11]MMCM:DRP67[10]
    3----------------------------MMCM:DRP67[9]MMCM:DRP67[8]
    4----------------------------MMCM:DRP67[7]MMCM:DRP67[6]
    5----------------------------MMCM:DRP67[5]MMCM:DRP67[4]
    6----------------------------MMCM:DRP67[3]MMCM:DRP67[2]
    7----------------------------MMCM:DRP67[1]MMCM:DRP67[0]
    8----------------------------MMCM:DRP66[15]MMCM:DRP66[14]
    9----------------------------MMCM:DRP66[13]MMCM:DRP66[12]
    10----------------------------MMCM:DRP66[11]MMCM:DRP66[10]
    11----------------------------MMCM:DRP66[9]MMCM:DRP66[8]
    12----------------------------MMCM:DRP66[7]MMCM:DRP66[6]
    13----------------------------MMCM:DRP66[5]MMCM:DRP66[4]
    14----------------------------MMCM:DRP66[3]MMCM:DRP66[2]
    15----------------------------MMCM:DRP66[1]MMCM:DRP66[0]
    16----------------------------MMCM:DRP65[15]MMCM:DRP65[14]
    17----------------------------MMCM:DRP65[13]MMCM:DRP65[12]
    18----------------------------MMCM:DRP65[11]MMCM:DRP65[10]
    19----------------------------MMCM:DRP65[9]MMCM:DRP65[8]
    20----------------------------MMCM:DRP65[7]MMCM:DRP65[6]
    21----------------------------MMCM:DRP65[5]MMCM:DRP65[4]
    22----------------------------MMCM:DRP65[3]MMCM:DRP65[2]
    23----------------------------MMCM:DRP65[1]MMCM:DRP65[0]
    24----------------------------MMCM:DRP64[15]MMCM:DRP64[14]
    25----------------------------MMCM:DRP64[13]MMCM:DRP64[12]
    26----------------------------MMCM:DRP64[11]MMCM:DRP64[10]
    27----------------------------MMCM:DRP64[9]MMCM:DRP64[8]
    28----------------------------MMCM:DRP64[7]MMCM:DRP64[6]
    29----------------------------MMCM:DRP64[5]MMCM:DRP64[4]
    30----------------------------MMCM:DRP64[3]MMCM:DRP64[2]
    31----------------------------MMCM:DRP64[1]MMCM:DRP64[0]
    32----------------------------MMCM:DRP63[15]MMCM:DRP63[14]
    33----------------------------MMCM:DRP63[13]MMCM:DRP63[12]
    34----------------------------MMCM:DRP63[11]MMCM:DRP63[10]
    35----------------------------MMCM:DRP63[9]MMCM:DRP63[8]
    36----------------------------MMCM:DRP63[7]MMCM:DRP63[6]
    37----------------------------MMCM:DRP63[5]MMCM:DRP63[4]
    38----------------------------MMCM:DRP63[3]MMCM:DRP63[2]
    39----------------------------MMCM:DRP63[1]MMCM:DRP63[0]
    40----------------------------MMCM:DRP62[15]MMCM:DRP62[14]
    41----------------------------MMCM:DRP62[13]MMCM:DRP62[12]
    42----------------------------MMCM:DRP62[11]MMCM:DRP62[10]
    43----------------------------MMCM:DRP62[9]MMCM:DRP62[8]
    44----------------------------MMCM:DRP62[7]MMCM:DRP62[6]
    45----------------------------MMCM:DRP62[5]MMCM:DRP62[4]
    46----------------------------MMCM:DRP62[3]MMCM:DRP62[2]
    47----------------------------MMCM:DRP62[1]MMCM:DRP62[0]
    48----------------------------MMCM:DRP61[15]MMCM:DRP61[14]
    49----------------------------MMCM:DRP61[13]MMCM:DRP61[12]
    50----------------------------MMCM:DRP61[11]MMCM:DRP61[10]
    51----------------------------MMCM:DRP61[9]MMCM:DRP61[8]
    52----------------------------MMCM:DRP61[7]MMCM:DRP61[6]
    53----------------------------MMCM:DRP61[5]MMCM:DRP61[4]
    54----------------------------MMCM:DRP61[3]MMCM:DRP61[2]
    55----------------------------MMCM:DRP61[1]MMCM:DRP61[0]
    56----------------------------MMCM:DRP60[15]MMCM:DRP60[14]
    57----------------------------MMCM:DRP60[13]MMCM:DRP60[12]
    58----------------------------MMCM:DRP60[11]MMCM:DRP60[10]
    59----------------------------MMCM:DRP60[9]MMCM:DRP60[8]
    60----------------------------MMCM:DRP60[7]MMCM:DRP60[6]
    61----------------------------MMCM:DRP60[5]MMCM:DRP60[4]
    62----------------------------MMCM:DRP60[3]MMCM:DRP60[2]
    63----------------------------MMCM:DRP60[1]MMCM:DRP60[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 4
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP5F[15]MMCM:DRP5F[14]
    1----------------------------MMCM:DRP5F[13]MMCM:DRP5F[12]
    2----------------------------MMCM:DRP5F[11]MMCM:DRP5F[10]
    3----------------------------MMCM:DRP5F[9]MMCM:DRP5F[8]
    4----------------------------MMCM:DRP5F[7]MMCM:DRP5F[6]
    5----------------------------MMCM:DRP5F[5]MMCM:DRP5F[4]
    6----------------------------MMCM:DRP5F[3]MMCM:DRP5F[2]
    7----------------------------MMCM:DRP5F[1]MMCM:DRP5F[0]
    8----------------------------MMCM:DRP5E[15]MMCM:DRP5E[14]
    9----------------------------MMCM:DRP5E[13]MMCM:DRP5E[12]
    10----------------------------MMCM:DRP5E[11]MMCM:DRP5E[10]
    11----------------------------MMCM:DRP5E[9]MMCM:DRP5E[8]
    12----------------------------MMCM:DRP5E[7]MMCM:DRP5E[6]
    13----------------------------MMCM:DRP5E[5]MMCM:DRP5E[4]
    14----------------------------MMCM:DRP5E[3]MMCM:DRP5E[2]
    15----------------------------MMCM:DRP5E[1]MMCM:DRP5E[0]
    16----------------------------MMCM:DRP5D[15]MMCM:DRP5D[14]
    17----------------------------MMCM:DRP5D[13]MMCM:DRP5D[12]
    18----------------------------MMCM:DRP5D[11]MMCM:DRP5D[10]
    19----------------------------MMCM:DRP5D[9]MMCM:DRP5D[8]
    20----------------------------MMCM:DRP5D[7]MMCM:DRP5D[6]
    21----------------------------MMCM:DRP5D[5]MMCM:DRP5D[4]
    22----------------------------MMCM:DRP5D[3]MMCM:DRP5D[2]
    23----------------------------MMCM:DRP5D[1]MMCM:DRP5D[0]
    24----------------------------MMCM:DRP5C[15]MMCM:DRP5C[14]
    25----------------------------MMCM:DRP5C[13]MMCM:DRP5C[12]
    26----------------------------MMCM:DRP5C[11]MMCM:DRP5C[10]
    27----------------------------MMCM:DRP5C[9]MMCM:DRP5C[8]
    28----------------------------MMCM:DRP5C[7]MMCM:DRP5C[6]
    29----------------------------MMCM:DRP5C[5]MMCM:DRP5C[4]
    30----------------------------MMCM:DRP5C[3]MMCM:DRP5C[2]
    31----------------------------MMCM:DRP5C[1]MMCM:DRP5C[0]
    32----------------------------MMCM:DRP5B[15]MMCM:DRP5B[14]
    33----------------------------MMCM:DRP5B[13]MMCM:DRP5B[12]
    34----------------------------MMCM:DRP5B[11]MMCM:DRP5B[10]
    35----------------------------MMCM:DRP5B[9]MMCM:DRP5B[8]
    36----------------------------MMCM:DRP5B[7]MMCM:DRP5B[6]
    37----------------------------MMCM:DRP5B[5]MMCM:DRP5B[4]
    38----------------------------MMCM:DRP5B[3]MMCM:DRP5B[2]
    39----------------------------MMCM:DRP5B[1]MMCM:DRP5B[0]
    40----------------------------MMCM:DRP5A[15]MMCM:DRP5A[14]
    41----------------------------MMCM:DRP5A[13]MMCM:DRP5A[12]
    42----------------------------MMCM:DRP5A[11]MMCM:DRP5A[10]
    43----------------------------MMCM:DRP5A[9]MMCM:DRP5A[8]
    44----------------------------MMCM:DRP5A[7]MMCM:DRP5A[6]
    45----------------------------MMCM:DRP5A[5]MMCM:DRP5A[4]
    46----------------------------MMCM:DRP5A[3]MMCM:DRP5A[2]
    47----------------------------MMCM:DRP5A[1]MMCM:DRP5A[0]
    48----------------------------MMCM:DRP59[15]MMCM:DRP59[14]
    49----------------------------MMCM:DRP59[13]MMCM:DRP59[12]
    50----------------------------MMCM:DRP59[11]MMCM:DRP59[10]
    51----------------------------MMCM:DRP59[9]MMCM:DRP59[8]
    52----------------------------MMCM:DRP59[7]MMCM:DRP59[6]
    53----------------------------MMCM:DRP59[5]MMCM:DRP59[4]
    54----------------------------MMCM:DRP59[3]MMCM:DRP59[2]
    55----------------------------MMCM:DRP59[1]MMCM:DRP59[0]
    56----------------------------MMCM:DRP58[15]MMCM:DRP58[14]
    57----------------------------MMCM:DRP58[13]MMCM:DRP58[12]
    58----------------------------MMCM:DRP58[11]MMCM:DRP58[10]
    59----------------------------MMCM:DRP58[9]MMCM:DRP58[8]
    60----------------------------MMCM:DRP58[7]MMCM:DRP58[6]
    61----------------------------MMCM:DRP58[5]MMCM:DRP58[4]
    62----------------------------MMCM:DRP58[3]MMCM:DRP58[2]
    63----------------------------MMCM:DRP58[1]MMCM:DRP58[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 5
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP57[15]MMCM:DRP57[14]
    1----------------------------MMCM:DRP57[13]MMCM:DRP57[12]
    2----------------------------MMCM:DRP57[11]MMCM:DRP57[10]
    3----------------------------MMCM:DRP57[9]MMCM:DRP57[8]
    4----------------------------MMCM:DRP57[7]MMCM:DRP57[6]
    5----------------------------MMCM:DRP57[5]MMCM:DRP57[4]
    6----------------------------MMCM:DRP57[3]MMCM:DRP57[2]
    7----------------------------MMCM:DRP57[1]MMCM:DRP57[0]
    8----------------------------MMCM:DRP56[15]MMCM:DRP56[14]
    9----------------------------MMCM:DRP56[13]MMCM:DRP56[12]
    10----------------------------MMCM:DRP56[11]MMCM:DRP56[10]
    11----------------------------MMCM:DRP56[9]MMCM:DRP56[8]
    12----------------------------MMCM:DRP56[7]MMCM:DRP56[6]
    13----------------------------MMCM:DRP56[5]MMCM:DRP56[4]
    14----------------------------MMCM:DRP56[3]MMCM:DRP56[2]
    15----------------------------MMCM:DRP56[1]MMCM:DRP56[0]
    16----------------------------MMCM:DRP55[15]MMCM:DRP55[14]
    17----------------------------MMCM:DRP55[13]MMCM:DRP55[12]
    18----------------------------MMCM:DRP55[11]MMCM:DRP55[10]
    19----------------------------MMCM:DRP55[9]MMCM:DRP55[8]
    20----------------------------MMCM:DRP55[7]MMCM:DRP55[6]
    21----------------------------MMCM:DRP55[5]MMCM:DRP55[4]
    22----------------------------MMCM:DRP55[3]MMCM:DRP55[2]
    23----------------------------MMCM:DRP55[1]MMCM:DRP55[0]
    24----------------------------MMCM:DRP54[15]MMCM:DRP54[14]
    25----------------------------MMCM:DRP54[13]MMCM:DRP54[12]
    26----------------------------MMCM:DRP54[11]MMCM:DRP54[10]
    27----------------------------MMCM:DRP54[9]MMCM:DRP54[8]
    28----------------------------MMCM:DRP54[7]MMCM:DRP54[6]
    29----------------------------MMCM:DRP54[5]MMCM:DRP54[4]
    30----------------------------MMCM:DRP54[3]MMCM:DRP54[2]
    31----------------------------MMCM:DRP54[1]MMCM:DRP54[0]
    32----------------------------MMCM:DRP53[15]MMCM:DRP53[14]
    33----------------------------MMCM:DRP53[13]MMCM:DRP53[12]
    34----------------------------MMCM:DRP53[11]MMCM:DRP53[10]
    35----------------------------MMCM:DRP53[9]MMCM:DRP53[8]
    36----------------------------MMCM:DRP53[7]MMCM:DRP53[6]
    37----------------------------MMCM:DRP53[5]MMCM:DRP53[4]
    38----------------------------MMCM:DRP53[3]MMCM:DRP53[2]
    39----------------------------MMCM:DRP53[1]MMCM:DRP53[0]
    40----------------------------MMCM:DRP52[15]MMCM:DRP52[14]
    41----------------------------MMCM:DRP52[13]MMCM:DRP52[12]
    42----------------------------MMCM:DRP52[11]MMCM:DRP52[10]
    43----------------------------MMCM:DRP52[9]MMCM:DRP52[8]
    44----------------------------MMCM:DRP52[7]MMCM:DRP52[6]
    45----------------------------MMCM:DRP52[5]MMCM:DRP52[4]
    46----------------------------MMCM:DRP52[3]MMCM:DRP52[2]
    47----------------------------MMCM:DRP52[1]MMCM:DRP52[0]
    48----------------------------MMCM:DRP51[15]MMCM:DRP51[14]
    49----------------------------MMCM:DRP51[13]MMCM:DRP51[12]
    50----------------------------MMCM:DRP51[11]MMCM:DRP51[10]
    51----------------------------MMCM:DRP51[9]MMCM:DRP51[8]
    52----------------------------MMCM:DRP51[7]MMCM:DRP51[6]
    53----------------------------MMCM:DRP51[5]MMCM:DRP51[4]
    54----------------------------MMCM:DRP51[3]MMCM:DRP51[2]
    55----------------------------MMCM:DRP51[1]MMCM:DRP51[0]
    56----------------------------MMCM:DRP50[15]MMCM:DRP50[14]
    57----------------------------MMCM:DRP50[13]MMCM:DRP50[12]
    58----------------------------MMCM:DRP50[11]MMCM:DRP50[10]
    59----------------------------MMCM:DRP50[9]MMCM:DRP50[8]
    60----------------------------MMCM:DRP50[7]MMCM:DRP50[6]
    61----------------------------MMCM:DRP50[5]MMCM:DRP50[4]
    62----------------------------MMCM:DRP50[3]MMCM:DRP50[2]
    63----------------------------MMCM:DRP50[1]MMCM:DRP50[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 6
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP4F[15]
    MMCM:RES[3]    		MMCM:DRP4F[14]
    1----------------------------MMCM:DRP4F[13]MMCM:DRP4F[12]
    MMCM:RES[2]
    2----------------------------MMCM:DRP4F[11]
    MMCM:RES[1]    		MMCM:DRP4F[10]
    3----------------------------MMCM:DRP4F[9]MMCM:DRP4F[8]
    MMCM:RES[0]
    4----------------------------MMCM:DRP4F[7]
    MMCM:LFHF[1]    		MMCM:DRP4F[6]
    5----------------------------MMCM:DRP4F[5]MMCM:DRP4F[4]
    MMCM:LFHF[0]
    6----------------------------MMCM:DRP4F[3]MMCM:DRP4F[2]
    7----------------------------MMCM:DRP4F[1]MMCM:DRP4F[0]
    8----------------------------MMCM:CP[3]
    MMCM:DRP4E[15]    		MMCM:DRP4E[14]
    9----------------------------MMCM:DRP4E[13]MMCM:CP[2]
    MMCM:DRP4E[12]
    10----------------------------MMCM:CP[1]
    MMCM:DRP4E[11]    		MMCM:DRP4E[10]
    11----------------------------MMCM:DRP4E[9]MMCM:CP[0]
    MMCM:DRP4E[8]
    12----------------------------MMCM:CP_BIAS_TRIP_SET
    MMCM:DRP4E[7]    		MMCM:DRP4E[6]
    13----------------------------MMCM:DRP4E[5]MMCM:CP_RES[1]
    MMCM:DRP4E[4]
    14----------------------------MMCM:CP_RES[0]
    MMCM:DRP4E[3]    		MMCM:DRP4E[2]
    15----------------------------MMCM:DRP4E[1]MMCM:DRP4E[0]
    16----------------------------MMCM:DRP4D[15]MMCM:DRP4D[14]
    17----------------------------MMCM:DRP4D[13]MMCM:DRP4D[12]
    18----------------------------MMCM:DRP4D[11]MMCM:DRP4D[10]
    19----------------------------MMCM:DRP4D[9]MMCM:DRP4D[8]
    20----------------------------MMCM:DRP4D[7]MMCM:DRP4D[6]
    21----------------------------MMCM:DRP4D[5]MMCM:DRP4D[4]
    22----------------------------MMCM:DRP4D[3]MMCM:DRP4D[2]
    23----------------------------MMCM:DRP4D[1]MMCM:DRP4D[0]
    24----------------------------MMCM:DRP4C[15]MMCM:DRP4C[14]
    25----------------------------MMCM:DRP4C[13]MMCM:DRP4C[12]
    MMCM:HVLF_CNT_TEST_EN
    26----------------------------MMCM:DRP4C[11]
    MMCM:HVLF_CNT_TEST[5]    		MMCM:DRP4C[10]
    27----------------------------MMCM:DRP4C[9]MMCM:DRP4C[8]
    MMCM:HVLF_CNT_TEST[4]
    28----------------------------MMCM:DRP4C[7]
    MMCM:HVLF_CNT_TEST[3]    		MMCM:DRP4C[6]
    29----------------------------MMCM:DRP4C[5]MMCM:DRP4C[4]
    MMCM:HVLF_CNT_TEST[2]
    30----------------------------MMCM:DRP4C[3]
    MMCM:HVLF_CNT_TEST[1]    		MMCM:DRP4C[2]
    31----------------------------MMCM:DRP4C[1]MMCM:DRP4C[0]
    MMCM:HVLF_CNT_TEST[0]
    32----------------------------MMCM:DRP4B[15]MMCM:DRP4B[14]
    33----------------------------MMCM:DRP4B[13]MMCM:DRP4B[12]
    34----------------------------MMCM:DRP4B[11]MMCM:DRP4B[10]
    35----------------------------MMCM:DRP4B[9]MMCM:DRP4B[8]
    36----------------------------MMCM:DRP4B[7]MMCM:DRP4B[6]
    37----------------------------MMCM:DRP4B[5]MMCM:DRP4B[4]
    38----------------------------MMCM:DRP4B[3]MMCM:DRP4B[2]
    39----------------------------MMCM:DRP4B[1]MMCM:DRP4B[0]
    40----------------------------MMCM:DRP4A[15]MMCM:DRP4A[14]
    41----------------------------MMCM:DRP4A[13]MMCM:DRP4A[12]
    42----------------------------MMCM:DRP4A[11]MMCM:DRP4A[10]
    43----------------------------MMCM:AVDD_COMP_SET[2]
    MMCM:DRP4A[9]    		MMCM:AVDD_COMP_SET[1]
    MMCM:DRP4A[8]
    44----------------------------MMCM:AVDD_COMP_SET[0]
    MMCM:DRP4A[7]    		MMCM:AVDD_VBG_PD[2]
    MMCM:DRP4A[6]
    45----------------------------MMCM:AVDD_VBG_PD[1]
    MMCM:DRP4A[5]    		MMCM:AVDD_VBG_PD[0]
    MMCM:DRP4A[4]
    46----------------------------MMCM:AVDD_VBG_SEL[3]
    MMCM:DRP4A[3]    		MMCM:AVDD_VBG_SEL[2]
    MMCM:DRP4A[2]
    47----------------------------MMCM:AVDD_VBG_SEL[1]
    MMCM:DRP4A[1]    		MMCM:AVDD_VBG_SEL[0]
    MMCM:DRP4A[0]
    48----------------------------MMCM:DRP49[15]
    MMCM:SUP_SEL_AREG    		MMCM:DRP49[14]
    MMCM:EN_CURR_SINK[1]
    49----------------------------MMCM:DRP49[13]
    MMCM:EN_CURR_SINK[0]    		MMCM:DRP49[12]
    MMCM:MVDD_SEL[1]
    50----------------------------MMCM:DRP49[11]
    MMCM:MVDD_SEL[0]    		MMCM:DRP49[10]
    MMCM:SEL_HV_NMOS
    51----------------------------MMCM:DRP49[9]MMCM:DRP49[8]
    52----------------------------MMCM:DRP49[7]MMCM:DRP49[6]
    53----------------------------MMCM:DRP49[5]MMCM:DRP49[4]
    54----------------------------MMCM:DRP49[3]MMCM:DRP49[2]
    55----------------------------MMCM:DRP49[1]MMCM:DRP49[0]
    56----------------------------MMCM:DRP48[15]MMCM:DRP48[14]
    57----------------------------MMCM:DRP48[13]MMCM:DRP48[12]
    58----------------------------MMCM:DRP48[11]MMCM:DRP48[10]
    59----------------------------MMCM:DRP48[9]MMCM:DRP48[8]
    60----------------------------MMCM:DRP48[7]MMCM:DRP48[6]
    61----------------------------MMCM:DRP48[5]MMCM:DRP48[4]
    62----------------------------MMCM:DRP48[3]MMCM:DRP48[2]
    63----------------------------MMCM:DRP48[1]MMCM:DRP48[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 7
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP47[15]MMCM:DRP47[14]
    1----------------------------MMCM:DRP47[13]MMCM:DRP47[12]
    2----------------------------MMCM:DRP47[11]MMCM:DRP47[10]
    3----------------------------MMCM:DRP47[9]MMCM:DRP47[8]
    4----------------------------MMCM:DRP47[7]MMCM:DRP47[6]
    5----------------------------MMCM:DRP47[5]MMCM:DRP47[4]
    6----------------------------MMCM:DRP47[3]MMCM:DRP47[2]
    7----------------------------MMCM:DRP47[1]MMCM:DRP47[0]
    8----------------------------MMCM:DRP46[15]MMCM:DRP46[14]
    9----------------------------MMCM:DRP46[13]MMCM:DRP46[12]
    10----------------------------MMCM:DRP46[11]MMCM:DRP46[10]
    11----------------------------MMCM:DRP46[9]MMCM:DRP46[8]
    12----------------------------MMCM:DRP46[7]MMCM:DRP46[6]
    13----------------------------MMCM:DRP46[5]MMCM:DRP46[4]
    14----------------------------MMCM:DRP46[3]MMCM:DRP46[2]
    15----------------------------MMCM:DRP46[1]MMCM:DRP46[0]
    MMCM:VLF_HIGH_PWDN_B
    16----------------------------MMCM:DRP45[15]MMCM:DRP45[14]
    17----------------------------MMCM:DRP45[13]MMCM:DRP45[12]
    MMCM:VREF_START[1]
    18----------------------------MMCM:DRP45[11]
    MMCM:VREF_START[0]    		MMCM:DRP45[10]
    19----------------------------MMCM:DRP45[9]MMCM:DRP45[8]
    20----------------------------MMCM:DRP45[7]MMCM:DRP45[6]
    21----------------------------MMCM:DRP45[5]MMCM:DRP45[4]
    22----------------------------MMCM:DRP45[3]MMCM:DRP45[2]
    23----------------------------MMCM:DRP45[1]MMCM:DRP45[0]
    24----------------------------MMCM:DRP44[15]MMCM:DRP44[14]
    25----------------------------MMCM:DRP44[13]MMCM:DRP44[12]
    26----------------------------MMCM:DRP44[11]MMCM:DRP44[10]
    27----------------------------MMCM:DRP44[9]MMCM:DRP44[8]
    MMCM:SPARE_ANALOG[4]
    28----------------------------MMCM:DRP44[7]
    MMCM:SPARE_ANALOG[3]    		MMCM:DRP44[6]
    29----------------------------MMCM:DRP44[5]MMCM:DRP44[4]
    MMCM:SPARE_ANALOG[2]
    30----------------------------MMCM:DRP44[3]
    MMCM:SPARE_ANALOG[1]    		MMCM:DRP44[2]
    31----------------------------MMCM:DRP44[1]MMCM:DRP44[0]
    MMCM:SPARE_ANALOG[0]
    32----------------------------MMCM:DRP43[15]MMCM:DRP43[14]
    33----------------------------MMCM:DRP43[13]MMCM:DRP43[12]
    34----------------------------MMCM:DRP43[11]MMCM:DRP43[10]
    35----------------------------MMCM:DRP43[9]MMCM:DRP43[8]
    36----------------------------MMCM:DRP43[7]MMCM:DRP43[6]
    37----------------------------MMCM:DRP43[5]MMCM:DRP43[4]
    38----------------------------MMCM:DRP43[3]MMCM:DRP43[2]
    39----------------------------MMCM:DRP43[1]MMCM:DRP43[0]
    MMCM:LF_LOW_SEL
    40----------------------------MMCM:DRP42[15]
    MMCM:LF_NEN[1]    		MMCM:DRP42[14]
    41----------------------------MMCM:DRP42[13]MMCM:DRP42[12]
    MMCM:LF_NEN[0]
    42----------------------------MMCM:DRP42[11]
    MMCM:LF_PEN[1]    		MMCM:DRP42[10]
    43----------------------------MMCM:DRP42[9]MMCM:DRP42[8]
    MMCM:LF_PEN[0]
    44----------------------------MMCM:DRP42[7]
    MMCM:VLF_HIGH_DIS_B    		MMCM:DRP42[6]
    45----------------------------MMCM:DRP42[5]MMCM:DRP42[4]
    MMCM:MAN_LF[2]
    46----------------------------MMCM:DRP42[3]
    MMCM:MAN_LF[1]    		MMCM:DRP42[2]
    47----------------------------MMCM:DRP42[1]MMCM:DRP42[0]
    MMCM:MAN_LF[0]
    48----------------------------MMCM:DRP41[15]MMCM:DRP41[14]
    49----------------------------MMCM:DRP41[13]MMCM:DRP41[12]
    50----------------------------MMCM:DRP41[11]MMCM:DRP41[10]
    51----------------------------MMCM:DRP41[9]MMCM:DRP41[8]
    52----------------------------MMCM:DRP41[7]MMCM:DRP41[6]
    53----------------------------MMCM:DRP41[5]MMCM:DRP41[4]
    54----------------------------MMCM:DRP41[3]MMCM:DRP41[2]
    55----------------------------MMCM:DRP41[1]MMCM:DRP41[0]
    56----------------------------MMCM:DRP40[15]MMCM:DRP40[14]
    57----------------------------MMCM:DRP40[13]MMCM:DRP40[12]
    58----------------------------MMCM:DRP40[11]MMCM:DRP40[10]
    59----------------------------MMCM:DRP40[9]MMCM:DRP40[8]
    60----------------------------MMCM:DRP40[7]MMCM:DRP40[6]
    61----------------------------MMCM:DRP40[5]MMCM:DRP40[4]
    62----------------------------MMCM:DRP40[3]MMCM:DRP40[2]
    63----------------------------MMCM:DRP40[1]MMCM:DRP40[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 8
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP3F[15]MMCM:DRP3F[14]
    1----------------------------MMCM:DRP3F[13]MMCM:DRP3F[12]
    2----------------------------MMCM:DRP3F[11]MMCM:DRP3F[10]
    3----------------------------MMCM:DRP3F[9]MMCM:DRP3F[8]
    4----------------------------MMCM:DRP3F[7]MMCM:DRP3F[6]
    5----------------------------MMCM:DRP3F[5]MMCM:DRP3F[4]
    6----------------------------MMCM:DRP3F[3]MMCM:DRP3F[2]
    7----------------------------MMCM:DRP3F[1]MMCM:DRP3F[0]
    8----------------------------MMCM:DRP3E[15]MMCM:DRP3E[14]
    9----------------------------MMCM:DRP3E[13]MMCM:DRP3E[12]
    10----------------------------MMCM:DRP3E[11]MMCM:DRP3E[10]
    11----------------------------MMCM:DRP3E[9]MMCM:DRP3E[8]
    12----------------------------MMCM:DRP3E[7]MMCM:DRP3E[6]
    13----------------------------MMCM:DRP3E[5]MMCM:DRP3E[4]
    14----------------------------MMCM:DRP3E[3]MMCM:DRP3E[2]
    15----------------------------MMCM:DRP3E[1]MMCM:DRP3E[0]
    16----------------------------MMCM:DRP3D[15]MMCM:DRP3D[14]
    17----------------------------MMCM:DRP3D[13]MMCM:DRP3D[12]
    18----------------------------MMCM:DRP3D[11]MMCM:DRP3D[10]
    19----------------------------MMCM:DRP3D[9]MMCM:DRP3D[8]
    20----------------------------MMCM:DRP3D[7]MMCM:DRP3D[6]
    21----------------------------MMCM:DRP3D[5]MMCM:DRP3D[4]
    22----------------------------MMCM:DRP3D[3]MMCM:DRP3D[2]
    23----------------------------MMCM:DRP3D[1]MMCM:DRP3D[0]
    24----------------------------MMCM:DRP3C[15]MMCM:DRP3C[14]
    25----------------------------MMCM:DRP3C[13]MMCM:DRP3C[12]
    26----------------------------MMCM:DRP3C[11]MMCM:DRP3C[10]
    27----------------------------MMCM:DRP3C[9]MMCM:DRP3C[8]
    28----------------------------MMCM:DRP3C[7]MMCM:DRP3C[6]
    29----------------------------MMCM:DRP3C[5]MMCM:DRP3C[4]
    30----------------------------MMCM:DRP3C[3]MMCM:DRP3C[2]
    31----------------------------MMCM:DRP3C[1]MMCM:DRP3C[0]
    32----------------------------MMCM:DRP3B[15]MMCM:DRP3B[14]
    33----------------------------MMCM:DRP3B[13]MMCM:DRP3B[12]
    34----------------------------MMCM:DRP3B[11]MMCM:DRP3B[10]
    35----------------------------MMCM:DRP3B[9]MMCM:DRP3B[8]
    36----------------------------MMCM:DRP3B[7]MMCM:DRP3B[6]
    37----------------------------MMCM:DRP3B[5]MMCM:DRP3B[4]
    38----------------------------MMCM:DRP3B[3]MMCM:DRP3B[2]
    39----------------------------MMCM:DRP3B[1]MMCM:DRP3B[0]
    40----------------------------MMCM:DRP3A[15]MMCM:DRP3A[14]
    41----------------------------MMCM:DRP3A[13]MMCM:DRP3A[12]
    42----------------------------MMCM:DRP3A[11]MMCM:DRP3A[10]
    43----------------------------MMCM:DRP3A[9]MMCM:DRP3A[8]
    44----------------------------MMCM:DRP3A[7]MMCM:DRP3A[6]
    45----------------------------MMCM:DRP3A[5]MMCM:DRP3A[4]
    46----------------------------MMCM:DRP3A[3]MMCM:DRP3A[2]
    47----------------------------MMCM:DRP3A[1]MMCM:DRP3A[0]
    48----------------------------MMCM:DRP39[15]MMCM:DRP39[14]
    49----------------------------MMCM:DRP39[13]MMCM:DRP39[12]
    50----------------------------MMCM:DRP39[11]MMCM:DRP39[10]
    51----------------------------MMCM:DRP39[9]MMCM:DRP39[8]
    52----------------------------MMCM:DRP39[7]MMCM:DRP39[6]
    53----------------------------MMCM:DRP39[5]MMCM:DRP39[4]
    54----------------------------MMCM:DRP39[3]MMCM:DRP39[2]
    55----------------------------MMCM:DRP39[1]MMCM:DRP39[0]
    56----------------------------MMCM:DRP38[15]MMCM:DRP38[14]
    57----------------------------MMCM:DRP38[13]MMCM:DRP38[12]
    58----------------------------MMCM:DRP38[11]MMCM:DRP38[10]
    59----------------------------MMCM:DRP38[9]MMCM:DRP38[8]
    60----------------------------MMCM:DRP38[7]MMCM:DRP38[6]
    61----------------------------MMCM:DRP38[5]MMCM:DRP38[4]
    62----------------------------MMCM:DRP38[3]MMCM:DRP38[2]
    63----------------------------MMCM:DRP38[1]MMCM:DRP38[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 9
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP37[15]MMCM:DRP37[14]
    1----------------------------MMCM:DRP37[13]MMCM:DRP37[12]
    2----------------------------MMCM:DRP37[11]MMCM:DRP37[10]
    3----------------------------MMCM:DRP37[9]MMCM:DRP37[8]
    4----------------------------MMCM:DRP37[7]MMCM:DRP37[6]
    5----------------------------MMCM:DRP37[5]MMCM:DRP37[4]
    6----------------------------MMCM:DRP37[3]MMCM:DRP37[2]
    7----------------------------MMCM:DRP37[1]MMCM:DRP37[0]
    8----------------------------MMCM:DRP36[15]MMCM:DRP36[14]
    9----------------------------MMCM:DRP36[13]MMCM:DRP36[12]
    10----------------------------MMCM:DRP36[11]MMCM:DRP36[10]
    11----------------------------MMCM:DRP36[9]MMCM:DRP36[8]
    12----------------------------MMCM:DRP36[7]MMCM:DRP36[6]
    13----------------------------MMCM:DRP36[5]MMCM:DRP36[4]
    14----------------------------MMCM:DRP36[3]MMCM:DRP36[2]
    15----------------------------MMCM:DRP36[1]MMCM:DRP36[0]
    16----------------------------MMCM:DRP35[15]MMCM:DRP35[14]
    17----------------------------MMCM:DRP35[13]MMCM:DRP35[12]
    18----------------------------MMCM:DRP35[11]MMCM:DRP35[10]
    19----------------------------MMCM:DRP35[9]MMCM:DRP35[8]
    20----------------------------MMCM:DRP35[7]MMCM:DRP35[6]
    21----------------------------MMCM:DRP35[5]MMCM:DRP35[4]
    22----------------------------MMCM:DRP35[3]MMCM:DRP35[2]
    23----------------------------MMCM:DRP35[1]MMCM:DRP35[0]
    24----------------------------MMCM:DRP34[15]MMCM:DRP34[14]
    25----------------------------MMCM:DRP34[13]MMCM:DRP34[12]
    26----------------------------MMCM:DRP34[11]MMCM:DRP34[10]
    27----------------------------MMCM:DRP34[9]MMCM:DRP34[8]
    28----------------------------MMCM:DRP34[7]MMCM:DRP34[6]
    29----------------------------MMCM:DRP34[5]MMCM:DRP34[4]
    30----------------------------MMCM:DRP34[3]MMCM:DRP34[2]
    31----------------------------MMCM:DRP34[1]MMCM:DRP34[0]
    32----------------------------MMCM:DRP33[15]MMCM:DRP33[14]
    33----------------------------MMCM:DRP33[13]MMCM:DRP33[12]
    34----------------------------MMCM:DRP33[11]MMCM:DRP33[10]
    35----------------------------MMCM:DRP33[9]MMCM:DRP33[8]
    36----------------------------MMCM:DRP33[7]MMCM:DRP33[6]
    37----------------------------MMCM:DRP33[5]MMCM:DRP33[4]
    38----------------------------MMCM:DRP33[3]MMCM:DRP33[2]
    39----------------------------MMCM:DRP33[1]MMCM:DRP33[0]
    40----------------------------MMCM:DRP32[15]MMCM:DRP32[14]
    41----------------------------MMCM:DRP32[13]MMCM:DRP32[12]
    42----------------------------MMCM:DRP32[11]MMCM:DRP32[10]
    43----------------------------MMCM:DRP32[9]MMCM:DRP32[8]
    44----------------------------MMCM:DRP32[7]MMCM:DRP32[6]
    45----------------------------MMCM:DRP32[5]MMCM:DRP32[4]
    46----------------------------MMCM:DRP32[3]MMCM:DRP32[2]
    47----------------------------MMCM:DRP32[1]MMCM:DRP32[0]
    48----------------------------MMCM:DRP31[15]MMCM:DRP31[14]
    49----------------------------MMCM:DRP31[13]MMCM:DRP31[12]
    50----------------------------MMCM:DRP31[11]MMCM:DRP31[10]
    51----------------------------MMCM:DRP31[9]MMCM:DRP31[8]
    52----------------------------MMCM:DRP31[7]MMCM:DRP31[6]
    53----------------------------MMCM:DRP31[5]MMCM:DRP31[4]
    54----------------------------MMCM:DRP31[3]MMCM:DRP31[2]
    55----------------------------MMCM:DRP31[1]MMCM:DRP31[0]
    56----------------------------MMCM:DRP30[15]MMCM:DRP30[14]
    57----------------------------MMCM:DRP30[13]MMCM:DRP30[12]
    58----------------------------MMCM:DRP30[11]MMCM:DRP30[10]
    59----------------------------MMCM:DRP30[9]MMCM:DRP30[8]
    60----------------------------MMCM:DRP30[7]MMCM:DRP30[6]
    61----------------------------MMCM:DRP30[5]MMCM:DRP30[4]
    62----------------------------MMCM:DRP30[3]MMCM:DRP30[2]
    63----------------------------MMCM:DRP30[1]MMCM:DRP30[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 10
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP2F[15]MMCM:DRP2F[14]
    1----------------------------MMCM:DRP2F[13]MMCM:DRP2F[12]
    2----------------------------MMCM:DRP2F[11]MMCM:DRP2F[10]
    3----------------------------MMCM:DRP2F[9]MMCM:DRP2F[8]
    4----------------------------MMCM:DRP2F[7]MMCM:DRP2F[6]
    5----------------------------MMCM:DRP2F[5]MMCM:DRP2F[4]
    6----------------------------MMCM:DRP2F[3]MMCM:DRP2F[2]
    7----------------------------MMCM:DRP2F[1]MMCM:DRP2F[0]
    8----------------------------MMCM:DRP2E[15]MMCM:DRP2E[14]
    9----------------------------MMCM:DRP2E[13]MMCM:DRP2E[12]
    10----------------------------MMCM:DRP2E[11]MMCM:DRP2E[10]
    11----------------------------MMCM:DRP2E[9]MMCM:DRP2E[8]
    12----------------------------MMCM:DRP2E[7]MMCM:DRP2E[6]
    13----------------------------MMCM:DRP2E[5]MMCM:DRP2E[4]
    14----------------------------MMCM:DRP2E[3]MMCM:DRP2E[2]
    15----------------------------MMCM:DRP2E[1]MMCM:DRP2E[0]
    16----------------------------MMCM:DRP2D[15]MMCM:DRP2D[14]
    17----------------------------MMCM:DRP2D[13]MMCM:DRP2D[12]
    18----------------------------MMCM:DRP2D[11]MMCM:DRP2D[10]
    19----------------------------MMCM:DRP2D[9]MMCM:DRP2D[8]
    20----------------------------MMCM:DRP2D[7]MMCM:DRP2D[6]
    21----------------------------MMCM:DRP2D[5]MMCM:DRP2D[4]
    22----------------------------MMCM:DRP2D[3]MMCM:DRP2D[2]
    23----------------------------MMCM:DRP2D[1]MMCM:DRP2D[0]
    24----------------------------MMCM:DRP2C[15]MMCM:DRP2C[14]
    25----------------------------MMCM:DRP2C[13]MMCM:DRP2C[12]
    26----------------------------MMCM:DRP2C[11]MMCM:DRP2C[10]
    27----------------------------MMCM:DRP2C[9]MMCM:DRP2C[8]
    28----------------------------MMCM:DRP2C[7]MMCM:DRP2C[6]
    29----------------------------MMCM:DRP2C[5]MMCM:DRP2C[4]
    30----------------------------MMCM:DRP2C[3]MMCM:DRP2C[2]
    31----------------------------MMCM:DRP2C[1]MMCM:DRP2C[0]
    32----------------------------MMCM:DRP2B[15]MMCM:DRP2B[14]
    33----------------------------MMCM:DRP2B[13]MMCM:DRP2B[12]
    34----------------------------MMCM:DRP2B[11]MMCM:DRP2B[10]
    35----------------------------MMCM:DRP2B[9]MMCM:DRP2B[8]
    36----------------------------MMCM:DRP2B[7]MMCM:DRP2B[6]
    37----------------------------MMCM:DRP2B[5]MMCM:DRP2B[4]
    38----------------------------MMCM:DRP2B[3]MMCM:DRP2B[2]
    39----------------------------MMCM:DRP2B[1]MMCM:DRP2B[0]
    40----------------------------MMCM:DRP2A[15]MMCM:DRP2A[14]
    41----------------------------MMCM:DRP2A[13]MMCM:DRP2A[12]
    42----------------------------MMCM:DRP2A[11]MMCM:DRP2A[10]
    43----------------------------MMCM:DRP2A[9]MMCM:DRP2A[8]
    44----------------------------MMCM:DRP2A[7]MMCM:DRP2A[6]
    45----------------------------MMCM:DRP2A[5]MMCM:DRP2A[4]
    46----------------------------MMCM:DRP2A[3]MMCM:DRP2A[2]
    47----------------------------MMCM:DRP2A[1]MMCM:DRP2A[0]
    48----------------------------MMCM:DRP29[15]MMCM:DRP29[14]
    49----------------------------MMCM:DRP29[13]MMCM:DRP29[12]
    50----------------------------MMCM:DRP29[11]MMCM:DRP29[10]
    51----------------------------MMCM:DRP29[9]MMCM:DRP29[8]
    52----------------------------MMCM:DRP29[7]MMCM:DRP29[6]
    53----------------------------MMCM:DRP29[5]MMCM:DRP29[4]
    54----------------------------MMCM:DRP29[3]MMCM:DRP29[2]
    55----------------------------MMCM:DRP29[1]MMCM:DRP29[0]
    56----------------------------MMCM:DRP28[15]
    MMCM:INTERP_EN[7]    		MMCM:DRP28[14]
    57----------------------------MMCM:DRP28[13]MMCM:DRP28[12]
    MMCM:INTERP_EN[6]
    58----------------------------MMCM:DRP28[11]
    MMCM:INTERP_EN[5]    		MMCM:DRP28[10]
    59----------------------------MMCM:DRP28[9]MMCM:DRP28[8]
    MMCM:INTERP_EN[4]
    60----------------------------MMCM:DRP28[7]
    MMCM:INTERP_EN[3]    		MMCM:DRP28[6]
    61----------------------------MMCM:DRP28[5]MMCM:DRP28[4]
    MMCM:INTERP_EN[2]
    62----------------------------MMCM:DRP28[3]
    MMCM:INTERP_EN[1]    		MMCM:DRP28[2]
    63----------------------------MMCM:DRP28[1]MMCM:DRP28[0]
    MMCM:INTERP_EN[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 11
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP27[15]MMCM:DRP27[14]
    1----------------------------MMCM:DRP27[13]MMCM:DRP27[12]
    2----------------------------MMCM:DRP27[11]MMCM:DRP27[10]
    3----------------------------MMCM:DRP27[9]MMCM:DRP27[8]
    4----------------------------MMCM:DRP27[7]MMCM:DRP27[6]
    5----------------------------MMCM:DRP27[5]MMCM:DRP27[4]
    6----------------------------MMCM:DRP27[3]MMCM:DRP27[2]
    7----------------------------MMCM:DRP27[1]MMCM:DRP27[0]
    8----------------------------MMCM:DRP26[15]MMCM:DRP26[14]
    9----------------------------MMCM:DRP26[13]MMCM:DRP26[12]
    10----------------------------MMCM:DRP26[11]MMCM:DRP26[10]
    11----------------------------MMCM:DRP26[9]MMCM:ANALOG_MISC[3]
    MMCM:DRP26[8]
    12----------------------------MMCM:ANALOG_MISC[2]
    MMCM:DRP26[7]    		MMCM:DRP26[6]
    13----------------------------MMCM:DRP26[5]MMCM:ANALOG_MISC[1]
    MMCM:DRP26[4]
    14----------------------------MMCM:ANALOG_MISC[0]
    MMCM:DRP26[3]    		MMCM:DRP26[2]
    15----------------------------MMCM:DRP26[1]MMCM:DRP26[0]
    16----------------------------MMCM:DRP25[15]MMCM:DRP25[14]
    17----------------------------MMCM:DRP25[13]MMCM:DRP25[12]
    18----------------------------MMCM:DRP25[11]MMCM:DRP25[10]
    19----------------------------MMCM:DRP25[9]MMCM:DRP25[8]
    20----------------------------MMCM:DRP25[7]MMCM:DRP25[6]
    21----------------------------MMCM:DRP25[5]MMCM:DRP25[4]
    22----------------------------MMCM:DRP25[3]MMCM:DRP25[2]
    23----------------------------MMCM:DRP25[1]MMCM:DRP25[0]
    24----------------------------MMCM:DRP24[15]MMCM:DRP24[14]
    25----------------------------MMCM:DRP24[13]MMCM:DRP24[12]
    26----------------------------MMCM:DRP24[11]MMCM:DRP24[10]
    27----------------------------MMCM:DRP24[9]MMCM:DRP24[8]
    28----------------------------MMCM:DRP24[7]MMCM:DRP24[6]
    29----------------------------MMCM:DRP24[5]MMCM:DRP24[4]
    30----------------------------MMCM:DRP24[3]MMCM:DRP24[2]
    31----------------------------MMCM:DRP24[1]MMCM:DRP24[0]
    32----------------------------MMCM:DRP23[15]MMCM:DRP23[14]
    33----------------------------MMCM:DRP23[13]MMCM:DRP23[12]
    34----------------------------MMCM:DRP23[11]MMCM:DRP23[10]
    35----------------------------MMCM:DRP23[9]MMCM:DRP23[8]
    36----------------------------MMCM:DRP23[7]MMCM:DRP23[6]
    37----------------------------MMCM:DRP23[5]MMCM:DRP23[4]
    38----------------------------MMCM:DRP23[3]MMCM:DRP23[2]
    39----------------------------MMCM:DRP23[1]MMCM:DRP23[0]
    40----------------------------MMCM:DRP22[15]MMCM:DRP22[14]
    41----------------------------MMCM:DRP22[13]MMCM:DRP22[12]
    42----------------------------MMCM:DRP22[11]MMCM:DRP22[10]
    43----------------------------MMCM:DRP22[9]MMCM:DRP22[8]
    44----------------------------MMCM:DRP22[7]MMCM:DRP22[6]
    45----------------------------MMCM:DRP22[5]MMCM:DRP22[4]
    46----------------------------MMCM:DRP22[3]MMCM:DRP22[2]
    MMCM:INTERP_TEST
    47----------------------------MMCM:DRP22[1]
    MMCM:EN_VCO_DIV1    		MMCM:DRP22[0]
    MMCM:EN_VCO_DIV6
    48----------------------------MMCM:DRP21[15]MMCM:DRP21[14]
    49----------------------------MMCM:DRP21[13]MMCM:DRP21[12]
    50----------------------------MMCM:DRP21[11]MMCM:DRP21[10]
    51----------------------------MMCM:DRP21[9]MMCM:DRP21[8]
    52----------------------------MMCM:DRP21[7]MMCM:DRP21[6]
    53----------------------------MMCM:DRP21[5]MMCM:DRP21[4]
    54----------------------------MMCM:DRP21[3]MMCM:DRP21[2]
    55----------------------------MMCM:DRP21[1]MMCM:DRP21[0]
    56----------------------------MMCM:DRP20[15]MMCM:DRP20[14]
    57----------------------------MMCM:DRP20[13]MMCM:DRP20[12]
    58----------------------------MMCM:DRP20[11]MMCM:DRP20[10]
    59----------------------------MMCM:DRP20[9]MMCM:DRP20[8]
    60----------------------------MMCM:DRP20[7]MMCM:DRP20[6]
    61----------------------------MMCM:DRP20[5]MMCM:DRP20[4]
    62----------------------------MMCM:DRP20[3]MMCM:DRP20[2]
    63----------------------------MMCM:DRP20[1]MMCM:DRP20[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 12
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP1F[15]MMCM:DRP1F[14]
    1----------------------------MMCM:DRP1F[13]MMCM:DRP1F[12]
    2----------------------------MMCM:DRP1F[11]MMCM:DRP1F[10]
    3----------------------------MMCM:DRP1F[9]
    MMCM:DVDD_COMP_SET[2]    		MMCM:DRP1F[8]
    MMCM:DVDD_COMP_SET[1]
    4----------------------------MMCM:DRP1F[7]
    MMCM:DVDD_COMP_SET[0]    		MMCM:DRP1F[6]
    MMCM:DVDD_VBG_PD[2]
    5----------------------------MMCM:DRP1F[5]
    MMCM:DVDD_VBG_PD[1]    		MMCM:DRP1F[4]
    MMCM:DVDD_VBG_PD[0]
    6----------------------------MMCM:DRP1F[3]
    MMCM:DVDD_VBG_SEL[3]    		MMCM:DRP1F[2]
    MMCM:DVDD_VBG_SEL[2]
    7----------------------------MMCM:DRP1F[1]
    MMCM:DVDD_VBG_SEL[1]    		MMCM:DRP1F[0]
    MMCM:DVDD_VBG_SEL[0]
    8----------------------------MMCM:DRP1E[15]
    MMCM:SUP_SEL_DREG    		MMCM:DRP1E[14]
    MMCM:SEL_LV_NMOS
    9----------------------------MMCM:DRP1E[13]MMCM:DRP1E[12]
    10----------------------------MMCM:DRP1E[11]MMCM:DRP1E[10]
    11----------------------------MMCM:DRP1E[9]MMCM:DRP1E[8]
    12----------------------------MMCM:DRP1E[7]MMCM:DRP1E[6]
    13----------------------------MMCM:DRP1E[5]MMCM:DRP1E[4]
    14----------------------------MMCM:DRP1E[3]MMCM:DRP1E[2]
    15----------------------------MMCM:DRP1E[1]MMCM:DRP1E[0]
    16----------------------------MMCM:DRP1D[15]MMCM:DRP1D[14]
    17----------------------------MMCM:DRP1D[13]MMCM:DRP1D[12]
    18----------------------------MMCM:DRP1D[11]
    MMCM:SEL_SLIPD    		MMCM:DRP1D[10]
    MMCM:PFD[6]
    19----------------------------MMCM:DRP1D[9]
    MMCM:PFD[5]    		MMCM:DRP1D[8]
    MMCM:PFD[4]
    20----------------------------MMCM:DRP1D[7]
    MMCM:PFD[3]    		MMCM:DRP1D[6]
    MMCM:PFD[2]
    21----------------------------MMCM:DRP1D[5]
    MMCM:PFD[1]    		MMCM:DRP1D[4]
    MMCM:PFD[0]
    22----------------------------MMCM:DRP1D[3]MMCM:DRP1D[2]
    23----------------------------MMCM:DRP1D[1]MMCM:DRP1D[0]
    24----------------------------MMCM:DRP1C[15]MMCM:DRP1C[14]
    25----------------------------MMCM:DRP1C[13]MMCM:DRP1C[12]
    26----------------------------MMCM:DRP1C[11]MMCM:DRP1C[10]
    27----------------------------MMCM:DRP1C[9]MMCM:DRP1C[8]
    28----------------------------MMCM:DRP1C[7]MMCM:DRP1C[6]
    29----------------------------MMCM:DRP1C[5]MMCM:DRP1C[4]
    MMCM:SPARE_DIGITAL[4]
    30----------------------------MMCM:DRP1C[3]
    MMCM:SPARE_DIGITAL[3]    		MMCM:DRP1C[2]
    MMCM:SPARE_DIGITAL[2]
    31----------------------------MMCM:DRP1C[1]
    MMCM:SPARE_DIGITAL[1]    		MMCM:DRP1C[0]
    MMCM:SPARE_DIGITAL[0]
    32----------------------------MMCM:DRP1B[15]MMCM:DRP1B[14]
    33----------------------------MMCM:DRP1B[13]MMCM:DRP1B[12]
    34----------------------------MMCM:DRP1B[11]MMCM:DRP1B[10]
    35----------------------------MMCM:DRP1B[9]MMCM:DRP1B[8]
    36----------------------------MMCM:DRP1B[7]MMCM:DRP1B[6]
    37----------------------------MMCM:DRP1B[5]MMCM:DRP1B[4]
    38----------------------------MMCM:DRP1B[3]MMCM:DRP1B[2]
    39----------------------------MMCM:DRP1B[1]MMCM:DRP1B[0]
    MMCM:FREQ_COMP[1]
    40----------------------------MMCM:DRP1A[15]
    MMCM:FREQ_COMP[0]    		MMCM:DRP1A[14]
    MMCM:LOCK_REF_DLY[4]
    41----------------------------MMCM:DRP1A[13]
    MMCM:LOCK_REF_DLY[3]    		MMCM:DRP1A[12]
    MMCM:LOCK_REF_DLY[2]
    42----------------------------MMCM:DRP1A[11]
    MMCM:LOCK_REF_DLY[1]    		MMCM:DRP1A[10]
    MMCM:LOCK_REF_DLY[0]
    43----------------------------MMCM:DRP1A[9]
    MMCM:LOCK_SAT_HIGH[9]    		MMCM:DRP1A[8]
    MMCM:LOCK_SAT_HIGH[8]
    44----------------------------MMCM:DRP1A[7]
    MMCM:LOCK_SAT_HIGH[7]    		MMCM:DRP1A[6]
    MMCM:LOCK_SAT_HIGH[6]
    45----------------------------MMCM:DRP1A[5]
    MMCM:LOCK_SAT_HIGH[5]    		MMCM:DRP1A[4]
    MMCM:LOCK_SAT_HIGH[4]
    46----------------------------MMCM:DRP1A[3]
    MMCM:LOCK_SAT_HIGH[3]    		MMCM:DRP1A[2]
    MMCM:LOCK_SAT_HIGH[2]
    47----------------------------MMCM:DRP1A[1]
    MMCM:LOCK_SAT_HIGH[1]    		MMCM:DRP1A[0]
    MMCM:LOCK_SAT_HIGH[0]
    48----------------------------MMCM:DRP19[15]MMCM:DRP19[14]
    MMCM:LOCK_FB_DLY[4]
    49----------------------------MMCM:DRP19[13]
    MMCM:LOCK_FB_DLY[3]    		MMCM:DRP19[12]
    MMCM:LOCK_FB_DLY[2]
    50----------------------------MMCM:DRP19[11]
    MMCM:LOCK_FB_DLY[1]    		MMCM:DRP19[10]
    MMCM:LOCK_FB_DLY[0]
    51----------------------------MMCM:DRP19[9]
    MMCM:UNLOCK_CNT[9]    		MMCM:DRP19[8]
    MMCM:UNLOCK_CNT[8]
    52----------------------------MMCM:DRP19[7]
    MMCM:UNLOCK_CNT[7]    		MMCM:DRP19[6]
    MMCM:UNLOCK_CNT[6]
    53----------------------------MMCM:DRP19[5]
    MMCM:UNLOCK_CNT[5]    		MMCM:DRP19[4]
    MMCM:UNLOCK_CNT[4]
    54----------------------------MMCM:DRP19[3]
    MMCM:UNLOCK_CNT[3]    		MMCM:DRP19[2]
    MMCM:UNLOCK_CNT[2]
    55----------------------------MMCM:DRP19[1]
    MMCM:UNLOCK_CNT[1]    		MMCM:DRP19[0]
    MMCM:UNLOCK_CNT[0]
    56----------------------------MMCM:DRP18[15]MMCM:DRP18[14]
    57----------------------------MMCM:DRP18[13]MMCM:DRP18[12]
    58----------------------------MMCM:DRP18[11]MMCM:DRP18[10]
    59----------------------------MMCM:DRP18[9]
    MMCM:LOCK_CNT[9]    		MMCM:DRP18[8]
    MMCM:LOCK_CNT[8]
    60----------------------------MMCM:DRP18[7]
    MMCM:LOCK_CNT[7]    		MMCM:DRP18[6]
    MMCM:LOCK_CNT[6]
    61----------------------------MMCM:DRP18[5]
    MMCM:LOCK_CNT[5]    		MMCM:DRP18[4]
    MMCM:LOCK_CNT[4]
    62----------------------------MMCM:DRP18[3]
    MMCM:LOCK_CNT[3]    		MMCM:DRP18[2]
    MMCM:LOCK_CNT[2]
    63----------------------------MMCM:DRP18[1]
    MMCM:LOCK_CNT[1]    		MMCM:DRP18[0]
    MMCM:LOCK_CNT[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 13
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP17[15]MMCM:DRP17[14]
    1----------------------------MMCM:CLKFBIN_EDGE
    MMCM:DRP17[13]    		MMCM:CLKFBIN_NOCOUNT
    MMCM:DRP17[12]
    2----------------------------MMCM:CLKFBIN_HT[5]
    MMCM:DRP17[11]    		MMCM:CLKFBIN_HT[4]
    MMCM:DRP17[10]
    3----------------------------MMCM:CLKFBIN_HT[3]
    MMCM:DRP17[9]    		MMCM:CLKFBIN_HT[2]
    MMCM:DRP17[8]
    4----------------------------MMCM:CLKFBIN_HT[1]
    MMCM:DRP17[7]    		MMCM:CLKFBIN_HT[0]
    MMCM:DRP17[6]
    5----------------------------MMCM:CLKFBIN_LT[5]
    MMCM:DRP17[5]    		MMCM:CLKFBIN_LT[4]
    MMCM:DRP17[4]
    6----------------------------MMCM:CLKFBIN_LT[3]
    MMCM:DRP17[3]    		MMCM:CLKFBIN_LT[2]
    MMCM:DRP17[2]
    7----------------------------MMCM:CLKFBIN_LT[1]
    MMCM:DRP17[1]    		MMCM:CLKFBIN_LT[0]
    MMCM:DRP17[0]
    8----------------------------MMCM:DRP16[15]MMCM:DRP16[14]
    9----------------------------MMCM:DIVCLK_EDGE
    MMCM:DRP16[13]    		MMCM:DIVCLK_NOCOUNT
    MMCM:DRP16[12]
    10----------------------------MMCM:DIVCLK_HT[5]
    MMCM:DRP16[11]    		MMCM:DIVCLK_HT[4]
    MMCM:DRP16[10]
    11----------------------------MMCM:DIVCLK_HT[3]
    MMCM:DRP16[9]    		MMCM:DIVCLK_HT[2]
    MMCM:DRP16[8]
    12----------------------------MMCM:DIVCLK_HT[1]
    MMCM:DRP16[7]    		MMCM:DIVCLK_HT[0]
    MMCM:DRP16[6]
    13----------------------------MMCM:DIVCLK_LT[5]
    MMCM:DRP16[5]    		MMCM:DIVCLK_LT[4]
    MMCM:DRP16[4]
    14----------------------------MMCM:DIVCLK_LT[3]
    MMCM:DRP16[3]    		MMCM:DIVCLK_LT[2]
    MMCM:DRP16[2]
    15----------------------------MMCM:DIVCLK_LT[1]
    MMCM:DRP16[1]    		MMCM:DIVCLK_LT[0]
    MMCM:DRP16[0]
    16----------------------------MMCM:DRP15[15]MMCM:CLKFBOUT_FRAC[2]
    MMCM:DRP15[14]
    17----------------------------MMCM:CLKFBOUT_FRAC[1]
    MMCM:DRP15[13]    		MMCM:CLKFBOUT_FRAC[0]
    MMCM:DRP15[12]
    18----------------------------MMCM:CLKFBOUT_FRAC_EN
    MMCM:DRP15[11]    		MMCM:CLKFBOUT_FRAC_WF_RISE
    MMCM:DRP15[10]
    19----------------------------MMCM:CLKFBOUT_MX[1]
    MMCM:DRP15[9]    		MMCM:CLKFBOUT_MX[0]
    MMCM:CLKFBOUT_USE_FINE_PS
    MMCM:DRP15[8]
    20----------------------------MMCM:CLKFBOUT_EDGE
    MMCM:DRP15[7]    		MMCM:CLKFBOUT_NOCOUNT
    MMCM:DRP15[6]
    21----------------------------MMCM:CLKFBOUT_DT[5]
    MMCM:DRP15[5]    		MMCM:CLKFBOUT_DT[4]
    MMCM:DRP15[4]
    22----------------------------MMCM:CLKFBOUT_DT[3]
    MMCM:DRP15[3]    		MMCM:CLKFBOUT_DT[2]
    MMCM:DRP15[2]
    23----------------------------MMCM:CLKFBOUT_DT[1]
    MMCM:DRP15[1]    		MMCM:CLKFBOUT_DT[0]
    MMCM:DRP15[0]
    24----------------------------MMCM:CLKFBOUT_PM_RISE[2]
    MMCM:DRP14[15]    		MMCM:CLKFBOUT_PM_RISE[1]
    MMCM:DRP14[14]
    25----------------------------MMCM:CLKFBOUT_PM_RISE[0]
    MMCM:DRP14[13]    		MMCM:CLKFBOUT_EN
    MMCM:DRP14[12]
    26----------------------------MMCM:CLKFBOUT_HT[5]
    MMCM:DRP14[11]    		MMCM:CLKFBOUT_HT[4]
    MMCM:DRP14[10]
    27----------------------------MMCM:CLKFBOUT_HT[3]
    MMCM:DRP14[9]    		MMCM:CLKFBOUT_HT[2]
    MMCM:DRP14[8]
    28----------------------------MMCM:CLKFBOUT_HT[1]
    MMCM:DRP14[7]    		MMCM:CLKFBOUT_HT[0]
    MMCM:DRP14[6]
    29----------------------------MMCM:CLKFBOUT_LT[5]
    MMCM:DRP14[5]    		MMCM:CLKFBOUT_LT[4]
    MMCM:DRP14[4]
    30----------------------------MMCM:CLKFBOUT_LT[3]
    MMCM:DRP14[3]    		MMCM:CLKFBOUT_LT[2]
    MMCM:DRP14[2]
    31----------------------------MMCM:CLKFBOUT_LT[1]
    MMCM:DRP14[1]    		MMCM:CLKFBOUT_LT[0]
    MMCM:DRP14[0]
    32----------------------------MMCM:DRP13[15]MMCM:DRP13[14]
    33----------------------------MMCM:CLKFBOUT_PM_FALL[2]
    MMCM:DRP13[13]    		MMCM:CLKFBOUT_PM_FALL[1]
    MMCM:DRP13[12]
    34----------------------------MMCM:CLKFBOUT_PM_FALL[0]
    MMCM:DRP13[11]    		MMCM:CLKFBOUT_FRAC_WF_FALL
    MMCM:DRP13[10]
    35----------------------------MMCM:CLKOUT6_MX[1]
    MMCM:DRP13[9]    		MMCM:CLKOUT6_MX[0]
    MMCM:CLKOUT6_USE_FINE_PS
    MMCM:DRP13[8]
    36----------------------------MMCM:CLKOUT6_EDGE
    MMCM:DRP13[7]    		MMCM:CLKOUT6_NOCOUNT
    MMCM:DRP13[6]
    37----------------------------MMCM:CLKOUT6_DT[5]
    MMCM:DRP13[5]    		MMCM:CLKOUT6_DT[4]
    MMCM:DRP13[4]
    38----------------------------MMCM:CLKOUT6_DT[3]
    MMCM:DRP13[3]    		MMCM:CLKOUT6_DT[2]
    MMCM:DRP13[2]
    39----------------------------MMCM:CLKOUT6_DT[1]
    MMCM:DRP13[1]    		MMCM:CLKOUT6_DT[0]
    MMCM:DRP13[0]
    40----------------------------MMCM:CLKOUT6_PM[2]
    MMCM:DRP12[15]    		MMCM:CLKOUT6_PM[1]
    MMCM:DRP12[14]
    41----------------------------MMCM:CLKOUT6_PM[0]
    MMCM:DRP12[13]    		MMCM:CLKOUT6_EN
    MMCM:DRP12[12]
    42----------------------------MMCM:CLKOUT6_HT[5]
    MMCM:DRP12[11]    		MMCM:CLKOUT6_HT[4]
    MMCM:DRP12[10]
    43----------------------------MMCM:CLKOUT6_HT[3]
    MMCM:DRP12[9]    		MMCM:CLKOUT6_HT[2]
    MMCM:DRP12[8]
    44----------------------------MMCM:CLKOUT6_HT[1]
    MMCM:DRP12[7]    		MMCM:CLKOUT6_HT[0]
    MMCM:DRP12[6]
    45----------------------------MMCM:CLKOUT6_LT[5]
    MMCM:DRP12[5]    		MMCM:CLKOUT6_LT[4]
    MMCM:DRP12[4]
    46----------------------------MMCM:CLKOUT6_LT[3]
    MMCM:DRP12[3]    		MMCM:CLKOUT6_LT[2]
    MMCM:DRP12[2]
    47----------------------------MMCM:CLKOUT6_LT[1]
    MMCM:DRP12[1]    		MMCM:CLKOUT6_LT[0]
    MMCM:DRP12[0]
    48----------------------------MMCM:DRP11[15]MMCM:DRP11[14]
    49----------------------------MMCM:DRP11[13]MMCM:DRP11[12]
    50----------------------------MMCM:DRP11[11]MMCM:DRP11[10]
    51----------------------------MMCM:CLKOUT4_CASCADE
    MMCM:CLKOUT4_MX[1]
    MMCM:DRP11[9]    		MMCM:CLKOUT4_MX[0]
    MMCM:CLKOUT4_USE_FINE_PS
    MMCM:DRP11[8]
    52----------------------------MMCM:CLKOUT4_EDGE
    MMCM:DRP11[7]    		MMCM:CLKOUT4_NOCOUNT
    MMCM:DRP11[6]
    53----------------------------MMCM:CLKOUT4_DT[5]
    MMCM:DRP11[5]    		MMCM:CLKOUT4_DT[4]
    MMCM:DRP11[4]
    54----------------------------MMCM:CLKOUT4_DT[3]
    MMCM:DRP11[3]    		MMCM:CLKOUT4_DT[2]
    MMCM:DRP11[2]
    55----------------------------MMCM:CLKOUT4_DT[1]
    MMCM:DRP11[1]    		MMCM:CLKOUT4_DT[0]
    MMCM:DRP11[0]
    56----------------------------MMCM:CLKOUT4_PM[2]
    MMCM:DRP10[15]    		MMCM:CLKOUT4_PM[1]
    MMCM:DRP10[14]
    57----------------------------MMCM:CLKOUT4_PM[0]
    MMCM:DRP10[13]    		MMCM:CLKOUT4_EN
    MMCM:DRP10[12]
    58----------------------------MMCM:CLKOUT4_HT[5]
    MMCM:DRP10[11]    		MMCM:CLKOUT4_HT[4]
    MMCM:DRP10[10]
    59----------------------------MMCM:CLKOUT4_HT[3]
    MMCM:DRP10[9]    		MMCM:CLKOUT4_HT[2]
    MMCM:DRP10[8]
    60----------------------------MMCM:CLKOUT4_HT[1]
    MMCM:DRP10[7]    		MMCM:CLKOUT4_HT[0]
    MMCM:DRP10[6]
    61----------------------------MMCM:CLKOUT4_LT[5]
    MMCM:DRP10[5]    		MMCM:CLKOUT4_LT[4]
    MMCM:DRP10[4]
    62----------------------------MMCM:CLKOUT4_LT[3]
    MMCM:DRP10[3]    		MMCM:CLKOUT4_LT[2]
    MMCM:DRP10[2]
    63----------------------------MMCM:CLKOUT4_LT[1]
    MMCM:DRP10[1]    		MMCM:CLKOUT4_LT[0]
    MMCM:DRP10[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 14
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP0F[15]MMCM:DRP0F[14]
    1----------------------------MMCM:DRP0F[13]MMCM:DRP0F[12]
    2----------------------------MMCM:DRP0F[11]MMCM:DRP0F[10]
    3----------------------------MMCM:CLKOUT3_MX[1]
    MMCM:DRP0F[9]    		MMCM:CLKOUT3_MX[0]
    MMCM:CLKOUT3_USE_FINE_PS
    MMCM:DRP0F[8]
    4----------------------------MMCM:CLKOUT3_EDGE
    MMCM:DRP0F[7]    		MMCM:CLKOUT3_NOCOUNT
    MMCM:DRP0F[6]
    5----------------------------MMCM:CLKOUT3_DT[5]
    MMCM:DRP0F[5]    		MMCM:CLKOUT3_DT[4]
    MMCM:DRP0F[4]
    6----------------------------MMCM:CLKOUT3_DT[3]
    MMCM:DRP0F[3]    		MMCM:CLKOUT3_DT[2]
    MMCM:DRP0F[2]
    7----------------------------MMCM:CLKOUT3_DT[1]
    MMCM:DRP0F[1]    		MMCM:CLKOUT3_DT[0]
    MMCM:DRP0F[0]
    8----------------------------MMCM:CLKOUT3_PM[2]
    MMCM:DRP0E[15]    		MMCM:CLKOUT3_PM[1]
    MMCM:DRP0E[14]
    9----------------------------MMCM:CLKOUT3_PM[0]
    MMCM:DRP0E[13]    		MMCM:CLKOUT3_EN
    MMCM:DRP0E[12]
    10----------------------------MMCM:CLKOUT3_HT[5]
    MMCM:DRP0E[11]    		MMCM:CLKOUT3_HT[4]
    MMCM:DRP0E[10]
    11----------------------------MMCM:CLKOUT3_HT[3]
    MMCM:DRP0E[9]    		MMCM:CLKOUT3_HT[2]
    MMCM:DRP0E[8]
    12----------------------------MMCM:CLKOUT3_HT[1]
    MMCM:DRP0E[7]    		MMCM:CLKOUT3_HT[0]
    MMCM:DRP0E[6]
    13----------------------------MMCM:CLKOUT3_LT[5]
    MMCM:DRP0E[5]    		MMCM:CLKOUT3_LT[4]
    MMCM:DRP0E[4]
    14----------------------------MMCM:CLKOUT3_LT[3]
    MMCM:DRP0E[3]    		MMCM:CLKOUT3_LT[2]
    MMCM:DRP0E[2]
    15----------------------------MMCM:CLKOUT3_LT[1]
    MMCM:DRP0E[1]    		MMCM:CLKOUT3_LT[0]
    MMCM:DRP0E[0]
    16----------------------------MMCM:DRP0D[15]MMCM:DRP0D[14]
    17----------------------------MMCM:DRP0D[13]MMCM:DRP0D[12]
    18----------------------------MMCM:DRP0D[11]MMCM:DRP0D[10]
    19----------------------------MMCM:CLKOUT2_MX[1]
    MMCM:DRP0D[9]    		MMCM:CLKOUT2_MX[0]
    MMCM:CLKOUT2_USE_FINE_PS
    MMCM:DRP0D[8]
    20----------------------------MMCM:CLKOUT2_EDGE
    MMCM:DRP0D[7]    		MMCM:CLKOUT2_NOCOUNT
    MMCM:DRP0D[6]
    21----------------------------MMCM:CLKOUT2_DT[5]
    MMCM:DRP0D[5]    		MMCM:CLKOUT2_DT[4]
    MMCM:DRP0D[4]
    22----------------------------MMCM:CLKOUT2_DT[3]
    MMCM:DRP0D[3]    		MMCM:CLKOUT2_DT[2]
    MMCM:DRP0D[2]
    23----------------------------MMCM:CLKOUT2_DT[1]
    MMCM:DRP0D[1]    		MMCM:CLKOUT2_DT[0]
    MMCM:DRP0D[0]
    24----------------------------MMCM:CLKOUT2_PM[2]
    MMCM:DRP0C[15]    		MMCM:CLKOUT2_PM[1]
    MMCM:DRP0C[14]
    25----------------------------MMCM:CLKOUT2_PM[0]
    MMCM:DRP0C[13]    		MMCM:CLKOUT2_EN
    MMCM:DRP0C[12]
    26----------------------------MMCM:CLKOUT2_HT[5]
    MMCM:DRP0C[11]    		MMCM:CLKOUT2_HT[4]
    MMCM:DRP0C[10]
    27----------------------------MMCM:CLKOUT2_HT[3]
    MMCM:DRP0C[9]    		MMCM:CLKOUT2_HT[2]
    MMCM:DRP0C[8]
    28----------------------------MMCM:CLKOUT2_HT[1]
    MMCM:DRP0C[7]    		MMCM:CLKOUT2_HT[0]
    MMCM:DRP0C[6]
    29----------------------------MMCM:CLKOUT2_LT[5]
    MMCM:DRP0C[5]    		MMCM:CLKOUT2_LT[4]
    MMCM:DRP0C[4]
    30----------------------------MMCM:CLKOUT2_LT[3]
    MMCM:DRP0C[3]    		MMCM:CLKOUT2_LT[2]
    MMCM:DRP0C[2]
    31----------------------------MMCM:CLKOUT2_LT[1]
    MMCM:DRP0C[1]    		MMCM:CLKOUT2_LT[0]
    MMCM:DRP0C[0]
    32----------------------------MMCM:DRP0B[15]MMCM:DRP0B[14]
    33----------------------------MMCM:DRP0B[13]MMCM:DRP0B[12]
    34----------------------------MMCM:DRP0B[11]MMCM:DRP0B[10]
    35----------------------------MMCM:CLKOUT1_MX[1]
    MMCM:DRP0B[9]    		MMCM:CLKOUT1_MX[0]
    MMCM:CLKOUT1_USE_FINE_PS
    MMCM:DRP0B[8]
    36----------------------------MMCM:CLKOUT1_EDGE
    MMCM:DRP0B[7]    		MMCM:CLKOUT1_NOCOUNT
    MMCM:DRP0B[6]
    37----------------------------MMCM:CLKOUT1_DT[5]
    MMCM:DRP0B[5]    		MMCM:CLKOUT1_DT[4]
    MMCM:DRP0B[4]
    38----------------------------MMCM:CLKOUT1_DT[3]
    MMCM:DRP0B[3]    		MMCM:CLKOUT1_DT[2]
    MMCM:DRP0B[2]
    39----------------------------MMCM:CLKOUT1_DT[1]
    MMCM:DRP0B[1]    		MMCM:CLKOUT1_DT[0]
    MMCM:DRP0B[0]
    40----------------------------MMCM:CLKOUT1_PM[2]
    MMCM:DRP0A[15]    		MMCM:CLKOUT1_PM[1]
    MMCM:DRP0A[14]
    41----------------------------MMCM:CLKOUT1_PM[0]
    MMCM:DRP0A[13]    		MMCM:CLKOUT1_EN
    MMCM:DRP0A[12]
    42----------------------------MMCM:CLKOUT1_HT[5]
    MMCM:DRP0A[11]    		MMCM:CLKOUT1_HT[4]
    MMCM:DRP0A[10]
    43----------------------------MMCM:CLKOUT1_HT[3]
    MMCM:DRP0A[9]    		MMCM:CLKOUT1_HT[2]
    MMCM:DRP0A[8]
    44----------------------------MMCM:CLKOUT1_HT[1]
    MMCM:DRP0A[7]    		MMCM:CLKOUT1_HT[0]
    MMCM:DRP0A[6]
    45----------------------------MMCM:CLKOUT1_LT[5]
    MMCM:DRP0A[5]    		MMCM:CLKOUT1_LT[4]
    MMCM:DRP0A[4]
    46----------------------------MMCM:CLKOUT1_LT[3]
    MMCM:DRP0A[3]    		MMCM:CLKOUT1_LT[2]
    MMCM:DRP0A[2]
    47----------------------------MMCM:CLKOUT1_LT[1]
    MMCM:DRP0A[1]    		MMCM:CLKOUT1_LT[0]
    MMCM:DRP0A[0]
    48----------------------------MMCM:DRP09[15]MMCM:CLKOUT0_FRAC[2]
    MMCM:DRP09[14]
    49----------------------------MMCM:CLKOUT0_FRAC[1]
    MMCM:DRP09[13]    		MMCM:CLKOUT0_FRAC[0]
    MMCM:DRP09[12]
    50----------------------------MMCM:CLKOUT0_FRAC_EN
    MMCM:DRP09[11]    		MMCM:CLKOUT0_FRAC_WF_RISE
    MMCM:DRP09[10]
    51----------------------------MMCM:CLKOUT0_MX[1]
    MMCM:DRP09[9]    		MMCM:CLKOUT0_MX[0]
    MMCM:CLKOUT0_USE_FINE_PS
    MMCM:DRP09[8]
    52----------------------------MMCM:CLKOUT0_EDGE
    MMCM:DRP09[7]    		MMCM:CLKOUT0_NOCOUNT
    MMCM:DRP09[6]
    53----------------------------MMCM:CLKOUT0_DT[5]
    MMCM:DRP09[5]    		MMCM:CLKOUT0_DT[4]
    MMCM:DRP09[4]
    54----------------------------MMCM:CLKOUT0_DT[3]
    MMCM:DRP09[3]    		MMCM:CLKOUT0_DT[2]
    MMCM:DRP09[2]
    55----------------------------MMCM:CLKOUT0_DT[1]
    MMCM:DRP09[1]    		MMCM:CLKOUT0_DT[0]
    MMCM:DRP09[0]
    56----------------------------MMCM:CLKOUT0_PM_RISE[2]
    MMCM:DRP08[15]    		MMCM:CLKOUT0_PM_RISE[1]
    MMCM:DRP08[14]
    57----------------------------MMCM:CLKOUT0_PM_RISE[0]
    MMCM:DRP08[13]    		MMCM:CLKOUT0_EN
    MMCM:DRP08[12]
    58----------------------------MMCM:CLKOUT0_HT[5]
    MMCM:DRP08[11]    		MMCM:CLKOUT0_HT[4]
    MMCM:DRP08[10]
    59----------------------------MMCM:CLKOUT0_HT[3]
    MMCM:DRP08[9]    		MMCM:CLKOUT0_HT[2]
    MMCM:DRP08[8]
    60----------------------------MMCM:CLKOUT0_HT[1]
    MMCM:DRP08[7]    		MMCM:CLKOUT0_HT[0]
    MMCM:DRP08[6]
    61----------------------------MMCM:CLKOUT0_LT[5]
    MMCM:DRP08[5]    		MMCM:CLKOUT0_LT[4]
    MMCM:DRP08[4]
    62----------------------------MMCM:CLKOUT0_LT[3]
    MMCM:DRP08[3]    		MMCM:CLKOUT0_LT[2]
    MMCM:DRP08[2]
    63----------------------------MMCM:CLKOUT0_LT[1]
    MMCM:DRP08[1]    		MMCM:CLKOUT0_LT[0]
    MMCM:DRP08[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 15
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------MMCM:DRP07[15]MMCM:DRP07[14]
    1----------------------------MMCM:CLKOUT0_PM_FALL[2]
    MMCM:DRP07[13]    		MMCM:CLKOUT0_PM_FALL[1]
    MMCM:DRP07[12]
    2----------------------------MMCM:CLKOUT0_PM_FALL[0]
    MMCM:DRP07[11]    		MMCM:CLKOUT0_FRAC_WF_FALL
    MMCM:DRP07[10]
    3----------------------------MMCM:CLKOUT5_MX[1]
    MMCM:DRP07[9]    		MMCM:CLKOUT5_MX[0]
    MMCM:CLKOUT5_USE_FINE_PS
    MMCM:DRP07[8]
    4----------------------------MMCM:CLKOUT5_EDGE
    MMCM:DRP07[7]    		MMCM:CLKOUT5_NOCOUNT
    MMCM:DRP07[6]
    5----------------------------MMCM:CLKOUT5_DT[5]
    MMCM:DRP07[5]    		MMCM:CLKOUT5_DT[4]
    MMCM:DRP07[4]
    6----------------------------MMCM:CLKOUT5_DT[3]
    MMCM:DRP07[3]    		MMCM:CLKOUT5_DT[2]
    MMCM:DRP07[2]
    7----------------------------MMCM:CLKOUT5_DT[1]
    MMCM:DRP07[1]    		MMCM:CLKOUT5_DT[0]
    MMCM:DRP07[0]
    8----------------------------MMCM:CLKOUT5_PM[2]
    MMCM:DRP06[15]    		MMCM:CLKOUT5_PM[1]
    MMCM:DRP06[14]
    9----------------------------MMCM:CLKOUT5_PM[0]
    MMCM:DRP06[13]    		MMCM:CLKOUT5_EN
    MMCM:DRP06[12]
    10----------------------------MMCM:CLKOUT5_HT[5]
    MMCM:DRP06[11]    		MMCM:CLKOUT5_HT[4]
    MMCM:DRP06[10]
    11----------------------------MMCM:CLKOUT5_HT[3]
    MMCM:DRP06[9]    		MMCM:CLKOUT5_HT[2]
    MMCM:DRP06[8]
    12----------------------------MMCM:CLKOUT5_HT[1]
    MMCM:DRP06[7]    		MMCM:CLKOUT5_HT[0]
    MMCM:DRP06[6]
    13----------------------------MMCM:CLKOUT5_LT[5]
    MMCM:DRP06[5]    		MMCM:CLKOUT5_LT[4]
    MMCM:DRP06[4]
    14----------------------------MMCM:CLKOUT5_LT[3]
    MMCM:DRP06[3]    		MMCM:CLKOUT5_LT[2]
    MMCM:DRP06[2]
    15----------------------------MMCM:CLKOUT5_LT[1]
    MMCM:DRP06[1]    		MMCM:CLKOUT5_LT[0]
    MMCM:DRP06[0]
    16----------------------------MMCM:DRP05[15]
    MMCM:IN_DLY_SET[5]    		MMCM:DRP05[14]
    MMCM:IN_DLY_SET[4]
    17----------------------------MMCM:DRP05[13]
    MMCM:IN_DLY_SET[3]    		MMCM:DRP05[12]
    MMCM:IN_DLY_SET[2]
    18----------------------------MMCM:DRP05[11]
    MMCM:IN_DLY_SET[1]    		MMCM:DRP05[10]
    MMCM:IN_DLY_SET[0]
    19----------------------------MMCM:DRP05[9]
    MMCM:IN_DLY_MX_DVDD[5]    		MMCM:DRP05[8]
    MMCM:IN_DLY_MX_DVDD[4]
    20----------------------------MMCM:DRP05[7]
    MMCM:IN_DLY_MX_DVDD[3]    		MMCM:DRP05[6]
    MMCM:IN_DLY_MX_DVDD[2]
    21----------------------------MMCM:DRP05[5]
    MMCM:IN_DLY_MX_DVDD[1]    		MMCM:DRP05[4]
    MMCM:IN_DLY_MX_DVDD[0]
    22----------------------------MMCM:DIRECT_PATH_CNTRL
    MMCM:DRP05[3]    		MMCM:DRP05[2]
    MMCM:IN_DLY_EN
    23----------------------------MMCM:DRP05[1]MMCM:DRP05[0]
    24----------------------------MMCM:DRP04[15]
    MMCM:TMUX_MUX_SEL[1]    		MMCM:DRP04[14]
    MMCM:TMUX_MUX_SEL[0]
    25----------------------------MMCM:CLKBURST_REPEAT
    MMCM:DRP04[13]    		MMCM:CLKBURST_ENABLE
    MMCM:DRP04[12]
    26----------------------------MMCM:CLKBURST_CNT[3]
    MMCM:DRP04[11]    		MMCM:CLKBURST_CNT[2]
    MMCM:DRP04[10]
    27----------------------------MMCM:CLKBURST_CNT[1]
    MMCM:DRP04[9]    		MMCM:CLKBURST_CNT[0]
    MMCM:DRP04[8]
    28----------------------------MMCM:DRP04[7]MMCM:DRP04[6]
    29----------------------------MMCM:DRP04[5]
    MMCM:SS_STEPS_INIT[2]    		MMCM:DRP04[4]
    MMCM:SS_STEPS_INIT[1]
    30----------------------------MMCM:DRP04[3]
    MMCM:SS_STEPS_INIT[0]    		MMCM:DRP04[2]
    MMCM:SS_STEPS[2]
    31----------------------------MMCM:DRP04[1]
    MMCM:SS_STEPS[1]    		MMCM:DRP04[0]
    MMCM:SS_STEPS[0]
    32----------------------------MMCM:DRP03[15]
    MMCM:MUX.PERF3[0]    		MMCM:DRP03[14]
    MMCM:MUX.PERF3[1]
    33----------------------------MMCM:DRP03[13]
    MMCM:MUX.PERF3[2]    		MMCM:DRP03[12]
    MMCM:MUX.PERF2[0]
    34----------------------------MMCM:DRP03[11]
    MMCM:MUX.PERF2[1]    		MMCM:DRP03[10]
    MMCM:MUX.PERF2[2]
    35----------------------------MMCM:DRP03[9]
    MMCM:MUX.PERF1[0]    		MMCM:DRP03[8]
    MMCM:MUX.PERF1[1]
    36----------------------------MMCM:DRP03[7]
    MMCM:MUX.PERF1[2]    		MMCM:DRP03[6]
    MMCM:MUX.PERF0[0]
    37----------------------------MMCM:DRP03[5]
    MMCM:MUX.PERF0[1]    		MMCM:DRP03[4]
    MMCM:MUX.PERF0[2]
    38----------------------------MMCM:DRP03[3]
    MMCM:SKEW_FLOP_INV[3]    		MMCM:DRP03[2]
    MMCM:SKEW_FLOP_INV[2]
    39----------------------------MMCM:DRP03[1]
    MMCM:SKEW_FLOP_INV[1]    		MMCM:DRP03[0]
    MMCM:SKEW_FLOP_INV[0]
    40----------------------------MMCM:DRP02[15]MMCM:DRP02[14]
    41----------------------------MMCM:DRP02[13]MMCM:DRP02[12]
    42----------------------------MMCM:DRP02[11]MMCM:DRP02[10]
    43----------------------------MMCM:DRP02[9]MMCM:DRP02[8]
    44----------------------------MMCM:DRP02[7]MMCM:DRP02[6]
    45----------------------------MMCM:DRP02[5]MMCM:DRP02[4]
    46----------------------------MMCM:DRP02[3]MMCM:DRP02[2]
    47----------------------------MMCM:DRP02[1]
    MMCM:SYNTH_CLK_DIV[1]    		MMCM:DRP02[0]
    MMCM:SYNTH_CLK_DIV[0]
    48----------------------------MMCM:DRP01[15]MMCM:DRP01[14]
    49----------------------------MMCM:DRP01[13]MMCM:DRP01[12]
    50----------------------------MMCM:BUF.CLKOUT3_FREQ_BB
    MMCM:DRP01[11]    		MMCM:BUF.CLKOUT2_FREQ_BB
    MMCM:DRP01[10]
    51----------------------------MMCM:BUF.CLKOUT1_FREQ_BB
    MMCM:DRP01[9]    		MMCM:BUF.CLKOUT0_FREQ_BB
    MMCM:DRP01[8]
    52----------------------------MMCM:DRP01[7]
    MMCM:MUX.CLKFBIN[0]    		MMCM:DRP01[6]
    MMCM:MUX.CLKFBIN[1]
    53----------------------------MMCM:DRP01[5]
    MMCM:MUX.CLKFBIN[2]    		MMCM:DRP01[4]
    MMCM:MUX.CLKIN1[0]
    54----------------------------MMCM:DRP01[3]
    MMCM:MUX.CLKIN1[1]    		MMCM:DRP01[2]
    MMCM:MUX.CLKIN1[2]
    55----------------------------MMCM:DRP01[1]
    MMCM:MUX.CLKIN2[0]    		MMCM:DRP01[0]
    MMCM:MUX.CLKIN2[1]
    56----------------------------MMCM:DRP00[15]
    MMCM:MUX.CLKIN2[2]    		MMCM:DRP00[14]
    MMCM:HROW_DLY_SET[2]
    57----------------------------MMCM:DRP00[13]
    MMCM:HROW_DLY_SET[1]    		MMCM:DRP00[12]
    MMCM:HROW_DLY_SET[0]
    58----------------------------MMCM:DRP00[11]
    MMCM:IN_DLY_MX_CVDD[5]    		MMCM:DRP00[10]
    MMCM:IN_DLY_MX_CVDD[4]
    59----------------------------MMCM:DRP00[9]
    MMCM:IN_DLY_MX_CVDD[3]    		MMCM:DRP00[8]
    MMCM:IN_DLY_MX_CVDD[2]
    60----------------------------MMCM:DRP00[7]
    MMCM:IN_DLY_MX_CVDD[1]    		MMCM:DRP00[6]
    MMCM:IN_DLY_MX_CVDD[0]
    61----------------------------MMCM:DRP00[5]MMCM:DRP00[4]
    62----------------------------MMCM:DRP00[3]
    MMCM:MUX.PERF3[3]    		MMCM:DRP00[2]
    MMCM:MUX.PERF2[3]
    63----------------------------MMCM:DRP00[1]
    MMCM:MUX.PERF1[3]    		MMCM:DRP00[0]
    MMCM:MUX.PERF0[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 16
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------CMT_BOT:ENABLE.SYNC_BB_SCMT_BOT:ENABLE.FREQ_BB0[2]
    33----------------------------CMT_BOT:ENABLE.FREQ_BB1[0]CMT_BOT:ENABLE.FREQ_BB2[2]
    34----------------------------CMT_BOT:ENABLE.FREQ_BB3[0]CMT_BOT:MUX.FREQ_BB0[0]
    35----------------------------CMT_BOT:MUX.FREQ_BB1[0]CMT_BOT:MUX.FREQ_BB2[0]
    36----------------------------CMT_BOT:MUX.FREQ_BB3[0]-
    37------------------------------
    38----------------------------CMT_BOT:BUF.SYNC_BB.DCMT_BOT:ENABLE.SYNC_BB
    39----------------------------CMT_BOT:BUF.SYNC_BB.U-
    40------------------------------
    41-----------------------------CMT_BOT:ENABLE.FREQ_BB0_S[0]
    42----------------------------CMT_BOT:ENABLE.FREQ_BB0[0]CMT_BOT:ENABLE.FREQ_BB1_S[0]
    43----------------------------CMT_BOT:ENABLE.FREQ_BB1[1]CMT_BOT:ENABLE.FREQ_BB2_S[0]
    44----------------------------CMT_BOT:ENABLE.FREQ_BB2[0]CMT_BOT:ENABLE.FREQ_BB3_S[0]
    45----------------------------CMT_BOT:ENABLE.FREQ_BB3[1]CMT_BOT:BUF.FREQ_BB0.D[1]
    46----------------------------CMT_BOT:BUF.FREQ_BB0.U[0]CMT_BOT:BUF.FREQ_BB1.D[1]
    47----------------------------CMT_BOT:BUF.FREQ_BB1.U[0]CMT_BOT:BUF.FREQ_BB2.D[1]
    48----------------------------CMT_BOT:BUF.FREQ_BB2.U[0]CMT_BOT:BUF.FREQ_BB3.D[1]
    49----------------------------CMT_BOT:BUF.FREQ_BB3.U[0]CMT_BOT:ENABLE.FREQ_BB0_S[1]
    50----------------------------CMT_BOT:ENABLE.FREQ_BB0[1]CMT_BOT:ENABLE.FREQ_BB1_S[1]
    51----------------------------CMT_BOT:ENABLE.FREQ_BB1[2]CMT_BOT:ENABLE.FREQ_BB2_S[1]
    52----------------------------CMT_BOT:ENABLE.FREQ_BB2[1]CMT_BOT:ENABLE.FREQ_BB3_S[1]
    53----------------------------CMT_BOT:ENABLE.FREQ_BB3[2]CMT_BOT:BUF.FREQ_BB0.U[1]
    54----------------------------CMT_BOT:BUF.FREQ_BB0.D[0]CMT_BOT:BUF.FREQ_BB1.U[1]
    55----------------------------CMT_BOT:BUF.FREQ_BB1.D[0]CMT_BOT:BUF.FREQ_BB2.U[1]
    56----------------------------CMT_BOT:BUF.FREQ_BB2.D[0]CMT_BOT:BUF.FREQ_BB3.U[1]
    57----------------------------CMT_BOT:BUF.FREQ_BB3.D[0]-
    58------------------------------
    59-----------------------------CMT_BOT:MUX.FREQ_BB0[1]
    60----------------------------CMT_BOT:MUX.FREQ_BB0[2]CMT_BOT:MUX.FREQ_BB1[1]
    61----------------------------CMT_BOT:MUX.FREQ_BB1[2]CMT_BOT:MUX.FREQ_BB2[1]
    62----------------------------CMT_BOT:MUX.FREQ_BB2[2]CMT_BOT:MUX.FREQ_BB3[1]
    63----------------------------CMT_BOT:MUX.FREQ_BB3[2]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 17
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16----------------------------PHASER_OUT0:TEST_OPT[0]PHASER_OUT0:TEST_OPT[1]
    17----------------------------PHASER_OUT0:TEST_OPT[2]PHASER_OUT0:TEST_OPT[3]
    18----------------------------PHASER_OUT0:TEST_OPT[4]PHASER_OUT0:TEST_OPT[5]
    19----------------------------PHASER_OUT0:TEST_OPT[6]PHASER_OUT0:TEST_OPT[7]
    20----------------------------PHASER_OUT0:TEST_OPT[8]PHASER_OUT0:TEST_OPT[9]
    21----------------------------PHASER_OUT0:TEST_OPT[10]PHASER_OUT0:DATA_RD_CYCLES
    22----------------------------PHASER_OUT0:OCLKDELAY_INVPHASER_OUT0:PHASER_OUT_EN
    23----------------------------PHASER_OUT0:EN_OSERDES_RSTPHASER_OUT0:COARSE_BYPASS
    24----------------------------PHASER_OUT0:OUTPUT_CLK_SRC[0]PHASER_OUT0:OUTPUT_CLK_SRC[1]
    25----------------------------PHASER_OUT0:STG1_BYPASSPHASER_OUT0:OCLK_DELAY[0]
    26----------------------------PHASER_OUT0:OCLK_DELAY[1]PHASER_OUT0:OCLK_DELAY[2]
    27----------------------------PHASER_OUT0:OCLK_DELAY[3]PHASER_OUT0:OCLK_DELAY[4]
    28----------------------------PHASER_OUT0:OCLK_DELAY[5]PHASER_OUT0:EN_TEST_RING
    29----------------------------PHASER_OUT0:DATA_CTL_NPHASER_OUT0:CTL_MODE
    30----------------------------PHASER_OUT0:CLKOUT_DIV[0]PHASER_OUT0:CLKOUT_DIV[1]
    31----------------------------PHASER_OUT0:CLKOUT_DIV[2]PHASER_OUT0:CLKOUT_DIV[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 18
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHASER_OUT0:INV.RSTPHASER_OUT0:MUX.PHASEREFCLK[0]
    1----------------------------PHASER_OUT0:MUX.PHASEREFCLK[1]PHASER_OUT0:MUX.PHASEREFCLK[2]
    2----------------------------PHASER_OUT0:MUX.PHASEREFCLK[3]PHASER_OUT0:COARSE_DELAY[0]
    3----------------------------PHASER_OUT0:COARSE_DELAY[1]PHASER_OUT0:COARSE_DELAY[2]
    4----------------------------PHASER_OUT0:COARSE_DELAY[3]PHASER_OUT0:COARSE_DELAY[4]
    5----------------------------PHASER_OUT0:COARSE_DELAY[5]PHASER_OUT0:FINE_DELAY[0]
    6----------------------------PHASER_OUT0:FINE_DELAY[1]PHASER_OUT0:FINE_DELAY[2]
    7----------------------------PHASER_OUT0:FINE_DELAY[3]PHASER_OUT0:FINE_DELAY[4]
    8----------------------------PHASER_OUT0:FINE_DELAY[5]PHASER_OUT0:SYNC_IN_DIV_RST
    9----------------------------PHASER_OUT0:CLKOUT_DIV_ST[0]PHASER_OUT0:CLKOUT_DIV_ST[1]
    10----------------------------PHASER_OUT0:CLKOUT_DIV_ST[2]PHASER_OUT0:CLKOUT_DIV_ST[3]
    11----------------------------PHASER_OUT0:CLKOUT_DIV[4]PHASER_OUT0:CLKOUT_DIV[5]
    12----------------------------PHASER_OUT0:CLKOUT_DIV[6]PHASER_OUT0:CLKOUT_DIV[7]
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48----------------------------PHASER_IN0:UPDATE_NONACTIVEPHASER_IN0:TEST_BP
    49----------------------------PHASER_IN0:DQS_AUTO_RECALPHASER_IN0:DQS_BIAS_MODE
    50----------------------------PHASER_IN0:REG_OPT_1PHASER_IN0:REG_OPT_4
    51----------------------------PHASER_IN0:RD_ADDR_INIT[0]PHASER_IN0:RD_ADDR_INIT[1]
    52----------------------------PHASER_IN0:SEL_OUTPHASER_IN0:SEL_CLK_OFFSET[0]
    53----------------------------PHASER_IN0:SEL_CLK_OFFSET[1]PHASER_IN0:OUTPUT_CLK_SRC[0]
    54----------------------------PHASER_IN0:OUTPUT_CLK_SRC[1]PHASER_IN0:WR_CYCLES
    55----------------------------PHASER_IN0:PHASER_IN_ENPHASER_IN0:EN_ISERDES_RST
    56----------------------------PHASER_IN0:ICLK_TO_RCLK_BYPASSPHASER_IN0:OUTPUT_CLK_SRC[2]
    57----------------------------PHASER_IN0:OUTPUT_CLK_SRC[3]PHASER_IN0:STG1_PD_UPDATE[0]
    58----------------------------PHASER_IN0:STG1_PD_UPDATE[1]PHASER_IN0:STG1_PD_UPDATE[2]
    59----------------------------PHASER_IN0:INV.RSTPHASER_IN0:MUX.PHASEREFCLK[0]
    60----------------------------PHASER_IN0:HALF_CYCLE_ADJPHASER_IN0:SEL_CLK_OFFSET[2]
    61----------------------------PHASER_IN0:RST_SELPHASER_IN0:REG_OPT_2
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 19
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19----------------------------PHASER_IN0:PD_REVERSE[0]PHASER_IN0:PD_REVERSE[1]
    20----------------------------PHASER_IN0:PD_REVERSE[2]-
    21----------------------------PHASER_IN0:FREQ_REF_DIV[0]PHASER_IN0:FREQ_REF_DIV[1]
    22----------------------------PHASER_IN0:DQS_FIND_PATTERN[0]PHASER_IN0:DQS_FIND_PATTERN[1]
    23----------------------------PHASER_IN0:DQS_FIND_PATTERN[2]PHASER_IN0:EN_TEST_RING
    24----------------------------PHASER_IN0:CTL_MODEPHASER_IN0:CLKOUT_DIV[0]
    25----------------------------PHASER_IN0:CLKOUT_DIV[1]PHASER_IN0:CLKOUT_DIV[2]
    26----------------------------PHASER_IN0:CLKOUT_DIV[3]PHASER_IN0:BURST_MODE
    27----------------------------PHASER_IN0:MUX.PHASEREFCLK[1]PHASER_IN0:MUX.PHASEREFCLK[2]
    28----------------------------PHASER_IN0:MUX.PHASEREFCLK[3]-
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48------------------------------
    49------------------------------
    50------------------------------
    51----------------------------PHASER_IN0:FINE_DELAY[0]PHASER_IN0:FINE_DELAY[1]
    52----------------------------PHASER_IN0:FINE_DELAY[2]PHASER_IN0:FINE_DELAY[3]
    53----------------------------PHASER_IN0:FINE_DELAY[4]PHASER_IN0:FINE_DELAY[5]
    54----------------------------PHASER_IN0:SYNC_IN_DIV_RSTPHASER_IN0:CLKOUT_DIV_ST[0]
    55----------------------------PHASER_IN0:CLKOUT_DIV_ST[1]PHASER_IN0:CLKOUT_DIV_ST[2]
    56----------------------------PHASER_IN0:CLKOUT_DIV_ST[3]PHASER_IN0:CLKOUT_DIV[4]
    57----------------------------PHASER_IN0:CLKOUT_DIV[5]PHASER_IN0:CLKOUT_DIV[6]
    58----------------------------PHASER_IN0:CLKOUT_DIV[7]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 20
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48----------------------------PHASER_OUT1:TEST_OPT[0]PHASER_OUT1:TEST_OPT[1]
    49----------------------------PHASER_OUT1:TEST_OPT[2]PHASER_OUT1:TEST_OPT[3]
    50----------------------------PHASER_OUT1:TEST_OPT[4]PHASER_OUT1:TEST_OPT[5]
    51----------------------------PHASER_OUT1:TEST_OPT[6]PHASER_OUT1:TEST_OPT[7]
    52----------------------------PHASER_OUT1:TEST_OPT[8]PHASER_OUT1:TEST_OPT[9]
    53----------------------------PHASER_OUT1:TEST_OPT[10]PHASER_OUT1:DATA_RD_CYCLES
    54----------------------------PHASER_OUT1:OCLKDELAY_INVPHASER_OUT1:PHASER_OUT_EN
    55----------------------------PHASER_OUT1:EN_OSERDES_RSTPHASER_OUT1:COARSE_BYPASS
    56----------------------------PHASER_OUT1:OUTPUT_CLK_SRC[0]PHASER_OUT1:OUTPUT_CLK_SRC[1]
    57----------------------------PHASER_OUT1:STG1_BYPASSPHASER_OUT1:OCLK_DELAY[0]
    58----------------------------PHASER_OUT1:OCLK_DELAY[1]PHASER_OUT1:OCLK_DELAY[2]
    59----------------------------PHASER_OUT1:OCLK_DELAY[3]PHASER_OUT1:OCLK_DELAY[4]
    60----------------------------PHASER_OUT1:OCLK_DELAY[5]PHASER_OUT1:EN_TEST_RING
    61----------------------------PHASER_OUT1:DATA_CTL_NPHASER_OUT1:CTL_MODE
    62----------------------------PHASER_OUT1:CLKOUT_DIV[0]PHASER_OUT1:CLKOUT_DIV[1]
    63----------------------------PHASER_OUT1:CLKOUT_DIV[2]PHASER_OUT1:CLKOUT_DIV[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 21
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------PHASER_OUT1:INV.RSTPHASER_OUT1:MUX.PHASEREFCLK[0]
    33----------------------------PHASER_OUT1:MUX.PHASEREFCLK[1]PHASER_OUT1:MUX.PHASEREFCLK[2]
    34----------------------------PHASER_OUT1:MUX.PHASEREFCLK[3]PHASER_OUT1:COARSE_DELAY[0]
    35----------------------------PHASER_OUT1:COARSE_DELAY[1]PHASER_OUT1:COARSE_DELAY[2]
    36----------------------------PHASER_OUT1:COARSE_DELAY[3]PHASER_OUT1:COARSE_DELAY[4]
    37----------------------------PHASER_OUT1:COARSE_DELAY[5]PHASER_OUT1:FINE_DELAY[0]
    38----------------------------PHASER_OUT1:FINE_DELAY[1]PHASER_OUT1:FINE_DELAY[2]
    39----------------------------PHASER_OUT1:FINE_DELAY[3]PHASER_OUT1:FINE_DELAY[4]
    40----------------------------PHASER_OUT1:FINE_DELAY[5]PHASER_OUT1:SYNC_IN_DIV_RST
    41----------------------------PHASER_OUT1:CLKOUT_DIV_ST[0]PHASER_OUT1:CLKOUT_DIV_ST[1]
    42----------------------------PHASER_OUT1:CLKOUT_DIV_ST[2]PHASER_OUT1:CLKOUT_DIV_ST[3]
    43----------------------------PHASER_OUT1:CLKOUT_DIV[4]PHASER_OUT1:CLKOUT_DIV[5]
    44----------------------------PHASER_OUT1:CLKOUT_DIV[6]PHASER_OUT1:CLKOUT_DIV[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 22
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16----------------------------PHASER_IN1:UPDATE_NONACTIVEPHASER_IN1:TEST_BP
    17----------------------------PHASER_IN1:DQS_AUTO_RECALPHASER_IN1:DQS_BIAS_MODE
    18----------------------------PHASER_IN1:REG_OPT_1PHASER_IN1:REG_OPT_4
    19----------------------------PHASER_IN1:RD_ADDR_INIT[0]PHASER_IN1:RD_ADDR_INIT[1]
    20----------------------------PHASER_IN1:SEL_OUTPHASER_IN1:SEL_CLK_OFFSET[0]
    21----------------------------PHASER_IN1:SEL_CLK_OFFSET[1]PHASER_IN1:OUTPUT_CLK_SRC[0]
    22----------------------------PHASER_IN1:OUTPUT_CLK_SRC[1]PHASER_IN1:WR_CYCLES
    23----------------------------PHASER_IN1:PHASER_IN_ENPHASER_IN1:EN_ISERDES_RST
    24----------------------------PHASER_IN1:ICLK_TO_RCLK_BYPASSPHASER_IN1:OUTPUT_CLK_SRC[2]
    25----------------------------PHASER_IN1:OUTPUT_CLK_SRC[3]PHASER_IN1:STG1_PD_UPDATE[0]
    26----------------------------PHASER_IN1:STG1_PD_UPDATE[1]PHASER_IN1:STG1_PD_UPDATE[2]
    27----------------------------PHASER_IN1:INV.RSTPHASER_IN1:MUX.PHASEREFCLK[0]
    28----------------------------PHASER_IN1:HALF_CYCLE_ADJPHASER_IN1:SEL_CLK_OFFSET[2]
    29----------------------------PHASER_IN1:RST_SELPHASER_IN1:REG_OPT_2
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48------------------------------
    49------------------------------
    50------------------------------
    51----------------------------PHASER_IN1:PD_REVERSE[0]PHASER_IN1:PD_REVERSE[1]
    52----------------------------PHASER_IN1:PD_REVERSE[2]-
    53----------------------------PHASER_IN1:FREQ_REF_DIV[0]PHASER_IN1:FREQ_REF_DIV[1]
    54----------------------------PHASER_IN1:DQS_FIND_PATTERN[0]PHASER_IN1:DQS_FIND_PATTERN[1]
    55----------------------------PHASER_IN1:DQS_FIND_PATTERN[2]PHASER_IN1:EN_TEST_RING
    56----------------------------PHASER_IN1:CTL_MODEPHASER_IN1:CLKOUT_DIV[0]
    57----------------------------PHASER_IN1:CLKOUT_DIV[1]PHASER_IN1:CLKOUT_DIV[2]
    58----------------------------PHASER_IN1:CLKOUT_DIV[3]PHASER_IN1:BURST_MODE
    59----------------------------PHASER_IN1:MUX.PHASEREFCLK[1]PHASER_IN1:MUX.PHASEREFCLK[2]
    60----------------------------PHASER_IN1:MUX.PHASEREFCLK[3]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 23
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19----------------------------PHASER_IN1:FINE_DELAY[0]PHASER_IN1:FINE_DELAY[1]
    20----------------------------PHASER_IN1:FINE_DELAY[2]PHASER_IN1:FINE_DELAY[3]
    21----------------------------PHASER_IN1:FINE_DELAY[4]PHASER_IN1:FINE_DELAY[5]
    22----------------------------PHASER_IN1:SYNC_IN_DIV_RSTPHASER_IN1:CLKOUT_DIV_ST[0]
    23----------------------------PHASER_IN1:CLKOUT_DIV_ST[1]PHASER_IN1:CLKOUT_DIV_ST[2]
    24----------------------------PHASER_IN1:CLKOUT_DIV_ST[3]PHASER_IN1:CLKOUT_DIV[4]
    25----------------------------PHASER_IN1:CLKOUT_DIV[5]PHASER_IN1:CLKOUT_DIV[6]
    26----------------------------PHASER_IN1:CLKOUT_DIV[7]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 24
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16--------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE1[0]HCLK_CMT:MUX.LCLK0_CMT_D[7]-HCLK_CMT:MUX.LCLK1_CMT_D[7]
    17--------------------------HCLK_CMT:MUX.LCLK0_CMT_D[8]HCLK_CMT:MUX.LCLK0_CMT_D[6]HCLK_CMT:MUX.LCLK1_CMT_D[8]HCLK_CMT:MUX.LCLK1_CMT_D[6]
    18--------------------------HCLK_CMT:MUX.LCLK0_CMT_D[5]HCLK_CMT:MUX.LCLK0_CMT_D[4]HCLK_CMT:MUX.LCLK1_CMT_D[5]HCLK_CMT:MUX.LCLK1_CMT_D[4]
    19--------------------------HCLK_CMT:MUX.LCLK0_CMT_D[3]HCLK_CMT:MUX.LCLK0_CMT_D[2]HCLK_CMT:MUX.LCLK1_CMT_D[3]HCLK_CMT:MUX.LCLK1_CMT_D[2]
    20--------------------------HCLK_CMT:MUX.LCLK0_CMT_D[1]HCLK_CMT:MUX.LCLK0_CMT_D[0]HCLK_CMT:MUX.LCLK1_CMT_D[1]HCLK_CMT:MUX.LCLK1_CMT_D[0]
    21--------------------------MMCM:MUX.CLKIN2_HCLK[6]MMCM:MUX.CLKIN2_HCLK[7]MMCM:MUX.CLKIN1_HCLK[6]MMCM:MUX.CLKIN1_HCLK[7]
    22--------------------------MMCM:MUX.CLKIN2_HCLK[8]MMCM:MUX.CLKIN2_HCLK[9]MMCM:MUX.CLKIN1_HCLK[8]MMCM:MUX.CLKIN1_HCLK[9]
    23--------------------------MMCM:MUX.CLKIN2_HCLK[10]MMCM:MUX.CLKIN2_HCLK[5]MMCM:MUX.CLKIN1_HCLK[10]MMCM:MUX.CLKIN1_HCLK[5]
    24--------------------------MMCM:MUX.CLKIN2_HCLK[4]MMCM:MUX.CLKIN2_HCLK[3]MMCM:MUX.CLKIN1_HCLK[4]MMCM:MUX.CLKIN1_HCLK[3]
    25--------------------------MMCM:MUX.CLKIN2_HCLK[2]MMCM:MUX.CLKIN2_HCLK[1]MMCM:MUX.CLKIN1_HCLK[2]MMCM:MUX.CLKIN1_HCLK[1]
    26--------------------------MMCM:MUX.CLKIN2_HCLK[0]MMCM:MUX.CLKFBIN_HCLK[6]MMCM:MUX.CLKIN1_HCLK[0]-
    27--------------------------MMCM:MUX.CLKFBIN_HCLK[7]MMCM:MUX.CLKFBIN_HCLK[8]--
    28--------------------------MMCM:MUX.CLKFBIN_HCLK[9]MMCM:MUX.CLKFBIN_HCLK[10]--
    29--------------------------MMCM:MUX.CLKFBIN_HCLK[5]MMCM:MUX.CLKFBIN_HCLK[4]--
    30--------------------------MMCM:MUX.CLKFBIN_HCLK[3]MMCM:MUX.CLKFBIN_HCLK[2]--
    31--------------------------MMCM:MUX.CLKFBIN_HCLK[1]MMCM:MUX.CLKFBIN_HCLK[0]--
    32--------------------------HCLK_CMT:MUX.HOUT6[7]HCLK_CMT:MUX.HOUT6[5]--
    33--------------------------HCLK_CMT:MUX.HOUT6[6]HCLK_CMT:MUX.HOUT6[0]--
    34--------------------------HCLK_CMT:MUX.HOUT6[1]HCLK_CMT:MUX.HOUT6[4]--
    35--------------------------HCLK_CMT:MUX.HOUT6[2]HCLK_CMT:MUX.HOUT6[3]PHASER_IN3:ENABLE.RCLKPHASER_IN2:ENABLE.RCLK
    36--------------------------HCLK_CMT:MUX.HOUT6[13]HCLK_CMT:MUX.HOUT6[12]PHASER_IN1:ENABLE.RCLKPHASER_IN0:ENABLE.RCLK
    37--------------------------HCLK_CMT:MUX.HOUT6[11]HCLK_CMT:MUX.HOUT6[10]MMCM:ENABLE.PERF3MMCM:ENABLE.PERF2
    38--------------------------HCLK_CMT:MUX.HOUT6[9]HCLK_CMT:MUX.HOUT6[8]MMCM:ENABLE.PERF1MMCM:ENABLE.PERF0
    39--------------------------HCLK_CMT:MUX.HOUT4[7]HCLK_CMT:MUX.HOUT4[5]HCLK_CMT:MUX.HOUT5[7]HCLK_CMT:MUX.HOUT5[5]
    40--------------------------HCLK_CMT:MUX.HOUT4[6]HCLK_CMT:MUX.HOUT4[0]HCLK_CMT:MUX.HOUT5[6]HCLK_CMT:MUX.HOUT5[0]
    41--------------------------HCLK_CMT:MUX.HOUT4[1]HCLK_CMT:MUX.HOUT4[4]HCLK_CMT:MUX.HOUT5[1]HCLK_CMT:MUX.HOUT5[4]
    42--------------------------HCLK_CMT:MUX.HOUT4[2]HCLK_CMT:MUX.HOUT4[3]HCLK_CMT:MUX.HOUT5[2]HCLK_CMT:MUX.HOUT5[3]
    43--------------------------HCLK_CMT:MUX.HOUT4[13]HCLK_CMT:MUX.HOUT4[12]HCLK_CMT:MUX.HOUT5[13]HCLK_CMT:MUX.HOUT5[12]
    44--------------------------HCLK_CMT:MUX.HOUT4[11]HCLK_CMT:MUX.HOUT4[10]HCLK_CMT:MUX.HOUT5[11]HCLK_CMT:MUX.HOUT5[10]
    45--------------------------HCLK_CMT:MUX.HOUT4[9]HCLK_CMT:MUX.HOUT4[8]HCLK_CMT:MUX.HOUT5[9]HCLK_CMT:MUX.HOUT5[8]
    46--------------------------HCLK_CMT:MUX.HOUT2[7]HCLK_CMT:MUX.HOUT2[5]HCLK_CMT:MUX.HOUT3[7]HCLK_CMT:MUX.HOUT3[5]
    47--------------------------HCLK_CMT:MUX.HOUT2[6]HCLK_CMT:MUX.HOUT2[0]HCLK_CMT:MUX.HOUT3[6]HCLK_CMT:MUX.HOUT3[0]
    48--------------------------HCLK_CMT:MUX.HOUT2[1]HCLK_CMT:MUX.HOUT2[4]HCLK_CMT:MUX.HOUT3[1]HCLK_CMT:MUX.HOUT3[4]
    49--------------------------HCLK_CMT:MUX.HOUT2[2]HCLK_CMT:MUX.HOUT2[3]HCLK_CMT:MUX.HOUT3[2]HCLK_CMT:MUX.HOUT3[3]
    50--------------------------HCLK_CMT:MUX.HOUT2[13]HCLK_CMT:MUX.HOUT2[12]HCLK_CMT:MUX.HOUT3[13]HCLK_CMT:MUX.HOUT3[12]
    51--------------------------HCLK_CMT:MUX.HOUT2[11]HCLK_CMT:MUX.HOUT2[10]HCLK_CMT:MUX.HOUT3[11]HCLK_CMT:MUX.HOUT3[10]
    52--------------------------HCLK_CMT:MUX.HOUT2[9]HCLK_CMT:MUX.HOUT2[8]HCLK_CMT:MUX.HOUT3[9]HCLK_CMT:MUX.HOUT3[8]
    53--------------------------HCLK_CMT:MUX.HOUT0[7]HCLK_CMT:MUX.HOUT0[5]HCLK_CMT:MUX.HOUT1[7]HCLK_CMT:MUX.HOUT1[5]
    54--------------------------HCLK_CMT:MUX.HOUT0[6]HCLK_CMT:MUX.HOUT0[0]HCLK_CMT:MUX.HOUT1[6]HCLK_CMT:MUX.HOUT1[0]
    55--------------------------HCLK_CMT:MUX.HOUT0[1]HCLK_CMT:MUX.HOUT0[4]HCLK_CMT:MUX.HOUT1[1]HCLK_CMT:MUX.HOUT1[4]
    56--------------------------HCLK_CMT:MUX.HOUT0[2]HCLK_CMT:MUX.HOUT0[3]HCLK_CMT:MUX.HOUT1[2]HCLK_CMT:MUX.HOUT1[3]
    57--------------------------HCLK_CMT:MUX.HOUT0[13]HCLK_CMT:MUX.HOUT0[12]HCLK_CMT:MUX.HOUT1[13]HCLK_CMT:MUX.HOUT1[12]
    58--------------------------HCLK_CMT:MUX.HOUT0[11]HCLK_CMT:MUX.HOUT0[10]HCLK_CMT:MUX.HOUT1[11]HCLK_CMT:MUX.HOUT1[10]
    59--------------------------HCLK_CMT:MUX.HOUT0[9]HCLK_CMT:MUX.HOUT0[8]HCLK_CMT:MUX.HOUT1[9]HCLK_CMT:MUX.HOUT1[8]
    60--------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE1[2]HCLK_CMT:MUX.PHASER_REF_BOUNCE0[1]HCLK_CMT:ENABLE.FREQ_BB3HCLK_CMT:ENABLE.FREQ_BB2
    61--------------------------HCLK_CMT:MUX.PHASER_REF_BOUNCE0[0]HCLK_CMT:MUX.PHASER_REF_BOUNCE0[2]HCLK_CMT:ENABLE.FREQ_BB1HCLK_CMT:ENABLE.FREQ_BB0
    62--------------------------HCLK_CMT:ENABLE.CCIO3HCLK_CMT:ENABLE.CCIO2HCLK_CMT:MUX.FREQ_BB3[0]HCLK_CMT:MUX.FREQ_BB2[0]
    63--------------------------HCLK_CMT:ENABLE.CCIO1HCLK_CMT:ENABLE.CCIO0HCLK_CMT:MUX.FREQ_BB1[0]HCLK_CMT:MUX.FREQ_BB0[0]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 25
    RowColumn
    01234567891011121314151617181920212223242526272829
    0--------------------------BUFMRCE0:MUX.I[3]BUFMRCE0:MUX.I[4]HCLK_CMT:MUX.FREQ_BB2[2]HCLK_CMT:MUX.FREQ_BB2[1]
    1--------------------------BUFMRCE0:MUX.I[5]BUFMRCE1:MUX.I[3]HCLK_CMT:MUX.FREQ_BB1[2]HCLK_CMT:MUX.FREQ_BB1[1]
    2--------------------------BUFMRCE1:MUX.I[4]BUFMRCE1:MUX.I[5]BUFMRCE0:MUX.I[0]BUFMRCE0:MUX.I[1]
    3--------------------------HCLK_CMT:MUX.FREQ_BB3[2]HCLK_CMT:MUX.FREQ_BB3[1]HCLK_CMT:MUX.FREQ_BB0[2]HCLK_CMT:MUX.FREQ_BB0[1]
    4--------------------------HCLK_CMT:MUX.HOUT7[8]HCLK_CMT:MUX.HOUT7[9]HCLK_CMT:MUX.HOUT8[8]HCLK_CMT:MUX.HOUT8[9]
    5--------------------------HCLK_CMT:MUX.HOUT7[10]HCLK_CMT:MUX.HOUT7[11]HCLK_CMT:MUX.HOUT8[10]HCLK_CMT:MUX.HOUT8[11]
    6--------------------------HCLK_CMT:MUX.HOUT7[12]HCLK_CMT:MUX.HOUT7[13]HCLK_CMT:MUX.HOUT8[12]HCLK_CMT:MUX.HOUT8[13]
    7--------------------------HCLK_CMT:MUX.HOUT7[3]HCLK_CMT:MUX.HOUT7[2]HCLK_CMT:MUX.HOUT8[3]HCLK_CMT:MUX.HOUT8[2]
    8--------------------------HCLK_CMT:MUX.HOUT7[4]HCLK_CMT:MUX.HOUT7[1]HCLK_CMT:MUX.HOUT8[4]HCLK_CMT:MUX.HOUT8[1]
    9--------------------------HCLK_CMT:MUX.HOUT7[0]HCLK_CMT:MUX.HOUT7[6]HCLK_CMT:MUX.HOUT8[0]HCLK_CMT:MUX.HOUT8[6]
    10--------------------------HCLK_CMT:MUX.HOUT7[5]HCLK_CMT:MUX.HOUT7[7]HCLK_CMT:MUX.HOUT8[5]HCLK_CMT:MUX.HOUT8[7]
    11--------------------------HCLK_CMT:MUX.HOUT9[8]HCLK_CMT:MUX.HOUT9[9]HCLK_CMT:MUX.HOUT10[8]HCLK_CMT:MUX.HOUT10[9]
    12--------------------------HCLK_CMT:MUX.HOUT9[10]HCLK_CMT:MUX.HOUT9[11]HCLK_CMT:MUX.HOUT10[10]HCLK_CMT:MUX.HOUT10[11]
    13--------------------------HCLK_CMT:MUX.HOUT9[12]HCLK_CMT:MUX.HOUT9[13]HCLK_CMT:MUX.HOUT10[12]HCLK_CMT:MUX.HOUT10[13]
    14--------------------------HCLK_CMT:MUX.HOUT9[3]HCLK_CMT:MUX.HOUT9[2]HCLK_CMT:MUX.HOUT10[3]HCLK_CMT:MUX.HOUT10[2]
    15--------------------------HCLK_CMT:MUX.HOUT9[4]HCLK_CMT:MUX.HOUT9[1]HCLK_CMT:MUX.HOUT10[4]HCLK_CMT:MUX.HOUT10[1]
    16--------------------------HCLK_CMT:MUX.HOUT9[0]HCLK_CMT:MUX.HOUT9[6]HCLK_CMT:MUX.HOUT10[0]HCLK_CMT:MUX.HOUT10[6]
    17--------------------------HCLK_CMT:MUX.HOUT9[5]HCLK_CMT:MUX.HOUT9[7]HCLK_CMT:MUX.HOUT10[5]HCLK_CMT:MUX.HOUT10[7]
    18--------------------------HCLK_CMT:MUX.HOUT11[8]HCLK_CMT:MUX.HOUT11[9]HCLK_CMT:MUX.HOUT12[8]HCLK_CMT:MUX.HOUT12[9]
    19--------------------------HCLK_CMT:MUX.HOUT11[10]HCLK_CMT:MUX.HOUT11[11]HCLK_CMT:MUX.HOUT12[10]HCLK_CMT:MUX.HOUT12[11]
    20--------------------------HCLK_CMT:MUX.HOUT11[12]HCLK_CMT:MUX.HOUT11[13]HCLK_CMT:MUX.HOUT12[12]HCLK_CMT:MUX.HOUT12[13]
    21--------------------------HCLK_CMT:MUX.HOUT11[3]HCLK_CMT:MUX.HOUT11[2]HCLK_CMT:MUX.HOUT12[3]HCLK_CMT:MUX.HOUT12[2]
    22--------------------------HCLK_CMT:MUX.HOUT11[4]HCLK_CMT:MUX.HOUT11[1]HCLK_CMT:MUX.HOUT12[4]HCLK_CMT:MUX.HOUT12[1]
    23--------------------------HCLK_CMT:MUX.HOUT11[0]HCLK_CMT:MUX.HOUT11[6]HCLK_CMT:MUX.HOUT12[0]HCLK_CMT:MUX.HOUT12[6]
    24--------------------------HCLK_CMT:MUX.HOUT11[5]HCLK_CMT:MUX.HOUT11[7]HCLK_CMT:MUX.HOUT12[5]HCLK_CMT:MUX.HOUT12[7]
    25--------------------------HCLK_CMT:MUX.HOUT13[8]HCLK_CMT:MUX.HOUT13[9]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[2]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[0]
    26--------------------------HCLK_CMT:MUX.HOUT13[10]HCLK_CMT:MUX.HOUT13[11]HCLK_CMT:MUX.PHASER_REF_BOUNCE2[1]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[2]
    27--------------------------HCLK_CMT:MUX.HOUT13[12]HCLK_CMT:MUX.HOUT13[13]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[0]HCLK_CMT:MUX.PHASER_REF_BOUNCE3[1]
    28--------------------------HCLK_CMT:MUX.HOUT13[3]HCLK_CMT:MUX.HOUT13[2]--
    29--------------------------HCLK_CMT:MUX.HOUT13[4]HCLK_CMT:MUX.HOUT13[1]--
    30--------------------------HCLK_CMT:MUX.HOUT13[0]HCLK_CMT:MUX.HOUT13[6]--
    31--------------------------HCLK_CMT:MUX.HOUT13[5]HCLK_CMT:MUX.HOUT13[7]--
    32--------------------------PLL:MUX.CLKFBIN_HCLK[0]PLL:MUX.CLKFBIN_HCLK[1]--
    33--------------------------PLL:MUX.CLKFBIN_HCLK[2]PLL:MUX.CLKFBIN_HCLK[3]--
    34--------------------------PLL:MUX.CLKFBIN_HCLK[4]PLL:MUX.CLKFBIN_HCLK[5]--
    35--------------------------PLL:MUX.CLKFBIN_HCLK[10]PLL:MUX.CLKFBIN_HCLK[9]--
    36--------------------------PLL:MUX.CLKFBIN_HCLK[8]PLL:MUX.CLKFBIN_HCLK[7]--
    37--------------------------PLL:MUX.CLKFBIN_HCLK[6]PLL:MUX.CLKIN2_HCLK[0]-PLL:MUX.CLKIN1_HCLK[0]
    38--------------------------PLL:MUX.CLKIN2_HCLK[1]PLL:MUX.CLKIN2_HCLK[2]PLL:MUX.CLKIN1_HCLK[1]PLL:MUX.CLKIN1_HCLK[2]
    39--------------------------PLL:MUX.CLKIN2_HCLK[3]PLL:MUX.CLKIN2_HCLK[4]PLL:MUX.CLKIN1_HCLK[3]PLL:MUX.CLKIN1_HCLK[4]
    40--------------------------PLL:MUX.CLKIN2_HCLK[5]PLL:MUX.CLKIN2_HCLK[10]PLL:MUX.CLKIN1_HCLK[5]PLL:MUX.CLKIN1_HCLK[10]
    41--------------------------PLL:MUX.CLKIN2_HCLK[9]PLL:MUX.CLKIN2_HCLK[8]PLL:MUX.CLKIN1_HCLK[9]PLL:MUX.CLKIN1_HCLK[8]
    42--------------------------PLL:MUX.CLKIN2_HCLK[7]PLL:MUX.CLKIN2_HCLK[6]PLL:MUX.CLKIN1_HCLK[7]PLL:MUX.CLKIN1_HCLK[6]
    43--------------------------HCLK_CMT:MUX.LCLK0_CMT_U[0]HCLK_CMT:MUX.LCLK0_CMT_U[1]HCLK_CMT:MUX.LCLK1_CMT_U[0]HCLK_CMT:MUX.LCLK1_CMT_U[1]
    44--------------------------HCLK_CMT:MUX.LCLK0_CMT_U[2]HCLK_CMT:MUX.LCLK0_CMT_U[3]HCLK_CMT:MUX.LCLK1_CMT_U[2]HCLK_CMT:MUX.LCLK1_CMT_U[3]
    45--------------------------HCLK_CMT:MUX.LCLK0_CMT_U[4]HCLK_CMT:MUX.LCLK0_CMT_U[5]HCLK_CMT:MUX.LCLK1_CMT_U[4]HCLK_CMT:MUX.LCLK1_CMT_U[5]
    46--------------------------HCLK_CMT:MUX.LCLK0_CMT_U[6]HCLK_CMT:MUX.LCLK0_CMT_U[8]HCLK_CMT:MUX.LCLK1_CMT_U[6]HCLK_CMT:MUX.LCLK1_CMT_U[8]
    47--------------------------HCLK_CMT:MUX.LCLK0_CMT_U[7]HCLK_CMT:MUX.PHASER_REF_BOUNCE1[1]HCLK_CMT:MUX.LCLK1_CMT_U[7]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 26
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHASER_REF:PHASER_REF_MISC[0]PHASER_REF:PHASER_REF_MISC[1]
    1----------------------------PHASER_REF:PHASER_REF_MISC[2]PHASER_REF:CP_BIAS_TRIP_SET
    2----------------------------PHASER_REF:TMUX_MUX_SEL[0]PHASER_REF:TMUX_MUX_SEL[1]
    3----------------------------PHASER_REF:SEL_SLIPDPHASER_REF:LOCK_REF_DLY[0]
    4----------------------------PHASER_REF:LOCK_REF_DLY[1]PHASER_REF:LOCK_REF_DLY[2]
    5----------------------------PHASER_REF:LOCK_REF_DLY[3]PHASER_REF:LOCK_REF_DLY[4]
    6----------------------------PHASER_REF:SEL_LF_HIGH[0]PHASER_REF:SEL_LF_HIGH[1]
    7----------------------------PHASER_REF:SEL_LF_HIGH[2]PHASER_REF:SUP_SEL_AREG
    8----------------------------PHASER_REF:CONTROL_3[0]PHASER_REF:CONTROL_3[1]
    9----------------------------PHASER_REF:CONTROL_3[2]PHASER_REF:CONTROL_3[3]
    10----------------------------PHASER_REF:CONTROL_3[4]PHASER_REF:CONTROL_3[5]
    11----------------------------PHASER_REF:CONTROL_3[6]PHASER_REF:CONTROL_3[7]
    12----------------------------PHASER_REF:CONTROL_3[8]PHASER_REF:CONTROL_3[9]
    13----------------------------PHASER_REF:CONTROL_3[10]PHASER_REF:CONTROL_3[11]
    14----------------------------PHASER_REF:CONTROL_3[12]PHASER_REF:CONTROL_3[13]
    15----------------------------PHASER_REF:CONTROL_3[14]PHASER_REF:CONTROL_3[15]
    16----------------------------PHASER_REF:INV.RSTPHASER_REF:MAN_LF[0]
    17----------------------------PHASER_REF:MAN_LF[1]PHASER_REF:MAN_LF[2]
    18----------------------------PHASER_REF:PFD[0]PHASER_REF:PFD[1]
    19----------------------------PHASER_REF:PFD[2]PHASER_REF:PFD[3]
    20----------------------------PHASER_REF:PFD[4]PHASER_REF:PFD[5]
    21----------------------------PHASER_REF:PFD[6]PHASER_REF:LOCK_FB_DLY[0]
    22----------------------------PHASER_REF:LOCK_FB_DLY[1]PHASER_REF:LOCK_FB_DLY[2]
    23----------------------------PHASER_REF:LOCK_FB_DLY[3]PHASER_REF:LOCK_FB_DLY[4]
    24----------------------------PHASER_REF:INV.PWRDWNPHASER_REF:PHASER_REF_EN
    25----------------------------PHASER_REF:LOCK_CNT[0]PHASER_REF:LOCK_CNT[1]
    26----------------------------PHASER_REF:LOCK_CNT[2]PHASER_REF:LOCK_CNT[3]
    27----------------------------PHASER_REF:LOCK_CNT[4]PHASER_REF:LOCK_CNT[5]
    28----------------------------PHASER_REF:LOCK_CNT[6]PHASER_REF:LOCK_CNT[7]
    29----------------------------PHASER_REF:LOCK_CNT[8]PHASER_REF:LOCK_CNT[9]
    30----------------------------PHASER_REF:LF_PEN[0]PHASER_REF:LF_PEN[1]
    31----------------------------PHASER_REF:LF_NEN[0]PHASER_REF:LF_NEN[1]
    32----------------------------PHASER_REF:CONTROL_2[0]PHASER_REF:CONTROL_2[1]
    33----------------------------PHASER_REF:CONTROL_2[2]PHASER_REF:CONTROL_2[3]
    34----------------------------PHASER_REF:CONTROL_2[4]PHASER_REF:CONTROL_2[5]
    35----------------------------PHASER_REF:CONTROL_2[6]PHASER_REF:CONTROL_2[7]
    36----------------------------PHASER_REF:CONTROL_2[8]PHASER_REF:CONTROL_2[9]
    37----------------------------PHASER_REF:CONTROL_2[10]PHASER_REF:CONTROL_2[11]
    38----------------------------PHASER_REF:CONTROL_2[12]PHASER_REF:CONTROL_2[13]
    39----------------------------PHASER_REF:CONTROL_2[14]PHASER_REF:CONTROL_2[15]
    40----------------------------PHASER_REF:CONTROL_1[0]PHASER_REF:CONTROL_1[1]
    41----------------------------PHASER_REF:CONTROL_1[2]PHASER_REF:CONTROL_1[3]
    42----------------------------PHASER_REF:CONTROL_1[4]PHASER_REF:CONTROL_1[5]
    43----------------------------PHASER_REF:CONTROL_1[6]PHASER_REF:CONTROL_1[7]
    44----------------------------PHASER_REF:CONTROL_1[8]PHASER_REF:CONTROL_1[9]
    45----------------------------PHASER_REF:CONTROL_1[10]PHASER_REF:CONTROL_1[11]
    46----------------------------PHASER_REF:CONTROL_1[12]PHASER_REF:CONTROL_1[13]
    47----------------------------PHASER_REF:CONTROL_1[14]PHASER_REF:CONTROL_1[15]
    48----------------------------PHASER_REF:CONTROL_0[0]PHASER_REF:CONTROL_0[1]
    49----------------------------PHASER_REF:CONTROL_0[2]PHASER_REF:CONTROL_0[3]
    50----------------------------PHASER_REF:CONTROL_0[4]PHASER_REF:CONTROL_0[5]
    51----------------------------PHASER_REF:CONTROL_0[6]PHASER_REF:CONTROL_0[7]
    52----------------------------PHASER_REF:CONTROL_0[8]PHASER_REF:CONTROL_0[9]
    53----------------------------PHASER_REF:CONTROL_0[10]PHASER_REF:CONTROL_0[11]
    54----------------------------PHASER_REF:CONTROL_0[12]PHASER_REF:CONTROL_0[13]
    55----------------------------PHASER_REF:CONTROL_0[14]PHASER_REF:CONTROL_0[15]
    56----------------------------PHASER_REF:CP_RES[0]PHASER_REF:CP_RES[1]
    57----------------------------PHASER_REF:CP[0]PHASER_REF:CP[1]
    58----------------------------PHASER_REF:CP[2]PHASER_REF:CP[3]
    59----------------------------PHASER_REF:AVDD_VBG_SEL[0]PHASER_REF:AVDD_VBG_SEL[1]
    60----------------------------PHASER_REF:AVDD_VBG_SEL[2]PHASER_REF:AVDD_VBG_SEL[3]
    61----------------------------PHASER_REF:AVDD_VBG_PD[0]PHASER_REF:AVDD_VBG_PD[1]
    62----------------------------PHASER_REF:AVDD_VBG_PD[2]PHASER_REF:AVDD_COMP_SET[0]
    63----------------------------PHASER_REF:AVDD_COMP_SET[1]PHASER_REF:AVDD_COMP_SET[2]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 27
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHASER_REF:CONTROL_4[0]PHASER_REF:CONTROL_4[1]
    1----------------------------PHASER_REF:CONTROL_4[2]PHASER_REF:CONTROL_4[3]
    2----------------------------PHASER_REF:CONTROL_4[4]PHASER_REF:CONTROL_4[5]
    3----------------------------PHASER_REF:CONTROL_4[6]PHASER_REF:CONTROL_4[7]
    4----------------------------PHASER_REF:CONTROL_4[8]PHASER_REF:CONTROL_4[9]
    5----------------------------PHASER_REF:CONTROL_4[10]PHASER_REF:CONTROL_4[11]
    6----------------------------PHASER_REF:CONTROL_4[12]PHASER_REF:CONTROL_4[13]
    7----------------------------PHASER_REF:CONTROL_4[14]PHASER_REF:CONTROL_4[15]
    8----------------------------PHASER_REF:CONTROL_5[0]PHASER_REF:CONTROL_5[1]
    9----------------------------PHASER_REF:CONTROL_5[2]PHASER_REF:CONTROL_5[3]
    10----------------------------PHASER_REF:CONTROL_5[4]PHASER_REF:CONTROL_5[5]
    11----------------------------PHASER_REF:CONTROL_5[6]PHASER_REF:CONTROL_5[7]
    12----------------------------PHASER_REF:CONTROL_5[8]PHASER_REF:CONTROL_5[9]
    13----------------------------PHASER_REF:CONTROL_5[10]PHASER_REF:CONTROL_5[11]
    14----------------------------PHASER_REF:CONTROL_5[12]PHASER_REF:CONTROL_5[13]
    15----------------------------PHASER_REF:CONTROL_5[14]PHASER_REF:CONTROL_5[15]
    16----------------------------PHASER_OUT2:TEST_OPT[0]PHASER_OUT2:TEST_OPT[1]
    17----------------------------PHASER_OUT2:TEST_OPT[2]PHASER_OUT2:TEST_OPT[3]
    18----------------------------PHASER_OUT2:TEST_OPT[4]PHASER_OUT2:TEST_OPT[5]
    19----------------------------PHASER_OUT2:TEST_OPT[6]PHASER_OUT2:TEST_OPT[7]
    20----------------------------PHASER_OUT2:TEST_OPT[8]PHASER_OUT2:TEST_OPT[9]
    21----------------------------PHASER_OUT2:TEST_OPT[10]PHASER_OUT2:DATA_RD_CYCLES
    22----------------------------PHASER_OUT2:OCLKDELAY_INVPHASER_OUT2:PHASER_OUT_EN
    23----------------------------PHASER_OUT2:EN_OSERDES_RSTPHASER_OUT2:COARSE_BYPASS
    24----------------------------PHASER_OUT2:OUTPUT_CLK_SRC[0]PHASER_OUT2:OUTPUT_CLK_SRC[1]
    25----------------------------PHASER_OUT2:STG1_BYPASSPHASER_OUT2:OCLK_DELAY[0]
    26----------------------------PHASER_OUT2:OCLK_DELAY[1]PHASER_OUT2:OCLK_DELAY[2]
    27----------------------------PHASER_OUT2:OCLK_DELAY[3]PHASER_OUT2:OCLK_DELAY[4]
    28----------------------------PHASER_OUT2:OCLK_DELAY[5]PHASER_OUT2:EN_TEST_RING
    29----------------------------PHASER_OUT2:DATA_CTL_NPHASER_OUT2:CTL_MODE
    30----------------------------PHASER_OUT2:CLKOUT_DIV[0]PHASER_OUT2:CLKOUT_DIV[1]
    31----------------------------PHASER_OUT2:CLKOUT_DIV[2]PHASER_OUT2:CLKOUT_DIV[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 28
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHASER_OUT2:INV.RSTPHASER_OUT2:MUX.PHASEREFCLK[0]
    1----------------------------PHASER_OUT2:MUX.PHASEREFCLK[1]PHASER_OUT2:MUX.PHASEREFCLK[2]
    2----------------------------PHASER_OUT2:MUX.PHASEREFCLK[3]PHASER_OUT2:COARSE_DELAY[0]
    3----------------------------PHASER_OUT2:COARSE_DELAY[1]PHASER_OUT2:COARSE_DELAY[2]
    4----------------------------PHASER_OUT2:COARSE_DELAY[3]PHASER_OUT2:COARSE_DELAY[4]
    5----------------------------PHASER_OUT2:COARSE_DELAY[5]PHASER_OUT2:FINE_DELAY[0]
    6----------------------------PHASER_OUT2:FINE_DELAY[1]PHASER_OUT2:FINE_DELAY[2]
    7----------------------------PHASER_OUT2:FINE_DELAY[3]PHASER_OUT2:FINE_DELAY[4]
    8----------------------------PHASER_OUT2:FINE_DELAY[5]PHASER_OUT2:SYNC_IN_DIV_RST
    9----------------------------PHASER_OUT2:CLKOUT_DIV_ST[0]PHASER_OUT2:CLKOUT_DIV_ST[1]
    10----------------------------PHASER_OUT2:CLKOUT_DIV_ST[2]PHASER_OUT2:CLKOUT_DIV_ST[3]
    11----------------------------PHASER_OUT2:CLKOUT_DIV[4]PHASER_OUT2:CLKOUT_DIV[5]
    12----------------------------PHASER_OUT2:CLKOUT_DIV[6]PHASER_OUT2:CLKOUT_DIV[7]
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48----------------------------PHASER_IN2:UPDATE_NONACTIVEPHASER_IN2:TEST_BP
    49----------------------------PHASER_IN2:DQS_AUTO_RECALPHASER_IN2:DQS_BIAS_MODE
    50----------------------------PHASER_IN2:REG_OPT_1PHASER_IN2:REG_OPT_4
    51----------------------------PHASER_IN2:RD_ADDR_INIT[0]PHASER_IN2:RD_ADDR_INIT[1]
    52----------------------------PHASER_IN2:SEL_OUTPHASER_IN2:SEL_CLK_OFFSET[0]
    53----------------------------PHASER_IN2:SEL_CLK_OFFSET[1]PHASER_IN2:OUTPUT_CLK_SRC[0]
    54----------------------------PHASER_IN2:OUTPUT_CLK_SRC[1]PHASER_IN2:WR_CYCLES
    55----------------------------PHASER_IN2:PHASER_IN_ENPHASER_IN2:EN_ISERDES_RST
    56----------------------------PHASER_IN2:ICLK_TO_RCLK_BYPASSPHASER_IN2:OUTPUT_CLK_SRC[2]
    57----------------------------PHASER_IN2:OUTPUT_CLK_SRC[3]PHASER_IN2:STG1_PD_UPDATE[0]
    58----------------------------PHASER_IN2:STG1_PD_UPDATE[1]PHASER_IN2:STG1_PD_UPDATE[2]
    59----------------------------PHASER_IN2:INV.RSTPHASER_IN2:MUX.PHASEREFCLK[0]
    60----------------------------PHASER_IN2:HALF_CYCLE_ADJPHASER_IN2:SEL_CLK_OFFSET[2]
    61----------------------------PHASER_IN2:RST_SELPHASER_IN2:REG_OPT_2
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 29
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19----------------------------PHASER_IN2:PD_REVERSE[0]PHASER_IN2:PD_REVERSE[1]
    20----------------------------PHASER_IN2:PD_REVERSE[2]-
    21----------------------------PHASER_IN2:FREQ_REF_DIV[0]PHASER_IN2:FREQ_REF_DIV[1]
    22----------------------------PHASER_IN2:DQS_FIND_PATTERN[0]PHASER_IN2:DQS_FIND_PATTERN[1]
    23----------------------------PHASER_IN2:DQS_FIND_PATTERN[2]PHASER_IN2:EN_TEST_RING
    24----------------------------PHASER_IN2:CTL_MODEPHASER_IN2:CLKOUT_DIV[0]
    25----------------------------PHASER_IN2:CLKOUT_DIV[1]PHASER_IN2:CLKOUT_DIV[2]
    26----------------------------PHASER_IN2:CLKOUT_DIV[3]PHASER_IN2:BURST_MODE
    27----------------------------PHASER_IN2:MUX.PHASEREFCLK[1]PHASER_IN2:MUX.PHASEREFCLK[2]
    28----------------------------PHASER_IN2:MUX.PHASEREFCLK[3]-
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48------------------------------
    49------------------------------
    50------------------------------
    51----------------------------PHASER_IN2:FINE_DELAY[0]PHASER_IN2:FINE_DELAY[1]
    52----------------------------PHASER_IN2:FINE_DELAY[2]PHASER_IN2:FINE_DELAY[3]
    53----------------------------PHASER_IN2:FINE_DELAY[4]PHASER_IN2:FINE_DELAY[5]
    54----------------------------PHASER_IN2:SYNC_IN_DIV_RSTPHASER_IN2:CLKOUT_DIV_ST[0]
    55----------------------------PHASER_IN2:CLKOUT_DIV_ST[1]PHASER_IN2:CLKOUT_DIV_ST[2]
    56----------------------------PHASER_IN2:CLKOUT_DIV_ST[3]PHASER_IN2:CLKOUT_DIV[4]
    57----------------------------PHASER_IN2:CLKOUT_DIV[5]PHASER_IN2:CLKOUT_DIV[6]
    58----------------------------PHASER_IN2:CLKOUT_DIV[7]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 30
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48----------------------------PHASER_OUT3:TEST_OPT[0]PHASER_OUT3:TEST_OPT[1]
    49----------------------------PHASER_OUT3:TEST_OPT[2]PHASER_OUT3:TEST_OPT[3]
    50----------------------------PHASER_OUT3:TEST_OPT[4]PHASER_OUT3:TEST_OPT[5]
    51----------------------------PHASER_OUT3:TEST_OPT[6]PHASER_OUT3:TEST_OPT[7]
    52----------------------------PHASER_OUT3:TEST_OPT[8]PHASER_OUT3:TEST_OPT[9]
    53----------------------------PHASER_OUT3:TEST_OPT[10]PHASER_OUT3:DATA_RD_CYCLES
    54----------------------------PHASER_OUT3:OCLKDELAY_INVPHASER_OUT3:PHASER_OUT_EN
    55----------------------------PHASER_OUT3:EN_OSERDES_RSTPHASER_OUT3:COARSE_BYPASS
    56----------------------------PHASER_OUT3:OUTPUT_CLK_SRC[0]PHASER_OUT3:OUTPUT_CLK_SRC[1]
    57----------------------------PHASER_OUT3:STG1_BYPASSPHASER_OUT3:OCLK_DELAY[0]
    58----------------------------PHASER_OUT3:OCLK_DELAY[1]PHASER_OUT3:OCLK_DELAY[2]
    59----------------------------PHASER_OUT3:OCLK_DELAY[3]PHASER_OUT3:OCLK_DELAY[4]
    60----------------------------PHASER_OUT3:OCLK_DELAY[5]PHASER_OUT3:EN_TEST_RING
    61----------------------------PHASER_OUT3:DATA_CTL_NPHASER_OUT3:CTL_MODE
    62----------------------------PHASER_OUT3:CLKOUT_DIV[0]PHASER_OUT3:CLKOUT_DIV[1]
    63----------------------------PHASER_OUT3:CLKOUT_DIV[2]PHASER_OUT3:CLKOUT_DIV[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 31
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------PHASER_OUT3:INV.RSTPHASER_OUT3:MUX.PHASEREFCLK[0]
    33----------------------------PHASER_OUT3:MUX.PHASEREFCLK[1]PHASER_OUT3:MUX.PHASEREFCLK[2]
    34----------------------------PHASER_OUT3:MUX.PHASEREFCLK[3]PHASER_OUT3:COARSE_DELAY[0]
    35----------------------------PHASER_OUT3:COARSE_DELAY[1]PHASER_OUT3:COARSE_DELAY[2]
    36----------------------------PHASER_OUT3:COARSE_DELAY[3]PHASER_OUT3:COARSE_DELAY[4]
    37----------------------------PHASER_OUT3:COARSE_DELAY[5]PHASER_OUT3:FINE_DELAY[0]
    38----------------------------PHASER_OUT3:FINE_DELAY[1]PHASER_OUT3:FINE_DELAY[2]
    39----------------------------PHASER_OUT3:FINE_DELAY[3]PHASER_OUT3:FINE_DELAY[4]
    40----------------------------PHASER_OUT3:FINE_DELAY[5]PHASER_OUT3:SYNC_IN_DIV_RST
    41----------------------------PHASER_OUT3:CLKOUT_DIV_ST[0]PHASER_OUT3:CLKOUT_DIV_ST[1]
    42----------------------------PHASER_OUT3:CLKOUT_DIV_ST[2]PHASER_OUT3:CLKOUT_DIV_ST[3]
    43----------------------------PHASER_OUT3:CLKOUT_DIV[4]PHASER_OUT3:CLKOUT_DIV[5]
    44----------------------------PHASER_OUT3:CLKOUT_DIV[6]PHASER_OUT3:CLKOUT_DIV[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 32
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16----------------------------PHASER_IN3:UPDATE_NONACTIVEPHASER_IN3:TEST_BP
    17----------------------------PHASER_IN3:DQS_AUTO_RECALPHASER_IN3:DQS_BIAS_MODE
    18----------------------------PHASER_IN3:REG_OPT_1PHASER_IN3:REG_OPT_4
    19----------------------------PHASER_IN3:RD_ADDR_INIT[0]PHASER_IN3:RD_ADDR_INIT[1]
    20----------------------------PHASER_IN3:SEL_OUTPHASER_IN3:SEL_CLK_OFFSET[0]
    21----------------------------PHASER_IN3:SEL_CLK_OFFSET[1]PHASER_IN3:OUTPUT_CLK_SRC[0]
    22----------------------------PHASER_IN3:OUTPUT_CLK_SRC[1]PHASER_IN3:WR_CYCLES
    23----------------------------PHASER_IN3:PHASER_IN_ENPHASER_IN3:EN_ISERDES_RST
    24----------------------------PHASER_IN3:ICLK_TO_RCLK_BYPASSPHASER_IN3:OUTPUT_CLK_SRC[2]
    25----------------------------PHASER_IN3:OUTPUT_CLK_SRC[3]PHASER_IN3:STG1_PD_UPDATE[0]
    26----------------------------PHASER_IN3:STG1_PD_UPDATE[1]PHASER_IN3:STG1_PD_UPDATE[2]
    27----------------------------PHASER_IN3:INV.RSTPHASER_IN3:MUX.PHASEREFCLK[0]
    28----------------------------PHASER_IN3:HALF_CYCLE_ADJPHASER_IN3:SEL_CLK_OFFSET[2]
    29----------------------------PHASER_IN3:RST_SELPHASER_IN3:REG_OPT_2
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48------------------------------
    49------------------------------
    50------------------------------
    51----------------------------PHASER_IN3:PD_REVERSE[0]PHASER_IN3:PD_REVERSE[1]
    52----------------------------PHASER_IN3:PD_REVERSE[2]-
    53----------------------------PHASER_IN3:FREQ_REF_DIV[0]PHASER_IN3:FREQ_REF_DIV[1]
    54----------------------------PHASER_IN3:DQS_FIND_PATTERN[0]PHASER_IN3:DQS_FIND_PATTERN[1]
    55----------------------------PHASER_IN3:DQS_FIND_PATTERN[2]PHASER_IN3:EN_TEST_RING
    56----------------------------PHASER_IN3:CTL_MODEPHASER_IN3:CLKOUT_DIV[0]
    57----------------------------PHASER_IN3:CLKOUT_DIV[1]PHASER_IN3:CLKOUT_DIV[2]
    58----------------------------PHASER_IN3:CLKOUT_DIV[3]PHASER_IN3:BURST_MODE
    59----------------------------PHASER_IN3:MUX.PHASEREFCLK[1]PHASER_IN3:MUX.PHASEREFCLK[2]
    60----------------------------PHASER_IN3:MUX.PHASEREFCLK[3]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 33
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19----------------------------PHASER_IN3:FINE_DELAY[0]PHASER_IN3:FINE_DELAY[1]
    20----------------------------PHASER_IN3:FINE_DELAY[2]PHASER_IN3:FINE_DELAY[3]
    21----------------------------PHASER_IN3:FINE_DELAY[4]PHASER_IN3:FINE_DELAY[5]
    22----------------------------PHASER_IN3:SYNC_IN_DIV_RSTPHASER_IN3:CLKOUT_DIV_ST[0]
    23----------------------------PHASER_IN3:CLKOUT_DIV_ST[1]PHASER_IN3:CLKOUT_DIV_ST[2]
    24----------------------------PHASER_IN3:CLKOUT_DIV_ST[3]PHASER_IN3:CLKOUT_DIV[4]
    25----------------------------PHASER_IN3:CLKOUT_DIV[5]PHASER_IN3:CLKOUT_DIV[6]
    26----------------------------PHASER_IN3:CLKOUT_DIV[7]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 34
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHY_CONTROL:RD_DURATION_0[0]PHY_CONTROL:RD_DURATION_0[1]
    1----------------------------PHY_CONTROL:RD_DURATION_0[2]PHY_CONTROL:RD_DURATION_0[3]
    2----------------------------PHY_CONTROL:RD_DURATION_0[4]PHY_CONTROL:RD_DURATION_0[5]
    3----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[0]PHY_CONTROL:RD_CMD_OFFSET_0[1]
    4----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[2]PHY_CONTROL:RD_CMD_OFFSET_0[3]
    5----------------------------PHY_CONTROL:RD_CMD_OFFSET_0[4]PHY_CONTROL:RD_CMD_OFFSET_0[5]
    6----------------------------PHY_CONTROL:WR_DURATION_0[0]PHY_CONTROL:WR_DURATION_0[1]
    7----------------------------PHY_CONTROL:WR_DURATION_0[2]PHY_CONTROL:WR_DURATION_0[3]
    8----------------------------PHY_CONTROL:WR_DURATION_0[4]PHY_CONTROL:WR_DURATION_0[5]
    9----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[0]PHY_CONTROL:WR_CMD_OFFSET_0[1]
    10----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[2]PHY_CONTROL:WR_CMD_OFFSET_0[3]
    11----------------------------PHY_CONTROL:WR_CMD_OFFSET_0[4]PHY_CONTROL:WR_CMD_OFFSET_0[5]
    12----------------------------PHY_CONTROL:DO_DURATION[0]PHY_CONTROL:DO_DURATION[1]
    13----------------------------PHY_CONTROL:DO_DURATION[2]PHY_CONTROL:SPARE
    14----------------------------PHY_CONTROL:MULTI_REGIONPHY_CONTROL:SYNC_MODE
    15----------------------------PHY_CONTROL:DISABLE_SEQ_MATCH-
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------PHY_CONTROL:RD_DURATION_1[0]PHY_CONTROL:RD_DURATION_1[1]
    33----------------------------PHY_CONTROL:RD_DURATION_1[2]PHY_CONTROL:RD_DURATION_1[3]
    34----------------------------PHY_CONTROL:RD_DURATION_1[4]PHY_CONTROL:RD_DURATION_1[5]
    35----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[0]PHY_CONTROL:RD_CMD_OFFSET_1[1]
    36----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[2]PHY_CONTROL:RD_CMD_OFFSET_1[3]
    37----------------------------PHY_CONTROL:RD_CMD_OFFSET_1[4]PHY_CONTROL:RD_CMD_OFFSET_1[5]
    38----------------------------PHY_CONTROL:WR_DURATION_1[0]PHY_CONTROL:WR_DURATION_1[1]
    39----------------------------PHY_CONTROL:WR_DURATION_1[2]PHY_CONTROL:WR_DURATION_1[3]
    40----------------------------PHY_CONTROL:WR_DURATION_1[4]PHY_CONTROL:WR_DURATION_1[5]
    41----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[0]PHY_CONTROL:WR_CMD_OFFSET_1[1]
    42----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[2]PHY_CONTROL:WR_CMD_OFFSET_1[3]
    43----------------------------PHY_CONTROL:WR_CMD_OFFSET_1[4]PHY_CONTROL:WR_CMD_OFFSET_1[5]
    44----------------------------PHY_CONTROL:CLK_RATIO[0]PHY_CONTROL:CLK_RATIO[1]
    45----------------------------PHY_CONTROL:CLK_RATIO[2]PHY_CONTROL:DI_DURATION[0]
    46----------------------------PHY_CONTROL:DI_DURATION[1]PHY_CONTROL:DI_DURATION[2]
    47------------------------------
    48----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[0]PHY_CONTROL:FOUR_WINDOW_CLOCKS[1]
    49----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[2]PHY_CONTROL:FOUR_WINDOW_CLOCKS[3]
    50----------------------------PHY_CONTROL:FOUR_WINDOW_CLOCKS[4]PHY_CONTROL:FOUR_WINDOW_CLOCKS[5]
    51----------------------------PHY_CONTROL:EVENTS_DELAY[0]PHY_CONTROL:EVENTS_DELAY[1]
    52----------------------------PHY_CONTROL:EVENTS_DELAY[2]PHY_CONTROL:EVENTS_DELAY[3]
    53----------------------------PHY_CONTROL:EVENTS_DELAY[4]PHY_CONTROL:EVENTS_DELAY[5]
    54----------------------------PHY_CONTROL:AO_TOGGLE[0]PHY_CONTROL:AO_TOGGLE[1]
    55----------------------------PHY_CONTROL:AO_TOGGLE[2]PHY_CONTROL:AO_TOGGLE[3]
    56----------------------------PHY_CONTROL:CMD_OFFSET[0]PHY_CONTROL:CMD_OFFSET[1]
    57----------------------------PHY_CONTROL:CMD_OFFSET[2]PHY_CONTROL:CMD_OFFSET[3]
    58----------------------------PHY_CONTROL:CMD_OFFSET[4]PHY_CONTROL:CMD_OFFSET[5]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 35
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PHY_CONTROL:RD_DURATION_2[0]PHY_CONTROL:RD_DURATION_2[1]
    1----------------------------PHY_CONTROL:RD_DURATION_2[2]PHY_CONTROL:RD_DURATION_2[3]
    2----------------------------PHY_CONTROL:RD_DURATION_2[4]PHY_CONTROL:RD_DURATION_2[5]
    3----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[0]PHY_CONTROL:RD_CMD_OFFSET_2[1]
    4----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[2]PHY_CONTROL:RD_CMD_OFFSET_2[3]
    5----------------------------PHY_CONTROL:RD_CMD_OFFSET_2[4]PHY_CONTROL:RD_CMD_OFFSET_2[5]
    6----------------------------PHY_CONTROL:WR_DURATION_2[0]PHY_CONTROL:WR_DURATION_2[1]
    7----------------------------PHY_CONTROL:WR_DURATION_2[2]PHY_CONTROL:WR_DURATION_2[3]
    8----------------------------PHY_CONTROL:WR_DURATION_2[4]PHY_CONTROL:WR_DURATION_2[5]
    9----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[0]PHY_CONTROL:WR_CMD_OFFSET_2[1]
    10----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[2]PHY_CONTROL:WR_CMD_OFFSET_2[3]
    11----------------------------PHY_CONTROL:WR_CMD_OFFSET_2[4]PHY_CONTROL:WR_CMD_OFFSET_2[5]
    12----------------------------PHY_CONTROL:CO_DURATION[0]PHY_CONTROL:CO_DURATION[1]
    13----------------------------PHY_CONTROL:CO_DURATION[2]PHY_CONTROL:AO_WRLVL_EN[0]
    14----------------------------PHY_CONTROL:AO_WRLVL_EN[1]PHY_CONTROL:AO_WRLVL_EN[2]
    15----------------------------PHY_CONTROL:AO_WRLVL_EN[3]PHY_CONTROL:PHY_COUNT_ENABLE
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------PHY_CONTROL:RD_DURATION_3[0]PHY_CONTROL:RD_DURATION_3[1]
    33----------------------------PHY_CONTROL:RD_DURATION_3[2]PHY_CONTROL:RD_DURATION_3[3]
    34----------------------------PHY_CONTROL:RD_DURATION_3[4]PHY_CONTROL:RD_DURATION_3[5]
    35----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[0]PHY_CONTROL:RD_CMD_OFFSET_3[1]
    36----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[2]PHY_CONTROL:RD_CMD_OFFSET_3[3]
    37----------------------------PHY_CONTROL:RD_CMD_OFFSET_3[4]PHY_CONTROL:RD_CMD_OFFSET_3[5]
    38----------------------------PHY_CONTROL:WR_DURATION_3[0]PHY_CONTROL:WR_DURATION_3[1]
    39----------------------------PHY_CONTROL:WR_DURATION_3[2]PHY_CONTROL:WR_DURATION_3[3]
    40----------------------------PHY_CONTROL:WR_DURATION_3[4]PHY_CONTROL:WR_DURATION_3[5]
    41----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[0]PHY_CONTROL:WR_CMD_OFFSET_3[1]
    42----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[2]PHY_CONTROL:WR_CMD_OFFSET_3[3]
    43----------------------------PHY_CONTROL:WR_CMD_OFFSET_3[4]PHY_CONTROL:WR_CMD_OFFSET_3[5]
    44----------------------------PHY_CONTROL:DATA_CTL_A_NPHY_CONTROL:DATA_CTL_B_N
    45----------------------------PHY_CONTROL:DATA_CTL_C_NPHY_CONTROL:DATA_CTL_D_N
    46----------------------------PHY_CONTROL:BURST_MODE-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 36
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32----------------------------CMT_TOP:ENABLE.SYNC_BB[0]CMT_TOP:ENABLE.FREQ_BB0[0]
    33----------------------------CMT_TOP:ENABLE.FREQ_BB1[0]CMT_TOP:ENABLE.FREQ_BB2[0]
    34----------------------------CMT_TOP:ENABLE.FREQ_BB3[0]CMT_TOP:MUX.FREQ_BB0[0]
    35----------------------------CMT_TOP:MUX.FREQ_BB1[0]CMT_TOP:MUX.FREQ_BB2[0]
    36----------------------------CMT_TOP:MUX.FREQ_BB3[0]CMT_TOP:MUX.FREQREFCLK[0]
    37----------------------------CMT_TOP:MUX.FREQREFCLK[1]CMT_TOP:MUX.FREQREFCLK[2]
    38----------------------------CMT_TOP:BUF.SYNC_BB.DCMT_TOP:ENABLE.SYNC_BB_N
    39----------------------------CMT_TOP:BUF.SYNC_BB.UCMT_TOP:ENABLE.SYNC_BB[1]
    40----------------------------CMT_TOP:DRIVE.SYNC_BBCMT_TOP:MUX.MEMREFCLK[0]
    41----------------------------CMT_TOP:MUX.MEMREFCLK[1]CMT_TOP:ENABLE.FREQ_BB0[1]
    42----------------------------CMT_TOP:ENABLE.FREQ_BB0_N[0]CMT_TOP:ENABLE.FREQ_BB1[1]
    43----------------------------CMT_TOP:ENABLE.FREQ_BB1_N[0]CMT_TOP:ENABLE.FREQ_BB2[1]
    44----------------------------CMT_TOP:ENABLE.FREQ_BB2_N[0]CMT_TOP:ENABLE.FREQ_BB3[1]
    45----------------------------CMT_TOP:ENABLE.FREQ_BB3_N[0]CMT_TOP:BUF.FREQ_BB0.D[1]
    46----------------------------CMT_TOP:BUF.FREQ_BB0.U[0]CMT_TOP:BUF.FREQ_BB1.D[1]
    47----------------------------CMT_TOP:BUF.FREQ_BB1.U[0]CMT_TOP:BUF.FREQ_BB2.D[1]
    48----------------------------CMT_TOP:BUF.FREQ_BB2.U[0]CMT_TOP:BUF.FREQ_BB3.D[1]
    49----------------------------CMT_TOP:BUF.FREQ_BB3.U[0]CMT_TOP:ENABLE.FREQ_BB0[2]
    50----------------------------CMT_TOP:ENABLE.FREQ_BB0_N[1]CMT_TOP:ENABLE.FREQ_BB1[2]
    51----------------------------CMT_TOP:ENABLE.FREQ_BB1_N[1]CMT_TOP:ENABLE.FREQ_BB2[2]
    52----------------------------CMT_TOP:ENABLE.FREQ_BB2_N[1]CMT_TOP:ENABLE.FREQ_BB3[2]
    53----------------------------CMT_TOP:ENABLE.FREQ_BB3_N[1]CMT_TOP:BUF.FREQ_BB0.U[1]
    54----------------------------CMT_TOP:BUF.FREQ_BB0.D[0]CMT_TOP:BUF.FREQ_BB1.U[1]
    55----------------------------CMT_TOP:BUF.FREQ_BB1.D[0]CMT_TOP:BUF.FREQ_BB2.U[1]
    56----------------------------CMT_TOP:BUF.FREQ_BB2.D[0]CMT_TOP:BUF.FREQ_BB3.U[1]
    57----------------------------CMT_TOP:BUF.FREQ_BB3.D[0]CMT_TOP:MUX.MEMREFCLK[2]
    58----------------------------CMT_TOP:MUX.SYNCIN[0]CMT_TOP:MUX.SYNCIN[1]
    59----------------------------CMT_TOP:MUX.SYNCIN[2]CMT_TOP:MUX.FREQ_BB0[1]
    60----------------------------CMT_TOP:MUX.FREQ_BB0[2]CMT_TOP:MUX.FREQ_BB1[1]
    61----------------------------CMT_TOP:MUX.FREQ_BB1[2]CMT_TOP:MUX.FREQ_BB2[1]
    62----------------------------CMT_TOP:MUX.FREQ_BB2[2]CMT_TOP:MUX.FREQ_BB3[1]
    63----------------------------CMT_TOP:MUX.FREQ_BB3[2]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 37
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP00[0]PLL:DRP00[1]
    1----------------------------PLL:DRP00[2]PLL:DRP00[3]
    2----------------------------PLL:DRP00[4]PLL:DRP00[5]
    3----------------------------PLL:DRP00[6]
    PLL:IN_DLY_MX_CVDD[0]    		PLL:DRP00[7]
    PLL:IN_DLY_MX_CVDD[1]
    4----------------------------PLL:DRP00[8]
    PLL:IN_DLY_MX_CVDD[2]    		PLL:DRP00[9]
    PLL:IN_DLY_MX_CVDD[3]
    5----------------------------PLL:DRP00[10]
    PLL:IN_DLY_MX_CVDD[4]    		PLL:DRP00[11]
    PLL:IN_DLY_MX_CVDD[5]
    6----------------------------PLL:DRP00[12]
    PLL:HROW_DLY_SET[0]    		PLL:DRP00[13]
    PLL:HROW_DLY_SET[1]
    7----------------------------PLL:DRP00[14]
    PLL:HROW_DLY_SET[2]    		PLL:DRP00[15]
    PLL:MUX.CLKIN2[0]
    8----------------------------PLL:DRP01[0]
    PLL:MUX.CLKIN2[1]    		PLL:DRP01[1]
    PLL:MUX.CLKIN2[2]
    9----------------------------PLL:DRP01[2]
    PLL:MUX.CLKIN1[0]    		PLL:DRP01[3]
    PLL:MUX.CLKIN1[1]
    10----------------------------PLL:DRP01[4]
    PLL:MUX.CLKIN1[2]    		PLL:DRP01[5]
    PLL:MUX.CLKFBIN[0]
    11----------------------------PLL:DRP01[6]
    PLL:MUX.CLKFBIN[1]    		PLL:DRP01[7]
    PLL:MUX.CLKFBIN[2]
    12----------------------------PLL:BUF.CLKOUT0_FREQ_BB
    PLL:DRP01[8]    		PLL:BUF.CLKOUT1_FREQ_BB
    PLL:DRP01[9]
    13----------------------------PLL:BUF.CLKOUT2_FREQ_BB
    PLL:DRP01[10]    		PLL:BUF.CLKOUT3_FREQ_BB
    PLL:DRP01[11]
    14----------------------------PLL:DRP01[12]PLL:DRP01[13]
    15----------------------------PLL:DRP01[14]PLL:DRP01[15]
    16----------------------------PLL:DRP02[0]
    PLL:SYNTH_CLK_DIV[0]    		PLL:DRP02[1]
    PLL:SYNTH_CLK_DIV[1]
    17----------------------------PLL:DRP02[2]PLL:DRP02[3]
    18----------------------------PLL:DRP02[4]PLL:DRP02[5]
    19----------------------------PLL:DRP02[6]PLL:DRP02[7]
    20----------------------------PLL:DRP02[8]PLL:DRP02[9]
    21----------------------------PLL:DRP02[10]PLL:DRP02[11]
    22----------------------------PLL:DRP02[12]PLL:DRP02[13]
    23----------------------------PLL:DRP02[14]PLL:DRP02[15]
    24----------------------------PLL:DRP03[0]
    PLL:SKEW_FLOP_INV[0]    		PLL:DRP03[1]
    PLL:SKEW_FLOP_INV[1]
    25----------------------------PLL:DRP03[2]
    PLL:SKEW_FLOP_INV[2]    		PLL:DRP03[3]
    PLL:SKEW_FLOP_INV[3]
    26----------------------------PLL:DRP03[4]PLL:DRP03[5]
    27----------------------------PLL:DRP03[6]PLL:DRP03[7]
    28----------------------------PLL:DRP03[8]PLL:DRP03[9]
    29----------------------------PLL:DRP03[10]PLL:DRP03[11]
    30----------------------------PLL:DRP03[12]PLL:DRP03[13]
    31----------------------------PLL:DRP03[14]PLL:DRP03[15]
    32----------------------------PLL:DRP04[0]PLL:DRP04[1]
    33----------------------------PLL:DRP04[2]PLL:DRP04[3]
    34----------------------------PLL:DRP04[4]PLL:DRP04[5]
    35----------------------------PLL:DRP04[6]PLL:DRP04[7]
    36----------------------------PLL:DRP04[8]PLL:DRP04[9]
    37----------------------------PLL:DRP04[10]PLL:DRP04[11]
    38----------------------------PLL:DRP04[12]PLL:DRP04[13]
    39----------------------------PLL:DRP04[14]
    PLL:TMUX_MUX_SEL[0]    		PLL:DRP04[15]
    PLL:TMUX_MUX_SEL[1]
    40----------------------------PLL:DRP05[0]PLL:DRP05[1]
    41----------------------------PLL:DRP05[2]
    PLL:IN_DLY_EN    		PLL:DIRECT_PATH_CNTRL
    PLL:DRP05[3]
    42----------------------------PLL:DRP05[4]
    PLL:IN_DLY_MX_DVDD[0]    		PLL:DRP05[5]
    PLL:IN_DLY_MX_DVDD[1]
    43----------------------------PLL:DRP05[6]
    PLL:IN_DLY_MX_DVDD[2]    		PLL:DRP05[7]
    PLL:IN_DLY_MX_DVDD[3]
    44----------------------------PLL:DRP05[8]
    PLL:IN_DLY_MX_DVDD[4]    		PLL:DRP05[9]
    PLL:IN_DLY_MX_DVDD[5]
    45----------------------------PLL:DRP05[10]
    PLL:IN_DLY_SET[0]    		PLL:DRP05[11]
    PLL:IN_DLY_SET[1]
    46----------------------------PLL:DRP05[12]
    PLL:IN_DLY_SET[2]    		PLL:DRP05[13]
    PLL:IN_DLY_SET[3]
    47----------------------------PLL:DRP05[14]
    PLL:IN_DLY_SET[4]    		PLL:DRP05[15]
    PLL:IN_DLY_SET[5]
    48----------------------------PLL:CLKOUT5_LT[0]
    PLL:DRP06[0]    		PLL:CLKOUT5_LT[1]
    PLL:DRP06[1]
    49----------------------------PLL:CLKOUT5_LT[2]
    PLL:DRP06[2]    		PLL:CLKOUT5_LT[3]
    PLL:DRP06[3]
    50----------------------------PLL:CLKOUT5_LT[4]
    PLL:DRP06[4]    		PLL:CLKOUT5_LT[5]
    PLL:DRP06[5]
    51----------------------------PLL:CLKOUT5_HT[0]
    PLL:DRP06[6]    		PLL:CLKOUT5_HT[1]
    PLL:DRP06[7]
    52----------------------------PLL:CLKOUT5_HT[2]
    PLL:DRP06[8]    		PLL:CLKOUT5_HT[3]
    PLL:DRP06[9]
    53----------------------------PLL:CLKOUT5_HT[4]
    PLL:DRP06[10]    		PLL:CLKOUT5_HT[5]
    PLL:DRP06[11]
    54----------------------------PLL:CLKOUT5_EN
    PLL:DRP06[12]    		PLL:CLKOUT5_PM[0]
    PLL:DRP06[13]
    55----------------------------PLL:CLKOUT5_PM[1]
    PLL:DRP06[14]    		PLL:CLKOUT5_PM[2]
    PLL:DRP06[15]
    56----------------------------PLL:CLKOUT5_DT[0]
    PLL:DRP07[0]    		PLL:CLKOUT5_DT[1]
    PLL:DRP07[1]
    57----------------------------PLL:CLKOUT5_DT[2]
    PLL:DRP07[2]    		PLL:CLKOUT5_DT[3]
    PLL:DRP07[3]
    58----------------------------PLL:CLKOUT5_DT[4]
    PLL:DRP07[4]    		PLL:CLKOUT5_DT[5]
    PLL:DRP07[5]
    59----------------------------PLL:CLKOUT5_NOCOUNT
    PLL:DRP07[6]    		PLL:CLKOUT5_EDGE
    PLL:DRP07[7]
    60----------------------------PLL:CLKOUT5_MX[0]
    PLL:DRP07[8]    		PLL:CLKOUT5_MX[1]
    PLL:DRP07[9]
    61----------------------------PLL:DRP07[10]PLL:DRP07[11]
    62----------------------------PLL:DRP07[12]PLL:DRP07[13]
    63----------------------------PLL:DRP07[14]PLL:DRP07[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 38
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:CLKOUT0_LT[0]
    PLL:DRP08[0]    		PLL:CLKOUT0_LT[1]
    PLL:DRP08[1]
    1----------------------------PLL:CLKOUT0_LT[2]
    PLL:DRP08[2]    		PLL:CLKOUT0_LT[3]
    PLL:DRP08[3]
    2----------------------------PLL:CLKOUT0_LT[4]
    PLL:DRP08[4]    		PLL:CLKOUT0_LT[5]
    PLL:DRP08[5]
    3----------------------------PLL:CLKOUT0_HT[0]
    PLL:DRP08[6]    		PLL:CLKOUT0_HT[1]
    PLL:DRP08[7]
    4----------------------------PLL:CLKOUT0_HT[2]
    PLL:DRP08[8]    		PLL:CLKOUT0_HT[3]
    PLL:DRP08[9]
    5----------------------------PLL:CLKOUT0_HT[4]
    PLL:DRP08[10]    		PLL:CLKOUT0_HT[5]
    PLL:DRP08[11]
    6----------------------------PLL:CLKOUT0_EN
    PLL:DRP08[12]    		PLL:CLKOUT0_PM[0]
    PLL:DRP08[13]
    7----------------------------PLL:CLKOUT0_PM[1]
    PLL:DRP08[14]    		PLL:CLKOUT0_PM[2]
    PLL:DRP08[15]
    8----------------------------PLL:CLKOUT0_DT[0]
    PLL:DRP09[0]    		PLL:CLKOUT0_DT[1]
    PLL:DRP09[1]
    9----------------------------PLL:CLKOUT0_DT[2]
    PLL:DRP09[2]    		PLL:CLKOUT0_DT[3]
    PLL:DRP09[3]
    10----------------------------PLL:CLKOUT0_DT[4]
    PLL:DRP09[4]    		PLL:CLKOUT0_DT[5]
    PLL:DRP09[5]
    11----------------------------PLL:CLKOUT0_NOCOUNT
    PLL:DRP09[6]    		PLL:CLKOUT0_EDGE
    PLL:DRP09[7]
    12----------------------------PLL:CLKOUT0_MX[0]
    PLL:DRP09[8]    		PLL:CLKOUT0_MX[1]
    PLL:DRP09[9]
    13----------------------------PLL:DRP09[10]PLL:DRP09[11]
    14----------------------------PLL:DRP09[12]PLL:DRP09[13]
    15----------------------------PLL:DRP09[14]PLL:DRP09[15]
    16----------------------------PLL:CLKOUT1_LT[0]
    PLL:DRP0A[0]    		PLL:CLKOUT1_LT[1]
    PLL:DRP0A[1]
    17----------------------------PLL:CLKOUT1_LT[2]
    PLL:DRP0A[2]    		PLL:CLKOUT1_LT[3]
    PLL:DRP0A[3]
    18----------------------------PLL:CLKOUT1_LT[4]
    PLL:DRP0A[4]    		PLL:CLKOUT1_LT[5]
    PLL:DRP0A[5]
    19----------------------------PLL:CLKOUT1_HT[0]
    PLL:DRP0A[6]    		PLL:CLKOUT1_HT[1]
    PLL:DRP0A[7]
    20----------------------------PLL:CLKOUT1_HT[2]
    PLL:DRP0A[8]    		PLL:CLKOUT1_HT[3]
    PLL:DRP0A[9]
    21----------------------------PLL:CLKOUT1_HT[4]
    PLL:DRP0A[10]    		PLL:CLKOUT1_HT[5]
    PLL:DRP0A[11]
    22----------------------------PLL:CLKOUT1_EN
    PLL:DRP0A[12]    		PLL:CLKOUT1_PM[0]
    PLL:DRP0A[13]
    23----------------------------PLL:CLKOUT1_PM[1]
    PLL:DRP0A[14]    		PLL:CLKOUT1_PM[2]
    PLL:DRP0A[15]
    24----------------------------PLL:CLKOUT1_DT[0]
    PLL:DRP0B[0]    		PLL:CLKOUT1_DT[1]
    PLL:DRP0B[1]
    25----------------------------PLL:CLKOUT1_DT[2]
    PLL:DRP0B[2]    		PLL:CLKOUT1_DT[3]
    PLL:DRP0B[3]
    26----------------------------PLL:CLKOUT1_DT[4]
    PLL:DRP0B[4]    		PLL:CLKOUT1_DT[5]
    PLL:DRP0B[5]
    27----------------------------PLL:CLKOUT1_NOCOUNT
    PLL:DRP0B[6]    		PLL:CLKOUT1_EDGE
    PLL:DRP0B[7]
    28----------------------------PLL:CLKOUT1_MX[0]
    PLL:DRP0B[8]    		PLL:CLKOUT1_MX[1]
    PLL:DRP0B[9]
    29----------------------------PLL:DRP0B[10]PLL:DRP0B[11]
    30----------------------------PLL:DRP0B[12]PLL:DRP0B[13]
    31----------------------------PLL:DRP0B[14]PLL:DRP0B[15]
    32----------------------------PLL:CLKOUT2_LT[0]
    PLL:DRP0C[0]    		PLL:CLKOUT2_LT[1]
    PLL:DRP0C[1]
    33----------------------------PLL:CLKOUT2_LT[2]
    PLL:DRP0C[2]    		PLL:CLKOUT2_LT[3]
    PLL:DRP0C[3]
    34----------------------------PLL:CLKOUT2_LT[4]
    PLL:DRP0C[4]    		PLL:CLKOUT2_LT[5]
    PLL:DRP0C[5]
    35----------------------------PLL:CLKOUT2_HT[0]
    PLL:DRP0C[6]    		PLL:CLKOUT2_HT[1]
    PLL:DRP0C[7]
    36----------------------------PLL:CLKOUT2_HT[2]
    PLL:DRP0C[8]    		PLL:CLKOUT2_HT[3]
    PLL:DRP0C[9]
    37----------------------------PLL:CLKOUT2_HT[4]
    PLL:DRP0C[10]    		PLL:CLKOUT2_HT[5]
    PLL:DRP0C[11]
    38----------------------------PLL:CLKOUT2_EN
    PLL:DRP0C[12]    		PLL:CLKOUT2_PM[0]
    PLL:DRP0C[13]
    39----------------------------PLL:CLKOUT2_PM[1]
    PLL:DRP0C[14]    		PLL:CLKOUT2_PM[2]
    PLL:DRP0C[15]
    40----------------------------PLL:CLKOUT2_DT[0]
    PLL:DRP0D[0]    		PLL:CLKOUT2_DT[1]
    PLL:DRP0D[1]
    41----------------------------PLL:CLKOUT2_DT[2]
    PLL:DRP0D[2]    		PLL:CLKOUT2_DT[3]
    PLL:DRP0D[3]
    42----------------------------PLL:CLKOUT2_DT[4]
    PLL:DRP0D[4]    		PLL:CLKOUT2_DT[5]
    PLL:DRP0D[5]
    43----------------------------PLL:CLKOUT2_NOCOUNT
    PLL:DRP0D[6]    		PLL:CLKOUT2_EDGE
    PLL:DRP0D[7]
    44----------------------------PLL:CLKOUT2_MX[0]
    PLL:DRP0D[8]    		PLL:CLKOUT2_MX[1]
    PLL:DRP0D[9]
    45----------------------------PLL:DRP0D[10]PLL:DRP0D[11]
    46----------------------------PLL:DRP0D[12]PLL:DRP0D[13]
    47----------------------------PLL:DRP0D[14]PLL:DRP0D[15]
    48----------------------------PLL:CLKOUT3_LT[0]
    PLL:DRP0E[0]    		PLL:CLKOUT3_LT[1]
    PLL:DRP0E[1]
    49----------------------------PLL:CLKOUT3_LT[2]
    PLL:DRP0E[2]    		PLL:CLKOUT3_LT[3]
    PLL:DRP0E[3]
    50----------------------------PLL:CLKOUT3_LT[4]
    PLL:DRP0E[4]    		PLL:CLKOUT3_LT[5]
    PLL:DRP0E[5]
    51----------------------------PLL:CLKOUT3_HT[0]
    PLL:DRP0E[6]    		PLL:CLKOUT3_HT[1]
    PLL:DRP0E[7]
    52----------------------------PLL:CLKOUT3_HT[2]
    PLL:DRP0E[8]    		PLL:CLKOUT3_HT[3]
    PLL:DRP0E[9]
    53----------------------------PLL:CLKOUT3_HT[4]
    PLL:DRP0E[10]    		PLL:CLKOUT3_HT[5]
    PLL:DRP0E[11]
    54----------------------------PLL:CLKOUT3_EN
    PLL:DRP0E[12]    		PLL:CLKOUT3_PM[0]
    PLL:DRP0E[13]
    55----------------------------PLL:CLKOUT3_PM[1]
    PLL:DRP0E[14]    		PLL:CLKOUT3_PM[2]
    PLL:DRP0E[15]
    56----------------------------PLL:CLKOUT3_DT[0]
    PLL:DRP0F[0]    		PLL:CLKOUT3_DT[1]
    PLL:DRP0F[1]
    57----------------------------PLL:CLKOUT3_DT[2]
    PLL:DRP0F[2]    		PLL:CLKOUT3_DT[3]
    PLL:DRP0F[3]
    58----------------------------PLL:CLKOUT3_DT[4]
    PLL:DRP0F[4]    		PLL:CLKOUT3_DT[5]
    PLL:DRP0F[5]
    59----------------------------PLL:CLKOUT3_NOCOUNT
    PLL:DRP0F[6]    		PLL:CLKOUT3_EDGE
    PLL:DRP0F[7]
    60----------------------------PLL:CLKOUT3_MX[0]
    PLL:DRP0F[8]    		PLL:CLKOUT3_MX[1]
    PLL:DRP0F[9]
    61----------------------------PLL:DRP0F[10]PLL:DRP0F[11]
    62----------------------------PLL:DRP0F[12]PLL:DRP0F[13]
    63----------------------------PLL:DRP0F[14]PLL:DRP0F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 39
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:CLKOUT4_LT[0]
    PLL:DRP10[0]    		PLL:CLKOUT4_LT[1]
    PLL:DRP10[1]
    1----------------------------PLL:CLKOUT4_LT[2]
    PLL:DRP10[2]    		PLL:CLKOUT4_LT[3]
    PLL:DRP10[3]
    2----------------------------PLL:CLKOUT4_LT[4]
    PLL:DRP10[4]    		PLL:CLKOUT4_LT[5]
    PLL:DRP10[5]
    3----------------------------PLL:CLKOUT4_HT[0]
    PLL:DRP10[6]    		PLL:CLKOUT4_HT[1]
    PLL:DRP10[7]
    4----------------------------PLL:CLKOUT4_HT[2]
    PLL:DRP10[8]    		PLL:CLKOUT4_HT[3]
    PLL:DRP10[9]
    5----------------------------PLL:CLKOUT4_HT[4]
    PLL:DRP10[10]    		PLL:CLKOUT4_HT[5]
    PLL:DRP10[11]
    6----------------------------PLL:CLKOUT4_EN
    PLL:DRP10[12]    		PLL:CLKOUT4_PM[0]
    PLL:DRP10[13]
    7----------------------------PLL:CLKOUT4_PM[1]
    PLL:DRP10[14]    		PLL:CLKOUT4_PM[2]
    PLL:DRP10[15]
    8----------------------------PLL:CLKOUT4_DT[0]
    PLL:DRP11[0]    		PLL:CLKOUT4_DT[1]
    PLL:DRP11[1]
    9----------------------------PLL:CLKOUT4_DT[2]
    PLL:DRP11[2]    		PLL:CLKOUT4_DT[3]
    PLL:DRP11[3]
    10----------------------------PLL:CLKOUT4_DT[4]
    PLL:DRP11[4]    		PLL:CLKOUT4_DT[5]
    PLL:DRP11[5]
    11----------------------------PLL:CLKOUT4_NOCOUNT
    PLL:DRP11[6]    		PLL:CLKOUT4_EDGE
    PLL:DRP11[7]
    12----------------------------PLL:CLKOUT4_MX[0]
    PLL:DRP11[8]    		PLL:CLKOUT4_MX[1]
    PLL:DRP11[9]
    13----------------------------PLL:DRP11[10]PLL:DRP11[11]
    14----------------------------PLL:DRP11[12]PLL:DRP11[13]
    15----------------------------PLL:DRP11[14]PLL:DRP11[15]
    16----------------------------PLL:DRP12[0]PLL:DRP12[1]
    17----------------------------PLL:DRP12[2]PLL:DRP12[3]
    18----------------------------PLL:DRP12[4]PLL:DRP12[5]
    19----------------------------PLL:DRP12[6]PLL:DRP12[7]
    20----------------------------PLL:DRP12[8]PLL:DRP12[9]
    21----------------------------PLL:DRP12[10]PLL:DRP12[11]
    22----------------------------PLL:DRP12[12]PLL:DRP12[13]
    23----------------------------PLL:DRP12[14]PLL:DRP12[15]
    24----------------------------PLL:DRP13[0]PLL:DRP13[1]
    25----------------------------PLL:DRP13[2]PLL:DRP13[3]
    26----------------------------PLL:DRP13[4]PLL:DRP13[5]
    27----------------------------PLL:DRP13[6]PLL:DRP13[7]
    28----------------------------PLL:DRP13[8]PLL:DRP13[9]
    29----------------------------PLL:DRP13[10]PLL:DRP13[11]
    30----------------------------PLL:DRP13[12]PLL:DRP13[13]
    31----------------------------PLL:DRP13[14]PLL:DRP13[15]
    32----------------------------PLL:CLKFBOUT_LT[0]
    PLL:DRP14[0]    		PLL:CLKFBOUT_LT[1]
    PLL:DRP14[1]
    33----------------------------PLL:CLKFBOUT_LT[2]
    PLL:DRP14[2]    		PLL:CLKFBOUT_LT[3]
    PLL:DRP14[3]
    34----------------------------PLL:CLKFBOUT_LT[4]
    PLL:DRP14[4]    		PLL:CLKFBOUT_LT[5]
    PLL:DRP14[5]
    35----------------------------PLL:CLKFBOUT_HT[0]
    PLL:DRP14[6]    		PLL:CLKFBOUT_HT[1]
    PLL:DRP14[7]
    36----------------------------PLL:CLKFBOUT_HT[2]
    PLL:DRP14[8]    		PLL:CLKFBOUT_HT[3]
    PLL:DRP14[9]
    37----------------------------PLL:CLKFBOUT_HT[4]
    PLL:DRP14[10]    		PLL:CLKFBOUT_HT[5]
    PLL:DRP14[11]
    38----------------------------PLL:CLKFBOUT_EN
    PLL:DRP14[12]    		PLL:CLKFBOUT_PM[0]
    PLL:DRP14[13]
    39----------------------------PLL:CLKFBOUT_PM[1]
    PLL:DRP14[14]    		PLL:CLKFBOUT_PM[2]
    PLL:DRP14[15]
    40----------------------------PLL:CLKFBOUT_DT[0]
    PLL:DRP15[0]    		PLL:CLKFBOUT_DT[1]
    PLL:DRP15[1]
    41----------------------------PLL:CLKFBOUT_DT[2]
    PLL:DRP15[2]    		PLL:CLKFBOUT_DT[3]
    PLL:DRP15[3]
    42----------------------------PLL:CLKFBOUT_DT[4]
    PLL:DRP15[4]    		PLL:CLKFBOUT_DT[5]
    PLL:DRP15[5]
    43----------------------------PLL:CLKFBOUT_NOCOUNT
    PLL:DRP15[6]    		PLL:CLKFBOUT_EDGE
    PLL:DRP15[7]
    44----------------------------PLL:CLKFBOUT_MX[0]
    PLL:DRP15[8]    		PLL:CLKFBOUT_MX[1]
    PLL:DRP15[9]
    45----------------------------PLL:DRP15[10]PLL:DRP15[11]
    46----------------------------PLL:DRP15[12]PLL:DRP15[13]
    47----------------------------PLL:DRP15[14]PLL:DRP15[15]
    48----------------------------PLL:DIVCLK_LT[0]
    PLL:DRP16[0]    		PLL:DIVCLK_LT[1]
    PLL:DRP16[1]
    49----------------------------PLL:DIVCLK_LT[2]
    PLL:DRP16[2]    		PLL:DIVCLK_LT[3]
    PLL:DRP16[3]
    50----------------------------PLL:DIVCLK_LT[4]
    PLL:DRP16[4]    		PLL:DIVCLK_LT[5]
    PLL:DRP16[5]
    51----------------------------PLL:DIVCLK_HT[0]
    PLL:DRP16[6]    		PLL:DIVCLK_HT[1]
    PLL:DRP16[7]
    52----------------------------PLL:DIVCLK_HT[2]
    PLL:DRP16[8]    		PLL:DIVCLK_HT[3]
    PLL:DRP16[9]
    53----------------------------PLL:DIVCLK_HT[4]
    PLL:DRP16[10]    		PLL:DIVCLK_HT[5]
    PLL:DRP16[11]
    54----------------------------PLL:DIVCLK_NOCOUNT
    PLL:DRP16[12]    		PLL:DIVCLK_EDGE
    PLL:DRP16[13]
    55----------------------------PLL:DRP16[14]PLL:DRP16[15]
    56----------------------------PLL:CLKFBIN_LT[0]
    PLL:DRP17[0]    		PLL:CLKFBIN_LT[1]
    PLL:DRP17[1]
    57----------------------------PLL:CLKFBIN_LT[2]
    PLL:DRP17[2]    		PLL:CLKFBIN_LT[3]
    PLL:DRP17[3]
    58----------------------------PLL:CLKFBIN_LT[4]
    PLL:DRP17[4]    		PLL:CLKFBIN_LT[5]
    PLL:DRP17[5]
    59----------------------------PLL:CLKFBIN_HT[0]
    PLL:DRP17[6]    		PLL:CLKFBIN_HT[1]
    PLL:DRP17[7]
    60----------------------------PLL:CLKFBIN_HT[2]
    PLL:DRP17[8]    		PLL:CLKFBIN_HT[3]
    PLL:DRP17[9]
    61----------------------------PLL:CLKFBIN_HT[4]
    PLL:DRP17[10]    		PLL:CLKFBIN_HT[5]
    PLL:DRP17[11]
    62----------------------------PLL:CLKFBIN_NOCOUNT
    PLL:DRP17[12]    		PLL:CLKFBIN_EDGE
    PLL:DRP17[13]
    63----------------------------PLL:DRP17[14]PLL:DRP17[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 40
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP18[0]
    PLL:LOCK_CNT[0]    		PLL:DRP18[1]
    PLL:LOCK_CNT[1]
    1----------------------------PLL:DRP18[2]
    PLL:LOCK_CNT[2]    		PLL:DRP18[3]
    PLL:LOCK_CNT[3]
    2----------------------------PLL:DRP18[4]
    PLL:LOCK_CNT[4]    		PLL:DRP18[5]
    PLL:LOCK_CNT[5]
    3----------------------------PLL:DRP18[6]
    PLL:LOCK_CNT[6]    		PLL:DRP18[7]
    PLL:LOCK_CNT[7]
    4----------------------------PLL:DRP18[8]
    PLL:LOCK_CNT[8]    		PLL:DRP18[9]
    PLL:LOCK_CNT[9]
    5----------------------------PLL:DRP18[10]PLL:DRP18[11]
    6----------------------------PLL:DRP18[12]PLL:DRP18[13]
    7----------------------------PLL:DRP18[14]PLL:DRP18[15]
    8----------------------------PLL:DRP19[0]
    PLL:UNLOCK_CNT[0]    		PLL:DRP19[1]
    PLL:UNLOCK_CNT[1]
    9----------------------------PLL:DRP19[2]
    PLL:UNLOCK_CNT[2]    		PLL:DRP19[3]
    PLL:UNLOCK_CNT[3]
    10----------------------------PLL:DRP19[4]
    PLL:UNLOCK_CNT[4]    		PLL:DRP19[5]
    PLL:UNLOCK_CNT[5]
    11----------------------------PLL:DRP19[6]
    PLL:UNLOCK_CNT[6]    		PLL:DRP19[7]
    PLL:UNLOCK_CNT[7]
    12----------------------------PLL:DRP19[8]
    PLL:UNLOCK_CNT[8]    		PLL:DRP19[9]
    PLL:UNLOCK_CNT[9]
    13----------------------------PLL:DRP19[10]
    PLL:LOCK_FB_DLY[0]    		PLL:DRP19[11]
    PLL:LOCK_FB_DLY[1]
    14----------------------------PLL:DRP19[12]
    PLL:LOCK_FB_DLY[2]    		PLL:DRP19[13]
    PLL:LOCK_FB_DLY[3]
    15----------------------------PLL:DRP19[14]
    PLL:LOCK_FB_DLY[4]    		PLL:DRP19[15]
    16----------------------------PLL:DRP1A[0]
    PLL:LOCK_SAT_HIGH[0]    		PLL:DRP1A[1]
    PLL:LOCK_SAT_HIGH[1]
    17----------------------------PLL:DRP1A[2]
    PLL:LOCK_SAT_HIGH[2]    		PLL:DRP1A[3]
    PLL:LOCK_SAT_HIGH[3]
    18----------------------------PLL:DRP1A[4]
    PLL:LOCK_SAT_HIGH[4]    		PLL:DRP1A[5]
    PLL:LOCK_SAT_HIGH[5]
    19----------------------------PLL:DRP1A[6]
    PLL:LOCK_SAT_HIGH[6]    		PLL:DRP1A[7]
    PLL:LOCK_SAT_HIGH[7]
    20----------------------------PLL:DRP1A[8]
    PLL:LOCK_SAT_HIGH[8]    		PLL:DRP1A[9]
    PLL:LOCK_SAT_HIGH[9]
    21----------------------------PLL:DRP1A[10]
    PLL:LOCK_REF_DLY[0]    		PLL:DRP1A[11]
    PLL:LOCK_REF_DLY[1]
    22----------------------------PLL:DRP1A[12]
    PLL:LOCK_REF_DLY[2]    		PLL:DRP1A[13]
    PLL:LOCK_REF_DLY[3]
    23----------------------------PLL:DRP1A[14]
    PLL:LOCK_REF_DLY[4]    		PLL:DRP1A[15]
    PLL:FREQ_COMP[0]
    24----------------------------PLL:DRP1B[0]
    PLL:FREQ_COMP[1]    		PLL:DRP1B[1]
    25----------------------------PLL:DRP1B[2]PLL:DRP1B[3]
    26----------------------------PLL:DRP1B[4]PLL:DRP1B[5]
    27----------------------------PLL:DRP1B[6]PLL:DRP1B[7]
    28----------------------------PLL:DRP1B[8]PLL:DRP1B[9]
    29----------------------------PLL:DRP1B[10]PLL:DRP1B[11]
    30----------------------------PLL:DRP1B[12]PLL:DRP1B[13]
    31----------------------------PLL:DRP1B[14]PLL:DRP1B[15]
    32----------------------------PLL:DRP1C[0]
    PLL:SPARE_DIGITAL[0]    		PLL:DRP1C[1]
    PLL:SPARE_DIGITAL[1]
    33----------------------------PLL:DRP1C[2]
    PLL:SPARE_DIGITAL[2]    		PLL:DRP1C[3]
    PLL:SPARE_DIGITAL[3]
    34----------------------------PLL:DRP1C[4]
    PLL:SPARE_DIGITAL[4]    		PLL:DRP1C[5]
    35----------------------------PLL:DRP1C[6]PLL:DRP1C[7]
    36----------------------------PLL:DRP1C[8]PLL:DRP1C[9]
    37----------------------------PLL:DRP1C[10]PLL:DRP1C[11]
    38----------------------------PLL:DRP1C[12]PLL:DRP1C[13]
    39----------------------------PLL:DRP1C[14]PLL:DRP1C[15]
    40----------------------------PLL:DRP1D[0]PLL:DRP1D[1]
    41----------------------------PLL:DRP1D[2]PLL:DRP1D[3]
    42----------------------------PLL:DRP1D[4]
    PLL:PFD[0]    		PLL:DRP1D[5]
    PLL:PFD[1]
    43----------------------------PLL:DRP1D[6]
    PLL:PFD[2]    		PLL:DRP1D[7]
    PLL:PFD[3]
    44----------------------------PLL:DRP1D[8]
    PLL:PFD[4]    		PLL:DRP1D[9]
    PLL:PFD[5]
    45----------------------------PLL:DRP1D[10]
    PLL:PFD[6]    		PLL:DRP1D[11]
    46----------------------------PLL:DRP1D[12]PLL:DRP1D[13]
    47----------------------------PLL:DRP1D[14]PLL:DRP1D[15]
    48----------------------------PLL:DRP1E[0]PLL:DRP1E[1]
    49----------------------------PLL:DRP1E[2]PLL:DRP1E[3]
    50----------------------------PLL:DRP1E[4]PLL:DRP1E[5]
    51----------------------------PLL:DRP1E[6]PLL:DRP1E[7]
    52----------------------------PLL:DRP1E[8]PLL:DRP1E[9]
    53----------------------------PLL:DRP1E[10]PLL:DRP1E[11]
    54----------------------------PLL:DRP1E[12]PLL:DRP1E[13]
    55----------------------------PLL:DRP1E[14]
    PLL:SEL_LV_NMOS    		PLL:DRP1E[15]
    PLL:SUP_SEL_DREG
    56----------------------------PLL:DRP1F[0]
    PLL:DVDD_VBG_SEL[0]    		PLL:DRP1F[1]
    PLL:DVDD_VBG_SEL[1]
    57----------------------------PLL:DRP1F[2]
    PLL:DVDD_VBG_SEL[2]    		PLL:DRP1F[3]
    PLL:DVDD_VBG_SEL[3]
    58----------------------------PLL:DRP1F[4]
    PLL:DVDD_VBG_PD[0]    		PLL:DRP1F[5]
    PLL:DVDD_VBG_PD[1]
    59----------------------------PLL:DRP1F[6]
    PLL:DVDD_VBG_PD[2]    		PLL:DRP1F[7]
    PLL:DVDD_COMP_SET[0]
    60----------------------------PLL:DRP1F[8]
    PLL:DVDD_COMP_SET[1]    		PLL:DRP1F[9]
    PLL:DVDD_COMP_SET[2]
    61----------------------------PLL:DRP1F[10]PLL:DRP1F[11]
    62----------------------------PLL:DRP1F[12]PLL:DRP1F[13]
    63----------------------------PLL:DRP1F[14]PLL:DRP1F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 41
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP20[0]PLL:DRP20[1]
    1----------------------------PLL:DRP20[2]PLL:DRP20[3]
    2----------------------------PLL:DRP20[4]PLL:DRP20[5]
    3----------------------------PLL:DRP20[6]PLL:DRP20[7]
    4----------------------------PLL:DRP20[8]PLL:DRP20[9]
    5----------------------------PLL:DRP20[10]PLL:DRP20[11]
    6----------------------------PLL:DRP20[12]PLL:DRP20[13]
    7----------------------------PLL:DRP20[14]PLL:DRP20[15]
    8----------------------------PLL:DRP21[0]PLL:DRP21[1]
    9----------------------------PLL:DRP21[2]PLL:DRP21[3]
    10----------------------------PLL:DRP21[4]PLL:DRP21[5]
    11----------------------------PLL:DRP21[6]PLL:DRP21[7]
    12----------------------------PLL:DRP21[8]PLL:DRP21[9]
    13----------------------------PLL:DRP21[10]PLL:DRP21[11]
    14----------------------------PLL:DRP21[12]PLL:DRP21[13]
    15----------------------------PLL:DRP21[14]PLL:DRP21[15]
    16----------------------------PLL:DRP22[0]
    PLL:EN_VCO_DIV6    		PLL:DRP22[1]
    PLL:EN_VCO_DIV1
    17----------------------------PLL:DRP22[2]PLL:DRP22[3]
    18----------------------------PLL:DRP22[4]PLL:DRP22[5]
    19----------------------------PLL:DRP22[6]PLL:DRP22[7]
    20----------------------------PLL:DRP22[8]PLL:DRP22[9]
    21----------------------------PLL:DRP22[10]PLL:DRP22[11]
    22----------------------------PLL:DRP22[12]PLL:DRP22[13]
    23----------------------------PLL:DRP22[14]PLL:DRP22[15]
    24----------------------------PLL:DRP23[0]PLL:DRP23[1]
    25----------------------------PLL:DRP23[2]PLL:DRP23[3]
    26----------------------------PLL:DRP23[4]PLL:DRP23[5]
    27----------------------------PLL:DRP23[6]PLL:DRP23[7]
    28----------------------------PLL:DRP23[8]PLL:DRP23[9]
    29----------------------------PLL:DRP23[10]PLL:DRP23[11]
    30----------------------------PLL:DRP23[12]PLL:DRP23[13]
    31----------------------------PLL:DRP23[14]PLL:DRP23[15]
    32----------------------------PLL:DRP24[0]PLL:DRP24[1]
    33----------------------------PLL:DRP24[2]PLL:DRP24[3]
    34----------------------------PLL:DRP24[4]PLL:DRP24[5]
    35----------------------------PLL:DRP24[6]PLL:DRP24[7]
    36----------------------------PLL:DRP24[8]PLL:DRP24[9]
    37----------------------------PLL:DRP24[10]PLL:DRP24[11]
    38----------------------------PLL:DRP24[12]PLL:DRP24[13]
    39----------------------------PLL:DRP24[14]PLL:DRP24[15]
    40----------------------------PLL:DRP25[0]PLL:DRP25[1]
    41----------------------------PLL:DRP25[2]PLL:DRP25[3]
    42----------------------------PLL:DRP25[4]PLL:DRP25[5]
    43----------------------------PLL:DRP25[6]PLL:DRP25[7]
    44----------------------------PLL:DRP25[8]PLL:DRP25[9]
    45----------------------------PLL:DRP25[10]PLL:DRP25[11]
    46----------------------------PLL:DRP25[12]PLL:DRP25[13]
    47----------------------------PLL:DRP25[14]PLL:DRP25[15]
    48----------------------------PLL:DRP26[0]PLL:DRP26[1]
    49----------------------------PLL:DRP26[2]PLL:ANALOG_MISC[0]
    PLL:DRP26[3]
    50----------------------------PLL:ANALOG_MISC[1]
    PLL:DRP26[4]    		PLL:DRP26[5]
    51----------------------------PLL:DRP26[6]PLL:ANALOG_MISC[2]
    PLL:DRP26[7]
    52----------------------------PLL:ANALOG_MISC[3]
    PLL:DRP26[8]    		PLL:DRP26[9]
    53----------------------------PLL:DRP26[10]PLL:DRP26[11]
    54----------------------------PLL:DRP26[12]PLL:DRP26[13]
    55----------------------------PLL:DRP26[14]PLL:DRP26[15]
    56----------------------------PLL:DRP27[0]PLL:DRP27[1]
    57----------------------------PLL:DRP27[2]PLL:DRP27[3]
    58----------------------------PLL:DRP27[4]PLL:DRP27[5]
    59----------------------------PLL:DRP27[6]PLL:DRP27[7]
    60----------------------------PLL:DRP27[8]PLL:DRP27[9]
    61----------------------------PLL:DRP27[10]PLL:DRP27[11]
    62----------------------------PLL:DRP27[12]PLL:DRP27[13]
    63----------------------------PLL:DRP27[14]PLL:DRP27[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 42
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP28[0]PLL:DRP28[1]
    1----------------------------PLL:DRP28[2]PLL:DRP28[3]
    2----------------------------PLL:DRP28[4]PLL:DRP28[5]
    3----------------------------PLL:DRP28[6]PLL:DRP28[7]
    4----------------------------PLL:DRP28[8]PLL:DRP28[9]
    5----------------------------PLL:DRP28[10]PLL:DRP28[11]
    6----------------------------PLL:DRP28[12]PLL:DRP28[13]
    7----------------------------PLL:DRP28[14]PLL:DRP28[15]
    8----------------------------PLL:DRP29[0]PLL:DRP29[1]
    9----------------------------PLL:DRP29[2]PLL:DRP29[3]
    10----------------------------PLL:DRP29[4]PLL:DRP29[5]
    11----------------------------PLL:DRP29[6]PLL:DRP29[7]
    12----------------------------PLL:DRP29[8]PLL:DRP29[9]
    13----------------------------PLL:DRP29[10]PLL:DRP29[11]
    14----------------------------PLL:DRP29[12]PLL:DRP29[13]
    15----------------------------PLL:DRP29[14]PLL:DRP29[15]
    16----------------------------PLL:DRP2A[0]PLL:DRP2A[1]
    17----------------------------PLL:DRP2A[2]PLL:DRP2A[3]
    18----------------------------PLL:DRP2A[4]PLL:DRP2A[5]
    19----------------------------PLL:DRP2A[6]PLL:DRP2A[7]
    20----------------------------PLL:DRP2A[8]PLL:DRP2A[9]
    21----------------------------PLL:DRP2A[10]PLL:DRP2A[11]
    22----------------------------PLL:DRP2A[12]PLL:DRP2A[13]
    23----------------------------PLL:DRP2A[14]PLL:DRP2A[15]
    24----------------------------PLL:DRP2B[0]PLL:DRP2B[1]
    25----------------------------PLL:DRP2B[2]PLL:DRP2B[3]
    26----------------------------PLL:DRP2B[4]PLL:DRP2B[5]
    27----------------------------PLL:DRP2B[6]PLL:DRP2B[7]
    28----------------------------PLL:DRP2B[8]PLL:DRP2B[9]
    29----------------------------PLL:DRP2B[10]PLL:DRP2B[11]
    30----------------------------PLL:DRP2B[12]PLL:DRP2B[13]
    31----------------------------PLL:DRP2B[14]PLL:DRP2B[15]
    32----------------------------PLL:DRP2C[0]PLL:DRP2C[1]
    33----------------------------PLL:DRP2C[2]PLL:DRP2C[3]
    34----------------------------PLL:DRP2C[4]PLL:DRP2C[5]
    35----------------------------PLL:DRP2C[6]PLL:DRP2C[7]
    36----------------------------PLL:DRP2C[8]PLL:DRP2C[9]
    37----------------------------PLL:DRP2C[10]PLL:DRP2C[11]
    38----------------------------PLL:DRP2C[12]PLL:DRP2C[13]
    39----------------------------PLL:DRP2C[14]PLL:DRP2C[15]
    40----------------------------PLL:DRP2D[0]PLL:DRP2D[1]
    41----------------------------PLL:DRP2D[2]PLL:DRP2D[3]
    42----------------------------PLL:DRP2D[4]PLL:DRP2D[5]
    43----------------------------PLL:DRP2D[6]PLL:DRP2D[7]
    44----------------------------PLL:DRP2D[8]PLL:DRP2D[9]
    45----------------------------PLL:DRP2D[10]PLL:DRP2D[11]
    46----------------------------PLL:DRP2D[12]PLL:DRP2D[13]
    47----------------------------PLL:DRP2D[14]PLL:DRP2D[15]
    48----------------------------PLL:DRP2E[0]PLL:DRP2E[1]
    49----------------------------PLL:DRP2E[2]PLL:DRP2E[3]
    50----------------------------PLL:DRP2E[4]PLL:DRP2E[5]
    51----------------------------PLL:DRP2E[6]PLL:DRP2E[7]
    52----------------------------PLL:DRP2E[8]PLL:DRP2E[9]
    53----------------------------PLL:DRP2E[10]PLL:DRP2E[11]
    54----------------------------PLL:DRP2E[12]PLL:DRP2E[13]
    55----------------------------PLL:DRP2E[14]PLL:DRP2E[15]
    56----------------------------PLL:DRP2F[0]PLL:DRP2F[1]
    57----------------------------PLL:DRP2F[2]PLL:DRP2F[3]
    58----------------------------PLL:DRP2F[4]PLL:DRP2F[5]
    59----------------------------PLL:DRP2F[6]PLL:DRP2F[7]
    60----------------------------PLL:DRP2F[8]PLL:DRP2F[9]
    61----------------------------PLL:DRP2F[10]PLL:DRP2F[11]
    62----------------------------PLL:DRP2F[12]PLL:DRP2F[13]
    63----------------------------PLL:DRP2F[14]PLL:DRP2F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 43
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP30[0]PLL:DRP30[1]
    1----------------------------PLL:DRP30[2]PLL:DRP30[3]
    2----------------------------PLL:DRP30[4]PLL:DRP30[5]
    3----------------------------PLL:DRP30[6]PLL:DRP30[7]
    4----------------------------PLL:DRP30[8]PLL:DRP30[9]
    5----------------------------PLL:DRP30[10]PLL:DRP30[11]
    6----------------------------PLL:DRP30[12]PLL:DRP30[13]
    7----------------------------PLL:DRP30[14]PLL:DRP30[15]
    8----------------------------PLL:DRP31[0]PLL:DRP31[1]
    9----------------------------PLL:DRP31[2]PLL:DRP31[3]
    10----------------------------PLL:DRP31[4]PLL:DRP31[5]
    11----------------------------PLL:DRP31[6]PLL:DRP31[7]
    12----------------------------PLL:DRP31[8]PLL:DRP31[9]
    13----------------------------PLL:DRP31[10]PLL:DRP31[11]
    14----------------------------PLL:DRP31[12]PLL:DRP31[13]
    15----------------------------PLL:DRP31[14]PLL:DRP31[15]
    16----------------------------PLL:DRP32[0]PLL:DRP32[1]
    17----------------------------PLL:DRP32[2]PLL:DRP32[3]
    18----------------------------PLL:DRP32[4]PLL:DRP32[5]
    19----------------------------PLL:DRP32[6]PLL:DRP32[7]
    20----------------------------PLL:DRP32[8]PLL:DRP32[9]
    21----------------------------PLL:DRP32[10]PLL:DRP32[11]
    22----------------------------PLL:DRP32[12]PLL:DRP32[13]
    23----------------------------PLL:DRP32[14]PLL:DRP32[15]
    24----------------------------PLL:DRP33[0]PLL:DRP33[1]
    25----------------------------PLL:DRP33[2]PLL:DRP33[3]
    26----------------------------PLL:DRP33[4]PLL:DRP33[5]
    27----------------------------PLL:DRP33[6]PLL:DRP33[7]
    28----------------------------PLL:DRP33[8]PLL:DRP33[9]
    29----------------------------PLL:DRP33[10]PLL:DRP33[11]
    30----------------------------PLL:DRP33[12]PLL:DRP33[13]
    31----------------------------PLL:DRP33[14]PLL:DRP33[15]
    32----------------------------PLL:DRP34[0]PLL:DRP34[1]
    33----------------------------PLL:DRP34[2]PLL:DRP34[3]
    34----------------------------PLL:DRP34[4]PLL:DRP34[5]
    35----------------------------PLL:DRP34[6]PLL:DRP34[7]
    36----------------------------PLL:DRP34[8]PLL:DRP34[9]
    37----------------------------PLL:DRP34[10]PLL:DRP34[11]
    38----------------------------PLL:DRP34[12]PLL:DRP34[13]
    39----------------------------PLL:DRP34[14]PLL:DRP34[15]
    40----------------------------PLL:DRP35[0]PLL:DRP35[1]
    41----------------------------PLL:DRP35[2]PLL:DRP35[3]
    42----------------------------PLL:DRP35[4]PLL:DRP35[5]
    43----------------------------PLL:DRP35[6]PLL:DRP35[7]
    44----------------------------PLL:DRP35[8]PLL:DRP35[9]
    45----------------------------PLL:DRP35[10]PLL:DRP35[11]
    46----------------------------PLL:DRP35[12]PLL:DRP35[13]
    47----------------------------PLL:DRP35[14]PLL:DRP35[15]
    48----------------------------PLL:DRP36[0]PLL:DRP36[1]
    49----------------------------PLL:DRP36[2]PLL:DRP36[3]
    50----------------------------PLL:DRP36[4]PLL:DRP36[5]
    51----------------------------PLL:DRP36[6]PLL:DRP36[7]
    52----------------------------PLL:DRP36[8]PLL:DRP36[9]
    53----------------------------PLL:DRP36[10]PLL:DRP36[11]
    54----------------------------PLL:DRP36[12]PLL:DRP36[13]
    55----------------------------PLL:DRP36[14]PLL:DRP36[15]
    56----------------------------PLL:DRP37[0]PLL:DRP37[1]
    57----------------------------PLL:DRP37[2]PLL:DRP37[3]
    58----------------------------PLL:DRP37[4]PLL:DRP37[5]
    59----------------------------PLL:DRP37[6]PLL:DRP37[7]
    60----------------------------PLL:DRP37[8]PLL:DRP37[9]
    61----------------------------PLL:DRP37[10]PLL:DRP37[11]
    62----------------------------PLL:DRP37[12]PLL:DRP37[13]
    63----------------------------PLL:DRP37[14]PLL:DRP37[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 44
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP38[0]PLL:DRP38[1]
    1----------------------------PLL:DRP38[2]PLL:DRP38[3]
    2----------------------------PLL:DRP38[4]PLL:DRP38[5]
    3----------------------------PLL:DRP38[6]PLL:DRP38[7]
    4----------------------------PLL:DRP38[8]PLL:DRP38[9]
    5----------------------------PLL:DRP38[10]PLL:DRP38[11]
    6----------------------------PLL:DRP38[12]PLL:DRP38[13]
    7----------------------------PLL:DRP38[14]PLL:DRP38[15]
    8----------------------------PLL:DRP39[0]PLL:DRP39[1]
    9----------------------------PLL:DRP39[2]PLL:DRP39[3]
    10----------------------------PLL:DRP39[4]PLL:DRP39[5]
    11----------------------------PLL:DRP39[6]PLL:DRP39[7]
    12----------------------------PLL:DRP39[8]PLL:DRP39[9]
    13----------------------------PLL:DRP39[10]PLL:DRP39[11]
    14----------------------------PLL:DRP39[12]PLL:DRP39[13]
    15----------------------------PLL:DRP39[14]PLL:DRP39[15]
    16----------------------------PLL:DRP3A[0]PLL:DRP3A[1]
    17----------------------------PLL:DRP3A[2]PLL:DRP3A[3]
    18----------------------------PLL:DRP3A[4]PLL:DRP3A[5]
    19----------------------------PLL:DRP3A[6]PLL:DRP3A[7]
    20----------------------------PLL:DRP3A[8]PLL:DRP3A[9]
    21----------------------------PLL:DRP3A[10]PLL:DRP3A[11]
    22----------------------------PLL:DRP3A[12]PLL:DRP3A[13]
    23----------------------------PLL:DRP3A[14]PLL:DRP3A[15]
    24----------------------------PLL:DRP3B[0]PLL:DRP3B[1]
    25----------------------------PLL:DRP3B[2]PLL:DRP3B[3]
    26----------------------------PLL:DRP3B[4]PLL:DRP3B[5]
    27----------------------------PLL:DRP3B[6]PLL:DRP3B[7]
    28----------------------------PLL:DRP3B[8]PLL:DRP3B[9]
    29----------------------------PLL:DRP3B[10]PLL:DRP3B[11]
    30----------------------------PLL:DRP3B[12]PLL:DRP3B[13]
    31----------------------------PLL:DRP3B[14]PLL:DRP3B[15]
    32----------------------------PLL:DRP3C[0]PLL:DRP3C[1]
    33----------------------------PLL:DRP3C[2]PLL:DRP3C[3]
    34----------------------------PLL:DRP3C[4]PLL:DRP3C[5]
    35----------------------------PLL:DRP3C[6]PLL:DRP3C[7]
    36----------------------------PLL:DRP3C[8]PLL:DRP3C[9]
    37----------------------------PLL:DRP3C[10]PLL:DRP3C[11]
    38----------------------------PLL:DRP3C[12]PLL:DRP3C[13]
    39----------------------------PLL:DRP3C[14]PLL:DRP3C[15]
    40----------------------------PLL:DRP3D[0]PLL:DRP3D[1]
    41----------------------------PLL:DRP3D[2]PLL:DRP3D[3]
    42----------------------------PLL:DRP3D[4]PLL:DRP3D[5]
    43----------------------------PLL:DRP3D[6]PLL:DRP3D[7]
    44----------------------------PLL:DRP3D[8]PLL:DRP3D[9]
    45----------------------------PLL:DRP3D[10]PLL:DRP3D[11]
    46----------------------------PLL:DRP3D[12]PLL:DRP3D[13]
    47----------------------------PLL:DRP3D[14]PLL:DRP3D[15]
    48----------------------------PLL:DRP3E[0]PLL:DRP3E[1]
    49----------------------------PLL:DRP3E[2]PLL:DRP3E[3]
    50----------------------------PLL:DRP3E[4]PLL:DRP3E[5]
    51----------------------------PLL:DRP3E[6]PLL:DRP3E[7]
    52----------------------------PLL:DRP3E[8]PLL:DRP3E[9]
    53----------------------------PLL:DRP3E[10]PLL:DRP3E[11]
    54----------------------------PLL:DRP3E[12]PLL:DRP3E[13]
    55----------------------------PLL:DRP3E[14]PLL:DRP3E[15]
    56----------------------------PLL:DRP3F[0]PLL:DRP3F[1]
    57----------------------------PLL:DRP3F[2]PLL:DRP3F[3]
    58----------------------------PLL:DRP3F[4]PLL:DRP3F[5]
    59----------------------------PLL:DRP3F[6]PLL:DRP3F[7]
    60----------------------------PLL:DRP3F[8]PLL:DRP3F[9]
    61----------------------------PLL:DRP3F[10]PLL:DRP3F[11]
    62----------------------------PLL:DRP3F[12]PLL:DRP3F[13]
    63----------------------------PLL:DRP3F[14]PLL:DRP3F[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 45
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP40[0]PLL:DRP40[1]
    1----------------------------PLL:DRP40[2]PLL:DRP40[3]
    2----------------------------PLL:DRP40[4]PLL:DRP40[5]
    3----------------------------PLL:DRP40[6]PLL:DRP40[7]
    4----------------------------PLL:DRP40[8]PLL:DRP40[9]
    5----------------------------PLL:DRP40[10]PLL:DRP40[11]
    6----------------------------PLL:DRP40[12]PLL:DRP40[13]
    7----------------------------PLL:DRP40[14]PLL:DRP40[15]
    8----------------------------PLL:DRP41[0]PLL:DRP41[1]
    9----------------------------PLL:DRP41[2]PLL:DRP41[3]
    10----------------------------PLL:DRP41[4]PLL:DRP41[5]
    11----------------------------PLL:DRP41[6]PLL:DRP41[7]
    12----------------------------PLL:DRP41[8]PLL:DRP41[9]
    13----------------------------PLL:DRP41[10]PLL:DRP41[11]
    14----------------------------PLL:DRP41[12]PLL:DRP41[13]
    15----------------------------PLL:DRP41[14]PLL:DRP41[15]
    16----------------------------PLL:DRP42[0]
    PLL:MAN_LF[0]    		PLL:DRP42[1]
    17----------------------------PLL:DRP42[2]PLL:DRP42[3]
    PLL:MAN_LF[1]
    18----------------------------PLL:DRP42[4]
    PLL:MAN_LF[2]    		PLL:DRP42[5]
    19----------------------------PLL:DRP42[6]PLL:DRP42[7]
    PLL:VLF_HIGH_DIS_B
    20----------------------------PLL:DRP42[8]
    PLL:LF_PEN[0]    		PLL:DRP42[9]
    21----------------------------PLL:DRP42[10]PLL:DRP42[11]
    PLL:LF_PEN[1]
    22----------------------------PLL:DRP42[12]
    PLL:LF_NEN[0]    		PLL:DRP42[13]
    23----------------------------PLL:DRP42[14]PLL:DRP42[15]
    PLL:LF_NEN[1]
    24----------------------------PLL:DRP43[0]
    PLL:LF_LOW_SEL    		PLL:DRP43[1]
    25----------------------------PLL:DRP43[2]PLL:DRP43[3]
    26----------------------------PLL:DRP43[4]PLL:DRP43[5]
    27----------------------------PLL:DRP43[6]PLL:DRP43[7]
    28----------------------------PLL:DRP43[8]PLL:DRP43[9]
    29----------------------------PLL:DRP43[10]PLL:DRP43[11]
    30----------------------------PLL:DRP43[12]PLL:DRP43[13]
    31----------------------------PLL:DRP43[14]PLL:DRP43[15]
    32----------------------------PLL:DRP44[0]
    PLL:SPARE_ANALOG[0]    		PLL:DRP44[1]
    33----------------------------PLL:DRP44[2]PLL:DRP44[3]
    PLL:SPARE_ANALOG[1]
    34----------------------------PLL:DRP44[4]
    PLL:SPARE_ANALOG[2]    		PLL:DRP44[5]
    35----------------------------PLL:DRP44[6]PLL:DRP44[7]
    PLL:SPARE_ANALOG[3]
    36----------------------------PLL:DRP44[8]
    PLL:SPARE_ANALOG[4]    		PLL:DRP44[9]
    37----------------------------PLL:DRP44[10]PLL:DRP44[11]
    38----------------------------PLL:DRP44[12]PLL:DRP44[13]
    39----------------------------PLL:DRP44[14]PLL:DRP44[15]
    40----------------------------PLL:DRP45[0]PLL:DRP45[1]
    41----------------------------PLL:DRP45[2]PLL:DRP45[3]
    42----------------------------PLL:DRP45[4]PLL:DRP45[5]
    43----------------------------PLL:DRP45[6]PLL:DRP45[7]
    44----------------------------PLL:DRP45[8]PLL:DRP45[9]
    45----------------------------PLL:DRP45[10]PLL:DRP45[11]
    PLL:VREF_START[0]
    46----------------------------PLL:DRP45[12]
    PLL:VREF_START[1]    		PLL:DRP45[13]
    47----------------------------PLL:DRP45[14]PLL:DRP45[15]
    48----------------------------PLL:DRP46[0]
    PLL:VLF_HIGH_PWDN_B    		PLL:DRP46[1]
    49----------------------------PLL:DRP46[2]PLL:DRP46[3]
    50----------------------------PLL:DRP46[4]PLL:DRP46[5]
    51----------------------------PLL:DRP46[6]PLL:DRP46[7]
    52----------------------------PLL:DRP46[8]PLL:DRP46[9]
    53----------------------------PLL:DRP46[10]PLL:DRP46[11]
    54----------------------------PLL:DRP46[12]PLL:DRP46[13]
    55----------------------------PLL:DRP46[14]PLL:DRP46[15]
    56----------------------------PLL:DRP47[0]PLL:DRP47[1]
    57----------------------------PLL:DRP47[2]PLL:DRP47[3]
    58----------------------------PLL:DRP47[4]PLL:DRP47[5]
    59----------------------------PLL:DRP47[6]PLL:DRP47[7]
    60----------------------------PLL:DRP47[8]PLL:DRP47[9]
    61----------------------------PLL:DRP47[10]PLL:DRP47[11]
    62----------------------------PLL:DRP47[12]PLL:DRP47[13]
    63----------------------------PLL:DRP47[14]PLL:DRP47[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 46
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP48[0]PLL:DRP48[1]
    1----------------------------PLL:DRP48[2]PLL:DRP48[3]
    2----------------------------PLL:DRP48[4]PLL:DRP48[5]
    3----------------------------PLL:DRP48[6]PLL:DRP48[7]
    4----------------------------PLL:DRP48[8]PLL:DRP48[9]
    5----------------------------PLL:DRP48[10]PLL:DRP48[11]
    6----------------------------PLL:DRP48[12]PLL:DRP48[13]
    7----------------------------PLL:DRP48[14]PLL:DRP48[15]
    8----------------------------PLL:DRP49[0]PLL:DRP49[1]
    9----------------------------PLL:DRP49[2]PLL:DRP49[3]
    10----------------------------PLL:DRP49[4]PLL:DRP49[5]
    11----------------------------PLL:DRP49[6]PLL:DRP49[7]
    12----------------------------PLL:DRP49[8]PLL:DRP49[9]
    13----------------------------PLL:DRP49[10]
    PLL:SEL_HV_NMOS    		PLL:DRP49[11]
    PLL:MVDD_SEL[0]
    14----------------------------PLL:DRP49[12]
    PLL:MVDD_SEL[1]    		PLL:DRP49[13]
    PLL:EN_CURR_SINK[0]
    15----------------------------PLL:DRP49[14]
    PLL:EN_CURR_SINK[1]    		PLL:DRP49[15]
    PLL:SUP_SEL_AREG
    16----------------------------PLL:AVDD_VBG_SEL[0]
    PLL:DRP4A[0]    		PLL:AVDD_VBG_SEL[1]
    PLL:DRP4A[1]
    17----------------------------PLL:AVDD_VBG_SEL[2]
    PLL:DRP4A[2]    		PLL:AVDD_VBG_SEL[3]
    PLL:DRP4A[3]
    18----------------------------PLL:AVDD_VBG_PD[0]
    PLL:DRP4A[4]    		PLL:AVDD_VBG_PD[1]
    PLL:DRP4A[5]
    19----------------------------PLL:AVDD_VBG_PD[2]
    PLL:DRP4A[6]    		PLL:AVDD_COMP_SET[0]
    PLL:DRP4A[7]
    20----------------------------PLL:AVDD_COMP_SET[1]
    PLL:DRP4A[8]    		PLL:AVDD_COMP_SET[2]
    PLL:DRP4A[9]
    21----------------------------PLL:DRP4A[10]PLL:DRP4A[11]
    22----------------------------PLL:DRP4A[12]PLL:DRP4A[13]
    23----------------------------PLL:DRP4A[14]PLL:DRP4A[15]
    24----------------------------PLL:DRP4B[0]PLL:DRP4B[1]
    25----------------------------PLL:DRP4B[2]PLL:DRP4B[3]
    26----------------------------PLL:DRP4B[4]PLL:DRP4B[5]
    27----------------------------PLL:DRP4B[6]PLL:DRP4B[7]
    28----------------------------PLL:DRP4B[8]PLL:DRP4B[9]
    29----------------------------PLL:DRP4B[10]PLL:DRP4B[11]
    30----------------------------PLL:DRP4B[12]PLL:DRP4B[13]
    31----------------------------PLL:DRP4B[14]PLL:DRP4B[15]
    32----------------------------PLL:DRP4C[0]
    PLL:HVLF_CNT_TEST[0]    		PLL:DRP4C[1]
    33----------------------------PLL:DRP4C[2]PLL:DRP4C[3]
    PLL:HVLF_CNT_TEST[1]
    34----------------------------PLL:DRP4C[4]
    PLL:HVLF_CNT_TEST[2]    		PLL:DRP4C[5]
    35----------------------------PLL:DRP4C[6]PLL:DRP4C[7]
    PLL:HVLF_CNT_TEST[3]
    36----------------------------PLL:DRP4C[8]
    PLL:HVLF_CNT_TEST[4]    		PLL:DRP4C[9]
    37----------------------------PLL:DRP4C[10]PLL:DRP4C[11]
    PLL:HVLF_CNT_TEST[5]
    38----------------------------PLL:DRP4C[12]
    PLL:HVLF_CNT_TEST_EN    		PLL:DRP4C[13]
    39----------------------------PLL:DRP4C[14]PLL:DRP4C[15]
    40----------------------------PLL:DRP4D[0]PLL:DRP4D[1]
    41----------------------------PLL:DRP4D[2]PLL:DRP4D[3]
    42----------------------------PLL:DRP4D[4]PLL:DRP4D[5]
    43----------------------------PLL:DRP4D[6]PLL:DRP4D[7]
    44----------------------------PLL:DRP4D[8]PLL:DRP4D[9]
    45----------------------------PLL:DRP4D[10]PLL:DRP4D[11]
    46----------------------------PLL:DRP4D[12]PLL:DRP4D[13]
    47----------------------------PLL:DRP4D[14]PLL:DRP4D[15]
    48----------------------------PLL:DRP4E[0]PLL:DRP4E[1]
    49----------------------------PLL:DRP4E[2]PLL:CP_RES[0]
    PLL:DRP4E[3]
    50----------------------------PLL:CP_RES[1]
    PLL:DRP4E[4]    		PLL:DRP4E[5]
    51----------------------------PLL:DRP4E[6]PLL:CP_BIAS_TRIP_SET
    PLL:DRP4E[7]
    52----------------------------PLL:CP[0]
    PLL:DRP4E[8]    		PLL:DRP4E[9]
    53----------------------------PLL:DRP4E[10]PLL:CP[1]
    PLL:DRP4E[11]
    54----------------------------PLL:CP[2]
    PLL:DRP4E[12]    		PLL:DRP4E[13]
    55----------------------------PLL:DRP4E[14]PLL:CP[3]
    PLL:DRP4E[15]
    56----------------------------PLL:DRP4F[0]PLL:DRP4F[1]
    57----------------------------PLL:DRP4F[2]PLL:DRP4F[3]
    58----------------------------PLL:DRP4F[4]
    PLL:LFHF[0]    		PLL:DRP4F[5]
    59----------------------------PLL:DRP4F[6]PLL:DRP4F[7]
    PLL:LFHF[1]
    60----------------------------PLL:DRP4F[8]
    PLL:RES[0]    		PLL:DRP4F[9]
    61----------------------------PLL:DRP4F[10]PLL:DRP4F[11]
    PLL:RES[1]
    62----------------------------PLL:DRP4F[12]
    PLL:RES[2]    		PLL:DRP4F[13]
    63----------------------------PLL:DRP4F[14]PLL:DRP4F[15]
    PLL:RES[3]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 47
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP50[0]PLL:DRP50[1]
    1----------------------------PLL:DRP50[2]PLL:DRP50[3]
    2----------------------------PLL:DRP50[4]PLL:DRP50[5]
    3----------------------------PLL:DRP50[6]PLL:DRP50[7]
    4----------------------------PLL:DRP50[8]PLL:DRP50[9]
    5----------------------------PLL:DRP50[10]PLL:DRP50[11]
    6----------------------------PLL:DRP50[12]PLL:DRP50[13]
    7----------------------------PLL:DRP50[14]PLL:DRP50[15]
    8----------------------------PLL:DRP51[0]PLL:DRP51[1]
    9----------------------------PLL:DRP51[2]PLL:DRP51[3]
    10----------------------------PLL:DRP51[4]PLL:DRP51[5]
    11----------------------------PLL:DRP51[6]PLL:DRP51[7]
    12----------------------------PLL:DRP51[8]PLL:DRP51[9]
    13----------------------------PLL:DRP51[10]PLL:DRP51[11]
    14----------------------------PLL:DRP51[12]PLL:DRP51[13]
    15----------------------------PLL:DRP51[14]PLL:DRP51[15]
    16----------------------------PLL:DRP52[0]PLL:DRP52[1]
    17----------------------------PLL:DRP52[2]PLL:DRP52[3]
    18----------------------------PLL:DRP52[4]PLL:DRP52[5]
    19----------------------------PLL:DRP52[6]PLL:DRP52[7]
    20----------------------------PLL:DRP52[8]PLL:DRP52[9]
    21----------------------------PLL:DRP52[10]PLL:DRP52[11]
    22----------------------------PLL:DRP52[12]PLL:DRP52[13]
    23----------------------------PLL:DRP52[14]PLL:DRP52[15]
    24----------------------------PLL:DRP53[0]PLL:DRP53[1]
    25----------------------------PLL:DRP53[2]PLL:DRP53[3]
    26----------------------------PLL:DRP53[4]PLL:DRP53[5]
    27----------------------------PLL:DRP53[6]PLL:DRP53[7]
    28----------------------------PLL:DRP53[8]PLL:DRP53[9]
    29----------------------------PLL:DRP53[10]PLL:DRP53[11]
    30----------------------------PLL:DRP53[12]PLL:DRP53[13]
    31----------------------------PLL:DRP53[14]PLL:DRP53[15]
    32----------------------------PLL:DRP54[0]PLL:DRP54[1]
    33----------------------------PLL:DRP54[2]PLL:DRP54[3]
    34----------------------------PLL:DRP54[4]PLL:DRP54[5]
    35----------------------------PLL:DRP54[6]PLL:DRP54[7]
    36----------------------------PLL:DRP54[8]PLL:DRP54[9]
    37----------------------------PLL:DRP54[10]PLL:DRP54[11]
    38----------------------------PLL:DRP54[12]PLL:DRP54[13]
    39----------------------------PLL:DRP54[14]PLL:DRP54[15]
    40----------------------------PLL:DRP55[0]PLL:DRP55[1]
    41----------------------------PLL:DRP55[2]PLL:DRP55[3]
    42----------------------------PLL:DRP55[4]PLL:DRP55[5]
    43----------------------------PLL:DRP55[6]PLL:DRP55[7]
    44----------------------------PLL:DRP55[8]PLL:DRP55[9]
    45----------------------------PLL:DRP55[10]PLL:DRP55[11]
    46----------------------------PLL:DRP55[12]PLL:DRP55[13]
    47----------------------------PLL:DRP55[14]PLL:DRP55[15]
    48----------------------------PLL:DRP56[0]PLL:DRP56[1]
    49----------------------------PLL:DRP56[2]PLL:DRP56[3]
    50----------------------------PLL:DRP56[4]PLL:DRP56[5]
    51----------------------------PLL:DRP56[6]PLL:DRP56[7]
    52----------------------------PLL:DRP56[8]PLL:DRP56[9]
    53----------------------------PLL:DRP56[10]PLL:DRP56[11]
    54----------------------------PLL:DRP56[12]PLL:DRP56[13]
    55----------------------------PLL:DRP56[14]PLL:DRP56[15]
    56----------------------------PLL:DRP57[0]PLL:DRP57[1]
    57----------------------------PLL:DRP57[2]PLL:DRP57[3]
    58----------------------------PLL:DRP57[4]PLL:DRP57[5]
    59----------------------------PLL:DRP57[6]PLL:DRP57[7]
    60----------------------------PLL:DRP57[8]PLL:DRP57[9]
    61----------------------------PLL:DRP57[10]PLL:DRP57[11]
    62----------------------------PLL:DRP57[12]PLL:DRP57[13]
    63----------------------------PLL:DRP57[14]PLL:DRP57[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 48
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:DRP58[0]PLL:DRP58[1]
    1----------------------------PLL:DRP58[2]PLL:DRP58[3]
    2----------------------------PLL:DRP58[4]PLL:DRP58[5]
    3----------------------------PLL:DRP58[6]PLL:DRP58[7]
    4----------------------------PLL:DRP58[8]PLL:DRP58[9]
    5----------------------------PLL:DRP58[10]PLL:DRP58[11]
    6----------------------------PLL:DRP58[12]PLL:DRP58[13]
    7----------------------------PLL:DRP58[14]PLL:DRP58[15]
    8----------------------------PLL:DRP59[0]PLL:DRP59[1]
    9----------------------------PLL:DRP59[2]PLL:DRP59[3]
    10----------------------------PLL:DRP59[4]PLL:DRP59[5]
    11----------------------------PLL:DRP59[6]PLL:DRP59[7]
    12----------------------------PLL:DRP59[8]PLL:DRP59[9]
    13----------------------------PLL:DRP59[10]PLL:DRP59[11]
    14----------------------------PLL:DRP59[12]PLL:DRP59[13]
    15----------------------------PLL:DRP59[14]PLL:DRP59[15]
    16----------------------------PLL:DRP5A[0]
    PLL:INV.RST    		PLL:DRP5A[1]
    PLL:INV.PWRDWN
    17----------------------------PLL:DRP5A[2]PLL:DRP5A[3]
    18----------------------------PLL:DRP5A[4]
    PLL:INV.CLKINSEL    		PLL:DRP5A[5]
    19----------------------------PLL:DRP5A[6]PLL:DRP5A[7]
    20----------------------------PLL:DRP5A[8]PLL:DRP5A[9]
    21----------------------------PLL:DRP5A[10]PLL:DRP5A[11]
    22----------------------------PLL:DRP5A[12]PLL:DRP5A[13]
    23----------------------------PLL:DRP5A[14]PLL:DRP5A[15]
    24----------------------------PLL:DRP5B[0]PLL:DRP5B[1]
    25----------------------------PLL:DRP5B[2]PLL:DRP5B[3]
    26----------------------------PLL:DRP5B[4]PLL:DRP5B[5]
    27----------------------------PLL:DRP5B[6]PLL:DRP5B[7]
    28----------------------------PLL:DRP5B[8]PLL:DRP5B[9]
    29----------------------------PLL:DRP5B[10]PLL:DRP5B[11]
    30----------------------------PLL:DRP5B[12]PLL:DRP5B[13]
    31----------------------------PLL:DRP5B[14]PLL:DRP5B[15]
    32----------------------------PLL:DRP5C[0]
    PLL:PLL_EN    		PLL:DRP5C[1]
    33----------------------------PLL:DRP5C[2]
    PLL:STARTUP_WAIT    		PLL:DRP5C[3]
    PLL:GTS_WAIT
    34----------------------------PLL:DRP5C[4]PLL:DRP5C[5]
    35----------------------------PLL:DRP5C[6]PLL:DRP5C[7]
    36----------------------------PLL:DRP5C[8]PLL:DRP5C[9]
    37----------------------------PLL:DRP5C[10]PLL:DRP5C[11]
    38----------------------------PLL:DRP5C[12]PLL:DRP5C[13]
    39----------------------------PLL:DRP5C[14]PLL:DRP5C[15]
    40----------------------------PLL:DRP5D[0]PLL:DRP5D[1]
    41----------------------------PLL:DRP5D[2]PLL:DRP5D[3]
    42----------------------------PLL:DRP5D[4]PLL:DRP5D[5]
    43----------------------------PLL:DRP5D[6]PLL:DRP5D[7]
    44----------------------------PLL:DRP5D[8]PLL:DRP5D[9]
    45----------------------------PLL:DRP5D[10]PLL:DRP5D[11]
    46----------------------------PLL:DRP5D[12]PLL:DRP5D[13]
    47----------------------------PLL:DRP5D[14]PLL:DRP5D[15]
    48----------------------------PLL:CONTROL_0[0]
    PLL:DRP5E[0]    		PLL:CONTROL_0[1]
    PLL:DRP5E[1]
    49----------------------------PLL:CONTROL_0[2]
    PLL:DRP5E[2]    		PLL:CONTROL_0[3]
    PLL:DRP5E[3]
    50----------------------------PLL:CONTROL_0[4]
    PLL:DRP5E[4]    		PLL:CONTROL_0[5]
    PLL:DRP5E[5]
    51----------------------------PLL:CONTROL_0[6]
    PLL:DRP5E[6]    		PLL:CONTROL_0[7]
    PLL:DRP5E[7]
    52----------------------------PLL:CONTROL_0[8]
    PLL:DRP5E[8]    		PLL:CONTROL_0[9]
    PLL:DRP5E[9]
    53----------------------------PLL:CONTROL_0[10]
    PLL:DRP5E[10]    		PLL:CONTROL_0[11]
    PLL:DRP5E[11]
    54----------------------------PLL:CONTROL_0[12]
    PLL:DRP5E[12]    		PLL:CONTROL_0[13]
    PLL:DRP5E[13]
    55----------------------------PLL:CONTROL_0[14]
    PLL:DRP5E[14]    		PLL:CONTROL_0[15]
    PLL:DRP5E[15]
    56----------------------------PLL:CONTROL_1[0]
    PLL:DRP5F[0]    		PLL:CONTROL_1[1]
    PLL:DRP5F[1]
    57----------------------------PLL:CONTROL_1[2]
    PLL:DRP5F[2]    		PLL:CONTROL_1[3]
    PLL:DRP5F[3]
    58----------------------------PLL:CONTROL_1[4]
    PLL:DRP5F[4]    		PLL:CONTROL_1[5]
    PLL:DRP5F[5]
    59----------------------------PLL:CONTROL_1[6]
    PLL:DRP5F[6]    		PLL:CONTROL_1[7]
    PLL:DRP5F[7]
    60----------------------------PLL:CONTROL_1[8]
    PLL:DRP5F[8]    		PLL:CONTROL_1[9]
    PLL:DRP5F[9]
    61----------------------------PLL:CONTROL_1[10]
    PLL:DRP5F[10]    		PLL:CONTROL_1[11]
    PLL:DRP5F[11]
    62----------------------------PLL:CONTROL_1[12]
    PLL:DRP5F[12]    		PLL:CONTROL_1[13]
    PLL:DRP5F[13]
    63----------------------------PLL:CONTROL_1[14]
    PLL:DRP5F[14]    		PLL:CONTROL_1[15]
    PLL:DRP5F[15]
    - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 1
    RowColumn
    CMT bittile 49
    RowColumn
    01234567891011121314151617181920212223242526272829
    0----------------------------PLL:CONTROL_2[0]
    PLL:DRP60[0]    		PLL:CONTROL_2[1]
    PLL:DRP60[1]
    1----------------------------PLL:CONTROL_2[2]
    PLL:DRP60[2]    		PLL:CONTROL_2[3]
    PLL:DRP60[3]
    2----------------------------PLL:CONTROL_2[4]
    PLL:DRP60[4]    		PLL:CONTROL_2[5]
    PLL:DRP60[5]
    3----------------------------PLL:CONTROL_2[6]
    PLL:DRP60[6]    		PLL:CONTROL_2[7]
    PLL:DRP60[7]
    4----------------------------PLL:CONTROL_2[8]
    PLL:DRP60[8]    		PLL:CONTROL_2[9]
    PLL:DRP60[9]
    5----------------------------PLL:CONTROL_2[10]
    PLL:DRP60[10]    		PLL:CONTROL_2[11]
    PLL:DRP60[11]
    6----------------------------PLL:CONTROL_2[12]
    PLL:DRP60[12]    		PLL:CONTROL_2[13]
    PLL:DRP60[13]
    7----------------------------PLL:CONTROL_2[14]
    PLL:DRP60[14]    		PLL:CONTROL_2[15]
    PLL:DRP60[15]
    8----------------------------PLL:CONTROL_3[0]
    PLL:DRP61[0]    		PLL:CONTROL_3[1]
    PLL:DRP61[1]
    9----------------------------PLL:CONTROL_3[2]
    PLL:DRP61[2]    		PLL:CONTROL_3[3]
    PLL:DRP61[3]
    10----------------------------PLL:CONTROL_3[4]
    PLL:DRP61[4]    		PLL:CONTROL_3[5]
    PLL:DRP61[5]
    11----------------------------PLL:CONTROL_3[6]
    PLL:DRP61[6]    		PLL:CONTROL_3[7]
    PLL:DRP61[7]
    12----------------------------PLL:CONTROL_3[8]
    PLL:DRP61[8]    		PLL:CONTROL_3[9]
    PLL:DRP61[9]
    13----------------------------PLL:CONTROL_3[10]
    PLL:DRP61[10]    		PLL:CONTROL_3[11]
    PLL:DRP61[11]
    14----------------------------PLL:CONTROL_3[12]
    PLL:DRP61[12]    		PLL:CONTROL_3[13]
    PLL:DRP61[13]
    15----------------------------PLL:CONTROL_3[14]
    PLL:DRP61[14]    		PLL:CONTROL_3[15]
    PLL:DRP61[15]
    16----------------------------PLL:CONTROL_4[0]
    PLL:DRP62[0]    		PLL:CONTROL_4[1]
    PLL:DRP62[1]
    17----------------------------PLL:CONTROL_4[2]
    PLL:DRP62[2]    		PLL:CONTROL_4[3]
    PLL:DRP62[3]
    18----------------------------PLL:CONTROL_4[4]
    PLL:DRP62[4]    		PLL:CONTROL_4[5]
    PLL:DRP62[5]
    19----------------------------PLL:CONTROL_4[6]
    PLL:DRP62[6]    		PLL:CONTROL_4[7]
    PLL:DRP62[7]
    20----------------------------PLL:CONTROL_4[8]
    PLL:DRP62[8]    		PLL:CONTROL_4[9]
    PLL:DRP62[9]
    21----------------------------PLL:CONTROL_4[10]
    PLL:DRP62[10]    		PLL:CONTROL_4[11]
    PLL:DRP62[11]
    22----------------------------PLL:CONTROL_4[12]
    PLL:DRP62[12]    		PLL:CONTROL_4[13]
    PLL:DRP62[13]
    23----------------------------PLL:CONTROL_4[14]
    PLL:DRP62[14]    		PLL:CONTROL_4[15]
    PLL:DRP62[15]
    24----------------------------PLL:CONTROL_5[0]
    PLL:DRP63[0]    		PLL:CONTROL_5[1]
    PLL:DRP63[1]
    25----------------------------PLL:CONTROL_5[2]
    PLL:DRP63[2]    		PLL:CONTROL_5[3]
    PLL:DRP63[3]
    26----------------------------PLL:CONTROL_5[4]
    PLL:DRP63[4]    		PLL:CONTROL_5[5]
    PLL:DRP63[5]
    27----------------------------PLL:CONTROL_5[6]
    PLL:DRP63[6]    		PLL:CONTROL_5[7]
    PLL:DRP63[7]
    28----------------------------PLL:CONTROL_5[8]
    PLL:DRP63[8]    		PLL:CONTROL_5[9]
    PLL:DRP63[9]
    29----------------------------PLL:CONTROL_5[10]
    PLL:DRP63[10]    		PLL:CONTROL_5[11]
    PLL:DRP63[11]
    30----------------------------PLL:CONTROL_5[12]
    PLL:DRP63[12]    		PLL:CONTROL_5[13]
    PLL:DRP63[13]
    31----------------------------PLL:CONTROL_5[14]
    PLL:DRP63[14]    		PLL:CONTROL_5[15]
    PLL:DRP63[15]
    32----------------------------PLL:CONTROL_6[0]
    PLL:DRP64[0]    		PLL:CONTROL_6[1]
    PLL:DRP64[1]
    33----------------------------PLL:CONTROL_6[2]
    PLL:DRP64[2]    		PLL:CONTROL_6[3]
    PLL:DRP64[3]
    34----------------------------PLL:CONTROL_6[4]
    PLL:DRP64[4]    		PLL:CONTROL_6[5]
    PLL:DRP64[5]
    35----------------------------PLL:CONTROL_6[6]
    PLL:DRP64[6]    		PLL:CONTROL_6[7]
    PLL:DRP64[7]
    36----------------------------PLL:CONTROL_6[8]
    PLL:DRP64[8]    		PLL:CONTROL_6[9]
    PLL:DRP64[9]
    37----------------------------PLL:CONTROL_6[10]
    PLL:DRP64[10]    		PLL:CONTROL_6[11]
    PLL:DRP64[11]
    38----------------------------PLL:CONTROL_6[12]
    PLL:DRP64[12]    		PLL:CONTROL_6[13]
    PLL:DRP64[13]
    39----------------------------PLL:CONTROL_6[14]
    PLL:DRP64[14]    		PLL:CONTROL_6[15]
    PLL:DRP64[15]
    40----------------------------PLL:CONTROL_7[0]
    PLL:DRP65[0]    		PLL:CONTROL_7[1]
    PLL:DRP65[1]
    41----------------------------PLL:CONTROL_7[2]
    PLL:DRP65[2]    		PLL:CONTROL_7[3]
    PLL:DRP65[3]
    42----------------------------PLL:CONTROL_7[4]
    PLL:DRP65[4]    		PLL:CONTROL_7[5]
    PLL:DRP65[5]
    43----------------------------PLL:CONTROL_7[6]
    PLL:DRP65[6]    		PLL:CONTROL_7[7]
    PLL:DRP65[7]
    44----------------------------PLL:CONTROL_7[8]
    PLL:DRP65[8]    		PLL:CONTROL_7[9]
    PLL:DRP65[9]
    45----------------------------PLL:CONTROL_7[10]
    PLL:DRP65[10]    		PLL:CONTROL_7[11]
    PLL:DRP65[11]
    46----------------------------PLL:CONTROL_7[12]
    PLL:DRP65[12]    		PLL:CONTROL_7[13]
    PLL:DRP65[13]
    47----------------------------PLL:CONTROL_7[14]
    PLL:DRP65[14]    		PLL:CONTROL_7[15]
    PLL:DRP65[15]
    48----------------------------PLL:DRP66[0]PLL:DRP66[1]
    49----------------------------PLL:DRP66[2]PLL:DRP66[3]
    50----------------------------PLL:DRP66[4]PLL:DRP66[5]
    51----------------------------PLL:DRP66[6]PLL:DRP66[7]
    52----------------------------PLL:DRP66[8]PLL:DRP66[9]
    53----------------------------PLL:DRP66[10]PLL:DRP66[11]
    54----------------------------PLL:DRP66[12]PLL:DRP66[13]
    55----------------------------PLL:DRP66[14]PLL:DRP66[15]
    56----------------------------PLL:DRP67[0]PLL:DRP67[1]
    57----------------------------PLL:DRP67[2]PLL:DRP67[3]
    58----------------------------PLL:DRP67[4]PLL:DRP67[5]
    59----------------------------PLL:DRP67[6]PLL:DRP67[7]
    60----------------------------PLL:DRP67[8]PLL:DRP67[9]
    61----------------------------PLL:DRP67[10]PLL:DRP67[11]
    62----------------------------PLL:DRP67[12]PLL:DRP67[13]
    63----------------------------PLL:DRP67[14]PLL:DRP67[15]
    - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 2
    RowColumn
    CMT bittile 50
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14--------------------------HCLK_CMT:ENABLE.CKINT0HCLK_CMT:ENABLE.CKINT1HCLK_CMT:ENABLE.RCLK0HCLK_CMT:ENABLE.RCLK1
    15--------------------------HCLK_CMT:ENABLE.CKINT2HCLK_CMT:ENABLE.CKINT3HCLK_CMT:ENABLE.RCLK2HCLK_CMT:ENABLE.RCLK3
    16--------------------------HCLK_CMT:MUX.PERF0[0]HCLK_CMT:MUX.PERF1[0]HCLK_CMT:MUX.PERF2[0]HCLK_CMT:MUX.PERF3[0]
    17--------------------------HCLK_CMT:MUX.PERF0[1]HCLK_CMT:MUX.PERF1[1]HCLK_CMT:MUX.PERF2[1]HCLK_CMT:MUX.PERF3[1]
    18--------------------------HCLK_CMT:MUX.PERF0[2]HCLK_CMT:MUX.PERF1[2]HCLK_CMT:MUX.PERF2[2]HCLK_CMT:MUX.PERF3[2]
    19--------------------------HCLK_CMT:MUX.PERF1[3]HCLK_CMT:MUX.PERF0[3]HCLK_CMT:MUX.PERF3[3]HCLK_CMT:MUX.PERF2[3]
    20--------------------------HCLK_CMT:MUX.PERF0[4]HCLK_CMT:MUX.PERF1[4]HCLK_CMT:MUX.PERF2[4]HCLK_CMT:MUX.PERF3[4]
    21--------------------------HCLK_CMT:ENABLE.HCLK9HCLK_CMT:ENABLE.HCLK8HCLK_CMT:ENABLE.HIN4HCLK_CMT:ENABLE.HIN5
    22--------------------------HCLK_CMT:ENABLE.HCLK7HCLK_CMT:ENABLE.HCLK6HCLK_CMT:ENABLE.HIN6HCLK_CMT:ENABLE.HIN7
    23--------------------------HCLK_CMT:ENABLE.HCLK5HCLK_CMT:ENABLE.HCLK4HCLK_CMT:ENABLE.HIN8HCLK_CMT:ENABLE.HIN9
    24--------------------------HCLK_CMT:ENABLE.HCLK3HCLK_CMT:ENABLE.HCLK2HCLK_CMT:ENABLE.HIN10HCLK_CMT:ENABLE.HIN11
    25--------------------------HCLK_CMT:ENABLE.HCLK1HCLK_CMT:ENABLE.HCLK0HCLK_CMT:ENABLE.HIN12HCLK_CMT:ENABLE.HIN13
    26--------------------------BUFMRCE1:MUX.I[0]BUFMRCE1:MUX.I[1]HCLK_CMT:ENABLE.HCLK10HCLK_CMT:ENABLE.HCLK11
    27--------------------------BUFMRCE1:MUX.I[2]BUFMRCE1:MUX.I[7]BUFMRCE0:ENABLEBUFMRCE1:ENABLE
    28--------------------------BUFMRCE0:MUX.I[2]BUFMRCE0:MUX.I[7]~BUFMRCE0:INV.CE~BUFMRCE1:INV.CE
    29--------------------------BUFMRCE1:MUX.I[6]BUFMRCE1:MUX.I[8]BUFMRCE0:INIT_OUTBUFMRCE1:INIT_OUT
    30--------------------------BUFMRCE1:MUX.I[9]BUFMRCE0:MUX.I[6]--
    31--------------------------BUFMRCE0:MUX.I[8]BUFMRCE0:MUX.I[9]BUFMRCE0:CE_TYPEBUFMRCE1:CE_TYPE
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    CMT bittile 3
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM:CONTROL_0[1, 28, 8][1, 29, 8][1, 28, 9][1, 29, 9][1, 28, 10][1, 29, 10][1, 28, 11][1, 29, 11][1, 28, 12][1, 29, 12][1, 28, 13][1, 29, 13][1, 28, 14][1, 29, 14][1, 28, 15][1, 29, 15]
    MMCM:CONTROL_1[1, 28, 0][1, 29, 0][1, 28, 1][1, 29, 1][1, 28, 2][1, 29, 2][1, 28, 3][1, 29, 3][1, 28, 4][1, 29, 4][1, 28, 5][1, 29, 5][1, 28, 6][1, 29, 6][1, 28, 7][1, 29, 7]
    MMCM:CONTROL_2[0, 28, 56][0, 29, 56][0, 28, 57][0, 29, 57][0, 28, 58][0, 29, 58][0, 28, 59][0, 29, 59][0, 28, 60][0, 29, 60][0, 28, 61][0, 29, 61][0, 28, 62][0, 29, 62][0, 28, 63][0, 29, 63]
    MMCM:CONTROL_3[0, 28, 48][0, 29, 48][0, 28, 49][0, 29, 49][0, 28, 50][0, 29, 50][0, 28, 51][0, 29, 51][0, 28, 52][0, 29, 52][0, 28, 53][0, 29, 53][0, 28, 54][0, 29, 54][0, 28, 55][0, 29, 55]
    MMCM:CONTROL_4[0, 28, 40][0, 29, 40][0, 28, 41][0, 29, 41][0, 28, 42][0, 29, 42][0, 28, 43][0, 29, 43][0, 28, 44][0, 29, 44][0, 28, 45][0, 29, 45][0, 28, 46][0, 29, 46][0, 28, 47][0, 29, 47]
    MMCM:CONTROL_5[0, 28, 32][0, 29, 32][0, 28, 33][0, 29, 33][0, 28, 34][0, 29, 34][0, 28, 35][0, 29, 35][0, 28, 36][0, 29, 36][0, 28, 37][0, 29, 37][0, 28, 38][0, 29, 38][0, 28, 39][0, 29, 39]
    MMCM:CONTROL_6[0, 28, 24][0, 29, 24][0, 28, 25][0, 29, 25][0, 28, 26][0, 29, 26][0, 28, 27][0, 29, 27][0, 28, 28][0, 29, 28][0, 28, 29][0, 29, 29][0, 28, 30][0, 29, 30][0, 28, 31][0, 29, 31]
    MMCM:CONTROL_7[0, 28, 16][0, 29, 16][0, 28, 17][0, 29, 17][0, 28, 18][0, 29, 18][0, 28, 19][0, 29, 19][0, 28, 20][0, 29, 20][0, 28, 21][0, 29, 21][0, 28, 22][0, 29, 22][0, 28, 23][0, 29, 23]
    MMCM:DRP00[15, 28, 56][15, 29, 56][15, 28, 57][15, 29, 57][15, 28, 58][15, 29, 58][15, 28, 59][15, 29, 59][15, 28, 60][15, 29, 60][15, 28, 61][15, 29, 61][15, 28, 62][15, 29, 62][15, 28, 63][15, 29, 63]
    MMCM:DRP01[15, 28, 48][15, 29, 48][15, 28, 49][15, 29, 49][15, 28, 50][15, 29, 50][15, 28, 51][15, 29, 51][15, 28, 52][15, 29, 52][15, 28, 53][15, 29, 53][15, 28, 54][15, 29, 54][15, 28, 55][15, 29, 55]
    MMCM:DRP02[15, 28, 40][15, 29, 40][15, 28, 41][15, 29, 41][15, 28, 42][15, 29, 42][15, 28, 43][15, 29, 43][15, 28, 44][15, 29, 44][15, 28, 45][15, 29, 45][15, 28, 46][15, 29, 46][15, 28, 47][15, 29, 47]
    MMCM:DRP03[15, 28, 32][15, 29, 32][15, 28, 33][15, 29, 33][15, 28, 34][15, 29, 34][15, 28, 35][15, 29, 35][15, 28, 36][15, 29, 36][15, 28, 37][15, 29, 37][15, 28, 38][15, 29, 38][15, 28, 39][15, 29, 39]
    MMCM:DRP04[15, 28, 24][15, 29, 24][15, 28, 25][15, 29, 25][15, 28, 26][15, 29, 26][15, 28, 27][15, 29, 27][15, 28, 28][15, 29, 28][15, 28, 29][15, 29, 29][15, 28, 30][15, 29, 30][15, 28, 31][15, 29, 31]
    MMCM:DRP05[15, 28, 16][15, 29, 16][15, 28, 17][15, 29, 17][15, 28, 18][15, 29, 18][15, 28, 19][15, 29, 19][15, 28, 20][15, 29, 20][15, 28, 21][15, 29, 21][15, 28, 22][15, 29, 22][15, 28, 23][15, 29, 23]
    MMCM:DRP06[15, 28, 8][15, 29, 8][15, 28, 9][15, 29, 9][15, 28, 10][15, 29, 10][15, 28, 11][15, 29, 11][15, 28, 12][15, 29, 12][15, 28, 13][15, 29, 13][15, 28, 14][15, 29, 14][15, 28, 15][15, 29, 15]
    MMCM:DRP07[15, 28, 0][15, 29, 0][15, 28, 1][15, 29, 1][15, 28, 2][15, 29, 2][15, 28, 3][15, 29, 3][15, 28, 4][15, 29, 4][15, 28, 5][15, 29, 5][15, 28, 6][15, 29, 6][15, 28, 7][15, 29, 7]
    MMCM:DRP08[14, 28, 56][14, 29, 56][14, 28, 57][14, 29, 57][14, 28, 58][14, 29, 58][14, 28, 59][14, 29, 59][14, 28, 60][14, 29, 60][14, 28, 61][14, 29, 61][14, 28, 62][14, 29, 62][14, 28, 63][14, 29, 63]
    MMCM:DRP09[14, 28, 48][14, 29, 48][14, 28, 49][14, 29, 49][14, 28, 50][14, 29, 50][14, 28, 51][14, 29, 51][14, 28, 52][14, 29, 52][14, 28, 53][14, 29, 53][14, 28, 54][14, 29, 54][14, 28, 55][14, 29, 55]
    MMCM:DRP0A[14, 28, 40][14, 29, 40][14, 28, 41][14, 29, 41][14, 28, 42][14, 29, 42][14, 28, 43][14, 29, 43][14, 28, 44][14, 29, 44][14, 28, 45][14, 29, 45][14, 28, 46][14, 29, 46][14, 28, 47][14, 29, 47]
    MMCM:DRP0B[14, 28, 32][14, 29, 32][14, 28, 33][14, 29, 33][14, 28, 34][14, 29, 34][14, 28, 35][14, 29, 35][14, 28, 36][14, 29, 36][14, 28, 37][14, 29, 37][14, 28, 38][14, 29, 38][14, 28, 39][14, 29, 39]
    MMCM:DRP0C[14, 28, 24][14, 29, 24][14, 28, 25][14, 29, 25][14, 28, 26][14, 29, 26][14, 28, 27][14, 29, 27][14, 28, 28][14, 29, 28][14, 28, 29][14, 29, 29][14, 28, 30][14, 29, 30][14, 28, 31][14, 29, 31]
    MMCM:DRP0D[14, 28, 16][14, 29, 16][14, 28, 17][14, 29, 17][14, 28, 18][14, 29, 18][14, 28, 19][14, 29, 19][14, 28, 20][14, 29, 20][14, 28, 21][14, 29, 21][14, 28, 22][14, 29, 22][14, 28, 23][14, 29, 23]
    MMCM:DRP0E[14, 28, 8][14, 29, 8][14, 28, 9][14, 29, 9][14, 28, 10][14, 29, 10][14, 28, 11][14, 29, 11][14, 28, 12][14, 29, 12][14, 28, 13][14, 29, 13][14, 28, 14][14, 29, 14][14, 28, 15][14, 29, 15]
    MMCM:DRP0F[14, 28, 0][14, 29, 0][14, 28, 1][14, 29, 1][14, 28, 2][14, 29, 2][14, 28, 3][14, 29, 3][14, 28, 4][14, 29, 4][14, 28, 5][14, 29, 5][14, 28, 6][14, 29, 6][14, 28, 7][14, 29, 7]
    MMCM:DRP10[13, 28, 56][13, 29, 56][13, 28, 57][13, 29, 57][13, 28, 58][13, 29, 58][13, 28, 59][13, 29, 59][13, 28, 60][13, 29, 60][13, 28, 61][13, 29, 61][13, 28, 62][13, 29, 62][13, 28, 63][13, 29, 63]
    MMCM:DRP11[13, 28, 48][13, 29, 48][13, 28, 49][13, 29, 49][13, 28, 50][13, 29, 50][13, 28, 51][13, 29, 51][13, 28, 52][13, 29, 52][13, 28, 53][13, 29, 53][13, 28, 54][13, 29, 54][13, 28, 55][13, 29, 55]
    MMCM:DRP12[13, 28, 40][13, 29, 40][13, 28, 41][13, 29, 41][13, 28, 42][13, 29, 42][13, 28, 43][13, 29, 43][13, 28, 44][13, 29, 44][13, 28, 45][13, 29, 45][13, 28, 46][13, 29, 46][13, 28, 47][13, 29, 47]
    MMCM:DRP13[13, 28, 32][13, 29, 32][13, 28, 33][13, 29, 33][13, 28, 34][13, 29, 34][13, 28, 35][13, 29, 35][13, 28, 36][13, 29, 36][13, 28, 37][13, 29, 37][13, 28, 38][13, 29, 38][13, 28, 39][13, 29, 39]
    MMCM:DRP14[13, 28, 24][13, 29, 24][13, 28, 25][13, 29, 25][13, 28, 26][13, 29, 26][13, 28, 27][13, 29, 27][13, 28, 28][13, 29, 28][13, 28, 29][13, 29, 29][13, 28, 30][13, 29, 30][13, 28, 31][13, 29, 31]
    MMCM:DRP15[13, 28, 16][13, 29, 16][13, 28, 17][13, 29, 17][13, 28, 18][13, 29, 18][13, 28, 19][13, 29, 19][13, 28, 20][13, 29, 20][13, 28, 21][13, 29, 21][13, 28, 22][13, 29, 22][13, 28, 23][13, 29, 23]
    MMCM:DRP16[13, 28, 8][13, 29, 8][13, 28, 9][13, 29, 9][13, 28, 10][13, 29, 10][13, 28, 11][13, 29, 11][13, 28, 12][13, 29, 12][13, 28, 13][13, 29, 13][13, 28, 14][13, 29, 14][13, 28, 15][13, 29, 15]
    MMCM:DRP17[13, 28, 0][13, 29, 0][13, 28, 1][13, 29, 1][13, 28, 2][13, 29, 2][13, 28, 3][13, 29, 3][13, 28, 4][13, 29, 4][13, 28, 5][13, 29, 5][13, 28, 6][13, 29, 6][13, 28, 7][13, 29, 7]
    MMCM:DRP18[12, 28, 56][12, 29, 56][12, 28, 57][12, 29, 57][12, 28, 58][12, 29, 58][12, 28, 59][12, 29, 59][12, 28, 60][12, 29, 60][12, 28, 61][12, 29, 61][12, 28, 62][12, 29, 62][12, 28, 63][12, 29, 63]
    MMCM:DRP19[12, 28, 48][12, 29, 48][12, 28, 49][12, 29, 49][12, 28, 50][12, 29, 50][12, 28, 51][12, 29, 51][12, 28, 52][12, 29, 52][12, 28, 53][12, 29, 53][12, 28, 54][12, 29, 54][12, 28, 55][12, 29, 55]
    MMCM:DRP1A[12, 28, 40][12, 29, 40][12, 28, 41][12, 29, 41][12, 28, 42][12, 29, 42][12, 28, 43][12, 29, 43][12, 28, 44][12, 29, 44][12, 28, 45][12, 29, 45][12, 28, 46][12, 29, 46][12, 28, 47][12, 29, 47]
    MMCM:DRP1B[12, 28, 32][12, 29, 32][12, 28, 33][12, 29, 33][12, 28, 34][12, 29, 34][12, 28, 35][12, 29, 35][12, 28, 36][12, 29, 36][12, 28, 37][12, 29, 37][12, 28, 38][12, 29, 38][12, 28, 39][12, 29, 39]
    MMCM:DRP1C[12, 28, 24][12, 29, 24][12, 28, 25][12, 29, 25][12, 28, 26][12, 29, 26][12, 28, 27][12, 29, 27][12, 28, 28][12, 29, 28][12, 28, 29][12, 29, 29][12, 28, 30][12, 29, 30][12, 28, 31][12, 29, 31]
    MMCM:DRP1D[12, 28, 16][12, 29, 16][12, 28, 17][12, 29, 17][12, 28, 18][12, 29, 18][12, 28, 19][12, 29, 19][12, 28, 20][12, 29, 20][12, 28, 21][12, 29, 21][12, 28, 22][12, 29, 22][12, 28, 23][12, 29, 23]
    MMCM:DRP1E[12, 28, 8][12, 29, 8][12, 28, 9][12, 29, 9][12, 28, 10][12, 29, 10][12, 28, 11][12, 29, 11][12, 28, 12][12, 29, 12][12, 28, 13][12, 29, 13][12, 28, 14][12, 29, 14][12, 28, 15][12, 29, 15]
    MMCM:DRP1F[12, 28, 0][12, 29, 0][12, 28, 1][12, 29, 1][12, 28, 2][12, 29, 2][12, 28, 3][12, 29, 3][12, 28, 4][12, 29, 4][12, 28, 5][12, 29, 5][12, 28, 6][12, 29, 6][12, 28, 7][12, 29, 7]
    MMCM:DRP20[11, 28, 56][11, 29, 56][11, 28, 57][11, 29, 57][11, 28, 58][11, 29, 58][11, 28, 59][11, 29, 59][11, 28, 60][11, 29, 60][11, 28, 61][11, 29, 61][11, 28, 62][11, 29, 62][11, 28, 63][11, 29, 63]
    MMCM:DRP21[11, 28, 48][11, 29, 48][11, 28, 49][11, 29, 49][11, 28, 50][11, 29, 50][11, 28, 51][11, 29, 51][11, 28, 52][11, 29, 52][11, 28, 53][11, 29, 53][11, 28, 54][11, 29, 54][11, 28, 55][11, 29, 55]
    MMCM:DRP22[11, 28, 40][11, 29, 40][11, 28, 41][11, 29, 41][11, 28, 42][11, 29, 42][11, 28, 43][11, 29, 43][11, 28, 44][11, 29, 44][11, 28, 45][11, 29, 45][11, 28, 46][11, 29, 46][11, 28, 47][11, 29, 47]
    MMCM:DRP23[11, 28, 32][11, 29, 32][11, 28, 33][11, 29, 33][11, 28, 34][11, 29, 34][11, 28, 35][11, 29, 35][11, 28, 36][11, 29, 36][11, 28, 37][11, 29, 37][11, 28, 38][11, 29, 38][11, 28, 39][11, 29, 39]
    MMCM:DRP24[11, 28, 24][11, 29, 24][11, 28, 25][11, 29, 25][11, 28, 26][11, 29, 26][11, 28, 27][11, 29, 27][11, 28, 28][11, 29, 28][11, 28, 29][11, 29, 29][11, 28, 30][11, 29, 30][11, 28, 31][11, 29, 31]
    MMCM:DRP25[11, 28, 16][11, 29, 16][11, 28, 17][11, 29, 17][11, 28, 18][11, 29, 18][11, 28, 19][11, 29, 19][11, 28, 20][11, 29, 20][11, 28, 21][11, 29, 21][11, 28, 22][11, 29, 22][11, 28, 23][11, 29, 23]
    MMCM:DRP26[11, 28, 8][11, 29, 8][11, 28, 9][11, 29, 9][11, 28, 10][11, 29, 10][11, 28, 11][11, 29, 11][11, 28, 12][11, 29, 12][11, 28, 13][11, 29, 13][11, 28, 14][11, 29, 14][11, 28, 15][11, 29, 15]
    MMCM:DRP27[11, 28, 0][11, 29, 0][11, 28, 1][11, 29, 1][11, 28, 2][11, 29, 2][11, 28, 3][11, 29, 3][11, 28, 4][11, 29, 4][11, 28, 5][11, 29, 5][11, 28, 6][11, 29, 6][11, 28, 7][11, 29, 7]
    MMCM:DRP28[10, 28, 56][10, 29, 56][10, 28, 57][10, 29, 57][10, 28, 58][10, 29, 58][10, 28, 59][10, 29, 59][10, 28, 60][10, 29, 60][10, 28, 61][10, 29, 61][10, 28, 62][10, 29, 62][10, 28, 63][10, 29, 63]
    MMCM:DRP29[10, 28, 48][10, 29, 48][10, 28, 49][10, 29, 49][10, 28, 50][10, 29, 50][10, 28, 51][10, 29, 51][10, 28, 52][10, 29, 52][10, 28, 53][10, 29, 53][10, 28, 54][10, 29, 54][10, 28, 55][10, 29, 55]
    MMCM:DRP2A[10, 28, 40][10, 29, 40][10, 28, 41][10, 29, 41][10, 28, 42][10, 29, 42][10, 28, 43][10, 29, 43][10, 28, 44][10, 29, 44][10, 28, 45][10, 29, 45][10, 28, 46][10, 29, 46][10, 28, 47][10, 29, 47]
    MMCM:DRP2B[10, 28, 32][10, 29, 32][10, 28, 33][10, 29, 33][10, 28, 34][10, 29, 34][10, 28, 35][10, 29, 35][10, 28, 36][10, 29, 36][10, 28, 37][10, 29, 37][10, 28, 38][10, 29, 38][10, 28, 39][10, 29, 39]
    MMCM:DRP2C[10, 28, 24][10, 29, 24][10, 28, 25][10, 29, 25][10, 28, 26][10, 29, 26][10, 28, 27][10, 29, 27][10, 28, 28][10, 29, 28][10, 28, 29][10, 29, 29][10, 28, 30][10, 29, 30][10, 28, 31][10, 29, 31]
    MMCM:DRP2D[10, 28, 16][10, 29, 16][10, 28, 17][10, 29, 17][10, 28, 18][10, 29, 18][10, 28, 19][10, 29, 19][10, 28, 20][10, 29, 20][10, 28, 21][10, 29, 21][10, 28, 22][10, 29, 22][10, 28, 23][10, 29, 23]
    MMCM:DRP2E[10, 28, 8][10, 29, 8][10, 28, 9][10, 29, 9][10, 28, 10][10, 29, 10][10, 28, 11][10, 29, 11][10, 28, 12][10, 29, 12][10, 28, 13][10, 29, 13][10, 28, 14][10, 29, 14][10, 28, 15][10, 29, 15]
    MMCM:DRP2F[10, 28, 0][10, 29, 0][10, 28, 1][10, 29, 1][10, 28, 2][10, 29, 2][10, 28, 3][10, 29, 3][10, 28, 4][10, 29, 4][10, 28, 5][10, 29, 5][10, 28, 6][10, 29, 6][10, 28, 7][10, 29, 7]
    MMCM:DRP30[9, 28, 56][9, 29, 56][9, 28, 57][9, 29, 57][9, 28, 58][9, 29, 58][9, 28, 59][9, 29, 59][9, 28, 60][9, 29, 60][9, 28, 61][9, 29, 61][9, 28, 62][9, 29, 62][9, 28, 63][9, 29, 63]
    MMCM:DRP31[9, 28, 48][9, 29, 48][9, 28, 49][9, 29, 49][9, 28, 50][9, 29, 50][9, 28, 51][9, 29, 51][9, 28, 52][9, 29, 52][9, 28, 53][9, 29, 53][9, 28, 54][9, 29, 54][9, 28, 55][9, 29, 55]
    MMCM:DRP32[9, 28, 40][9, 29, 40][9, 28, 41][9, 29, 41][9, 28, 42][9, 29, 42][9, 28, 43][9, 29, 43][9, 28, 44][9, 29, 44][9, 28, 45][9, 29, 45][9, 28, 46][9, 29, 46][9, 28, 47][9, 29, 47]
    MMCM:DRP33[9, 28, 32][9, 29, 32][9, 28, 33][9, 29, 33][9, 28, 34][9, 29, 34][9, 28, 35][9, 29, 35][9, 28, 36][9, 29, 36][9, 28, 37][9, 29, 37][9, 28, 38][9, 29, 38][9, 28, 39][9, 29, 39]
    MMCM:DRP34[9, 28, 24][9, 29, 24][9, 28, 25][9, 29, 25][9, 28, 26][9, 29, 26][9, 28, 27][9, 29, 27][9, 28, 28][9, 29, 28][9, 28, 29][9, 29, 29][9, 28, 30][9, 29, 30][9, 28, 31][9, 29, 31]
    MMCM:DRP35[9, 28, 16][9, 29, 16][9, 28, 17][9, 29, 17][9, 28, 18][9, 29, 18][9, 28, 19][9, 29, 19][9, 28, 20][9, 29, 20][9, 28, 21][9, 29, 21][9, 28, 22][9, 29, 22][9, 28, 23][9, 29, 23]
    MMCM:DRP36[9, 28, 8][9, 29, 8][9, 28, 9][9, 29, 9][9, 28, 10][9, 29, 10][9, 28, 11][9, 29, 11][9, 28, 12][9, 29, 12][9, 28, 13][9, 29, 13][9, 28, 14][9, 29, 14][9, 28, 15][9, 29, 15]
    MMCM:DRP37[9, 28, 0][9, 29, 0][9, 28, 1][9, 29, 1][9, 28, 2][9, 29, 2][9, 28, 3][9, 29, 3][9, 28, 4][9, 29, 4][9, 28, 5][9, 29, 5][9, 28, 6][9, 29, 6][9, 28, 7][9, 29, 7]
    MMCM:DRP38[8, 28, 56][8, 29, 56][8, 28, 57][8, 29, 57][8, 28, 58][8, 29, 58][8, 28, 59][8, 29, 59][8, 28, 60][8, 29, 60][8, 28, 61][8, 29, 61][8, 28, 62][8, 29, 62][8, 28, 63][8, 29, 63]
    MMCM:DRP39[8, 28, 48][8, 29, 48][8, 28, 49][8, 29, 49][8, 28, 50][8, 29, 50][8, 28, 51][8, 29, 51][8, 28, 52][8, 29, 52][8, 28, 53][8, 29, 53][8, 28, 54][8, 29, 54][8, 28, 55][8, 29, 55]
    MMCM:DRP3A[8, 28, 40][8, 29, 40][8, 28, 41][8, 29, 41][8, 28, 42][8, 29, 42][8, 28, 43][8, 29, 43][8, 28, 44][8, 29, 44][8, 28, 45][8, 29, 45][8, 28, 46][8, 29, 46][8, 28, 47][8, 29, 47]
    MMCM:DRP3B[8, 28, 32][8, 29, 32][8, 28, 33][8, 29, 33][8, 28, 34][8, 29, 34][8, 28, 35][8, 29, 35][8, 28, 36][8, 29, 36][8, 28, 37][8, 29, 37][8, 28, 38][8, 29, 38][8, 28, 39][8, 29, 39]
    MMCM:DRP3C[8, 28, 24][8, 29, 24][8, 28, 25][8, 29, 25][8, 28, 26][8, 29, 26][8, 28, 27][8, 29, 27][8, 28, 28][8, 29, 28][8, 28, 29][8, 29, 29][8, 28, 30][8, 29, 30][8, 28, 31][8, 29, 31]
    MMCM:DRP3D[8, 28, 16][8, 29, 16][8, 28, 17][8, 29, 17][8, 28, 18][8, 29, 18][8, 28, 19][8, 29, 19][8, 28, 20][8, 29, 20][8, 28, 21][8, 29, 21][8, 28, 22][8, 29, 22][8, 28, 23][8, 29, 23]
    MMCM:DRP3E[8, 28, 8][8, 29, 8][8, 28, 9][8, 29, 9][8, 28, 10][8, 29, 10][8, 28, 11][8, 29, 11][8, 28, 12][8, 29, 12][8, 28, 13][8, 29, 13][8, 28, 14][8, 29, 14][8, 28, 15][8, 29, 15]
    MMCM:DRP3F[8, 28, 0][8, 29, 0][8, 28, 1][8, 29, 1][8, 28, 2][8, 29, 2][8, 28, 3][8, 29, 3][8, 28, 4][8, 29, 4][8, 28, 5][8, 29, 5][8, 28, 6][8, 29, 6][8, 28, 7][8, 29, 7]
    MMCM:DRP40[7, 28, 56][7, 29, 56][7, 28, 57][7, 29, 57][7, 28, 58][7, 29, 58][7, 28, 59][7, 29, 59][7, 28, 60][7, 29, 60][7, 28, 61][7, 29, 61][7, 28, 62][7, 29, 62][7, 28, 63][7, 29, 63]
    MMCM:DRP41[7, 28, 48][7, 29, 48][7, 28, 49][7, 29, 49][7, 28, 50][7, 29, 50][7, 28, 51][7, 29, 51][7, 28, 52][7, 29, 52][7, 28, 53][7, 29, 53][7, 28, 54][7, 29, 54][7, 28, 55][7, 29, 55]
    MMCM:DRP42[7, 28, 40][7, 29, 40][7, 28, 41][7, 29, 41][7, 28, 42][7, 29, 42][7, 28, 43][7, 29, 43][7, 28, 44][7, 29, 44][7, 28, 45][7, 29, 45][7, 28, 46][7, 29, 46][7, 28, 47][7, 29, 47]
    MMCM:DRP43[7, 28, 32][7, 29, 32][7, 28, 33][7, 29, 33][7, 28, 34][7, 29, 34][7, 28, 35][7, 29, 35][7, 28, 36][7, 29, 36][7, 28, 37][7, 29, 37][7, 28, 38][7, 29, 38][7, 28, 39][7, 29, 39]
    MMCM:DRP44[7, 28, 24][7, 29, 24][7, 28, 25][7, 29, 25][7, 28, 26][7, 29, 26][7, 28, 27][7, 29, 27][7, 28, 28][7, 29, 28][7, 28, 29][7, 29, 29][7, 28, 30][7, 29, 30][7, 28, 31][7, 29, 31]
    MMCM:DRP45[7, 28, 16][7, 29, 16][7, 28, 17][7, 29, 17][7, 28, 18][7, 29, 18][7, 28, 19][7, 29, 19][7, 28, 20][7, 29, 20][7, 28, 21][7, 29, 21][7, 28, 22][7, 29, 22][7, 28, 23][7, 29, 23]
    MMCM:DRP46[7, 28, 8][7, 29, 8][7, 28, 9][7, 29, 9][7, 28, 10][7, 29, 10][7, 28, 11][7, 29, 11][7, 28, 12][7, 29, 12][7, 28, 13][7, 29, 13][7, 28, 14][7, 29, 14][7, 28, 15][7, 29, 15]
    MMCM:DRP47[7, 28, 0][7, 29, 0][7, 28, 1][7, 29, 1][7, 28, 2][7, 29, 2][7, 28, 3][7, 29, 3][7, 28, 4][7, 29, 4][7, 28, 5][7, 29, 5][7, 28, 6][7, 29, 6][7, 28, 7][7, 29, 7]
    MMCM:DRP48[6, 28, 56][6, 29, 56][6, 28, 57][6, 29, 57][6, 28, 58][6, 29, 58][6, 28, 59][6, 29, 59][6, 28, 60][6, 29, 60][6, 28, 61][6, 29, 61][6, 28, 62][6, 29, 62][6, 28, 63][6, 29, 63]
    MMCM:DRP49[6, 28, 48][6, 29, 48][6, 28, 49][6, 29, 49][6, 28, 50][6, 29, 50][6, 28, 51][6, 29, 51][6, 28, 52][6, 29, 52][6, 28, 53][6, 29, 53][6, 28, 54][6, 29, 54][6, 28, 55][6, 29, 55]
    MMCM:DRP4A[6, 28, 40][6, 29, 40][6, 28, 41][6, 29, 41][6, 28, 42][6, 29, 42][6, 28, 43][6, 29, 43][6, 28, 44][6, 29, 44][6, 28, 45][6, 29, 45][6, 28, 46][6, 29, 46][6, 28, 47][6, 29, 47]
    MMCM:DRP4B[6, 28, 32][6, 29, 32][6, 28, 33][6, 29, 33][6, 28, 34][6, 29, 34][6, 28, 35][6, 29, 35][6, 28, 36][6, 29, 36][6, 28, 37][6, 29, 37][6, 28, 38][6, 29, 38][6, 28, 39][6, 29, 39]
    MMCM:DRP4C[6, 28, 24][6, 29, 24][6, 28, 25][6, 29, 25][6, 28, 26][6, 29, 26][6, 28, 27][6, 29, 27][6, 28, 28][6, 29, 28][6, 28, 29][6, 29, 29][6, 28, 30][6, 29, 30][6, 28, 31][6, 29, 31]
    MMCM:DRP4D[6, 28, 16][6, 29, 16][6, 28, 17][6, 29, 17][6, 28, 18][6, 29, 18][6, 28, 19][6, 29, 19][6, 28, 20][6, 29, 20][6, 28, 21][6, 29, 21][6, 28, 22][6, 29, 22][6, 28, 23][6, 29, 23]
    MMCM:DRP4E[6, 28, 8][6, 29, 8][6, 28, 9][6, 29, 9][6, 28, 10][6, 29, 10][6, 28, 11][6, 29, 11][6, 28, 12][6, 29, 12][6, 28, 13][6, 29, 13][6, 28, 14][6, 29, 14][6, 28, 15][6, 29, 15]
    MMCM:DRP4F[6, 28, 0][6, 29, 0][6, 28, 1][6, 29, 1][6, 28, 2][6, 29, 2][6, 28, 3][6, 29, 3][6, 28, 4][6, 29, 4][6, 28, 5][6, 29, 5][6, 28, 6][6, 29, 6][6, 28, 7][6, 29, 7]
    MMCM:DRP50[5, 28, 56][5, 29, 56][5, 28, 57][5, 29, 57][5, 28, 58][5, 29, 58][5, 28, 59][5, 29, 59][5, 28, 60][5, 29, 60][5, 28, 61][5, 29, 61][5, 28, 62][5, 29, 62][5, 28, 63][5, 29, 63]
    MMCM:DRP51[5, 28, 48][5, 29, 48][5, 28, 49][5, 29, 49][5, 28, 50][5, 29, 50][5, 28, 51][5, 29, 51][5, 28, 52][5, 29, 52][5, 28, 53][5, 29, 53][5, 28, 54][5, 29, 54][5, 28, 55][5, 29, 55]
    MMCM:DRP52[5, 28, 40][5, 29, 40][5, 28, 41][5, 29, 41][5, 28, 42][5, 29, 42][5, 28, 43][5, 29, 43][5, 28, 44][5, 29, 44][5, 28, 45][5, 29, 45][5, 28, 46][5, 29, 46][5, 28, 47][5, 29, 47]
    MMCM:DRP53[5, 28, 32][5, 29, 32][5, 28, 33][5, 29, 33][5, 28, 34][5, 29, 34][5, 28, 35][5, 29, 35][5, 28, 36][5, 29, 36][5, 28, 37][5, 29, 37][5, 28, 38][5, 29, 38][5, 28, 39][5, 29, 39]
    MMCM:DRP54[5, 28, 24][5, 29, 24][5, 28, 25][5, 29, 25][5, 28, 26][5, 29, 26][5, 28, 27][5, 29, 27][5, 28, 28][5, 29, 28][5, 28, 29][5, 29, 29][5, 28, 30][5, 29, 30][5, 28, 31][5, 29, 31]
    MMCM:DRP55[5, 28, 16][5, 29, 16][5, 28, 17][5, 29, 17][5, 28, 18][5, 29, 18][5, 28, 19][5, 29, 19][5, 28, 20][5, 29, 20][5, 28, 21][5, 29, 21][5, 28, 22][5, 29, 22][5, 28, 23][5, 29, 23]
    MMCM:DRP56[5, 28, 8][5, 29, 8][5, 28, 9][5, 29, 9][5, 28, 10][5, 29, 10][5, 28, 11][5, 29, 11][5, 28, 12][5, 29, 12][5, 28, 13][5, 29, 13][5, 28, 14][5, 29, 14][5, 28, 15][5, 29, 15]
    MMCM:DRP57[5, 28, 0][5, 29, 0][5, 28, 1][5, 29, 1][5, 28, 2][5, 29, 2][5, 28, 3][5, 29, 3][5, 28, 4][5, 29, 4][5, 28, 5][5, 29, 5][5, 28, 6][5, 29, 6][5, 28, 7][5, 29, 7]
    MMCM:DRP58[4, 28, 56][4, 29, 56][4, 28, 57][4, 29, 57][4, 28, 58][4, 29, 58][4, 28, 59][4, 29, 59][4, 28, 60][4, 29, 60][4, 28, 61][4, 29, 61][4, 28, 62][4, 29, 62][4, 28, 63][4, 29, 63]
    MMCM:DRP59[4, 28, 48][4, 29, 48][4, 28, 49][4, 29, 49][4, 28, 50][4, 29, 50][4, 28, 51][4, 29, 51][4, 28, 52][4, 29, 52][4, 28, 53][4, 29, 53][4, 28, 54][4, 29, 54][4, 28, 55][4, 29, 55]
    MMCM:DRP5A[4, 28, 40][4, 29, 40][4, 28, 41][4, 29, 41][4, 28, 42][4, 29, 42][4, 28, 43][4, 29, 43][4, 28, 44][4, 29, 44][4, 28, 45][4, 29, 45][4, 28, 46][4, 29, 46][4, 28, 47][4, 29, 47]
    MMCM:DRP5B[4, 28, 32][4, 29, 32][4, 28, 33][4, 29, 33][4, 28, 34][4, 29, 34][4, 28, 35][4, 29, 35][4, 28, 36][4, 29, 36][4, 28, 37][4, 29, 37][4, 28, 38][4, 29, 38][4, 28, 39][4, 29, 39]
    MMCM:DRP5C[4, 28, 24][4, 29, 24][4, 28, 25][4, 29, 25][4, 28, 26][4, 29, 26][4, 28, 27][4, 29, 27][4, 28, 28][4, 29, 28][4, 28, 29][4, 29, 29][4, 28, 30][4, 29, 30][4, 28, 31][4, 29, 31]
    MMCM:DRP5D[4, 28, 16][4, 29, 16][4, 28, 17][4, 29, 17][4, 28, 18][4, 29, 18][4, 28, 19][4, 29, 19][4, 28, 20][4, 29, 20][4, 28, 21][4, 29, 21][4, 28, 22][4, 29, 22][4, 28, 23][4, 29, 23]
    MMCM:DRP5E[4, 28, 8][4, 29, 8][4, 28, 9][4, 29, 9][4, 28, 10][4, 29, 10][4, 28, 11][4, 29, 11][4, 28, 12][4, 29, 12][4, 28, 13][4, 29, 13][4, 28, 14][4, 29, 14][4, 28, 15][4, 29, 15]
    MMCM:DRP5F[4, 28, 0][4, 29, 0][4, 28, 1][4, 29, 1][4, 28, 2][4, 29, 2][4, 28, 3][4, 29, 3][4, 28, 4][4, 29, 4][4, 28, 5][4, 29, 5][4, 28, 6][4, 29, 6][4, 28, 7][4, 29, 7]
    MMCM:DRP60[3, 28, 56][3, 29, 56][3, 28, 57][3, 29, 57][3, 28, 58][3, 29, 58][3, 28, 59][3, 29, 59][3, 28, 60][3, 29, 60][3, 28, 61][3, 29, 61][3, 28, 62][3, 29, 62][3, 28, 63][3, 29, 63]
    MMCM:DRP61[3, 28, 48][3, 29, 48][3, 28, 49][3, 29, 49][3, 28, 50][3, 29, 50][3, 28, 51][3, 29, 51][3, 28, 52][3, 29, 52][3, 28, 53][3, 29, 53][3, 28, 54][3, 29, 54][3, 28, 55][3, 29, 55]
    MMCM:DRP62[3, 28, 40][3, 29, 40][3, 28, 41][3, 29, 41][3, 28, 42][3, 29, 42][3, 28, 43][3, 29, 43][3, 28, 44][3, 29, 44][3, 28, 45][3, 29, 45][3, 28, 46][3, 29, 46][3, 28, 47][3, 29, 47]
    MMCM:DRP63[3, 28, 32][3, 29, 32][3, 28, 33][3, 29, 33][3, 28, 34][3, 29, 34][3, 28, 35][3, 29, 35][3, 28, 36][3, 29, 36][3, 28, 37][3, 29, 37][3, 28, 38][3, 29, 38][3, 28, 39][3, 29, 39]
    MMCM:DRP64[3, 28, 24][3, 29, 24][3, 28, 25][3, 29, 25][3, 28, 26][3, 29, 26][3, 28, 27][3, 29, 27][3, 28, 28][3, 29, 28][3, 28, 29][3, 29, 29][3, 28, 30][3, 29, 30][3, 28, 31][3, 29, 31]
    MMCM:DRP65[3, 28, 16][3, 29, 16][3, 28, 17][3, 29, 17][3, 28, 18][3, 29, 18][3, 28, 19][3, 29, 19][3, 28, 20][3, 29, 20][3, 28, 21][3, 29, 21][3, 28, 22][3, 29, 22][3, 28, 23][3, 29, 23]
    MMCM:DRP66[3, 28, 8][3, 29, 8][3, 28, 9][3, 29, 9][3, 28, 10][3, 29, 10][3, 28, 11][3, 29, 11][3, 28, 12][3, 29, 12][3, 28, 13][3, 29, 13][3, 28, 14][3, 29, 14][3, 28, 15][3, 29, 15]
    MMCM:DRP67[3, 28, 0][3, 29, 0][3, 28, 1][3, 29, 1][3, 28, 2][3, 29, 2][3, 28, 3][3, 29, 3][3, 28, 4][3, 29, 4][3, 28, 5][3, 29, 5][3, 28, 6][3, 29, 6][3, 28, 7][3, 29, 7]
    MMCM:DRP68[2, 28, 56][2, 29, 56][2, 28, 57][2, 29, 57][2, 28, 58][2, 29, 58][2, 28, 59][2, 29, 59][2, 28, 60][2, 29, 60][2, 28, 61][2, 29, 61][2, 28, 62][2, 29, 62][2, 28, 63][2, 29, 63]
    MMCM:DRP69[2, 28, 48][2, 29, 48][2, 28, 49][2, 29, 49][2, 28, 50][2, 29, 50][2, 28, 51][2, 29, 51][2, 28, 52][2, 29, 52][2, 28, 53][2, 29, 53][2, 28, 54][2, 29, 54][2, 28, 55][2, 29, 55]
    MMCM:DRP6A[2, 28, 40][2, 29, 40][2, 28, 41][2, 29, 41][2, 28, 42][2, 29, 42][2, 28, 43][2, 29, 43][2, 28, 44][2, 29, 44][2, 28, 45][2, 29, 45][2, 28, 46][2, 29, 46][2, 28, 47][2, 29, 47]
    MMCM:DRP6B[2, 28, 32][2, 29, 32][2, 28, 33][2, 29, 33][2, 28, 34][2, 29, 34][2, 28, 35][2, 29, 35][2, 28, 36][2, 29, 36][2, 28, 37][2, 29, 37][2, 28, 38][2, 29, 38][2, 28, 39][2, 29, 39]
    MMCM:DRP6C[2, 28, 24][2, 29, 24][2, 28, 25][2, 29, 25][2, 28, 26][2, 29, 26][2, 28, 27][2, 29, 27][2, 28, 28][2, 29, 28][2, 28, 29][2, 29, 29][2, 28, 30][2, 29, 30][2, 28, 31][2, 29, 31]
    MMCM:DRP6D[2, 28, 16][2, 29, 16][2, 28, 17][2, 29, 17][2, 28, 18][2, 29, 18][2, 28, 19][2, 29, 19][2, 28, 20][2, 29, 20][2, 28, 21][2, 29, 21][2, 28, 22][2, 29, 22][2, 28, 23][2, 29, 23]
    MMCM:DRP6E[2, 28, 8][2, 29, 8][2, 28, 9][2, 29, 9][2, 28, 10][2, 29, 10][2, 28, 11][2, 29, 11][2, 28, 12][2, 29, 12][2, 28, 13][2, 29, 13][2, 28, 14][2, 29, 14][2, 28, 15][2, 29, 15]
    MMCM:DRP6F[2, 28, 0][2, 29, 0][2, 28, 1][2, 29, 1][2, 28, 2][2, 29, 2][2, 28, 3][2, 29, 3][2, 28, 4][2, 29, 4][2, 28, 5][2, 29, 5][2, 28, 6][2, 29, 6][2, 28, 7][2, 29, 7]
    MMCM:DRP70[1, 28, 56][1, 29, 56][1, 28, 57][1, 29, 57][1, 28, 58][1, 29, 58][1, 28, 59][1, 29, 59][1, 28, 60][1, 29, 60][1, 28, 61][1, 29, 61][1, 28, 62][1, 29, 62][1, 28, 63][1, 29, 63]
    MMCM:DRP71[1, 28, 48][1, 29, 48][1, 28, 49][1, 29, 49][1, 28, 50][1, 29, 50][1, 28, 51][1, 29, 51][1, 28, 52][1, 29, 52][1, 28, 53][1, 29, 53][1, 28, 54][1, 29, 54][1, 28, 55][1, 29, 55]
    MMCM:DRP72[1, 28, 40][1, 29, 40][1, 28, 41][1, 29, 41][1, 28, 42][1, 29, 42][1, 28, 43][1, 29, 43][1, 28, 44][1, 29, 44][1, 28, 45][1, 29, 45][1, 28, 46][1, 29, 46][1, 28, 47][1, 29, 47]
    MMCM:DRP73[1, 28, 32][1, 29, 32][1, 28, 33][1, 29, 33][1, 28, 34][1, 29, 34][1, 28, 35][1, 29, 35][1, 28, 36][1, 29, 36][1, 28, 37][1, 29, 37][1, 28, 38][1, 29, 38][1, 28, 39][1, 29, 39]
    MMCM:DRP74[1, 28, 24][1, 29, 24][1, 28, 25][1, 29, 25][1, 28, 26][1, 29, 26][1, 28, 27][1, 29, 27][1, 28, 28][1, 29, 28][1, 28, 29][1, 29, 29][1, 28, 30][1, 29, 30][1, 28, 31][1, 29, 31]
    MMCM:DRP75[1, 28, 16][1, 29, 16][1, 28, 17][1, 29, 17][1, 28, 18][1, 29, 18][1, 28, 19][1, 29, 19][1, 28, 20][1, 29, 20][1, 28, 21][1, 29, 21][1, 28, 22][1, 29, 22][1, 28, 23][1, 29, 23]
    MMCM:DRP76[1, 28, 8][1, 29, 8][1, 28, 9][1, 29, 9][1, 28, 10][1, 29, 10][1, 28, 11][1, 29, 11][1, 28, 12][1, 29, 12][1, 28, 13][1, 29, 13][1, 28, 14][1, 29, 14][1, 28, 15][1, 29, 15]
    MMCM:DRP77[1, 28, 0][1, 29, 0][1, 28, 1][1, 29, 1][1, 28, 2][1, 29, 2][1, 28, 3][1, 29, 3][1, 28, 4][1, 29, 4][1, 28, 5][1, 29, 5][1, 28, 6][1, 29, 6][1, 28, 7][1, 29, 7]
    MMCM:DRP78[0, 28, 56][0, 29, 56][0, 28, 57][0, 29, 57][0, 28, 58][0, 29, 58][0, 28, 59][0, 29, 59][0, 28, 60][0, 29, 60][0, 28, 61][0, 29, 61][0, 28, 62][0, 29, 62][0, 28, 63][0, 29, 63]
    MMCM:DRP79[0, 28, 48][0, 29, 48][0, 28, 49][0, 29, 49][0, 28, 50][0, 29, 50][0, 28, 51][0, 29, 51][0, 28, 52][0, 29, 52][0, 28, 53][0, 29, 53][0, 28, 54][0, 29, 54][0, 28, 55][0, 29, 55]
    MMCM:DRP7A[0, 28, 40][0, 29, 40][0, 28, 41][0, 29, 41][0, 28, 42][0, 29, 42][0, 28, 43][0, 29, 43][0, 28, 44][0, 29, 44][0, 28, 45][0, 29, 45][0, 28, 46][0, 29, 46][0, 28, 47][0, 29, 47]
    MMCM:DRP7B[0, 28, 32][0, 29, 32][0, 28, 33][0, 29, 33][0, 28, 34][0, 29, 34][0, 28, 35][0, 29, 35][0, 28, 36][0, 29, 36][0, 28, 37][0, 29, 37][0, 28, 38][0, 29, 38][0, 28, 39][0, 29, 39]
    MMCM:DRP7C[0, 28, 24][0, 29, 24][0, 28, 25][0, 29, 25][0, 28, 26][0, 29, 26][0, 28, 27][0, 29, 27][0, 28, 28][0, 29, 28][0, 28, 29][0, 29, 29][0, 28, 30][0, 29, 30][0, 28, 31][0, 29, 31]
    MMCM:DRP7D[0, 28, 16][0, 29, 16][0, 28, 17][0, 29, 17][0, 28, 18][0, 29, 18][0, 28, 19][0, 29, 19][0, 28, 20][0, 29, 20][0, 28, 21][0, 29, 21][0, 28, 22][0, 29, 22][0, 28, 23][0, 29, 23]
    MMCM:DRP7E[0, 28, 8][0, 29, 8][0, 28, 9][0, 29, 9][0, 28, 10][0, 29, 10][0, 28, 11][0, 29, 11][0, 28, 12][0, 29, 12][0, 28, 13][0, 29, 13][0, 28, 14][0, 29, 14][0, 28, 15][0, 29, 15]
    MMCM:DRP7F[0, 28, 0][0, 29, 0][0, 28, 1][0, 29, 1][0, 28, 2][0, 29, 2][0, 28, 3][0, 29, 3][0, 28, 4][0, 29, 4][0, 28, 5][0, 29, 5][0, 28, 6][0, 29, 6][0, 28, 7][0, 29, 7]
    PHASER_REF:CONTROL_0[26, 29, 55][26, 28, 55][26, 29, 54][26, 28, 54][26, 29, 53][26, 28, 53][26, 29, 52][26, 28, 52][26, 29, 51][26, 28, 51][26, 29, 50][26, 28, 50][26, 29, 49][26, 28, 49][26, 29, 48][26, 28, 48]
    PHASER_REF:CONTROL_1[26, 29, 47][26, 28, 47][26, 29, 46][26, 28, 46][26, 29, 45][26, 28, 45][26, 29, 44][26, 28, 44][26, 29, 43][26, 28, 43][26, 29, 42][26, 28, 42][26, 29, 41][26, 28, 41][26, 29, 40][26, 28, 40]
    PHASER_REF:CONTROL_2[26, 29, 39][26, 28, 39][26, 29, 38][26, 28, 38][26, 29, 37][26, 28, 37][26, 29, 36][26, 28, 36][26, 29, 35][26, 28, 35][26, 29, 34][26, 28, 34][26, 29, 33][26, 28, 33][26, 29, 32][26, 28, 32]
    PHASER_REF:CONTROL_3[26, 29, 15][26, 28, 15][26, 29, 14][26, 28, 14][26, 29, 13][26, 28, 13][26, 29, 12][26, 28, 12][26, 29, 11][26, 28, 11][26, 29, 10][26, 28, 10][26, 29, 9][26, 28, 9][26, 29, 8][26, 28, 8]
    PHASER_REF:CONTROL_4[27, 29, 7][27, 28, 7][27, 29, 6][27, 28, 6][27, 29, 5][27, 28, 5][27, 29, 4][27, 28, 4][27, 29, 3][27, 28, 3][27, 29, 2][27, 28, 2][27, 29, 1][27, 28, 1][27, 29, 0][27, 28, 0]
    PHASER_REF:CONTROL_5[27, 29, 15][27, 28, 15][27, 29, 14][27, 28, 14][27, 29, 13][27, 28, 13][27, 29, 12][27, 28, 12][27, 29, 11][27, 28, 11][27, 29, 10][27, 28, 10][27, 29, 9][27, 28, 9][27, 29, 8][27, 28, 8]
    PLL:CONTROL_0[48, 29, 55][48, 28, 55][48, 29, 54][48, 28, 54][48, 29, 53][48, 28, 53][48, 29, 52][48, 28, 52][48, 29, 51][48, 28, 51][48, 29, 50][48, 28, 50][48, 29, 49][48, 28, 49][48, 29, 48][48, 28, 48]
    PLL:CONTROL_1[48, 29, 63][48, 28, 63][48, 29, 62][48, 28, 62][48, 29, 61][48, 28, 61][48, 29, 60][48, 28, 60][48, 29, 59][48, 28, 59][48, 29, 58][48, 28, 58][48, 29, 57][48, 28, 57][48, 29, 56][48, 28, 56]
    PLL:CONTROL_2[49, 29, 7][49, 28, 7][49, 29, 6][49, 28, 6][49, 29, 5][49, 28, 5][49, 29, 4][49, 28, 4][49, 29, 3][49, 28, 3][49, 29, 2][49, 28, 2][49, 29, 1][49, 28, 1][49, 29, 0][49, 28, 0]
    PLL:CONTROL_3[49, 29, 15][49, 28, 15][49, 29, 14][49, 28, 14][49, 29, 13][49, 28, 13][49, 29, 12][49, 28, 12][49, 29, 11][49, 28, 11][49, 29, 10][49, 28, 10][49, 29, 9][49, 28, 9][49, 29, 8][49, 28, 8]
    PLL:CONTROL_4[49, 29, 23][49, 28, 23][49, 29, 22][49, 28, 22][49, 29, 21][49, 28, 21][49, 29, 20][49, 28, 20][49, 29, 19][49, 28, 19][49, 29, 18][49, 28, 18][49, 29, 17][49, 28, 17][49, 29, 16][49, 28, 16]
    PLL:CONTROL_5[49, 29, 31][49, 28, 31][49, 29, 30][49, 28, 30][49, 29, 29][49, 28, 29][49, 29, 28][49, 28, 28][49, 29, 27][49, 28, 27][49, 29, 26][49, 28, 26][49, 29, 25][49, 28, 25][49, 29, 24][49, 28, 24]
    PLL:CONTROL_6[49, 29, 39][49, 28, 39][49, 29, 38][49, 28, 38][49, 29, 37][49, 28, 37][49, 29, 36][49, 28, 36][49, 29, 35][49, 28, 35][49, 29, 34][49, 28, 34][49, 29, 33][49, 28, 33][49, 29, 32][49, 28, 32]
    PLL:CONTROL_7[49, 29, 47][49, 28, 47][49, 29, 46][49, 28, 46][49, 29, 45][49, 28, 45][49, 29, 44][49, 28, 44][49, 29, 43][49, 28, 43][49, 29, 42][49, 28, 42][49, 29, 41][49, 28, 41][49, 29, 40][49, 28, 40]
    PLL:DRP00[37, 29, 7][37, 28, 7][37, 29, 6][37, 28, 6][37, 29, 5][37, 28, 5][37, 29, 4][37, 28, 4][37, 29, 3][37, 28, 3][37, 29, 2][37, 28, 2][37, 29, 1][37, 28, 1][37, 29, 0][37, 28, 0]
    PLL:DRP01[37, 29, 15][37, 28, 15][37, 29, 14][37, 28, 14][37, 29, 13][37, 28, 13][37, 29, 12][37, 28, 12][37, 29, 11][37, 28, 11][37, 29, 10][37, 28, 10][37, 29, 9][37, 28, 9][37, 29, 8][37, 28, 8]
    PLL:DRP02[37, 29, 23][37, 28, 23][37, 29, 22][37, 28, 22][37, 29, 21][37, 28, 21][37, 29, 20][37, 28, 20][37, 29, 19][37, 28, 19][37, 29, 18][37, 28, 18][37, 29, 17][37, 28, 17][37, 29, 16][37, 28, 16]
    PLL:DRP03[37, 29, 31][37, 28, 31][37, 29, 30][37, 28, 30][37, 29, 29][37, 28, 29][37, 29, 28][37, 28, 28][37, 29, 27][37, 28, 27][37, 29, 26][37, 28, 26][37, 29, 25][37, 28, 25][37, 29, 24][37, 28, 24]
    PLL:DRP04[37, 29, 39][37, 28, 39][37, 29, 38][37, 28, 38][37, 29, 37][37, 28, 37][37, 29, 36][37, 28, 36][37, 29, 35][37, 28, 35][37, 29, 34][37, 28, 34][37, 29, 33][37, 28, 33][37, 29, 32][37, 28, 32]
    PLL:DRP05[37, 29, 47][37, 28, 47][37, 29, 46][37, 28, 46][37, 29, 45][37, 28, 45][37, 29, 44][37, 28, 44][37, 29, 43][37, 28, 43][37, 29, 42][37, 28, 42][37, 29, 41][37, 28, 41][37, 29, 40][37, 28, 40]
    PLL:DRP06[37, 29, 55][37, 28, 55][37, 29, 54][37, 28, 54][37, 29, 53][37, 28, 53][37, 29, 52][37, 28, 52][37, 29, 51][37, 28, 51][37, 29, 50][37, 28, 50][37, 29, 49][37, 28, 49][37, 29, 48][37, 28, 48]
    PLL:DRP07[37, 29, 63][37, 28, 63][37, 29, 62][37, 28, 62][37, 29, 61][37, 28, 61][37, 29, 60][37, 28, 60][37, 29, 59][37, 28, 59][37, 29, 58][37, 28, 58][37, 29, 57][37, 28, 57][37, 29, 56][37, 28, 56]
    PLL:DRP08[38, 29, 7][38, 28, 7][38, 29, 6][38, 28, 6][38, 29, 5][38, 28, 5][38, 29, 4][38, 28, 4][38, 29, 3][38, 28, 3][38, 29, 2][38, 28, 2][38, 29, 1][38, 28, 1][38, 29, 0][38, 28, 0]
    PLL:DRP09[38, 29, 15][38, 28, 15][38, 29, 14][38, 28, 14][38, 29, 13][38, 28, 13][38, 29, 12][38, 28, 12][38, 29, 11][38, 28, 11][38, 29, 10][38, 28, 10][38, 29, 9][38, 28, 9][38, 29, 8][38, 28, 8]
    PLL:DRP0A[38, 29, 23][38, 28, 23][38, 29, 22][38, 28, 22][38, 29, 21][38, 28, 21][38, 29, 20][38, 28, 20][38, 29, 19][38, 28, 19][38, 29, 18][38, 28, 18][38, 29, 17][38, 28, 17][38, 29, 16][38, 28, 16]
    PLL:DRP0B[38, 29, 31][38, 28, 31][38, 29, 30][38, 28, 30][38, 29, 29][38, 28, 29][38, 29, 28][38, 28, 28][38, 29, 27][38, 28, 27][38, 29, 26][38, 28, 26][38, 29, 25][38, 28, 25][38, 29, 24][38, 28, 24]
    PLL:DRP0C[38, 29, 39][38, 28, 39][38, 29, 38][38, 28, 38][38, 29, 37][38, 28, 37][38, 29, 36][38, 28, 36][38, 29, 35][38, 28, 35][38, 29, 34][38, 28, 34][38, 29, 33][38, 28, 33][38, 29, 32][38, 28, 32]
    PLL:DRP0D[38, 29, 47][38, 28, 47][38, 29, 46][38, 28, 46][38, 29, 45][38, 28, 45][38, 29, 44][38, 28, 44][38, 29, 43][38, 28, 43][38, 29, 42][38, 28, 42][38, 29, 41][38, 28, 41][38, 29, 40][38, 28, 40]
    PLL:DRP0E[38, 29, 55][38, 28, 55][38, 29, 54][38, 28, 54][38, 29, 53][38, 28, 53][38, 29, 52][38, 28, 52][38, 29, 51][38, 28, 51][38, 29, 50][38, 28, 50][38, 29, 49][38, 28, 49][38, 29, 48][38, 28, 48]
    PLL:DRP0F[38, 29, 63][38, 28, 63][38, 29, 62][38, 28, 62][38, 29, 61][38, 28, 61][38, 29, 60][38, 28, 60][38, 29, 59][38, 28, 59][38, 29, 58][38, 28, 58][38, 29, 57][38, 28, 57][38, 29, 56][38, 28, 56]
    PLL:DRP10[39, 29, 7][39, 28, 7][39, 29, 6][39, 28, 6][39, 29, 5][39, 28, 5][39, 29, 4][39, 28, 4][39, 29, 3][39, 28, 3][39, 29, 2][39, 28, 2][39, 29, 1][39, 28, 1][39, 29, 0][39, 28, 0]
    PLL:DRP11[39, 29, 15][39, 28, 15][39, 29, 14][39, 28, 14][39, 29, 13][39, 28, 13][39, 29, 12][39, 28, 12][39, 29, 11][39, 28, 11][39, 29, 10][39, 28, 10][39, 29, 9][39, 28, 9][39, 29, 8][39, 28, 8]
    PLL:DRP12[39, 29, 23][39, 28, 23][39, 29, 22][39, 28, 22][39, 29, 21][39, 28, 21][39, 29, 20][39, 28, 20][39, 29, 19][39, 28, 19][39, 29, 18][39, 28, 18][39, 29, 17][39, 28, 17][39, 29, 16][39, 28, 16]
    PLL:DRP13[39, 29, 31][39, 28, 31][39, 29, 30][39, 28, 30][39, 29, 29][39, 28, 29][39, 29, 28][39, 28, 28][39, 29, 27][39, 28, 27][39, 29, 26][39, 28, 26][39, 29, 25][39, 28, 25][39, 29, 24][39, 28, 24]
    PLL:DRP14[39, 29, 39][39, 28, 39][39, 29, 38][39, 28, 38][39, 29, 37][39, 28, 37][39, 29, 36][39, 28, 36][39, 29, 35][39, 28, 35][39, 29, 34][39, 28, 34][39, 29, 33][39, 28, 33][39, 29, 32][39, 28, 32]
    PLL:DRP15[39, 29, 47][39, 28, 47][39, 29, 46][39, 28, 46][39, 29, 45][39, 28, 45][39, 29, 44][39, 28, 44][39, 29, 43][39, 28, 43][39, 29, 42][39, 28, 42][39, 29, 41][39, 28, 41][39, 29, 40][39, 28, 40]
    PLL:DRP16[39, 29, 55][39, 28, 55][39, 29, 54][39, 28, 54][39, 29, 53][39, 28, 53][39, 29, 52][39, 28, 52][39, 29, 51][39, 28, 51][39, 29, 50][39, 28, 50][39, 29, 49][39, 28, 49][39, 29, 48][39, 28, 48]
    PLL:DRP17[39, 29, 63][39, 28, 63][39, 29, 62][39, 28, 62][39, 29, 61][39, 28, 61][39, 29, 60][39, 28, 60][39, 29, 59][39, 28, 59][39, 29, 58][39, 28, 58][39, 29, 57][39, 28, 57][39, 29, 56][39, 28, 56]
    PLL:DRP18[40, 29, 7][40, 28, 7][40, 29, 6][40, 28, 6][40, 29, 5][40, 28, 5][40, 29, 4][40, 28, 4][40, 29, 3][40, 28, 3][40, 29, 2][40, 28, 2][40, 29, 1][40, 28, 1][40, 29, 0][40, 28, 0]
    PLL:DRP19[40, 29, 15][40, 28, 15][40, 29, 14][40, 28, 14][40, 29, 13][40, 28, 13][40, 29, 12][40, 28, 12][40, 29, 11][40, 28, 11][40, 29, 10][40, 28, 10][40, 29, 9][40, 28, 9][40, 29, 8][40, 28, 8]
    PLL:DRP1A[40, 29, 23][40, 28, 23][40, 29, 22][40, 28, 22][40, 29, 21][40, 28, 21][40, 29, 20][40, 28, 20][40, 29, 19][40, 28, 19][40, 29, 18][40, 28, 18][40, 29, 17][40, 28, 17][40, 29, 16][40, 28, 16]
    PLL:DRP1B[40, 29, 31][40, 28, 31][40, 29, 30][40, 28, 30][40, 29, 29][40, 28, 29][40, 29, 28][40, 28, 28][40, 29, 27][40, 28, 27][40, 29, 26][40, 28, 26][40, 29, 25][40, 28, 25][40, 29, 24][40, 28, 24]
    PLL:DRP1C[40, 29, 39][40, 28, 39][40, 29, 38][40, 28, 38][40, 29, 37][40, 28, 37][40, 29, 36][40, 28, 36][40, 29, 35][40, 28, 35][40, 29, 34][40, 28, 34][40, 29, 33][40, 28, 33][40, 29, 32][40, 28, 32]
    PLL:DRP1D[40, 29, 47][40, 28, 47][40, 29, 46][40, 28, 46][40, 29, 45][40, 28, 45][40, 29, 44][40, 28, 44][40, 29, 43][40, 28, 43][40, 29, 42][40, 28, 42][40, 29, 41][40, 28, 41][40, 29, 40][40, 28, 40]
    PLL:DRP1E[40, 29, 55][40, 28, 55][40, 29, 54][40, 28, 54][40, 29, 53][40, 28, 53][40, 29, 52][40, 28, 52][40, 29, 51][40, 28, 51][40, 29, 50][40, 28, 50][40, 29, 49][40, 28, 49][40, 29, 48][40, 28, 48]
    PLL:DRP1F[40, 29, 63][40, 28, 63][40, 29, 62][40, 28, 62][40, 29, 61][40, 28, 61][40, 29, 60][40, 28, 60][40, 29, 59][40, 28, 59][40, 29, 58][40, 28, 58][40, 29, 57][40, 28, 57][40, 29, 56][40, 28, 56]
    PLL:DRP20[41, 29, 7][41, 28, 7][41, 29, 6][41, 28, 6][41, 29, 5][41, 28, 5][41, 29, 4][41, 28, 4][41, 29, 3][41, 28, 3][41, 29, 2][41, 28, 2][41, 29, 1][41, 28, 1][41, 29, 0][41, 28, 0]
    PLL:DRP21[41, 29, 15][41, 28, 15][41, 29, 14][41, 28, 14][41, 29, 13][41, 28, 13][41, 29, 12][41, 28, 12][41, 29, 11][41, 28, 11][41, 29, 10][41, 28, 10][41, 29, 9][41, 28, 9][41, 29, 8][41, 28, 8]
    PLL:DRP22[41, 29, 23][41, 28, 23][41, 29, 22][41, 28, 22][41, 29, 21][41, 28, 21][41, 29, 20][41, 28, 20][41, 29, 19][41, 28, 19][41, 29, 18][41, 28, 18][41, 29, 17][41, 28, 17][41, 29, 16][41, 28, 16]
    PLL:DRP23[41, 29, 31][41, 28, 31][41, 29, 30][41, 28, 30][41, 29, 29][41, 28, 29][41, 29, 28][41, 28, 28][41, 29, 27][41, 28, 27][41, 29, 26][41, 28, 26][41, 29, 25][41, 28, 25][41, 29, 24][41, 28, 24]
    PLL:DRP24[41, 29, 39][41, 28, 39][41, 29, 38][41, 28, 38][41, 29, 37][41, 28, 37][41, 29, 36][41, 28, 36][41, 29, 35][41, 28, 35][41, 29, 34][41, 28, 34][41, 29, 33][41, 28, 33][41, 29, 32][41, 28, 32]
    PLL:DRP25[41, 29, 47][41, 28, 47][41, 29, 46][41, 28, 46][41, 29, 45][41, 28, 45][41, 29, 44][41, 28, 44][41, 29, 43][41, 28, 43][41, 29, 42][41, 28, 42][41, 29, 41][41, 28, 41][41, 29, 40][41, 28, 40]
    PLL:DRP26[41, 29, 55][41, 28, 55][41, 29, 54][41, 28, 54][41, 29, 53][41, 28, 53][41, 29, 52][41, 28, 52][41, 29, 51][41, 28, 51][41, 29, 50][41, 28, 50][41, 29, 49][41, 28, 49][41, 29, 48][41, 28, 48]
    PLL:DRP27[41, 29, 63][41, 28, 63][41, 29, 62][41, 28, 62][41, 29, 61][41, 28, 61][41, 29, 60][41, 28, 60][41, 29, 59][41, 28, 59][41, 29, 58][41, 28, 58][41, 29, 57][41, 28, 57][41, 29, 56][41, 28, 56]
    PLL:DRP28[42, 29, 7][42, 28, 7][42, 29, 6][42, 28, 6][42, 29, 5][42, 28, 5][42, 29, 4][42, 28, 4][42, 29, 3][42, 28, 3][42, 29, 2][42, 28, 2][42, 29, 1][42, 28, 1][42, 29, 0][42, 28, 0]
    PLL:DRP29[42, 29, 15][42, 28, 15][42, 29, 14][42, 28, 14][42, 29, 13][42, 28, 13][42, 29, 12][42, 28, 12][42, 29, 11][42, 28, 11][42, 29, 10][42, 28, 10][42, 29, 9][42, 28, 9][42, 29, 8][42, 28, 8]
    PLL:DRP2A[42, 29, 23][42, 28, 23][42, 29, 22][42, 28, 22][42, 29, 21][42, 28, 21][42, 29, 20][42, 28, 20][42, 29, 19][42, 28, 19][42, 29, 18][42, 28, 18][42, 29, 17][42, 28, 17][42, 29, 16][42, 28, 16]
    PLL:DRP2B[42, 29, 31][42, 28, 31][42, 29, 30][42, 28, 30][42, 29, 29][42, 28, 29][42, 29, 28][42, 28, 28][42, 29, 27][42, 28, 27][42, 29, 26][42, 28, 26][42, 29, 25][42, 28, 25][42, 29, 24][42, 28, 24]
    PLL:DRP2C[42, 29, 39][42, 28, 39][42, 29, 38][42, 28, 38][42, 29, 37][42, 28, 37][42, 29, 36][42, 28, 36][42, 29, 35][42, 28, 35][42, 29, 34][42, 28, 34][42, 29, 33][42, 28, 33][42, 29, 32][42, 28, 32]
    PLL:DRP2D[42, 29, 47][42, 28, 47][42, 29, 46][42, 28, 46][42, 29, 45][42, 28, 45][42, 29, 44][42, 28, 44][42, 29, 43][42, 28, 43][42, 29, 42][42, 28, 42][42, 29, 41][42, 28, 41][42, 29, 40][42, 28, 40]
    PLL:DRP2E[42, 29, 55][42, 28, 55][42, 29, 54][42, 28, 54][42, 29, 53][42, 28, 53][42, 29, 52][42, 28, 52][42, 29, 51][42, 28, 51][42, 29, 50][42, 28, 50][42, 29, 49][42, 28, 49][42, 29, 48][42, 28, 48]
    PLL:DRP2F[42, 29, 63][42, 28, 63][42, 29, 62][42, 28, 62][42, 29, 61][42, 28, 61][42, 29, 60][42, 28, 60][42, 29, 59][42, 28, 59][42, 29, 58][42, 28, 58][42, 29, 57][42, 28, 57][42, 29, 56][42, 28, 56]
    PLL:DRP30[43, 29, 7][43, 28, 7][43, 29, 6][43, 28, 6][43, 29, 5][43, 28, 5][43, 29, 4][43, 28, 4][43, 29, 3][43, 28, 3][43, 29, 2][43, 28, 2][43, 29, 1][43, 28, 1][43, 29, 0][43, 28, 0]
    PLL:DRP31[43, 29, 15][43, 28, 15][43, 29, 14][43, 28, 14][43, 29, 13][43, 28, 13][43, 29, 12][43, 28, 12][43, 29, 11][43, 28, 11][43, 29, 10][43, 28, 10][43, 29, 9][43, 28, 9][43, 29, 8][43, 28, 8]
    PLL:DRP32[43, 29, 23][43, 28, 23][43, 29, 22][43, 28, 22][43, 29, 21][43, 28, 21][43, 29, 20][43, 28, 20][43, 29, 19][43, 28, 19][43, 29, 18][43, 28, 18][43, 29, 17][43, 28, 17][43, 29, 16][43, 28, 16]
    PLL:DRP33[43, 29, 31][43, 28, 31][43, 29, 30][43, 28, 30][43, 29, 29][43, 28, 29][43, 29, 28][43, 28, 28][43, 29, 27][43, 28, 27][43, 29, 26][43, 28, 26][43, 29, 25][43, 28, 25][43, 29, 24][43, 28, 24]
    PLL:DRP34[43, 29, 39][43, 28, 39][43, 29, 38][43, 28, 38][43, 29, 37][43, 28, 37][43, 29, 36][43, 28, 36][43, 29, 35][43, 28, 35][43, 29, 34][43, 28, 34][43, 29, 33][43, 28, 33][43, 29, 32][43, 28, 32]
    PLL:DRP35[43, 29, 47][43, 28, 47][43, 29, 46][43, 28, 46][43, 29, 45][43, 28, 45][43, 29, 44][43, 28, 44][43, 29, 43][43, 28, 43][43, 29, 42][43, 28, 42][43, 29, 41][43, 28, 41][43, 29, 40][43, 28, 40]
    PLL:DRP36[43, 29, 55][43, 28, 55][43, 29, 54][43, 28, 54][43, 29, 53][43, 28, 53][43, 29, 52][43, 28, 52][43, 29, 51][43, 28, 51][43, 29, 50][43, 28, 50][43, 29, 49][43, 28, 49][43, 29, 48][43, 28, 48]
    PLL:DRP37[43, 29, 63][43, 28, 63][43, 29, 62][43, 28, 62][43, 29, 61][43, 28, 61][43, 29, 60][43, 28, 60][43, 29, 59][43, 28, 59][43, 29, 58][43, 28, 58][43, 29, 57][43, 28, 57][43, 29, 56][43, 28, 56]
    PLL:DRP38[44, 29, 7][44, 28, 7][44, 29, 6][44, 28, 6][44, 29, 5][44, 28, 5][44, 29, 4][44, 28, 4][44, 29, 3][44, 28, 3][44, 29, 2][44, 28, 2][44, 29, 1][44, 28, 1][44, 29, 0][44, 28, 0]
    PLL:DRP39[44, 29, 15][44, 28, 15][44, 29, 14][44, 28, 14][44, 29, 13][44, 28, 13][44, 29, 12][44, 28, 12][44, 29, 11][44, 28, 11][44, 29, 10][44, 28, 10][44, 29, 9][44, 28, 9][44, 29, 8][44, 28, 8]
    PLL:DRP3A[44, 29, 23][44, 28, 23][44, 29, 22][44, 28, 22][44, 29, 21][44, 28, 21][44, 29, 20][44, 28, 20][44, 29, 19][44, 28, 19][44, 29, 18][44, 28, 18][44, 29, 17][44, 28, 17][44, 29, 16][44, 28, 16]
    PLL:DRP3B[44, 29, 31][44, 28, 31][44, 29, 30][44, 28, 30][44, 29, 29][44, 28, 29][44, 29, 28][44, 28, 28][44, 29, 27][44, 28, 27][44, 29, 26][44, 28, 26][44, 29, 25][44, 28, 25][44, 29, 24][44, 28, 24]
    PLL:DRP3C[44, 29, 39][44, 28, 39][44, 29, 38][44, 28, 38][44, 29, 37][44, 28, 37][44, 29, 36][44, 28, 36][44, 29, 35][44, 28, 35][44, 29, 34][44, 28, 34][44, 29, 33][44, 28, 33][44, 29, 32][44, 28, 32]
    PLL:DRP3D[44, 29, 47][44, 28, 47][44, 29, 46][44, 28, 46][44, 29, 45][44, 28, 45][44, 29, 44][44, 28, 44][44, 29, 43][44, 28, 43][44, 29, 42][44, 28, 42][44, 29, 41][44, 28, 41][44, 29, 40][44, 28, 40]
    PLL:DRP3E[44, 29, 55][44, 28, 55][44, 29, 54][44, 28, 54][44, 29, 53][44, 28, 53][44, 29, 52][44, 28, 52][44, 29, 51][44, 28, 51][44, 29, 50][44, 28, 50][44, 29, 49][44, 28, 49][44, 29, 48][44, 28, 48]
    PLL:DRP3F[44, 29, 63][44, 28, 63][44, 29, 62][44, 28, 62][44, 29, 61][44, 28, 61][44, 29, 60][44, 28, 60][44, 29, 59][44, 28, 59][44, 29, 58][44, 28, 58][44, 29, 57][44, 28, 57][44, 29, 56][44, 28, 56]
    PLL:DRP40[45, 29, 7][45, 28, 7][45, 29, 6][45, 28, 6][45, 29, 5][45, 28, 5][45, 29, 4][45, 28, 4][45, 29, 3][45, 28, 3][45, 29, 2][45, 28, 2][45, 29, 1][45, 28, 1][45, 29, 0][45, 28, 0]
    PLL:DRP41[45, 29, 15][45, 28, 15][45, 29, 14][45, 28, 14][45, 29, 13][45, 28, 13][45, 29, 12][45, 28, 12][45, 29, 11][45, 28, 11][45, 29, 10][45, 28, 10][45, 29, 9][45, 28, 9][45, 29, 8][45, 28, 8]
    PLL:DRP42[45, 29, 23][45, 28, 23][45, 29, 22][45, 28, 22][45, 29, 21][45, 28, 21][45, 29, 20][45, 28, 20][45, 29, 19][45, 28, 19][45, 29, 18][45, 28, 18][45, 29, 17][45, 28, 17][45, 29, 16][45, 28, 16]
    PLL:DRP43[45, 29, 31][45, 28, 31][45, 29, 30][45, 28, 30][45, 29, 29][45, 28, 29][45, 29, 28][45, 28, 28][45, 29, 27][45, 28, 27][45, 29, 26][45, 28, 26][45, 29, 25][45, 28, 25][45, 29, 24][45, 28, 24]
    PLL:DRP44[45, 29, 39][45, 28, 39][45, 29, 38][45, 28, 38][45, 29, 37][45, 28, 37][45, 29, 36][45, 28, 36][45, 29, 35][45, 28, 35][45, 29, 34][45, 28, 34][45, 29, 33][45, 28, 33][45, 29, 32][45, 28, 32]
    PLL:DRP45[45, 29, 47][45, 28, 47][45, 29, 46][45, 28, 46][45, 29, 45][45, 28, 45][45, 29, 44][45, 28, 44][45, 29, 43][45, 28, 43][45, 29, 42][45, 28, 42][45, 29, 41][45, 28, 41][45, 29, 40][45, 28, 40]
    PLL:DRP46[45, 29, 55][45, 28, 55][45, 29, 54][45, 28, 54][45, 29, 53][45, 28, 53][45, 29, 52][45, 28, 52][45, 29, 51][45, 28, 51][45, 29, 50][45, 28, 50][45, 29, 49][45, 28, 49][45, 29, 48][45, 28, 48]
    PLL:DRP47[45, 29, 63][45, 28, 63][45, 29, 62][45, 28, 62][45, 29, 61][45, 28, 61][45, 29, 60][45, 28, 60][45, 29, 59][45, 28, 59][45, 29, 58][45, 28, 58][45, 29, 57][45, 28, 57][45, 29, 56][45, 28, 56]
    PLL:DRP48[46, 29, 7][46, 28, 7][46, 29, 6][46, 28, 6][46, 29, 5][46, 28, 5][46, 29, 4][46, 28, 4][46, 29, 3][46, 28, 3][46, 29, 2][46, 28, 2][46, 29, 1][46, 28, 1][46, 29, 0][46, 28, 0]
    PLL:DRP49[46, 29, 15][46, 28, 15][46, 29, 14][46, 28, 14][46, 29, 13][46, 28, 13][46, 29, 12][46, 28, 12][46, 29, 11][46, 28, 11][46, 29, 10][46, 28, 10][46, 29, 9][46, 28, 9][46, 29, 8][46, 28, 8]
    PLL:DRP4A[46, 29, 23][46, 28, 23][46, 29, 22][46, 28, 22][46, 29, 21][46, 28, 21][46, 29, 20][46, 28, 20][46, 29, 19][46, 28, 19][46, 29, 18][46, 28, 18][46, 29, 17][46, 28, 17][46, 29, 16][46, 28, 16]
    PLL:DRP4B[46, 29, 31][46, 28, 31][46, 29, 30][46, 28, 30][46, 29, 29][46, 28, 29][46, 29, 28][46, 28, 28][46, 29, 27][46, 28, 27][46, 29, 26][46, 28, 26][46, 29, 25][46, 28, 25][46, 29, 24][46, 28, 24]
    PLL:DRP4C[46, 29, 39][46, 28, 39][46, 29, 38][46, 28, 38][46, 29, 37][46, 28, 37][46, 29, 36][46, 28, 36][46, 29, 35][46, 28, 35][46, 29, 34][46, 28, 34][46, 29, 33][46, 28, 33][46, 29, 32][46, 28, 32]
    PLL:DRP4D[46, 29, 47][46, 28, 47][46, 29, 46][46, 28, 46][46, 29, 45][46, 28, 45][46, 29, 44][46, 28, 44][46, 29, 43][46, 28, 43][46, 29, 42][46, 28, 42][46, 29, 41][46, 28, 41][46, 29, 40][46, 28, 40]
    PLL:DRP4E[46, 29, 55][46, 28, 55][46, 29, 54][46, 28, 54][46, 29, 53][46, 28, 53][46, 29, 52][46, 28, 52][46, 29, 51][46, 28, 51][46, 29, 50][46, 28, 50][46, 29, 49][46, 28, 49][46, 29, 48][46, 28, 48]
    PLL:DRP4F[46, 29, 63][46, 28, 63][46, 29, 62][46, 28, 62][46, 29, 61][46, 28, 61][46, 29, 60][46, 28, 60][46, 29, 59][46, 28, 59][46, 29, 58][46, 28, 58][46, 29, 57][46, 28, 57][46, 29, 56][46, 28, 56]
    PLL:DRP50[47, 29, 7][47, 28, 7][47, 29, 6][47, 28, 6][47, 29, 5][47, 28, 5][47, 29, 4][47, 28, 4][47, 29, 3][47, 28, 3][47, 29, 2][47, 28, 2][47, 29, 1][47, 28, 1][47, 29, 0][47, 28, 0]
    PLL:DRP51[47, 29, 15][47, 28, 15][47, 29, 14][47, 28, 14][47, 29, 13][47, 28, 13][47, 29, 12][47, 28, 12][47, 29, 11][47, 28, 11][47, 29, 10][47, 28, 10][47, 29, 9][47, 28, 9][47, 29, 8][47, 28, 8]
    PLL:DRP52[47, 29, 23][47, 28, 23][47, 29, 22][47, 28, 22][47, 29, 21][47, 28, 21][47, 29, 20][47, 28, 20][47, 29, 19][47, 28, 19][47, 29, 18][47, 28, 18][47, 29, 17][47, 28, 17][47, 29, 16][47, 28, 16]
    PLL:DRP53[47, 29, 31][47, 28, 31][47, 29, 30][47, 28, 30][47, 29, 29][47, 28, 29][47, 29, 28][47, 28, 28][47, 29, 27][47, 28, 27][47, 29, 26][47, 28, 26][47, 29, 25][47, 28, 25][47, 29, 24][47, 28, 24]
    PLL:DRP54[47, 29, 39][47, 28, 39][47, 29, 38][47, 28, 38][47, 29, 37][47, 28, 37][47, 29, 36][47, 28, 36][47, 29, 35][47, 28, 35][47, 29, 34][47, 28, 34][47, 29, 33][47, 28, 33][47, 29, 32][47, 28, 32]
    PLL:DRP55[47, 29, 47][47, 28, 47][47, 29, 46][47, 28, 46][47, 29, 45][47, 28, 45][47, 29, 44][47, 28, 44][47, 29, 43][47, 28, 43][47, 29, 42][47, 28, 42][47, 29, 41][47, 28, 41][47, 29, 40][47, 28, 40]
    PLL:DRP56[47, 29, 55][47, 28, 55][47, 29, 54][47, 28, 54][47, 29, 53][47, 28, 53][47, 29, 52][47, 28, 52][47, 29, 51][47, 28, 51][47, 29, 50][47, 28, 50][47, 29, 49][47, 28, 49][47, 29, 48][47, 28, 48]
    PLL:DRP57[47, 29, 63][47, 28, 63][47, 29, 62][47, 28, 62][47, 29, 61][47, 28, 61][47, 29, 60][47, 28, 60][47, 29, 59][47, 28, 59][47, 29, 58][47, 28, 58][47, 29, 57][47, 28, 57][47, 29, 56][47, 28, 56]
    PLL:DRP58[48, 29, 7][48, 28, 7][48, 29, 6][48, 28, 6][48, 29, 5][48, 28, 5][48, 29, 4][48, 28, 4][48, 29, 3][48, 28, 3][48, 29, 2][48, 28, 2][48, 29, 1][48, 28, 1][48, 29, 0][48, 28, 0]
    PLL:DRP59[48, 29, 15][48, 28, 15][48, 29, 14][48, 28, 14][48, 29, 13][48, 28, 13][48, 29, 12][48, 28, 12][48, 29, 11][48, 28, 11][48, 29, 10][48, 28, 10][48, 29, 9][48, 28, 9][48, 29, 8][48, 28, 8]
    PLL:DRP5A[48, 29, 23][48, 28, 23][48, 29, 22][48, 28, 22][48, 29, 21][48, 28, 21][48, 29, 20][48, 28, 20][48, 29, 19][48, 28, 19][48, 29, 18][48, 28, 18][48, 29, 17][48, 28, 17][48, 29, 16][48, 28, 16]
    PLL:DRP5B[48, 29, 31][48, 28, 31][48, 29, 30][48, 28, 30][48, 29, 29][48, 28, 29][48, 29, 28][48, 28, 28][48, 29, 27][48, 28, 27][48, 29, 26][48, 28, 26][48, 29, 25][48, 28, 25][48, 29, 24][48, 28, 24]
    PLL:DRP5C[48, 29, 39][48, 28, 39][48, 29, 38][48, 28, 38][48, 29, 37][48, 28, 37][48, 29, 36][48, 28, 36][48, 29, 35][48, 28, 35][48, 29, 34][48, 28, 34][48, 29, 33][48, 28, 33][48, 29, 32][48, 28, 32]
    PLL:DRP5D[48, 29, 47][48, 28, 47][48, 29, 46][48, 28, 46][48, 29, 45][48, 28, 45][48, 29, 44][48, 28, 44][48, 29, 43][48, 28, 43][48, 29, 42][48, 28, 42][48, 29, 41][48, 28, 41][48, 29, 40][48, 28, 40]
    PLL:DRP5E[48, 29, 55][48, 28, 55][48, 29, 54][48, 28, 54][48, 29, 53][48, 28, 53][48, 29, 52][48, 28, 52][48, 29, 51][48, 28, 51][48, 29, 50][48, 28, 50][48, 29, 49][48, 28, 49][48, 29, 48][48, 28, 48]
    PLL:DRP5F[48, 29, 63][48, 28, 63][48, 29, 62][48, 28, 62][48, 29, 61][48, 28, 61][48, 29, 60][48, 28, 60][48, 29, 59][48, 28, 59][48, 29, 58][48, 28, 58][48, 29, 57][48, 28, 57][48, 29, 56][48, 28, 56]
    PLL:DRP60[49, 29, 7][49, 28, 7][49, 29, 6][49, 28, 6][49, 29, 5][49, 28, 5][49, 29, 4][49, 28, 4][49, 29, 3][49, 28, 3][49, 29, 2][49, 28, 2][49, 29, 1][49, 28, 1][49, 29, 0][49, 28, 0]
    PLL:DRP61[49, 29, 15][49, 28, 15][49, 29, 14][49, 28, 14][49, 29, 13][49, 28, 13][49, 29, 12][49, 28, 12][49, 29, 11][49, 28, 11][49, 29, 10][49, 28, 10][49, 29, 9][49, 28, 9][49, 29, 8][49, 28, 8]
    PLL:DRP62[49, 29, 23][49, 28, 23][49, 29, 22][49, 28, 22][49, 29, 21][49, 28, 21][49, 29, 20][49, 28, 20][49, 29, 19][49, 28, 19][49, 29, 18][49, 28, 18][49, 29, 17][49, 28, 17][49, 29, 16][49, 28, 16]
    PLL:DRP63[49, 29, 31][49, 28, 31][49, 29, 30][49, 28, 30][49, 29, 29][49, 28, 29][49, 29, 28][49, 28, 28][49, 29, 27][49, 28, 27][49, 29, 26][49, 28, 26][49, 29, 25][49, 28, 25][49, 29, 24][49, 28, 24]
    PLL:DRP64[49, 29, 39][49, 28, 39][49, 29, 38][49, 28, 38][49, 29, 37][49, 28, 37][49, 29, 36][49, 28, 36][49, 29, 35][49, 28, 35][49, 29, 34][49, 28, 34][49, 29, 33][49, 28, 33][49, 29, 32][49, 28, 32]
    PLL:DRP65[49, 29, 47][49, 28, 47][49, 29, 46][49, 28, 46][49, 29, 45][49, 28, 45][49, 29, 44][49, 28, 44][49, 29, 43][49, 28, 43][49, 29, 42][49, 28, 42][49, 29, 41][49, 28, 41][49, 29, 40][49, 28, 40]
    PLL:DRP66[49, 29, 55][49, 28, 55][49, 29, 54][49, 28, 54][49, 29, 53][49, 28, 53][49, 29, 52][49, 28, 52][49, 29, 51][49, 28, 51][49, 29, 50][49, 28, 50][49, 29, 49][49, 28, 49][49, 29, 48][49, 28, 48]
    PLL:DRP67[49, 29, 63][49, 28, 63][49, 29, 62][49, 28, 62][49, 29, 61][49, 28, 61][49, 29, 60][49, 28, 60][49, 29, 59][49, 28, 59][49, 29, 58][49, 28, 58][49, 29, 57][49, 28, 57][49, 29, 56][49, 28, 56]
    Non-inverted[15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
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    CMT bittile 4
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM:CLKFBIN_HT[13, 28, 2][13, 29, 2][13, 28, 3][13, 29, 3][13, 28, 4][13, 29, 4]
    MMCM:CLKFBIN_LT[13, 28, 5][13, 29, 5][13, 28, 6][13, 29, 6][13, 28, 7][13, 29, 7]
    MMCM:CLKFBOUT_DT[13, 28, 21][13, 29, 21][13, 28, 22][13, 29, 22][13, 28, 23][13, 29, 23]
    MMCM:CLKFBOUT_HT[13, 28, 26][13, 29, 26][13, 28, 27][13, 29, 27][13, 28, 28][13, 29, 28]
    MMCM:CLKFBOUT_LT[13, 28, 29][13, 29, 29][13, 28, 30][13, 29, 30][13, 28, 31][13, 29, 31]
    MMCM:CLKOUT0_DT[14, 28, 53][14, 29, 53][14, 28, 54][14, 29, 54][14, 28, 55][14, 29, 55]
    MMCM:CLKOUT0_HT[14, 28, 58][14, 29, 58][14, 28, 59][14, 29, 59][14, 28, 60][14, 29, 60]
    MMCM:CLKOUT0_LT[14, 28, 61][14, 29, 61][14, 28, 62][14, 29, 62][14, 28, 63][14, 29, 63]
    MMCM:CLKOUT1_DT[14, 28, 37][14, 29, 37][14, 28, 38][14, 29, 38][14, 28, 39][14, 29, 39]
    MMCM:CLKOUT1_HT[14, 28, 42][14, 29, 42][14, 28, 43][14, 29, 43][14, 28, 44][14, 29, 44]
    MMCM:CLKOUT1_LT[14, 28, 45][14, 29, 45][14, 28, 46][14, 29, 46][14, 28, 47][14, 29, 47]
    MMCM:CLKOUT2_DT[14, 28, 21][14, 29, 21][14, 28, 22][14, 29, 22][14, 28, 23][14, 29, 23]
    MMCM:CLKOUT2_HT[14, 28, 26][14, 29, 26][14, 28, 27][14, 29, 27][14, 28, 28][14, 29, 28]
    MMCM:CLKOUT2_LT[14, 28, 29][14, 29, 29][14, 28, 30][14, 29, 30][14, 28, 31][14, 29, 31]
    MMCM:CLKOUT3_DT[14, 28, 5][14, 29, 5][14, 28, 6][14, 29, 6][14, 28, 7][14, 29, 7]
    MMCM:CLKOUT3_HT[14, 28, 10][14, 29, 10][14, 28, 11][14, 29, 11][14, 28, 12][14, 29, 12]
    MMCM:CLKOUT3_LT[14, 28, 13][14, 29, 13][14, 28, 14][14, 29, 14][14, 28, 15][14, 29, 15]
    MMCM:CLKOUT4_DT[13, 28, 53][13, 29, 53][13, 28, 54][13, 29, 54][13, 28, 55][13, 29, 55]
    MMCM:CLKOUT4_HT[13, 28, 58][13, 29, 58][13, 28, 59][13, 29, 59][13, 28, 60][13, 29, 60]
    MMCM:CLKOUT4_LT[13, 28, 61][13, 29, 61][13, 28, 62][13, 29, 62][13, 28, 63][13, 29, 63]
    MMCM:CLKOUT5_DT[15, 28, 5][15, 29, 5][15, 28, 6][15, 29, 6][15, 28, 7][15, 29, 7]
    MMCM:CLKOUT5_HT[15, 28, 10][15, 29, 10][15, 28, 11][15, 29, 11][15, 28, 12][15, 29, 12]
    MMCM:CLKOUT5_LT[15, 28, 13][15, 29, 13][15, 28, 14][15, 29, 14][15, 28, 15][15, 29, 15]
    MMCM:CLKOUT6_DT[13, 28, 37][13, 29, 37][13, 28, 38][13, 29, 38][13, 28, 39][13, 29, 39]
    MMCM:CLKOUT6_HT[13, 28, 42][13, 29, 42][13, 28, 43][13, 29, 43][13, 28, 44][13, 29, 44]
    MMCM:CLKOUT6_LT[13, 28, 45][13, 29, 45][13, 28, 46][13, 29, 46][13, 28, 47][13, 29, 47]
    MMCM:DIVCLK_HT[13, 28, 10][13, 29, 10][13, 28, 11][13, 29, 11][13, 28, 12][13, 29, 12]
    MMCM:DIVCLK_LT[13, 28, 13][13, 29, 13][13, 28, 14][13, 29, 14][13, 28, 15][13, 29, 15]
    MMCM:FINE_PS_FRAC[1, 29, 26][1, 28, 27][1, 29, 27][1, 28, 28][1, 29, 28][1, 28, 29]
    MMCM:HVLF_CNT_TEST[6, 28, 26][6, 29, 27][6, 28, 28][6, 29, 29][6, 28, 30][6, 29, 31]
    MMCM:IN_DLY_MX_CVDD[15, 28, 58][15, 29, 58][15, 28, 59][15, 29, 59][15, 28, 60][15, 29, 60]
    MMCM:IN_DLY_MX_DVDD[15, 28, 19][15, 29, 19][15, 28, 20][15, 29, 20][15, 28, 21][15, 29, 21]
    MMCM:IN_DLY_SET[15, 28, 16][15, 29, 16][15, 28, 17][15, 29, 17][15, 28, 18][15, 29, 18]
    PHASER_IN0:FINE_DELAY[19, 29, 53][19, 28, 53][19, 29, 52][19, 28, 52][19, 29, 51][19, 28, 51]
    PHASER_IN1:FINE_DELAY[23, 29, 21][23, 28, 21][23, 29, 20][23, 28, 20][23, 29, 19][23, 28, 19]
    PHASER_IN2:FINE_DELAY[29, 29, 53][29, 28, 53][29, 29, 52][29, 28, 52][29, 29, 51][29, 28, 51]
    PHASER_IN3:FINE_DELAY[33, 29, 21][33, 28, 21][33, 29, 20][33, 28, 20][33, 29, 19][33, 28, 19]
    PHASER_OUT0:COARSE_DELAY[18, 28, 5][18, 29, 4][18, 28, 4][18, 29, 3][18, 28, 3][18, 29, 2]
    PHASER_OUT0:FINE_DELAY[18, 28, 8][18, 29, 7][18, 28, 7][18, 29, 6][18, 28, 6][18, 29, 5]
    PHASER_OUT0:OCLK_DELAY[17, 28, 28][17, 29, 27][17, 28, 27][17, 29, 26][17, 28, 26][17, 29, 25]
    PHASER_OUT1:COARSE_DELAY[21, 28, 37][21, 29, 36][21, 28, 36][21, 29, 35][21, 28, 35][21, 29, 34]
    PHASER_OUT1:FINE_DELAY[21, 28, 40][21, 29, 39][21, 28, 39][21, 29, 38][21, 28, 38][21, 29, 37]
    PHASER_OUT1:OCLK_DELAY[20, 28, 60][20, 29, 59][20, 28, 59][20, 29, 58][20, 28, 58][20, 29, 57]
    PHASER_OUT2:COARSE_DELAY[28, 28, 5][28, 29, 4][28, 28, 4][28, 29, 3][28, 28, 3][28, 29, 2]
    PHASER_OUT2:FINE_DELAY[28, 28, 8][28, 29, 7][28, 28, 7][28, 29, 6][28, 28, 6][28, 29, 5]
    PHASER_OUT2:OCLK_DELAY[27, 28, 28][27, 29, 27][27, 28, 27][27, 29, 26][27, 28, 26][27, 29, 25]
    PHASER_OUT3:COARSE_DELAY[31, 28, 37][31, 29, 36][31, 28, 36][31, 29, 35][31, 28, 35][31, 29, 34]
    PHASER_OUT3:FINE_DELAY[31, 28, 40][31, 29, 39][31, 28, 39][31, 29, 38][31, 28, 38][31, 29, 37]
    PHASER_OUT3:OCLK_DELAY[30, 28, 60][30, 29, 59][30, 28, 59][30, 29, 58][30, 28, 58][30, 29, 57]
    PHY_CONTROL:CMD_OFFSET[34, 29, 58][34, 28, 58][34, 29, 57][34, 28, 57][34, 29, 56][34, 28, 56]
    PHY_CONTROL:EVENTS_DELAY[34, 29, 53][34, 28, 53][34, 29, 52][34, 28, 52][34, 29, 51][34, 28, 51]
    PHY_CONTROL:FOUR_WINDOW_CLOCKS[34, 29, 50][34, 28, 50][34, 29, 49][34, 28, 49][34, 29, 48][34, 28, 48]
    PHY_CONTROL:RD_CMD_OFFSET_0[34, 29, 5][34, 28, 5][34, 29, 4][34, 28, 4][34, 29, 3][34, 28, 3]
    PHY_CONTROL:RD_CMD_OFFSET_1[34, 29, 37][34, 28, 37][34, 29, 36][34, 28, 36][34, 29, 35][34, 28, 35]
    PHY_CONTROL:RD_CMD_OFFSET_2[35, 29, 5][35, 28, 5][35, 29, 4][35, 28, 4][35, 29, 3][35, 28, 3]
    PHY_CONTROL:RD_CMD_OFFSET_3[35, 29, 37][35, 28, 37][35, 29, 36][35, 28, 36][35, 29, 35][35, 28, 35]
    PHY_CONTROL:RD_DURATION_0[34, 29, 2][34, 28, 2][34, 29, 1][34, 28, 1][34, 29, 0][34, 28, 0]
    PHY_CONTROL:RD_DURATION_1[34, 29, 34][34, 28, 34][34, 29, 33][34, 28, 33][34, 29, 32][34, 28, 32]
    PHY_CONTROL:RD_DURATION_2[35, 29, 2][35, 28, 2][35, 29, 1][35, 28, 1][35, 29, 0][35, 28, 0]
    PHY_CONTROL:RD_DURATION_3[35, 29, 34][35, 28, 34][35, 29, 33][35, 28, 33][35, 29, 32][35, 28, 32]
    PHY_CONTROL:WR_CMD_OFFSET_0[34, 29, 11][34, 28, 11][34, 29, 10][34, 28, 10][34, 29, 9][34, 28, 9]
    PHY_CONTROL:WR_CMD_OFFSET_1[34, 29, 43][34, 28, 43][34, 29, 42][34, 28, 42][34, 29, 41][34, 28, 41]
    PHY_CONTROL:WR_CMD_OFFSET_2[35, 29, 11][35, 28, 11][35, 29, 10][35, 28, 10][35, 29, 9][35, 28, 9]
    PHY_CONTROL:WR_CMD_OFFSET_3[35, 29, 43][35, 28, 43][35, 29, 42][35, 28, 42][35, 29, 41][35, 28, 41]
    PHY_CONTROL:WR_DURATION_0[34, 29, 8][34, 28, 8][34, 29, 7][34, 28, 7][34, 29, 6][34, 28, 6]
    PHY_CONTROL:WR_DURATION_1[34, 29, 40][34, 28, 40][34, 29, 39][34, 28, 39][34, 29, 38][34, 28, 38]
    PHY_CONTROL:WR_DURATION_2[35, 29, 8][35, 28, 8][35, 29, 7][35, 28, 7][35, 29, 6][35, 28, 6]
    PHY_CONTROL:WR_DURATION_3[35, 29, 40][35, 28, 40][35, 29, 39][35, 28, 39][35, 29, 38][35, 28, 38]
    PLL:CLKFBIN_HT[39, 29, 61][39, 28, 61][39, 29, 60][39, 28, 60][39, 29, 59][39, 28, 59]
    PLL:CLKFBIN_LT[39, 29, 58][39, 28, 58][39, 29, 57][39, 28, 57][39, 29, 56][39, 28, 56]
    PLL:CLKFBOUT_DT[39, 29, 42][39, 28, 42][39, 29, 41][39, 28, 41][39, 29, 40][39, 28, 40]
    PLL:CLKFBOUT_HT[39, 29, 37][39, 28, 37][39, 29, 36][39, 28, 36][39, 29, 35][39, 28, 35]
    PLL:CLKFBOUT_LT[39, 29, 34][39, 28, 34][39, 29, 33][39, 28, 33][39, 29, 32][39, 28, 32]
    PLL:CLKOUT0_DT[38, 29, 10][38, 28, 10][38, 29, 9][38, 28, 9][38, 29, 8][38, 28, 8]
    PLL:CLKOUT0_HT[38, 29, 5][38, 28, 5][38, 29, 4][38, 28, 4][38, 29, 3][38, 28, 3]
    PLL:CLKOUT0_LT[38, 29, 2][38, 28, 2][38, 29, 1][38, 28, 1][38, 29, 0][38, 28, 0]
    PLL:CLKOUT1_DT[38, 29, 26][38, 28, 26][38, 29, 25][38, 28, 25][38, 29, 24][38, 28, 24]
    PLL:CLKOUT1_HT[38, 29, 21][38, 28, 21][38, 29, 20][38, 28, 20][38, 29, 19][38, 28, 19]
    PLL:CLKOUT1_LT[38, 29, 18][38, 28, 18][38, 29, 17][38, 28, 17][38, 29, 16][38, 28, 16]
    PLL:CLKOUT2_DT[38, 29, 42][38, 28, 42][38, 29, 41][38, 28, 41][38, 29, 40][38, 28, 40]
    PLL:CLKOUT2_HT[38, 29, 37][38, 28, 37][38, 29, 36][38, 28, 36][38, 29, 35][38, 28, 35]
    PLL:CLKOUT2_LT[38, 29, 34][38, 28, 34][38, 29, 33][38, 28, 33][38, 29, 32][38, 28, 32]
    PLL:CLKOUT3_DT[38, 29, 58][38, 28, 58][38, 29, 57][38, 28, 57][38, 29, 56][38, 28, 56]
    PLL:CLKOUT3_HT[38, 29, 53][38, 28, 53][38, 29, 52][38, 28, 52][38, 29, 51][38, 28, 51]
    PLL:CLKOUT3_LT[38, 29, 50][38, 28, 50][38, 29, 49][38, 28, 49][38, 29, 48][38, 28, 48]
    PLL:CLKOUT4_DT[39, 29, 10][39, 28, 10][39, 29, 9][39, 28, 9][39, 29, 8][39, 28, 8]
    PLL:CLKOUT4_HT[39, 29, 5][39, 28, 5][39, 29, 4][39, 28, 4][39, 29, 3][39, 28, 3]
    PLL:CLKOUT4_LT[39, 29, 2][39, 28, 2][39, 29, 1][39, 28, 1][39, 29, 0][39, 28, 0]
    PLL:CLKOUT5_DT[37, 29, 58][37, 28, 58][37, 29, 57][37, 28, 57][37, 29, 56][37, 28, 56]
    PLL:CLKOUT5_HT[37, 29, 53][37, 28, 53][37, 29, 52][37, 28, 52][37, 29, 51][37, 28, 51]
    PLL:CLKOUT5_LT[37, 29, 50][37, 28, 50][37, 29, 49][37, 28, 49][37, 29, 48][37, 28, 48]
    PLL:DIVCLK_HT[39, 29, 53][39, 28, 53][39, 29, 52][39, 28, 52][39, 29, 51][39, 28, 51]
    PLL:DIVCLK_LT[39, 29, 50][39, 28, 50][39, 29, 49][39, 28, 49][39, 29, 48][39, 28, 48]
    PLL:HVLF_CNT_TEST[46, 29, 37][46, 28, 36][46, 29, 35][46, 28, 34][46, 29, 33][46, 28, 32]
    PLL:IN_DLY_MX_CVDD[37, 29, 5][37, 28, 5][37, 29, 4][37, 28, 4][37, 29, 3][37, 28, 3]
    PLL:IN_DLY_MX_DVDD[37, 29, 44][37, 28, 44][37, 29, 43][37, 28, 43][37, 29, 42][37, 28, 42]
    PLL:IN_DLY_SET[37, 29, 47][37, 28, 47][37, 29, 46][37, 28, 46][37, 29, 45][37, 28, 45]
    Non-inverted[5][4][3][2][1][0]
    - - +
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    CMT bittile 5
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFMRCE0:ENABLE[50, 28, 27]
    BUFMRCE0:INIT_OUT[50, 28, 29]
    BUFMRCE1:ENABLE[50, 29, 27]
    BUFMRCE1:INIT_OUT[50, 29, 29]
    CMT_BOT:BUF.SYNC_BB.D[16, 28, 38]
    CMT_BOT:BUF.SYNC_BB.U[16, 28, 39]
    CMT_BOT:ENABLE.SYNC_BB[16, 29, 38]
    CMT_BOT:ENABLE.SYNC_BB_S[16, 28, 32]
    CMT_TOP:BUF.SYNC_BB.D[36, 28, 38]
    CMT_TOP:BUF.SYNC_BB.U[36, 28, 39]
    CMT_TOP:DRIVE.SYNC_BB[36, 28, 40]
    CMT_TOP:ENABLE.SYNC_BB_N[36, 29, 38]
    HCLK_CMT:ENABLE.CCIO0[24, 27, 63]
    HCLK_CMT:ENABLE.CCIO1[24, 26, 63]
    HCLK_CMT:ENABLE.CCIO2[24, 27, 62]
    HCLK_CMT:ENABLE.CCIO3[24, 26, 62]
    HCLK_CMT:ENABLE.CKINT0[50, 26, 14]
    HCLK_CMT:ENABLE.CKINT1[50, 27, 14]
    HCLK_CMT:ENABLE.CKINT2[50, 26, 15]
    HCLK_CMT:ENABLE.CKINT3[50, 27, 15]
    HCLK_CMT:ENABLE.FREQ_BB0[24, 29, 61]
    HCLK_CMT:ENABLE.FREQ_BB1[24, 28, 61]
    HCLK_CMT:ENABLE.FREQ_BB2[24, 29, 60]
    HCLK_CMT:ENABLE.FREQ_BB3[24, 28, 60]
    HCLK_CMT:ENABLE.HCLK0[50, 27, 25]
    HCLK_CMT:ENABLE.HCLK1[50, 26, 25]
    HCLK_CMT:ENABLE.HCLK10[50, 28, 26]
    HCLK_CMT:ENABLE.HCLK11[50, 29, 26]
    HCLK_CMT:ENABLE.HCLK2[50, 27, 24]
    HCLK_CMT:ENABLE.HCLK3[50, 26, 24]
    HCLK_CMT:ENABLE.HCLK4[50, 27, 23]
    HCLK_CMT:ENABLE.HCLK5[50, 26, 23]
    HCLK_CMT:ENABLE.HCLK6[50, 27, 22]
    HCLK_CMT:ENABLE.HCLK7[50, 26, 22]
    HCLK_CMT:ENABLE.HCLK8[50, 27, 21]
    HCLK_CMT:ENABLE.HCLK9[50, 26, 21]
    HCLK_CMT:ENABLE.HIN10[50, 28, 24]
    HCLK_CMT:ENABLE.HIN11[50, 29, 24]
    HCLK_CMT:ENABLE.HIN12[50, 28, 25]
    HCLK_CMT:ENABLE.HIN13[50, 29, 25]
    HCLK_CMT:ENABLE.HIN4[50, 28, 21]
    HCLK_CMT:ENABLE.HIN5[50, 29, 21]
    HCLK_CMT:ENABLE.HIN6[50, 28, 22]
    HCLK_CMT:ENABLE.HIN7[50, 29, 22]
    HCLK_CMT:ENABLE.HIN8[50, 28, 23]
    HCLK_CMT:ENABLE.HIN9[50, 29, 23]
    HCLK_CMT:ENABLE.RCLK0[50, 28, 14]
    HCLK_CMT:ENABLE.RCLK1[50, 29, 14]
    HCLK_CMT:ENABLE.RCLK2[50, 28, 15]
    HCLK_CMT:ENABLE.RCLK3[50, 29, 15]
    MMCM:BUF.CLKOUT0_FREQ_BB[15, 29, 51]
    MMCM:BUF.CLKOUT1_FREQ_BB[15, 28, 51]
    MMCM:BUF.CLKOUT2_FREQ_BB[15, 29, 50]
    MMCM:BUF.CLKOUT3_FREQ_BB[15, 28, 50]
    MMCM:CLKBURST_ENABLE[15, 29, 25]
    MMCM:CLKBURST_REPEAT[15, 28, 25]
    MMCM:CLKFBIN_EDGE[13, 28, 1]
    MMCM:CLKFBIN_NOCOUNT[13, 29, 1]
    MMCM:CLKFBOUT_EDGE[13, 28, 20]
    MMCM:CLKFBOUT_EN[13, 29, 25]
    MMCM:CLKFBOUT_FRAC_EN[13, 28, 18]
    MMCM:CLKFBOUT_FRAC_WF_FALL[13, 29, 34]
    MMCM:CLKFBOUT_FRAC_WF_RISE[13, 29, 18]
    MMCM:CLKFBOUT_NOCOUNT[13, 29, 20]
    MMCM:CLKFBOUT_USE_FINE_PS[13, 29, 19]
    MMCM:CLKOUT0_EDGE[14, 28, 52]
    MMCM:CLKOUT0_EN[14, 29, 57]
    MMCM:CLKOUT0_FRAC_EN[14, 28, 50]
    MMCM:CLKOUT0_FRAC_WF_FALL[15, 29, 2]
    MMCM:CLKOUT0_FRAC_WF_RISE[14, 29, 50]
    MMCM:CLKOUT0_NOCOUNT[14, 29, 52]
    MMCM:CLKOUT0_USE_FINE_PS[14, 29, 51]
    MMCM:CLKOUT1_EDGE[14, 28, 36]
    MMCM:CLKOUT1_EN[14, 29, 41]
    MMCM:CLKOUT1_NOCOUNT[14, 29, 36]
    MMCM:CLKOUT1_USE_FINE_PS[14, 29, 35]
    MMCM:CLKOUT2_EDGE[14, 28, 20]
    MMCM:CLKOUT2_EN[14, 29, 25]
    MMCM:CLKOUT2_NOCOUNT[14, 29, 20]
    MMCM:CLKOUT2_USE_FINE_PS[14, 29, 19]
    MMCM:CLKOUT3_EDGE[14, 28, 4]
    MMCM:CLKOUT3_EN[14, 29, 9]
    MMCM:CLKOUT3_NOCOUNT[14, 29, 4]
    MMCM:CLKOUT3_USE_FINE_PS[14, 29, 3]
    MMCM:CLKOUT4_CASCADE[13, 28, 51]
    MMCM:CLKOUT4_EDGE[13, 28, 52]
    MMCM:CLKOUT4_EN[13, 29, 57]
    MMCM:CLKOUT4_NOCOUNT[13, 29, 52]
    MMCM:CLKOUT4_USE_FINE_PS[13, 29, 51]
    MMCM:CLKOUT5_EDGE[15, 28, 4]
    MMCM:CLKOUT5_EN[15, 29, 9]
    MMCM:CLKOUT5_NOCOUNT[15, 29, 4]
    MMCM:CLKOUT5_USE_FINE_PS[15, 29, 3]
    MMCM:CLKOUT6_EDGE[13, 28, 36]
    MMCM:CLKOUT6_EN[13, 29, 41]
    MMCM:CLKOUT6_NOCOUNT[13, 29, 36]
    MMCM:CLKOUT6_USE_FINE_PS[13, 29, 35]
    MMCM:CP_BIAS_TRIP_SET[6, 28, 12]
    MMCM:DIRECT_PATH_CNTRL[15, 28, 22]
    MMCM:DIVCLK_EDGE[13, 28, 9]
    MMCM:DIVCLK_NOCOUNT[13, 29, 9]
    MMCM:ENABLE.PERF0[24, 29, 38]
    MMCM:ENABLE.PERF1[24, 28, 38]
    MMCM:ENABLE.PERF2[24, 29, 37]
    MMCM:ENABLE.PERF3[24, 28, 37]
    MMCM:EN_VCO_DIV1[11, 28, 47]
    MMCM:EN_VCO_DIV6[11, 29, 47]
    MMCM:GTS_WAIT[1, 28, 30]
    MMCM:HVLF_CNT_TEST_EN[6, 29, 25]
    MMCM:INTERP_TEST[11, 29, 46]
    MMCM:INV.CLKINSEL[1, 29, 45]
    MMCM:INV.PSEN[1, 28, 46]
    MMCM:INV.PSINCDEC[1, 29, 46]
    MMCM:INV.PWRDWN[1, 28, 47]
    MMCM:INV.RST[1, 29, 47]
    MMCM:IN_DLY_EN[15, 29, 22]
    MMCM:LF_LOW_SEL[7, 29, 39]
    MMCM:MMCM_EN[1, 29, 31]
    MMCM:SEL_HV_NMOS[6, 29, 50]
    MMCM:SEL_LV_NMOS[12, 29, 8]
    MMCM:SEL_SLIPD[12, 28, 18]
    MMCM:SS_EN[1, 28, 31]
    MMCM:STARTUP_WAIT[1, 29, 30]
    MMCM:SUP_SEL_AREG[6, 28, 48]
    MMCM:SUP_SEL_DREG[12, 28, 8]
    MMCM:VLF_HIGH_DIS_B[7, 28, 44]
    MMCM:VLF_HIGH_PWDN_B[7, 29, 15]
    PHASER_IN0:BURST_MODE[19, 29, 26]
    PHASER_IN0:DQS_AUTO_RECAL[18, 28, 49]
    PHASER_IN0:DQS_BIAS_MODE[18, 29, 49]
    PHASER_IN0:ENABLE.RCLK[24, 29, 36]
    PHASER_IN0:EN_ISERDES_RST[18, 29, 55]
    PHASER_IN0:EN_TEST_RING[19, 29, 23]
    PHASER_IN0:HALF_CYCLE_ADJ[18, 28, 60]
    PHASER_IN0:ICLK_TO_RCLK_BYPASS[18, 28, 56]
    PHASER_IN0:INV.RST[18, 28, 59]
    PHASER_IN0:PHASER_IN_EN[18, 28, 55]
    PHASER_IN0:REG_OPT_1[18, 28, 50]
    PHASER_IN0:REG_OPT_2[18, 29, 61]
    PHASER_IN0:REG_OPT_4[18, 29, 50]
    PHASER_IN0:RST_SEL[18, 28, 61]
    PHASER_IN0:SEL_OUT[18, 28, 52]
    PHASER_IN0:SYNC_IN_DIV_RST[19, 28, 54]
    PHASER_IN0:TEST_BP[18, 29, 48]
    PHASER_IN0:UPDATE_NONACTIVE[18, 28, 48]
    PHASER_IN0:WR_CYCLES[18, 29, 54]
    PHASER_IN1:BURST_MODE[22, 29, 58]
    PHASER_IN1:DQS_AUTO_RECAL[22, 28, 17]
    PHASER_IN1:DQS_BIAS_MODE[22, 29, 17]
    PHASER_IN1:ENABLE.RCLK[24, 28, 36]
    PHASER_IN1:EN_ISERDES_RST[22, 29, 23]
    PHASER_IN1:EN_TEST_RING[22, 29, 55]
    PHASER_IN1:HALF_CYCLE_ADJ[22, 28, 28]
    PHASER_IN1:ICLK_TO_RCLK_BYPASS[22, 28, 24]
    PHASER_IN1:INV.RST[22, 28, 27]
    PHASER_IN1:PHASER_IN_EN[22, 28, 23]
    PHASER_IN1:REG_OPT_1[22, 28, 18]
    PHASER_IN1:REG_OPT_2[22, 29, 29]
    PHASER_IN1:REG_OPT_4[22, 29, 18]
    PHASER_IN1:RST_SEL[22, 28, 29]
    PHASER_IN1:SEL_OUT[22, 28, 20]
    PHASER_IN1:SYNC_IN_DIV_RST[23, 28, 22]
    PHASER_IN1:TEST_BP[22, 29, 16]
    PHASER_IN1:UPDATE_NONACTIVE[22, 28, 16]
    PHASER_IN1:WR_CYCLES[22, 29, 22]
    PHASER_IN2:BURST_MODE[29, 29, 26]
    PHASER_IN2:DQS_AUTO_RECAL[28, 28, 49]
    PHASER_IN2:DQS_BIAS_MODE[28, 29, 49]
    PHASER_IN2:ENABLE.RCLK[24, 29, 35]
    PHASER_IN2:EN_ISERDES_RST[28, 29, 55]
    PHASER_IN2:EN_TEST_RING[29, 29, 23]
    PHASER_IN2:HALF_CYCLE_ADJ[28, 28, 60]
    PHASER_IN2:ICLK_TO_RCLK_BYPASS[28, 28, 56]
    PHASER_IN2:INV.RST[28, 28, 59]
    PHASER_IN2:PHASER_IN_EN[28, 28, 55]
    PHASER_IN2:REG_OPT_1[28, 28, 50]
    PHASER_IN2:REG_OPT_2[28, 29, 61]
    PHASER_IN2:REG_OPT_4[28, 29, 50]
    PHASER_IN2:RST_SEL[28, 28, 61]
    PHASER_IN2:SEL_OUT[28, 28, 52]
    PHASER_IN2:SYNC_IN_DIV_RST[29, 28, 54]
    PHASER_IN2:TEST_BP[28, 29, 48]
    PHASER_IN2:UPDATE_NONACTIVE[28, 28, 48]
    PHASER_IN2:WR_CYCLES[28, 29, 54]
    PHASER_IN3:BURST_MODE[32, 29, 58]
    PHASER_IN3:DQS_AUTO_RECAL[32, 28, 17]
    PHASER_IN3:DQS_BIAS_MODE[32, 29, 17]
    PHASER_IN3:ENABLE.RCLK[24, 28, 35]
    PHASER_IN3:EN_ISERDES_RST[32, 29, 23]
    PHASER_IN3:EN_TEST_RING[32, 29, 55]
    PHASER_IN3:HALF_CYCLE_ADJ[32, 28, 28]
    PHASER_IN3:ICLK_TO_RCLK_BYPASS[32, 28, 24]
    PHASER_IN3:INV.RST[32, 28, 27]
    PHASER_IN3:PHASER_IN_EN[32, 28, 23]
    PHASER_IN3:REG_OPT_1[32, 28, 18]
    PHASER_IN3:REG_OPT_2[32, 29, 29]
    PHASER_IN3:REG_OPT_4[32, 29, 18]
    PHASER_IN3:RST_SEL[32, 28, 29]
    PHASER_IN3:SEL_OUT[32, 28, 20]
    PHASER_IN3:SYNC_IN_DIV_RST[33, 28, 22]
    PHASER_IN3:TEST_BP[32, 29, 16]
    PHASER_IN3:UPDATE_NONACTIVE[32, 28, 16]
    PHASER_IN3:WR_CYCLES[32, 29, 22]
    PHASER_OUT0:COARSE_BYPASS[17, 29, 23]
    PHASER_OUT0:DATA_CTL_N[17, 28, 29]
    PHASER_OUT0:DATA_RD_CYCLES[17, 29, 21]
    PHASER_OUT0:EN_OSERDES_RST[17, 28, 23]
    PHASER_OUT0:EN_TEST_RING[17, 29, 28]
    PHASER_OUT0:INV.RST[18, 28, 0]
    PHASER_OUT0:OCLKDELAY_INV[17, 28, 22]
    PHASER_OUT0:PHASER_OUT_EN[17, 29, 22]
    PHASER_OUT0:SYNC_IN_DIV_RST[18, 29, 8]
    PHASER_OUT1:COARSE_BYPASS[20, 29, 55]
    PHASER_OUT1:DATA_CTL_N[20, 28, 61]
    PHASER_OUT1:DATA_RD_CYCLES[20, 29, 53]
    PHASER_OUT1:EN_OSERDES_RST[20, 28, 55]
    PHASER_OUT1:EN_TEST_RING[20, 29, 60]
    PHASER_OUT1:INV.RST[21, 28, 32]
    PHASER_OUT1:OCLKDELAY_INV[20, 28, 54]
    PHASER_OUT1:PHASER_OUT_EN[20, 29, 54]
    PHASER_OUT1:SYNC_IN_DIV_RST[21, 29, 40]
    PHASER_OUT2:COARSE_BYPASS[27, 29, 23]
    PHASER_OUT2:DATA_CTL_N[27, 28, 29]
    PHASER_OUT2:DATA_RD_CYCLES[27, 29, 21]
    PHASER_OUT2:EN_OSERDES_RST[27, 28, 23]
    PHASER_OUT2:EN_TEST_RING[27, 29, 28]
    PHASER_OUT2:INV.RST[28, 28, 0]
    PHASER_OUT2:OCLKDELAY_INV[27, 28, 22]
    PHASER_OUT2:PHASER_OUT_EN[27, 29, 22]
    PHASER_OUT2:SYNC_IN_DIV_RST[28, 29, 8]
    PHASER_OUT3:COARSE_BYPASS[30, 29, 55]
    PHASER_OUT3:DATA_CTL_N[30, 28, 61]
    PHASER_OUT3:DATA_RD_CYCLES[30, 29, 53]
    PHASER_OUT3:EN_OSERDES_RST[30, 28, 55]
    PHASER_OUT3:EN_TEST_RING[30, 29, 60]
    PHASER_OUT3:INV.RST[31, 28, 32]
    PHASER_OUT3:OCLKDELAY_INV[30, 28, 54]
    PHASER_OUT3:PHASER_OUT_EN[30, 29, 54]
    PHASER_OUT3:SYNC_IN_DIV_RST[31, 29, 40]
    PHASER_REF:CP_BIAS_TRIP_SET[26, 29, 1]
    PHASER_REF:INV.PWRDWN[26, 28, 24]
    PHASER_REF:INV.RST[26, 28, 16]
    PHASER_REF:PHASER_REF_EN[26, 29, 24]
    PHASER_REF:SEL_SLIPD[26, 28, 3]
    PHASER_REF:SUP_SEL_AREG[26, 29, 7]
    PHY_CONTROL:BURST_MODE[35, 28, 46]
    PHY_CONTROL:DATA_CTL_A_N[35, 28, 44]
    PHY_CONTROL:DATA_CTL_B_N[35, 29, 44]
    PHY_CONTROL:DATA_CTL_C_N[35, 28, 45]
    PHY_CONTROL:DATA_CTL_D_N[35, 29, 45]
    PHY_CONTROL:DISABLE_SEQ_MATCH[34, 28, 15]
    PHY_CONTROL:MULTI_REGION[34, 28, 14]
    PHY_CONTROL:PHY_COUNT_ENABLE[35, 29, 15]
    PHY_CONTROL:SPARE[34, 29, 13]
    PHY_CONTROL:SYNC_MODE[34, 29, 14]
    PLL:BUF.CLKOUT0_FREQ_BB[37, 28, 12]
    PLL:BUF.CLKOUT1_FREQ_BB[37, 29, 12]
    PLL:BUF.CLKOUT2_FREQ_BB[37, 28, 13]
    PLL:BUF.CLKOUT3_FREQ_BB[37, 29, 13]
    PLL:CLKFBIN_EDGE[39, 29, 62]
    PLL:CLKFBIN_NOCOUNT[39, 28, 62]
    PLL:CLKFBOUT_EDGE[39, 29, 43]
    PLL:CLKFBOUT_EN[39, 28, 38]
    PLL:CLKFBOUT_NOCOUNT[39, 28, 43]
    PLL:CLKOUT0_EDGE[38, 29, 11]
    PLL:CLKOUT0_EN[38, 28, 6]
    PLL:CLKOUT0_NOCOUNT[38, 28, 11]
    PLL:CLKOUT1_EDGE[38, 29, 27]
    PLL:CLKOUT1_EN[38, 28, 22]
    PLL:CLKOUT1_NOCOUNT[38, 28, 27]
    PLL:CLKOUT2_EDGE[38, 29, 43]
    PLL:CLKOUT2_EN[38, 28, 38]
    PLL:CLKOUT2_NOCOUNT[38, 28, 43]
    PLL:CLKOUT3_EDGE[38, 29, 59]
    PLL:CLKOUT3_EN[38, 28, 54]
    PLL:CLKOUT3_NOCOUNT[38, 28, 59]
    PLL:CLKOUT4_EDGE[39, 29, 11]
    PLL:CLKOUT4_EN[39, 28, 6]
    PLL:CLKOUT4_NOCOUNT[39, 28, 11]
    PLL:CLKOUT5_EDGE[37, 29, 59]
    PLL:CLKOUT5_EN[37, 28, 54]
    PLL:CLKOUT5_NOCOUNT[37, 28, 59]
    PLL:CP_BIAS_TRIP_SET[46, 29, 51]
    PLL:DIRECT_PATH_CNTRL[37, 29, 41]
    PLL:DIVCLK_EDGE[39, 29, 54]
    PLL:DIVCLK_NOCOUNT[39, 28, 54]
    PLL:EN_VCO_DIV1[41, 29, 16]
    PLL:EN_VCO_DIV6[41, 28, 16]
    PLL:GTS_WAIT[48, 29, 33]
    PLL:HVLF_CNT_TEST_EN[46, 28, 38]
    PLL:INV.CLKINSEL[48, 28, 18]
    PLL:INV.PWRDWN[48, 29, 16]
    PLL:INV.RST[48, 28, 16]
    PLL:IN_DLY_EN[37, 28, 41]
    PLL:LF_LOW_SEL[45, 28, 24]
    PLL:PLL_EN[48, 28, 32]
    PLL:SEL_HV_NMOS[46, 28, 13]
    PLL:SEL_LV_NMOS[40, 28, 55]
    PLL:STARTUP_WAIT[48, 28, 33]
    PLL:SUP_SEL_AREG[46, 29, 15]
    PLL:SUP_SEL_DREG[40, 29, 55]
    PLL:VLF_HIGH_DIS_B[45, 29, 19]
    PLL:VLF_HIGH_PWDN_B[45, 28, 48]
    Non-inverted[0]
    - - +
    +
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    CMT bittile 6
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT_BOT:BUF.FREQ_BB0.D[16, 29, 45][16, 28, 54]
    CMT_BOT:BUF.FREQ_BB0.U[16, 29, 53][16, 28, 46]
    CMT_BOT:BUF.FREQ_BB1.D[16, 29, 46][16, 28, 55]
    CMT_BOT:BUF.FREQ_BB1.U[16, 29, 54][16, 28, 47]
    CMT_BOT:BUF.FREQ_BB2.D[16, 29, 47][16, 28, 56]
    CMT_BOT:BUF.FREQ_BB2.U[16, 29, 55][16, 28, 48]
    CMT_BOT:BUF.FREQ_BB3.D[16, 29, 48][16, 28, 57]
    CMT_BOT:BUF.FREQ_BB3.U[16, 29, 56][16, 28, 49]
    CMT_BOT:ENABLE.FREQ_BB0_S[16, 29, 49][16, 29, 41]
    CMT_BOT:ENABLE.FREQ_BB1_S[16, 29, 50][16, 29, 42]
    CMT_BOT:ENABLE.FREQ_BB2_S[16, 29, 51][16, 29, 43]
    CMT_BOT:ENABLE.FREQ_BB3_S[16, 29, 52][16, 29, 44]
    CMT_TOP:BUF.FREQ_BB0.D[36, 29, 45][36, 28, 54]
    CMT_TOP:BUF.FREQ_BB0.U[36, 29, 53][36, 28, 46]
    CMT_TOP:BUF.FREQ_BB1.D[36, 29, 46][36, 28, 55]
    CMT_TOP:BUF.FREQ_BB1.U[36, 29, 54][36, 28, 47]
    CMT_TOP:BUF.FREQ_BB2.D[36, 29, 47][36, 28, 56]
    CMT_TOP:BUF.FREQ_BB2.U[36, 29, 55][36, 28, 48]
    CMT_TOP:BUF.FREQ_BB3.D[36, 29, 48][36, 28, 57]
    CMT_TOP:BUF.FREQ_BB3.U[36, 29, 56][36, 28, 49]
    CMT_TOP:ENABLE.FREQ_BB0_N[36, 28, 50][36, 28, 42]
    CMT_TOP:ENABLE.FREQ_BB1_N[36, 28, 51][36, 28, 43]
    CMT_TOP:ENABLE.FREQ_BB2_N[36, 28, 52][36, 28, 44]
    CMT_TOP:ENABLE.FREQ_BB3_N[36, 28, 53][36, 28, 45]
    CMT_TOP:ENABLE.SYNC_BB[36, 29, 39][36, 28, 32]
    MMCM:CLKFBOUT_MX[13, 28, 19][13, 29, 19]
    MMCM:CLKOUT0_MX[14, 28, 51][14, 29, 51]
    MMCM:CLKOUT1_MX[14, 28, 35][14, 29, 35]
    MMCM:CLKOUT2_MX[14, 28, 19][14, 29, 19]
    MMCM:CLKOUT3_MX[14, 28, 3][14, 29, 3]
    MMCM:CLKOUT4_MX[13, 28, 51][13, 29, 51]
    MMCM:CLKOUT5_MX[15, 28, 3][15, 29, 3]
    MMCM:CLKOUT6_MX[13, 28, 35][13, 29, 35]
    MMCM:CP_RES[6, 29, 13][6, 28, 14]
    MMCM:EN_CURR_SINK[6, 29, 48][6, 28, 49]
    MMCM:FREQ_COMP[12, 29, 39][12, 28, 40]
    MMCM:LFHF[6, 28, 4][6, 29, 5]
    MMCM:LF_NEN[7, 28, 40][7, 29, 41]
    MMCM:LF_PEN[7, 28, 42][7, 29, 43]
    MMCM:MVDD_SEL[6, 29, 49][6, 28, 50]
    MMCM:SYNTH_CLK_DIV[15, 28, 47][15, 29, 47]
    MMCM:TMUX_MUX_SEL[15, 28, 24][15, 29, 24]
    MMCM:VREF_START[7, 29, 17][7, 28, 18]
    PHASER_IN0:RD_ADDR_INIT[18, 29, 51][18, 28, 51]
    PHASER_IN1:RD_ADDR_INIT[22, 29, 19][22, 28, 19]
    PHASER_IN2:RD_ADDR_INIT[28, 29, 51][28, 28, 51]
    PHASER_IN3:RD_ADDR_INIT[32, 29, 19][32, 28, 19]
    PHASER_REF:CP_RES[26, 29, 56][26, 28, 56]
    PHASER_REF:LF_NEN[26, 29, 31][26, 28, 31]
    PHASER_REF:LF_PEN[26, 29, 30][26, 28, 30]
    PHASER_REF:TMUX_MUX_SEL[26, 29, 2][26, 28, 2]
    PLL:CLKFBOUT_MX[39, 29, 44][39, 28, 44]
    PLL:CLKOUT0_MX[38, 29, 12][38, 28, 12]
    PLL:CLKOUT1_MX[38, 29, 28][38, 28, 28]
    PLL:CLKOUT2_MX[38, 29, 44][38, 28, 44]
    PLL:CLKOUT3_MX[38, 29, 60][38, 28, 60]
    PLL:CLKOUT4_MX[39, 29, 12][39, 28, 12]
    PLL:CLKOUT5_MX[37, 29, 60][37, 28, 60]
    PLL:CP_RES[46, 28, 50][46, 29, 49]
    PLL:EN_CURR_SINK[46, 28, 15][46, 29, 14]
    PLL:FREQ_COMP[40, 28, 24][40, 29, 23]
    PLL:LFHF[46, 29, 59][46, 28, 58]
    PLL:LF_NEN[45, 29, 23][45, 28, 22]
    PLL:LF_PEN[45, 29, 21][45, 28, 20]
    PLL:MVDD_SEL[46, 28, 14][46, 29, 13]
    PLL:SYNTH_CLK_DIV[37, 29, 16][37, 28, 16]
    PLL:TMUX_MUX_SEL[37, 29, 39][37, 28, 39]
    PLL:VREF_START[45, 28, 46][45, 29, 45]
    Non-inverted[1][0]
    - - +
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    CMT bittile 7
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT_BOT:ENABLE.FREQ_BB0[16, 29, 32][16, 28, 50][16, 28, 42]
    CMT_BOT:ENABLE.FREQ_BB1[16, 28, 51][16, 28, 43][16, 28, 33]
    CMT_BOT:ENABLE.FREQ_BB2[16, 29, 33][16, 28, 52][16, 28, 44]
    CMT_BOT:ENABLE.FREQ_BB3[16, 28, 53][16, 28, 45][16, 28, 34]
    CMT_TOP:ENABLE.FREQ_BB0[36, 29, 49][36, 29, 41][36, 29, 32]
    CMT_TOP:ENABLE.FREQ_BB1[36, 29, 50][36, 29, 42][36, 28, 33]
    CMT_TOP:ENABLE.FREQ_BB2[36, 29, 51][36, 29, 43][36, 29, 33]
    CMT_TOP:ENABLE.FREQ_BB3[36, 29, 52][36, 29, 44][36, 28, 34]
    MMCM:AVDD_COMP_SET[6, 28, 43][6, 29, 43][6, 28, 44]
    MMCM:AVDD_VBG_PD[6, 29, 44][6, 28, 45][6, 29, 45]
    MMCM:CLKFBOUT_FRAC[13, 29, 16][13, 28, 17][13, 29, 17]
    MMCM:CLKFBOUT_PM_FALL[13, 28, 33][13, 29, 33][13, 28, 34]
    MMCM:CLKFBOUT_PM_RISE[13, 28, 24][13, 29, 24][13, 28, 25]
    MMCM:CLKOUT0_FRAC[14, 29, 48][14, 28, 49][14, 29, 49]
    MMCM:CLKOUT0_PM_FALL[15, 28, 1][15, 29, 1][15, 28, 2]
    MMCM:CLKOUT0_PM_RISE[14, 28, 56][14, 29, 56][14, 28, 57]
    MMCM:CLKOUT1_PM[14, 28, 40][14, 29, 40][14, 28, 41]
    MMCM:CLKOUT2_PM[14, 28, 24][14, 29, 24][14, 28, 25]
    MMCM:CLKOUT3_PM[14, 28, 8][14, 29, 8][14, 28, 9]
    MMCM:CLKOUT4_PM[13, 28, 56][13, 29, 56][13, 28, 57]
    MMCM:CLKOUT5_PM[15, 28, 8][15, 29, 8][15, 28, 9]
    MMCM:CLKOUT6_PM[13, 28, 40][13, 29, 40][13, 28, 41]
    MMCM:DVDD_COMP_SET[12, 28, 3][12, 29, 3][12, 28, 4]
    MMCM:DVDD_VBG_PD[12, 29, 4][12, 28, 5][12, 29, 5]
    MMCM:HROW_DLY_SET[15, 29, 56][15, 28, 57][15, 29, 57]
    MMCM:MAN_LF[7, 29, 45][7, 28, 46][7, 29, 47]
    MMCM:SS_STEPS[15, 29, 30][15, 28, 31][15, 29, 31]
    MMCM:SS_STEPS_INIT[15, 28, 29][15, 29, 29][15, 28, 30]
    PHASER_IN0:DQS_FIND_PATTERN[19, 28, 23][19, 29, 22][19, 28, 22]
    PHASER_IN0:SEL_CLK_OFFSET[18, 29, 60][18, 28, 53][18, 29, 52]
    PHASER_IN1:DQS_FIND_PATTERN[22, 28, 55][22, 29, 54][22, 28, 54]
    PHASER_IN1:SEL_CLK_OFFSET[22, 29, 28][22, 28, 21][22, 29, 20]
    PHASER_IN2:DQS_FIND_PATTERN[29, 28, 23][29, 29, 22][29, 28, 22]
    PHASER_IN2:SEL_CLK_OFFSET[28, 29, 60][28, 28, 53][28, 29, 52]
    PHASER_IN3:DQS_FIND_PATTERN[32, 28, 55][32, 29, 54][32, 28, 54]
    PHASER_IN3:SEL_CLK_OFFSET[32, 29, 28][32, 28, 21][32, 29, 20]
    PHASER_REF:AVDD_COMP_SET[26, 29, 63][26, 28, 63][26, 29, 62]
    PHASER_REF:AVDD_VBG_PD[26, 28, 62][26, 29, 61][26, 28, 61]
    PHASER_REF:MAN_LF[26, 29, 17][26, 28, 17][26, 29, 16]
    PHASER_REF:PHASER_REF_MISC[26, 28, 1][26, 29, 0][26, 28, 0]
    PHASER_REF:SEL_LF_HIGH[26, 28, 7][26, 29, 6][26, 28, 6]
    PHY_CONTROL:CO_DURATION[35, 28, 13][35, 29, 12][35, 28, 12]
    PHY_CONTROL:DI_DURATION[34, 29, 46][34, 28, 46][34, 29, 45]
    PHY_CONTROL:DO_DURATION[34, 28, 13][34, 29, 12][34, 28, 12]
    PLL:AVDD_COMP_SET[46, 29, 20][46, 28, 20][46, 29, 19]
    PLL:AVDD_VBG_PD[46, 28, 19][46, 29, 18][46, 28, 18]
    PLL:CLKFBOUT_PM[39, 29, 39][39, 28, 39][39, 29, 38]
    PLL:CLKOUT0_PM[38, 29, 7][38, 28, 7][38, 29, 6]
    PLL:CLKOUT1_PM[38, 29, 23][38, 28, 23][38, 29, 22]
    PLL:CLKOUT2_PM[38, 29, 39][38, 28, 39][38, 29, 38]
    PLL:CLKOUT3_PM[38, 29, 55][38, 28, 55][38, 29, 54]
    PLL:CLKOUT4_PM[39, 29, 7][39, 28, 7][39, 29, 6]
    PLL:CLKOUT5_PM[37, 29, 55][37, 28, 55][37, 29, 54]
    PLL:DVDD_COMP_SET[40, 29, 60][40, 28, 60][40, 29, 59]
    PLL:DVDD_VBG_PD[40, 28, 59][40, 29, 58][40, 28, 58]
    PLL:HROW_DLY_SET[37, 28, 7][37, 29, 6][37, 28, 6]
    PLL:MAN_LF[45, 28, 18][45, 29, 17][45, 28, 16]
    Non-inverted[2][1][0]
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    CMT bittile 8
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM:ANALOG_MISC[11, 29, 11][11, 28, 12][11, 29, 13][11, 28, 14]
    MMCM:AVDD_VBG_SEL[6, 28, 46][6, 29, 46][6, 28, 47][6, 29, 47]
    MMCM:CLKBURST_CNT[15, 28, 26][15, 29, 26][15, 28, 27][15, 29, 27]
    MMCM:CP[6, 28, 8][6, 29, 9][6, 28, 10][6, 29, 11]
    MMCM:DVDD_VBG_SEL[12, 28, 6][12, 29, 6][12, 28, 7][12, 29, 7]
    MMCM:RES[6, 28, 0][6, 29, 1][6, 28, 2][6, 29, 3]
    MMCM:SKEW_FLOP_INV[15, 28, 38][15, 29, 38][15, 28, 39][15, 29, 39]
    PHASER_IN0:CLKOUT_DIV_ST[19, 28, 56][19, 29, 55][19, 28, 55][19, 29, 54]
    PHASER_IN1:CLKOUT_DIV_ST[23, 28, 24][23, 29, 23][23, 28, 23][23, 29, 22]
    PHASER_IN2:CLKOUT_DIV_ST[29, 28, 56][29, 29, 55][29, 28, 55][29, 29, 54]
    PHASER_IN3:CLKOUT_DIV_ST[33, 28, 24][33, 29, 23][33, 28, 23][33, 29, 22]
    PHASER_OUT0:CLKOUT_DIV_ST[18, 29, 10][18, 28, 10][18, 29, 9][18, 28, 9]
    PHASER_OUT1:CLKOUT_DIV_ST[21, 29, 42][21, 28, 42][21, 29, 41][21, 28, 41]
    PHASER_OUT2:CLKOUT_DIV_ST[28, 29, 10][28, 28, 10][28, 29, 9][28, 28, 9]
    PHASER_OUT3:CLKOUT_DIV_ST[31, 29, 42][31, 28, 42][31, 29, 41][31, 28, 41]
    PHASER_REF:AVDD_VBG_SEL[26, 29, 60][26, 28, 60][26, 29, 59][26, 28, 59]
    PHASER_REF:CP[26, 29, 58][26, 28, 58][26, 29, 57][26, 28, 57]
    PHY_CONTROL:AO_TOGGLE[34, 29, 55][34, 28, 55][34, 29, 54][34, 28, 54]
    PHY_CONTROL:AO_WRLVL_EN[35, 28, 15][35, 29, 14][35, 28, 14][35, 29, 13]
    PLL:ANALOG_MISC[41, 28, 52][41, 29, 51][41, 28, 50][41, 29, 49]
    PLL:AVDD_VBG_SEL[46, 29, 17][46, 28, 17][46, 29, 16][46, 28, 16]
    PLL:CP[46, 29, 55][46, 28, 54][46, 29, 53][46, 28, 52]
    PLL:DVDD_VBG_SEL[40, 29, 57][40, 28, 57][40, 29, 56][40, 28, 56]
    PLL:RES[46, 29, 63][46, 28, 62][46, 29, 61][46, 28, 60]
    PLL:SKEW_FLOP_INV[37, 29, 25][37, 28, 25][37, 29, 24][37, 28, 24]
    Non-inverted[3][2][1][0]
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    +
    +
    +
    CMT bittile 9
    RowColumn
    + + + + + + + + + + +
    MMCM:LOCK_FB_DLY[12, 29, 48][12, 28, 49][12, 29, 49][12, 28, 50][12, 29, 50]
    MMCM:LOCK_REF_DLY[12, 29, 40][12, 28, 41][12, 29, 41][12, 28, 42][12, 29, 42]
    MMCM:SPARE_ANALOG[7, 29, 27][7, 28, 28][7, 29, 29][7, 28, 30][7, 29, 31]
    MMCM:SPARE_DIGITAL[12, 29, 29][12, 28, 30][12, 29, 30][12, 28, 31][12, 29, 31]
    PHASER_REF:LOCK_FB_DLY[26, 29, 23][26, 28, 23][26, 29, 22][26, 28, 22][26, 29, 21]
    PHASER_REF:LOCK_REF_DLY[26, 29, 5][26, 28, 5][26, 29, 4][26, 28, 4][26, 29, 3]
    PLL:LOCK_FB_DLY[40, 28, 15][40, 29, 14][40, 28, 14][40, 29, 13][40, 28, 13]
    PLL:LOCK_REF_DLY[40, 28, 23][40, 29, 22][40, 28, 22][40, 29, 21][40, 28, 21]
    PLL:SPARE_ANALOG[45, 28, 36][45, 29, 35][45, 28, 34][45, 29, 33][45, 28, 32]
    PLL:SPARE_DIGITAL[40, 28, 34][40, 29, 33][40, 28, 33][40, 29, 32][40, 28, 32]
    Non-inverted[4][3][2][1][0]
    - - +
    +
    CMT bittile 10
    RowColumn
    + +
    MMCM:INTERP_EN[10, 28, 56][10, 29, 57][10, 28, 58][10, 29, 59][10, 28, 60][10, 29, 61][10, 28, 62][10, 29, 63]
    Non-inverted[7][6][5][4][3][2][1][0]
    - - +
    +
    +
    +
    CMT bittile 11
    RowColumn
    + + + +
    MMCM:PFD[12, 29, 18][12, 28, 19][12, 29, 19][12, 28, 20][12, 29, 20][12, 28, 21][12, 29, 21]
    PHASER_REF:PFD[26, 28, 21][26, 29, 20][26, 28, 20][26, 29, 19][26, 28, 19][26, 29, 18][26, 28, 18]
    PLL:PFD[40, 28, 45][40, 29, 44][40, 28, 44][40, 29, 43][40, 28, 43][40, 29, 42][40, 28, 42]
    Non-inverted[6][5][4][3][2][1][0]
    - - +
    +
    +
    +
    +
    +
    +
    +
    CMT bittile 12
    RowColumn
    + + + + + + + +
    MMCM:LOCK_CNT[12, 28, 59][12, 29, 59][12, 28, 60][12, 29, 60][12, 28, 61][12, 29, 61][12, 28, 62][12, 29, 62][12, 28, 63][12, 29, 63]
    MMCM:LOCK_SAT_HIGH[12, 28, 43][12, 29, 43][12, 28, 44][12, 29, 44][12, 28, 45][12, 29, 45][12, 28, 46][12, 29, 46][12, 28, 47][12, 29, 47]
    MMCM:UNLOCK_CNT[12, 28, 51][12, 29, 51][12, 28, 52][12, 29, 52][12, 28, 53][12, 29, 53][12, 28, 54][12, 29, 54][12, 28, 55][12, 29, 55]
    PHASER_REF:LOCK_CNT[26, 29, 29][26, 28, 29][26, 29, 28][26, 28, 28][26, 29, 27][26, 28, 27][26, 29, 26][26, 28, 26][26, 29, 25][26, 28, 25]
    PLL:LOCK_CNT[40, 29, 4][40, 28, 4][40, 29, 3][40, 28, 3][40, 29, 2][40, 28, 2][40, 29, 1][40, 28, 1][40, 29, 0][40, 28, 0]
    PLL:LOCK_SAT_HIGH[40, 29, 20][40, 28, 20][40, 29, 19][40, 28, 19][40, 29, 18][40, 28, 18][40, 29, 17][40, 28, 17][40, 29, 16][40, 28, 16]
    PLL:UNLOCK_CNT[40, 29, 12][40, 28, 12][40, 29, 11][40, 28, 11][40, 29, 10][40, 28, 10][40, 29, 9][40, 28, 9][40, 29, 8][40, 28, 8]
    Non-inverted[9][8][7][6][5][4][3][2][1][0]
    - - +
    +
    +
    +
    +
    CMT bittile 13
    RowColumn
    + + + + + + + + + +
    MMCM:MUX.PERF0[15, 29, 63][15, 29, 37][15, 28, 37][15, 29, 36]
    MMCM:MUX.PERF1[15, 28, 63][15, 28, 36][15, 29, 35][15, 28, 35]
    MMCM:MUX.PERF2[15, 29, 62][15, 29, 34][15, 28, 34][15, 29, 33]
    MMCM:MUX.PERF3[15, 28, 62][15, 28, 33][15, 29, 32][15, 28, 32]
    NONE0000
    CLKOUT01000
    CLKFBOUT1001
    CLKOUT21010
    CLKOUT11100
    CLKOUT31110
    - - +
    +
    CMT bittile 14
    RowColumn
    + + + + + + +
    MMCM:MUX.CLKFBIN[15, 28, 53][15, 29, 52][15, 28, 52]
    FREQ_BB0000
    CLKFBIN_HCLK001
    FREQ_BB2010
    FREQ_BB1100
    CLKFBIN_CKINT101
    FREQ_BB3110
    - - +
    +
    CMT bittile 15
    RowColumn
    + + + + + + +
    MMCM:MUX.CLKIN2[15, 28, 56][15, 29, 55][15, 28, 55]
    FREQ_BB0000
    CLKIN2_HCLK001
    FREQ_BB2010
    FREQ_BB1100
    CLKIN2_CKINT101
    FREQ_BB3110
    - - +
    +
    CMT bittile 16
    RowColumn
    + + + + + + +
    MMCM:MUX.CLKIN1[15, 29, 54][15, 28, 54][15, 29, 53]
    FREQ_BB0000
    CLKIN1_HCLK001
    FREQ_BB2010
    FREQ_BB1100
    CLKIN1_CKINT101
    FREQ_BB3110
    - - +
    +
    +
    +
    +
    CMT bittile 17
    RowColumn
    + + + + + + + + +
    CMT_BOT:MUX.FREQ_BB0[16, 28, 60][16, 29, 59][16, 29, 34]
    CMT_BOT:MUX.FREQ_BB1[16, 28, 61][16, 29, 60][16, 28, 35]
    CMT_BOT:MUX.FREQ_BB2[16, 28, 62][16, 29, 61][16, 29, 35]
    CMT_BOT:MUX.FREQ_BB3[16, 28, 63][16, 29, 62][16, 28, 36]
    NONE000
    MMCM_CLKOUT0001
    MMCM_CLKOUT1011
    MMCM_CLKOUT2101
    MMCM_CLKOUT3111
    - - +
    +
    +
    +
    +
    CMT bittile 18
    RowColumn
    + + + + +
    PHASER_OUT0:TEST_OPT[17, 28, 21][17, 29, 20][17, 28, 20][17, 29, 19][17, 28, 19][17, 29, 18][17, 28, 18][17, 29, 17][17, 28, 17][17, 29, 16][17, 28, 16]
    PHASER_OUT1:TEST_OPT[20, 28, 53][20, 29, 52][20, 28, 52][20, 29, 51][20, 28, 51][20, 29, 50][20, 28, 50][20, 29, 49][20, 28, 49][20, 29, 48][20, 28, 48]
    PHASER_OUT2:TEST_OPT[27, 28, 21][27, 29, 20][27, 28, 20][27, 29, 19][27, 28, 19][27, 29, 18][27, 28, 18][27, 29, 17][27, 28, 17][27, 29, 16][27, 28, 16]
    PHASER_OUT3:TEST_OPT[30, 28, 53][30, 29, 52][30, 28, 52][30, 29, 51][30, 28, 51][30, 29, 50][30, 28, 50][30, 29, 49][30, 28, 49][30, 29, 48][30, 28, 48]
    Non-inverted[10][9][8][7][6][5][4][3][2][1][0]
    - - +
    +
    +
    +
    +
    CMT bittile 19
    RowColumn
    + + + + + + + +
    PHASER_OUT0:OUTPUT_CLK_SRC[17, 29, 24][17, 28, 24]
    PHASER_OUT1:OUTPUT_CLK_SRC[20, 29, 56][20, 28, 56]
    PHASER_OUT2:OUTPUT_CLK_SRC[27, 29, 24][27, 28, 24]
    PHASER_OUT3:OUTPUT_CLK_SRC[30, 29, 56][30, 28, 56]
    PHASE_REF00
    DELAYED_REF01
    FREQ_REF10
    DELAYED_PHASE_REF11
    - - +
    +
    +
    +
    +
    CMT bittile 20
    RowColumn
    + + + + + +
    PHASER_OUT0:STG1_BYPASS[17, 28, 25]
    PHASER_OUT1:STG1_BYPASS[20, 28, 57]
    PHASER_OUT2:STG1_BYPASS[27, 28, 25]
    PHASER_OUT3:STG1_BYPASS[30, 28, 57]
    PHASE_REF0
    FREQ_REF1
    - - +
    +
    +
    +
    +
    +
    +
    +
    +
    CMT bittile 21
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + +
    PHASER_IN0:CLKOUT_DIV[19, 28, 58][19, 29, 57][19, 28, 57][19, 29, 56][19, 28, 26][19, 29, 25][19, 28, 25][19, 29, 24]
    PHASER_IN1:CLKOUT_DIV[23, 28, 26][23, 29, 25][23, 28, 25][23, 29, 24][22, 28, 58][22, 29, 57][22, 28, 57][22, 29, 56]
    PHASER_IN2:CLKOUT_DIV[29, 28, 58][29, 29, 57][29, 28, 57][29, 29, 56][29, 28, 26][29, 29, 25][29, 28, 25][29, 29, 24]
    PHASER_IN3:CLKOUT_DIV[33, 28, 26][33, 29, 25][33, 28, 25][33, 29, 24][32, 28, 58][32, 29, 57][32, 28, 57][32, 29, 56]
    PHASER_OUT0:CLKOUT_DIV[18, 29, 12][18, 28, 12][18, 29, 11][18, 28, 11][17, 29, 31][17, 28, 31][17, 29, 30][17, 28, 30]
    PHASER_OUT1:CLKOUT_DIV[21, 29, 44][21, 28, 44][21, 29, 43][21, 28, 43][20, 29, 63][20, 28, 63][20, 29, 62][20, 28, 62]
    PHASER_OUT2:CLKOUT_DIV[28, 29, 12][28, 28, 12][28, 29, 11][28, 28, 11][27, 29, 31][27, 28, 31][27, 29, 30][27, 28, 30]
    PHASER_OUT3:CLKOUT_DIV[31, 29, 44][31, 28, 44][31, 29, 43][31, 28, 43][30, 29, 63][30, 28, 63][30, 29, 62][30, 28, 62]
    NONE00000000
    200010000
    300010001
    400100010
    500100011
    600110100
    700110101
    801000110
    901000111
    1001011000
    1101011001
    1201101010
    1301101011
    1401111100
    1501111101
    1610001110
    - - +
    +
    +
    +
    +
    +
    +
    +
    +
    CMT bittile 22
    RowColumn
    + + + + + + + + + +
    PHASER_IN0:CTL_MODE[19, 28, 24]
    PHASER_IN1:CTL_MODE[22, 28, 56]
    PHASER_IN2:CTL_MODE[29, 28, 24]
    PHASER_IN3:CTL_MODE[32, 28, 56]
    PHASER_OUT0:CTL_MODE[17, 29, 29]
    PHASER_OUT1:CTL_MODE[20, 29, 61]
    PHASER_OUT2:CTL_MODE[27, 29, 29]
    PHASER_OUT3:CTL_MODE[30, 29, 61]
    SOFT0
    HARD1
    - - +
    +
    +
    +
    +
    CMT bittile 23
    RowColumn
    + + + + + + + + + + +
    PHASER_OUT0:MUX.PHASEREFCLK[18, 28, 2][18, 29, 1][18, 28, 1][18, 29, 0]
    PHASER_OUT1:MUX.PHASEREFCLK[21, 28, 34][21, 29, 33][21, 28, 33][21, 29, 32]
    PHASER_OUT2:MUX.PHASEREFCLK[28, 28, 2][28, 29, 1][28, 28, 1][28, 29, 0]
    PHASER_OUT3:MUX.PHASEREFCLK[31, 28, 34][31, 29, 33][31, 28, 33][31, 29, 32]
    NONE0000
    MRCLK0_N0001
    MRCLK1_N0011
    MRCLK00101
    MRCLK10111
    MRCLK0_S1001
    MRCLK1_S1011
    - - +
    +
    +
    +
    +
    CMT bittile 24
    RowColumn
    + + + + + + + + + +
    PHASER_IN0:OUTPUT_CLK_SRC[18, 28, 57][18, 29, 56][18, 28, 54][18, 29, 53]
    PHASER_IN1:OUTPUT_CLK_SRC[22, 28, 25][22, 29, 24][22, 28, 22][22, 29, 21]
    PHASER_IN2:OUTPUT_CLK_SRC[28, 28, 57][28, 29, 56][28, 28, 54][28, 29, 53]
    PHASER_IN3:OUTPUT_CLK_SRC[32, 28, 25][32, 29, 24][32, 28, 22][32, 29, 21]
    PHASE_REF0000
    FREQ_REF0010
    DELAYED_REF0100
    DELAYED_MEM_REF0101
    MEM_REF1000
    DELAYED_PHASE_REF1100
    - - +
    +
    +
    +
    +
    CMT bittile 25
    RowColumn
    + + + + + + + + + + + +
    PHASER_IN0:STG1_PD_UPDATE[18, 29, 58][18, 28, 58][18, 29, 57]
    PHASER_IN1:STG1_PD_UPDATE[22, 29, 26][22, 28, 26][22, 29, 25]
    PHASER_IN2:STG1_PD_UPDATE[28, 29, 58][28, 28, 58][28, 29, 57]
    PHASER_IN3:STG1_PD_UPDATE[32, 29, 26][32, 28, 26][32, 29, 25]
    2000
    3001
    4010
    5011
    6100
    7101
    8110
    9111
    - - +
    +
    +
    +
    +
    CMT bittile 26
    RowColumn
    + + + + + + + + + + +
    PHASER_IN0:MUX.PHASEREFCLK[19, 28, 28][19, 29, 27][19, 28, 27][18, 29, 59]
    PHASER_IN1:MUX.PHASEREFCLK[22, 28, 60][22, 29, 59][22, 28, 59][22, 29, 27]
    PHASER_IN2:MUX.PHASEREFCLK[29, 28, 28][29, 29, 27][29, 28, 27][28, 29, 59]
    PHASER_IN3:MUX.PHASEREFCLK[32, 28, 60][32, 29, 59][32, 28, 59][32, 29, 27]
    DQS_PAD0000
    MRCLK0_N0001
    MRCLK1_N0011
    MRCLK00101
    MRCLK10111
    MRCLK0_S1001
    MRCLK1_S1011
    - - +
    +
    +
    +
    +
    CMT bittile 27
    RowColumn
    + + + + + + + + + + + +
    PHASER_IN0:PD_REVERSE[19, 28, 20][19, 29, 19][19, 28, 19]
    PHASER_IN1:PD_REVERSE[22, 28, 52][22, 29, 51][22, 28, 51]
    PHASER_IN2:PD_REVERSE[29, 28, 20][29, 29, 19][29, 28, 19]
    PHASER_IN3:PD_REVERSE[32, 28, 52][32, 29, 51][32, 28, 51]
    1000
    2001
    3010
    4011
    5100
    6101
    7110
    8111
    - - +
    +
    +
    +
    +
    CMT bittile 28
    RowColumn
    + + + + + + +
    PHASER_IN0:FREQ_REF_DIV[19, 29, 21][19, 28, 21]
    PHASER_IN1:FREQ_REF_DIV[22, 29, 53][22, 28, 53]
    PHASER_IN2:FREQ_REF_DIV[29, 29, 21][29, 28, 21]
    PHASER_IN3:FREQ_REF_DIV[32, 29, 53][32, 28, 53]
    NONE00
    DIV201
    DIV410
    - - +
    +
    CMT bittile 29
    RowColumn
    + + + + +
    HCLK_CMT:MUX.PHASER_REF_BOUNCE1[24, 26, 60][25, 27, 47][24, 26, 16]
    NONE000
    CLKOUT001
    TMUXOUT010
    CCIO1100
    - - +
    +
    +
    +
    +
    +
    +
    CMT bittile 30
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    MMCM:MUX.CLKFBIN_HCLK[24, 27, 28][24, 26, 28][24, 27, 27][24, 26, 27][24, 27, 26][24, 26, 29][24, 27, 29][24, 26, 30][24, 27, 30][24, 26, 31][24, 27, 31]
    MMCM:MUX.CLKIN1_HCLK[24, 28, 23][24, 29, 22][24, 28, 22][24, 29, 21][24, 28, 21][24, 29, 23][24, 28, 24][24, 29, 24][24, 28, 25][24, 29, 25][24, 28, 26]
    MMCM:MUX.CLKIN2_HCLK[24, 26, 23][24, 27, 22][24, 26, 22][24, 27, 21][24, 26, 21][24, 27, 23][24, 26, 24][24, 27, 24][24, 26, 25][24, 27, 25][24, 26, 26]
    PLL:MUX.CLKFBIN_HCLK[25, 26, 35][25, 27, 35][25, 26, 36][25, 27, 36][25, 26, 37][25, 27, 34][25, 26, 34][25, 27, 33][25, 26, 33][25, 27, 32][25, 26, 32]
    PLL:MUX.CLKIN1_HCLK[25, 29, 40][25, 28, 41][25, 29, 41][25, 28, 42][25, 29, 42][25, 28, 40][25, 29, 39][25, 28, 39][25, 29, 38][25, 28, 38][25, 29, 37]
    PLL:MUX.CLKIN2_HCLK[25, 27, 40][25, 26, 41][25, 27, 41][25, 26, 42][25, 27, 42][25, 26, 40][25, 27, 39][25, 26, 39][25, 27, 38][25, 26, 38][25, 27, 37]
    NONE00000000000
    HCLK000001000001
    HCLK100001000010
    HCLK200001000100
    HCLK300001001000
    HCLK400001010000
    HCLK500001100000
    HCLK600010000001
    HCLK700010000010
    HCLK800010000100
    HCLK900010001000
    HCLK1000010010000
    HCLK1100010100000
    RCLK000100000001
    RCLK100100000010
    RCLK200100000100
    RCLK300100001000
    PHASER_REF_BOUNCE000100010000
    PHASER_REF_BOUNCE100100100000
    HIN401000000001
    HIN501000000010
    HIN601000000100
    HIN701000001000
    PHASER_REF_BOUNCE201000010000
    PHASER_REF_BOUNCE301000100000
    HIN810000000001
    HIN910000000010
    HIN1010000000100
    HIN1110000001000
    HIN1210000010000
    HIN1310000100000
    - - +
    +
    CMT bittile 31
    RowColumn
    + + + + +
    HCLK_CMT:MUX.PHASER_REF_BOUNCE0[24, 27, 61][24, 27, 60][24, 26, 61]
    NONE000
    CLKOUT001
    TMUXOUT010
    CCIO0100
    - - +
    +
    +
    +
    +
    CMT bittile 32
    RowColumn
    + + + + + + + + + + + + + + + + + + + + +
    HCLK_CMT:MUX.LCLK0_CMT_D[24, 26, 17][24, 27, 16][24, 27, 17][24, 26, 18][24, 27, 18][24, 26, 19][24, 27, 19][24, 26, 20][24, 27, 20]
    HCLK_CMT:MUX.LCLK0_CMT_U[25, 27, 46][25, 26, 47][25, 26, 46][25, 27, 45][25, 26, 45][25, 27, 44][25, 26, 44][25, 27, 43][25, 26, 43]
    HCLK_CMT:MUX.LCLK1_CMT_D[24, 28, 17][24, 29, 16][24, 29, 17][24, 28, 18][24, 29, 18][24, 28, 19][24, 29, 19][24, 28, 20][24, 29, 20]
    HCLK_CMT:MUX.LCLK1_CMT_U[25, 29, 46][25, 28, 47][25, 28, 46][25, 29, 45][25, 28, 45][25, 29, 44][25, 28, 44][25, 29, 43][25, 28, 43]
    NONE000000000
    RCLK0001000001
    RCLK1001000010
    RCLK2001000100
    RCLK3001001000
    HCLK0010000001
    HCLK1010000010
    HCLK2010000100
    HCLK3010001000
    HCLK4010010000
    HCLK5010100000
    HCLK6100000001
    HCLK7100000010
    HCLK8100000100
    HCLK9100001000
    HCLK10100010000
    HCLK11100100000
    - - +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    CMT bittile 33
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    HCLK_CMT:MUX.HOUT0[24, 26, 57][24, 27, 57][24, 26, 58][24, 27, 58][24, 26, 59][24, 27, 59][24, 26, 53][24, 26, 54][24, 27, 53][24, 27, 55][24, 27, 56][24, 26, 56][24, 26, 55][24, 27, 54]
    HCLK_CMT:MUX.HOUT1[24, 28, 57][24, 29, 57][24, 28, 58][24, 29, 58][24, 28, 59][24, 29, 59][24, 28, 53][24, 28, 54][24, 29, 53][24, 29, 55][24, 29, 56][24, 28, 56][24, 28, 55][24, 29, 54]
    HCLK_CMT:MUX.HOUT10[25, 29, 13][25, 28, 13][25, 29, 12][25, 28, 12][25, 29, 11][25, 28, 11][25, 29, 17][25, 29, 16][25, 28, 17][25, 28, 15][25, 28, 14][25, 29, 14][25, 29, 15][25, 28, 16]
    HCLK_CMT:MUX.HOUT11[25, 27, 20][25, 26, 20][25, 27, 19][25, 26, 19][25, 27, 18][25, 26, 18][25, 27, 24][25, 27, 23][25, 26, 24][25, 26, 22][25, 26, 21][25, 27, 21][25, 27, 22][25, 26, 23]
    HCLK_CMT:MUX.HOUT12[25, 29, 20][25, 28, 20][25, 29, 19][25, 28, 19][25, 29, 18][25, 28, 18][25, 29, 24][25, 29, 23][25, 28, 24][25, 28, 22][25, 28, 21][25, 29, 21][25, 29, 22][25, 28, 23]
    HCLK_CMT:MUX.HOUT13[25, 27, 27][25, 26, 27][25, 27, 26][25, 26, 26][25, 27, 25][25, 26, 25][25, 27, 31][25, 27, 30][25, 26, 31][25, 26, 29][25, 26, 28][25, 27, 28][25, 27, 29][25, 26, 30]
    HCLK_CMT:MUX.HOUT2[24, 26, 50][24, 27, 50][24, 26, 51][24, 27, 51][24, 26, 52][24, 27, 52][24, 26, 46][24, 26, 47][24, 27, 46][24, 27, 48][24, 27, 49][24, 26, 49][24, 26, 48][24, 27, 47]
    HCLK_CMT:MUX.HOUT3[24, 28, 50][24, 29, 50][24, 28, 51][24, 29, 51][24, 28, 52][24, 29, 52][24, 28, 46][24, 28, 47][24, 29, 46][24, 29, 48][24, 29, 49][24, 28, 49][24, 28, 48][24, 29, 47]
    HCLK_CMT:MUX.HOUT4[24, 26, 43][24, 27, 43][24, 26, 44][24, 27, 44][24, 26, 45][24, 27, 45][24, 26, 39][24, 26, 40][24, 27, 39][24, 27, 41][24, 27, 42][24, 26, 42][24, 26, 41][24, 27, 40]
    HCLK_CMT:MUX.HOUT5[24, 28, 43][24, 29, 43][24, 28, 44][24, 29, 44][24, 28, 45][24, 29, 45][24, 28, 39][24, 28, 40][24, 29, 39][24, 29, 41][24, 29, 42][24, 28, 42][24, 28, 41][24, 29, 40]
    HCLK_CMT:MUX.HOUT6[24, 26, 36][24, 27, 36][24, 26, 37][24, 27, 37][24, 26, 38][24, 27, 38][24, 26, 32][24, 26, 33][24, 27, 32][24, 27, 34][24, 27, 35][24, 26, 35][24, 26, 34][24, 27, 33]
    HCLK_CMT:MUX.HOUT7[25, 27, 6][25, 26, 6][25, 27, 5][25, 26, 5][25, 27, 4][25, 26, 4][25, 27, 10][25, 27, 9][25, 26, 10][25, 26, 8][25, 26, 7][25, 27, 7][25, 27, 8][25, 26, 9]
    HCLK_CMT:MUX.HOUT8[25, 29, 6][25, 28, 6][25, 29, 5][25, 28, 5][25, 29, 4][25, 28, 4][25, 29, 10][25, 29, 9][25, 28, 10][25, 28, 8][25, 28, 7][25, 29, 7][25, 29, 8][25, 28, 9]
    HCLK_CMT:MUX.HOUT9[25, 27, 13][25, 26, 13][25, 27, 12][25, 26, 12][25, 27, 11][25, 26, 11][25, 27, 17][25, 27, 16][25, 26, 17][25, 26, 15][25, 26, 14][25, 27, 14][25, 27, 15][25, 26, 16]
    NONE00000000000000
    HCLK000000100000001
    HCLK600000100000010
    HIN400000100000100
    HIN800000100001000
    MMCM_CLKOUT600000100010000
    PLL_CLKFBOUT00000100100000
    MMCM_CLKOUT200000101000000
    PLL_CLKOUT000000110000000
    HCLK100001000000001
    HCLK700001000000010
    HIN500001000000100
    HIN900001000001000
    MMCM_CLKFBOUT00001000010000
    PLL_TMUXOUT00001000100000
    MMCM_CLKOUT2B00001001000000
    PLL_CLKOUT100001010000000
    HCLK200010000000001
    HCLK800010000000010
    HIN600010000000100
    HIN1000010000001000
    MMCM_CLKFBOUTB00010000010000
    MMCM_CLKOUT000010000100000
    MMCM_CLKOUT300010001000000
    PLL_CLKOUT200010010000000
    HCLK300100000000001
    HCLK900100000000010
    HIN700100000000100
    HIN1100100000001000
    MMCM_TMUXOUT00100000010000
    MMCM_CLKOUT0B00100000100000
    MMCM_CLKOUT3B00100001000000
    PLL_CLKOUT300100010000000
    HCLK401000000000001
    HCLK1001000000000010
    PHASER_REF_BOUNCE201000000000100
    HIN1201000000001000
    PHASER_REF_BOUNCE001000000010000
    MMCM_CLKOUT101000000100000
    MMCM_CLKOUT401000001000000
    PLL_CLKOUT401000010000000
    HCLK510000000000001
    HCLK1110000000000010
    PHASER_REF_BOUNCE310000000000100
    HIN1310000000001000
    PHASER_REF_BOUNCE110000000010000
    MMCM_CLKOUT1B10000000100000
    MMCM_CLKOUT510000001000000
    PLL_CLKOUT510000010000000
    - - +
    +
    CMT bittile 34
    RowColumn
    + + + +
    HCLK_CMT:MUX.FREQ_BB3[25, 26, 3][25, 27, 3][24, 28, 62]
    NONE000
    CKINT3011
    CCIO3101
    - - +
    +
    CMT bittile 35
    RowColumn
    + + + +
    HCLK_CMT:MUX.FREQ_BB1[25, 28, 1][25, 29, 1][24, 28, 63]
    NONE000
    CKINT1011
    CCIO1101
    - - +
    +
    CMT bittile 36
    RowColumn
    + + + +
    HCLK_CMT:MUX.FREQ_BB2[25, 28, 0][25, 29, 0][24, 29, 62]
    NONE000
    CKINT2011
    CCIO2101
    - - +
    +
    CMT bittile 37
    RowColumn
    + + + +
    HCLK_CMT:MUX.FREQ_BB0[25, 28, 3][25, 29, 3][24, 29, 63]
    NONE000
    CKINT0011
    CCIO0101
    - - +
    +
    CMT bittile 38
    RowColumn
    + + + + + + + + + + + + + + +
    BUFMRCE0:MUX.I[50, 27, 31][50, 26, 31][50, 27, 28][50, 27, 30][25, 26, 1][25, 27, 0][25, 26, 0][50, 26, 28][25, 29, 2][25, 28, 2]
    NONE0000000000
    CCIO00000000001
    HIN40000001110
    HIN50000010110
    HIN60000100110
    HIN70001000110
    HIN80010001010
    HIN90010010010
    HIN100010100010
    HIN110011000010
    CKINT00100000110
    HIN120110000010
    CKINT11000000110
    HIN131010000010
    - - +
    +
    CMT bittile 39
    RowColumn
    + + + + +
    HCLK_CMT:MUX.PHASER_REF_BOUNCE3[25, 29, 26][25, 29, 27][25, 28, 27]
    NONE000
    CLKOUT001
    TMUXOUT010
    CCIO3100
    - - +
    +
    CMT bittile 40
    RowColumn
    + + + + +
    HCLK_CMT:MUX.PHASER_REF_BOUNCE2[25, 28, 25][25, 28, 26][25, 29, 25]
    NONE000
    CLKOUT001
    TMUXOUT010
    CCIO2100
    - - +
    +
    CMT bittile 41
    RowColumn
    + + + + +
    PHY_CONTROL:CLK_RATIO[34, 28, 45][34, 29, 44][34, 28, 44]
    1000
    2001
    4010
    8100
    - - +
    +
    +
    +
    +
    CMT bittile 42
    RowColumn
    + + + + + + + + +
    CMT_TOP:MUX.FREQ_BB0[36, 28, 60][36, 29, 59][36, 29, 34]
    CMT_TOP:MUX.FREQ_BB1[36, 28, 61][36, 29, 60][36, 28, 35]
    CMT_TOP:MUX.FREQ_BB2[36, 28, 62][36, 29, 61][36, 29, 35]
    CMT_TOP:MUX.FREQ_BB3[36, 28, 63][36, 29, 62][36, 28, 36]
    NONE000
    PLL_CLKOUT0001
    PLL_CLKOUT1011
    PLL_CLKOUT2101
    PLL_CLKOUT3111
    - - +
    +
    CMT bittile 43
    RowColumn
    + + + + + +
    CMT_TOP:MUX.SYNCIN[36, 28, 59][36, 29, 58][36, 28, 58]
    PLL_CLKOUT2000
    FREQ_BB0001
    FREQ_BB1011
    FREQ_BB2101
    FREQ_BB3111
    - - +
    +
    CMT bittile 44
    RowColumn
    + + + + + +
    CMT_TOP:MUX.FREQREFCLK[36, 29, 37][36, 28, 37][36, 29, 36]
    PLL_CLKOUT0000
    FREQ_BB0001
    FREQ_BB1011
    FREQ_BB2101
    FREQ_BB3111
    - - +
    +
    CMT bittile 45
    RowColumn
    + + + + + +
    CMT_TOP:MUX.MEMREFCLK[36, 29, 57][36, 28, 41][36, 29, 40]
    PLL_CLKOUT1000
    FREQ_BB0001
    FREQ_BB1011
    FREQ_BB2101
    FREQ_BB3111
    - - +
    +
    CMT bittile 46
    RowColumn
    + + + + + + +
    PLL:MUX.CLKIN1[37, 28, 10][37, 29, 9][37, 28, 9]
    FREQ_BB0000
    FREQ_BB1001
    FREQ_BB2010
    FREQ_BB3011
    CLKIN1_HCLK100
    CLKIN1_CKINT101
    - - +
    +
    CMT bittile 47
    RowColumn
    + + + + + + +
    PLL:MUX.CLKIN2[37, 29, 8][37, 28, 8][37, 29, 7]
    FREQ_BB0000
    FREQ_BB1001
    FREQ_BB2010
    FREQ_BB3011
    CLKIN2_HCLK100
    CLKIN2_CKINT101
    - - +
    +
    CMT bittile 48
    RowColumn
    + + + + + + +
    PLL:MUX.CLKFBIN[37, 29, 11][37, 28, 11][37, 29, 10]
    FREQ_BB0000
    FREQ_BB1001
    FREQ_BB2010
    FREQ_BB3011
    CLKFBIN_HCLK100
    CLKFBIN_CKINT101
    - - +
    +
    +
    CMT bittile 49
    RowColumn
    + + + + + + + + +
    HCLK_CMT:MUX.PERF0[50, 26, 20][50, 27, 19][50, 26, 18][50, 26, 17][50, 26, 16]
    HCLK_CMT:MUX.PERF1[50, 27, 20][50, 26, 19][50, 27, 18][50, 27, 17][50, 27, 16]
    NONE00000
    PHASER_IN_RCLK001001
    PHASER_IN_RCLK101010
    PHASER_IN_RCLK201100
    MMCM_PERF010001
    MMCM_PERF110010
    PHASER_IN_RCLK310100
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
    +
    CMT bittile 50
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14----------------------------CMT:ENABLE.RCLK0CMT:ENABLE.RCLK1
    15----------------------------CMT:ENABLE.RCLK2CMT:ENABLE.RCLK3
    + + + + + + + + + + + + + + +
    BUFMRCE1:MUX.I[50, 26, 30][50, 27, 29][50, 27, 27][50, 26, 29][25, 27, 2][25, 26, 2][25, 27, 1][50, 26, 27][50, 27, 26][50, 26, 26]
    NONE0000000000
    CCIO30000000001
    HIN40000001110
    HIN50000010110
    HIN60000100110
    HIN70001000110
    HIN80010001010
    HIN90010010010
    HIN100010100010
    HIN110011000010
    CKINT00100000110
    HIN120110000010
    CKINT11000000110
    HIN131010000010
    -
    -
    -
    -
    +
    +
    - - - - - + + + + + + + + + +
    CMT:ENABLE.RCLK0[50, 28, 14]
    CMT:ENABLE.RCLK1[50, 29, 14]
    CMT:ENABLE.RCLK2[50, 28, 15]
    CMT:ENABLE.RCLK3[50, 29, 15]
    Non-inverted[0]
    HCLK_CMT:MUX.PERF2[50, 28, 20][50, 29, 19][50, 28, 18][50, 28, 17][50, 28, 16]
    HCLK_CMT:MUX.PERF3[50, 29, 20][50, 28, 19][50, 29, 18][50, 29, 17][50, 29, 16]
    NONE00000
    PHASER_IN_RCLK001001
    PHASER_IN_RCLK101010
    PHASER_IN_RCLK201100
    MMCM_PERF210001
    MMCM_PERF310010
    PHASER_IN_RCLK310100
    +
    +
    + + + + +
    BUFMRCE0:INV.CE[50, 28, 28]
    BUFMRCE1:INV.CE[50, 29, 28]
    Inverted~[0]
    +
    +
    + + + + +
    BUFMRCE0:CE_TYPE[50, 28, 31]
    BUFMRCE1:CE_TYPE[50, 29, 31]
    SYNC0
    ASYNC1

    @@ -645,6 +8901,476 @@

    CMT_FIFO ARRAY_MODE_4_X_81

    +
    +

    MMCM Tables

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameMMCM:CPMMCM:RESMMCM:LFHF
    HIGH:1000
    HIGH:101550
    HIGH:111590
    HIGH:121310
    HIGH:131590
    HIGH:141590
    HIGH:151590
    HIGH:161590
    HIGH:171550
    HIGH:181550
    HIGH:191210
    HIGH:24150
    HIGH:201210
    HIGH:211210
    HIGH:225120
    HIGH:235120
    HIGH:245120
    HIGH:255120
    HIGH:26340
    HIGH:27340
    HIGH:28340
    HIGH:29340
    HIGH:35110
    HIGH:30340
    HIGH:31340
    HIGH:32340
    HIGH:33340
    HIGH:34340
    HIGH:35340
    HIGH:36340
    HIGH:37340
    HIGH:38340
    HIGH:39340
    HIGH:4770
    HIGH:40340
    HIGH:41340
    HIGH:42280
    HIGH:43280
    HIGH:44280
    HIGH:45280
    HIGH:46280
    HIGH:47710
    HIGH:48710
    HIGH:494120
    HIGH:51370
    HIGH:504120
    HIGH:514120
    HIGH:524120
    HIGH:53610
    HIGH:54610
    HIGH:55560
    HIGH:56560
    HIGH:57560
    HIGH:58240
    HIGH:59240
    HIGH:614110
    HIGH:60240
    HIGH:61240
    HIGH:624100
    HIGH:633120
    HIGH:643120
    HIGH:714130
    HIGH:81530
    HIGH:91450
    LOW:1000
    LOW:10250
    LOW:11290
    LOW:122140
    LOW:132140
    LOW:142140
    LOW:152140
    LOW:16210
    LOW:17210
    LOW:18210
    LOW:19260
    LOW:22150
    LOW:20260
    LOW:21260
    LOW:22260
    LOW:23260
    LOW:24260
    LOW:25260
    LOW:262100
    LOW:272100
    LOW:282100
    LOW:292100
    LOW:32150
    LOW:302100
    LOW:312120
    LOW:322120
    LOW:332120
    LOW:342120
    LOW:352120
    LOW:362120
    LOW:372120
    LOW:382120
    LOW:392120
    LOW:42150
    LOW:402120
    LOW:412120
    LOW:422120
    LOW:432120
    LOW:442120
    LOW:452120
    LOW:462120
    LOW:472120
    LOW:48220
    LOW:49220
    LOW:5270
    LOW:50220
    LOW:51220
    LOW:52220
    LOW:53220
    LOW:54220
    LOW:55220
    LOW:56220
    LOW:57220
    LOW:58220
    LOW:59220
    LOW:62110
    LOW:60220
    LOW:61220
    LOW:62220
    LOW:63220
    LOW:64220
    LOW:72130
    LOW:8230
    LOW:9250
    SS:1000
    SS:10253
    SS:11293
    SS:122143
    SS:132143
    SS:142143
    SS:152143
    SS:16213
    SS:17213
    SS:18213
    SS:19263
    SS:22153
    SS:20263
    SS:21263
    SS:22263
    SS:23263
    SS:24263
    SS:25263
    SS:262103
    SS:272103
    SS:282103
    SS:292103
    SS:32153
    SS:302103
    SS:312123
    SS:322123
    SS:332123
    SS:342123
    SS:352123
    SS:362123
    SS:372123
    SS:382123
    SS:392123
    SS:42153
    SS:402123
    SS:412123
    SS:422123
    SS:432123
    SS:442123
    SS:452123
    SS:462123
    SS:472123
    SS:48223
    SS:49223
    SS:5273
    SS:50223
    SS:51223
    SS:52223
    SS:53223
    SS:54223
    SS:55223
    SS:56223
    SS:57223
    SS:58223
    SS:59223
    SS:62113
    SS:60223
    SS:61223
    SS:62223
    SS:63223
    SS:64223
    SS:72133
    SS:8233
    SS:9253
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NameMMCM:LOCK_REF_DLYMMCM:LOCK_FB_DLYMMCM:LOCK_CNTMMCM:LOCK_SAT_HIGHMMCM:UNLOCK_CNT
    166100010011
    102828100010011
    11313190010011
    12313182510011
    13313175010011
    14313170010011
    15313165010011
    16313162510011
    17313157510011
    18313155010011
    19313152510011
    266100010011
    20313150010011
    21313147510011
    22313145010011
    23313142510011
    24313140010011
    25313140010011
    26313137510011
    27313135010011
    28313135010011
    29313132510011
    388100010011
    30313132510011
    31313130010011
    32313130010011
    33313130010011
    34313127510011
    35313127510011
    36313127510011
    37313125010011
    38313125010011
    39313125010011
    41111100010011
    40313125010011
    41313125010011
    42313125010011
    43313125010011
    44313125010011
    45313125010011
    46313125010011
    47313125010011
    48313125010011
    49313125010011
    51414100010011
    50313125010011
    51313125010011
    52313125010011
    53313125010011
    54313125010011
    55313125010011
    56313125010011
    57313125010011
    58313125010011
    59313125010011
    61717100010011
    60313125010011
    61313125010011
    62313125010011
    63313125010011
    64313125010011
    71919100010011
    82222100010011
    92525100010011
    +
    +
    +

    PLL Tables

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NamePLL:CPPLL:RESPLL:LFHF
    HIGH:1000
    HIGH:101570
    HIGH:1115110
    HIGH:1215130
    HIGH:131530
    HIGH:141450
    HIGH:151550
    HIGH:161550
    HIGH:171550
    HIGH:181550
    HIGH:19760
    HIGH:2370
    HIGH:20760
    HIGH:21760
    HIGH:22760
    HIGH:235120
    HIGH:245120
    HIGH:255120
    HIGH:261210
    HIGH:271210
    HIGH:281210
    HIGH:291210
    HIGH:35150
    HIGH:301210
    HIGH:311210
    HIGH:321210
    HIGH:331210
    HIGH:34420
    HIGH:35420
    HIGH:36420
    HIGH:37280
    HIGH:38280
    HIGH:39280
    HIGH:47150
    HIGH:40340
    HIGH:41280
    HIGH:42280
    HIGH:43280
    HIGH:44280
    HIGH:45280
    HIGH:46280
    HIGH:47280
    HIGH:48280
    HIGH:49280
    HIGH:57110
    HIGH:50280
    HIGH:51280
    HIGH:52280
    HIGH:53280
    HIGH:544120
    HIGH:554120
    HIGH:564120
    HIGH:574120
    HIGH:584120
    HIGH:594120
    HIGH:61370
    HIGH:604120
    HIGH:61240
    HIGH:62240
    HIGH:63240
    HIGH:64240
    HIGH:714110
    HIGH:814130
    HIGH:915130
    LOW:1000
    LOW:10210
    LOW:11210
    LOW:12260
    LOW:13260
    LOW:14260
    LOW:15260
    LOW:162100
    LOW:172100
    LOW:182100
    LOW:192100
    LOW:22150
    LOW:202120
    LOW:212120
    LOW:222120
    LOW:232120
    LOW:242120
    LOW:252120
    LOW:262120
    LOW:272120
    LOW:282120
    LOW:292120
    LOW:3270
    LOW:302120
    LOW:31220
    LOW:32220
    LOW:33220
    LOW:34220
    LOW:35220
    LOW:36220
    LOW:37220
    LOW:38220
    LOW:39220
    LOW:42130
    LOW:40220
    LOW:413120
    LOW:423120
    LOW:433120
    LOW:443120
    LOW:453120
    LOW:463120
    LOW:473120
    LOW:48240
    LOW:49240
    LOW:5250
    LOW:50240
    LOW:51240
    LOW:52240
    LOW:53240
    LOW:54240
    LOW:55240
    LOW:56240
    LOW:57240
    LOW:58240
    LOW:59240
    LOW:6250
    LOW:60240
    LOW:61240
    LOW:62240
    LOW:63240
    LOW:64240
    LOW:7290
    LOW:82140
    LOW:92140
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    NamePLL:LOCK_REF_DLYPLL:LOCK_FB_DLYPLL:LOCK_CNTPLL:LOCK_SAT_HIGHPLL:UNLOCK_CNT
    166100010011
    102828100010011
    11313190010011
    12313182510011
    13313175010011
    14313170010011
    15313165010011
    16313162510011
    17313157510011
    18313155010011
    19313152510011
    266100010011
    20313150010011
    21313147510011
    22313145010011
    23313142510011
    24313140010011
    25313140010011
    26313137510011
    27313135010011
    28313135010011
    29313132510011
    388100010011
    30313132510011
    31313130010011
    32313130010011
    33313130010011
    34313127510011
    35313127510011
    36313127510011
    37313125010011
    38313125010011
    39313125010011
    41111100010011
    40313125010011
    41313125010011
    42313125010011
    43313125010011
    44313125010011
    45313125010011
    46313125010011
    47313125010011
    48313125010011
    49313125010011
    51414100010011
    50313125010011
    51313125010011
    52313125010011
    53313125010011
    54313125010011
    55313125010011
    56313125010011
    57313125010011
    58313125010011
    59313125010011
    61717100010011
    60313125010011
    61313125010011
    62313125010011
    63313125010011
    64313125010011
    71919100010011
    82222100010011
    92525100010011
    +
    diff --git a/xilinx/virtex7/config.html b/xilinx/virtex7/config.html new file mode 100644 index 00000000..c27072bf --- /dev/null +++ b/xilinx/virtex7/config.html @@ -0,0 +1,1138 @@ + + + + + + + Configuration registers — Project Combine documentation + + + + + + + + + + + + + + + + +
    + + +
    + +
    +
    +
    + +
    +
    +
    +
    + +
    +

    Configuration registers

    +
    +

    Todo

    +

    document

    +
    +
    +

    COR

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.COR bittile 0
    RowColumn
    0
    0STARTUP:GWE_CYCLE[0]
    1STARTUP:GWE_CYCLE[1]
    2STARTUP:GWE_CYCLE[2]
    3STARTUP:GTS_CYCLE[0]
    4STARTUP:GTS_CYCLE[1]
    5STARTUP:GTS_CYCLE[2]
    6STARTUP:LCK_CYCLE[0]
    7STARTUP:LCK_CYCLE[1]
    8STARTUP:LCK_CYCLE[2]
    9STARTUP:MATCH_CYCLE[0]
    10STARTUP:MATCH_CYCLE[1]
    11STARTUP:MATCH_CYCLE[2]
    12STARTUP:DONE_CYCLE[0]
    13STARTUP:DONE_CYCLE[1]
    14STARTUP:DONE_CYCLE[2]
    15STARTUP:STARTUPCLK[0]
    16STARTUP:STARTUPCLK[1]
    17STARTUP:CONFIG_RATE[0]
    18STARTUP:CONFIG_RATE[1]
    19STARTUP:CONFIG_RATE[2]
    20STARTUP:CONFIG_RATE[3]
    21CAPTURE:EXTMASTERCCLK_DIV[0]
    STARTUP:CONFIG_RATE[4]
    22CAPTURE:EXTMASTERCCLK_DIV[1]
    STARTUP:CONFIG_RATE[5]
    23CAPTURE:ONESHOT
    24STARTUP:DRIVE_DONE
    25STARTUP:DONE_PIPE
    26CAPTURE:EXTMASTERCCLK_EN
    27STARTUP:DONE_SIGNALS_POWERDOWN
    +
    +
    + + + + + + + + + + + +
    STARTUP:GTS_CYCLE[0, 0, 5][0, 0, 4][0, 0, 3]
    STARTUP:GWE_CYCLE[0, 0, 2][0, 0, 1][0, 0, 0]
    1000
    2001
    3010
    4011
    5100
    6101
    DONE110
    KEEP111
    +
    +
    + + + + + + + + + + + +
    STARTUP:LCK_CYCLE[0, 0, 8][0, 0, 7][0, 0, 6]
    STARTUP:MATCH_CYCLE[0, 0, 11][0, 0, 10][0, 0, 9]
    0000
    1001
    2010
    3011
    4100
    5101
    6110
    NOWAIT111
    +
    + + + + + + + + + +
    STARTUP:DONE_CYCLE[0, 0, 14][0, 0, 13][0, 0, 12]
    1000
    2001
    3010
    4011
    5100
    6101
    KEEP111
    +
    + + + + + +
    STARTUP:STARTUPCLK[0, 0, 16][0, 0, 15]
    CCLK00
    USERCLK01
    JTAGCLK10
    +
    + + + + + + + + + + + + + +
    STARTUP:CONFIG_RATE[0, 0, 22][0, 0, 21][0, 0, 20][0, 0, 19][0, 0, 18][0, 0, 17]
    3000000
    9000001
    22000100
    40001011
    6010000
    16010001
    26010010
    50010101
    66011000
    12100000
    33100001
    +
    + + + + + + +
    CAPTURE:EXTMASTERCCLK_DIV[0, 0, 22][0, 0, 21]
    800
    401
    210
    111
    +
    +
    +
    +
    +
    + + + + + + + +
    CAPTURE:EXTMASTERCCLK_EN[0, 0, 26]
    CAPTURE:ONESHOT[0, 0, 23]
    STARTUP:DONE_PIPE[0, 0, 25]
    STARTUP:DONE_SIGNALS_POWERDOWN[0, 0, 27]
    STARTUP:DRIVE_DONE[0, 0, 24]
    Non-inverted[0]
    +
    +
    +

    COR1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.COR1 bittile 0
    RowColumn
    0
    0MISC:BPI_PAGE_SIZE[0]
    1MISC:BPI_PAGE_SIZE[1]
    2MISC:BPI_1ST_READ_CYCLE[0]
    3MISC:BPI_1ST_READ_CYCLE[1]
    4-
    5-
    6MISC:POST_CRC_RECONFIG
    7MISC:POST_CRC_SEL
    8MISC:POST_CRC_EN
    9~MISC:POST_CRC_INIT_FLAG
    10MISC:TRIM_REG[0]
    11MISC:TRIM_REG[1]
    12MISC:TRIM_BITSTREAM
    13-
    14-
    15~MISC:POST_CRC_KEEP
    16MISC:POST_CRC_CORRECT
    17MISC:PERSIST_DEASSERT_AT_DESYNC
    18-
    19-
    20-
    21MISC:CFG_IO_ACCESS_TDO
    22-
    23-
    24-
    25-
    26MISC:POST_CRC_CLK
    27MISC:POST_CRC_FREQ[0]
    28MISC:POST_CRC_FREQ[1]
    29MISC:POST_CRC_FREQ[2]
    30-
    31MISC:XADC_PARTIAL_RECONFIG
    +
    + + + + + +
    MISC:BPI_PAGE_SIZE[0, 0, 1][0, 0, 0]
    100
    401
    810
    +
    + + + + + + +
    MISC:BPI_1ST_READ_CYCLE[0, 0, 3][0, 0, 2]
    100
    201
    310
    411
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + +
    MISC:CFG_IO_ACCESS_TDO[0, 0, 21]
    MISC:PERSIST_DEASSERT_AT_DESYNC[0, 0, 17]
    MISC:POST_CRC_CORRECT[0, 0, 16]
    MISC:POST_CRC_EN[0, 0, 8]
    MISC:POST_CRC_RECONFIG[0, 0, 6]
    MISC:POST_CRC_SEL[0, 0, 7]
    MISC:TRIM_BITSTREAM[0, 0, 12]
    MISC:XADC_PARTIAL_RECONFIG[0, 0, 31]
    Non-inverted[0]
    +
    +
    + + + + +
    MISC:POST_CRC_INIT_FLAG[0, 0, 9]
    MISC:POST_CRC_KEEP[0, 0, 15]
    Inverted~[0]
    +
    + + + +
    MISC:TRIM_REG[0, 0, 11][0, 0, 10]
    Non-inverted[1][0]
    +
    + + + + +
    MISC:POST_CRC_CLK[0, 0, 26]
    CFG_CLK0
    INTERNAL1
    +
    + + + + + + + + + +
    MISC:POST_CRC_FREQ[0, 0, 29][0, 0, 28][0, 0, 27]
    50000
    25001
    13010
    6011
    3100
    2101
    1110
    +
    +
    +

    CTL

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.CTL bittile 0
    RowColumn
    0
    0MISC:GTS_USR_B
    1-
    2-
    3MISC:PERSIST
    4MISC:SECURITY[0]
    5MISC:SECURITY[1]
    6MISC:ENCRYPT
    7FRAME_ECC:FARSRC
    8~MISC:GLUTMASK
    9~MISC:SELECTMAP_ABORT
    10~MISC:CONFIG_FALLBACK
    11MISC:SEC_ERROR
    12MISC:OVERTEMP_POWERDOWN
    13~MISC:INIT_SIGNALS_ERROR
    14MISC:SEC_STATUS
    15-
    16-
    17-
    18-
    19-
    20-
    21-
    22-
    23-
    24-
    25-
    26-
    27-
    28-
    29MISC:SEC_ALL
    30MISC:ICAP_SELECT
    31MISC:ENCRYPT_KEY_SELECT
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + +
    MISC:ENCRYPT[0, 0, 6]
    MISC:GTS_USR_B[0, 0, 0]
    MISC:OVERTEMP_POWERDOWN[0, 0, 12]
    MISC:PERSIST[0, 0, 3]
    MISC:SEC_ALL[0, 0, 29]
    MISC:SEC_ERROR[0, 0, 11]
    MISC:SEC_STATUS[0, 0, 14]
    Non-inverted[0]
    +
    + + + + + +
    MISC:SECURITY[0, 0, 5][0, 0, 4]
    NONE00
    LEVEL101
    LEVEL210
    +
    + + + + +
    FRAME_ECC:FARSRC[0, 0, 7]
    EFAR0
    FAR1
    +
    +
    +
    +
    + + + + + + +
    MISC:CONFIG_FALLBACK[0, 0, 10]
    MISC:GLUTMASK[0, 0, 8]
    MISC:INIT_SIGNALS_ERROR[0, 0, 13]
    MISC:SELECTMAP_ABORT[0, 0, 9]
    Inverted~[0]
    +
    + + + + +
    MISC:ICAP_SELECT[0, 0, 30]
    TOP0
    BOTTOM1
    +
    + + + + +
    MISC:ENCRYPT_KEY_SELECT[0, 0, 31]
    BBRAM0
    EFUSE1
    +
    +
    +

    CTL1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.CTL1 bittile 0
    RowColumn
    0
    0MISC:MODE_PIN_TEST[0]
    1MISC:MODE_PIN_TEST[1]
    2MISC:DIS_VGG_REG
    3MISC:ENABLE_VGG_CLAMP
    4MISC:VGG_POS_GAIN_SEL
    5-
    6MISC:VGG_NEG_GAIN_SEL[0]
    7MISC:VGG_NEG_GAIN_SEL[1]
    8MISC:VGG_NEG_GAIN_SEL[2]
    9MISC:VGG_NEG_GAIN_SEL[3]
    10MISC:VGG_NEG_GAIN_SEL[4]
    11-
    12-
    13MISC:VGG_SEL[0]
    14MISC:VGG_SEL[1]
    15MISC:VGG_SEL[2]
    16MISC:VGG_SEL[3]
    17MISC:VGG_SEL[4]
    18-
    19-
    20MISC:ICAP_ENCRYPTION
    +
    + + + + + +
    MISC:MODE_PIN_TEST[0, 0, 1][0, 0, 0]
    DISABLE00
    TEST001
    TEST110
    +
    +
    +
    +
    + + + + + + +
    MISC:DIS_VGG_REG[0, 0, 2]
    MISC:ENABLE_VGG_CLAMP[0, 0, 3]
    MISC:ICAP_ENCRYPTION[0, 0, 20]
    MISC:VGG_POS_GAIN_SEL[0, 0, 4]
    Non-inverted[0]
    +
    +
    + + + + +
    MISC:VGG_NEG_GAIN_SEL[0, 0, 10][0, 0, 9][0, 0, 8][0, 0, 7][0, 0, 6]
    MISC:VGG_SEL[0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14][0, 0, 13]
    Non-inverted[4][3][2][1][0]
    +
    +
    +

    BSPI

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.BSPI bittile 0
    RowColumn
    0
    0MISC:SPI_OPCODE[0]
    1MISC:SPI_OPCODE[1]
    2MISC:SPI_OPCODE[2]
    3MISC:SPI_OPCODE[3]
    4MISC:SPI_OPCODE[4]
    5MISC:SPI_OPCODE[5]
    6MISC:SPI_OPCODE[6]
    7MISC:SPI_OPCODE[7]
    8MISC:SPI_BUSWIDTH[0]
    9MISC:SPI_BUSWIDTH[1]
    10-
    11-
    12MISC:BPI_SYNC_MODE[0]
    13MISC:BPI_SYNC_MODE[1]
    14MISC:BPI_SYNC_MODE[2]
    15MISC:BPI_SYNC_MODE[3]
    16MISC:BPI_SYNC_MODE[4]
    17MISC:BPI_SYNC_MODE[5]
    18MISC:BPI_SYNC_MODE[6]
    19MISC:BPI_SYNC_MODE[7]
    20MISC:BPI_SYNC_MODE[8]
    21MISC:BPI_SYNC_MODE[9]
    22MISC:BPI_SYNC_MODE[10]
    23MISC:BPI_SYNC_MODE[11]
    24MISC:BPI_SYNC_MODE[12]
    25MISC:BPI_SYNC_MODE[13]
    26MISC:BPI_SYNC_MODE[14]
    27MISC:BPI_SYNC_MODE[15]
    +
    + + + +
    MISC:SPI_OPCODE[0, 0, 7][0, 0, 6][0, 0, 5][0, 0, 4][0, 0, 3][0, 0, 2][0, 0, 1][0, 0, 0]
    Non-inverted[7][6][5][4][3][2][1][0]
    +
    + + + + + +
    MISC:SPI_BUSWIDTH[0, 0, 9][0, 0, 8]
    100
    201
    410
    +
    + + + + + +
    MISC:BPI_SYNC_MODE[0, 0, 27][0, 0, 26][0, 0, 25][0, 0, 24][0, 0, 23][0, 0, 22][0, 0, 21][0, 0, 20][0, 0, 19][0, 0, 18][0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14][0, 0, 13][0, 0, 12]
    NONE0000000000000000
    TYPE21010100111001111
    TYPE11101100111001111
    +
    +
    +

    WBSTAR

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.WBSTAR bittile 0
    RowColumn
    0
    0MISC:NEXT_CONFIG_ADDR[0]
    1MISC:NEXT_CONFIG_ADDR[1]
    2MISC:NEXT_CONFIG_ADDR[2]
    3MISC:NEXT_CONFIG_ADDR[3]
    4MISC:NEXT_CONFIG_ADDR[4]
    5MISC:NEXT_CONFIG_ADDR[5]
    6MISC:NEXT_CONFIG_ADDR[6]
    7MISC:NEXT_CONFIG_ADDR[7]
    8MISC:NEXT_CONFIG_ADDR[8]
    9MISC:NEXT_CONFIG_ADDR[9]
    10MISC:NEXT_CONFIG_ADDR[10]
    11MISC:NEXT_CONFIG_ADDR[11]
    12MISC:NEXT_CONFIG_ADDR[12]
    13MISC:NEXT_CONFIG_ADDR[13]
    14MISC:NEXT_CONFIG_ADDR[14]
    15MISC:NEXT_CONFIG_ADDR[15]
    16MISC:NEXT_CONFIG_ADDR[16]
    17MISC:NEXT_CONFIG_ADDR[17]
    18MISC:NEXT_CONFIG_ADDR[18]
    19MISC:NEXT_CONFIG_ADDR[19]
    20MISC:NEXT_CONFIG_ADDR[20]
    21MISC:NEXT_CONFIG_ADDR[21]
    22MISC:NEXT_CONFIG_ADDR[22]
    23MISC:NEXT_CONFIG_ADDR[23]
    24MISC:NEXT_CONFIG_ADDR[24]
    25MISC:NEXT_CONFIG_ADDR[25]
    26MISC:NEXT_CONFIG_ADDR[26]
    27MISC:NEXT_CONFIG_ADDR[27]
    28MISC:NEXT_CONFIG_ADDR[28]
    29MISC:REVISION_SELECT_TRISTATE
    30MISC:REVISION_SELECT[0]
    31MISC:REVISION_SELECT[1]
    +
    + + + +
    MISC:NEXT_CONFIG_ADDR[0, 0, 28][0, 0, 27][0, 0, 26][0, 0, 25][0, 0, 24][0, 0, 23][0, 0, 22][0, 0, 21][0, 0, 20][0, 0, 19][0, 0, 18][0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14][0, 0, 13][0, 0, 12][0, 0, 11][0, 0, 10][0, 0, 9][0, 0, 8][0, 0, 7][0, 0, 6][0, 0, 5][0, 0, 4][0, 0, 3][0, 0, 2][0, 0, 1][0, 0, 0]
    Non-inverted[28][27][26][25][24][23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    +
    + + + +
    MISC:REVISION_SELECT_TRISTATE[0, 0, 29]
    Non-inverted[0]
    +
    + + + +
    MISC:REVISION_SELECT[0, 0, 31][0, 0, 30]
    Non-inverted[1][0]
    +
    +
    +

    TIMER

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.TIMER bittile 0
    RowColumn
    0
    0MISC:TIMER[0]
    1MISC:TIMER[1]
    2MISC:TIMER[2]
    3MISC:TIMER[3]
    4MISC:TIMER[4]
    5MISC:TIMER[5]
    6MISC:TIMER[6]
    7MISC:TIMER[7]
    8MISC:TIMER[8]
    9MISC:TIMER[9]
    10MISC:TIMER[10]
    11MISC:TIMER[11]
    12MISC:TIMER[12]
    13MISC:TIMER[13]
    14MISC:TIMER[14]
    15MISC:TIMER[15]
    16MISC:TIMER[16]
    17MISC:TIMER[17]
    18MISC:TIMER[18]
    19MISC:TIMER[19]
    20MISC:TIMER[20]
    21MISC:TIMER[21]
    22MISC:TIMER[22]
    23MISC:TIMER[23]
    24-
    25-
    26-
    27-
    28-
    29-
    30MISC:TIMER_CFG
    31MISC:TIMER_USR
    +
    + + + +
    MISC:TIMER[0, 0, 23][0, 0, 22][0, 0, 21][0, 0, 20][0, 0, 19][0, 0, 18][0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14][0, 0, 13][0, 0, 12][0, 0, 11][0, 0, 10][0, 0, 9][0, 0, 8][0, 0, 7][0, 0, 6][0, 0, 5][0, 0, 4][0, 0, 3][0, 0, 2][0, 0, 1][0, 0, 0]
    Non-inverted[23][22][21][20][19][18][17][16][15][14][13][12][11][10][9][8][7][6][5][4][3][2][1][0]
    +
    +
    + + + + +
    MISC:TIMER_CFG[0, 0, 30]
    MISC:TIMER_USR[0, 0, 31]
    Non-inverted[0]
    +
    +
    +

    TESTMODE

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.TESTMODE bittile 0
    RowColumn
    0
    0-
    1-
    2-
    3-
    4-
    5-
    6-
    7-
    8MISC:TEST_VGG_SEL[0]
    9MISC:TEST_VGG_SEL[1]
    10MISC:TEST_VGG_SEL[2]
    11MISC:TEST_VGG_SEL[3]
    12MISC:TEST_NEG_SLOPE_VGG
    13-
    14-
    15-
    16-
    17-
    18-
    19-
    20-
    21MISC:TEST_VGG_ENABLE
    22-
    23-
    24-
    25-
    26-
    27-
    28MISC:TEST_REF_SEL[0]
    29MISC:TEST_REF_SEL[1]
    30MISC:TEST_REF_SEL[2]
    +
    + + + +
    MISC:TEST_VGG_SEL[0, 0, 11][0, 0, 10][0, 0, 9][0, 0, 8]
    Non-inverted[3][2][1][0]
    +
    +
    + + + + +
    MISC:TEST_NEG_SLOPE_VGG[0, 0, 12]
    MISC:TEST_VGG_ENABLE[0, 0, 21]
    Non-inverted[0]
    +
    + + + +
    MISC:TEST_REF_SEL[0, 0, 30][0, 0, 29][0, 0, 28]
    Non-inverted[2][1][0]
    +
    +
    +

    TRIM0

    + + + + + + + + + + + + + + + + +
    REG.TRIM0 bittile 0
    RowColumn
    0
    0MISC:MPD_SEL[0]
    1MISC:MPD_SEL[1]
    2MISC:MPD_SEL[2]
    3MISC:MPD_OVERRIDE
    4MISC:MPD_DIS_OVERRIDE
    5MISC:TRIM_SPARE[0]
    6MISC:TRIM_SPARE[1]
    +
    + + + +
    MISC:MPD_SEL[0, 0, 2][0, 0, 1][0, 0, 0]
    Non-inverted[2][1][0]
    +
    +
    + + + + +
    MISC:MPD_DIS_OVERRIDE[0, 0, 4]
    MISC:MPD_OVERRIDE[0, 0, 3]
    Non-inverted[0]
    +
    + + + +
    MISC:TRIM_SPARE[0, 0, 6][0, 0, 5]
    Non-inverted[1][0]
    +
    +
    +

    TRIM1

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.TRIM1 bittile 0
    RowColumn
    0
    0-
    1-
    2-
    3-
    4-
    5-
    6-
    7-
    8-
    9-
    10-
    11-
    12-
    13-
    14MISC:VBG_FLAT_SEL[0]
    15MISC:VBG_FLAT_SEL[1]
    16MISC:VBG_FLAT_SEL[2]
    17MISC:VBG_FLAT_SEL[3]
    18MISC:VBG_FLAT_SEL[4]
    19MISC:VBG_FLAT_SEL[5]
    20MISC:VGGSEL[0]
    21MISC:VGGSEL[1]
    22MISC:VGGSEL[2]
    23MISC:VGGSEL[3]
    24MISC:VGGSEL[4]
    25MISC:VGGSEL[5]
    26MISC:VGGSEL2[0]
    27MISC:VGGSEL2[1]
    28MISC:VGGSEL2[2]
    29MISC:VGGSEL2[3]
    30MISC:VGGSEL2[4]
    31MISC:VGGSEL2[5]
    +
    +
    +
    + + + + + +
    MISC:VBG_FLAT_SEL[0, 0, 19][0, 0, 18][0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14]
    MISC:VGGSEL[0, 0, 25][0, 0, 24][0, 0, 23][0, 0, 22][0, 0, 21][0, 0, 20]
    MISC:VGGSEL2[0, 0, 31][0, 0, 30][0, 0, 29][0, 0, 28][0, 0, 27][0, 0, 26]
    Non-inverted[5][4][3][2][1][0]
    +
    +
    +

    TRIM2

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    REG.TRIM2 bittile 0
    RowColumn
    0
    0MISC:VGG_TRIM_TOP[0]
    1MISC:VGG_TRIM_TOP[1]
    2MISC:VGG_TRIM_TOP[2]
    3MISC:VGG_TRIM_TOP[3]
    4MISC:VGG_TRIM_TOP[4]
    5MISC:VGG_TRIM_TOP[5]
    6MISC:VGG_TRIM_TOP[6]
    7MISC:VGG_TRIM_TOP[7]
    8MISC:VGG_TRIM_TOP[8]
    9MISC:VGG_TRIM_TOP[9]
    10MISC:VGG_TRIM_TOP[10]
    11MISC:VGG_TRIM_TOP[11]
    12MISC:VGG_TRIM_BOT[0]
    13MISC:VGG_TRIM_BOT[1]
    14MISC:VGG_TRIM_BOT[2]
    15MISC:VGG_TRIM_BOT[3]
    16MISC:VGG_TRIM_BOT[4]
    17MISC:VGG_TRIM_BOT[5]
    18MISC:VGG_TRIM_BOT[6]
    19MISC:VGG_TRIM_BOT[7]
    20MISC:VGG_TRIM_BOT[8]
    21MISC:VGG_TRIM_BOT[9]
    22MISC:VGG_TRIM_BOT[10]
    23MISC:VGG_TRIM_BOT[11]
    +
    +
    + + + + +
    MISC:VGG_TRIM_BOT[0, 0, 23][0, 0, 22][0, 0, 21][0, 0, 20][0, 0, 19][0, 0, 18][0, 0, 17][0, 0, 16][0, 0, 15][0, 0, 14][0, 0, 13][0, 0, 12]
    MISC:VGG_TRIM_TOP[0, 0, 11][0, 0, 10][0, 0, 9][0, 0, 8][0, 0, 7][0, 0, 6][0, 0, 5][0, 0, 4][0, 0, 3][0, 0, 2][0, 0, 1][0, 0, 0]
    Non-inverted[11][10][9][8][7][6][5][4][3][2][1][0]
    +
    +
    + + +
    +
    + +
    +
    +
    +
    + + + + \ No newline at end of file diff --git a/xilinx/virtex7/dsp.html b/xilinx/virtex7/dsp.html index 4c722919..867c6295 100644 --- a/xilinx/virtex7/dsp.html +++ b/xilinx/virtex7/dsp.html @@ -67,10 +67,12 @@
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • diff --git a/xilinx/virtex7/geometry.html b/xilinx/virtex7/geometry.html index 85e26d2e..90009fd9 100644 --- a/xilinx/virtex7/geometry.html +++ b/xilinx/virtex7/geometry.html @@ -68,10 +68,12 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • diff --git a/xilinx/virtex7/index.html b/xilinx/virtex7/index.html index b8a1ce9a..ec8b10dc 100644 --- a/xilinx/virtex7/index.html +++ b/xilinx/virtex7/index.html @@ -64,10 +64,12 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • @@ -135,6 +137,13 @@

    Virtex 7
  • Input/Output +
    • +
  • Configuration Center
  • Clock interconnect diff --git a/xilinx/virtex7/interconnect.html b/xilinx/virtex7/interconnect.html index 7fc94610..184689d0 100644 --- a/xilinx/virtex7/interconnect.html +++ b/xilinx/virtex7/interconnect.html @@ -70,10 +70,12 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • @@ -269,21 +271,21 @@

    Bitstream
    @@ -291,22 +293,22 @@

    Bitstream
    diff --git a/xilinx/virtex7/io.html b/xilinx/virtex7/io.html index 00cdd671..1672b1e7 100644 --- a/xilinx/virtex7/io.html +++ b/xilinx/virtex7/io.html @@ -19,7 +19,7 @@ - + @@ -65,12 +65,16 @@
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • @@ -278,6 +282,498 @@

    I/O banks and special functionsTCK, TDI, TDO, TMS

    +
    +

    Bitstream — HCLK_IOI_HP

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    HCLK_IOI_HP bittile 0
    RowColumn
    012345678910111213141516171819202122232425262728293031323334353637
    0--------------------------------------
    1--------------------------------------
    2--------------------------------------
    3--------------------------------------
    4--------------------------------------
    5--------------------------------------
    6--------------------------------------
    7--------------------------------------
    8--------------------------------------
    9--------------------------------------
    10--------------------------------------
    11--------------------------------------
    12--------------------------------------
    13--------------------------------------
    14--------------------------HCLK_IOI:MUX.HCLK_IO_D3[6]HCLK_IOI:MUX.HCLK_IO_U3[5]HCLK_IOI:ENABLE.HCLK8HCLK_IOI:ENABLE.HCLK1HCLK_IOI:MUX.HCLK_IO_U5[2]HCLK_IOI:MUX.HCLK_IO_D5[2]HCLK_IOI:MUX.HCLK_IO_U4[6]BUFR3:BUFR_DIVIDE[0]--HCLK_IOI:ENABLE.PERF2HCLK_IOI:ENABLE.PERF3
    15--------------------------HCLK_IOI:MUX.HCLK_IO_U3[4]HCLK_IOI:MUX.HCLK_IO_D3[5]HCLK_IOI:ENABLE.HCLK0HCLK_IOI:ENABLE.HCLK9HCLK_IOI:MUX.HCLK_IO_D5[3]HCLK_IOI:MUX.HCLK_IO_U5[1]HCLK_IOI:MUX.HCLK_IO_U4[5]BUFR3:BUFR_DIVIDE[3]BUFR2:MUX.I[2]BUFR3:MUX.I[7]--
    16--------------------------HCLK_IOI:MUX.HCLK_IO_D3[4]HCLK_IOI:MUX.HCLK_IO_U3[6]-HCLK_IOI:ENABLE.HCLK2HCLK_IOI:MUX.HCLK_IO_U5[3]HCLK_IOI:MUX.HCLK_IO_D5[1]BUFR3:MUX.I[0]BUFR3:BUFR_DIVIDE[2]BUFR2:MUX.I[3]BUFR3:MUX.I[6]~BUFIO2:DELAY_BYPASS~BUFIO3:DELAY_BYPASS
    17--------------------------HCLK_IOI:MUX.HCLK_IO_U0[6]HCLK_IOI:MUX.HCLK_IO_D1[0]HCLK_IOI:BUF.RCLK3HCLK_IOI:ENABLE.HCLK10HCLK_IOI:MUX.HCLK_IO_U5[4]HCLK_IOI:MUX.HCLK_IO_U5[0]-BUFR3:BUFR_DIVIDE[1]BUFR2:MUX.I[4]BUFR3:MUX.I[5]BUFIO2:MUX.IBUFIO3:MUX.I
    18--------------------------HCLK_IOI:MUX.HCLK_IO_U0[5]HCLK_IOI:MUX.HCLK_IO_U1[0]HCLK_IOI:MUX.HCLK_IO_D0[5]HCLK_IOI:ENABLE.HCLK3HCLK_IOI:MUX.HCLK_IO_U5[5]HCLK_IOI:MUX.HCLK_IO_D5[0]-BUFR2:BUFR_DIVIDE[0]BUFR2:MUX.I[5]BUFR3:MUX.I[4]BUFIO2:ENABLEBUFIO3:ENABLE
    19--------------------------HCLK_IOI:MUX.HCLK_IO_U0[4]HCLK_IOI:MUX.HCLK_IO_D0[1]HCLK_IOI:MUX.HCLK_IO_D1[6]HCLK_IOI:ENABLE.HCLK11HCLK_IOI:MUX.HCLK_IO_U5[6]HCLK_IOI:BUF.RCLK2BUFR3:ENABLEBUFR2:BUFR_DIVIDE[3]BUFR2:MUX.I[6]BUFR3:MUX.I[3]--
    20--------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:MUX.HCLK_IO_D1[1]HCLK_IOI:MUX.HCLK_IO_D4[6]HCLK_IOI:MUX.HCLK_IO_U3[2]HCLK_IOI:MUX.HCLK_IO_U2[6]BUFR3:MUX.I[2]BUFR2:ENABLEBUFR2:BUFR_DIVIDE[2]BUFR2:MUX.I[7]-HCLK_IOI:ENABLE.PERF1-
    21--------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:MUX.HCLK_IO_U0[1]HCLK_IOI:MUX.HCLK_IO_U4[3]HCLK_IOI:MUX.HCLK_IO_D3[3]HCLK_IOI:MUX.HCLK_IO_U2[5]HCLK_IOI:MUX.HCLK_IO_D5[6]-BUFR2:BUFR_DIVIDE[1]-BUFR3:MUX.I[1]~BUFIO1:DELAY_BYPASSBUFIO1:MUX.I
    22--------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:MUX.HCLK_IO_U1[1]HCLK_IOI:MUX.HCLK_IO_D4[3]HCLK_IOI:MUX.HCLK_IO_U3[3]HCLK_IOI:MUX.HCLK_IO_U2[4]HCLK_IOI:MUX.HCLK_IO_D5[5]-----BUFIO1:ENABLE
    23--------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:MUX.HCLK_IO_D0[2]HCLK_IOI:MUX.HCLK_IO_U4[2]HCLK_IOI:ENABLE.HCLK4HCLK_IOI:MUX.HCLK_IO_U2[3]HCLK_IOI:MUX.HCLK_IO_D5[4]HCLK_IOI:MUX.HCLK_IO_U4[4]BUFR1:BUFR_DIVIDE[0]BUFR1:MUX.I[2]BUFR0:MUX.I[0]--
    24--------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:MUX.HCLK_IO_D1[2]HCLK_IOI:MUX.HCLK_IO_D3[2]HCLK_IOI:MUX.HCLK_IO_D0[4]HCLK_IOI:MUX.HCLK_IO_D2[3]HCLK_IOI:MUX.HCLK_IO_D2[5]HCLK_IOI:MUX.HCLK_IO_U1[4]BUFR1:BUFR_DIVIDE[3]BUFR1:MUX.I[3]BUFR0:MUX.I[1]BUFR2:MUX.I[0]-
    25--------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:MUX.HCLK_IO_U0[2]HCLK_IOI:MUX.HCLK_IO_D4[2]HCLK_IOI:MUX.HCLK_IO_D0[6]HCLK_IOI:MUX.HCLK_IO_U2[2]HCLK_IOI:MUX.HCLK_IO_D2[4]HCLK_IOI:MUX.HCLK_IO_D1[4]BUFR1:BUFR_DIVIDE[2]BUFR1:MUX.I[4]BUFR0:MUX.I[3]BUFR2:MUX.I[1]-
    26--------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.HCLK_IO_U1[2]HCLK_IOI:MUX.HCLK_IO_U3[1]HCLK_IOI:MUX.HCLK_IO_U0[3]HCLK_IOI:MUX.HCLK_IO_D2[2]HCLK_IOI:MUX.HCLK_IO_D2[6]BUFR1:ENABLEBUFR1:BUFR_DIVIDE[1]BUFR1:MUX.I[5]BUFR0:MUX.I[4]BUFR1:MUX.I[0]-
    27--------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.HCLK_IO_D0[3]HCLK_IOI:MUX.HCLK_IO_U4[1]HCLK_IOI:ENABLE.HCLK5HCLK_IOI:MUX.HCLK_IO_U2[1]HCLK_IOI:MUX.HCLK_IO_D4[4]-BUFR0:BUFR_DIVIDE[0]-BUFR0:MUX.I[5]BUFR1:MUX.I[1]-
    28--------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.HCLK_IO_D1[3]HCLK_IOI:MUX.HCLK_IO_D3[1]HCLK_IOI:MUX.HCLK_IO_U0[0]HCLK_IOI:MUX.HCLK_IO_D2[1]HCLK_IOI:MUX.HCLK_IO_U1[6]-BUFR0:BUFR_DIVIDE[3]-BUFR0:MUX.I[6]HCLK_IOI:ENABLE.PERF0-
    29--------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.HCLK_IO_U1[3]HCLK_IOI:MUX.HCLK_IO_D4[1]HCLK_IOI:MUX.HCLK_IO_D0[0]HCLK_IOI:MUX.HCLK_IO_U2[0]HCLK_IOI:MUX.HCLK_IO_D1[5]HCLK_IOI:BUF.RCLK0BUFR0:BUFR_DIVIDE[2]BUFR1:MUX.I[7]BUFR0:MUX.I[7]BUFIO0:MUX.I-
    30--------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.HCLK_IO_D4[0]HCLK_IOI:MUX.HCLK_IO_U3[0]HCLK_IOI:ENABLE.HCLK6HCLK_IOI:MUX.HCLK_IO_D2[0]HCLK_IOI:MUX.HCLK_IO_D4[5]BUFR0:ENABLEBUFR0:BUFR_DIVIDE[1]BUFR1:MUX.I[6]---
    31--------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.HCLK_IO_D3[0]HCLK_IOI:MUX.HCLK_IO_U4[0]HCLK_IOI:ENABLE.HCLK7HCLK_IOI:BUF.RCLK1HCLK_IOI:MUX.HCLK_IO_U1[5]--BUFR0:MUX.I[2]-~BUFIO0:DELAY_BYPASSBUFIO0:ENABLE
    +
    + + + + + + + + + + + + + + + +
    IDELAYCTRL:MUX.REFCLK[0, 26, 31][0, 26, 30][0, 26, 29][0, 26, 28][0, 26, 27][0, 26, 26][0, 26, 25][0, 26, 24][0, 26, 23][0, 26, 22][0, 26, 21][0, 26, 20]
    NONE000000000000
    HCLK_IO_D0000000000001
    HCLK_IO_D1000000000010
    HCLK_IO_D2000000000100
    HCLK_IO_D3000000001000
    HCLK_IO_D4000000010000
    HCLK_IO_D5000000100000
    HCLK_IO_U0000001000000
    HCLK_IO_U1000010000000
    HCLK_IO_U2000100000000
    HCLK_IO_U3001000000000
    HCLK_IO_U4010000000000
    HCLK_IO_U5100000000000
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    HCLK_IOI:MUX.HCLK_IO_D0[0, 29, 25][0, 28, 18][0, 29, 24][0, 27, 27][0, 27, 23][0, 27, 19][0, 29, 29]
    HCLK_IOI:MUX.HCLK_IO_D1[0, 28, 19][0, 31, 29][0, 32, 25][0, 27, 28][0, 27, 24][0, 27, 20][0, 27, 17]
    HCLK_IOI:MUX.HCLK_IO_D2[0, 31, 26][0, 31, 24][0, 31, 25][0, 30, 24][0, 30, 26][0, 30, 28][0, 30, 30]
    HCLK_IOI:MUX.HCLK_IO_D3[0, 26, 14][0, 27, 15][0, 26, 16][0, 29, 21][0, 28, 24][0, 28, 28][0, 27, 31]
    HCLK_IOI:MUX.HCLK_IO_D4[0, 28, 20][0, 31, 30][0, 31, 27][0, 28, 22][0, 28, 25][0, 28, 29][0, 27, 30]
    HCLK_IOI:MUX.HCLK_IO_D5[0, 31, 21][0, 31, 22][0, 31, 23][0, 30, 15][0, 31, 14][0, 31, 16][0, 31, 18]
    HCLK_IOI:MUX.HCLK_IO_U0[0, 26, 17][0, 26, 18][0, 26, 19][0, 29, 26][0, 27, 25][0, 27, 21][0, 29, 28]
    HCLK_IOI:MUX.HCLK_IO_U1[0, 31, 28][0, 31, 31][0, 32, 24][0, 27, 29][0, 27, 26][0, 27, 22][0, 27, 18]
    HCLK_IOI:MUX.HCLK_IO_U2[0, 30, 20][0, 30, 21][0, 30, 22][0, 30, 23][0, 30, 25][0, 30, 27][0, 30, 29]
    HCLK_IOI:MUX.HCLK_IO_U3[0, 27, 16][0, 27, 14][0, 26, 15][0, 29, 22][0, 29, 20][0, 28, 26][0, 28, 30]
    HCLK_IOI:MUX.HCLK_IO_U4[0, 32, 14][0, 32, 15][0, 32, 23][0, 28, 21][0, 28, 23][0, 28, 27][0, 28, 31]
    HCLK_IOI:MUX.HCLK_IO_U5[0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 30, 14][0, 31, 15][0, 31, 17]
    NONE0000000
    HCLK00010001
    HCLK10010010
    HCLK20010100
    HCLK30011000
    HCLK40100001
    HCLK50100010
    HCLK60100100
    HCLK70101000
    HCLK81000001
    HCLK91000010
    HCLK101000100
    HCLK111001000
    +
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    +
    +
    +
    +
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    +
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    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFIO0:ENABLE[0, 37, 31]
    BUFIO1:ENABLE[0, 37, 22]
    BUFIO2:ENABLE[0, 36, 18]
    BUFIO3:ENABLE[0, 37, 18]
    BUFR0:ENABLE[0, 32, 30]
    BUFR1:ENABLE[0, 32, 26]
    BUFR2:ENABLE[0, 32, 20]
    BUFR3:ENABLE[0, 32, 19]
    HCLK_IOI:BUF.RCLK0[0, 32, 29]
    HCLK_IOI:BUF.RCLK1[0, 30, 31]
    HCLK_IOI:BUF.RCLK2[0, 31, 19]
    HCLK_IOI:BUF.RCLK3[0, 28, 17]
    HCLK_IOI:ENABLE.HCLK0[0, 28, 15]
    HCLK_IOI:ENABLE.HCLK1[0, 29, 14]
    HCLK_IOI:ENABLE.HCLK10[0, 29, 17]
    HCLK_IOI:ENABLE.HCLK11[0, 29, 19]
    HCLK_IOI:ENABLE.HCLK2[0, 29, 16]
    HCLK_IOI:ENABLE.HCLK3[0, 29, 18]
    HCLK_IOI:ENABLE.HCLK4[0, 29, 23]
    HCLK_IOI:ENABLE.HCLK5[0, 29, 27]
    HCLK_IOI:ENABLE.HCLK6[0, 29, 30]
    HCLK_IOI:ENABLE.HCLK7[0, 29, 31]
    HCLK_IOI:ENABLE.HCLK8[0, 28, 14]
    HCLK_IOI:ENABLE.HCLK9[0, 29, 15]
    HCLK_IOI:ENABLE.PERF0[0, 36, 28]
    HCLK_IOI:ENABLE.PERF1[0, 36, 20]
    HCLK_IOI:ENABLE.PERF2[0, 36, 14]
    HCLK_IOI:ENABLE.PERF3[0, 37, 14]
    Non-inverted[0]
    +
    +
    +
    +
    + + + + + + + + + + + + + + +
    BUFR0:MUX.I[0, 35, 29][0, 35, 28][0, 35, 27][0, 35, 26][0, 35, 25][0, 34, 31][0, 35, 24][0, 35, 23]
    BUFR1:MUX.I[0, 34, 29][0, 34, 30][0, 34, 26][0, 34, 25][0, 34, 24][0, 34, 23][0, 36, 27][0, 36, 26]
    BUFR2:MUX.I[0, 34, 20][0, 34, 19][0, 34, 18][0, 34, 17][0, 34, 16][0, 34, 15][0, 36, 25][0, 36, 24]
    BUFR3:MUX.I[0, 35, 15][0, 35, 16][0, 35, 17][0, 35, 18][0, 35, 19][0, 31, 20][0, 35, 21][0, 32, 16]
    NONE00000000
    BUFIO0_I00000001
    BUFIO1_I00000010
    BUFIO2_I00000100
    BUFIO3_I00001000
    CKINT000010000
    CKINT100100000
    CKINT201000000
    CKINT310000000
    +
    +
    +
    +
    + + + + + + + + + + + + + + +
    BUFR0:BUFR_DIVIDE[0, 33, 28][0, 33, 29][0, 33, 30][0, 33, 27]
    BUFR1:BUFR_DIVIDE[0, 33, 24][0, 33, 25][0, 33, 26][0, 33, 23]
    BUFR2:BUFR_DIVIDE[0, 33, 19][0, 33, 20][0, 33, 21][0, 33, 18]
    BUFR3:BUFR_DIVIDE[0, 33, 15][0, 33, 16][0, 33, 17][0, 33, 14]
    BYPASS0000
    10001
    20011
    30101
    40111
    51001
    61011
    71101
    81111
    +
    +
    +
    +
    + + + + + + +
    BUFIO0:DELAY_BYPASS[0, 36, 31]
    BUFIO1:DELAY_BYPASS[0, 36, 21]
    BUFIO2:DELAY_BYPASS[0, 36, 16]
    BUFIO3:DELAY_BYPASS[0, 37, 16]
    Inverted~[0]
    +
    +
    +
    +
    + + + + + + + +
    BUFIO0:MUX.I[0, 36, 29]
    BUFIO1:MUX.I[0, 37, 21]
    BUFIO2:MUX.I[0, 36, 17]
    BUFIO3:MUX.I[0, 37, 17]
    CCIO0
    PERF1
    +
    +
    +

    Bitstream — HCLK_IOI_HR

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    HCLK_IOI_HR bittile 0
    RowColumn
    012345678910111213141516171819202122232425262728293031323334353637
    0--------------------------------------
    1--------------------------------------
    2--------------------------------------
    3--------------------------------------
    4--------------------------------------
    5--------------------------------------
    6--------------------------------------
    7--------------------------------------
    8--------------------------------------
    9--------------------------------------
    10--------------------------------------
    11--------------------------------------
    12--------------------------------------
    13--------------------------------------
    14--------------------------HCLK_IOI:MUX.HCLK_IO_D3[6]HCLK_IOI:MUX.HCLK_IO_U3[5]HCLK_IOI:ENABLE.HCLK8HCLK_IOI:ENABLE.HCLK1HCLK_IOI:MUX.HCLK_IO_U5[2]HCLK_IOI:MUX.HCLK_IO_D5[2]HCLK_IOI:MUX.HCLK_IO_U4[6]BUFR3:BUFR_DIVIDE[0]--HCLK_IOI:ENABLE.PERF2HCLK_IOI:ENABLE.PERF3
    15--------------------------HCLK_IOI:MUX.HCLK_IO_U3[4]HCLK_IOI:MUX.HCLK_IO_D3[5]HCLK_IOI:ENABLE.HCLK0HCLK_IOI:ENABLE.HCLK9HCLK_IOI:MUX.HCLK_IO_D5[3]HCLK_IOI:MUX.HCLK_IO_U5[1]HCLK_IOI:MUX.HCLK_IO_U4[5]BUFR3:BUFR_DIVIDE[3]BUFR2:MUX.I[2]BUFR3:MUX.I[7]--
    16--------------------------HCLK_IOI:MUX.HCLK_IO_D3[4]HCLK_IOI:MUX.HCLK_IO_U3[6]-HCLK_IOI:ENABLE.HCLK2HCLK_IOI:MUX.HCLK_IO_U5[3]HCLK_IOI:MUX.HCLK_IO_D5[1]BUFR3:MUX.I[0]BUFR3:BUFR_DIVIDE[2]BUFR2:MUX.I[3]BUFR3:MUX.I[6]~BUFIO2:DELAY_BYPASS~BUFIO3:DELAY_BYPASS
    17--------------------------HCLK_IOI:MUX.HCLK_IO_U0[6]HCLK_IOI:MUX.HCLK_IO_D1[0]HCLK_IOI:BUF.RCLK3HCLK_IOI:ENABLE.HCLK10HCLK_IOI:MUX.HCLK_IO_U5[4]HCLK_IOI:MUX.HCLK_IO_U5[0]-BUFR3:BUFR_DIVIDE[1]BUFR2:MUX.I[4]BUFR3:MUX.I[5]BUFIO2:MUX.IBUFIO3:MUX.I
    18--------------------------HCLK_IOI:MUX.HCLK_IO_U0[5]HCLK_IOI:MUX.HCLK_IO_U1[0]HCLK_IOI:MUX.HCLK_IO_D0[5]HCLK_IOI:ENABLE.HCLK3HCLK_IOI:MUX.HCLK_IO_U5[5]HCLK_IOI:MUX.HCLK_IO_D5[0]-BUFR2:BUFR_DIVIDE[0]BUFR2:MUX.I[5]BUFR3:MUX.I[4]BUFIO2:ENABLEBUFIO3:ENABLE
    19--------------------------HCLK_IOI:MUX.HCLK_IO_U0[4]HCLK_IOI:MUX.HCLK_IO_D0[1]HCLK_IOI:MUX.HCLK_IO_D1[6]HCLK_IOI:ENABLE.HCLK11HCLK_IOI:MUX.HCLK_IO_U5[6]HCLK_IOI:BUF.RCLK2BUFR3:ENABLEBUFR2:BUFR_DIVIDE[3]BUFR2:MUX.I[6]BUFR3:MUX.I[3]--
    20--------------------------IDELAYCTRL:MUX.REFCLK[0]HCLK_IOI:MUX.HCLK_IO_D1[1]HCLK_IOI:MUX.HCLK_IO_D4[6]HCLK_IOI:MUX.HCLK_IO_U3[2]HCLK_IOI:MUX.HCLK_IO_U2[6]BUFR3:MUX.I[2]BUFR2:ENABLEBUFR2:BUFR_DIVIDE[2]BUFR2:MUX.I[7]-HCLK_IOI:ENABLE.PERF1-
    21--------------------------IDELAYCTRL:MUX.REFCLK[1]HCLK_IOI:MUX.HCLK_IO_U0[1]HCLK_IOI:MUX.HCLK_IO_U4[3]HCLK_IOI:MUX.HCLK_IO_D3[3]HCLK_IOI:MUX.HCLK_IO_U2[5]HCLK_IOI:MUX.HCLK_IO_D5[6]-BUFR2:BUFR_DIVIDE[1]-BUFR3:MUX.I[1]~BUFIO1:DELAY_BYPASSBUFIO1:MUX.I
    22--------------------------IDELAYCTRL:MUX.REFCLK[2]HCLK_IOI:MUX.HCLK_IO_U1[1]HCLK_IOI:MUX.HCLK_IO_D4[3]HCLK_IOI:MUX.HCLK_IO_U3[3]HCLK_IOI:MUX.HCLK_IO_U2[4]HCLK_IOI:MUX.HCLK_IO_D5[5]-----BUFIO1:ENABLE
    23--------------------------IDELAYCTRL:MUX.REFCLK[3]HCLK_IOI:MUX.HCLK_IO_D0[2]HCLK_IOI:MUX.HCLK_IO_U4[2]HCLK_IOI:ENABLE.HCLK4HCLK_IOI:MUX.HCLK_IO_U2[3]HCLK_IOI:MUX.HCLK_IO_D5[4]HCLK_IOI:MUX.HCLK_IO_U4[4]BUFR1:BUFR_DIVIDE[0]BUFR1:MUX.I[2]BUFR0:MUX.I[0]--
    24--------------------------IDELAYCTRL:MUX.REFCLK[4]HCLK_IOI:MUX.HCLK_IO_D1[2]HCLK_IOI:MUX.HCLK_IO_D3[2]HCLK_IOI:MUX.HCLK_IO_D0[4]HCLK_IOI:MUX.HCLK_IO_D2[3]HCLK_IOI:MUX.HCLK_IO_D2[5]HCLK_IOI:MUX.HCLK_IO_U1[4]BUFR1:BUFR_DIVIDE[3]BUFR1:MUX.I[3]BUFR0:MUX.I[1]BUFR2:MUX.I[0]-
    25--------------------------IDELAYCTRL:MUX.REFCLK[5]HCLK_IOI:MUX.HCLK_IO_U0[2]HCLK_IOI:MUX.HCLK_IO_D4[2]HCLK_IOI:MUX.HCLK_IO_D0[6]HCLK_IOI:MUX.HCLK_IO_U2[2]HCLK_IOI:MUX.HCLK_IO_D2[4]HCLK_IOI:MUX.HCLK_IO_D1[4]BUFR1:BUFR_DIVIDE[2]BUFR1:MUX.I[4]BUFR0:MUX.I[3]BUFR2:MUX.I[1]-
    26--------------------------IDELAYCTRL:MUX.REFCLK[6]HCLK_IOI:MUX.HCLK_IO_U1[2]HCLK_IOI:MUX.HCLK_IO_U3[1]HCLK_IOI:MUX.HCLK_IO_U0[3]HCLK_IOI:MUX.HCLK_IO_D2[2]HCLK_IOI:MUX.HCLK_IO_D2[6]BUFR1:ENABLEBUFR1:BUFR_DIVIDE[1]BUFR1:MUX.I[5]BUFR0:MUX.I[4]BUFR1:MUX.I[0]-
    27--------------------------IDELAYCTRL:MUX.REFCLK[7]HCLK_IOI:MUX.HCLK_IO_D0[3]HCLK_IOI:MUX.HCLK_IO_U4[1]HCLK_IOI:ENABLE.HCLK5HCLK_IOI:MUX.HCLK_IO_U2[1]HCLK_IOI:MUX.HCLK_IO_D4[4]-BUFR0:BUFR_DIVIDE[0]-BUFR0:MUX.I[5]BUFR1:MUX.I[1]-
    28--------------------------IDELAYCTRL:MUX.REFCLK[8]HCLK_IOI:MUX.HCLK_IO_D1[3]HCLK_IOI:MUX.HCLK_IO_D3[1]HCLK_IOI:MUX.HCLK_IO_U0[0]HCLK_IOI:MUX.HCLK_IO_D2[1]HCLK_IOI:MUX.HCLK_IO_U1[6]-BUFR0:BUFR_DIVIDE[3]-BUFR0:MUX.I[6]HCLK_IOI:ENABLE.PERF0-
    29--------------------------IDELAYCTRL:MUX.REFCLK[9]HCLK_IOI:MUX.HCLK_IO_U1[3]HCLK_IOI:MUX.HCLK_IO_D4[1]HCLK_IOI:MUX.HCLK_IO_D0[0]HCLK_IOI:MUX.HCLK_IO_U2[0]HCLK_IOI:MUX.HCLK_IO_D1[5]HCLK_IOI:BUF.RCLK0BUFR0:BUFR_DIVIDE[2]BUFR1:MUX.I[7]BUFR0:MUX.I[7]BUFIO0:MUX.I-
    30--------------------------IDELAYCTRL:MUX.REFCLK[10]HCLK_IOI:MUX.HCLK_IO_D4[0]HCLK_IOI:MUX.HCLK_IO_U3[0]HCLK_IOI:ENABLE.HCLK6HCLK_IOI:MUX.HCLK_IO_D2[0]HCLK_IOI:MUX.HCLK_IO_D4[5]BUFR0:ENABLEBUFR0:BUFR_DIVIDE[1]BUFR1:MUX.I[6]---
    31--------------------------IDELAYCTRL:MUX.REFCLK[11]HCLK_IOI:MUX.HCLK_IO_D3[0]HCLK_IOI:MUX.HCLK_IO_U4[0]HCLK_IOI:ENABLE.HCLK7HCLK_IOI:BUF.RCLK1HCLK_IOI:MUX.HCLK_IO_U1[5]--BUFR0:MUX.I[2]-~BUFIO0:DELAY_BYPASSBUFIO0:ENABLE
    +
    + + + + + + + + + + + + + + + +
    IDELAYCTRL:MUX.REFCLK[0, 26, 31][0, 26, 30][0, 26, 29][0, 26, 28][0, 26, 27][0, 26, 26][0, 26, 25][0, 26, 24][0, 26, 23][0, 26, 22][0, 26, 21][0, 26, 20]
    NONE000000000000
    HCLK_IO_D0000000000001
    HCLK_IO_D1000000000010
    HCLK_IO_D2000000000100
    HCLK_IO_D3000000001000
    HCLK_IO_D4000000010000
    HCLK_IO_D5000000100000
    HCLK_IO_U0000001000000
    HCLK_IO_U1000010000000
    HCLK_IO_U2000100000000
    HCLK_IO_U3001000000000
    HCLK_IO_U4010000000000
    HCLK_IO_U5100000000000
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    HCLK_IOI:MUX.HCLK_IO_D0[0, 29, 25][0, 28, 18][0, 29, 24][0, 27, 27][0, 27, 23][0, 27, 19][0, 29, 29]
    HCLK_IOI:MUX.HCLK_IO_D1[0, 28, 19][0, 31, 29][0, 32, 25][0, 27, 28][0, 27, 24][0, 27, 20][0, 27, 17]
    HCLK_IOI:MUX.HCLK_IO_D2[0, 31, 26][0, 31, 24][0, 31, 25][0, 30, 24][0, 30, 26][0, 30, 28][0, 30, 30]
    HCLK_IOI:MUX.HCLK_IO_D3[0, 26, 14][0, 27, 15][0, 26, 16][0, 29, 21][0, 28, 24][0, 28, 28][0, 27, 31]
    HCLK_IOI:MUX.HCLK_IO_D4[0, 28, 20][0, 31, 30][0, 31, 27][0, 28, 22][0, 28, 25][0, 28, 29][0, 27, 30]
    HCLK_IOI:MUX.HCLK_IO_D5[0, 31, 21][0, 31, 22][0, 31, 23][0, 30, 15][0, 31, 14][0, 31, 16][0, 31, 18]
    HCLK_IOI:MUX.HCLK_IO_U0[0, 26, 17][0, 26, 18][0, 26, 19][0, 29, 26][0, 27, 25][0, 27, 21][0, 29, 28]
    HCLK_IOI:MUX.HCLK_IO_U1[0, 31, 28][0, 31, 31][0, 32, 24][0, 27, 29][0, 27, 26][0, 27, 22][0, 27, 18]
    HCLK_IOI:MUX.HCLK_IO_U2[0, 30, 20][0, 30, 21][0, 30, 22][0, 30, 23][0, 30, 25][0, 30, 27][0, 30, 29]
    HCLK_IOI:MUX.HCLK_IO_U3[0, 27, 16][0, 27, 14][0, 26, 15][0, 29, 22][0, 29, 20][0, 28, 26][0, 28, 30]
    HCLK_IOI:MUX.HCLK_IO_U4[0, 32, 14][0, 32, 15][0, 32, 23][0, 28, 21][0, 28, 23][0, 28, 27][0, 28, 31]
    HCLK_IOI:MUX.HCLK_IO_U5[0, 30, 19][0, 30, 18][0, 30, 17][0, 30, 16][0, 30, 14][0, 31, 15][0, 31, 17]
    NONE0000000
    HCLK00010001
    HCLK10010010
    HCLK20010100
    HCLK30011000
    HCLK40100001
    HCLK50100010
    HCLK60100100
    HCLK70101000
    HCLK81000001
    HCLK91000010
    HCLK101000100
    HCLK111001000
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    BUFIO0:ENABLE[0, 37, 31]
    BUFIO1:ENABLE[0, 37, 22]
    BUFIO2:ENABLE[0, 36, 18]
    BUFIO3:ENABLE[0, 37, 18]
    BUFR0:ENABLE[0, 32, 30]
    BUFR1:ENABLE[0, 32, 26]
    BUFR2:ENABLE[0, 32, 20]
    BUFR3:ENABLE[0, 32, 19]
    HCLK_IOI:BUF.RCLK0[0, 32, 29]
    HCLK_IOI:BUF.RCLK1[0, 30, 31]
    HCLK_IOI:BUF.RCLK2[0, 31, 19]
    HCLK_IOI:BUF.RCLK3[0, 28, 17]
    HCLK_IOI:ENABLE.HCLK0[0, 28, 15]
    HCLK_IOI:ENABLE.HCLK1[0, 29, 14]
    HCLK_IOI:ENABLE.HCLK10[0, 29, 17]
    HCLK_IOI:ENABLE.HCLK11[0, 29, 19]
    HCLK_IOI:ENABLE.HCLK2[0, 29, 16]
    HCLK_IOI:ENABLE.HCLK3[0, 29, 18]
    HCLK_IOI:ENABLE.HCLK4[0, 29, 23]
    HCLK_IOI:ENABLE.HCLK5[0, 29, 27]
    HCLK_IOI:ENABLE.HCLK6[0, 29, 30]
    HCLK_IOI:ENABLE.HCLK7[0, 29, 31]
    HCLK_IOI:ENABLE.HCLK8[0, 28, 14]
    HCLK_IOI:ENABLE.HCLK9[0, 29, 15]
    HCLK_IOI:ENABLE.PERF0[0, 36, 28]
    HCLK_IOI:ENABLE.PERF1[0, 36, 20]
    HCLK_IOI:ENABLE.PERF2[0, 36, 14]
    HCLK_IOI:ENABLE.PERF3[0, 37, 14]
    Non-inverted[0]
    +
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    BUFR0:MUX.I[0, 35, 29][0, 35, 28][0, 35, 27][0, 35, 26][0, 35, 25][0, 34, 31][0, 35, 24][0, 35, 23]
    BUFR1:MUX.I[0, 34, 29][0, 34, 30][0, 34, 26][0, 34, 25][0, 34, 24][0, 34, 23][0, 36, 27][0, 36, 26]
    BUFR2:MUX.I[0, 34, 20][0, 34, 19][0, 34, 18][0, 34, 17][0, 34, 16][0, 34, 15][0, 36, 25][0, 36, 24]
    BUFR3:MUX.I[0, 35, 15][0, 35, 16][0, 35, 17][0, 35, 18][0, 35, 19][0, 31, 20][0, 35, 21][0, 32, 16]
    NONE00000000
    BUFIO0_I00000001
    BUFIO1_I00000010
    BUFIO2_I00000100
    BUFIO3_I00001000
    CKINT000010000
    CKINT100100000
    CKINT201000000
    CKINT310000000
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    BUFR0:BUFR_DIVIDE[0, 33, 28][0, 33, 29][0, 33, 30][0, 33, 27]
    BUFR1:BUFR_DIVIDE[0, 33, 24][0, 33, 25][0, 33, 26][0, 33, 23]
    BUFR2:BUFR_DIVIDE[0, 33, 19][0, 33, 20][0, 33, 21][0, 33, 18]
    BUFR3:BUFR_DIVIDE[0, 33, 15][0, 33, 16][0, 33, 17][0, 33, 14]
    BYPASS0000
    10001
    20011
    30101
    40111
    51001
    61011
    71101
    81111
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    BUFIO0:DELAY_BYPASS[0, 36, 31]
    BUFIO1:DELAY_BYPASS[0, 36, 21]
    BUFIO2:DELAY_BYPASS[0, 36, 16]
    BUFIO3:DELAY_BYPASS[0, 37, 16]
    Inverted~[0]
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    BUFIO0:MUX.I[0, 36, 29]
    BUFIO1:MUX.I[0, 37, 21]
    BUFIO2:MUX.I[0, 36, 17]
    BUFIO3:MUX.I[0, 37, 17]
    CCIO0
    PERF1
    +
    @@ -285,7 +781,7 @@

    I/O banks and special functions - +
    diff --git a/xilinx/virtex7/pcie.html b/xilinx/virtex7/pcie.html index d2b38c43..a874d42f 100644 --- a/xilinx/virtex7/pcie.html +++ b/xilinx/virtex7/pcie.html @@ -64,6 +64,7 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
      @@ -72,6 +73,7 @@
  • PCI Express Gen3 cores
    • +
  • Configuration registers
    • diff --git a/xilinx/virtex7/pcie3.html b/xilinx/virtex7/pcie3.html index fdbca64e..efa51a40 100644 --- a/xilinx/virtex7/pcie3.html +++ b/xilinx/virtex7/pcie3.html @@ -19,6 +19,7 @@ + @@ -63,6 +64,7 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Configuration Center
  • Clock interconnect
  • Clock management tile
  • PCI Express Gen2 cores
    • @@ -70,6 +72,7 @@
  • Bitstream
    • +
  • Configuration registers
    • @@ -4645,6 +4648,7 @@

    Bitstream +