diff --git a/_sources/xilinx/virtex4/io.rst.txt b/_sources/xilinx/virtex4/io.rst.txt index 6812521f..d0cea79e 100644 --- a/_sources/xilinx/virtex4/io.rst.txt +++ b/_sources/xilinx/virtex4/io.rst.txt @@ -107,6 +107,13 @@ Row ``r + 4`` is not used as ``SYSMON`` input — the "analog function" of that Bitstream ========= +.. raw:: html + :file: ../gen/tile-xc4v-IO.html + + +Tables +====== + .. raw:: html :file: ../gen/xc4v-iostd-drive.html @@ -118,6 +125,3 @@ Bitstream .. raw:: html :file: ../gen/xc4v-iostd-lvds.html - -.. raw:: html - :file: ../gen/tile-xc4v-IO.html diff --git a/_sources/xilinx/virtex5/io.rst.txt b/_sources/xilinx/virtex5/io.rst.txt index 17e6507a..e8ce0444 100644 --- a/_sources/xilinx/virtex5/io.rst.txt +++ b/_sources/xilinx/virtex5/io.rst.txt @@ -148,6 +148,13 @@ The ``SYSMON`` present on the device can use up to 16 IOB pairs from the left I/ Bitstream ========= +.. raw:: html + :file: ../gen/tile-xc5v-IO.html + + +Tables +====== + .. raw:: html :file: ../gen/xc5v-iostd-drive.html @@ -162,6 +169,3 @@ Bitstream .. raw:: html :file: ../gen/xc5v-iodelay-default-idelay-value.html - -.. raw:: html - :file: ../gen/tile-xc5v-IO.html diff --git a/_sources/xilinx/virtex6/io.rst.txt b/_sources/xilinx/virtex6/io.rst.txt index dab2062d..2e8d56a1 100644 --- a/_sources/xilinx/virtex6/io.rst.txt +++ b/_sources/xilinx/virtex6/io.rst.txt @@ -127,6 +127,20 @@ The devices also have dedicated configuration bank 0, which has no user I/O and Bitstream — ``IO`` ================== +.. raw:: html + :file: ../gen/tile-xc6v-IO.html + + +Bitstream — ``HCLK_IOI`` +======================== + +.. raw:: html + :file: ../gen/tile-xc6v-HCLK_IOI.html + + +Tables +====== + .. raw:: html :file: ../gen/xc6v-iostd-drive.html @@ -139,13 +153,6 @@ Bitstream — ``IO`` .. raw:: html :file: ../gen/xc6v-iostd-lvds.html -.. raw:: html - :file: ../gen/tile-xc6v-IO.html - - -Bitstream — ``HCLK_IOI`` -======================== - .. raw:: html :file: ../gen/xc6v-iostd-lvdsbias.html @@ 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"general-structure"], [87, "general-structure"], [104, "general-structure"], [118, "general-structure"], [134, "general-structure"], [148, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [161, "global-bits"], [162, "global-bits"], [163, "global-bits"], [164, "global-bits"], [165, "global-bits"], [166, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [129, "hclk"], [144, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [123, "i-o-banks-and-special-functions"], [139, "i-o-banks-and-special-functions"], [151, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [161, "i-o-pins"], [162, "i-o-pins"], [163, "i-o-pins"], [164, "i-o-pins"], [165, "i-o-pins"], [166, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [170, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [161, "imux-bits"], [162, "imux-bits"], [163, "imux-bits"], [164, "imux-bits"], [165, "imux-bits"], [166, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[148, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [157, "io-b"]], "IO.L": [[79, "io-l"], [157, "io-l"]], "IO.R": [[79, "io-r"], [157, "io-r"]], "IO.T": [[79, "io-t"], [157, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [170, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [170, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [123, "input-output"], [139, "input-output"], [151, "input-output"], [157, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [171, "input-output-buffer"]], "Interconnect": [[122, "interconnect"], [138, "interconnect"], [150, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [169, "introduction"]], "JED bits": [[160, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [159, "jed-mapping"], [161, "jed-mapping"], [162, "jed-mapping"], [163, "jed-mapping"], [164, "jed-mapping"], [165, "jed-mapping"], [166, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[159, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[159, "jed-mapping-macrocells-without-iob"]], "JED structure": [[159, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [170, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[171, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MMCM Tables": [[145, "mmcm-tables"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [171, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[148, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [171, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [171, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[152, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[153, "pci-express-gen3-cores"]], "PCI Express cores": [[124, "pci-express-cores"], [140, "pci-express-cores"]], "PCI Express holes": [[148, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[152, "pcie-l"]], "PCIE_R": [[152, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PLL Tables": [[145, "pll-tables"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[129, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [169, "packages"]], "Part": [[17, "part"], [160, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[125, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [118, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[148, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [171, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [170, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [171, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [160, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [161, "speed-data"], [162, "speed-data"], [163, "speed-data"], [164, "speed-data"], [165, "speed-data"], [166, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [118, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[158, 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110, 126, 141], "9998": [45, 59, 81, 96, 110, 126, 141], "9999": [45, 59, 81, 96, 110, 126, 141], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 159, "9fb_group": [161, 162, 163, 164, 165, 166], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 159, "9reg_d_ireg": 159, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 124, 127, 142, 152, 153], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 117, 125, 130, 133, 140, 144], "9rowcolumn01234567891011121314151617181920212223242526272829": [114, 135, 136, 145, 152], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [119, 120], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 118, 123, 134, 139, 148, 151, 160, 171], "AED": [12, 169], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 171], "As": [35, 134, 171], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 118, 134, 148, 171], "ISE": [35, 171], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 118, 134, 139, 148, 171], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 118, 123, 134, 139, 148, 151, 171], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 118, 134, 139, 148, 151, 160, 169, 171], "Its": [35, 81], "No": 148, "Not": [15, 16, 36, 55, 91, 171], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 148, 171], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 118, 134, 139, 148, 151], "These": [36, 91, 139, 148], "To": [35, 36, 96], "_": [17, 34, 36, 160, 171], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 159, 171], "_gclk": 171, "_init": [46, 82], "_inv": [36, 171], "_lct": 171, "_mc": [12, 169], "_mux": [36, 46, 82], "_none": 171, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a17": [6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a18": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a19": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a20": [6, 7, 22, 23, 24, 165, 166], "a21": [6, 7, 22, 23, 165, 166], "a22": [6, 7, 22, 23, 165, 166], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5ffinit": [128, 143], "a5ffinitslice0": [128, 143], "a5ffmux": [128, 143], "a5ffsr": [128, 143], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 128, "a5q0": 60, "a5q0100": [60, 128, 143], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a6lut": [60, 112, 128, 143], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a_dfeclkdlyadj": 136, "a_dfedlyovrd": 136, "a_dfedlyovrdgtx0": 136, "a_dfedlyovrdgtx1": 136, "a_dfedlyovrdgtx2": 136, "a_dfedlyovrdgtx3": 136, "a_dfetap1": 136, "a_dfetap2": 136, "a_dfetap3": 136, "a_dfetap4": 136, "a_dfetapovrd": 136, "a_dfetapovrdgtx0": 136, "a_dfetapovrdgtx1": 136, "a_dfetapovrdgtx2": 136, "a_dfetapovrdgtx3": 136, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 136, "a_gtxrxresetgtx0": 136, "a_gtxrxresetgtx1": 136, "a_gtxrxresetgtx2": 136, "a_gtxrxresetgtx3": 136, "a_gtxtxreset": 136, "a_gtxtxresetgtx0": 136, "a_gtxtxresetgtx1": 136, "a_gtxtxresetgtx2": 136, "a_gtxtxresetgtx3": 136, "a_input": [116, 132, 147], "a_loopback": 136, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 136, "a_pllclkrxresetgtx0": 136, "a_pllclkrxresetgtx1": 136, "a_pllclkrxresetgtx2": 136, "a_pllclkrxresetgtx3": 136, "a_pllclktxreset": 136, "a_pllclktxresetgtx0": 136, "a_pllclktxresetgtx1": 136, "a_pllclktxresetgtx2": 136, "a_pllclktxresetgtx3": 136, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 136, "a_pllrxresetgtx0": 136, "a_pllrxresetgtx1": 136, "a_pllrxresetgtx2": 136, "a_pllrxresetgtx3": 136, "a_plltxreset": 136, "a_plltxresetgtx0": 136, "a_plltxresetgtx1": 136, "a_plltxresetgtx2": 136, "a_plltxresetgtx3": 136, "a_prbscntreset": 136, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 136, "a_prbscntresetgtx1": 136, "a_prbscntresetgtx2": 136, "a_prbscntresetgtx3": 136, "a_q": 81, "a_rxbufreset": 136, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 136, "a_rxbufresetgtx1": 136, "a_rxbufresetgtx2": 136, "a_rxbufresetgtx3": 136, "a_rxcdrfreqreset": 136, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 136, "a_rxcdrfreqresetgtx1": 136, "a_rxcdrfreqresetgtx2": 136, "a_rxcdrfreqresetgtx3": 136, "a_rxcdrhold": 136, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 136, "a_rxcdrholdgtx1": 136, "a_rxcdrholdgtx2": 136, "a_rxcdrholdgtx3": 136, "a_rxcdrphasereset": 136, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 136, "a_rxcdrphaseresetgtx1": 136, "a_rxcdrphaseresetgtx2": 136, "a_rxcdrphaseresetgtx3": 136, "a_rxcdrreset": 136, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 136, "a_rxcdrresetgtx1": 136, "a_rxcdrresetgtx2": 136, "a_rxcdrresetgtx3": 136, "a_rxdfereset": 136, "a_rxdferesetgtx0": 136, "a_rxdferesetgtx1": 136, "a_rxdferesetgtx2": 136, "a_rxdferesetgtx3": 136, "a_rxenpmaphasealign": 136, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 136, "a_rxenpmaphasealigngtx1": 136, "a_rxenpmaphasealigngtx2": 136, "a_rxenpmaphasealigngtx3": 136, "a_rxenprbstst": 136, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 136, "a_rxensamplealigngtx0": 136, "a_rxensamplealigngtx1": 136, "a_rxensamplealigngtx2": 136, "a_rxensamplealigngtx3": 136, "a_rxeqmix": 136, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 136, "a_rxplllkdetengtx0": 136, "a_rxplllkdetengtx1": 136, "a_rxplllkdetengtx2": 136, "a_rxplllkdetengtx3": 136, "a_rxpllpowerdown": 136, "a_rxpllpowerdowngtx0": 136, "a_rxpllpowerdowngtx1": 136, "a_rxpllpowerdowngtx2": 136, "a_rxpllpowerdowngtx3": 136, "a_rxpmasetphas": 136, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 136, "a_rxpmasetphasegtx1": 136, "a_rxpmasetphasegtx2": 136, "a_rxpmasetphasegtx3": 136, "a_rxpolar": 136, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 136, "a_rxpolaritygtx1": 136, "a_rxpolaritygtx2": 136, "a_rxpolaritygtx3": 136, "a_rxpowerdown": 136, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 136, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 136, "a_rxresetgtx1": 136, "a_rxresetgtx2": 136, "a_rxresetgtx3": 136, "a_txbufdiffctrl": 136, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 136, "a_txdeemphgtx0": 136, "a_txdeemphgtx1": 136, "a_txdeemphgtx2": 136, "a_txdeemphgtx3": 136, "a_txdiffctrl": 136, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 136, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 136, "a_txelecidlegtx1": 136, "a_txelecidlegtx2": 136, "a_txelecidlegtx3": 136, "a_txenpmaphasealign": 136, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 136, "a_txenpmaphasealigngtx1": 136, "a_txenpmaphasealigngtx2": 136, "a_txenpmaphasealigngtx3": 136, "a_txenprbstst": 136, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 136, "a_txplllkdeten": 136, "a_txplllkdetengtx0": 136, "a_txplllkdetengtx1": 136, "a_txplllkdetengtx2": 136, "a_txplllkdetengtx3": 136, "a_txpllpowerdown": 136, "a_txpllpowerdowngtx0": 136, "a_txpllpowerdowngtx1": 136, "a_txpllpowerdowngtx2": 136, "a_txpllpowerdowngtx3": 136, "a_txpmasetphas": 136, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 136, "a_txpmasetphasegtx1": 136, "a_txpmasetphasegtx2": 136, "a_txpmasetphasegtx3": 136, "a_txpolar": 136, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 136, "a_txpolaritygtx1": 136, "a_txpolaritygtx2": 136, "a_txpolaritygtx3": 136, "a_txpostemphasi": 136, "a_txpowerdown": 136, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 136, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 136, "a_txprbsforceerrgtx1": 136, "a_txprbsforceerrgtx2": 136, "a_txprbsforceerrgtx3": 136, "a_txpreemphasi": 136, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 136, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 136, "a_txresetgtx1": 136, "a_txresetgtx2": 136, "a_txresetgtx3": 136, "a_txsw": 136, "a_txswinggtx0": 136, "a_txswinggtx1": 136, "a_txswinggtx2": 136, "a_txswinggtx3": 136, "aa1": [6, 7, 22, 23, 165, 166], "aa10": [6, 7, 165, 166], "aa11": [6, 7, 165, 166], "aa12": [6, 7, 165, 166], "aa13": [6, 7, 165, 166], "aa14": [6, 7, 165, 166], "aa15": [6, 7, 165, 166], "aa16": [6, 7, 165, 166], "aa17": [6, 7, 165, 166], "aa18": [6, 7, 165, 166], "aa19": [6, 7, 165, 166], "aa2": [6, 7, 22, 23, 165, 166], "aa20": [6, 7, 165, 166], "aa21": [6, 7, 165, 166], "aa22": [6, 7, 165, 166], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 165, 166], "aa4": [6, 7, 22, 23, 165, 166], "aa5": [6, 7, 165, 166], "aa6": [6, 7, 165, 166], "aa7": [6, 7, 165, 166], "aa8": [6, 7, 165, 166], "aa9": [6, 7, 165, 166], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 165, 166], "ab10": [6, 7, 165, 166], "ab11": [6, 7, 165, 166], "ab12": [6, 7, 165, 166], "ab13": [6, 7, 165, 166], "ab14": [6, 7, 165, 166], "ab15": [6, 7, 165, 166], "ab16": [6, 7, 165, 166], "ab17": [6, 7, 165, 166], "ab18": [6, 7, 165, 166], "ab19": [6, 7, 165, 166], "ab2": [6, 7, 22, 23, 165, 166], "ab20": [6, 7, 165, 166], "ab21": [6, 7, 165, 166], "ab22": [6, 7, 165, 166], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 165, 166], "ab4": [6, 7, 22, 23, 165, 166], "ab5": [6, 7, 165, 166], "ab6": [6, 7, 165, 166], "ab7": [6, 7, 165, 166], "ab8": [6, 7, 165, 166], "ab9": [6, 7, 165, 166], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 148, 151, 171], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 160, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 136, "ac_cap_dis_0": [66, 119, 120], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 119, "ac_cap_dis_0gtx_du": 120, "ac_cap_dis_1": [66, 119, 120], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 119, "ac_cap_dis_1gtx_du": 120, "ac_cap_disgtx0": 136, "ac_cap_disgtx1": 136, "ac_cap_disgtx2": 136, "ac_cap_disgtx3": 136, "acb": [12, 34, 169], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 169, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 118, 134, 148, 151, 160, 169, 171], "activ": [35, 36, 46, 82, 170], "activelanesin": 124, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 118, 134, 148, 171], "acy0": [60, 112, 128, 143], "acy0slice0": [112, 128, 143], "acy0slice1": [60, 128], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 118, 134, 148, 171], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 118, 134], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 72, "addr_cascade_out_a": 141, "addr_cascade_out_abram": 141, "addr_cascade_out_b": 141, "addr_cascade_out_bbram": 141, "addra0": 72, "addra1": 72, "addra10": 72, "addra11": 72, "addra2": 72, "addra3": 72, "addra4": 72, "addra5": 72, "addra6": 72, "addra7": 72, "addra8": 72, "addra9": 72, "addral0": 141, "addral1": 141, "addral10": 141, "addral11": 141, "addral12": 141, "addral13": 141, "addral14": 141, "addral2": 141, "addral3": 141, "addral4": 141, "addral5": 141, "addral6": 141, "addral7": 141, "addral8": 141, "addral9": 141, "addrau0": 141, "addrau1": 141, "addrau10": 141, "addrau11": 141, "addrau12": 141, "addrau13": 141, "addrau14": 141, "addrau2": 141, "addrau3": 141, "addrau4": 141, "addrau5": 141, "addrau6": 141, "addrau7": 141, "addrau8": 141, "addrau9": 141, "addrb0": 72, "addrb1": 72, "addrb10": 72, "addrb11": 72, "addrb2": 72, "addrb3": 72, "addrb4": 72, "addrb5": 72, "addrb6": 72, "addrb7": 72, "addrb8": 72, "addrb9": 72, "addrbl0": 141, "addrbl1": 141, "addrbl10": 141, "addrbl11": 141, "addrbl12": 141, "addrbl13": 141, "addrbl14": 141, "addrbl2": 141, "addrbl3": 141, "addrbl4": 141, "addrbl5": 141, "addrbl6": 141, "addrbl7": 141, "addrbl8": 141, "addrbl9": 141, "addrbu0": 141, "addrbu1": 141, "addrbu10": 141, "addrbu11": 141, "addrbu12": 141, "addrbu13": 141, "addrbu14": 141, "addrbu2": 141, "addrbu3": 141, "addrbu4": 141, "addrbu5": 141, "addrbu6": 141, "addrbu7": 141, "addrbu8": 141, "addrbu9": 141, "address": [15, 16, 35, 46, 81, 82, 91, 96], "adi1mux": [60, 112, 128, 143], "adi1muxslice0": [60, 112, 128], "adjac": [55, 91, 96, 148, 151], "adreg": [132, 147], "adregdsp0": 132, "adregdsp1": 132, "adv_b": 151, "advanc": 14, "ae1": [22, 23], "ae10": [22, 23], "ae11": [22, 23], "ae12": [22, 23], "ae13": [22, 23], "ae14": [22, 23], "ae15": [22, 23], "ae16": [22, 23], "ae17": [22, 23], "ae18": [22, 23], "ae19": [22, 23], "ae2": [22, 23], "ae20": [22, 23], "ae21": [22, 23], "ae22": [22, 23], "ae23": [22, 23], "ae24": [22, 23], "ae25": [22, 23], "ae26": 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[22, 23], "af22": [22, 23], "af23": [22, 23], "af24": [22, 23], "af25": [22, 23], "af26": [22, 23], "af3": [22, 23], "af4": [22, 23], "af5": [22, 23], "af6": [22, 23], "af7": [22, 23], "af8": [22, 23], "af9": [22, 23], "aff_latch": 128, "aff_latchslice0": 128, "affect": [36, 91, 148, 171], "affinit": [112, 128, 143], "affinitslice0": [112, 128, 143], "affinitslice1": 128, "affmux": [60, 112, 128, 143], "affmuxslice1": 60, "affsr": [112, 128, 143], "affsrinit": 60, "affsrinitslice0": 60, "affsrinitslice1": 60, "affsrslice0": 143, "affsrslice1": [128, 143], "after": [35, 36, 55, 91, 104, 118], "afterward": 171, "ag": 35, "again": [35, 91], "agp": 79, "agp0": 93, "agp00011": 79, "agp0100101011": 93, "agp0111": 79, "agp011101010": 79, "agp011101011": 79, "agp1111": 93, "ai1": [128, 143], "aim": 11, "align": [96, 148], "align_comma_msb": 88, "align_comma_word": [89, 105, 136], "align_comma_word_0": [66, 119, 120], "align_comma_word_0gtp": 66, "align_comma_word_0gtp_du": 119, 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134, 139, 148, 151, 159, 160, 169, 171], "alt": [46, 82], "alt0": [37, 46, 60, 82, 99, 112, 128, 143], "alt00010001": 107, "alt0010001": 107, "altdig": [46, 82], "altern": [46, 82, 148], "alumode0": [116, 132, 147], "alumode0dsp0": 116, "alumode0dsp1": 116, "alumode1": [116, 132, 147], "alumode2": [116, 132, 147], "alumode2dsp0": 147, "alumode2dsp1": 147, "alumode3": [116, 132, 147], "alumode3dsp0": [116, 132], "alumode3dsp1": 132, "alumodereg": [116, 132, 147], "alwai": [12, 14, 17, 35, 36, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 139, 148, 160, 171], "amount": [58, 87, 104], "an": [12, 14, 15, 17, 34, 35, 36, 46, 55, 56, 58, 81, 87, 91, 92, 96, 148, 151, 159, 160, 169, 170, 171], "analog": [55, 91, 108, 123, 139, 151], "analog_misc": [130, 145], "analog_read111": 63, "and1": [37, 46], "ani": [35, 36, 46, 55, 58, 87, 91, 108, 123, 148, 171], "anoth": [46, 82, 91, 104, 118, 134, 148, 151], "anyth": [35, 82], "anywai": [55, 148], "anywher": 148, "ao_toggl": 145, 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171], "arbitrarili": 12, "architectur": [104, 169], "area": [15, 16, 35, 45, 47, 55, 58, 81, 83, 87, 91, 96, 104, 118, 134, 148, 159, 160, 171], "areg": [45, 81, 103], "areg_acascreg": [116, 132, 147], "aren": [55, 58, 151], "ari_cap_en": 153, "ari_cap_enablepcie3": 153, "arm": 148, "around": [91, 104, 134], "arrai": [35, 159, 160, 171], "arrang": [151, 159], "array_mod": 145, "array_mode_4_x_40": 145, "array_mode_4_x_81": 145, "array_mode_8_x_41": 145, "array_modein_fifo": 145, "ascii": 171, "assembl": [46, 82], "assert": [15, 16], "assign": [13, 15, 16, 58, 87, 104, 118, 134, 148, 171], "associ": [12, 34, 36, 37, 42, 46, 55, 58, 82, 87, 91, 99, 104, 108, 118, 123, 134, 148, 160, 169, 170, 171], "async": [14, 36, 81, 171], "async1": [53, 61, 65, 144, 145], "async11": [45, 59], "asynchron": [46, 56, 82, 171], "atbbumpen": 105, "atben": 105, "atbsel": 105, "attempt": 35, "attribut": [45, 46, 81, 82, 96], "auto": 35, "auto01": 136, "auto_c": 105, "auto_calgt11a": 105, "auto_calgt11b": 105, "auto_dps00": [102, 114], "auto_zd211": [102, 114], "autoincr": 35, "automot": [12, 34], "autoreset_over_under_flow": 116, "autoreset_patdet": [132, 147], "autoreset_pattern_detect": 116, "autoreset_pattern_detect_optinv": 116, "autoreset_pattern_detectdsp0": 116, "aux": [2, 3, 4, 5, 6, 7, 8, 9], "auxiliari": [108, 123, 139, 151], "avail": [17, 55, 91, 104, 118, 134, 148, 160], "avdd_comp_set": [130, 145], "avdd_vbg_pd": [130, 145], "avdd_vbg_sel": [130, 145], "ave_freq_lock1": 114, "ave_freq_lock10": 102, "awai": [104, 118, 148], "ax0": [60, 112, 128, 143], "ax01": [60, 112, 128, 143], "ax0100": [112, 128, 143], "ax1": [60, 112], "ax10": [128, 143], "ax1010": 60, "axisten_if_cc_alignment_mod": 153, "axisten_if_cc_alignment_modepcie3": 153, "axisten_if_cc_parity_chk": 153, "axisten_if_cq_alignment_mod": 153, "axisten_if_enable_client_tag": 153, "axisten_if_enable_msg_rout": 153, "axisten_if_enable_rx_msg_intfc": 153, "axisten_if_rc_alignment_mod": 153, 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151, "bufio1": [113, 151], "bufio100000001000": 113, "bufio111": 100, "bufio1_i0000000000000010": 139, "bufio1_i00000010": 151, "bufio2": [113, 151], "bufio200000010000": 113, "bufio2_0": 61, "bufio2_1": 61, "bufio2_2": 61, "bufio2_3": 61, "bufio2_4": 61, "bufio2_5": 61, "bufio2_6": 61, "bufio2_7": 61, "bufio2_bt001010": 64, "bufio2_bt0_40000": 71, "bufio2_bt101011": 64, "bufio2_bt1_50001": 71, "bufio2_bt201100": 64, "bufio2_bt2_60010": 71, "bufio2_bt301111": 64, "bufio2_bt3_70011": 71, "bufio2_bt410000": 64, "bufio2_bt510001": 64, "bufio2_bt610010": 64, "bufio2_bt710011": 64, "bufio2_i0000000000000100": 139, "bufio2_i00000100": 151, "bufio2_lr000000": 64, "bufio2_lr0_40101": 71, "bufio2_lr100001": 64, "bufio2_lr1_50110": 71, "bufio2_lr200010": 64, "bufio2_lr2_60111": 71, "bufio2_lr300011": 64, "bufio2_lr3_71111": 71, "bufio2_lr400100": 64, "bufio2_lr500111": 64, "bufio2_lr601000": 64, "bufio2_lr701001": 64, "bufio2fb_bt000000": 71, "bufio2fb_bt001010": 64, "bufio2fb_bt100001": 71, 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5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c20": [6, 7, 22, 23, 24, 165, 166], "c21": [6, 7, 22, 23, 165, 166], "c22": [6, 7, 22, 23, 165, 166], "c23": [22, 23], "c24": [22, 23], "c25": [22, 23], "c26": [22, 23], "c3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c5ffinit": [128, 143], "c5ffinitslice0": [128, 143], "c5ffmux": [128, 143], "c5ffsr": [128, 143], "c5ffsrinit": 60, "c5ffsrinitslice0": 60, "c5ffsrslice0": 128, "c5ffsrslice1": 128, "c5q0": 60, "c5q0100": [60, 128, 143], "c6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c6lut": [60, 112, 128, 143], "c7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 161, 162, 163, 164, 165, 166], "c8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 162, 163, 164, 165, 166], "c9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "cal_ba": 69, "cal_bypass": 69, "cal_ca": 69, "cal_calibration_mod": 69, "cal_clk_div": 69, "cal_delai": 69, "cal_ra": 69, "calcul": [15, 16], "calibration0": 69, "call": [36, 55, 58, 87, 91, 134, 148, 171], "came": [35, 91], "can": [12, 14, 17, 34, 35, 36, 46, 55, 56, 58, 81, 82, 87, 91, 96, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "cannot": [35, 46, 82, 96, 134, 148, 171], "cap": 76, "capabilities_ptr": [140, 152], "capabilitiespoint": 124, "capabl": [12, 34, 46, 92, 96, 108, 123, 139, 151], "captur": [39, 46, 48, 49, 56, 75, 82, 84, 92, 101, 115, 131, 146, 170], "cardbus_cis_point": [70, 140, 152], "cardbuscispoint": 124, "cardin": [55, 91], "care": 35, "carri": [54, 90], "carryin": [103, 116, 132, 147], "carryin0": [53, 65], "carryindsp0": [116, 132], "carryindsp1": [116, 132], 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145], "clkinsel_mod": [71, 114], "clkinsel_modepl": [71, 114], "clkinsel_stat": [71, 114], "clkinsel_staticpl": [71, 114], "clkinselmmcm0": 130, "clkinselmmcm1": 130, "clkinselpl": 145, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 155, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 156], "clkout0000": [71, 130], "clkout0001": 130, "clkout001": 145, "clkout01000": 145, "clkout0_deskew_adjust": 114, "clkout0_dt": [130, 145], "clkout0_edg": [130, 145], "clkout0_edgemmcm": 145, "clkout0_edgemmcm0": 130, "clkout0_edgemmcm1": 130, "clkout0_edgepl": 145, "clkout0_en": [130, 145], "clkout0_enmmcm": 145, "clkout0_enmmcm0": 130, "clkout0_enmmcm1": 130, "clkout0_enpl": 145, "clkout0_frac": [130, 145], "clkout0_frac_en": [130, 145], "clkout0_frac_enmmcm": 145, "clkout0_frac_enmmcm0": 130, "clkout0_frac_enmmcm1": 130, "clkout0_frac_wf": 130, "clkout0_frac_wf_fal": 145, "clkout0_frac_wf_fallmmcm": 145, "clkout0_frac_wf_ris": 145, "clkout0_frac_wf_risemmcm": 145, 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[130, 145], "clkout6_lt": [130, 145], "clkout6_mx": [130, 145], "clkout6_nocount": [130, 145], "clkout6_nocountmmcm": 145, "clkout6_nocountmmcm0": 130, "clkout6_nocountmmcm1": 130, "clkout6_pm": [130, 145], "clkout6_use_fine_p": [130, 145], "clkout6_use_fine_psmmcm": 145, "clkout6_use_fine_psmmcm0": 130, "clkout6_use_fine_psmmcm1": 130, "clkout_div": 145, "clkout_div_st": 145, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [119, 120], "clkout_north_s0": [119, 120], "clkout_north_s101": [119, 120], "clkout_phase_shift": 64, "clkout_south": [119, 120], "clkout_south_n0": [119, 120], "clkout_south_n001": [119, 120], "clkout_west": 66, "clkout_westgtp": 66, "clkoutdcm0000": 114, "clkoutdcm1100": 114, "clkoutdcm2001": 114, "clkoutdcm3101": 114, "clkoutdcm4010": 114, "clkoutdcm5110": 114, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [119, 120], "clkpn1": [119, 120], "clkr": [58, 78, 156], "clkrcv_trst": [120, 136], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 136, "clkrcv_trstgtx_dual": 120, "clkslice0": 112, "clkslice1": [60, 128], "clkt": [58, 78, 87, 156], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 136, "clktestsig1": 135, "clktestsig11": 136, "clktestsig1111": 136, "clktestsig_sel": 135, "clktestsig_selgth": 135, "clkv": [78, 156], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 118, 121, 123, 134, 137, 139, 148, 149, 151, 160, 169, 171], "clock_delai": 125, "clock_hold": 130, "clock_holdmmcm0": 130, "clock_holdmmcm1": 130, "clock_invert_m": 116, "clock_invert_p": 116, "clock_invert_pdsp1": 116, "clockwis": [58, 87], "close": [58, 81, 134, 148], "closest": 58, "clr0": 154, "clrmux": 154, "clrmuxlc0": 154, "clrmuxlc1": 154, "clrmuxlc2": 154, "clrmuxlc3": 154, "cm_trim": 136, "cm_trim_0": [66, 120], "cm_trim_1": [66, 120], "cmd_intx_impl": [140, 152], "cmd_intx_implementedpci": [140, 152], "cmd_offset": 145, "cmo": 14, "cmos0": 155, "cmos00": [74, 79], "cmos00111": 139, "cmos01": 74, "cmos111": [57, 93, 108, 123], "cmos1200011": 139, "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 118, 121, 123, 134, 137, 148, 149], "cmt0": 61, "cmt10": 61, "cmt_bot": 145, "cmt_bufg_": 134, "cmt_bufg_bot": [134, 137], "cmt_bufg_top": [134, 137], "cmt_clk010000000001000": 113, "cmt_clk100000010001000": 113, "cmt_clk1000001000010000": 113, "cmt_clk1100100000010000": 113, "cmt_clk1200000001010000": 113, "cmt_clk1300000100010000": 113, "cmt_clk1400010000010000": 113, "cmt_clk1501000000010000": 113, "cmt_clk1610000000100000": 113, "cmt_clk1700000010100000": 113, "cmt_clk1800001000100000": 113, "cmt_clk1900100000100000": 113, "cmt_clk2000000001100000": 113, "cmt_clk200001000001000": 113, "cmt_clk2100000100100000": 113, "cmt_clk2200010000100000": 113, "cmt_clk2301000000100000": 113, "cmt_clk2410000000000010": 113, "cmt_clk2500000010000010": 113, "cmt_clk2600001000000010": 113, "cmt_clk2700100000000010": 113, "cmt_clk300100000001000": 113, "cmt_clk400000001001000": 113, "cmt_clk500000100001000": 113, "cmt_clk600010000001000": 113, "cmt_clk701000000001000": 113, "cmt_clk810000000010000": 113, "cmt_clk900000010010000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_fifo": 149, "cmt_pll": 71, "cmt_top": 145, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 155, "cmuxosc": 155, "cnr": [58, 78, 87, 156], "co01": 154, "co1": 154, "co_dur": 145, "coarse_bypass": 145, "coarse_delai": 145, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 118, 134, 148], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 123, 139, 151, 159, 160, 161, 162, 163, 164, 165, 166, 168, 170], "columnar": 104, "com": [51, 86], "com_burst_v": 136, "com_burst_val_0": [66, 119, 120], "com_burst_val_1": [66, 119, 120], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 171], "combination": 81, "combinatori": [14, 36, 171], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 118, 123, 134, 148, 169, 171], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 136, "comma_10b_enable_0": [66, 119, 120], "comma_10b_enable_1": [66, 119, 120], "comma_10b_mask": [88, 89, 105], "comma_doubl": 136, "comma_double_0": [119, 120], "comma_double_0gtp_du": 119, "comma_double_0gtx_du": 120, "comma_double_1": [119, 120], "comma_double_1gtp_du": 119, "comma_double_1gtx_du": 120, "comma_doublegtx0": 136, "comma_doublegtx1": 136, "comma_doublegtx2": 136, "comma_doublegtx3": 136, "commerci": [17, 160], "common": [100, 151], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [148, 159], "companion": [44, 106], "compat": [12, 34, 169], "compens": 82, "complement": [108, 123, 139, 151], "complet": [12, 13, 16, 34, 35, 36, 104, 148, 159, 169], "complex": [15, 16, 148], "comput": [81, 159], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86, 102, 114], "concur00100101": 102, "concur1001": [64, 114], "concurdcm": [51, 86, 102], "concurdcm0": 114, "concurdcm1": 114, "config": [15, 16, 159], "config01": 114, "config10": 102, "config_fallback": [115, 131, 146], "config_r": [39, 48, 49, 75, 84, 101, 115, 131, 146, 155], "configrout": 124, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 118, 121, 123, 134, 137, 139, 149, 151, 156, 159, 168], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 123, 139, 148, 170, 171], "consecut": 134, "consid": [35, 104, 108, 118, 123, 134, 139, 148, 151], "consist": [35, 36, 81, 104, 118, 123, 134, 139, 148], "const": [13, 14, 35, 36, 46, 82, 170, 171], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 171, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 170, 171], "content": [35, 46, 82, 134], "contigu": [15, 16], "continu": [35, 151], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "control_0": [130, 145], "control_1": [130, 145], "control_2": [130, 145], "control_3": [130, 145], "control_4": [130, 145], "control_5": [130, 145], "control_6": 145, "control_7": 145, "convert": [15, 16], "convst": 109, "convstclk": [111, 127, 142], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 159, 160, 171], "cor": [41, 54, 78, 90, 106, 121, 137, 149], "cor1": [54, 67, 121, 137, 149], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 118, 121, 137, 149, 169, 171], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 148, 156], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 118, 123, 134, 139, 148, 151, 160, 171], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 118, 134, 148, 161, 162, 163, 164, 165, 166], "cout": [46, 82, 157], "coutmux": [60, 112, 128, 143], "coutmuxslice1": 60, "cover": [104, 118, 134, 148, 151, 171], "cp": [130, 145], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 162, 169], "cp_bias_trip_set": [130, 145], "cp_bias_trip_setmmcm": 145, "cp_bias_trip_setmmcm0": 130, "cp_bias_trip_setmmcm1": 130, "cp_bias_trip_setpl": 145, "cp_re": [130, 145], "cpl_timeout_disable_support": [140, 152], "cpl_timeout_ranges_support": [140, 152], "cpld": [0, 12, 34, 36, 169, 171], "cpmc440clk": 125, "cpmc440timerclock": 125, "cpmdcrclk": 125, "cpmdma0llclk": 125, "cpmdma1llclk": 125, "cpmdma2llclk": 125, "cpmdma3llclk": 125, "cpmfcmclk": 125, "cpminterconnectclk": 125, "cpmmcclk": 125, "cpmmcm": [130, 145], "cpmppcmplbclk": 125, "cpmppcs0plbclk": 125, "cpmppcs1plbclk": 125, "cppll": 145, "crammod": [60, 112, 128, 143], "crc": [39, 48, 49, 62, 84, 101, 115, 155], "crc32_0": [119, 120], "crc32_1": [119, 120], "crc32_2": [119, 120], "crc32_3": [119, 120], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [119, 120], "crc_start_of_pkt": [88, 89], "crcclk": [119, 120], "crcclkgtp_dual": 119, "crcclkgtx_dual": 120, "creat": [55, 87, 91, 104, 118], "create_edg": [98, 111, 129, 144], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 116, 132, 147], "cregdsp": [53, 65], "cregdsp0": [116, 132], "cregdsp1": 132, "crm_core_clk_freq_500": 153, "crm_core_clk_freq_500pcie3": 153, "crm_module_rst": [140, 152], "crm_user_clk_freq": 153, "crmcoreclk": 124, "crmcoreclkdlo": 124, "crmcoreclkpci": 124, "crmcoreclkrxo": 124, "crmcoreclkrxopci": 124, "crmcoreclktxo": 124, "crmcoreclktxopci": 124, "crmuserclk": 124, "crmuserclkrxo": 124, "crmuserclktxo": 124, "cross": [58, 91, 134, 148], "cs144": [20, 21, 34, 163, 169], "cs280": [24, 25, 34, 164, 169], "cs48": [26, 27, 28, 30, 31, 34, 161, 162, 169], "cs_b": [108, 123], "csi_b": [139, 151], "cso2pin": [50, 63], "cso_b": [123, 139, 151], "cspin": [98, 111, 127], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 121, 137, 149], "ctl1": [137, 149], "ctl_mode": 145, "ctl_modephaser_in0": 145, "ctl_modephaser_in1": 145, "ctl_modephaser_in2": 145, "ctl_modephaser_in3": 145, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [122, 138, 150], "ctrl00001": [138, 150], "ctrl1": [122, 138, 150], "ctrl10010": [138, 150], "ctrl2": 122, "ctrl3": 122, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 118, 148], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 128, 143], "cx0100": [112, 128, 143], "cx1": [60, 112], "cx10": [128, 143], "cx1010": 60, "cxt": 134, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 128, 143], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 128, 143], "cyinitslice0": [73, 99, 112, 128, 143], "cyinitslice1": [37, 46, 60, 73, 112, 128, 143], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 123, 139, 145, 151, 171], "d0": [132, 147], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166, 171], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d100001": 123, "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d15": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d16": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d17": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d18": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d19": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d20": [6, 7, 22, 23, 24, 132, 147, 165, 166], "d21": [6, 7, 22, 23, 132, 147, 165, 166], "d22": [6, 7, 22, 23, 132, 147, 165, 166], "d23": [22, 23, 132, 147], "d24": [22, 23, 132, 147], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d3iob0": [108, 123], "d3iob1": [108, 123], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d4iob0": 108, "d4iob1": 108, "d4ologic0": 123, "d4ologic1": 123, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 123, 132, 147, 163, 164, 165, 166], "d5ffinit": [128, 143], "d5ffinitslice0": [128, 143], "d5ffmux": [128, 143], "d5ffsr": [128, 143], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 128, "d5ologic0": [108, 123], "d5ologic1": [108, 123], "d5q0": 60, "d5q0100": [60, 128, 143], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 147, 161, 162, 163, 164, 165, 166], "d6iob0": 123, "d6iob1": 123, "d6lut": [60, 112, 128, 143], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 132, 147, 161, 162, 163, 164, 165, 166], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d_in": [108, 123], "d_out_busi": 123, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 118, 121, 123, 134, 148, 155, 159, 160, 167, 171], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_ctl_a_n": 145, "data_ctl_a_nphy_control": 145, "data_ctl_b_n": 145, "data_ctl_c_n": 145, "data_ctl_c_nphy_control": 145, "data_ctl_d_n": 145, "data_ctl_n": 145, "data_ctl_nphaser_out0": 145, "data_ctl_nphaser_out1": 145, "data_ctl_nphaser_out2": 145, "data_ctl_nphaser_out3": 145, "data_l": [110, 126, 141], "data_r": [61, 108, 123], "data_rd_cycl": 145, "data_u": [110, 126, 141], "data_width": [108, 123], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 159, 168, 170, 171], "datain": 123, "datain1000": 123, "datainilogic0": 123, "datainilogic1": 123, "dataint": 155, "datap": [45, 59, 81, 96], "datap_l": [110, 126, 141], "datap_u": [110, 126, 141], "datareg": 13, "datastream": [17, 160], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 122, 138, 150, 154, 157], "dbl0001010000": 122, "dbl0001100000": 122, "dbl0010010000": 122, "dbl0010100000": 122, "dbl0100010000": 122, "dbl0100100000": 122, "dbl1000010000": 122, "dbl1000100000": 122, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 123, 139, 151], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 127], "dci_clk_enablemisc": 85, "dci_misc": [108, 123, 139], "dci_mod": [57, 93, 108, 123, 139], "dci_osc_sel": 50, "dci_t": [108, 123, 139], "dci_test_mux": 50, "dcireset": [98, 111, 127, 142], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 123, 139], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 119, 120, 127, 135, 136, 142], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 135, "dclkgtp": 66, "dclkgtp_dual": 119, "dclkgtx_dual": 120, "dclksysmon": 111, "dclkxadc": 142, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": [64, 114], "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": [71, 114], "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin001": 114, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": [64, 114], "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfb010": 114, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": [71, 114], "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": [102, 114], "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_clkdv_clkfx_alignmentdcm0": 114, "dcm_clkdv_clkfx_alignmentdcm1": 114, "dcm_clkfb_iodly_muxinsel": 114, "dcm_clkfb_iodly_muxinseldcm0": 114, "dcm_clkfb_iodly_muxinseldcm1": 114, "dcm_clkfb_iodly_muxout_sel": 114, "dcm_clkfb_iodly_muxout_seldcm0": 114, "dcm_clkfb_iodly_muxout_seldcm1": 114, "dcm_clkin_iodly_muxinsel": 114, "dcm_clkin_iodly_muxinseldcm0": 114, "dcm_clkin_iodly_muxinseldcm1": 114, "dcm_clkin_iodly_muxout_sel": 114, "dcm_clkin_iodly_muxout_seldcm0": 114, "dcm_clkin_iodly_muxout_seldcm1": 114, "dcm_clklost_en": 114, "dcm_clklost_endcm0": 114, "dcm_clklost_endcm1": 114, "dcm_com_pwc_fb_en": 114, "dcm_com_pwc_fb_endcm0": 114, "dcm_com_pwc_fb_endcm1": 114, "dcm_com_pwc_fb_tap": 114, "dcm_com_pwc_ref_en": 114, "dcm_com_pwc_ref_endcm0": 114, "dcm_com_pwc_ref_endcm1": 114, "dcm_com_pwc_ref_tap": 114, "dcm_common_msb_sel": 114, "dcm_enabl": 50, "dcm_ext_fb_en": [102, 114], "dcm_ext_fb_endcm": 102, "dcm_ext_fb_endcm0": 114, "dcm_ext_fb_endcm1": 114, "dcm_lock_high": 102, "dcm_lock_high_b": 114, "dcm_lock_high_bdcm0": 114, "dcm_lock_high_bdcm1": 114, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pll_rst_dcm": 114, "dcm_pll_rst_dcmdcm0": 114, "dcm_pll_rst_dcmdcm1": 114, "dcm_powerdown_common_en_b": 114, "dcm_powerdown_common_en_bdcm0": 114, "dcm_powerdown_common_en_bdcm1": 114, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_reg_pwrd_cfg": 114, "dcm_reg_pwrd_cfgdcm0": 114, "dcm_reg_pwrd_cfgdcm1": 114, "dcm_scanmod": 114, "dcm_scanmodedcm0": 114, "dcm_scanmodedcm1": 114, "dcm_shutdown": [48, 84, 101], "dcm_trim_cal": 114, "dcm_unused_taps_powerdown": [102, 114], "dcm_unused_taps_powerdowndcm": 102, "dcm_use_reg_readi": 114, "dcm_use_reg_readydcm0": 114, "dcm_use_reg_readydcm1": 114, "dcm_vbg_pd": [102, 114], "dcm_vbg_sel": [102, 114], "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": [102, 114], "dcm_vreg_enabledcm": 102, "dcm_vreg_enabledcm0": 114, "dcm_vreg_enabledcm1": 114, "dcm_vreg_phase_margin": 102, "dcm_vsply_valid_acc": 114, "dcm_wait_pll": 114, "dcm_wait_plldcm0": 114, "dcm_wait_plldcm1": 114, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcmt_bot": 145, "dcmt_top": 145, "dcr_autolock_en": 125, "dcr_test": 125, "dcremacclk": 117, "dcy0": [60, 112, 128, 143], "dcy0slice0": [112, 128, 143], "dcy0slice1": [60, 143], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 123], "ddr00100": 123, "ddr01": 69, "ddr01100": 123, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": [108, 123], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 136], "dec_mcomma_detect_0": [66, 119, 120], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 119, "dec_mcomma_detect_0gtx_du": 120, "dec_mcomma_detect_1": [66, 119, 120], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 119, "dec_mcomma_detect_1gtx_du": 120, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 136, "dec_mcomma_detectgtx1": 136, "dec_mcomma_detectgtx2": 136, "dec_mcomma_detectgtx3": 136, "dec_pcomma_detect": [88, 89, 105, 136], "dec_pcomma_detect_0": [66, 119, 120], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 119, "dec_pcomma_detect_0gtx_du": 120, "dec_pcomma_detect_1": [66, 119, 120], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 119, "dec_pcomma_detect_1gtx_du": 120, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 136, "dec_pcomma_detectgtx1": 136, "dec_pcomma_detectgtx2": 136, "dec_pcomma_detectgtx3": 136, "dec_valid_comma_onli": [88, 89, 105, 136], "dec_valid_comma_only_0": [66, 119, 120], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 119, "dec_valid_comma_only_0gtx_du": 120, "dec_valid_comma_only_1": [66, 119, 120], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 119, "dec_valid_comma_only_1gtx_du": 120, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 136, "dec_valid_comma_onlygtx1": 136, "dec_valid_comma_onlygtx2": 136, "dec_valid_comma_onlygtx3": 136, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 139, 148, 151, 160, 169, 171], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "default10": 123, "default_idelay_valu": 123, "default_only1011": 113, "defin": 171, "definit": 151, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [161, 162, 163, 164, 165, 166], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_pt_ut": [161, 162, 163, 164, 165, 166], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "delai": [14, 44, 47, 74, 78, 118, 121, 134, 137, 139, 148, 149], "delay0": 157, "delay_bypass": 151, "delay_bypassbufio0": 151, "delay_bypassbufio1": 151, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_line1": 114, "delay_src": 123, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 123, "delayed_mem_ref0101": 145, "delayed_phase_ref11": 145, "delayed_phase_ref1100": 145, "delayed_ref01": 145, "delayed_ref0100": 145, "delayed_write0": 141, "delayed_write00": 126, "delaymux": 157, "delaymuxint": 157, "delaymuxiob2": 157, "delaymuxiob3": 157, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 118, 134, 148, 151, 160, 170, 171], "deriv": [12, 34, 56, 92, 169, 171], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 114, 129, 130, 144, 145, 160], "descript": [45, 99], "design": [12, 36, 58, 169, 171], "deskew_adjust": [54, 64, 90, 102, 114], "despit": 148, "destin": 36, "detail": [35, 58, 87, 96, 170], "determin": [12, 34, 35, 46, 82, 171], "dev_cap2_ari_forwarding_support": 152, "dev_cap2_ari_forwarding_supportedpci": 152, "dev_cap2_atomicop32_completer_support": 152, "dev_cap2_atomicop32_completer_supportedpci": 152, "dev_cap2_atomicop64_completer_support": 152, "dev_cap2_atomicop_routing_support": 152, "dev_cap2_cas128_completer_support": 152, "dev_cap2_cas128_completer_supportedpci": 152, "dev_cap2_endend_tlp_prefix_support": 152, "dev_cap2_endend_tlp_prefix_supportedpci": 152, "dev_cap2_extended_fmt_field_support": 152, "dev_cap2_ltr_mechanism_support": 152, "dev_cap2_ltr_mechanism_supportedpci": 152, "dev_cap2_max_endend_tlp_prefix": 152, "dev_cap2_no_ro_enabled_prpr_pass": 152, "dev_cap2_tph_completer_support": 152, "dev_cap_enable_slot_pwr_limit_scal": [140, 152], "dev_cap_enable_slot_pwr_limit_scalepci": [140, 152], "dev_cap_enable_slot_pwr_limit_valu": [140, 152], "dev_cap_endpoint_l0s_lat": [70, 140, 152], "dev_cap_endpoint_l1_lat": [70, 140, 152], "dev_cap_ext_tag_support": [70, 140, 152], "dev_cap_ext_tag_supportedpci": [140, 152], "dev_cap_function_level_reset_cap": [140, 152], "dev_cap_max_payload_support": [70, 140, 152], "dev_cap_phantom_functions_support": [70, 140, 152], "dev_cap_role_based_error": [70, 140, 152], "dev_cap_rsvd_14_12": [140, 152], "dev_cap_rsvd_17_16": [140, 152], "dev_cap_rsvd_31_29": [140, 152], "dev_control_aux_power_support": [140, 152], "dev_control_aux_power_supportedpci": 152, "dev_control_ext_tag_default": 152, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 121, 123, 137, 139, 149, 151, 159, 168, 170], "device_id": 140, "devicebram": 45, "devicecapabilityendpointl0slat": 124, "devicecapabilityendpointl1lat": 124, "devicedcm": [51, 52, 86], "deviceid": 124, "deviceiodelai": 123, "devicemmcm": 130, "devicepl": 114, "deviceserialnumb": 124, "devicevalu": [47, 61], "devoid": 148, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [120, 136], "dfe_cfg": 136, "dfe_cfg_0": 120, "dfe_cfg_1": 120, "dfe_drp_en": 136, "dfe_drp_engtx0": 136, "dfe_drp_engtx1": 136, "dfe_drp_engtx2": 136, "dfe_drp_engtx3": 136, "dfe_train_ctrl_lane0": 135, "dfe_train_ctrl_lane1": 135, "dfe_train_ctrl_lane2": 135, "dfe_train_ctrl_lane3": 135, "dff": [14, 36, 171], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dff1": 15, "dff_latch": 128, "dff_latchslice0": 128, "dffce": 171, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dffinit": [112, 128, 143], "dffinitslice0": [112, 128, 143], "dffmux": [60, 112, 128, 143], "dffmuxslice1": 60, "dffsr": [112, 128, 143], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 143, "dffsrslice1": 128, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": [102, 114], "dfs_ave_freq_sample_interv": [102, 114], "dfs_c": [52, 64], "dfs_cfg_bypass": 114, "dfs_cfg_bypassdcm0": 114, "dfs_cfg_bypassdcm1": 114, "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_custom_fast_sync": 114, "dfs_early_lock": [102, 114], "dfs_early_lockdcm": 102, "dfs_early_lockdcm0": 114, "dfs_early_lockdcm1": 114, "dfs_en": 114, "dfs_en_relrst": 102, "dfs_en_relrst_b": 114, "dfs_en_relrst_bdcm0": 114, "dfs_en_relrst_bdcm1": 114, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_endcm0": 114, "dfs_endcm1": 114, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_fast_upd": 114, "dfs_fast_updatedcm0": 114, "dfs_fast_updatedcm1": 114, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102, 114], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": [64, 114], "dfs_frequency_modedcm1": [64, 114], "dfs_hardsync": 102, "dfs_hardsync_b": 114, "dfs_hf_trim_cal": 114, "dfs_jf_lower_limit": 114, "dfs_mpw_high": 114, "dfs_mpw_highdcm0": 114, "dfs_mpw_highdcm1": 114, "dfs_mpw_low": 114, "dfs_mpw_lowdcm0": 114, "dfs_mpw_lowdcm1": 114, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_osc_on_fx": 114, "dfs_osc_on_fxdcm0": 114, "dfs_osc_on_fxdcm1": 114, "dfs_oscillator_mod": [102, 114], "dfs_oscillator_modedcm0": 114, "dfs_oscillator_modedcm1": 114, "dfs_output_psdly_on_concur": 114, "dfs_output_psdly_on_concurdcm0": 114, "dfs_output_psdly_on_concurdcm1": 114, "dfs_pwrd_clkin_stop_b": 114, "dfs_pwrd_clkin_stop_bdcm0": 114, "dfs_pwrd_clkin_stop_bdcm1": 114, "dfs_pwrd_clkin_stop_sticky_b": 114, "dfs_pwrd_clkin_stop_sticky_bdcm0": 114, "dfs_pwrd_clkin_stop_sticky_bdcm1": 114, "dfs_pwrd_reply_times_out_b": 114, "dfs_pwrd_reply_times_out_bdcm0": 114, "dfs_pwrd_reply_times_out_bdcm1": 114, "dfs_ref_on_fx": 114, "dfs_ref_on_fxdcm0": 114, "dfs_ref_on_fxdcm1": 114, "dfs_skip_fin": 102, "dfs_skip_finedcm": 102, "dfs_spare": 102, "dfs_sync_to_dl": 114, "dfs_sync_to_dlldcm0": 114, "dfs_sync_to_dlldcm1": 114, "dfs_synth_clock_spe": 114, "dfs_synth_fast_synch": 114, "dfs_taptrim": 114, "dfs_tp_sel": 102, "dfs_tp_seldcm": 102, "dfs_trackmod": 102, "dfs_trackmodedcm": 102, "dfs_tweak": 114, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 46, 81, 82, 96, 154], "di0": [102, 154], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 154], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "di_dur": 145, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 148, 151, 160], "dif": [46, 82], "dif_mux": [37, 46, 82, 99], "dif_muxslice0": 99, "diff010": [108, 123], "diff10": [74, 79], "diff101": [57, 93], "diff110": 57, "diff_hp10010": 139, "diff_lp00010": 139, "differ": [16, 35, 36, 46, 55, 82, 91, 151, 169, 171], "differenti": [14, 56, 108, 123, 139, 151], "dig": [46, 82], "dig_mux": [37, 46, 82, 99], "dig_muxslice0": 99, "dig_muxslice2": 99, "digit": [44, 54, 55, 56, 67, 90, 91, 92, 106], "digrx_fwdclk": 105, "digrx_sync_mod": 105, "digrx_sync_modegt11a": 105, "digrx_sync_modegt11b": 105, "dimens": 58, "dimension": 159, "din": [139, 151], "din0": 72, "din0000": 72, "din0001": 72, "din0int": 72, "din1": 72, "din10": 72, "din1000": 72, "din10000": 72, "din10001": 72, "din1001": 72, "din10int": 72, "din11": 72, "din11001": 72, "din11010": 72, "din11int": 72, "din12": 72, "din12010": 72, "din12011": 72, "din12int": 72, "din13": 72, "din13010": 72, "din13011": 72, "din13int": 72, "din14": 72, "din14010": 72, "din14011": 72, "din14int": 72, "din15": 72, "din15000": 72, "din15011": 72, "din15int": 72, "din16": 72, "din16110": 72, "din16111": 72, "din16int": 72, "din17": 72, "din17100": 72, "din17111": 72, "din17int": 72, "din18": 72, "din18100": 72, "din18101": 72, "din18int": 72, "din19": 72, "din19100": 72, "din19101": 72, "din19int": 72, "din1int": 72, "din2": 72, "din20": 72, "din2000": 72, "din2001": 72, "din20100": 72, "din20101": 72, "din20int": 72, "din21": 72, "din21101": 72, "din21110": 72, "din21int": 72, "din22": 72, "din22110": 72, "din22111": 72, "din22int": 72, "din23": 72, "din23110": 72, "din23111": 72, "din23int": 72, "din24": 72, "din24110": 72, "din24111": 72, "din24int": 72, "din25": 72, "din25100": 72, "din25111": 72, "din25int": 72, "din26": 72, "din26100": 72, "din26101": 72, "din26int": 72, "din27": 72, "din27100": 72, "din27101": 72, "din27int": 72, "din28": 72, "din28100": 72, "din28101": 72, "din28int": 72, "din29": 72, "din29101": 72, "din29110": 72, "din29int": 72, "din2int": 72, "din3": 72, "din30": 72, "din3001": 72, "din3010": 72, "din30110": 72, "din30111": 72, "din30int": 72, "din31": 72, "din31110": 72, "din31111": 72, "din31int": 72, "din3int": 72, "din4": 72, "din4010": 72, "din4011": 72, "din4int": 72, "din5": 72, "din5010": 72, "din5011": 72, "din5int": 72, "din6": 72, "din6010": 72, "din6011": 72, "din6int": 72, "din7": 72, "din7000": 72, "din7011": 72, "din7int": 72, "din8": 72, "din8000": 72, "din8001": 72, "din8int": 72, "din9": 72, "din9000": 72, "din9001": 72, "din9int": 72, "dinpin": [98, 111, 127], "dip": [81, 96], "dipa": 96, "dipb": 96, "direct": [36, 55, 81, 91], "direct0": [45, 53, 65, 103, 116, 132, 136, 147], "direct_path_cntrl": [130, 145], "direct_path_cntrlmmcm": 145, "direct_path_cntrlmmcm0": 130, "direct_path_cntrlmmcm1": 130, "direct_path_cntrlpl": 145, "directli": [14, 17, 35, 36, 46, 58, 81, 82, 91, 160, 171], "dis_tstblclamp": 141, "dis_tstfiforst": [126, 141], "dis_vgg_reg": [131, 146], "disabl": [36, 171], "disable00": 146, "disable111": 155, "disable_aspm_l1_tim": [140, 152], "disable_aspm_l1_timerpci": [140, 152], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 140, 152], "disable_err_msg": 152, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 140, 152], "disable_id_checkpci": [140, 152], "disable_jtag": [127, 142], "disable_lane_revers": [140, 152], "disable_lane_reversalpci": 140, "disable_locked_filt": 152, "disable_ppm_filt": 152, "disable_ppm_filterpci": 152, "disable_rx_poisoned_resp": 152, "disable_rx_poisoned_resppci": 152, "disable_rx_tc_filt": [140, 152], "disable_scrambl": [70, 140, 152], "disable_scramblingpci": 152, "disable_seq_match": 145, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 171], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 134, 148], "distrubut": 134, "div12110": 69, "div2001": 69, "div201": [69, 145], "div4010": 69, "div410": [69, 145], "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divclk_edg": [130, 145], "divclk_edgemmcm": 145, "divclk_edgemmcm0": 130, "divclk_edgemmcm1": 130, "divclk_edgepl": 145, "divclk_ht": [130, 145], "divclk_lt": [130, 145], "divclk_nocount": [130, 145], "divclk_nocountmmcm": 145, "divclk_nocountmmcm0": 130, "divclk_nocountmmcm1": 130, "divclk_nocountpl": 145, "divid": [11, 12, 58, 61, 104, 118, 134, 148, 159, 171], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 169], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_cfg0": 135, "dll_cfg1": 135, "dll_clkfb_stopped_pwrd_en_b": 114, "dll_clkfb_stopped_pwrd_en_bdcm0": 114, "dll_clkfb_stopped_pwrd_en_bdcm1": 114, "dll_clkin_stopped_pwrd_en_b": 114, "dll_clkin_stopped_pwrd_en_bdcm0": 114, "dll_clkin_stopped_pwrd_en_bdcm1": 114, "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": [102, 114], "dll_deskew_lock_by1": [102, 114], "dll_deskew_lock_by1dcm": 102, "dll_deskew_lock_by1dcm0": 114, "dll_deskew_lock_by1dcm1": 114, "dll_deskew_maxtap": [102, 114], "dll_deskew_mintap": [102, 114], "dll_enabl": [51, 52, 64, 76, 86], "dll_enabledcm": [51, 52], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_etpp_hold": 114, "dll_etpp_holddcm0": 114, "dll_etpp_holddcm1": 114, "dll_fdbklost_en": 114, "dll_fdbklost_endcm0": 114, "dll_fdbklost_endcm1": 114, "dll_frequency_mod": [51, 52, 64, 86, 102, 114], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": [102, 114], "dll_pd_dly_sel": 102, "dll_period_lock_by1": [102, 114], "dll_period_lock_by1dcm": 102, "dll_period_lock_by1dcm0": 114, "dll_period_lock_by1dcm1": 114, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": [102, 114], "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": [102, 114], "dll_phase_shift_lock_by1": [102, 114], "dll_phase_shift_lock_by1dcm": 102, "dll_phase_shift_lock_by1dcm0": 114, "dll_phase_shift_lock_by1dcm1": 114, "dll_pwrd_on_scanmode_b": 114, "dll_pwrd_on_scanmode_bdcm0": 114, "dll_pwrd_on_scanmode_bdcm1": 114, "dll_pwrd_sticky_b": 114, "dll_pwrd_sticky_bdcm0": 114, "dll_pwrd_sticky_bdcm1": 114, "dll_settle_tim": [102, 114], "dll_spare": 102, "dll_synth_clock_spe": 114, "dll_tapinit_ctl": 114, "dll_test_mux_sel": [102, 114], "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dll_zd1_en": 114, "dll_zd1_endcm0": 114, "dll_zd1_endcm1": 114, "dll_zd1_jf_overflow_hold": 114, "dll_zd1_jf_overflow_holddcm0": 114, "dll_zd1_jf_overflow_holddcm1": 114, "dll_zd1_phase_sel_init": 114, "dll_zd1_pwc_en": 114, "dll_zd1_pwc_endcm0": 114, "dll_zd1_pwc_endcm1": 114, "dll_zd1_pwc_tap": 114, "dll_zd1_tap_init": 114, "dll_zd2_en": [102, 114], "dll_zd2_endcm": 102, "dll_zd2_endcm0": 114, "dll_zd2_endcm1": 114, "dll_zd2_jf_overflow_hold": 114, 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"doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 72, "doa6": 72, "doa6int": 72, "doa7": 72, "doa8": 72, "doa8int": 72, "doa9": 72, "doa9int": 72, "doa_reg": [45, 59, 96], "doa_reg_l": [110, 126, 141], "doa_reg_u": [110, 126, 141], "dob": [81, 96], "dob0": 72, "dob0int": 72, "dob1": 72, "dob10": [72, 96], "dob10int": 72, "dob11": [72, 96], "dob11int": 72, "dob12": 72, "dob12int": 72, "dob13": 72, "dob13int": 72, "dob14": 72, "dob14int": 72, "dob15": 72, "dob15int": 72, "dob1int": 72, "dob2": 72, "dob3": 72, "dob4": [72, 96], "dob4int": 72, "dob5": [72, 96], "dob6": [72, 96], "dob6int": 72, "dob7": [72, 96], "dob8": [72, 96], "dob8int": 72, "dob9": [72, 96], "dob9int": 72, "dob_reg": [45, 59, 96], "dob_reg_l": [110, 126, 141], "dob_reg_u": [110, 126, 141], "document": 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[66, 102, 105, 114, 119, 120, 130, 136, 145], "drp47_mask": [102, 105], "drp48": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp48_mask": [102, 105], "drp48_maskdcm": 102, "drp49": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp49_mask": [102, 105], "drp49_maskdcm": 102, "drp4a": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4a_mask": [102, 105], "drp4b": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4b_mask": [102, 105], "drp4c": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4c_mask": [102, 105], "drp4c_maskdcm": 102, "drp4d": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4d_mask": [102, 105], "drp4d_maskdcm": 102, "drp4e": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4e_mask": [102, 105], "drp4f": [66, 102, 105, 114, 119, 120, 130, 136, 145], "drp4f_mask": [102, 105], "drp50": [66, 102, 105, 114, 130, 145], "drp50_mask": [102, 105], "drp50_maskdcm": 102, "drp51": [66, 102, 105, 114, 130, 145], "drp51_mask": [102, 105], "drp51_maskdcm": 102, "drp52": [66, 102, 105, 114, 130, 145], "drp52_mask": [102, 105], "drp52_maskdcm": 102, "drp53": [66, 102, 105, 114, 130, 145], "drp53_mask": [102, 105], "drp53_maskdcm": 102, "drp54": [66, 102, 105, 114, 130, 145], "drp54_mask": [102, 105], "drp54_maskdcm": 102, "drp55": [66, 102, 105, 114, 130, 145], "drp55_mask": [102, 105], "drp55_maskdcm": 102, "drp56": [66, 102, 105, 114, 130, 145], "drp56_mask": [102, 105], "drp56_maskdcm": 102, "drp57": [66, 102, 105, 114, 130, 145], "drp57_mask": [102, 105], "drp57_maskdcm": 102, "drp58": [66, 102, 105, 130, 145], "drp58_mask": [102, 105], "drp58_maskdcm": 102, "drp59": [66, 102, 105, 130, 145], "drp59_mask": [102, 105], "drp59_maskdcm": 102, "drp5a": [66, 102, 105, 130, 145], "drp5a_mask": [102, 105], "drp5a_maskdcm": 102, "drp5b": [66, 102, 105, 130, 145], "drp5b_mask": [102, 105], "drp5b_maskdcm": 102, "drp5c": [66, 102, 105, 130, 145], "drp5c_mask": [102, 105], "drp5c_maskdcm": 102, "drp5d": [66, 102, 105, 130, 145], "drp5d_mask": [102, 105], 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145], "drp70_mask": 105, "drp71": [66, 105, 130, 145], "drp71_mask": 105, "drp72": [66, 105, 130, 145], "drp72_mask": 105, "drp73": [66, 105, 130, 145], "drp73_mask": 105, "drp74": [66, 105, 130, 145], "drp74_mask": 105, "drp75": [66, 105, 130, 145], "drp75_mask": 105, "drp76": [66, 105, 130, 145], "drp76_mask": 105, "drp77": [66, 105, 130, 145], "drp77_mask": 105, "drp78": [66, 105, 130, 145], "drp78_mask": 105, "drp79": [66, 105, 130, 145], "drp79_mask": 105, "drp7a": [66, 105, 130, 145], "drp7a_mask": 105, "drp7b": [66, 105, 130, 145], "drp7b_mask": 105, "drp7c": [66, 105, 130, 145], "drp7c_mask": 105, "drp7d": [66, 105, 130, 145], "drp7d_mask": 105, "drp7e": [66, 105, 130, 145], "drp7e_mask": 105, "drp7f": [66, 105, 130, 145], "drp7f_mask": 105, "drp_mask": 113, "drp_mask_abov": 129, "drp_mask_above_l": 144, "drp_mask_above_r": 144, "drp_mask_below": 129, "drp_mask_below_l": 144, "drp_mask_below_lhclk": 144, "drp_mask_below_r": 144, "drp_mask_below_rhclk": 144, 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82, 99], "dxmuxslice1": [37, 46, 73], "dxmuxslice3": [37, 46], "dymux": [37, 46, 73, 82, 99], "dymuxslice0": 73, "dymuxslice1": [37, 46, 73], "dymuxslice3": [37, 46], "dynamic1": [71, 114, 136], "dynamic_en": 139, "dynamic_enabledci": 139, "e": [55, 78, 87, 154, 157], "e0": [38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 155, 157], "e000": 154, "e00000010001": 107, "e0000001010": 79, "e000001": [42, 55], "e0000010010": 79, "e00001": [42, 55], "e0000101": 91, "e0001": 72, "e00010": [42, 55], "e000100000001": 91, "e0001000000010": 91, "e000100000010": 91, "e000100000100": 91, "e000100001000": 91, "e0001000010000": 91, "e00010001": [91, 107], "e00011010": 55, "e001000000": 73, "e0010000000010": 107, "e001000000010": 91, "e0010000000100": [91, 107], "e0010000001000": 107, "e00100001": [91, 107], "e0010001": [91, 107], "e0010010": 107, "e0011": 72, "e00110000": 55, "e0011111111": 155, "e0100000000010": 107, "e0100000000100": 91, "e0100000001000": 107, "e0100000010": 79, "e010001": [42, 55], "e0100010": 91, "e01001": [42, 55], "e01101000": [42, 55], "e01110001": 55, "e1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 24, 25, 72, 73, 79, 154, 157, 162, 163, 164, 165, 166], "e100": 154, "e1000000000100": 107, "e1000000010": 79, "e10000010001": 107, "e10000100": [42, 55], "e1001": 72, "e101": 154, "e10100": 72, "e10110": 72, "e1011110": 157, "e10gbasekr_ld_coeff_upd_lane0": 135, "e10gbasekr_ld_coeff_upd_lane1": 135, "e10gbasekr_ld_coeff_upd_lane2": 135, "e10gbasekr_ld_coeff_upd_lane3": 135, "e10gbasekr_lp_coeff_upd_lane0": 135, "e10gbasekr_lp_coeff_upd_lane1": 135, "e10gbasekr_lp_coeff_upd_lane2": 135, "e10gbasekr_lp_coeff_upd_lane3": 135, "e10gbasekr_pma_ctrl_lane0": 135, "e10gbasekr_pma_ctrl_lane1": 135, "e10gbasekr_pma_ctrl_lane2": 135, "e10gbasekr_pma_ctrl_lane3": 135, "e10gbasekx_ctrl_lane0": 135, "e10gbasekx_ctrl_lane1": 135, "e10gbasekx_ctrl_lane2": 135, "e10gbasekx_ctrl_lane3": 135, "e10gbaser_pcs_cfg_lane0": 135, "e10gbaser_pcs_cfg_lane1": 135, "e10gbaser_pcs_cfg_lane2": 135, "e10gbaser_pcs_cfg_lane3": 135, "e10gbaser_pcs_seeda0_lane0": 135, "e10gbaser_pcs_seeda0_lane1": 135, "e10gbaser_pcs_seeda0_lane2": 135, "e10gbaser_pcs_seeda0_lane3": 135, "e10gbaser_pcs_seeda1_lane0": 135, "e10gbaser_pcs_seeda1_lane1": 135, "e10gbaser_pcs_seeda1_lane2": 135, "e10gbaser_pcs_seeda1_lane3": 135, "e10gbaser_pcs_seeda2_lane0": 135, "e10gbaser_pcs_seeda2_lane1": 135, "e10gbaser_pcs_seeda2_lane2": 135, "e10gbaser_pcs_seeda2_lane3": 135, "e10gbaser_pcs_seeda3_lane0": 135, "e10gbaser_pcs_seeda3_lane1": 135, "e10gbaser_pcs_seeda3_lane2": 135, "e10gbaser_pcs_seeda3_lane3": 135, "e10gbaser_pcs_seedb0_lane0": 135, "e10gbaser_pcs_seedb0_lane1": 135, "e10gbaser_pcs_seedb0_lane2": 135, "e10gbaser_pcs_seedb0_lane3": 135, "e10gbaser_pcs_seedb1_lane0": 135, "e10gbaser_pcs_seedb1_lane1": 135, "e10gbaser_pcs_seedb1_lane2": 135, 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"e13101": 72, "e14": [2, 3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e14010": 72, "e14101": 72, "e15": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e15101": 72, "e16": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e16100": 72, "e16111": 72, "e17": [24, 25, 72, 73, 79, 164], "e17110": 72, "e17111": 72, "e18": [24, 25, 72, 73, 79, 164], "e18000": 72, "e18111": 72, "e19": [6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e19111": 72, "e1int": 154, "e2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e20": [6, 7, 24, 72, 73, 79, 165, 166], "e2001": 72, "e20101": 72, "e2011": 72, "e20110": 72, "e21": [6, 7, 72, 73, 79, 165, 166], "e21100": 72, "e2110111111": 155, "e21110": 72, "e22": [6, 7, 72, 73, 79, 165, 166], "e22100": 72, "e22110": 72, "e23": [22, 23, 72, 73, 79], "e23110": 72, "e24": [22, 23], "e25": [22, 23], "e26": [22, 23], "e3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e3001": 72, "e3111011111": 155, "e4": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e4000": 72, "e401": 155, "e4010": 72, "e5": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e500": 155, "e5011": 72, "e6": [2, 3, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 155, 157, 161, 162, 164, 165, 166], "e6001": 72, "e601": 155, "e6011": 72, "e6int": 157, "e7": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e700": 155, "e7011": 72, "e7int": 154, "e8": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 162, 164, 165, 166], "e8001": 72, "e8011": 72, "e8int": 154, "e9": [2, 3, 6, 7, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 164, 165, 166], "e9100": 72, "e9111": 72, "each": [14, 15, 16, 34, 35, 36, 42, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 171], "earlier": [34, 104, 169], "easi": [55, 91], "ebai": 35, "ecc": 106, "edg": [14, 55, 58, 87, 91, 118, 123, 134, 148], "ee0": [68, 138, 150], "ee1": [68, 138, 150], "ee2": [68, 138, 150], "ee3": [68, 138, 150], "efar0": [131, 146], "effect": [35, 36, 46, 81, 82, 91, 148, 171], "efuse1": [62, 115, 131, 146], "eg": [12, 55, 58, 91], "eight": 91, "eighth1011": 69, "eighth2111": 69, "eint": 154, "either": [14, 35, 36, 58, 81, 82, 134, 148, 160, 170, 171], "el0": [68, 122, 138, 150], "el1": [68, 122, 138, 150], "el2": [68, 122, 138, 150], "el3": [68, 138, 150], "electron": [159, 171], "element": [17, 160], "elimin": 58, "els": [15, 16, 36, 171], "em_cclk": 151, "emac": [117, 118, 133, 134], "emac0_1000basex_en": 117, "emac0_addrfilter_en": 117, "emac0_bytephi": 117, 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96], "init_4": [109, 111, 127, 142], "init_40": [109, 111, 127, 142], "init_41": [109, 111, 127, 142], "init_42": [109, 111, 127, 142], "init_43": [109, 111, 127, 142], "init_44": [109, 111, 127, 142], "init_45": [109, 111, 127, 142], "init_46": [109, 111, 127, 142], "init_47": [109, 111, 127, 142], "init_48": [109, 111, 127, 142], "init_49": [109, 111, 127, 142], "init_4a": [109, 111, 127, 142], "init_4b": [109, 111, 127, 142], "init_4c": [109, 111, 127, 142], "init_4d": [109, 111, 127, 142], "init_4f": [109, 111, 127, 142], "init_5": [109, 142], "init_50": [109, 111, 127, 142], "init_51": [109, 111, 127, 142], "init_52": [109, 111, 127, 142], "init_53": [109, 111, 127, 142], "init_54": [109, 111, 127, 142], "init_55": [109, 111, 127, 142], "init_56": [109, 111, 127, 142], "init_57": [109, 111, 127, 142], "init_58": [109, 142], "init_59": [109, 142], "init_5a": [109, 142], "init_5b": [109, 142], "init_5c": [109, 142], "init_5d": [109, 142], "init_5f": [109, 142], "init_6": 109, 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"init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_outbufhce_r0": 130, "init_outbufhce_r10": 130, "init_outbufhce_r2": 130, "init_outbufhce_r4": 130, "init_outbufhce_r6": 130, "init_outbufhce_r8": 130, "init_outbufmrce1": 145, "init_outmmcm0": 130, "init_outmmcm1": 130, "init_rank1_parti": [108, 123], "init_rank2": [108, 123], "init_rank3": [108, 123], "init_signals_error": [131, 146], "init_skip": 62, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 171], "initp_xx": [81, 96], "initpin": [98, 111, 127, 142], "initpinmisc": 111, "initx": 73, "initxint": 73, "initxslice1": 73, "inityint": 73, "inmode0": [132, 147], "inmode1": [132, 147], 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87, 90, 92, 96, 104, 106, 118, 121, 134, 137, 139, 148, 149, 171], "interconnect_imask": 125, "interconnect_tmpl_sel": 125, "intereconnect": 148, "interfac": [11, 33, 41, 52, 54, 58, 64, 67, 87, 90, 106, 168], "interface_typ": [108, 123], "interface_typeilogic0": 108, "interface_typeilogic1": 108, "interfer": [46, 82], "interleav": 16, "intern": [36, 56, 92, 96, 148, 170], "internal1": [131, 146], "internal_vref": [113, 139], "internalclk0": [49, 62], "interp_en": [130, 145], "interp_test": 145, "interpos": 148, "interpret": 17, "interrupt": [35, 91], "interrupt_pin": [140, 152], "interrupt_stat_auto": 152, "interrupt_stat_autopci": 152, "interruptpin": 124, "intersect": [38, 47, 55, 58, 87, 104, 118, 134, 148], "intest": [13, 35, 170], "intf": [104, 107, 118, 121, 134, 137, 148, 149], "intosc00": 76, "intro": [41, 54, 67, 78, 106, 121, 137, 149, 156], "introduc": [58, 96, 148], "introduct": [11, 33, 44, 54, 90, 168], "inv": [15, 36, 37, 42, 43, 46, 47, 51, 52, 55, 57, 59, 60, 61, 64, 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23, 24, 25, 163, 164, 165, 166], "p104": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p105": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p106": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p107": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p108": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p109": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p11": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p110": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p111": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p112": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p113": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p114": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p115": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p116": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p117": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p120": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p121": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p122": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p123": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p124": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p125": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p126": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p127": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p128": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p129": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p13": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p130": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p131": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p132": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p133": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p134": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p135": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p136": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p137": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p138": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p139": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p14": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p140": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p141": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p142": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p143": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p144": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 163, 164, 165, 166], "p145": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p146": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p147": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p148": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p149": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 166], "p15": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p150": [3, 6, 7, 18, 19, 22, 23, 24, 25, 164, 165, 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25, 164, 165, 166], "p1cmdclk": 69, "p1cmden": 69, "p1rdclk": 69, "p1rden": 69, "p1wrclk": 69, "p1wren": 69, "p2": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 161, 162, 163, 164, 165, 166], "p20": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p200": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p201": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p202": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p203": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p204": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p205": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p206": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p207": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p208": [3, 6, 7, 22, 23, 24, 25, 164, 165, 166], "p209": [3, 6, 7], "p21": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p210": [3, 6, 7], "p211": [3, 6, 7], "p212": [3, 6, 7], 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6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p250": [6, 7], "p251": [6, 7], "p252": [6, 7], "p253": [6, 7], "p254": [6, 7], "p255": [6, 7], "p256": [6, 7], "p257": [6, 7], "p258": [6, 7], "p259": [6, 7], "p26": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p260": [6, 7], "p261": [6, 7], "p262": [6, 7], "p263": [6, 7], "p264": [6, 7], "p265": [6, 7], "p266": [6, 7], "p267": [6, 7], "p268": [6, 7], "p269": [6, 7], "p27": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p270": [6, 7], "p271": [6, 7], "p272": [6, 7], "p273": [6, 7], "p274": [6, 7], "p275": [6, 7], "p276": [6, 7], "p277": [6, 7], "p278": [6, 7], "p279": [6, 7], "p28": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p280": [6, 7], "p281": [6, 7], "p282": [6, 7], "p283": [6, 7], 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21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p3clk": 69, "p3cmdclk": 69, "p3cmden": 69, "p3en": 69, "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p4clk": 69, "p4cmdclk": 69, "p4cmden": 69, "p4en": 69, "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p5clk": 69, "p5cmdclk": 69, "p5cmden": 69, "p5en": 69, "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 162, 163, 164, 165, 166], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p_d": 81, "packag": [11, 17, 33, 36, 56, 148, 151, 160, 168, 170], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 123, 139, 151, 160, 169, 171], "pair": [17, 58, 82, 96, 104, 108, 123, 139, 148, 151, 160], "parallel": [16, 108, 123, 139, 151], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 123, 148, 161, 162, 163, 164, 165, 166, 168, 170], "partial": [34, 81, 96, 170], "particip": 36, "particular": [17, 160], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 134, 148, 154, 155, 157, 158], "pass0": [64, 71, 114], "pass00000000": 102, "pass00000000000001": 113, "pass00000000001": 113, "pass00000001": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 116, "path": [36, 81], "pattern": [87, 116, 132, 147], "pattern0": [116, 132, 147], "pbbaseptr": 124, "pbcapabilitydw0basepow": 124, "pbcapabilitydw0datascal": 124, "pbcapabilitydw0pmst": 124, "pbcapabilitydw0pmsubst": 124, "pbcapabilitydw0powerrail": 124, "pbcapabilitydw0typ": 124, "pbcapabilitydw1basepow": 124, "pbcapabilitydw1datascal": 124, "pbcapabilitydw1pmst": 124, "pbcapabilitydw1pmsubst": 124, "pbcapabilitydw1powerrail": 124, "pbcapabilitydw1typ": 124, "pbcapabilitydw2basepow": 124, "pbcapabilitydw2datascal": 124, "pbcapabilitydw2pmst": 124, "pbcapabilitydw2pmsubst": 124, "pbcapabilitydw2powerrail": 124, "pbcapabilitydw2typ": 124, "pbcapabilitydw3basepow": 124, "pbcapabilitydw3datascal": 124, "pbcapabilitydw3pmst": 124, "pbcapabilitydw3pmsubst": 124, "pbcapabilitydw3powerrail": 124, "pbcapabilitydw3typ": 124, "pbcapabilitynextptr": 124, "pbcapabilitysystemalloc": 124, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 161, 162, 169], "pc84": [18, 29, 34], "pci": [44, 56, 58, 67, 78, 90, 91, 92, 121, 137, 149], "pci000": 91, "pci100": 91, "pci33_3": [57, 79], "pci33_30": [57, 93], "pci33_300": [57, 93], "pci33_30000": 93, "pci33_300000": [57, 93], "pci33_3000000": 123, "pci33_3000000000000": 123, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 123, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 123, "pci66_3000000000000": 123, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 123, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, "pci_clampiob0": 57, "pci_clampiob1": 57, "pci_clampiob3": 57, "pci_clampiob4": 57, "pci_delai": 80, "pci_express_mod": 136, "pci_express_mode_0": [66, 119, 120], "pci_express_mode_1": [66, 119, 120], "pci_express_mode_1gtp": 66, "pci_input": 57, "pci_inputiob1": 57, "pci_inputiob2": 57, "pci_inputiob3": 57, "pci_inputiob4": 57, "pci_inputiob5": 57, "pcice10": 57, "pcice_mux": 57, "pcie": [70, 118, 124, 134, 140, 148, 152], "pcie0": [66, 119, 120], "pcie2": 148, "pcie3": [148, 153], "pcie_base_ptr": [140, 152], "pcie_cap_capability_id": [140, 152], "pcie_cap_capability_vers": [70, 140, 152], "pcie_cap_device_port_typ": [70, 140, 152], "pcie_cap_int_msg_num": [70, 140], "pcie_cap_nextptr": [140, 152], "pcie_cap_on": [140, 152], "pcie_cap_onpci": [140, 152], "pcie_cap_rsvd_15_14": [140, 152], "pcie_cap_slot_impl": [70, 140, 152], "pcie_gener": 70, "pcie_l": [148, 149], "pcie_r": [148, 149], "pcie_revis": [140, 152], "pciecapabilityintmsgnum": 124, "pciecapabilitynextptr": 124, "pciecapabilityslotimpl": 124, "pcierevis": 124, "pcierevisionpci": 124, "pcilog": [58, 80, 87, 90, 91], "pcilogics": [47, 58, 67], "pcix": 57, "pcix0": [57, 93], "pcix00": [93, 108], "pcix000000": 123, "pcix000001": 57, "pcix0011": 93, "pcix001111100000": 123, "pcix0100101011": 93, "pcix0110001100": [108, 123], "pcix011001100": 93, "pcix01111": 93, "pcix01111011": 108, "pcix100110": 57, "pcix111110": 57, "pcix11111111": 57, "pcix66_3": 79, "pcix66_30111": 79, "pcix66_3101001100": 79, "pcomma_10b_valu": [88, 89, 136], "pcomma_10b_value_0": [66, 119, 120], "pcomma_10b_value_1": [66, 119, 120], "pcomma_detect": [88, 89, 105, 136], "pcomma_detect_0": [66, 119, 120], "pcomma_detect_1": [66, 119, 120], "pcomma_detect_1gtp": 66, "pcomma_detectgtx0": 136, "pcomma_detectgtx1": 136, "pcomma_detectgtx2": 136, "pcomma_detectgtx3": 136, "pcomma_valu": 105, "pcs0": [66, 119, 120], "pcs10": 136, "pcs_ability_lane0": 135, "pcs_ability_lane1": 135, "pcs_ability_lane2": 135, "pcs_ability_lane3": 135, "pcs_bit_slip": 105, "pcs_com_cfg": 119, "pcs_ctrl1_lane0": 135, "pcs_ctrl1_lane1": 135, "pcs_ctrl1_lane2": 135, "pcs_ctrl1_lane3": 135, "pcs_ctrl2_lane0": 135, "pcs_ctrl2_lane1": 135, "pcs_ctrl2_lane2": 135, "pcs_ctrl2_lane3": 135, "pcs_misc_cfg_0_lane0": 135, "pcs_misc_cfg_0_lane1": 135, "pcs_misc_cfg_0_lane2": 135, "pcs_misc_cfg_0_lane3": 135, "pcs_misc_cfg_1_lane0": 135, "pcs_misc_cfg_1_lane1": 135, "pcs_misc_cfg_1_lane2": 135, "pcs_misc_cfg_1_lane3": 135, "pcs_mode_lane0": 135, "pcs_mode_lane1": 135, "pcs_mode_lane2": 135, "pcs_mode_lane3": 135, "pcs_reset_1_lane0": 135, "pcs_reset_1_lane1": 135, "pcs_reset_1_lane2": 135, "pcs_reset_1_lane3": 135, "pcs_reset_lane0": 135, "pcs_reset_lane1": 135, "pcs_reset_lane2": 135, "pcs_reset_lane3": 135, "pcs_type_lane0": 135, "pcs_type_lane1": 135, "pcs_type_lane2": 135, "pcs_type_lane3": 135, "pd_revers": 145, "pdelidle_drp_en": 136, "pdelidle_drp_en_0": 66, "pdelidle_drp_en_1": 66, "pdelidle_drp_en_1gtp": 66, "pdrive": [57, 79, 93, 108, 123, 139], "pdriveiostd": [57, 79, 93, 108, 123, 139], "pdstatuspin": 76, "pdstatuspinmisc": 76, "pent": 122, "pent00010100": 122, "pent00011000": 122, "pent00100100": 122, "pent00101000": 122, "pent01000100": 122, "pent01001000": 122, "pent10000100": 122, "pent10001000": 122, "per": [12, 14, 17, 33, 34, 35, 36, 46, 55, 56, 58, 81, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 170, 171], "perf0": [130, 139, 145, 151], "perf0001": 136, "perf01": 139, "perf0_il": 130, "perf0_ilmmcm0": 130, "perf0_ilmmcm1": 130, "perf0_ir": 130, "perf0_irmmcm0": 130, "perf0_irmmcm1": 130, "perf0_ol": 130, "perf0_olmmcm0": 130, "perf0_olmmcm1": 130, "perf0_or": 130, "perf0_ormmcm0": 130, "perf0_ormmcm1": 130, "perf0hclk_ioi": 139, "perf1": [130, 139, 145, 151], "perf1011": 136, "perf11": 139, "perf1_il": 130, "perf1_ilmmcm0": 130, "perf1_ilmmcm1": 130, "perf1_ir": 130, "perf1_irmmcm0": 130, "perf1_irmmcm1": 130, "perf1_ol": 130, "perf1_olmmcm0": 130, "perf1_olmmcm1": 130, "perf1_or": 130, "perf1_ormmcm0": 130, "perf1_ormmcm1": 130, "perf1mmcm": 145, "perf2": [130, 139, 145, 151], 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"pf0_ari_cap_next_func": 153, "pf0_ari_cap_nextptr": 153, "pf0_ari_cap_v": 153, "pf0_bar0_aperture_s": 153, "pf0_bar0_control": 153, "pf0_bar1_aperture_s": 153, "pf0_bar1_control": 153, "pf0_bar2_aperture_s": 153, "pf0_bar2_control": 153, "pf0_bar3_aperture_s": 153, "pf0_bar3_control": 153, "pf0_bar4_aperture_s": 153, "pf0_bar4_control": 153, "pf0_bar5_aperture_s": 153, "pf0_bar5_control": 153, "pf0_bist_regist": 153, "pf0_capability_point": 153, "pf0_class_cod": 153, "pf0_dev_cap2_obff_support": 153, "pf0_dev_cap_endpoint_l0s_lat": 153, "pf0_dev_cap_endpoint_l1_lat": 153, "pf0_dev_cap_max_payload_s": 153, "pf0_device_id": 153, "pf0_dpa_cap_nextptr": 153, "pf0_dpa_cap_sub_state_control": 153, "pf0_dpa_cap_sub_state_power_allocation0": 153, "pf0_dpa_cap_sub_state_power_allocation1": 153, "pf0_dpa_cap_sub_state_power_allocation2": 153, "pf0_dpa_cap_sub_state_power_allocation3": 153, "pf0_dpa_cap_sub_state_power_allocation4": 153, "pf0_dpa_cap_sub_state_power_allocation5": 153, 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"phaser_in_en": 145, "phaser_in_enphaser_in0": 145, "phaser_in_enphaser_in1": 145, "phaser_in_enphaser_in2": 145, "phaser_in_enphaser_in3": 145, "phaser_in_rclk001001": 145, "phaser_in_rclk101010": 145, "phaser_in_rclk201100": 145, "phaser_in_rclk310100": 145, "phaser_out0": 145, "phaser_out1": 145, "phaser_out2": 145, "phaser_out3": 145, "phaser_out_en": 145, "phaser_ref": 145, "phaser_ref_bounce0": 145, "phaser_ref_bounce000100010000": 145, "phaser_ref_bounce001000000010000": 145, "phaser_ref_bounce1": 145, "phaser_ref_bounce100100100000": 145, "phaser_ref_bounce110000000010000": 145, "phaser_ref_bounce2": 145, "phaser_ref_bounce201000000000100": 145, "phaser_ref_bounce201000010000": 145, "phaser_ref_bounce3": 145, "phaser_ref_bounce301000100000": 145, "phaser_ref_bounce310000000000100": 145, "phaser_ref_en": 145, "phaser_ref_misc": 145, "phaserefclk": 145, "phi": 35, "philip": [169, 170], "phy_control": 145, "phy_count_en": 145, "phyemac0gtxclk": 117, "phyemac0mclkin": 117, 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146], "post_crc_sel": [62, 115, 131, 146], "potenti": 36, "power": [12, 17, 34, 35, 36, 160, 169, 171], "power_en": 105, "power_sav": 136, "powerdown": [54, 67], "powerdown_statu": [84, 101], "powerdownpin": [76, 85, 98], "powerdownpinmisc": [76, 85], "powerpc": [44, 82, 90, 92, 96, 121], "powerup_clk": 76, "powerup_delai": 76, "ppc": [87, 90, 104, 118, 125], "ppcdm_asyncmod": 125, "ppcds_asyncmod": 125, "ppcm_arbconfig": 125, "ppcm_control": 125, "ppcm_counter": 125, "ppcs0_addrmap_tmpl0": 125, "ppcs0_addrmap_tmpl1": 125, "ppcs0_addrmap_tmpl2": 125, "ppcs0_addrmap_tmpl3": 125, "ppcs0_control": 125, "ppcs0_width_128n64": 125, "ppcs1_addrmap_tmpl0": 125, "ppcs1_addrmap_tmpl1": 125, "ppcs1_addrmap_tmpl2": 125, "ppcs1_addrmap_tmpl3": 125, "ppcs1_control": 125, "ppcs1_width_128n64": 125, "ppds_25001001000111": 50, "ppds_250111": 57, "ppds_33001001000111": 50, "ppds_330111": 57, "pq100": [18, 19, 29, 34], "pq160": [18, 19, 22, 34], "pq208": [3, 6, 7, 12, 24, 25, 34, 164, 165, 166, 169], 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23], "u25": [22, 23], "u26": [22, 23], "u3": [6, 7, 22, 23, 24, 25, 164, 165, 166], "u4": [6, 7, 22, 23, 24, 25, 164, 165, 166], "u5": [24, 25, 164], "u6": [24, 25, 164], "u7": [24, 25, 164], "u8": [24, 25, 164], "u9": [24, 25, 164], "ucmt_top": 145, "uct": [159, 171], "uct0": [161, 162, 163, 164, 165, 166, 171], "uct0101": 159, "uct1": [161, 162, 163, 164, 165, 166, 171], "uct1110": 159, "uct2": [161, 162, 163, 164, 165, 166, 171], "uct2110": 159, "uct3": [161, 162, 163, 164, 165, 166, 171], "uct3111": 159, "ue": [159, 161, 162, 163, 164, 165, 166, 171], "uim": [16, 17, 32, 33, 34, 35], "uim0": 26, "uim10": 26, "uim110": 29, "uim1110": [18, 19, 22, 29], "uim11110": [19, 22, 23], "uim_area_bit": 15, "uim_ibuf_bit": 17, "uim_o": 36, "uim_oe_mux": 36, "uim_oe_mux4544": 15, "uim_out_inv": [15, 36], "uim_out_inv46": 15, "uim_row_bit": 15, "uim_subarea_bit": 15, "ul": [58, 63, 87], "ulvds_250000000000100": 50, "ulvds_25000100001": 85, "ulvds_250001000111": 100, "ulvds_25001000001": 85, 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"update_nonactivephaser_in2": 145, "update_nonactivephaser_in3": 145, "upgrad": [81, 92], "upload": 35, "upper": [41, 46, 54, 58, 67, 81, 82, 87, 90, 96, 104, 108, 118, 123, 134], "upsid": 104, "upstream_fac": [140, 152], "upstream_facingpci": [140, 152], "upstreamfac": 124, "upstreamfacingpci": 124, "upward": [36, 46, 82, 123], "ur": [58, 63, 87], "ur_atom": 152, "ur_atomicpci": 152, "ur_cfg1": 152, "ur_inv_req": [140, 152], "ur_inv_reqpci": 152, "ur_prs_respons": 152, "us": [12, 14, 15, 16, 17, 34, 35, 36, 42, 45, 46, 47, 50, 55, 56, 58, 81, 82, 83, 85, 87, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "usabl": [55, 58], "use_dport": [132, 147], "use_dportdsp0": 147, "use_dportdsp1": 147, "use_mult": [116, 132, 147], "use_multdsp0": 147, "use_multdsp1": 147, "use_pattern_detect": 116, "use_rid_pin": 152, "use_rid_pinspci": 152, "use_simd": [116, 132, 147], "use_vref01": [2, 3, 6, 7], "useless": [55, 148], "user": [56, 92, 139, 151, 159, 171], "user1": 63, "user_clk2_div2": 152, "user_clk2_div2pci": 152, "user_clk_freq": [140, 152], "user_mode00": [88, 89], "user_operation0": 135, "userclk0": 155, "userclk01": [39, 48, 49, 62, 75, 76, 84, 101, 115, 131, 146], "userclk1": 155, "usercod": [2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 35, 36], "userid": [40, 50, 63, 76, 85, 98, 111, 127, 142], "usr_cfg": 70, "usr_code_err_clr": 136, "usr_code_err_clr_0": 66, "usr_code_err_clr_0gtp": 66, "usr_code_err_clr_1": 66, "usr_code_err_clr_1gtp": 66, "usr_code_err_clrgtx0": 136, "usr_code_err_clrgtx1": 136, "usr_code_err_clrgtx2": 136, "usr_code_err_clrgtx3": 136, "usr_ext_cfg": 70, "usrcclk_en": [98, 111, 127, 142], "usrclk0": [119, 120], "usrclk1": [119, 120], "usual": [17, 35, 36, 91, 104, 118, 171], "v": [12, 78], "v0": [73, 76, 79, 154, 155, 157, 158], "v0000": 155, "v00110": 155, "v0int": 157, "v1": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 154, 155, 157, 158, 164, 165, 166], "v10": [24, 25, 164], "v1001": 155, "v10010": 155, "v11": [24, 25, 164], "v12": [24, 25, 164], "v13": [24, 25, 164], "v14": [24, 25, 164], "v15": [24, 25, 164], "v16": [24, 25, 164], "v17": [24, 25, 164], "v18": [24, 25, 164], "v19": [6, 7, 24, 25, 164, 165, 166], "v1int": 157, "v2": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 90, 154, 155, 157, 158, 164, 165, 166], "v20": [6, 7, 24, 165, 166], "v2010": 155, "v20100": 155, "v21": [6, 7, 165, 166], "v22": [6, 7, 165, 166], "v23": [22, 23], "v24": [22, 23], "v25": [22, 23], "v26": [22, 23], "v2int": [155, 157], "v2osc": 155, "v2p": 90, "v3": [6, 7, 22, 23, 24, 25, 73, 76, 79, 80, 154, 155, 157, 158, 164, 165, 166], "v30000": 155, "v3011": 155, "v31110": 155, "v3int": 157, "v4": [6, 7, 22, 23, 24, 25, 154, 155, 157, 158, 164, 165, 166], "v40100": 155, "v4100": 155, "v411": 155, "v4111101111": 155, "v4int": [155, 157], "v4tbuf0": 154, "v5": [24, 25, 154, 155, 157, 158, 164], "v50101": 155, "v510": 155, "v5101": 155, "v5111110111": 155, "v5int": [155, 157], "v6": [24, 25, 154, 155, 157, 158, 164], "v60110": 155, "v611": 155, "v6110": 155, "v6111111011": 155, "v6int": [155, 157], "v6tbuf3": 157, "v7": [24, 25, 154, 155, 157, 158, 164], "v70111": 155, "v710": 155, "v7111": 155, "v7111111101": 155, "v7int": 155, "v8": [24, 25, 164], "v9": [24, 25, 164], "valid": [15, 16, 35], "valu": [14, 15, 16, 17, 35, 36, 46, 54, 81, 82, 90, 91, 96, 160, 170, 171], "vari": [34, 35, 36, 104, 108, 118, 134, 148, 171], "variabl": [123, 159], "variable01": 123, "variable11": 108, "variable110": 64, "variant": [12, 34, 36, 55, 58, 87, 91, 104, 118, 134, 148, 151, 171], "variou": [46, 55, 56, 82, 91, 92, 171], "vbg_dll_sel": 115, "vbg_flat_sel": 146, "vbg_pd": [51, 86], "vbg_sel": [51, 52, 86, 115, 131], "vbg_slope_opt": 63, "vbg_vgg_flast_sel": 131, "vbg_vgg_neg_sel": 131, "vbrk": [104, 118], "vc0_cpl_infinit": [70, 140, 152], "vc0_rx_ram_limit": [70, 140, 152], "vc0_total_credits_cd": [70, 140, 152], "vc0_total_credits_ch": [70, 140, 152], "vc0_total_credits_npd": 152, "vc0_total_credits_nph": [70, 140, 152], "vc0_total_credits_pd": [70, 140, 152], "vc0_total_credits_ph": [70, 140, 152], "vc0_tx_lastpacket": [70, 140, 152], "vc0rxfifobasec": 124, "vc0rxfifobasenp": 124, "vc0rxfifobasep": 124, "vc0rxfifolimitc": 124, "vc0rxfifolimitnp": 124, "vc0rxfifolimitp": 124, "vc0totalcreditscd": 124, "vc0totalcreditsch": 124, "vc0totalcreditsnph": 124, "vc0totalcreditspd": 124, "vc0totalcreditsph": 124, "vc0txfifobasec": 124, "vc0txfifobasenp": 124, "vc0txfifobasep": 124, "vc0txfifolimitc": 124, "vc0txfifolimitnp": 124, "vc0txfifolimitp": 124, "vc1rxfifobasec": 124, "vc1rxfifobasenp": 124, "vc1rxfifobasep": 124, "vc1rxfifolimitc": 124, "vc1rxfifolimitnp": 124, "vc1rxfifolimitp": 124, "vc1totalcreditscd": 124, "vc1totalcreditsch": 124, "vc1totalcreditsnph": 124, "vc1totalcreditspd": 124, "vc1totalcreditsph": 124, "vc1txfifobasec": 124, "vc1txfifobasenp": 124, "vc1txfifobasep": 124, "vc1txfifolimitc": 124, "vc1txfifolimitnp": 124, "vc1txfifolimitp": 124, "vc_base_ptr": [140, 152], "vc_cap_id": [140, 152], "vc_cap_nextptr": [140, 152], "vc_cap_on": [140, 152], "vc_cap_reject_snoop_transact": [140, 152], "vc_cap_reject_snoop_transactionspci": 152, "vc_cap_vers": [140, 152], "vcbaseptr": 124, "vcc": [36, 160, 161, 162, 163, 164, 165, 166, 169, 171], "vcc00": 61, "vcc0000": [2, 3, 4, 5, 6, 7, 8, 9], "vcc0000000000": [138, 150], "vcc00000010": 68, "vcc00010001": 107, "vcc0010000001": 122, "vcc00100001": 107, "vcc01": 15, "vcc01000010": 68, "vcc10": [132, 147], "vcc11": [2, 3, 4, 5, 6, 7, 8, 9], "vcc110": 159, "vcc11000001": 68, "vcc11111111": [4, 5, 161], "vcc1111111111111111": [8, 9], "vcc11111111111111111": 162, "vcc111111111111111111111111111": 163, "vcc1111111111111111111111111111": 2, "vcc1111111111111111111111111111111111111111111111": 164, "vcc111111111111111111111111111111111111111111111111": 3, "vcc111111111111111111111111111111111111111111111111111111111111111": 165, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111": 6, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111111111111": 166, "vcc1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111": 7, "vcc_gnd": 154, "vccapabilitynextptr": 124, "vccaux": [2, 3, 4, 5, 6, 7, 8, 9, 12], "vccint": [2, 3, 4, 5, 6, 7, 8, 9, 12, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34], "vccio": [12, 17, 34], "vccio0": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "vccio1": [2, 3, 5, 6, 7, 9, 21, 25], "vccio2": [6, 7, 25], "vccio3": [6, 7, 25], "vco_ctrl_en": 105, "vcodac_init": 105, "vdd11": 114, "vdd_vbg000": 102, "ve": 78, "vendor": [35, 170, 171], "vendor_id": 140, "vendorid": 124, "veri": [12, 34, 36, 46, 55, 81, 139, 148, 169, 171], "verif": 35, "verifi": [35, 91], "version": [12, 16, 34, 36, 46, 48, 49, 55, 56, 58, 92, 96, 148], "vertic": [38, 46, 47, 54, 55, 81, 82, 87, 91, 96, 134, 148], "vf0_ari_cap_nextptr": 153, "vf0_capability_point": 153, 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"zia_gclk2_en": [161, 162, 163, 164, 165, 166], "zia_gclk3_en": [161, 162, 163, 164, 165, 166], "zynq": 148, "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "FPGAcore", "General interconnect", "Input / Output", "Xilinx FPGAs", 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transceivers", "Virtex 6", "Interconnect", "Input/Output", "PCI Express cores", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Clock management tile", "Configuration registers", "DSP", "Device geometry", "Virtex 7", "Interconnect", "Input/Output", "PCI Express Gen2 cores", "PCI Express Gen3 cores", "Configurable Logic Block", "Corners", "XC5200", "Input/Output", "Splitters", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [47, 91], "03": 55, "1": [46, 82], "12": [49, 55, 62], "128": 82, "16": [46, 82], "2": [81, 85, 88, 89, 90, 93], "3": [46, 48, 50, 51, 54, 57, 81], "32": [46, 82], "34": 62, "3a": [49, 50, 52, 57, 58, 81], "3e": [48, 50, 52, 57, 58, 81], "4": [46, 106], "405": 95, "5": 121, "6": [67, 137], "64": [46, 82], "7": 149, "AND": 15, "The": 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[45, 55, 58, 81, 91, 150], "bspi": 146, "bu": [36, 83], "buffer": [14, 15, 36, 43, 57, 58, 79, 87, 93, 171], "buse": 82, "carri": [46, 82], "cclk_freq": [49, 62], "center": [38, 47, 98, 104, 111, 118, 127, 134, 142, 148], "check": 35, "clb": [42, 55, 91], "clbll": [112, 128, 143], "clblm": [112, 128, 143], "clexl": 60, "clexm": 60, "clk": 93, "clk_b": [91, 93], "clk_bali_rebuf": 144, "clk_bufg": 144, "clk_bufg_rebuf": 144, "clk_cmt_b": 113, "clk_cmt_t": 113, "clk_dcm_b": 100, "clk_dcm_t": 100, "clk_hrow": [100, 113, 144], "clk_iob_b": [100, 113], "clk_iob_t": [100, 113], "clk_mgt_b": 113, "clk_mgt_t": 113, "clk_t": [91, 93], "clk_term_b": 100, "clk_term_t": 100, "clkb": [38, 47, 55, 74, 83, 158], "clkb_2dll": 74, "clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 158, "clkl": [47, 80, 158], "clkpad": 91, "clkr": [47, 80, 158], "clkt": [38, 47, 55, 74, 83, 158], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 158], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113, 114, 129, 130, 144, 145], "cmt": [68, 113, 114, 130, 145], "cmt_bufg_bot": 129, "cmt_bufg_top": 129, "cmt_fifo": 145, "cnr": [76, 91, 155], "column": [58, 72, 104, 118, 134, 148, 171], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 115, 127, 128, 131, 142, 143, 146, 148, 154, 171], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 121, 137, 149, 156, 167, 168], "control": [69, 171], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 115, 131, 146], "cor1": [49, 62, 115, 131, 146], "cor2": [49, 62], "core": [95, 124, 125, 140, 152, 153], "corner": [40, 50, 63, 76, 85, 155], "cpld": [11, 33, 168], "ctl": [39, 48, 49, 62, 75, 84, 101, 115, 131, 146], "ctl1": [131, 146], "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 113, 161, 162, 163, 164, 165, 166], "databas": [10, 17, 32, 160, 167], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 122, 138, 150], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 118, 134, 148, 160, 167, 169, 171], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 116, 132, 147], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 118, 134, 148], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [117, 133], "exit": 35, "export": 36, "express": [70, 124, 140, 148, 152, 153], "eye_mask": 62, "fb": [14, 15, 16, 36, 159, 171], "fc": [38, 39, 40, 42, 43], "fclk": 171, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 123, 139, 151], "fuse": [15, 16, 35, 36, 159], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 152, "gen3": 153, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 118, 134, 148], "general5": 62, "geometri": [58, 87, 104, 118, 134, 148], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 159, 161, 162, 163, 164, 165, 166], "gt": 91, "gth": 135, "gtp": [119, 148], "gtx": [120, 136, 148], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113, 129, 144], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": [113, 139], "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_hp": 151, "hclk_ioi_hr": 151, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 118, 148], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "ibuf": 23, "idcod": [35, 170], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 159, 161, 162, 163, 164, 165, 166], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 123, 139, 151, 157, 171], "instruct": [13, 35, 170], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 122, 129, 138, 144, 150], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 170], "intf": [55, 68, 91, 122, 138, 150], "introduct": [12, 34, 56, 92, 169], "io": [58, 79, 87, 100, 113, 139, 148, 157], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 159, 171], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 170], "isp": [13, 35, 170], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 160, 161, 162, 163, 164, 165, 166], "jtag": [13, 35, 170], "keeper": 36, "l": [43, 79, 93, 157], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 160], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 171, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 128, 143, 154], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 171, "mac": [117, 133], "macrocel": [14, 15, 16, 36, 159, 171], "manag": [51, 52, 64, 86, 102, 114, 130, 145], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 161, 162, 163, 164, 165, 166], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 148], "misc": [14, 36, 171], "mmcm": 145, "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 171], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 123, 139, 151, 157, 171], "overview": [14, 36, 171], "packag": [12, 34, 169], "part": [17, 160], "pci": [70, 80, 87, 94, 124, 140, 148, 152, 153], "pci_ce_delai": 61, "pcie_l": 152, "pcie_r": 152, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 161, 162, 163, 164, 165, 166, 169], "placement": 148, "pll": 145, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 129, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 118, 125], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 148, "product": [14, 15, 16, 36, 82, 159, 171], "program": [13, 35, 170], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 157], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 126, 141], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 115, 131, 146, 170, 171], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 148], "row": [38, 47, 58, 83, 87, 100, 171], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 170], "schema": [17, 160], "secondari": [38, 47, 58], "sequenc": [13, 35, 170], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 123, 139, 151], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 118], "splitter": [55, 158], "standard": [100, 113], "structur": [1, 14, 15, 16, 36, 58, 87, 104, 118, 134, 148, 159, 171], "sum": [14, 36, 82, 159, 171], "system": [109, 148], "t": [43, 57, 79, 83, 88, 89, 93, 157], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92, 114, 130, 145], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 159, 171], "termin": [55, 91, 100], "testmod": [62, 131, 146], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 114, 130, 145, 160], "timer": [62, 115, 131, 146], "tl": [52, 76, 155], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 115, 118, 119, 120, 121, 122, 127, 128, 129, 130, 131, 134, 135, 136, 137, 138, 142, 143, 144, 145, 146, 148, 149, 150, 151, 156, 170, 171], "top": [17, 38, 47, 61, 72, 77, 83, 91, 160], "tr": [52, 76, 155], "transceiv": [66, 88, 89, 105, 119, 120, 135, 136, 148], "trim": 131, "trim0": 146, "trim1": 146, "trim2": 146, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 171, "unk1c": 131, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 121, 137, 149], "w": 91, "wbstar": 146, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 159], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xadc": 142, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 156, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 161, "xcr3064xl": 162, "xcr3128xl": 163, "xcr3256xl": 164, "xcr3384xl": 165, "xcr3512xl": 166, "xilinx": [11, 33, 44, 168], "xor": [14, 36], "xpla3": 168, "xv": [16, 35, 36], "zia": 171}}) \ No newline at end of file +Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[45, "bram-s3"]], "BRAM.S3A": [[45, "bram-s3a"]], "BRAM.S3ADSP": [[45, "bram-s3adsp"]], "BRAM.S3E": [[45, "bram-s3e"]], "BSPI": [[146, "bspi"]], "Backbone": [[55, "backbone"], [91, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitstream": [[37, "bitstream"], [45, "bitstream"], [46, "bitstream"], [53, "bitstream"], [59, "bitstream"], [64, "bitstream"], [65, "bitstream"], [66, "bitstream"], [69, "bitstream"], [70, "bitstream"], [71, "bitstream"], [73, "bitstream"], [81, "bitstream"], [82, "bitstream"], [88, "bitstream"], [89, "bitstream"], [96, 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"bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [128, "bitstream-clbll"], [143, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [128, "bitstream-clblm"], [143, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_IOI": [[139, "bitstream-hclk-ioi"]], "Bitstream \u2014 HCLK_IOI_HP": [[151, "bitstream-hclk-ioi-hp"]], "Bitstream \u2014 HCLK_IOI_HR": [[151, "bitstream-hclk-ioi-hr"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[122, "bitstream-intf"], [138, "bitstream-intf"], [150, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[150, 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"Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [126, "block-ram"], [141, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [160, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [170, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [158, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[158, "clkh"]], "CLKL": [[80, "clkl"], [158, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [158, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [158, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[158, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_BALI_REBUF": [[144, "clk-bali-rebuf"]], "CLK_BUFG": [[144, "clk-bufg"]], "CLK_BUFG_REBUF": [[144, "clk-bufg-rebuf"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"], [144, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CMT": [[114, "cmt"], [130, "cmt"], [145, "cmt"]], "CMT_BUFG_BOT": [[129, "cmt-bufg-bot"]], "CMT_BUFG_TOP": [[129, "cmt-bufg-top"]], "CMT_FIFO": [[145, "cmt-fifo"]], "CNR.BL": [[76, "cnr-bl"], [155, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [155, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [155, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [155, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [115, "cor"], [131, "cor"], [146, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [115, "cor1"], [131, "cor1"], [146, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [115, "ctl"], [131, "ctl"], [146, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[131, "ctl1"], [146, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [118, "center-column"], [134, "center-column"]], "Center column and configuration center": [[148, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"], [129, "clock-interconnect"], [144, "clock-interconnect"]], "Clock management tile": [[114, "clock-management-tile"], [130, "clock-management-tile"], [145, "clock-management-tile"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [128, "configurable-logic-block"], [143, "configurable-logic-block"], [154, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [127, "configuration-center"], [142, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [115, "configuration-registers"], [131, "configuration-registers"], [146, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [121, null], [137, null], [149, null], [156, null], [167, null], [168, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [155, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [116, "dsp"], [132, "dsp"], [147, "dsp"]], "Database schema": [[17, "database-schema"], [160, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [167, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [160, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [118, "device-geometry"], [134, "device-geometry"], [148, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [169, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [171, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [169, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [118, "ecc"], [134, "ecc"], [148, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[117, "ethernet-macs"], [133, "ethernet-macs"]], "FB columns and rows": [[171, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[171, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[159, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[159, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[159, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [159, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[159, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTH transceivers": [[135, "gth-transceivers"]], "GTP and GTX right column holes": [[148, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[119, "gtp-transceivers"]], "GTX transceivers": [[120, "gtx-transceivers"], [136, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [118, "general-structure"], [134, "general-structure"], [148, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [161, "global-bits"], [162, "global-bits"], [163, "global-bits"], [164, "global-bits"], [165, "global-bits"], [166, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [129, "hclk"], [144, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [123, "i-o-banks-and-special-functions"], [139, "i-o-banks-and-special-functions"], [151, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [161, "i-o-pins"], [162, "i-o-pins"], [163, "i-o-pins"], [164, "i-o-pins"], [165, "i-o-pins"], [166, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [170, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [161, "imux-bits"], [162, "imux-bits"], [163, "imux-bits"], [164, "imux-bits"], [165, "imux-bits"], [166, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[148, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [157, "io-b"]], "IO.L": [[79, "io-l"], [157, "io-l"]], "IO.R": [[79, "io-r"], [157, "io-r"]], "IO.T": [[79, "io-t"], [157, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [170, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [170, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [123, "input-output"], [139, "input-output"], [151, "input-output"], [157, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [171, "input-output-buffer"]], "Interconnect": [[122, "interconnect"], [138, "interconnect"], [150, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [169, "introduction"]], "JED bits": [[160, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [159, "jed-mapping"], [161, "jed-mapping"], [162, "jed-mapping"], [163, "jed-mapping"], [164, "jed-mapping"], [165, "jed-mapping"], [166, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[159, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[159, "jed-mapping-macrocells-without-iob"]], "JED structure": [[159, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [170, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[171, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MMCM Tables": [[145, "mmcm-tables"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [171, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[148, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [171, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [171, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[152, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[153, "pci-express-gen3-cores"]], "PCI Express cores": [[124, "pci-express-cores"], [140, "pci-express-cores"]], "PCI Express holes": [[148, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[152, "pcie-l"]], "PCIE_R": [[152, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PLL Tables": [[145, "pll-tables"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[129, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [169, "packages"]], "Part": [[17, "part"], [160, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[125, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [118, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[148, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [171, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [170, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [171, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [160, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [161, "speed-data"], [162, "speed-data"], [163, "speed-data"], [164, "speed-data"], [165, "speed-data"], [166, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [118, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[158, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[171, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [131, "testmode"], [146, "testmode"]], "TIMER": [[62, "timer"], [115, "timer"], [131, "timer"], [146, "timer"]], "TRIM": [[131, "trim"]], "TRIM0": [[146, "trim0"]], "TRIM1": [[146, "trim1"]], "TRIM2": [[146, "trim2"]], "Tables": [[71, "tables"], [108, "tables"], [114, "tables"], [123, "tables"], [130, "tables"], [139, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[81, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[81, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[83, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [160, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], 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110, 126, 141], "9998": [45, 59, 81, 96, 110, 126, 141], "9999": [45, 59, 81, 96, 110, 126, 141], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 159, "9fb_group": [161, 162, 163, 164, 165, 166], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 159, "9reg_d_ireg": 159, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 124, 127, 142, 152, 153], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 117, 125, 130, 133, 140, 144], "9rowcolumn01234567891011121314151617181920212223242526272829": [114, 135, 136, 145, 152], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [119, 120], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 118, 123, 134, 139, 148, 151, 160, 171], "AED": [12, 169], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 171], "As": [35, 134, 171], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 118, 134, 148, 171], "ISE": [35, 171], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 118, 134, 139, 148, 171], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 118, 123, 134, 139, 148, 151, 171], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 118, 134, 139, 148, 151, 160, 169, 171], "Its": [35, 81], "No": 148, "Not": [15, 16, 36, 55, 91, 171], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 148, 171], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 169, 170, 171], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 118, 134, 139, 148, 151], "These": [36, 91, 139, 148], "To": [35, 36, 96], "_": [17, 34, 36, 160, 171], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 159, 171], "_gclk": 171, "_init": [46, 82], "_inv": [36, 171], "_lct": 171, "_mc": [12, 169], "_mux": [36, 46, 82], "_none": 171, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 163, 164, 165, 166], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a17": [6, 7, 22, 23, 24, 25, 45, 164, 165, 166], "a18": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a19": [6, 7, 22, 23, 24, 25, 164, 165, 166], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a20": [6, 7, 22, 23, 24, 165, 166], "a21": [6, 7, 22, 23, 165, 166], "a22": [6, 7, 22, 23, 165, 166], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a5ffinit": [128, 143], "a5ffinitslice0": [128, 143], "a5ffmux": [128, 143], "a5ffsr": [128, 143], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 128, "a5q0": 60, "a5q0100": [60, 128, 143], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a6lut": [60, 112, 128, 143], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 161, 162, 163, 164, 165, 166], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 162, 163, 164, 165, 166], "a_dfeclkdlyadj": 136, "a_dfedlyovrd": 136, "a_dfedlyovrdgtx0": 136, "a_dfedlyovrdgtx1": 136, "a_dfedlyovrdgtx2": 136, "a_dfedlyovrdgtx3": 136, "a_dfetap1": 136, "a_dfetap2": 136, "a_dfetap3": 136, "a_dfetap4": 136, "a_dfetapovrd": 136, "a_dfetapovrdgtx0": 136, "a_dfetapovrdgtx1": 136, "a_dfetapovrdgtx2": 136, "a_dfetapovrdgtx3": 136, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 136, "a_gtxrxresetgtx0": 136, "a_gtxrxresetgtx1": 136, "a_gtxrxresetgtx2": 136, "a_gtxrxresetgtx3": 136, "a_gtxtxreset": 136, "a_gtxtxresetgtx0": 136, "a_gtxtxresetgtx1": 136, "a_gtxtxresetgtx2": 136, "a_gtxtxresetgtx3": 136, "a_input": [116, 132, 147], "a_loopback": 136, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 136, "a_pllclkrxresetgtx0": 136, "a_pllclkrxresetgtx1": 136, "a_pllclkrxresetgtx2": 136, "a_pllclkrxresetgtx3": 136, "a_pllclktxreset": 136, "a_pllclktxresetgtx0": 136, "a_pllclktxresetgtx1": 136, "a_pllclktxresetgtx2": 136, "a_pllclktxresetgtx3": 136, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 136, "a_pllrxresetgtx0": 136, "a_pllrxresetgtx1": 136, "a_pllrxresetgtx2": 136, "a_pllrxresetgtx3": 136, "a_plltxreset": 136, "a_plltxresetgtx0": 136, "a_plltxresetgtx1": 136, "a_plltxresetgtx2": 136, "a_plltxresetgtx3": 136, "a_prbscntreset": 136, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 136, "a_prbscntresetgtx1": 136, "a_prbscntresetgtx2": 136, "a_prbscntresetgtx3": 136, "a_q": 81, "a_rxbufreset": 136, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 136, "a_rxbufresetgtx1": 136, "a_rxbufresetgtx2": 136, "a_rxbufresetgtx3": 136, "a_rxcdrfreqreset": 136, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 136, "a_rxcdrfreqresetgtx1": 136, "a_rxcdrfreqresetgtx2": 136, "a_rxcdrfreqresetgtx3": 136, "a_rxcdrhold": 136, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 136, "a_rxcdrholdgtx1": 136, "a_rxcdrholdgtx2": 136, "a_rxcdrholdgtx3": 136, "a_rxcdrphasereset": 136, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 136, "a_rxcdrphaseresetgtx1": 136, "a_rxcdrphaseresetgtx2": 136, "a_rxcdrphaseresetgtx3": 136, "a_rxcdrreset": 136, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 136, "a_rxcdrresetgtx1": 136, "a_rxcdrresetgtx2": 136, "a_rxcdrresetgtx3": 136, "a_rxdfereset": 136, "a_rxdferesetgtx0": 136, "a_rxdferesetgtx1": 136, "a_rxdferesetgtx2": 136, "a_rxdferesetgtx3": 136, "a_rxenpmaphasealign": 136, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 136, "a_rxenpmaphasealigngtx1": 136, "a_rxenpmaphasealigngtx2": 136, "a_rxenpmaphasealigngtx3": 136, "a_rxenprbstst": 136, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 136, "a_rxensamplealigngtx0": 136, "a_rxensamplealigngtx1": 136, "a_rxensamplealigngtx2": 136, "a_rxensamplealigngtx3": 136, "a_rxeqmix": 136, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 136, "a_rxplllkdetengtx0": 136, "a_rxplllkdetengtx1": 136, "a_rxplllkdetengtx2": 136, "a_rxplllkdetengtx3": 136, "a_rxpllpowerdown": 136, "a_rxpllpowerdowngtx0": 136, "a_rxpllpowerdowngtx1": 136, "a_rxpllpowerdowngtx2": 136, "a_rxpllpowerdowngtx3": 136, "a_rxpmasetphas": 136, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 136, "a_rxpmasetphasegtx1": 136, "a_rxpmasetphasegtx2": 136, "a_rxpmasetphasegtx3": 136, "a_rxpolar": 136, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 136, "a_rxpolaritygtx1": 136, "a_rxpolaritygtx2": 136, "a_rxpolaritygtx3": 136, "a_rxpowerdown": 136, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 136, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 136, "a_rxresetgtx1": 136, "a_rxresetgtx2": 136, "a_rxresetgtx3": 136, "a_txbufdiffctrl": 136, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 136, "a_txdeemphgtx0": 136, "a_txdeemphgtx1": 136, "a_txdeemphgtx2": 136, "a_txdeemphgtx3": 136, "a_txdiffctrl": 136, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 136, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 136, "a_txelecidlegtx1": 136, "a_txelecidlegtx2": 136, "a_txelecidlegtx3": 136, "a_txenpmaphasealign": 136, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 136, "a_txenpmaphasealigngtx1": 136, "a_txenpmaphasealigngtx2": 136, "a_txenpmaphasealigngtx3": 136, "a_txenprbstst": 136, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 136, "a_txplllkdeten": 136, "a_txplllkdetengtx0": 136, "a_txplllkdetengtx1": 136, "a_txplllkdetengtx2": 136, "a_txplllkdetengtx3": 136, "a_txpllpowerdown": 136, "a_txpllpowerdowngtx0": 136, "a_txpllpowerdowngtx1": 136, "a_txpllpowerdowngtx2": 136, "a_txpllpowerdowngtx3": 136, "a_txpmasetphas": 136, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 136, "a_txpmasetphasegtx1": 136, "a_txpmasetphasegtx2": 136, "a_txpmasetphasegtx3": 136, "a_txpolar": 136, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 136, "a_txpolaritygtx1": 136, "a_txpolaritygtx2": 136, "a_txpolaritygtx3": 136, "a_txpostemphasi": 136, "a_txpowerdown": 136, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 136, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 136, "a_txprbsforceerrgtx1": 136, "a_txprbsforceerrgtx2": 136, "a_txprbsforceerrgtx3": 136, "a_txpreemphasi": 136, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 136, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 136, "a_txresetgtx1": 136, "a_txresetgtx2": 136, "a_txresetgtx3": 136, "a_txsw": 136, "a_txswinggtx0": 136, "a_txswinggtx1": 136, "a_txswinggtx2": 136, "a_txswinggtx3": 136, "aa1": [6, 7, 22, 23, 165, 166], "aa10": [6, 7, 165, 166], "aa11": [6, 7, 165, 166], "aa12": [6, 7, 165, 166], "aa13": [6, 7, 165, 166], "aa14": [6, 7, 165, 166], "aa15": [6, 7, 165, 166], "aa16": [6, 7, 165, 166], "aa17": [6, 7, 165, 166], "aa18": [6, 7, 165, 166], "aa19": [6, 7, 165, 166], "aa2": [6, 7, 22, 23, 165, 166], "aa20": [6, 7, 165, 166], "aa21": [6, 7, 165, 166], "aa22": [6, 7, 165, 166], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 165, 166], "aa4": [6, 7, 22, 23, 165, 166], "aa5": [6, 7, 165, 166], "aa6": [6, 7, 165, 166], "aa7": [6, 7, 165, 166], "aa8": [6, 7, 165, 166], "aa9": [6, 7, 165, 166], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 165, 166], "ab10": [6, 7, 165, 166], "ab11": [6, 7, 165, 166], "ab12": [6, 7, 165, 166], "ab13": [6, 7, 165, 166], "ab14": [6, 7, 165, 166], "ab15": [6, 7, 165, 166], "ab16": [6, 7, 165, 166], "ab17": [6, 7, 165, 166], "ab18": [6, 7, 165, 166], "ab19": [6, 7, 165, 166], "ab2": [6, 7, 22, 23, 165, 166], "ab20": [6, 7, 165, 166], "ab21": [6, 7, 165, 166], "ab22": [6, 7, 165, 166], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 165, 166], "ab4": [6, 7, 22, 23, 165, 166], "ab5": [6, 7, 165, 166], "ab6": [6, 7, 165, 166], "ab7": [6, 7, 165, 166], "ab8": [6, 7, 165, 166], "ab9": [6, 7, 165, 166], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 148, 151, 171], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 160, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 136, "ac_cap_dis_0": [66, 119, 120], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 119, "ac_cap_dis_0gtx_du": 120, "ac_cap_dis_1": [66, 119, 120], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 119, "ac_cap_dis_1gtx_du": 120, "ac_cap_disgtx0": 136, "ac_cap_disgtx1": 136, "ac_cap_disgtx2": 136, "ac_cap_disgtx3": 136, "acb": [12, 34, 169], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 169, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 118, 134, 148, 151, 160, 169, 171], "activ": [35, 36, 46, 82, 170], "activelanesin": 124, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 118, 134, 148, 171], "acy0": [60, 112, 128, 143], "acy0slice0": [112, 128, 143], "acy0slice1": [60, 128], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 118, 134, 148, 171], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 118, 134], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, 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"addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 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114, "clkoutdcm4010": 114, "clkoutdcm5110": 114, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkperf": 139, "clkperfiodelay0": 139, "clkperfologic1": 139, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [119, 120], "clkpn1": [119, 120], "clkr": [58, 78, 156], "clkrcv_trst": [120, 136], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 136, "clkrcv_trstgtx_dual": 120, "clkslice0": 112, "clkslice1": [60, 128], "clkt": [58, 78, 87, 156], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 136, "clktestsig1": 135, "clktestsig11": 136, "clktestsig1111": 136, "clktestsig_sel": 135, "clktestsig_selgth": 135, "clkv": [78, 156], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 118, 121, 123, 134, 137, 139, 148, 149, 151, 160, 169, 171], "clock_delai": 125, "clock_hold": 130, "clock_holdmmcm0": 130, "clock_holdmmcm1": 130, "clock_invert_m": 116, "clock_invert_p": 116, "clock_invert_pdsp1": 116, "clockwis": [58, 87], "close": [58, 81, 134, 148], "closest": 58, "clr0": 154, "clrmux": 154, "clrmuxlc0": 154, "clrmuxlc1": 154, "clrmuxlc2": 154, "clrmuxlc3": 154, "cm_trim": 136, "cm_trim_0": [66, 120], "cm_trim_1": [66, 120], "cmd_intx_impl": [140, 152], "cmd_intx_implementedpci": [140, 152], "cmd_offset": 145, "cmo": 14, "cmos0": 155, "cmos00": [74, 79], "cmos00111": 139, "cmos01": 74, "cmos111": [57, 93, 108, 123], "cmos1200011": 139, "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 118, 121, 123, 134, 137, 148, 149], "cmt0": 61, "cmt10": 61, "cmt_bot": 145, "cmt_bufg_": 134, "cmt_bufg_bot": [134, 137], "cmt_bufg_top": [134, 137], "cmt_clk010000000001000": 113, "cmt_clk100000010001000": 113, "cmt_clk1000001000010000": 113, "cmt_clk1100100000010000": 113, "cmt_clk1200000001010000": 113, "cmt_clk1300000100010000": 113, "cmt_clk1400010000010000": 113, "cmt_clk1501000000010000": 113, "cmt_clk1610000000100000": 113, "cmt_clk1700000010100000": 113, "cmt_clk1800001000100000": 113, "cmt_clk1900100000100000": 113, "cmt_clk2000000001100000": 113, "cmt_clk200001000001000": 113, "cmt_clk2100000100100000": 113, "cmt_clk2200010000100000": 113, "cmt_clk2301000000100000": 113, "cmt_clk2410000000000010": 113, "cmt_clk2500000010000010": 113, "cmt_clk2600001000000010": 113, "cmt_clk2700100000000010": 113, "cmt_clk300100000001000": 113, "cmt_clk400000001001000": 113, "cmt_clk500000100001000": 113, "cmt_clk600010000001000": 113, "cmt_clk701000000001000": 113, "cmt_clk810000000010000": 113, "cmt_clk900000010010000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_fifo": 149, "cmt_pll": 71, "cmt_top": 145, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 155, "cmuxosc": 155, "cnr": [58, 78, 87, 156], "co01": 154, "co1": 154, "co_dur": 145, "coarse_bypass": 145, "coarse_delai": 145, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 118, 134, 148], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 123, 139, 151, 159, 160, 161, 162, 163, 164, 165, 166, 168, 170], "columnar": 104, "com": [51, 86], "com_burst_v": 136, "com_burst_val_0": [66, 119, 120], "com_burst_val_1": [66, 119, 120], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 171], "combination": 81, "combinatori": [14, 36, 171], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 118, 123, 134, 148, 169, 171], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 136, "comma_10b_enable_0": [66, 119, 120], "comma_10b_enable_1": [66, 119, 120], "comma_10b_mask": [88, 89, 105], "comma_doubl": 136, "comma_double_0": [119, 120], "comma_double_0gtp_du": 119, "comma_double_0gtx_du": 120, "comma_double_1": [119, 120], "comma_double_1gtp_du": 119, "comma_double_1gtx_du": 120, "comma_doublegtx0": 136, "comma_doublegtx1": 136, "comma_doublegtx2": 136, "comma_doublegtx3": 136, "commerci": [17, 160], "common": [100, 151], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [148, 159], "companion": [44, 106], "compat": [12, 34, 169], "compens": 82, "complement": [108, 123, 139, 151], "complet": [12, 13, 16, 34, 35, 36, 104, 148, 159, 169], "complex": [15, 16, 148], "comput": [81, 159], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86, 102, 114], "concur00100101": 102, "concur1001": [64, 114], "concurdcm": [51, 86, 102], "concurdcm0": 114, "concurdcm1": 114, "config": [15, 16, 159], "config01": 114, "config10": 102, "config_fallback": [115, 131, 146], "config_r": [39, 48, 49, 75, 84, 101, 115, 131, 146, 155], "configrout": 124, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 118, 121, 123, 134, 137, 139, 149, 151, 156, 159, 168], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 123, 139, 148, 170, 171], "consecut": 134, "consid": [35, 104, 108, 118, 123, 134, 139, 148, 151], "consist": [35, 36, 81, 104, 118, 123, 134, 139, 148], "const": [13, 14, 35, 36, 46, 82, 170, 171], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 171, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 170, 171], "content": [35, 46, 82, 134], "contigu": [15, 16], "continu": [35, 151], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "control_0": [130, 145], "control_1": [130, 145], "control_2": [130, 145], "control_3": [130, 145], "control_4": [130, 145], "control_5": [130, 145], "control_6": 145, "control_7": 145, "convert": [15, 16], "convst": 109, "convstclk": [111, 127, 142], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 159, 160, 171], "cor": [41, 54, 78, 90, 106, 121, 137, 149], "cor1": [54, 67, 121, 137, 149], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 118, 121, 137, 149, 169, 171], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 148, 156], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 118, 123, 134, 139, 148, 151, 160, 171], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 118, 134, 148, 161, 162, 163, 164, 165, 166], "cout": [46, 82, 157], "coutmux": [60, 112, 128, 143], "coutmuxslice1": 60, "cover": [104, 118, 134, 148, 151, 171], "cp": [130, 145], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 162, 169], "cp_bias_trip_set": [130, 145], "cp_bias_trip_setmmcm": 145, "cp_bias_trip_setmmcm0": 130, "cp_bias_trip_setmmcm1": 130, "cp_bias_trip_setpl": 145, "cp_re": [130, 145], "cpl_timeout_disable_support": [140, 152], "cpl_timeout_ranges_support": [140, 152], "cpld": [0, 12, 34, 36, 169, 171], "cpmc440clk": 125, "cpmc440timerclock": 125, "cpmdcrclk": 125, "cpmdma0llclk": 125, "cpmdma1llclk": 125, "cpmdma2llclk": 125, "cpmdma3llclk": 125, "cpmfcmclk": 125, "cpminterconnectclk": 125, "cpmmcclk": 125, "cpmmcm": [130, 145], "cpmppcmplbclk": 125, "cpmppcs0plbclk": 125, "cpmppcs1plbclk": 125, "cppll": 145, "crammod": [60, 112, 128, 143], "crc": [39, 48, 49, 62, 84, 101, 115, 155], "crc32_0": [119, 120], "crc32_1": [119, 120], "crc32_2": [119, 120], "crc32_3": [119, 120], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [119, 120], "crc_start_of_pkt": [88, 89], "crcclk": [119, 120], "crcclkgtp_dual": 119, "crcclkgtx_dual": 120, "creat": [55, 87, 91, 104, 118], "create_edg": [98, 111, 129, 144], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 116, 132, 147], "cregdsp": [53, 65], "cregdsp0": [116, 132], "cregdsp1": 132, "crm_core_clk_freq_500": 153, "crm_core_clk_freq_500pcie3": 153, "crm_module_rst": [140, 152], "crm_user_clk_freq": 153, "crmcoreclk": 124, "crmcoreclkdlo": 124, "crmcoreclkpci": 124, "crmcoreclkrxo": 124, "crmcoreclkrxopci": 124, "crmcoreclktxo": 124, "crmcoreclktxopci": 124, "crmuserclk": 124, "crmuserclkrxo": 124, "crmuserclktxo": 124, "cross": [58, 91, 134, 148], "cs144": [20, 21, 34, 163, 169], "cs280": [24, 25, 34, 164, 169], "cs48": [26, 27, 28, 30, 31, 34, 161, 162, 169], "cs_b": [108, 123], "csi_b": [139, 151], "cso2pin": [50, 63], "cso_b": [123, 139, 151], "cspin": [98, 111, 127], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 121, 137, 149], "ctl1": [137, 149], "ctl_mode": 145, "ctl_modephaser_in0": 145, "ctl_modephaser_in1": 145, "ctl_modephaser_in2": 145, "ctl_modephaser_in3": 145, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [122, 138, 150], "ctrl00001": [138, 150], "ctrl1": [122, 138, 150], "ctrl10010": [138, 150], "ctrl2": 122, "ctrl3": 122, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 118, 148], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 128, 143], "cx0100": [112, 128, 143], "cx1": [60, 112], "cx10": [128, 143], "cx1010": 60, "cxt": 134, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 128, 143], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 128, 143], "cyinitslice0": [73, 99, 112, 128, 143], "cyinitslice1": [37, 46, 60, 73, 112, 128, 143], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 123, 139, 145, 151, 171], "d0": [132, 147], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 139, 147, 161, 162, 163, 164, 165, 166, 171], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d100001": [123, 139], "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d15": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d16": [3, 6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d17": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d18": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d19": [6, 7, 22, 23, 24, 25, 132, 147, 164, 165, 166], "d1ologic0": 139, "d1ologic1": 139, "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 139, 147, 161, 162, 163, 164, 165, 166], "d20": [6, 7, 22, 23, 24, 132, 147, 165, 166], "d21": [6, 7, 22, 23, 132, 147, 165, 166], "d22": [6, 7, 22, 23, 132, 147, 165, 166], "d23": [22, 23, 132, 147], "d24": [22, 23, 132, 147], "d25": [22, 23], "d26": [22, 23], "d2ologic0": [108, 139], "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 139, 147, 161, 162, 163, 164, 165, 166], "d3iob0": [108, 123], "d3iob1": [108, 123], "d3ologic0": 139, "d3ologic1": 139, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 139, 147, 161, 162, 163, 164, 165, 166], "d4iob0": 108, "d4iob1": 108, "d4ologic0": [123, 139], "d4ologic1": 123, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 123, 132, 139, 147, 163, 164, 165, 166], "d5ffinit": [128, 143], "d5ffinitslice0": [128, 143], "d5ffmux": [128, 143], "d5ffsr": [128, 143], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 128, "d5ilogic1": 139, "d5ologic0": [108, 123], "d5ologic1": [108, 123], "d5q0": 60, "d5q0100": [60, 128, 143], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 123, 132, 139, 147, 161, 162, 163, 164, 165, 166], "d6iob0": 123, "d6iob1": 123, "d6lut": [60, 112, 128, 143], "d6ologic1": 139, "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 132, 147, 161, 162, 163, 164, 165, 166], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 132, 147, 162, 163, 164, 165, 166], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 132, 147, 163, 164, 165, 166], "d_emu": 139, "d_emu_opt": 139, "d_in": [108, 123], "d_out_busi": 123, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 118, 121, 123, 134, 148, 155, 159, 160, 167, 171], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_ctl_a_n": 145, "data_ctl_a_nphy_control": 145, "data_ctl_b_n": 145, "data_ctl_c_n": 145, "data_ctl_c_nphy_control": 145, "data_ctl_d_n": 145, "data_ctl_n": 145, "data_ctl_nphaser_out0": 145, "data_ctl_nphaser_out1": 145, "data_ctl_nphaser_out2": 145, "data_ctl_nphaser_out3": 145, "data_l": [110, 126, 141], "data_r": [61, 108, 123, 139], "data_rd_cycl": 145, "data_u": [110, 126, 141], "data_width": [108, 123, 139], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 159, 168, 170, 171], "datain": [123, 139], "datain00100": 139, "datain1000": 123, "datainilogic0": 123, "datainilogic1": 123, "datainiob1": 139, "dataint": 155, "datap": [45, 59, 81, 96], "datap_l": [110, 126, 141], "datap_u": [110, 126, 141], "datareg": 13, "datastream": [17, 160], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 122, 138, 150, 154, 157], "dbl0001010000": 122, "dbl0001100000": 122, "dbl0010010000": 122, "dbl0010100000": 122, "dbl0100010000": 122, "dbl0100100000": 122, "dbl1000010000": 122, "dbl1000100000": 122, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 123, 139, 151], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 127], "dci_clk_enablemisc": 85, "dci_misc": [108, 123, 139], "dci_mod": [57, 93, 108, 123, 139], "dci_osc_sel": 50, "dci_t": [108, 123, 139], "dci_test_mux": 50, "dcireset": [98, 111, 127, 142], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 123, 139], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 119, 120, 127, 135, 136, 142], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 135, "dclkgtp": 66, "dclkgtp_dual": 119, "dclkgtx_dual": 120, "dclksysmon": 111, "dclkxadc": 142, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": [64, 114], "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": [71, 114], "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin001": 114, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": [64, 114], "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfb010": 114, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": [71, 114], "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": [102, 114], "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_clkdv_clkfx_alignmentdcm0": 114, "dcm_clkdv_clkfx_alignmentdcm1": 114, "dcm_clkfb_iodly_muxinsel": 114, "dcm_clkfb_iodly_muxinseldcm0": 114, "dcm_clkfb_iodly_muxinseldcm1": 114, "dcm_clkfb_iodly_muxout_sel": 114, "dcm_clkfb_iodly_muxout_seldcm0": 114, "dcm_clkfb_iodly_muxout_seldcm1": 114, "dcm_clkin_iodly_muxinsel": 114, "dcm_clkin_iodly_muxinseldcm0": 114, "dcm_clkin_iodly_muxinseldcm1": 114, "dcm_clkin_iodly_muxout_sel": 114, "dcm_clkin_iodly_muxout_seldcm0": 114, "dcm_clkin_iodly_muxout_seldcm1": 114, "dcm_clklost_en": 114, "dcm_clklost_endcm0": 114, "dcm_clklost_endcm1": 114, "dcm_com_pwc_fb_en": 114, "dcm_com_pwc_fb_endcm0": 114, "dcm_com_pwc_fb_endcm1": 114, "dcm_com_pwc_fb_tap": 114, "dcm_com_pwc_ref_en": 114, "dcm_com_pwc_ref_endcm0": 114, "dcm_com_pwc_ref_endcm1": 114, "dcm_com_pwc_ref_tap": 114, "dcm_common_msb_sel": 114, "dcm_enabl": 50, "dcm_ext_fb_en": [102, 114], "dcm_ext_fb_endcm": 102, "dcm_ext_fb_endcm0": 114, "dcm_ext_fb_endcm1": 114, "dcm_lock_high": 102, "dcm_lock_high_b": 114, "dcm_lock_high_bdcm0": 114, "dcm_lock_high_bdcm1": 114, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pll_rst_dcm": 114, "dcm_pll_rst_dcmdcm0": 114, "dcm_pll_rst_dcmdcm1": 114, "dcm_powerdown_common_en_b": 114, "dcm_powerdown_common_en_bdcm0": 114, "dcm_powerdown_common_en_bdcm1": 114, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_reg_pwrd_cfg": 114, "dcm_reg_pwrd_cfgdcm0": 114, "dcm_reg_pwrd_cfgdcm1": 114, "dcm_scanmod": 114, "dcm_scanmodedcm0": 114, "dcm_scanmodedcm1": 114, "dcm_shutdown": [48, 84, 101], "dcm_trim_cal": 114, "dcm_unused_taps_powerdown": [102, 114], "dcm_unused_taps_powerdowndcm": 102, "dcm_use_reg_readi": 114, "dcm_use_reg_readydcm0": 114, "dcm_use_reg_readydcm1": 114, "dcm_vbg_pd": [102, 114], "dcm_vbg_sel": [102, 114], "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": [102, 114], "dcm_vreg_enabledcm": 102, "dcm_vreg_enabledcm0": 114, "dcm_vreg_enabledcm1": 114, "dcm_vreg_phase_margin": 102, "dcm_vsply_valid_acc": 114, "dcm_wait_pll": 114, "dcm_wait_plldcm0": 114, "dcm_wait_plldcm1": 114, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcmt_bot": 145, "dcmt_top": 145, "dcr_autolock_en": 125, "dcr_test": 125, "dcremacclk": 117, "dcy0": [60, 112, 128, 143], "dcy0slice0": [112, 128, 143], "dcy0slice1": [60, 143], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 123, 139], "ddr00100": 123, "ddr01": 69, "ddr01100": [123, 139], "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr3_bypass": 139, "ddr3_bypassologic0": 139, "ddr3_data": 139, "ddr3_dataologic1": 139, "ddr_clk_edg": [108, 123, 139], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 136], "dec_mcomma_detect_0": [66, 119, 120], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 119, "dec_mcomma_detect_0gtx_du": 120, "dec_mcomma_detect_1": [66, 119, 120], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 119, "dec_mcomma_detect_1gtx_du": 120, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 136, "dec_mcomma_detectgtx1": 136, "dec_mcomma_detectgtx2": 136, "dec_mcomma_detectgtx3": 136, "dec_pcomma_detect": [88, 89, 105, 136], "dec_pcomma_detect_0": [66, 119, 120], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 119, "dec_pcomma_detect_0gtx_du": 120, "dec_pcomma_detect_1": [66, 119, 120], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 119, "dec_pcomma_detect_1gtx_du": 120, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 136, "dec_pcomma_detectgtx1": 136, "dec_pcomma_detectgtx2": 136, "dec_pcomma_detectgtx3": 136, "dec_valid_comma_onli": [88, 89, 105, 136], "dec_valid_comma_only_0": [66, 119, 120], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 119, "dec_valid_comma_only_0gtx_du": 120, "dec_valid_comma_only_1": [66, 119, 120], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 119, "dec_valid_comma_only_1gtx_du": 120, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 136, "dec_valid_comma_onlygtx1": 136, "dec_valid_comma_onlygtx2": 136, "dec_valid_comma_onlygtx3": 136, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 118, 123, 139, 148, 151, 160, 169, 171], "def": [15, 16], "default": [17, 35, 54], "default0": 139, "default00": 108, "default0011": 139, "default10": 123, "default_idelay_valu": [123, 139], "default_only1011": 113, "defin": 171, "definit": 151, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [161, 162, 163, 164, 165, 166], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 161, 162, 163, 164, 165, 166], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_pt_ut": [161, 162, 163, 164, 165, 166], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "delai": [14, 44, 47, 74, 78, 118, 121, 134, 137, 139, 148, 149], "delay0": 157, "delay_bypass": 151, "delay_bypassbufio0": 151, "delay_bypassbufio1": 151, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_line1": 114, "delay_src": [123, 139], "delay_typ": 139, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 123, "delaychain_osc10000": 139, "delayed_mem_ref0101": 145, "delayed_phase_ref11": 145, "delayed_phase_ref1100": 145, "delayed_ref01": 145, "delayed_ref0100": 145, "delayed_write0": 141, "delayed_write00": 126, "delaymux": 157, "delaymuxint": 157, "delaymuxiob2": 157, "delaymuxiob3": 157, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 118, 134, 148, 151, 160, 170, 171], "deriv": [12, 34, 56, 92, 169, 171], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 114, 129, 130, 144, 145, 160], "descript": [45, 99], "design": [12, 36, 58, 169, 171], "deskew_adjust": [54, 64, 90, 102, 114], "despit": 148, "destin": 36, "detail": [35, 58, 87, 96, 170], "determin": [12, 34, 35, 46, 82, 171], "dev_cap2_ari_forwarding_support": 152, "dev_cap2_ari_forwarding_supportedpci": 152, "dev_cap2_atomicop32_completer_support": 152, "dev_cap2_atomicop32_completer_supportedpci": 152, "dev_cap2_atomicop64_completer_support": 152, "dev_cap2_atomicop_routing_support": 152, "dev_cap2_cas128_completer_support": 152, "dev_cap2_cas128_completer_supportedpci": 152, "dev_cap2_endend_tlp_prefix_support": 152, "dev_cap2_endend_tlp_prefix_supportedpci": 152, "dev_cap2_extended_fmt_field_support": 152, "dev_cap2_ltr_mechanism_support": 152, "dev_cap2_ltr_mechanism_supportedpci": 152, "dev_cap2_max_endend_tlp_prefix": 152, "dev_cap2_no_ro_enabled_prpr_pass": 152, "dev_cap2_tph_completer_support": 152, "dev_cap_enable_slot_pwr_limit_scal": [140, 152], "dev_cap_enable_slot_pwr_limit_scalepci": [140, 152], "dev_cap_enable_slot_pwr_limit_valu": [140, 152], "dev_cap_endpoint_l0s_lat": [70, 140, 152], "dev_cap_endpoint_l1_lat": [70, 140, 152], "dev_cap_ext_tag_support": [70, 140, 152], "dev_cap_ext_tag_supportedpci": [140, 152], "dev_cap_function_level_reset_cap": [140, 152], "dev_cap_max_payload_support": [70, 140, 152], "dev_cap_phantom_functions_support": [70, 140, 152], "dev_cap_role_based_error": [70, 140, 152], "dev_cap_rsvd_14_12": [140, 152], "dev_cap_rsvd_17_16": [140, 152], "dev_cap_rsvd_31_29": [140, 152], "dev_control_aux_power_support": [140, 152], "dev_control_aux_power_supportedpci": 152, "dev_control_ext_tag_default": 152, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 121, 123, 137, 139, 149, 151, 159, 168, 170], "device_id": 140, "devicebram": 45, "devicecapabilityendpointl0slat": 124, "devicecapabilityendpointl1lat": 124, "devicedcm": [51, 52, 86], "deviceid": 124, "deviceiodelai": [123, 139], "devicemmcm": 130, "devicepl": 114, "deviceserialnumb": 124, "devicevalu": [47, 61], "devoid": 148, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [120, 136], "dfe_cfg": 136, "dfe_cfg_0": 120, "dfe_cfg_1": 120, "dfe_drp_en": 136, "dfe_drp_engtx0": 136, "dfe_drp_engtx1": 136, "dfe_drp_engtx2": 136, "dfe_drp_engtx3": 136, "dfe_train_ctrl_lane0": 135, "dfe_train_ctrl_lane1": 135, "dfe_train_ctrl_lane2": 135, "dfe_train_ctrl_lane3": 135, "dff": [14, 36, 171], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dff1": 15, "dff_latch": 128, "dff_latchslice0": 128, "dffce": 171, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 159], "dffinit": [112, 128, 143], "dffinitslice0": [112, 128, 143], "dffmux": [60, 112, 128, 143], "dffmuxslice1": 60, "dffsr": [112, 128, 143], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 143, "dffsrslice1": 128, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": [102, 114], "dfs_ave_freq_sample_interv": [102, 114], "dfs_c": [52, 64], "dfs_cfg_bypass": 114, "dfs_cfg_bypassdcm0": 114, "dfs_cfg_bypassdcm1": 114, "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_custom_fast_sync": 114, "dfs_early_lock": [102, 114], "dfs_early_lockdcm": 102, "dfs_early_lockdcm0": 114, "dfs_early_lockdcm1": 114, "dfs_en": 114, "dfs_en_relrst": 102, "dfs_en_relrst_b": 114, "dfs_en_relrst_bdcm0": 114, "dfs_en_relrst_bdcm1": 114, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_endcm0": 114, "dfs_endcm1": 114, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_fast_upd": 114, "dfs_fast_updatedcm0": 114, "dfs_fast_updatedcm1": 114, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102, 114], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": [64, 114], "dfs_frequency_modedcm1": [64, 114], "dfs_hardsync": 102, "dfs_hardsync_b": 114, "dfs_hf_trim_cal": 114, "dfs_jf_lower_limit": 114, "dfs_mpw_high": 114, "dfs_mpw_highdcm0": 114, "dfs_mpw_highdcm1": 114, "dfs_mpw_low": 114, "dfs_mpw_lowdcm0": 114, "dfs_mpw_lowdcm1": 114, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_osc_on_fx": 114, "dfs_osc_on_fxdcm0": 114, "dfs_osc_on_fxdcm1": 114, "dfs_oscillator_mod": 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154], "di0": [102, 154], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 154], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "di_dur": 145, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 148, 151, 160], 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"disable_aspm_l1_tim": [140, 152], "disable_aspm_l1_timerpci": [140, 152], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 140, 152], "disable_err_msg": 152, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 140, 152], "disable_id_checkpci": [140, 152], "disable_jtag": [127, 142], "disable_lane_revers": [140, 152], "disable_lane_reversalpci": 140, "disable_locked_filt": 152, "disable_ppm_filt": 152, "disable_ppm_filterpci": 152, "disable_rx_poisoned_resp": 152, "disable_rx_poisoned_resppci": 152, "disable_rx_tc_filt": [140, 152], "disable_scrambl": [70, 140, 152], "disable_scramblingpci": 152, "disable_seq_match": 145, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 171], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 134, 148], "distrubut": 134, "div12110": 69, "div2001": 69, "div201": [69, 145], "div4010": 69, "div410": [69, 145], "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divclk_edg": [130, 145], "divclk_edgemmcm": 145, "divclk_edgemmcm0": 130, "divclk_edgemmcm1": 130, "divclk_edgepl": 145, "divclk_ht": [130, 145], "divclk_lt": [130, 145], "divclk_nocount": [130, 145], "divclk_nocountmmcm": 145, "divclk_nocountmmcm0": 130, "divclk_nocountmmcm1": 130, "divclk_nocountpl": 145, "divid": [11, 12, 58, 61, 104, 118, 134, 148, 159, 171], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 169], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_cfg0": 135, "dll_cfg1": 135, "dll_clkfb_stopped_pwrd_en_b": 114, "dll_clkfb_stopped_pwrd_en_bdcm0": 114, "dll_clkfb_stopped_pwrd_en_bdcm1": 114, "dll_clkin_stopped_pwrd_en_b": 114, "dll_clkin_stopped_pwrd_en_bdcm0": 114, "dll_clkin_stopped_pwrd_en_bdcm1": 114, "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": [102, 114], "dll_deskew_lock_by1": [102, 114], "dll_deskew_lock_by1dcm": 102, "dll_deskew_lock_by1dcm0": 114, "dll_deskew_lock_by1dcm1": 114, "dll_deskew_maxtap": [102, 114], "dll_deskew_mintap": [102, 114], "dll_enabl": [51, 52, 64, 76, 86], "dll_enabledcm": [51, 52], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_etpp_hold": 114, "dll_etpp_holddcm0": 114, "dll_etpp_holddcm1": 114, "dll_fdbklost_en": 114, "dll_fdbklost_endcm0": 114, "dll_fdbklost_endcm1": 114, "dll_frequency_mod": [51, 52, 64, 86, 102, 114], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": [102, 114], "dll_pd_dly_sel": 102, "dll_period_lock_by1": [102, 114], "dll_period_lock_by1dcm": 102, "dll_period_lock_by1dcm0": 114, "dll_period_lock_by1dcm1": 114, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": [102, 114], "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": [102, 114], "dll_phase_shift_lock_by1": [102, 114], "dll_phase_shift_lock_by1dcm": 102, "dll_phase_shift_lock_by1dcm0": 114, "dll_phase_shift_lock_by1dcm1": 114, "dll_pwrd_on_scanmode_b": 114, "dll_pwrd_on_scanmode_bdcm0": 114, "dll_pwrd_on_scanmode_bdcm1": 114, "dll_pwrd_sticky_b": 114, "dll_pwrd_sticky_bdcm0": 114, "dll_pwrd_sticky_bdcm1": 114, "dll_settle_tim": [102, 114], "dll_spare": 102, "dll_synth_clock_spe": 114, "dll_tapinit_ctl": 114, "dll_test_mux_sel": [102, 114], "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dll_zd1_en": 114, "dll_zd1_endcm0": 114, "dll_zd1_endcm1": 114, "dll_zd1_jf_overflow_hold": 114, "dll_zd1_jf_overflow_holddcm0": 114, "dll_zd1_jf_overflow_holddcm1": 114, "dll_zd1_phase_sel_init": 114, "dll_zd1_pwc_en": 114, "dll_zd1_pwc_endcm0": 114, "dll_zd1_pwc_endcm1": 114, "dll_zd1_pwc_tap": 114, "dll_zd1_tap_init": 114, "dll_zd2_en": [102, 114], "dll_zd2_endcm": 102, "dll_zd2_endcm0": 114, "dll_zd2_endcm1": 114, "dll_zd2_jf_overflow_hold": 114, "dll_zd2_jf_overflow_holddcm0": 114, "dll_zd2_jf_overflow_holddcm1": 114, "dll_zd2_pwc_en": 114, "dll_zd2_pwc_endcm0": 114, "dll_zd2_pwc_endcm1": 114, "dll_zd2_pwc_tap": 114, "dll_zd2_tap_init": 114, "dllc": [51, 86], "dllp": 78, "dly0001": 139, "dly1110": 139, "dly2010": 139, "dly3000": 139, "dma0_control": 125, "dma0_rxchannelctrl": 125, "dma0_rxirqtim": 125, "dma0_txchannelctrl": 125, "dma0_txirqtim": 125, "dma1_control": 125, "dma1_rxchannelctrl": 125, "dma1_rxirqtim": 125, "dma1_txchannelctrl": 125, "dma1_txirqtim": 125, "dma2_control": 125, "dma2_rxchannelctrl": 125, "dma2_rxirqtim": 125, "dma2_txchannelctrl": 125, "dma2_txirqtim": 125, "dma3_control": 125, "dma3_rxchannelctrl": 125, "dma3_rxirqtim": 125, "dma3_txchannelctrl": 125, "dma3_txirqtim": 125, "dma_test": 125, "dmux": 154, "dna_opt": 63, "dna_port": [56, 63, 127, 142], "dnstream_link_num": [140, 152, 153], "do": [35, 46, 81, 82, 91, 96, 151], "do1": 154, "do11000": 154, "do11001": 154, "do11010": 154, "do11011": 154, "do_dur": 145, "doa": [81, 96], "doa0": [72, 96], "doa0int": 72, "doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 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136, 137, 138, 139, 142, 143, 146, 148, 149, 150, 156], "doe": [34, 148], "doesn": [16, 36, 46, 55, 58, 81, 91, 148, 171], "dologic0": 139, "domux": 154, "domuxlc2": 154, "don": [35, 36, 46, 55, 58, 148, 171], "done": [2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 34, 35, 36, 96, 108, 123, 139, 151], "done110": [39, 48, 75, 84, 101, 115, 131, 146], "done111": [49, 62], "done_act": 155, "done_cycl": [39, 48, 49, 62, 75, 84, 101, 115, 131, 146], "done_in00": 155, "done_pip": [39, 48, 49, 62, 75, 84, 101, 115, 131, 146], "done_signals_powerdown": [131, 146], "donein": 155, "donepin": [50, 63, 76, 85, 98, 111, 127, 142, 155], "donepinint": 155, "donepinmisc": 76, "dont_set1": 116, "dop": [81, 96], "dopa": 96, "doubl": [55, 91], "dout": 151, "dout0": 72, "dout000": 72, "dout0000": 72, "dout001": 72, "dout0int": 72, "dout1": 72, "dout10": 72, "dout100": 72, "dout1000": 72, "dout1001": 72, "dout10010": 72, "dout101": 72, "dout10int": 72, "dout11": 72, "dout1100": 72, "dout1101": 72, "dout11010": 72, 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4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 24, 25, 72, 73, 79, 154, 157, 162, 163, 164, 165, 166], "e100": 154, "e1000000000100": 107, "e1000000010": 79, "e10000010001": 107, "e10000100": [42, 55], "e1001": 72, "e101": 154, "e10100": 72, "e10110": 72, "e1011110": 157, "e10gbasekr_ld_coeff_upd_lane0": 135, "e10gbasekr_ld_coeff_upd_lane1": 135, "e10gbasekr_ld_coeff_upd_lane2": 135, "e10gbasekr_ld_coeff_upd_lane3": 135, "e10gbasekr_lp_coeff_upd_lane0": 135, "e10gbasekr_lp_coeff_upd_lane1": 135, "e10gbasekr_lp_coeff_upd_lane2": 135, "e10gbasekr_lp_coeff_upd_lane3": 135, "e10gbasekr_pma_ctrl_lane0": 135, "e10gbasekr_pma_ctrl_lane1": 135, "e10gbasekr_pma_ctrl_lane2": 135, "e10gbasekr_pma_ctrl_lane3": 135, "e10gbasekx_ctrl_lane0": 135, "e10gbasekx_ctrl_lane1": 135, "e10gbasekx_ctrl_lane2": 135, "e10gbasekx_ctrl_lane3": 135, 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135, "e10gbaser_pcs_seedb2_lane1": 135, "e10gbaser_pcs_seedb2_lane2": 135, "e10gbaser_pcs_seedb2_lane3": 135, "e10gbaser_pcs_seedb3_lane0": 135, "e10gbaser_pcs_seedb3_lane1": 135, "e10gbaser_pcs_seedb3_lane2": 135, "e10gbaser_pcs_seedb3_lane3": 135, "e10gbaser_pcs_test_ctrl_lane0": 135, "e10gbaser_pcs_test_ctrl_lane1": 135, "e10gbaser_pcs_test_ctrl_lane2": 135, "e10gbaser_pcs_test_ctrl_lane3": 135, "e10gbasex_pcs_tstctrl_lane0": 135, "e10gbasex_pcs_tstctrl_lane1": 135, "e10gbasex_pcs_tstctrl_lane2": 135, "e10gbasex_pcs_tstctrl_lane3": 135, "e10int": 154, "e11": [3, 6, 7, 20, 21, 24, 25, 72, 73, 79, 154, 157, 163, 164, 165, 166], "e11000100": [42, 55], "e1101110": 157, "e1101111111": 155, "e11100": 72, "e11100100": [42, 55], "e11111110": 157, "e12": [2, 3, 6, 7, 20, 21, 24, 25, 72, 73, 79, 163, 164, 165, 166], "e12010": 72, "e12101": 72, "e13": [2, 3, 6, 7, 20, 21, 24, 25, 72, 73, 79, 163, 164, 165, 166], "e13010": 72, "e13101": 72, "e14": [2, 3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e14010": 72, "e14101": 72, "e15": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e15101": 72, "e16": [3, 6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e16100": 72, "e16111": 72, "e17": [24, 25, 72, 73, 79, 164], "e17110": 72, "e17111": 72, "e18": [24, 25, 72, 73, 79, 164], "e18000": 72, "e18111": 72, "e19": [6, 7, 24, 25, 72, 73, 79, 164, 165, 166], "e19111": 72, "e1int": 154, "e2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e20": [6, 7, 24, 72, 73, 79, 165, 166], "e2001": 72, "e20101": 72, "e2011": 72, "e20110": 72, "e21": [6, 7, 72, 73, 79, 165, 166], "e21100": 72, "e2110111111": 155, "e21110": 72, "e22": [6, 7, 72, 73, 79, 165, 166], "e22100": 72, "e22110": 72, "e23": [22, 23, 72, 73, 79], "e23110": 72, "e24": [22, 23], "e25": [22, 23], "e26": [22, 23], "e3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e3001": 72, "e3111011111": 155, "e4": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 163, 164, 165, 166], "e4000": 72, "e401": 155, "e4010": 72, "e5": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e500": 155, "e5011": 72, "e6": [2, 3, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 155, 157, 161, 162, 164, 165, 166], "e6001": 72, "e601": 155, "e6011": 72, "e6int": 157, "e7": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 38, 42, 47, 55, 72, 73, 79, 83, 91, 107, 154, 155, 157, 161, 162, 164, 165, 166], "e700": 155, "e7011": 72, "e7int": 154, "e8": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 162, 164, 165, 166], "e8001": 72, "e8011": 72, "e8int": 154, "e9": [2, 3, 6, 7, 24, 25, 72, 73, 79, 83, 91, 107, 154, 157, 164, 165, 166], "e9100": 72, "e9111": 72, "each": [14, 15, 16, 34, 35, 36, 42, 46, 55, 58, 81, 82, 87, 91, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 171], "earlier": [34, 104, 169], "easi": [55, 91], "ebai": 35, "ecc": 106, "edg": [14, 55, 58, 87, 91, 118, 123, 134, 148], "ee0": [68, 138, 150], "ee1": [68, 138, 150], "ee2": [68, 138, 150], "ee3": [68, 138, 150], "efar0": [131, 146], "effect": [35, 36, 46, 81, 82, 91, 148, 171], "efuse1": [62, 115, 131, 146], "eg": [12, 55, 58, 91], "eight": 91, "eighth1011": 69, "eighth2111": 69, "eint": 154, "either": [14, 35, 36, 58, 81, 82, 134, 148, 160, 170, 171], "el0": [68, 122, 138, 150], "el1": [68, 122, 138, 150], "el2": [68, 122, 138, 150], "el3": [68, 138, 150], "electron": [159, 171], "element": [17, 160], "elimin": 58, "els": [15, 16, 36, 171], "em_cclk": 151, "emac": [117, 118, 133, 134], "emac0_1000basex_en": 117, "emac0_addrfilter_en": 117, "emac0_bytephi": 117, "emac0_configvec_79": 117, "emac0_dcrbaseaddr": 117, "emac0_funct": 117, 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117, "emac1_dcrbaseaddr": 117, "emac1_funct": 117, "emac1_gtloopback": 117, "emac1_host_en": 117, "emac1_linktimerv": 117, "emac1_ltcheck_dis": 117, "emac1_mdio_en": 117, "emac1_pauseaddr": 117, "emac1_phyinitautoneg_en": 117, "emac1_phyisol": 117, "emac1_phyloopbackmsb": 117, "emac1_phypowerdown": 117, "emac1_phyreset": 117, "emac1_rgmii_en": 117, "emac1_rx16bitclient_en": 117, "emac1_rx_en": 117, "emac1_rxflowctrl_en": 117, "emac1_rxhalfduplex": 117, "emac1_rxinbandfcs_en": 117, "emac1_rxjumboframe_en": 117, "emac1_rxreset": 117, "emac1_rxvlan_en": 117, "emac1_sgmii_en": 117, "emac1_speed_lsb": 117, "emac1_speed_msb": 117, "emac1_tx16bitclient_en": 117, "emac1_tx_en": 117, "emac1_txflowctrl_en": 117, "emac1_txhalfduplex": 117, "emac1_txifgadjust_en": 117, "emac1_txinbandfcs_en": 117, "emac1_txjumboframe_en": 117, "emac1_txreset": 117, "emac1_txvlan_en": 117, "emac1_unicastaddr": 117, "emac1_unidirection_en": 117, "emac1_useclken": 117, "emac_1000basex_en": 133, "emac_addrfilter_en": 133, "emac_bytephi": 133, "emac_configvec_79": 133, "emac_ctrllencheck_dis": 133, "emac_dcrbaseaddr": 133, "emac_funct": 133, "emac_gtloopback": 133, "emac_host_en": 133, "emac_linktimerv": 133, "emac_ltcheck_dis": 133, "emac_mdio_en": 133, "emac_pauseaddr": 133, "emac_phyinitautoneg_en": 133, "emac_phyisol": 133, "emac_phyloopbackmsb": 133, "emac_phypowerdown": 133, "emac_phyreset": 133, "emac_rgmii_en": 133, "emac_rx16bitclient_en": 133, "emac_rx_en": 133, "emac_rxflowctrl_en": 133, "emac_rxhalfduplex": 133, "emac_rxinbandfcs_en": 133, "emac_rxjumboframe_en": 133, "emac_rxreset": 133, "emac_rxvlan_en": 133, "emac_sgmii_en": 133, "emac_speed_lsb": 133, "emac_speed_msb": 133, "emac_tx16bitclient_en": 133, "emac_tx_en": 133, "emac_txflowctrl_en": 133, "emac_txhalfduplex": 133, "emac_txifgadjust_en": 133, "emac_txinbandfcs_en": 133, "emac_txjumboframe_en": 133, "emac_txreset": 133, "emac_txvlan_en": 133, "emac_unicastaddr": 133, "emac_unidirection_en": 133, "emac_useclken": 133, "empti": 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"en_oserdes_rstphaser_out2": 145, "en_oserdes_rstphaser_out3": 145, "en_porb": 49, "en_pwctl": 51, "en_pwctldcm": 51, "en_pwrgate_l": 141, "en_pwrgate_u": 141, "en_rel": 97, "en_relpmcd1": 97, "en_relrst_b": 51, "en_relrst_bdcm": 51, "en_rstram_a": 59, "en_rstram_b": 59, "en_sdbiterr_init_v6": 141, "en_suspend": [49, 62], "en_sw_gsr": [49, 62], "en_syn": [110, 126, 141], "en_test_r": 145, "en_tst_regout_dly_sel": 141, "en_tstblclamp": 126, "en_tstblclamp_rd": 141, "en_tstblclampbram": 126, "en_tstblclmp_ww": 141, "en_tstblpc_dli": 141, "en_tstbramrst": [126, 141], "en_tstbramrstbram": 126, "en_tstextclk": 141, "en_tstpulsepu_dli": 141, "en_tstrefbl": 126, "en_tstrfmode_dli": 141, "en_tstrsrw": 126, "en_tstrstc_pw": 141, "en_tstsnm": 141, "en_vco_div1": [130, 145], "en_vco_div1mmcm": 145, "en_vco_div6": [130, 145], "en_vco_div6mmcm0": 130, "en_vco_div6mmcm1": 130, "en_vco_div6pl": 145, "en_vtest": [101, 131], "ena": 96, "enabl": [12, 14, 16, 33, 34, 35, 36, 40, 43, 46, 47, 49, 50, 51, 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109, "init_68": 109, "init_69": 109, "init_6a": 109, "init_6b": 109, "init_6c": 109, "init_6d": 109, "init_6f": 109, "init_a": [45, 59, 81, 96], "init_a_l": [110, 126, 141], "init_a_u": [110, 126, 141], "init_b": [45, 59, 81, 96, 139, 151], "init_b_l": [110, 126, 141], "init_b_u": [110, 126, 141], "init_bitslip": 139, "init_bitslipcnt": [108, 123, 139], "init_c": [108, 123, 139], "init_dly_cnt": 139, "init_fifo_addr": 139, "init_fifo_reset": 139, "init_loadcnt": [108, 123, 139], "init_orank1": 139, "init_orank2_parti": 139, "init_out": [98, 111, 129, 130, 144, 145], "init_outbufgctrl0": 98, "init_outbufgctrl1": 98, "init_outbufgctrl10": 98, "init_outbufgctrl11": 98, "init_outbufgctrl12": 98, "init_outbufgctrl13": 98, "init_outbufgctrl14": 98, "init_outbufgctrl15": 98, "init_outbufgctrl16": 98, "init_outbufgctrl17": 98, "init_outbufgctrl18": 98, "init_outbufgctrl19": 98, "init_outbufgctrl2": 98, "init_outbufgctrl20": 98, "init_outbufgctrl21": 98, "init_outbufgctrl22": 98, "init_outbufgctrl23": 98, "init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_outbufhce_r0": 130, "init_outbufhce_r10": 130, "init_outbufhce_r2": 130, "init_outbufhce_r4": 130, "init_outbufhce_r6": 130, "init_outbufhce_r8": 130, "init_outbufmrce1": 145, "init_outmmcm0": 130, "init_outmmcm1": 130, "init_pipe_data0": 139, "init_pipe_data1": 139, "init_rank1_parti": [108, 123, 139], "init_rank2": [108, 123, 139], "init_rank3": [108, 123, 139], "init_signals_error": [131, 146], "init_skip": 62, "init_trank1": 139, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 171], "initp_xx": [81, 96], "initpin": [98, 111, 127, 142], "initpinmisc": 111, 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153, 154, 155, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 171], "invert_clk_do": 96, "invert_clk_doa_reg": 96, "invert_clk_dob_reg": 96, "invert_zd1_custom": 51, "invert_zd1_customdcm": 51, "inverted0": 69, "involv": [15, 16, 36, 87, 104, 118, 171], "io": [17, 54, 55, 56, 78, 81, 90, 91, 92, 104, 106, 108, 118, 121, 123, 134, 137, 155, 156], "io0": [79, 157], "io00011": 139, "io0011": 123, "io1": [79, 157], "io2": [79, 157], "io3": [79, 157], "io_mc": [159, 160, 170], "io_speci": [17, 160], "io_special_overrid": 17, "io_var_loadable11111": 139, "iob": [10, 11, 17, 35, 36, 47, 58, 78, 83, 87, 91, 106, 108, 121, 123, 139, 151, 160, 168, 170], "iob0": [57, 93, 108, 123, 139, 151, 157], "iob1": [57, 79, 93, 108, 123, 139, 151, 157], "iob2": [57, 79, 93, 157], "iob3": [57, 79, 93, 157], "iob4": [57, 93], "iob5": [57, 93], "iob6": 57, "iob7": 57, "iob_": [17, 34, 36, 160, 171], "iob_0_0": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], 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19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 161, 162, 163, 164, 165, 166], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 162, 163, 164, 165, 166], "p_d": 81, "packag": [11, 17, 33, 36, 56, 148, 151, 160, 168, 170], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 123, 139, 151, 160, 169, 171], "pair": [17, 58, 82, 96, 104, 108, 123, 139, 148, 151, 160], "parallel": [16, 108, 123, 139, 151], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 123, 148, 161, 162, 163, 164, 165, 166, 168, 170], "partial": [34, 81, 96, 170], "particip": 36, "particular": [17, 160], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 134, 148, 154, 155, 157, 158], "pass0": [64, 71, 114], "pass00000000": 102, "pass00000000000001": 113, "pass00000000001": 113, "pass00000001": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 116, "path": [36, 81], "pattern": [87, 116, 132, 147], "pattern0": [116, 132, 147], "pbbaseptr": 124, "pbcapabilitydw0basepow": 124, "pbcapabilitydw0datascal": 124, "pbcapabilitydw0pmst": 124, "pbcapabilitydw0pmsubst": 124, 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123, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 123, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 123, "pci66_3000000000000": 123, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 123, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, 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"pcs_bit_slip": 105, "pcs_com_cfg": 119, "pcs_ctrl1_lane0": 135, "pcs_ctrl1_lane1": 135, "pcs_ctrl1_lane2": 135, "pcs_ctrl1_lane3": 135, "pcs_ctrl2_lane0": 135, "pcs_ctrl2_lane1": 135, "pcs_ctrl2_lane2": 135, "pcs_ctrl2_lane3": 135, "pcs_misc_cfg_0_lane0": 135, "pcs_misc_cfg_0_lane1": 135, "pcs_misc_cfg_0_lane2": 135, "pcs_misc_cfg_0_lane3": 135, "pcs_misc_cfg_1_lane0": 135, "pcs_misc_cfg_1_lane1": 135, "pcs_misc_cfg_1_lane2": 135, "pcs_misc_cfg_1_lane3": 135, "pcs_mode_lane0": 135, "pcs_mode_lane1": 135, "pcs_mode_lane2": 135, "pcs_mode_lane3": 135, "pcs_reset_1_lane0": 135, "pcs_reset_1_lane1": 135, "pcs_reset_1_lane2": 135, "pcs_reset_1_lane3": 135, "pcs_reset_lane0": 135, "pcs_reset_lane1": 135, "pcs_reset_lane2": 135, "pcs_reset_lane3": 135, "pcs_type_lane0": 135, "pcs_type_lane1": 135, "pcs_type_lane2": 135, "pcs_type_lane3": 135, "pd_revers": 145, "pdelidle_drp_en": 136, "pdelidle_drp_en_0": 66, "pdelidle_drp_en_1": 66, "pdelidle_drp_en_1gtp": 66, "pdrive": [57, 79, 93, 108, 123, 139], "pdriveiostd": [57, 79, 93, 108, 123, 139], "pdstatuspin": 76, "pdstatuspinmisc": 76, "pent": 122, "pent00010100": 122, "pent00011000": 122, "pent00100100": 122, "pent00101000": 122, "pent01000100": 122, "pent01001000": 122, "pent10000100": 122, "pent10001000": 122, "per": [12, 14, 17, 33, 34, 35, 36, 46, 55, 56, 58, 81, 91, 92, 96, 104, 108, 118, 123, 134, 139, 148, 151, 159, 160, 170, 171], "perf0": [130, 139, 145, 151], "perf0001": 136, "perf01": 139, "perf0_il": 130, "perf0_ilmmcm0": 130, "perf0_ilmmcm1": 130, "perf0_ir": 130, "perf0_irmmcm0": 130, "perf0_irmmcm1": 130, "perf0_ol": 130, "perf0_olmmcm0": 130, "perf0_olmmcm1": 130, "perf0_or": 130, "perf0_ormmcm0": 130, "perf0_ormmcm1": 130, "perf0hclk_ioi": 139, "perf1": [130, 139, 145, 151], "perf1011": 136, "perf11": 139, "perf1_il": 130, "perf1_ilmmcm0": 130, "perf1_ilmmcm1": 130, "perf1_ir": 130, "perf1_irmmcm0": 130, "perf1_irmmcm1": 130, "perf1_ol": 130, "perf1_olmmcm0": 130, "perf1_olmmcm1": 130, "perf1_or": 130, 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"pf0_dpa_cap_sub_state_power_allocation4": 153, "pf0_dpa_cap_sub_state_power_allocation5": 153, "pf0_dpa_cap_sub_state_power_allocation6": 153, "pf0_dpa_cap_sub_state_power_allocation7": 153, "pf0_dpa_cap_v": 153, "pf0_dsn_cap_nextptr": 153, "pf0_expansion_rom_aperture_s": 153, "pf0_interrupt_lin": 153, "pf0_interrupt_pin": 153, "pf0_ltr_cap_max_nosnoop_lat": 153, "pf0_ltr_cap_max_snoop_lat": 153, "pf0_ltr_cap_nextptr": 153, "pf0_ltr_cap_ver": 153, "pf0_msi_cap_nextptr": 153, "pf0_msix_cap_nextptr": 153, "pf0_msix_cap_pba_offset": 153, "pf0_msix_cap_table_offset": 153, "pf0_msix_cap_table_s": 153, "pf0_pb_cap_nextptr": 153, "pf0_pb_cap_ver": 153, "pf0_pm_cap_id": 153, "pf0_pm_cap_nextptr": 153, "pf0_pm_cap_ver_id": 153, "pf0_rbar_cap_index0": 153, "pf0_rbar_cap_index1": 153, "pf0_rbar_cap_index2": 153, "pf0_rbar_cap_nextptr": 153, "pf0_rbar_cap_size0": 153, "pf0_rbar_cap_size1": 153, "pf0_rbar_cap_size2": 153, "pf0_rbar_cap_v": 153, "pf0_rbar_num": 153, "pf0_revision_id": 153, "pf0_sriov_bar0_aperture_s": 153, "pf0_sriov_bar0_control": 153, "pf0_sriov_bar1_aperture_s": 153, "pf0_sriov_bar1_control": 153, "pf0_sriov_bar2_aperture_s": 153, "pf0_sriov_bar2_control": 153, "pf0_sriov_bar3_aperture_s": 153, "pf0_sriov_bar3_control": 153, "pf0_sriov_bar4_aperture_s": 153, "pf0_sriov_bar4_control": 153, "pf0_sriov_bar5_aperture_s": 153, "pf0_sriov_bar5_control": 153, "pf0_sriov_cap_initial_vf": 153, "pf0_sriov_cap_nextptr": 153, "pf0_sriov_cap_total_vf": 153, "pf0_sriov_cap_v": 153, "pf0_sriov_first_vf_offset": 153, "pf0_sriov_func_dep_link": 153, "pf0_sriov_supported_page_s": 153, "pf0_sriov_vf_device_id": 153, "pf0_subsystem_id": 153, "pf0_tphr_cap_nextptr": 153, "pf0_tphr_cap_st_mode_sel": 153, "pf0_tphr_cap_st_table_loc": 153, "pf0_tphr_cap_st_table_s": 153, "pf0_tphr_cap_ver": 153, "pf0_vc_cap_nextptr": 153, "pf0_vc_cap_ver": 153, "pf1_aer_cap_nextptr": 153, "pf1_ari_cap_next_func": 153, "pf1_ari_cap_nextptr": 153, "pf1_bar0_aperture_s": 153, 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"pf1_sriov_cap_nextptr": 153, "pf1_sriov_cap_total_vf": 153, "pf1_sriov_cap_v": 153, "pf1_sriov_first_vf_offset": 153, "pf1_sriov_func_dep_link": 153, "pf1_sriov_supported_page_s": 153, "pf1_sriov_vf_device_id": 153, "pf1_subsystem_id": 153, "pf1_tphr_cap_nextptr": 153, "pf1_tphr_cap_st_mode_sel": 153, "pf1_tphr_cap_st_table_loc": 153, "pf1_tphr_cap_st_table_s": 153, "pf1_tphr_cap_ver": 153, "pfd": [130, 145], "pgate011": 50, "pgate0111": 50, "pgl0_lane": 140, "pgl1_lane": 140, "pgl2_lane": 140, "pgl3_lane": 140, "pgl4_lane": 140, "pgl5_lane": 140, "pgl6_lane": 140, "pgl7_lane": 140, "phase": [44, 67], "phase_freq_lock0": 114, "phase_freq_lock00": 102, "phase_ref0": 145, "phase_ref00": 145, "phase_ref0000": 145, "phase_shift": [51, 52, 64, 86, 102, 114], "phase_shift_neg": [51, 52, 64, 86, 102, 114], "phase_shift_negativedcm": [51, 102], "phase_shift_negativedcm0": 114, "phase_shift_negativedcm1": 114, "phasealign_drp_en": 136, "phasealign_drp_en_0": 66, "phasealign_drp_en_1": 66, "phasealign_drp_en_1gtp": 66, "phaser1": 145, "phaser_in0": 145, "phaser_in1": 145, "phaser_in2": 145, "phaser_in3": 145, "phaser_in_en": 145, "phaser_in_enphaser_in0": 145, "phaser_in_enphaser_in1": 145, "phaser_in_enphaser_in2": 145, "phaser_in_enphaser_in3": 145, "phaser_in_rclk001001": 145, "phaser_in_rclk101010": 145, "phaser_in_rclk201100": 145, "phaser_in_rclk310100": 145, "phaser_out0": 145, "phaser_out1": 145, "phaser_out2": 145, "phaser_out3": 145, "phaser_out_en": 145, "phaser_ref": 145, "phaser_ref_bounce0": 145, "phaser_ref_bounce000100010000": 145, "phaser_ref_bounce001000000010000": 145, "phaser_ref_bounce1": 145, "phaser_ref_bounce100100100000": 145, "phaser_ref_bounce110000000010000": 145, "phaser_ref_bounce2": 145, "phaser_ref_bounce201000000000100": 145, "phaser_ref_bounce201000010000": 145, "phaser_ref_bounce3": 145, "phaser_ref_bounce301000100000": 145, "phaser_ref_bounce310000000000100": 145, "phaser_ref_en": 145, "phaser_ref_misc": 145, "phaserefclk": 145, "phi": 35, "philip": [169, 170], "phy_control": 145, "phy_count_en": 145, "phyemac0gtxclk": 117, "phyemac0mclkin": 117, "phyemac0miitxclk": 117, "phyemac0rxclk": 117, "phyemac0txgmiimiiclkin": 117, "phyemac1gtxclk": 117, "phyemac1mclkin": 117, "phyemac1miitxclk": 117, "phyemac1rxclk": 117, "phyemac1txgmiimiiclkin": 117, "physic": [55, 159], "pick": [46, 82, 96], "picosecond": [17, 160], "pin": [10, 11, 14, 17, 32, 33, 36, 46, 63, 81, 82, 91, 96, 108, 123, 139, 151, 160, 167, 168, 170, 171], "pipe1": 136, "pipelin": [56, 81, 96], "pitch": [12, 34, 169], "pl_auto_config": [140, 152], "pl_center": [51, 86], "pl_eq_adapt_iter_count": 153, "pl_eq_adapt_reject_retry_count": 153, "pl_fast_train": [140, 152], "pl_fast_trainpci": [140, 152], "pl_lane0_eq_control": 153, "pl_lane1_eq_control": 153, "pl_lane2_eq_control": 153, "pl_lane3_eq_control": 153, "pl_lane4_eq_control": 153, "pl_lane5_eq_control": 153, "pl_lane6_eq_control": 153, "pl_lane7_eq_control": 153, "pl_link_cap_max_link_spe": 153, "pl_link_cap_max_link_width": 153, "pl_n_fts_comclk_gen1": 153, "pl_n_fts_comclk_gen2": 153, "pl_n_fts_comclk_gen3": 153, "pl_n_fts_gen1": 153, "pl_n_fts_gen2": 153, "pl_n_fts_gen3": 153, "pla": [159, 171], "place": [12, 35, 36, 55, 58, 91, 104, 151], "placement": 58, "plain": [12, 17, 34, 58, 87, 92, 96, 148, 160, 169], "plain0": [4, 5, 8, 9], "plain00": [2, 3, 6, 7], "plane": [81, 96, 159, 160], "plastic": [12, 34, 169], "platic": 34, "plb_test": 125, "plcc": [12, 34, 169], "pll": [71, 114, 149], "pll00": 66, "pll0_clkout0": 61, "pll0_clkout0_d": 61, "pll0_clkout0_u": 61, "pll0_clkout1": 61, "pll0_clkout1_d": 61, "pll0_clkout1_u": 61, "pll0d_clkout000": 61, "pll0d_clkout0111": 61, "pll0d_clkout101": 61, "pll0d_clkout1110": 61, "pll0d_locked00": 61, "pll0d_locked1": 61, "pll0u_clkout0000": 61, "pll0u_clkout001": 61, "pll0u_clkout100": 61, "pll0u_clkout1001": 61, "pll0u_locked1": 61, "pll0u_locked11": 61, "pll11": 66, "pll1_clkout0": 61, "pll1_clkout0_d": 61, "pll1_clkout0_u": 61, "pll1_clkout1": 61, "pll1_clkout1_d": 61, "pll1_clkout1_u": 61, "pll1d_clkout010": 61, "pll1d_clkout0101": 61, "pll1d_clkout1100": 61, "pll1d_clkout111": 61, "pll1d_locked0": 61, "pll1d_locked01": 61, "pll1u_clkout0010": 61, "pll1u_clkout011": 61, "pll1u_clkout1011": 61, "pll1u_clkout110": 61, "pll1u_locked0": 61, "pll1u_locked10": 61, "pll_add_leakag": 71, "pll_avdd_comp_set": [71, 114], "pll_avdd_vbg_pd": 114, "pll_avdd_vbg_sel": 114, "pll_bufpll": 61, "pll_bufpll_b": 67, "pll_bufpll_out0": 67, "pll_bufpll_out1": 67, "pll_bufpll_t": 67, "pll_cfg0": 135, "pll_cfg1": 135, "pll_cfg2": 135, "pll_clamp_bypass": 71, "pll_clamp_ref_sel": 71, "pll_clk0mx": [71, 114], "pll_clk1mx": [71, 114], "pll_clk2mx": [71, 114], "pll_clk3mx": [71, 114], "pll_clk4mx": [71, 114], "pll_clk5mx": [71, 114], "pll_clk_lost_detect": 71, "pll_clkburst_cnt": [71, 114], "pll_clkburst_en": [71, 114], "pll_clkcntrl": 114, "pll_clkcntrlpll": 114, "pll_clkfbmx": [71, 114], "pll_clkfbout00000100100000": 145, "pll_clkfbout001010": 71, "pll_clkfbout2_dt": [71, 114], "pll_clkfbout2_edg": [71, 114], "pll_clkfbout2_ht": [71, 114], "pll_clkfbout2_lt": [71, 114], "pll_clkfbout2_nocount": [71, 114], "pll_clkfbout2_nocountpl": 114, "pll_clkfbout_dt": [71, 114], "pll_clkfbout_edg": [71, 114], "pll_clkfbout_en": [71, 114], "pll_clkfbout_ht": [71, 114], "pll_clkfbout_lt": [71, 114], "pll_clkfbout_nocount": [71, 114], "pll_clkfbout_nocountpl": 114, "pll_clkfbout_pm": [71, 114], "pll_clkin100": 114, "pll_clkinfb101": 114, "pll_clkout0000": 145, "pll_clkout000000110000000": 145, "pll_clkout0001": 145, "pll_clkout0010010": 71, "pll_clkout0_dt": [71, 114], "pll_clkout0_edg": [71, 114], "pll_clkout0_en": [71, 114], "pll_clkout0_ht": [71, 114], "pll_clkout0_lt": [71, 114], "pll_clkout0_nocount": [71, 114], "pll_clkout0_nocountpl": 114, "pll_clkout0_pm": [71, 114], "pll_clkout1000": 145, "pll_clkout100001010000000": 145, "pll_clkout1010100": 71, "pll_clkout1011": 145, "pll_clkout1_dt": [71, 114], "pll_clkout1_edg": [71, 114], "pll_clkout1_en": [71, 114], "pll_clkout1_ht": [71, 114], "pll_clkout1_lt": [71, 114], "pll_clkout1_nocount": [71, 114], "pll_clkout1_nocountpl": 114, "pll_clkout1_pm": [71, 114], "pll_clkout2000": 145, "pll_clkout200010010000000": 145, "pll_clkout2010001": 71, "pll_clkout2101": 145, "pll_clkout2_dt": [71, 114], "pll_clkout2_edg": [71, 114], "pll_clkout2_en": [71, 114], "pll_clkout2_ht": [71, 114], "pll_clkout2_lt": [71, 114], "pll_clkout2_nocount": [71, 114], "pll_clkout2_nocountpl": 114, "pll_clkout2_pm": [71, 114], "pll_clkout300100010000000": 145, "pll_clkout3100010": 71, "pll_clkout3111": 145, "pll_clkout3_dt": [71, 114], "pll_clkout3_edg": [71, 114], "pll_clkout3_en": [71, 114], "pll_clkout3_ht": [71, 114], "pll_clkout3_lt": [71, 114], "pll_clkout3_nocount": [71, 114], "pll_clkout3_nocountpl": 114, "pll_clkout3_pm": [71, 114], "pll_clkout401000010000000": 145, "pll_clkout4100100": 71, "pll_clkout4_dt": [71, 114], "pll_clkout4_edg": [71, 114], "pll_clkout4_en": [71, 114], "pll_clkout4_ht": [71, 114], "pll_clkout4_lt": [71, 114], "pll_clkout4_nocount": [71, 114], "pll_clkout4_nocountpl": 114, "pll_clkout4_pm": [71, 114], "pll_clkout510000010000000": 145, "pll_clkout5100001": 71, "pll_clkout5_dt": [71, 114], "pll_clkout5_edg": [71, 114], "pll_clkout5_en": [71, 114], "pll_clkout5_ht": [71, 114], "pll_clkout5_lt": [71, 114], "pll_clkout5_nocount": [71, 114], "pll_clkout5_nocountpl": 114, "pll_clkout5_pm": [71, 114], "pll_com_cfg": 120, "pll_com_cfg_0": 66, "pll_com_cfg_1": 66, "pll_cp": [71, 114], "pll_cp_bias_trip_shift": [71, 114], "pll_cp_bias_trip_shiftpl": 114, "pll_cp_cfg": 120, "pll_cp_cfg_0": 66, "pll_cp_cfg_1": 66, "pll_cp_re": [71, 114], "pll_cp_repl": 71, "pll_cp_replpll": 71, "pll_cppll": [71, 114], "pll_direct_path_cntrl": [71, 114], "pll_divclk_dt": 114, "pll_divclk_edg": [71, 114], "pll_divclk_edgepl": 114, "pll_divclk_en": 71, "pll_divclk_ht": [71, 114], "pll_divclk_lt": [71, 114], "pll_divclk_nocount": [71, 114], "pll_divsel_fb": [119, 120], "pll_divsel_fb_0": 66, "pll_divsel_fb_1": 66, "pll_divsel_ref": [119, 120], "pll_divsel_ref_0": 66, "pll_divsel_ref_1": 66, "pll_drp_en": 136, "pll_drp_en_0": 66, "pll_drp_en_1": 66, "pll_drp_en_1gtp": 66, "pll_dvdd_comp_set": [71, 114], "pll_dvdd_vbg_pd": 114, "pll_dvdd_vbg_sel": 114, "pll_en": [71, 114, 145], "pll_en_cntrl": [71, 114], "pll_en_dli": [71, 114], "pll_en_dlypl": 114, "pll_en_leakag": 71, "pll_en_tclk0": [71, 114], "pll_en_tclk0pll": 114, "pll_en_tclk1": [71, 114], "pll_en_tclk2": [71, 114], "pll_en_tclk3": [71, 114], "pll_en_tclk3pll": 114, "pll_en_tclk4": 114, "pll_en_tclk4pll": 114, "pll_en_vco0": [71, 114], "pll_en_vco1": [71, 114], "pll_en_vco2": [71, 114], "pll_en_vco2pl": 114, "pll_en_vco3": [71, 114], "pll_en_vco3pl": 114, "pll_en_vco4": [71, 114], "pll_en_vco5": [71, 114], "pll_en_vco6": [71, 114], "pll_en_vco6pl": 114, "pll_en_vco7": [71, 114], "pll_en_vco7pl": 114, "pll_en_vco_div1": [71, 114], "pll_en_vco_div1pl": 114, "pll_en_vco_div6": [71, 114], "pll_en_vco_div6pl": 114, "pll_enpll": 145, "pll_fb_dccen": 120, "pll_fb_dccengtx_dual": 120, "pll_flock": 114, "pll_in_dly_mx_sel": [71, 114], "pll_in_dly_set": [71, 114], "pll_inc_flock": 114, "pll_inc_slock": 114, "pll_inc_slockpl": 114, "pll_intfb": [71, 114], "pll_lf_nen": 114, "pll_lf_pen": 114, "pll_lfhf": [71, 114], "pll_lkdet_cfg": 120, "pll_lock_cnt": [71, 114], "pll_lock_cnt_rst_fast": 114, "pll_lock_cntpll": 71, "pll_lock_fb_dli": 71, "pll_lock_fb_dlypl": 71, "pll_lock_fb_p1": 114, "pll_lock_fb_p2": 114, "pll_lock_ref_dli": 71, "pll_lock_ref_dlypl": 71, "pll_lock_ref_p1": 114, "pll_lock_ref_p2": 114, "pll_lock_sat_high": 71, "pll_lock_sat_highpl": 71, "pll_man_lf_en": [71, 114], "pll_misc": 114, "pll_nbti_en": [71, 114], "pll_nbti_enpl": 114, "pll_pfd_cntrl": [71, 114], "pll_pfd_dly": [71, 114], "pll_pmcd_mode": 114, "pll_pmcd_modepl": 114, "pll_pwrd_cfg": [71, 114], "pll_re": [71, 114], "pll_reg_input": 71, "pll_respll": [71, 114], "pll_rxdivsel_out_0": [66, 119, 120], "pll_rxdivsel_out_1": [66, 119, 120], "pll_sata_0": [66, 119, 120], "pll_sata_0gtp": 66, "pll_sata_0gtp_du": 119, "pll_sata_0gtx_du": 120, "pll_sata_1": [66, 119, 120], "pll_sata_1gtp": 66, "pll_sata_1gtp_du": 119, "pll_sata_1gtx_du": 120, "pll_sel_slipd": [71, 114], "pll_source_0": 66, "pll_source_0gtp": 66, "pll_source_1": 66, "pll_source_1gtp": 66, "pll_startup_en": [119, 120], "pll_startup_en_0": 66, "pll_startup_en_0gtp": 66, "pll_startup_en_1": 66, "pll_startup_en_1gtp": 66, "pll_startup_engtp_du": 119, "pll_startup_engtx_du": 120, "pll_tck4_sel": 114, "pll_tdcc_cfg": 120, "pll_test_clk_out001100": 71, "pll_test_in_window": 71, "pll_tmuxout00001000100000": 145, "pll_txdivsel_comm_out": 119, "pll_txdivsel_out_0": [66, 119, 120], "pll_txdivsel_out_1": [66, 119, 120], "pll_unlock_cnt": [71, 114], "pll_unlock_cnt_rst_fast": 114, "pll_unlock_cnt_rst_fastpl": 114, "pll_vdd_sel": 71, "pll_vlfhigh_di": [71, 114], "pll_vlfhigh_displ": 114, "pllclk0010": 66, "pllclk1110": 66, "pllin": 61, "pllin0000": 61, "pllin1001": 61, "pllin2010": 61, "pllin3011": 61, "pllin4100": 61, "pllin5101": 61, "plllkdet_cfg": 119, "plllkdet_cfg_0": 66, "plllkdet_cfg_1": 66, "plm_auto_config": 70, "plu": [104, 118, 134, 148], "pm_aspm_fastexit": 152, "pm_aspm_fastexitpci": 152, "pm_aspml0s_timeout": [152, 153], "pm_aspml0s_timeout_en": 152, "pm_aspml0s_timeout_func": 152, "pm_aspml1_entry_delai": 153, "pm_base_ptr": [140, 152], "pm_cap_auxcurr": [70, 140, 152], "pm_cap_d1support": [70, 140, 152], "pm_cap_d2support": [70, 140, 152], "pm_cap_d2supportpci": [140, 152], "pm_cap_dsi": [70, 140, 152], "pm_cap_id": [140, 152], "pm_cap_nextptr": [140, 152], "pm_cap_on": [140, 152], "pm_cap_onpci": [140, 152], "pm_cap_pme_clock": [70, 140, 152], "pm_cap_pmesupport": [70, 140, 152], "pm_cap_rsvd_04": [140, 152], "pm_cap_vers": [70, 140, 152], "pm_csr_b2b3": [140, 152], "pm_csr_bpccen": [140, 152], "pm_csr_bpccenpci": [140, 152], "pm_csr_nosoftrst": [140, 152], "pm_data0": [70, 140, 152], "pm_data1": [70, 140, 152], "pm_data2": [70, 140, 152], "pm_data3": [70, 140, 152], "pm_data4": [70, 140, 152], "pm_data5": [70, 140, 152], "pm_data6": [70, 140, 152], "pm_data7": [70, 140, 152], "pm_data_scale0": [70, 140, 152], "pm_data_scale1": [70, 140, 152], "pm_data_scale2": [70, 140, 152], "pm_data_scale3": [70, 140, 152], "pm_data_scale4": [70, 140, 152], "pm_data_scale5": [70, 140, 152], "pm_data_scale6": [70, 140, 152], "pm_data_scale7": [70, 140, 152], "pm_l1_reentry_delai": 153, "pm_mf": 152, "pm_mfpcie": 152, "pm_pme_service_timeout_delai": 153, "pm_pme_turnoff_ack_delai": 153, "pma1": [66, 119, 120], "pma11": 136, "pma_bit_slip": 105, "pma_cas_clk_en": 136, "pma_cdr_scan": 136, "pma_cdr_scan_0": [66, 119, 120], "pma_cdr_scan_1": [66, 119, 120], "pma_cfg": 136, "pma_com_cfg": [119, 120], "pma_com_cfg_east": 66, "pma_com_cfg_west": 66, "pma_ctrl1_lane0": 135, "pma_ctrl1_lane1": 135, "pma_ctrl1_lane2": 135, "pma_ctrl1_lane3": 135, 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102], "psenmmcm": 145, "psincdec": [51, 52, 64, 86, 102, 114, 130, 145], "psincdec100": 55, "psincdecdcm": 86, "psincdecdcm0": 114, "psincdecdcm1": 114, "psincdecmmcm0": 130, "psincdecmmcm1": 130, "pslew": [57, 63, 108, 123, 139], "pslew4_in": 129, "pslewiostd": [57, 108, 123, 139], "pt": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 159, 160, 161, 162, 163, 164, 165, 166, 171], "pt0": [16, 171], "pt00": [2, 3, 4, 5, 6, 7, 8, 9, 15], "pt000": 16, "pt0010": [2, 3, 4, 5, 6, 7, 8, 9], "pt01": [2, 3, 4, 5, 6, 7, 8, 9], "pt010": 159, "pt1": [15, 159], "pt11": 16, "pt110": [2, 3, 4, 5, 6, 7, 8, 9], "pt111": 15, "pt2": 36, "pt201": 16, "pt3": 36, "pt310": 16, "pt4": 14, "pt40": 171, "pt5": 14, "pt6": 14, "pt7": 14, "pt8": 171, "pt9": 171, "pt_col": [159, 160], "pt_inv10": [2, 3, 4, 5, 6, 7, 8, 9], "pta": 14, "ptb": 14, "ptc": 14, "pte2omux": 55, "pte2omux0": 55, "pte2omux1": 55, "pte2omux2": 55, "pte2omux3": 55, "ptrn_cfg0_lsb": 135, "ptrn_cfg0_msb": 135, "ptrn_len_cfg": 135, "pu_gt": [54, 67], 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171], "pump": 155, "purpos": [12, 15, 34, 35, 36, 46, 81, 82, 91, 96, 104, 118, 134, 148, 169, 170, 171], "put": [35, 148], "pwrdwn": [130, 145], "pwrdwn_b": 108, "pwrdwnmmcm": 145, "pwrdwnphaser_ref": 145, "pwrgnd11111": 154, "pwrup_dli": 135, "q": [14, 46, 171], "q011": 155, "q10100": 154, "q10101": 154, "q10110": 154, "q10111": 154, "q1q4": 155, "q1q400": 155, "q1q401": 155, "q1q411": 155, "q2": 155, "q201": 155, "q210": 155, "q211": 155, "q3": 155, "q301": 155, "q310": 155, "qf32": 12, "qf48": 12, "qfg32": [5, 12], "qfg48": [9, 12], "qfn": 12, "qfp": [12, 34, 169], "quad": [68, 72, 138, 150], "quadrant": 58, "quantiti": 12, "quarter00": 69, "quarter001": 69, "quarter1": 102, "quarter10": 114, "quarter1010": 69, "quarter2110": 69, "quiet": [50, 85, 100, 113, 139], "quietdci": [113, 139], "quietdci0": 50, "quietdci1": [50, 85], "quietio": 57, "quit": [36, 134, 148], "r": [78, 108, 123, 139, 151, 154, 155, 156], "r0": 79, "r00000010010": 79, "r00100000010": 79, "r01101": 154, "r0int": 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166], "r9": [3, 6, 7, 24, 25, 164, 165, 166], "r_edg": 61, "rail": [12, 34], "raisevgg": 85, "ram": [44, 54, 55, 56, 67, 78, 90, 91, 92, 106, 121, 137, 149], "ram0": 96, "ram32011": [60, 112, 128, 143], "ram64001": [60, 112, 128, 143], "ram_extension_": 96, "ram_extension_a": [96, 110, 126, 141], "ram_extension_abram": 126, "ram_extension_b": [96, 110, 126, 141], "ram_extension_bbram": 126, "ram_mod": 59, "ramb16": 96, "ramb16_": 81, "ramb16bwe_": 81, "ramb16bwer": 81, "ramb16bwer1": 59, "ramb32_s64_ecc": 96, "ramb8bwer0": 59, "ramconfig": 73, "ramsharetxrx": 124, "ramsharetxrxpci": 124, "random": 35, "rang": [2, 3, 4, 5, 6, 7, 8, 9, 35, 58, 87, 151, 159, 161, 162, 163, 164, 165, 166], "rank12_dli": 139, "rank12_dlyilogic0": 139, "rank23_dli": 139, "rank23_dlyilogic1": 139, "rare": 35, "rate": [14, 36, 171], "rather": 104, "ratio": 56, "raw": 159, "rb": 54, "rbar_base_ptr": 152, "rbar_cap_control_encodedbar0": 152, "rbar_cap_control_encodedbar1": 152, "rbar_cap_control_encodedbar2": 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169, 170, 171], "usabl": [55, 58], "use_dport": [132, 147], "use_dportdsp0": 147, "use_dportdsp1": 147, "use_mult": [116, 132, 147], "use_multdsp0": 147, "use_multdsp1": 147, "use_pattern_detect": 116, "use_rid_pin": 152, "use_rid_pinspci": 152, "use_simd": [116, 132, 147], "use_vref01": [2, 3, 6, 7], "useless": [55, 148], "user": [56, 92, 139, 151, 159, 171], "user1": 63, "user_clk2_div2": 152, "user_clk2_div2pci": 152, "user_clk_freq": [140, 152], "user_mode00": [88, 89], "user_operation0": 135, "userclk0": 155, "userclk01": [39, 48, 49, 62, 75, 76, 84, 101, 115, 131, 146], "userclk1": 155, "usercod": [2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 35, 36], "userid": [40, 50, 63, 76, 85, 98, 111, 127, 142], "usr_cfg": 70, "usr_code_err_clr": 136, "usr_code_err_clr_0": 66, "usr_code_err_clr_0gtp": 66, "usr_code_err_clr_1": 66, "usr_code_err_clr_1gtp": 66, "usr_code_err_clrgtx0": 136, "usr_code_err_clrgtx1": 136, "usr_code_err_clrgtx2": 136, "usr_code_err_clrgtx3": 136, "usr_ext_cfg": 70, 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"v31110": 155, "v3int": 157, "v4": [6, 7, 22, 23, 24, 25, 154, 155, 157, 158, 164, 165, 166], "v40100": 155, "v41": 139, "v4100": 155, "v411": 155, "v4111101111": 155, "v4int": [155, 157], "v4tbuf0": 154, "v5": [24, 25, 154, 155, 157, 158, 164], "v50": 139, "v50101": 155, "v510": 155, "v5101": 155, "v5111110111": 155, "v5int": [155, 157], "v6": [24, 25, 154, 155, 157, 158, 164], "v60110": 155, "v611": 155, "v6110": 155, "v6111111011": 155, "v6int": [155, 157], "v6tbuf3": 157, "v7": [24, 25, 154, 155, 157, 158, 164], "v70111": 155, "v710": 155, "v7111": 155, "v7111111101": 155, "v7int": 155, "v8": [24, 25, 164], "v9": [24, 25, 164], "valid": [15, 16, 35], "valu": [14, 15, 16, 17, 35, 36, 46, 54, 81, 82, 90, 91, 96, 160, 170, 171], "var_loadable00011": 139, "vari": [34, 35, 36, 104, 108, 118, 134, 148, 171], "variabl": [123, 159], "variable00001": 139, "variable01": 123, "variable11": 108, "variable110": 64, "variable_swapped00101": 139, "variant": [12, 34, 36, 55, 58, 87, 91, 104, 118, 134, 148, 151, 171], "variou": [46, 55, 56, 82, 91, 92, 171], "vbg_dll_sel": 115, "vbg_flat_sel": 146, "vbg_pd": [51, 86], "vbg_sel": [51, 52, 86, 115, 131], "vbg_slope_opt": 63, "vbg_vgg_flast_sel": 131, "vbg_vgg_neg_sel": 131, "vbrk": [104, 118], "vc0_cpl_infinit": [70, 140, 152], "vc0_rx_ram_limit": [70, 140, 152], "vc0_total_credits_cd": [70, 140, 152], "vc0_total_credits_ch": [70, 140, 152], "vc0_total_credits_npd": 152, "vc0_total_credits_nph": [70, 140, 152], "vc0_total_credits_pd": [70, 140, 152], "vc0_total_credits_ph": [70, 140, 152], "vc0_tx_lastpacket": [70, 140, 152], "vc0rxfifobasec": 124, "vc0rxfifobasenp": 124, "vc0rxfifobasep": 124, "vc0rxfifolimitc": 124, "vc0rxfifolimitnp": 124, "vc0rxfifolimitp": 124, "vc0totalcreditscd": 124, "vc0totalcreditsch": 124, "vc0totalcreditsnph": 124, "vc0totalcreditspd": 124, "vc0totalcreditsph": 124, "vc0txfifobasec": 124, "vc0txfifobasenp": 124, "vc0txfifobasep": 124, "vc0txfifolimitc": 124, "vc0txfifolimitnp": 124, "vc0txfifolimitp": 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68, "vcc11111111": [4, 5, 161], "vcc1111111111111111": [8, 9], "vcc11111111111111111": 162, "vcc111111111111111111111111111": 163, "vcc1111111111111111111111111111": 2, "vcc1111111111111111111111111111111111111111111111": 164, "vcc111111111111111111111111111111111111111111111111": 3, "vcc111111111111111111111111111111111111111111111111111111111111111": 165, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111": 6, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111111111111": 166, "vcc1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111": 7, "vcc_gnd": 154, "vccapabilitynextptr": 124, "vccaux": [2, 3, 4, 5, 6, 7, 8, 9, 12], "vccint": [2, 3, 4, 5, 6, 7, 8, 9, 12, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34], "vccio": [12, 17, 34], "vccio0": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "vccio1": [2, 3, 5, 6, 7, 9, 21, 25], "vccio2": [6, 7, 25], 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"clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 158, "clkl": [47, 80, 158], "clkpad": 91, "clkr": [47, 80, 158], "clkt": [38, 47, 55, 74, 83, 158], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 158], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113, 114, 129, 130, 144, 145], "cmt": [68, 113, 114, 130, 145], "cmt_bufg_bot": 129, "cmt_bufg_top": 129, "cmt_fifo": 145, "cnr": [76, 91, 155], "column": [58, 72, 104, 118, 134, 148, 171], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 115, 127, 128, 131, 142, 143, 146, 148, 154, 171], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 121, 137, 149, 156, 167, 168], "control": [69, 171], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 115, 131, 146], "cor1": [49, 62, 115, 131, 146], "cor2": [49, 62], "core": [95, 124, 125, 140, 152, 153], "corner": [40, 50, 63, 76, 85, 155], "cpld": [11, 33, 168], "ctl": [39, 48, 49, 62, 75, 84, 101, 115, 131, 146], "ctl1": [131, 146], "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 113, 161, 162, 163, 164, 165, 166], "databas": [10, 17, 32, 160, 167], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 122, 138, 150], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 118, 134, 148, 160, 167, 169, 171], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 116, 132, 147], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 118, 134, 148], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [117, 133], "exit": 35, "export": 36, "express": [70, 124, 140, 148, 152, 153], "eye_mask": 62, "fb": [14, 15, 16, 36, 159, 171], "fc": [38, 39, 40, 42, 43], "fclk": 171, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 123, 139, 151], "fuse": [15, 16, 35, 36, 159], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 152, "gen3": 153, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 118, 134, 148], "general5": 62, "geometri": [58, 87, 104, 118, 134, 148], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 159, 161, 162, 163, 164, 165, 166], "gt": 91, "gth": 135, "gtp": [119, 148], "gtx": [120, 136, 148], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113, 129, 144], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": [113, 139], "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_hp": 151, "hclk_ioi_hr": 151, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 118, 148], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "ibuf": 23, "idcod": [35, 170], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 159, 161, 162, 163, 164, 165, 166], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 123, 139, 151, 157, 171], "instruct": [13, 35, 170], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 122, 129, 138, 144, 150], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 170], "intf": [55, 68, 91, 122, 138, 150], "introduct": [12, 34, 56, 92, 169], "io": [58, 79, 87, 100, 113, 139, 148, 157], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 159, 171], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 170], "isp": [13, 35, 170], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 160, 161, 162, 163, 164, 165, 166], "jtag": [13, 35, 170], "keeper": 36, "l": [43, 79, 93, 157], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 160], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 171, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 128, 143, 154], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 171, "mac": [117, 133], "macrocel": [14, 15, 16, 36, 159, 171], "manag": [51, 52, 64, 86, 102, 114, 130, 145], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 159, 161, 162, 163, 164, 165, 166], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 148], "misc": [14, 36, 171], "mmcm": 145, "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 171], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 123, 139, 151, 161, 162, 163, 164, 165, 166], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 123, 139, 151, 157, 171], "overview": [14, 36, 171], "packag": [12, 34, 169], "part": [17, 160], "pci": [70, 80, 87, 94, 124, 140, 148, 152, 153], "pci_ce_delai": 61, "pcie_l": 152, "pcie_r": 152, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 161, 162, 163, 164, 165, 166, 169], "placement": 148, "pll": 145, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 129, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 118, 125], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 148, "product": [14, 15, 16, 36, 82, 159, 171], "program": [13, 35, 170], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 157], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 126, 141], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 115, 131, 146, 170, 171], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 148], "row": [38, 47, 58, 83, 87, 100, 171], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 170], "schema": [17, 160], "secondari": [38, 47, 58], "sequenc": [13, 35, 170], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 123, 139, 151], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 160, 161, 162, 163, 164, 165, 166], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 118], "splitter": [55, 158], "standard": [100, 113], "structur": [1, 14, 15, 16, 36, 58, 87, 104, 118, 134, 148, 159, 171], "sum": [14, 36, 82, 159, 171], "system": [109, 148], "t": [43, 57, 79, 83, 88, 89, 93, 157], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92, 108, 114, 123, 130, 139, 145], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 159, 171], "termin": [55, 91, 100], "testmod": [62, 131, 146], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 114, 130, 145, 160], "timer": [62, 115, 131, 146], "tl": [52, 76, 155], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 115, 118, 119, 120, 121, 122, 127, 128, 129, 130, 131, 134, 135, 136, 137, 138, 142, 143, 144, 145, 146, 148, 149, 150, 151, 156, 170, 171], "top": [17, 38, 47, 61, 72, 77, 83, 91, 160], "tr": [52, 76, 155], "transceiv": [66, 88, 89, 105, 119, 120, 135, 136, 148], "trim": 131, "trim0": 146, "trim1": 146, "trim2": 146, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 171, "unk1c": 131, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 121, 137, 149], "w": 91, "wbstar": 146, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 159], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xadc": 142, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 156, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 161, "xcr3064xl": 162, "xcr3128xl": 163, "xcr3256xl": 164, "xcr3384xl": 165, "xcr3512xl": 166, "xilinx": [11, 33, 44, 168], "xor": [14, 36], "xpla3": 168, "xv": [16, 35, 36], "zia": 171}}) \ No newline at end of file diff --git a/xilinx/virtex4/index.html b/xilinx/virtex4/index.html index 4d85fb34..c49a3023 100644 --- a/xilinx/virtex4/index.html +++ b/xilinx/virtex4/index.html @@ -138,6 +138,7 @@

Virtex 4
  • Input/Output
  • Configuration Center