From aa3ed6f8ae93c48670989fe1929b2442bca48426 Mon Sep 17 00:00:00 2001 From: wanda-phi <145241585+wanda-phi@users.noreply.github.com> Date: Fri, 20 Sep 2024 13:14:30 +0000 Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=20f2be1?= =?UTF-8?q?db124d5989d9113623e8f7e639f63184f7d=20=F0=9F=9A=80?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- _sources/xilinx/virtex7/clock.rst.txt | 41 + _sources/xilinx/virtex7/cmt.rst.txt | 20 + _sources/xilinx/virtex7/index.rst.txt | 2 + objects.inv | Bin 2886 -> 2927 bytes searchindex.js | 2 +- xilinx/index.html | 2 + xilinx/spartan6/clock.html | 34 + xilinx/virtex5/clock.html | 1508 +++---- xilinx/virtex5/io.html | 37 + xilinx/virtex7/bram.html | 2 + xilinx/virtex7/clb.html | 2 + xilinx/virtex7/clock.html | 5675 +++++++++++++++++++++++++ xilinx/virtex7/cmt.html | 681 +++ xilinx/virtex7/dsp.html | 2 + xilinx/virtex7/geometry.html | 2 + xilinx/virtex7/index.html | 15 + xilinx/virtex7/interconnect.html | 2 + xilinx/virtex7/io.html | 6 +- xilinx/virtex7/pcie.html | 6 +- xilinx/virtex7/pcie3.html | 2 + 20 files changed, 7282 insertions(+), 759 deletions(-) create mode 100644 _sources/xilinx/virtex7/clock.rst.txt create mode 100644 _sources/xilinx/virtex7/cmt.rst.txt create mode 100644 xilinx/virtex7/clock.html create mode 100644 xilinx/virtex7/cmt.html diff --git a/_sources/xilinx/virtex7/clock.rst.txt b/_sources/xilinx/virtex7/clock.rst.txt new file mode 100644 index 00000000..75f693ba --- /dev/null +++ b/_sources/xilinx/virtex7/clock.rst.txt @@ -0,0 +1,41 @@ +.. _virtex7-clock: + +Clock interconnect +################## + +.. todo:: describe this madness + + +``HCLK`` +======== + +.. raw:: html + :file: ../gen/tile-xc7v-HCLK.html + + +``CLK_BUFG`` +============ + +.. raw:: html + :file: ../gen/tile-xc7v-CLK_BUFG.html + + +``CLK_HROW`` +============ + +.. raw:: html + :file: ../gen/tile-xc7v-CLK_HROW.html + + +``CLK_BUFG_REBUF`` +================== + +.. raw:: html + :file: ../gen/tile-xc7v-CLK_BUFG_REBUF.html + + +``CLK_BALI_REBUF`` +================== + +.. raw:: html + :file: ../gen/tile-xc7v-CLK_BALI_REBUF.html diff --git a/_sources/xilinx/virtex7/cmt.rst.txt b/_sources/xilinx/virtex7/cmt.rst.txt new file mode 100644 index 00000000..2700fef0 --- /dev/null +++ b/_sources/xilinx/virtex7/cmt.rst.txt @@ -0,0 +1,20 @@ +.. _virtex7-cmt: + +Clock management tile +##################### + +.. todo:: describe this madness + + +``CMT`` +======= + +.. raw:: html + :file: ../gen/tile-xc7v-CMT.html + + +``CMT_FIFO`` +============ + +.. raw:: html + :file: ../gen/tile-xc7v-CMT_FIFO.html diff --git a/_sources/xilinx/virtex7/index.rst.txt b/_sources/xilinx/virtex7/index.rst.txt index 36e9d8cc..0d4d5091 100644 --- a/_sources/xilinx/virtex7/index.rst.txt +++ b/_sources/xilinx/virtex7/index.rst.txt @@ -13,5 +13,7 @@ Virtex 7 bram dsp io + clock + cmt pcie pcie3 diff --git a/objects.inv b/objects.inv index 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[[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [125, "block-ram"], [139, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [154, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [164, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [152, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[152, "clkh"]], "CLKL": [[80, "clkl"], [152, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [152, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [152, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[152, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CMT_BUFG_BOT": [[128, "cmt-bufg-bot"]], "CMT_BUFG_TOP": [[128, "cmt-bufg-top"]], "CNR.BL": [[76, "cnr-bl"], [149, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [149, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [149, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [149, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [114, "cor"], [129, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [114, "cor1"], [129, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [114, "ctl"], [129, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[129, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [117, "center-column"], [132, "center-column"]], "Center column and configuration center": [[142, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"], [128, "clock-interconnect"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [127, "configurable-logic-block"], [140, "configurable-logic-block"], [148, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [126, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [114, "configuration-registers"], [129, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [120, null], [135, null], [143, null], [150, null], [161, null], [162, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [149, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [115, "dsp"], [130, "dsp"], [141, "dsp"]], "Database schema": [[17, "database-schema"], [154, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [161, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [154, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [117, "device-geometry"], [132, "device-geometry"], [142, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [163, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [165, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [163, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [117, "ecc"], [132, "ecc"], [142, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[116, "ethernet-macs"], [131, "ethernet-macs"]], "FB columns and rows": [[165, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[165, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[153, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[153, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[153, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [153, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[153, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTH transceivers": [[133, "gth-transceivers"]], "GTP and GTX right column holes": [[142, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[118, "gtp-transceivers"]], "GTX transceivers": [[119, "gtx-transceivers"], [134, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [117, "general-structure"], [132, "general-structure"], [142, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [155, "global-bits"], [156, "global-bits"], [157, "global-bits"], [158, "global-bits"], [159, "global-bits"], [160, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [128, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [122, "i-o-banks-and-special-functions"], [137, "i-o-banks-and-special-functions"], [145, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [155, "i-o-pins"], [156, "i-o-pins"], [157, "i-o-pins"], [158, "i-o-pins"], [159, "i-o-pins"], [160, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [164, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [155, "imux-bits"], [156, "imux-bits"], [157, "imux-bits"], [158, "imux-bits"], [159, "imux-bits"], [160, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[142, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [151, "io-b"]], "IO.L": [[79, "io-l"], [151, "io-l"]], "IO.R": [[79, "io-r"], [151, "io-r"]], "IO.T": [[79, "io-t"], [151, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [164, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [164, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [122, "input-output"], [137, "input-output"], [145, "input-output"], [151, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [165, "input-output-buffer"]], "Interconnect": [[121, "interconnect"], [136, "interconnect"], [144, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [163, "introduction"]], "JED bits": [[154, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [153, "jed-mapping"], [155, "jed-mapping"], [156, "jed-mapping"], [157, "jed-mapping"], [158, "jed-mapping"], [159, "jed-mapping"], [160, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[153, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[153, "jed-mapping-macrocells-without-iob"]], "JED structure": [[153, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [164, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[165, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [165, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[142, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [165, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [165, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[146, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[147, "pci-express-gen3-cores"]], "PCI Express cores": [[123, "pci-express-cores"], [138, "pci-express-cores"]], "PCI Express holes": [[142, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[146, "pcie-l"]], "PCIE_R": [[146, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[128, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [163, "packages"]], "Part": [[17, "part"], [154, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[124, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [117, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[142, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [165, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [164, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [165, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [154, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [155, "speed-data"], [156, "speed-data"], [157, "speed-data"], [158, "speed-data"], [159, "speed-data"], [160, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [117, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[152, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[165, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [129, "testmode"]], "TIMER": [[62, "timer"], [114, "timer"], [129, "timer"]], "TRIM": [[129, "trim"]], "Tables": [[71, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[81, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[81, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[83, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [154, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [38, "id2"], [38, "id3"], [38, "id4"], [38, "id5"], [38, "id6"], [38, "id7"], [38, "id8"], [39, "id1"], [40, "id1"], [40, "id2"], [40, "id3"], [40, "id4"], [40, "id5"], [41, "id1"], [43, "id1"], [43, "id2"], [43, "id3"], [46, "id1"], [47, "id1"], [47, "id2"], [47, "id3"], [47, "id4"], [47, "id5"], [47, "id6"], [47, "id7"], [47, "id8"], [47, "id9"], [47, "id10"], [48, "id1"], [49, "id1"], [50, "id1"], [50, "id2"], [50, "id3"], [50, "id4"], [50, "id5"], [51, "id1"], [52, "id1"], [53, "id1"], [54, "id1"], [56, "id1"], [57, "id1"], [57, "id2"], [57, "id3"], [57, "id4"], [57, "id5"], [58, "id1"], [60, "id1"], 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59, 81, 96, 110, 125, 139], "9793": [45, 59, 81, 96, 110, 125, 139], "9794": [45, 59, 81, 96, 110, 125, 139], "9795": [45, 59, 81, 96, 110, 125, 139], "9796": [45, 59, 81, 96, 110, 125, 139], "9797": [45, 59, 81, 96, 110, 125, 139], "9798": [45, 59, 81, 96, 110, 125, 139], "9799": [45, 59, 81, 96, 110, 125, 139], "98": [2, 3, 6, 7, 45, 59, 61, 72, 81, 89, 96, 110, 125, 139, 155, 156, 157, 158, 159, 160], "980": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9800": [5, 45, 59, 81, 96, 110, 125, 139, 158, 159, 160], "9801": [45, 59, 81, 96, 110, 125, 139], "9802": [45, 59, 81, 96, 110, 125, 139], "9803": [45, 59, 81, 96, 110, 125, 139], "9804": [45, 59, 81, 96, 110, 125, 139], "9805": [45, 59, 81, 96, 110, 125, 139], "9806": [45, 59, 81, 96, 110, 125, 139], "9807": [45, 59, 81, 96, 110, 125, 139], "9808": [45, 59, 81, 96, 110, 125, 139], "9809": [45, 59, 81, 96, 110, 125, 139], "981": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9810": [45, 59, 81, 96, 110, 125, 139], "9811": [45, 59, 81, 96, 110, 125, 139], "9812": [45, 59, 81, 96, 110, 125, 139], "9813": [45, 59, 81, 96, 110, 125, 139], "9814": [45, 59, 81, 96, 110, 125, 139], "9815": [45, 59, 81, 96, 110, 125, 139], "9816": [45, 59, 81, 96, 110, 125, 139], "9817": [45, 59, 81, 96, 110, 125, 139], "9818": [45, 59, 81, 96, 110, 125, 139], "9819": [45, 59, 81, 96, 110, 125, 139], "982": [6, 7, 45, 59, 72, 81, 96, 110, 125, 139], "9820": [45, 59, 81, 96, 110, 125, 139], "9821": [45, 59, 81, 96, 110, 125, 139], "9822": [45, 59, 81, 96, 110, 125, 139], "9823": [45, 59, 81, 96, 110, 125, 139], "9824": [45, 59, 81, 96, 110, 125, 139], "9825": [45, 59, 81, 96, 110, 125, 139], "9826": [45, 59, 81, 96, 110, 125, 139], "9827": [45, 59, 81, 96, 110, 125, 139], "9828": [45, 59, 81, 96, 110, 125, 139], "9829": [45, 59, 81, 96, 110, 125, 139], "983": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9830": [45, 59, 81, 96, 110, 125, 139], "9831": [45, 59, 81, 96, 110, 125, 139], "9832": [45, 59, 81, 96, 110, 125, 139], "9833": [45, 59, 81, 96, 110, 125, 139], "9834": [45, 59, 81, 96, 110, 125, 139], "9835": [45, 59, 81, 96, 110, 125, 139], "9836": [45, 59, 81, 96, 110, 125, 139], "9837": [45, 59, 81, 96, 110, 125, 139], "9838": [45, 59, 81, 96, 110, 125, 139], "9839": [45, 59, 81, 96, 110, 125, 139], "984": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9840": [45, 59, 81, 96, 110, 125, 139], "9841": [45, 59, 81, 96, 110, 125, 139], "9842": [45, 59, 81, 96, 110, 125, 139], "9843": [45, 59, 81, 96, 110, 125, 139], "9844": [45, 59, 81, 96, 110, 125, 139], "9845": [45, 59, 81, 96, 110, 125, 139], "9846": [45, 59, 81, 96, 110, 125, 139], "9847": [45, 59, 81, 96, 110, 125, 139], "9848": [45, 59, 81, 96, 110, 125, 139], "9849": [45, 59, 81, 96, 110, 125, 139], "985": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9850": [45, 59, 81, 96, 110, 125, 139], "9851": [45, 59, 81, 96, 110, 125, 139], "9852": [45, 59, 81, 96, 110, 125, 139], "9853": [45, 59, 81, 96, 110, 125, 139], "9854": [45, 59, 81, 96, 110, 125, 139], "9855": [45, 59, 81, 96, 110, 125, 139], "9856": [45, 59, 81, 96, 110, 125, 139], "9857": [45, 59, 81, 96, 110, 125, 139], "9858": [45, 59, 81, 96, 110, 125, 139], "9859": [45, 59, 81, 96, 110, 125, 139], "986": [45, 59, 72, 81, 96, 110, 125, 139], "9860": [45, 59, 81, 96, 110, 125, 139], "9861": [45, 59, 81, 96, 110, 125, 139], "9862": [45, 59, 81, 96, 110, 125, 139], "9863": [45, 59, 81, 96, 110, 125, 139], "9864": [45, 59, 81, 96, 110, 125, 139], "9865": [45, 59, 81, 96, 110, 125, 139], "9866": [45, 59, 81, 96, 110, 125, 139], "9867": [45, 59, 81, 96, 110, 125, 139], "9868": [45, 59, 81, 96, 110, 125, 139], "9869": [45, 59, 81, 96, 110, 125, 139], "987": [45, 59, 72, 81, 96, 110, 125, 139], "9870": [45, 59, 81, 96, 110, 125, 139], "9871": [45, 59, 81, 96, 110, 125, 139], "9872": [45, 59, 81, 96, 110, 125, 139], "9873": [45, 59, 81, 96, 110, 125, 139], "9874": [45, 59, 81, 96, 110, 125, 139], "9875": [45, 59, 81, 96, 110, 125, 139], "9876": [45, 59, 81, 96, 110, 125, 139], "9877": [45, 59, 81, 96, 110, 125, 139], "9878": [45, 59, 81, 96, 110, 125, 139], "9879": [45, 59, 81, 96, 110, 125, 139], "988": [45, 59, 72, 81, 96, 110, 125, 139], "9880": [45, 59, 81, 96, 110, 125, 139], "9881": [45, 59, 81, 96, 110, 125, 139], "9882": [45, 59, 81, 96, 110, 125, 139], "9883": [45, 59, 81, 96, 110, 125, 139], "9884": [45, 59, 81, 96, 110, 125, 139], "9885": [45, 59, 81, 96, 110, 125, 139], "9886": [45, 59, 81, 96, 110, 125, 139], "9887": [45, 59, 81, 96, 110, 125, 139], "9888": [45, 59, 81, 96, 110, 125, 139], "9889": [45, 59, 81, 96, 110, 125, 139], "989": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9890": [45, 59, 81, 96, 110, 125, 139], "9891": [45, 59, 81, 96, 110, 125, 139], "9892": [45, 59, 81, 96, 110, 125, 139], "9893": [45, 59, 81, 96, 110, 125, 139], "9894": [45, 59, 81, 96, 110, 125, 139], "9895": [45, 59, 81, 96, 110, 125, 139], "9896": [45, 59, 81, 96, 110, 125, 139], "9897": [45, 59, 81, 96, 110, 125, 139], "9898": [45, 59, 81, 96, 110, 125, 139], "9899": [45, 59, 81, 96, 110, 125, 139], "99": [2, 3, 7, 45, 59, 61, 72, 81, 89, 96, 110, 125, 139, 155, 156, 157, 158, 159, 160], "990": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9900": [7, 45, 59, 81, 96, 110, 125, 139], "9901": [45, 59, 81, 96, 110, 125, 139], "9902": [45, 59, 81, 96, 110, 125, 139], "9903": [45, 59, 81, 96, 110, 125, 139], "9904": [45, 59, 81, 96, 110, 125, 139], "9905": [45, 59, 81, 96, 110, 125, 139], "9906": [45, 59, 81, 96, 110, 125, 139], "9907": [45, 59, 81, 96, 110, 125, 139], "9908": [45, 59, 81, 96, 110, 125, 139], "9909": [45, 59, 81, 96, 110, 125, 139], "991": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9910": [45, 59, 81, 96, 110, 125, 139], "9911": [45, 59, 81, 96, 110, 125, 139], "9912": [45, 59, 81, 96, 110, 125, 139], "9913": [45, 59, 81, 96, 110, 125, 139], "9914": [45, 59, 81, 96, 110, 125, 139], "9915": [45, 59, 81, 96, 110, 125, 139], "9916": [45, 59, 81, 96, 110, 125, 139], "9917": [45, 59, 81, 96, 110, 125, 139], "9918": [45, 59, 81, 96, 110, 125, 139], "9919": [45, 59, 81, 96, 110, 125, 139], "992": [7, 45, 59, 72, 81, 96, 110, 125, 139], "9920": [45, 59, 81, 96, 110, 125, 139], "9921": [45, 59, 81, 96, 110, 125, 139], "9922": [45, 59, 81, 96, 110, 125, 139], "9923": [45, 59, 81, 96, 110, 125, 139], "9924": [45, 59, 81, 96, 110, 125, 139], "9925": [45, 59, 81, 96, 110, 125, 139], "9926": [45, 59, 81, 96, 110, 125, 139], "9927": [45, 59, 81, 96, 110, 125, 139], "9928": [45, 59, 81, 96, 110, 125, 139], "9929": [45, 59, 81, 96, 110, 125, 139], "993": [45, 59, 72, 81, 96, 110, 125, 139], "9930": [45, 59, 81, 96, 110, 125, 139], "9931": [45, 59, 81, 96, 110, 125, 139], "9932": [45, 59, 81, 96, 110, 125, 139], "9933": [45, 59, 81, 96, 110, 125, 139], "9934": [45, 59, 81, 96, 110, 125, 139], "9935": [45, 59, 81, 96, 110, 125, 139], "9936": [45, 59, 81, 96, 110, 125, 139], "9937": [45, 59, 81, 96, 110, 125, 139], "9938": [45, 59, 81, 96, 110, 125, 139], "9939": [45, 59, 81, 96, 110, 125, 139], "994": [45, 59, 72, 81, 96, 110, 125, 139], "9940": [45, 59, 81, 96, 110, 125, 139], "9941": [45, 59, 81, 96, 110, 125, 139], "9942": [45, 59, 81, 96, 110, 125, 139], "9943": [45, 59, 81, 96, 110, 125, 139], "9944": [45, 59, 81, 96, 110, 125, 139], "9945": [45, 59, 81, 96, 110, 125, 139], "9946": [45, 59, 81, 96, 110, 125, 139], "9947": [45, 59, 81, 96, 110, 125, 139], "9948": [45, 59, 81, 96, 110, 125, 139], "9949": [45, 59, 81, 96, 110, 125, 139], "995": [45, 59, 72, 81, 96, 110, 125, 139], "9950": [45, 59, 81, 96, 110, 125, 139], "9951": [45, 59, 81, 96, 110, 125, 139], "9952": [45, 59, 81, 96, 110, 125, 139], "9953": [45, 59, 81, 96, 110, 125, 139], "9954": [45, 59, 81, 96, 110, 125, 139], "9955": [45, 59, 81, 96, 110, 125, 139], "9956": [45, 59, 81, 96, 110, 125, 139], "9957": [45, 59, 81, 96, 110, 125, 139], "9958": [45, 59, 81, 96, 110, 125, 139], "9959": [45, 59, 81, 96, 110, 125, 139], "996": [45, 59, 72, 81, 96, 110, 125, 139], "9960": [45, 59, 81, 96, 110, 125, 139], "9961": [45, 59, 81, 96, 110, 125, 139], "9962": [45, 59, 81, 96, 110, 125, 139], "9963": [45, 59, 81, 96, 110, 125, 139], "9964": [45, 59, 81, 96, 110, 125, 139], "9965": [45, 59, 81, 96, 110, 125, 139], "9966": [45, 59, 81, 96, 110, 125, 139], "9967": [45, 59, 81, 96, 110, 125, 139], "9968": [45, 59, 81, 96, 110, 125, 139], "9969": [45, 59, 81, 96, 110, 125, 139], "997": [45, 59, 72, 81, 96, 110, 125, 139], "9970": [45, 59, 81, 96, 110, 125, 139], "9971": [45, 59, 81, 96, 110, 125, 139], "9972": [45, 59, 81, 96, 110, 125, 139], "9973": [45, 59, 81, 96, 110, 125, 139], "9974": [45, 59, 81, 96, 110, 125, 139], "9975": [45, 59, 81, 96, 110, 125, 139], "9976": [45, 59, 81, 96, 110, 125, 139], "9977": [45, 59, 81, 96, 110, 125, 139], "9978": [45, 59, 81, 96, 110, 125, 139], "9979": [45, 59, 81, 96, 110, 125, 139], "998": [45, 59, 72, 81, 96, 110, 125, 139], "9980": [45, 59, 81, 96, 110, 125, 139], "9981": [45, 59, 81, 96, 110, 125, 139], "9982": [45, 59, 81, 96, 110, 125, 139], "9983": [45, 59, 81, 96, 110, 125, 139], "9984": [45, 59, 81, 96, 110, 125, 139], "9985": [45, 59, 81, 96, 110, 125, 139], "9986": [45, 59, 81, 96, 110, 125, 139], "9987": [45, 59, 81, 96, 110, 125, 139], "9988": [45, 59, 81, 96, 110, 125, 139], "9989": [45, 59, 81, 96, 110, 125, 139], "999": [45, 59, 72, 81, 96, 110, 125, 139], "9990": [45, 59, 81, 96, 110, 125, 139], "9991": [45, 59, 81, 96, 110, 125, 139], "9992": [45, 59, 81, 96, 110, 125, 139], "9993": [45, 59, 81, 96, 110, 125, 139], "9994": [45, 59, 81, 96, 110, 125, 139], "9995": [45, 59, 81, 96, 110, 125, 139], "9996": [45, 59, 81, 96, 110, 125, 139], "9997": [45, 59, 81, 96, 110, 125, 139], "9998": [45, 59, 81, 96, 110, 125, 139], "9999": [45, 59, 81, 96, 110, 125, 139], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 153, "9fb_group": [155, 156, 157, 158, 159, 160], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 153, "9reg_d_ireg": 153, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 123, 126, 146, 147], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 116, 124, 131, 138], "9rowcolumn01234567891011121314151617181920212223242526272829": [133, 134, 146], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [118, 119], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 117, 122, 132, 137, 142, 145, 154, 165], "AED": [12, 163], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 165], "As": [35, 132, 165], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 117, 132, 142, 165], "ISE": [35, 165], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 117, 132, 137, 142, 165], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 117, 122, 132, 137, 142, 145, 165], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 117, 132, 137, 142, 145, 154, 163, 165], "Its": [35, 81], "No": 142, "Not": [15, 16, 36, 55, 91, 165], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 142, 165], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 117, 122, 132, 137, 142, 145, 153, 154, 163, 164, 165], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 117, 132, 137, 142, 145], "These": [36, 91, 137, 142], "To": [35, 36, 96], "_": [17, 34, 36, 154, 165], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 153, 165], "_gclk": 165, "_init": [46, 82], "_inv": [36, 165], "_lct": 165, "_mc": [12, 163], "_mux": [36, 46, 82], "_none": 165, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 156, 157, 158, 159, 160], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 157, 158, 159, 160], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 157, 158, 159, 160], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 157, 158, 159, 160], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 158, 159, 160], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 158, 159, 160], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 158, 159, 160], "a17": [6, 7, 22, 23, 24, 25, 45, 158, 159, 160], "a18": [6, 7, 22, 23, 24, 25, 158, 159, 160], "a19": [6, 7, 22, 23, 24, 25, 158, 159, 160], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a20": [6, 7, 22, 23, 24, 159, 160], "a21": [6, 7, 22, 23, 159, 160], "a22": [6, 7, 22, 23, 159, 160], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a5ffinit": [127, 140], "a5ffinitslice0": [127, 140], "a5ffmux": [127, 140], "a5ffsr": [127, 140], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 127, "a5q0": 60, "a5q0100": [60, 127, 140], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a6lut": [60, 112, 127, 140], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 155, 156, 157, 158, 159, 160], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 156, 157, 158, 159, 160], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 156, 157, 158, 159, 160], "a_dfeclkdlyadj": 134, "a_dfedlyovrd": 134, "a_dfedlyovrdgtx0": 134, "a_dfedlyovrdgtx1": 134, "a_dfedlyovrdgtx2": 134, "a_dfedlyovrdgtx3": 134, "a_dfetap1": 134, "a_dfetap2": 134, "a_dfetap3": 134, "a_dfetap4": 134, "a_dfetapovrd": 134, "a_dfetapovrdgtx0": 134, "a_dfetapovrdgtx1": 134, "a_dfetapovrdgtx2": 134, "a_dfetapovrdgtx3": 134, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 134, "a_gtxrxresetgtx0": 134, "a_gtxrxresetgtx1": 134, "a_gtxrxresetgtx2": 134, "a_gtxrxresetgtx3": 134, "a_gtxtxreset": 134, "a_gtxtxresetgtx0": 134, "a_gtxtxresetgtx1": 134, "a_gtxtxresetgtx2": 134, "a_gtxtxresetgtx3": 134, "a_input": [115, 130, 141], "a_loopback": 134, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 134, "a_pllclkrxresetgtx0": 134, "a_pllclkrxresetgtx1": 134, "a_pllclkrxresetgtx2": 134, "a_pllclkrxresetgtx3": 134, "a_pllclktxreset": 134, "a_pllclktxresetgtx0": 134, "a_pllclktxresetgtx1": 134, "a_pllclktxresetgtx2": 134, "a_pllclktxresetgtx3": 134, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 134, "a_pllrxresetgtx0": 134, "a_pllrxresetgtx1": 134, "a_pllrxresetgtx2": 134, "a_pllrxresetgtx3": 134, "a_plltxreset": 134, "a_plltxresetgtx0": 134, "a_plltxresetgtx1": 134, "a_plltxresetgtx2": 134, "a_plltxresetgtx3": 134, "a_prbscntreset": 134, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 134, "a_prbscntresetgtx1": 134, "a_prbscntresetgtx2": 134, "a_prbscntresetgtx3": 134, "a_q": 81, "a_rxbufreset": 134, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 134, "a_rxbufresetgtx1": 134, "a_rxbufresetgtx2": 134, "a_rxbufresetgtx3": 134, "a_rxcdrfreqreset": 134, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 134, "a_rxcdrfreqresetgtx1": 134, "a_rxcdrfreqresetgtx2": 134, "a_rxcdrfreqresetgtx3": 134, "a_rxcdrhold": 134, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 134, "a_rxcdrholdgtx1": 134, "a_rxcdrholdgtx2": 134, "a_rxcdrholdgtx3": 134, "a_rxcdrphasereset": 134, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 134, "a_rxcdrphaseresetgtx1": 134, "a_rxcdrphaseresetgtx2": 134, "a_rxcdrphaseresetgtx3": 134, "a_rxcdrreset": 134, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 134, "a_rxcdrresetgtx1": 134, "a_rxcdrresetgtx2": 134, "a_rxcdrresetgtx3": 134, "a_rxdfereset": 134, "a_rxdferesetgtx0": 134, "a_rxdferesetgtx1": 134, "a_rxdferesetgtx2": 134, "a_rxdferesetgtx3": 134, "a_rxenpmaphasealign": 134, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 134, "a_rxenpmaphasealigngtx1": 134, "a_rxenpmaphasealigngtx2": 134, "a_rxenpmaphasealigngtx3": 134, "a_rxenprbstst": 134, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 134, "a_rxensamplealigngtx0": 134, "a_rxensamplealigngtx1": 134, "a_rxensamplealigngtx2": 134, "a_rxensamplealigngtx3": 134, "a_rxeqmix": 134, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 134, "a_rxplllkdetengtx0": 134, "a_rxplllkdetengtx1": 134, "a_rxplllkdetengtx2": 134, "a_rxplllkdetengtx3": 134, "a_rxpllpowerdown": 134, "a_rxpllpowerdowngtx0": 134, "a_rxpllpowerdowngtx1": 134, "a_rxpllpowerdowngtx2": 134, "a_rxpllpowerdowngtx3": 134, "a_rxpmasetphas": 134, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 134, "a_rxpmasetphasegtx1": 134, "a_rxpmasetphasegtx2": 134, "a_rxpmasetphasegtx3": 134, "a_rxpolar": 134, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 134, "a_rxpolaritygtx1": 134, "a_rxpolaritygtx2": 134, "a_rxpolaritygtx3": 134, "a_rxpowerdown": 134, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 134, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 134, "a_rxresetgtx1": 134, "a_rxresetgtx2": 134, "a_rxresetgtx3": 134, "a_txbufdiffctrl": 134, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 134, "a_txdeemphgtx0": 134, "a_txdeemphgtx1": 134, "a_txdeemphgtx2": 134, "a_txdeemphgtx3": 134, "a_txdiffctrl": 134, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 134, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 134, "a_txelecidlegtx1": 134, "a_txelecidlegtx2": 134, "a_txelecidlegtx3": 134, "a_txenpmaphasealign": 134, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 134, "a_txenpmaphasealigngtx1": 134, "a_txenpmaphasealigngtx2": 134, "a_txenpmaphasealigngtx3": 134, "a_txenprbstst": 134, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 134, "a_txplllkdeten": 134, "a_txplllkdetengtx0": 134, "a_txplllkdetengtx1": 134, "a_txplllkdetengtx2": 134, "a_txplllkdetengtx3": 134, "a_txpllpowerdown": 134, "a_txpllpowerdowngtx0": 134, "a_txpllpowerdowngtx1": 134, "a_txpllpowerdowngtx2": 134, "a_txpllpowerdowngtx3": 134, "a_txpmasetphas": 134, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 134, "a_txpmasetphasegtx1": 134, "a_txpmasetphasegtx2": 134, "a_txpmasetphasegtx3": 134, "a_txpolar": 134, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 134, "a_txpolaritygtx1": 134, "a_txpolaritygtx2": 134, "a_txpolaritygtx3": 134, "a_txpostemphasi": 134, "a_txpowerdown": 134, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 134, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 134, "a_txprbsforceerrgtx1": 134, "a_txprbsforceerrgtx2": 134, "a_txprbsforceerrgtx3": 134, "a_txpreemphasi": 134, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 134, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 134, "a_txresetgtx1": 134, "a_txresetgtx2": 134, "a_txresetgtx3": 134, "a_txsw": 134, "a_txswinggtx0": 134, "a_txswinggtx1": 134, "a_txswinggtx2": 134, "a_txswinggtx3": 134, "aa1": [6, 7, 22, 23, 159, 160], "aa10": [6, 7, 159, 160], "aa11": [6, 7, 159, 160], "aa12": [6, 7, 159, 160], "aa13": [6, 7, 159, 160], "aa14": [6, 7, 159, 160], "aa15": [6, 7, 159, 160], "aa16": [6, 7, 159, 160], "aa17": [6, 7, 159, 160], "aa18": [6, 7, 159, 160], "aa19": [6, 7, 159, 160], "aa2": [6, 7, 22, 23, 159, 160], "aa20": [6, 7, 159, 160], "aa21": [6, 7, 159, 160], "aa22": [6, 7, 159, 160], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 159, 160], "aa4": [6, 7, 22, 23, 159, 160], "aa5": [6, 7, 159, 160], "aa6": [6, 7, 159, 160], "aa7": [6, 7, 159, 160], "aa8": [6, 7, 159, 160], "aa9": [6, 7, 159, 160], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 159, 160], "ab10": [6, 7, 159, 160], "ab11": [6, 7, 159, 160], "ab12": [6, 7, 159, 160], "ab13": [6, 7, 159, 160], "ab14": [6, 7, 159, 160], "ab15": [6, 7, 159, 160], "ab16": [6, 7, 159, 160], "ab17": [6, 7, 159, 160], "ab18": [6, 7, 159, 160], "ab19": [6, 7, 159, 160], "ab2": [6, 7, 22, 23, 159, 160], "ab20": [6, 7, 159, 160], "ab21": [6, 7, 159, 160], "ab22": [6, 7, 159, 160], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 159, 160], "ab4": [6, 7, 22, 23, 159, 160], "ab5": [6, 7, 159, 160], "ab6": [6, 7, 159, 160], "ab7": [6, 7, 159, 160], "ab8": [6, 7, 159, 160], "ab9": [6, 7, 159, 160], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 132, 142, 145, 165], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 154, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 134, "ac_cap_dis_0": [66, 118, 119], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 118, "ac_cap_dis_0gtx_du": 119, "ac_cap_dis_1": [66, 118, 119], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 118, "ac_cap_dis_1gtx_du": 119, "ac_cap_disgtx0": 134, "ac_cap_disgtx1": 134, "ac_cap_disgtx2": 134, "ac_cap_disgtx3": 134, "acb": [12, 34, 163], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 163, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 117, 132, 142, 145, 154, 163, 165], "activ": [35, 36, 46, 82, 164], "activelanesin": 123, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 117, 132, 142, 165], "acy0": [60, 112, 127, 140], "acy0slice0": [112, 127, 140], "acy0slice1": [60, 127], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 117, 132, 142, 165], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 117, 132], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, 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113, "cmt_clk1000010100000000": 113, "cmt_clk1000101000000000": 113, "cmt_clk1100001000001000": 113, "cmt_clk1100010000000100": 113, "cmt_clk1200010010000000": 113, "cmt_clk1201001000000000": 113, "cmt_clk1300001000010000": 113, "cmt_clk1300010000000010": 113, "cmt_clk1400010001000000": 113, "cmt_clk1410001000000000": 113, "cmt_clk1500001000100000": 113, "cmt_clk1500010000000001": 113, "cmt_clk1600010100000000": 113, "cmt_clk1600101000000000": 113, "cmt_clk1700000100000100": 113, "cmt_clk1700100000001000": 113, "cmt_clk1800100100000000": 113, "cmt_clk1900000100001000": 113, "cmt_clk1900100000000100": 113, "cmt_clk200000100010000": 113, "cmt_clk2000100010000000": 113, "cmt_clk200100000000010": 113, "cmt_clk2001000100000000": 113, "cmt_clk2100000100010000": 113, "cmt_clk2100100000000010": 113, "cmt_clk2200100001000000": 113, "cmt_clk2210000100000000": 113, "cmt_clk2300000100100000": 113, "cmt_clk2300100000000001": 113, "cmt_clk2400010010000000": 113, "cmt_clk2401001000000000": 113, "cmt_clk2500000010000100": 113, "cmt_clk2501000000001000": 113, "cmt_clk2600100010000000": 113, "cmt_clk2601000100000000": 113, "cmt_clk2700000010001000": 113, "cmt_clk2701000000000100": 113, "cmt_clk300000000001010": 113, "cmt_clk300000000010100": 113, "cmt_clk400000010010000": 113, "cmt_clk401000000000010": 113, "cmt_clk500000000010010": 113, "cmt_clk600000001010000": 113, "cmt_clk610000000000010": 113, "cmt_clk700000000010001": 113, "cmt_clk700000000100010": 113, "cmt_clk800011000000000": 113, "cmt_clk900001000000100": 113, "cmt_clk900010000001000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_pll": 71, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 149, "cmuxosc": 149, "cnr": [58, 78, 87, 150], "co01": 148, "co1": 148, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 117, 132, 142], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 122, 137, 145, 153, 154, 155, 156, 157, 158, 159, 160, 162, 164], "columnar": 104, "com": [51, 86], "com_burst_v": 134, "com_burst_val_0": [66, 118, 119], "com_burst_val_1": [66, 118, 119], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 165], "combination": 81, "combinatori": [14, 36, 165], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 117, 122, 132, 142, 163, 165], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 134, "comma_10b_enable_0": [66, 118, 119], "comma_10b_enable_1": [66, 118, 119], "comma_10b_mask": [88, 89, 105], "comma_doubl": 134, "comma_double_0": [118, 119], "comma_double_0gtp_du": 118, "comma_double_0gtx_du": 119, "comma_double_1": [118, 119], "comma_double_1gtp_du": 118, "comma_double_1gtx_du": 119, "comma_doublegtx0": 134, "comma_doublegtx1": 134, "comma_doublegtx2": 134, "comma_doublegtx3": 134, "commerci": [17, 154], "common": [100, 145], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [142, 153], "companion": [44, 106], "compat": [12, 34, 163], "compens": 82, "complement": [108, 122, 137, 145], "complet": [12, 13, 16, 34, 35, 36, 104, 142, 153, 163], "complex": [15, 16, 142], "comput": [81, 153], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86], "concur00100101": 102, "concur1001": 64, "concur_en": 102, "concur_enabledcm": 102, "concurdcm": [51, 52, 86], "concurdcm0": 64, "concurdcm1": 64, "config": [15, 16, 153], "config10": 102, "config_fallback": [114, 129], "config_r": [39, 48, 49, 75, 84, 101, 114, 129, 149], "configrout": 123, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 117, 120, 122, 132, 135, 137, 143, 145, 150, 153, 162], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 122, 137, 142, 164, 165], "consecut": 132, "consid": [35, 104, 108, 117, 122, 132, 137, 142, 145], "consist": [35, 36, 81, 104, 117, 122, 132, 137, 142], "const": [13, 14, 35, 36, 46, 82, 164, 165], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 165, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 132, 137, 142, 145, 164, 165], "content": [35, 46, 82, 132], "contigu": [15, 16], "continu": [35, 145], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "convert": [15, 16], "convst": 109, "convstclk": [111, 126], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 153, 154, 165], "cor": [41, 54, 78, 90, 106, 120, 135], "cor1": [54, 67, 120, 135], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 117, 120, 135, 143, 163, 165], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 142, 150], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 117, 122, 132, 137, 142, 145, 154, 165], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 117, 132, 142, 155, 156, 157, 158, 159, 160], "cout": [46, 82, 151], "coutmux": [60, 112, 127, 140], "coutmuxslice1": 60, "cover": [104, 117, 132, 142, 145, 165], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 156, 163], "cpl_timeout_disable_support": [138, 146], "cpl_timeout_ranges_support": [138, 146], "cpld": [0, 12, 34, 36, 163, 165], "cpmc440clk": 124, "cpmc440timerclock": 124, "cpmdcrclk": 124, "cpmdma0llclk": 124, "cpmdma1llclk": 124, "cpmdma2llclk": 124, "cpmdma3llclk": 124, "cpmfcmclk": 124, "cpminterconnectclk": 124, "cpmmcclk": 124, "cpmppcmplbclk": 124, "cpmppcs0plbclk": 124, "cpmppcs1plbclk": 124, "crammod": [60, 112, 127, 140], "crc": [39, 48, 49, 62, 84, 101, 114, 149], "crc32_0": [118, 119], "crc32_1": [118, 119], "crc32_2": [118, 119], "crc32_3": [118, 119], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [118, 119], "crc_start_of_pkt": [88, 89], "crcclk": [118, 119], "crcclkgtp_dual": 118, "crcclkgtx_dual": 119, "creat": [55, 87, 91, 104, 117], "create_edg": [98, 111, 128], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 115, 130, 141], "cregdsp": [53, 65], "cregdsp0": [115, 130], "cregdsp1": 130, "crm_core_clk_freq_500": 147, "crm_core_clk_freq_500pcie3": 147, "crm_module_rst": [138, 146], "crm_user_clk_freq": 147, "crmcoreclk": 123, "crmcoreclkdlo": 123, "crmcoreclkpci": 123, "crmcoreclkrxo": 123, "crmcoreclkrxopci": 123, "crmcoreclktxo": 123, "crmcoreclktxopci": 123, "crmuserclk": 123, "crmuserclkrxo": 123, "crmuserclktxo": 123, "cross": [58, 91, 132, 142], "cs144": [20, 21, 34, 157, 163], "cs280": [24, 25, 34, 158, 163], "cs48": [26, 27, 28, 30, 31, 34, 155, 156, 163], "cs_b": [108, 122], "csi_b": [137, 145], "cso2pin": [50, 63], "cso_b": [122, 137, 145], "cspin": [98, 111, 126], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 120, 135], "ctl1": 135, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [121, 136, 144], "ctrl00001": [136, 144], "ctrl1": [121, 136, 144], "ctrl10010": [136, 144], "ctrl2": 121, "ctrl3": 121, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 117, 142], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 127, 140], "cx0100": [112, 127, 140], "cx1": [60, 112], "cx10": [127, 140], "cx1010": 60, "cxt": 132, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 127, 140], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 127, 140], "cyinitslice0": [73, 99, 112, 127, 140], "cyinitslice1": [37, 46, 60, 73, 112, 127, 140], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 122, 137, 145, 165], "d0": [130, 141], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 141, 155, 156, 157, 158, 159, 160, 165], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 141, 156, 157, 158, 159, 160], "d100001": 122, "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 141, 157, 158, 159, 160], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 141, 157, 158, 159, 160], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 141, 157, 158, 159, 160], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d15": [3, 6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d16": [3, 6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d17": [6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d18": [6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d19": [6, 7, 22, 23, 24, 25, 130, 141, 158, 159, 160], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 141, 155, 156, 157, 158, 159, 160], "d20": [6, 7, 22, 23, 24, 130, 141, 159, 160], "d21": [6, 7, 22, 23, 130, 141, 159, 160], "d22": [6, 7, 22, 23, 130, 141, 159, 160], "d23": [22, 23, 130, 141], "d24": [22, 23, 130, 141], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 141, 155, 156, 157, 158, 159, 160], "d3iob0": [108, 122], "d3iob1": [108, 122], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 141, 155, 156, 157, 158, 159, 160], "d4iob0": 108, "d4iob1": 108, "d4ologic0": 122, "d4ologic1": 122, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 122, 130, 141, 157, 158, 159, 160], "d5ffinit": [127, 140], "d5ffinitslice0": [127, 140], "d5ffmux": [127, 140], "d5ffsr": [127, 140], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 127, "d5ologic0": [108, 122], "d5ologic1": [108, 122], "d5q0": 60, "d5q0100": [60, 127, 140], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 141, 155, 156, 157, 158, 159, 160], "d6iob0": 122, "d6iob1": 122, "d6lut": [60, 112, 127, 140], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 130, 141, 155, 156, 157, 158, 159, 160], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 141, 156, 157, 158, 159, 160], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 141, 157, 158, 159, 160], "d_in": [108, 122], "d_out_busi": 122, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 117, 120, 122, 132, 142, 149, 153, 154, 161, 165], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_l": [110, 125, 139], "data_r": [61, 108, 122], "data_u": [110, 125, 139], "data_width": [108, 122], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 153, 162, 164, 165], "datain": 122, "datain1000": 122, "datainilogic0": 122, "datainilogic1": 122, "dataint": 149, "datap": [45, 59, 81, 96], "datap_l": [110, 125, 139], "datap_u": [110, 125, 139], "datareg": 13, "datastream": [17, 154], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 121, 136, 144, 148, 151], "dbl0001010000": 121, "dbl0001100000": 121, "dbl0010010000": 121, "dbl0010100000": 121, "dbl0100010000": 121, "dbl0100100000": 121, "dbl1000010000": 121, "dbl1000100000": 121, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 122, 137, 145], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 126], "dci_clk_enablemisc": 85, "dci_misc": [108, 122, 137], "dci_mod": [57, 93, 108, 122, 137], "dci_osc_sel": 50, "dci_t": [108, 122, 137], "dci_test_mux": 50, "dcireset": [98, 111, 126], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 122, 137], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 118, 119, 126, 133, 134], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 133, "dclkgtp": 66, "dclkgtp_dual": 118, "dclkgtx_dual": 119, "dclksysmon": 111, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": 64, "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": 71, "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": 64, "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": 71, "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": 102, "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_enabl": 50, "dcm_ext_fb_en": 102, "dcm_ext_fb_endcm": 102, "dcm_lock_high": 102, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_shutdown": [48, 84, 101], "dcm_unused_taps_powerdown": 102, "dcm_unused_taps_powerdowndcm": 102, "dcm_vbg_pd": 102, "dcm_vbg_sel": 102, "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": 102, "dcm_vreg_enabledcm": 102, "dcm_vreg_phase_margin": 102, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcr_autolock_en": 124, "dcr_test": 124, "dcremacclk": 116, "dcy0": [60, 112, 127, 140], "dcy0slice0": [112, 127, 140], "dcy0slice1": [60, 140], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 122], "ddr00100": 122, "ddr01": 69, "ddr01100": 122, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": [108, 122], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 134], "dec_mcomma_detect_0": [66, 118, 119], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 118, "dec_mcomma_detect_0gtx_du": 119, "dec_mcomma_detect_1": [66, 118, 119], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 118, "dec_mcomma_detect_1gtx_du": 119, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 134, "dec_mcomma_detectgtx1": 134, "dec_mcomma_detectgtx2": 134, "dec_mcomma_detectgtx3": 134, "dec_pcomma_detect": [88, 89, 105, 134], "dec_pcomma_detect_0": [66, 118, 119], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 118, "dec_pcomma_detect_0gtx_du": 119, "dec_pcomma_detect_1": [66, 118, 119], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 118, "dec_pcomma_detect_1gtx_du": 119, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 134, "dec_pcomma_detectgtx1": 134, "dec_pcomma_detectgtx2": 134, "dec_pcomma_detectgtx3": 134, "dec_valid_comma_onli": [88, 89, 105, 134], "dec_valid_comma_only_0": [66, 118, 119], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 118, "dec_valid_comma_only_0gtx_du": 119, "dec_valid_comma_only_1": [66, 118, 119], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 118, "dec_valid_comma_only_1gtx_du": 119, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 134, "dec_valid_comma_onlygtx1": 134, "dec_valid_comma_onlygtx2": 134, "dec_valid_comma_onlygtx3": 134, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 137, 142, 145, 154, 163, 165], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "default10": 122, "default_idelay_valu": 122, "default_only1011": 113, "defin": 165, "definit": 145, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [155, 156, 157, 158, 159, 160], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 155, 156, 157, 158, 159, 160], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_pt_ut": [155, 156, 157, 158, 159, 160], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "delai": [14, 44, 47, 74, 78, 117, 120, 132, 135, 142, 143], "delay0": 151, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_src": 122, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 122, "delayed_write0": 139, "delayed_write00": 125, "delaymux": 151, "delaymuxint": 151, "delaymuxiob2": 151, "delaymuxiob3": 151, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 117, 132, 142, 145, 154, 164, 165], "deriv": [12, 34, 56, 92, 163, 165], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 128, 154], "descript": [45, 99], "design": [12, 36, 58, 163, 165], "deskew_adjust": [54, 64, 90, 102], "despit": 142, "destin": 36, "detail": [35, 58, 87, 96, 164], "determin": [12, 34, 35, 46, 82, 165], "dev_cap2_ari_forwarding_support": 146, "dev_cap2_ari_forwarding_supportedpci": 146, "dev_cap2_atomicop32_completer_support": 146, "dev_cap2_atomicop32_completer_supportedpci": 146, "dev_cap2_atomicop64_completer_support": 146, "dev_cap2_atomicop_routing_support": 146, "dev_cap2_cas128_completer_support": 146, "dev_cap2_cas128_completer_supportedpci": 146, "dev_cap2_endend_tlp_prefix_support": 146, "dev_cap2_endend_tlp_prefix_supportedpci": 146, "dev_cap2_extended_fmt_field_support": 146, "dev_cap2_ltr_mechanism_support": 146, "dev_cap2_ltr_mechanism_supportedpci": 146, "dev_cap2_max_endend_tlp_prefix": 146, "dev_cap2_no_ro_enabled_prpr_pass": 146, "dev_cap2_tph_completer_support": 146, "dev_cap_enable_slot_pwr_limit_scal": [138, 146], "dev_cap_enable_slot_pwr_limit_scalepci": [138, 146], "dev_cap_enable_slot_pwr_limit_valu": [138, 146], "dev_cap_endpoint_l0s_lat": [70, 138, 146], "dev_cap_endpoint_l1_lat": [70, 138, 146], "dev_cap_ext_tag_support": [70, 138, 146], "dev_cap_ext_tag_supportedpci": [138, 146], "dev_cap_function_level_reset_cap": [138, 146], "dev_cap_max_payload_support": [70, 138, 146], "dev_cap_phantom_functions_support": [70, 138, 146], "dev_cap_role_based_error": [70, 138, 146], "dev_cap_rsvd_14_12": [138, 146], "dev_cap_rsvd_17_16": [138, 146], "dev_cap_rsvd_31_29": [138, 146], "dev_control_aux_power_support": [138, 146], "dev_control_aux_power_supportedpci": 146, "dev_control_ext_tag_default": 146, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 120, 122, 135, 137, 143, 145, 153, 162, 164], "device_id": 138, "devicebram": 45, "devicecapabilityendpointl0slat": 123, "devicecapabilityendpointl1lat": 123, "devicedcm": [51, 52, 86], "deviceid": 123, "deviceiodelai": 122, "deviceserialnumb": 123, "devicevalu": [47, 61], "devoid": 142, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [119, 134], "dfe_cfg": 134, "dfe_cfg_0": 119, "dfe_cfg_1": 119, "dfe_drp_en": 134, "dfe_drp_engtx0": 134, "dfe_drp_engtx1": 134, "dfe_drp_engtx2": 134, "dfe_drp_engtx3": 134, "dfe_train_ctrl_lane0": 133, "dfe_train_ctrl_lane1": 133, "dfe_train_ctrl_lane2": 133, "dfe_train_ctrl_lane3": 133, "dff": [14, 36, 165], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 153], "dff1": 15, "dff_latch": 127, "dff_latchslice0": 127, "dffce": 165, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 153], "dffinit": [112, 127, 140], "dffinitslice0": [112, 127, 140], "dffmux": [60, 112, 127, 140], "dffmuxslice1": 60, "dffsr": [112, 127, 140], "dffsrinit": 60, "dffsrinitslice1": 60, "dffsrslice0": 140, "dffsrslice1": 127, "dfs_": [52, 64], "dfs_ave_freq_adj_interv": 102, "dfs_ave_freq_gain": 102, "dfs_ave_freq_sample_interv": 102, "dfs_c": [52, 64], "dfs_coarse_sel": 102, "dfs_coarse_seldcm": 102, "dfs_coin_window": 102, "dfs_early_lock": 102, "dfs_early_lockdcm": 102, "dfs_en_relrst": 102, "dfs_en_relrstdcm": 102, "dfs_enabl": [51, 52, 64, 86, 102], "dfs_enabledcm": [51, 52, 86, 102], "dfs_enabledcm0": 64, "dfs_enabledcm1": 64, "dfs_extend_flush_tim": 102, "dfs_extend_flush_timedcm": 102, "dfs_extend_halt_tim": 102, "dfs_extend_halt_timedcm": 102, "dfs_extend_run_tim": 102, "dfs_extend_run_timedcm": 102, "dfs_feedback": [51, 52, 64, 86, 102], "dfs_feedbackdcm": [51, 52, 102], "dfs_feedbackdcm0": 64, "dfs_feedbackdcm1": 64, "dfs_fine_sel": 102, "dfs_fine_seldcm": 102, "dfs_frequency_mod": [51, 52, 64, 86, 102], "dfs_frequency_modedcm": [51, 52, 102], "dfs_frequency_modedcm0": 64, "dfs_frequency_modedcm1": 64, "dfs_hardsync": 102, "dfs_non_stop": 102, "dfs_non_stopdcm": 102, "dfs_oscillator_mod": 102, "dfs_skip_fin": 102, "dfs_skip_finedcm": 102, "dfs_spare": 102, "dfs_tp_sel": 102, "dfs_tp_seldcm": 102, "dfs_trackmod": 102, "dfs_trackmodedcm": 102, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 46, 81, 82, 96, 148], "di0": [102, 148], "di1": 102, "di10": 102, "di10dcm": 102, "di11": [102, 148], "di12": 102, "di126": [2, 12], "di12dcm": 102, "di13": 102, "di13dcm": 102, "di14": 102, "di14dcm": 102, "di15": 102, "di1dcm": 102, "di2": 102, "di222": [3, 12], "di288": [6, 12], "di2dcm": 102, "di3": 102, "di324": [7, 12], "di4": 102, "di44": [4, 5, 12], "di4dcm": 102, "di5": 102, "di5dcm": 102, "di6": 102, "di6dcm": 102, "di7": 102, "di8": 102, "di81": [8, 9, 12], "di9": 102, "di9dcm": 102, "dia": 96, "dia0": 72, "dia1": 72, "dia10": 72, "dia11": 72, "dia12": 72, "dia13": 72, "dia14": 72, "dia15": 72, "dia2": 72, "dia3": 72, "dia4": 72, "dia5": 72, "dia6": 72, "dia7": 72, "dia8": 72, "dia9": 72, "diagon": [55, 91], "dib": 96, "dib0": 72, "dib1": 72, "dib10": 72, "dib11": 72, "dib12": 72, "dib13": 72, "dib14": 72, "dib15": 72, "dib16": 81, "dib2": 72, "dib3": 72, "dib31": 81, "dib4": 72, "dib5": 72, "dib6": 72, "dib7": 72, "dib8": 72, "dib9": 72, "die": [12, 17, 56, 142, 145, 154], "dif": [46, 82], "dif_mux": [37, 46, 82, 99], "dif_muxslice0": 99, "diff010": [108, 122], "diff10": [74, 79], "diff101": [57, 93], "diff110": 57, "diff_hp10010": 137, "diff_lp00010": 137, "differ": [16, 35, 36, 46, 55, 82, 91, 145, 163, 165], "differenti": [14, 56, 108, 122, 137, 145], "dig": [46, 82], "dig_mux": [37, 46, 82, 99], "dig_muxslice0": 99, "dig_muxslice2": 99, "digit": [44, 54, 55, 56, 67, 90, 91, 92, 106], "digrx_fwdclk": 105, "digrx_sync_mod": 105, "digrx_sync_modegt11a": 105, "digrx_sync_modegt11b": 105, "dimens": 58, "dimension": 153, "din": [137, 145], "din0": 72, "din0000": 72, "din0001": 72, "din0int": 72, "din1": 72, "din10": 72, "din1000": 72, "din10000": 72, "din10001": 72, "din1001": 72, "din10int": 72, "din11": 72, "din11001": 72, "din11010": 72, "din11int": 72, "din12": 72, "din12010": 72, "din12011": 72, "din12int": 72, "din13": 72, "din13010": 72, "din13011": 72, "din13int": 72, "din14": 72, "din14010": 72, "din14011": 72, "din14int": 72, "din15": 72, "din15000": 72, "din15011": 72, "din15int": 72, "din16": 72, "din16110": 72, "din16111": 72, "din16int": 72, "din17": 72, "din17100": 72, "din17111": 72, "din17int": 72, "din18": 72, "din18100": 72, "din18101": 72, "din18int": 72, "din19": 72, "din19100": 72, "din19101": 72, "din19int": 72, "din1int": 72, "din2": 72, "din20": 72, "din2000": 72, "din2001": 72, "din20100": 72, "din20101": 72, "din20int": 72, "din21": 72, "din21101": 72, "din21110": 72, "din21int": 72, "din22": 72, "din22110": 72, "din22111": 72, "din22int": 72, "din23": 72, "din23110": 72, "din23111": 72, "din23int": 72, "din24": 72, "din24110": 72, "din24111": 72, "din24int": 72, "din25": 72, "din25100": 72, "din25111": 72, "din25int": 72, "din26": 72, "din26100": 72, "din26101": 72, "din26int": 72, "din27": 72, "din27100": 72, "din27101": 72, "din27int": 72, "din28": 72, "din28100": 72, "din28101": 72, "din28int": 72, "din29": 72, "din29101": 72, "din29110": 72, "din29int": 72, "din2int": 72, "din3": 72, "din30": 72, "din3001": 72, "din3010": 72, "din30110": 72, "din30111": 72, "din30int": 72, "din31": 72, "din31110": 72, "din31111": 72, "din31int": 72, "din3int": 72, "din4": 72, "din4010": 72, "din4011": 72, "din4int": 72, "din5": 72, "din5010": 72, "din5011": 72, "din5int": 72, "din6": 72, "din6010": 72, "din6011": 72, "din6int": 72, "din7": 72, "din7000": 72, "din7011": 72, "din7int": 72, "din8": 72, "din8000": 72, "din8001": 72, "din8int": 72, "din9": 72, "din9000": 72, "din9001": 72, "din9int": 72, "dinpin": [98, 111, 126], "dip": [81, 96], "dipa": 96, "dipb": 96, "direct": [36, 55, 81, 91], "direct0": [45, 53, 65, 103, 115, 130, 134, 141], "directli": [14, 17, 35, 36, 46, 58, 81, 82, 91, 154, 165], "dis_tstblclamp": 139, "dis_tstfiforst": [125, 139], "dis_vgg_reg": 129, "disabl": [36, 165], "disable111": 149, "disable_aspm_l1_tim": [138, 146], "disable_aspm_l1_timerpci": [138, 146], "disable_attr": [47, 61, 74, 83], "disable_attrbufg1": 74, "disable_attrbufgmux0": 47, "disable_attrbufgmux2": 47, "disable_attrbufgmux6": 47, "disable_attrbufgmux7": 47, "disable_attrint": 74, "disable_bar_filt": [70, 138, 146], "disable_err_msg": 146, "disable_gt": [57, 93], "disable_gtsiob0": 57, "disable_gtsiob1": 93, "disable_gtsiob2": [57, 93], "disable_gtsiob3": 57, "disable_gtsiob4": [57, 93], "disable_id_check": [70, 138, 146], "disable_id_checkpci": [138, 146], "disable_jtag": 126, "disable_lane_revers": [138, 146], "disable_lane_reversalpci": 138, "disable_locked_filt": 146, "disable_ppm_filt": 146, "disable_ppm_filterpci": 146, "disable_rx_poisoned_resp": 146, "disable_rx_poisoned_resppci": 146, "disable_rx_tc_filt": [138, 146], "disable_scrambl": [70, 138, 146], "disable_scramblingpci": 146, "disable_vrd_reg": 62, "disablebandgap": 85, "disablebandgapmisc": 85, "disablevgggener": 85, "disablevgggenerationmisc": 85, "disconnect": [55, 165], "displac": 58, "dispmp1": 75, "dispmp2": 75, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 55, 58, 91], "distribut": [41, 54, 55, 58, 87, 90, 91, 132, 142], "distrubut": 132, "div12110": 69, "div2001": 69, "div201": 69, "div4010": 69, "div410": 69, "div60": 69, "div6011": 69, "div71": 69, "div8100": 69, "divclk11": 61, "divid": [11, 12, 58, 61, 104, 117, 132, 142, 153, 165], "divide_100": 61, "divide_1000": 61, "divide_2001": 61, "divide_201": 61, "divide_300": 61, "divide_3010": 61, "divide_400": 61, "divide_4011": 61, "divide_501": 61, "divide_5100": 61, "divide_601": 61, "divide_6101": 61, "divide_710": 61, "divide_7110": 61, "divide_810": 61, "divide_8111": 61, "divide_bypass": 61, "divis": [96, 163], "dll": [51, 74, 78, 86, 92], "dll_": [52, 64], "dll_c": [52, 64], "dll_cfg0": 133, "dll_cfg1": 133, "dll_control_clock_spe": 102, "dll_control_clock_speeddcm": 102, "dll_ctl_sel_clkin_div2": 102, "dll_ctl_sel_clkin_div2dcm": 102, "dll_dead_tim": 102, "dll_deskew_lock_by1": 102, "dll_deskew_lock_by1dcm": 102, "dll_deskew_maxtap": 102, "dll_deskew_mintap": 102, "dll_enabl": [51, 52, 64, 76, 86, 102], "dll_enabledcm": [51, 52, 102], "dll_enabledcm0": 64, "dll_enabledcm1": 64, "dll_enablemisc": 76, "dll_frequency_mod": [51, 52, 64, 86, 102], "dll_frequency_modedcm": 52, "dll_frequency_modedcm0": 64, "dll_frequency_modedcm1": 64, "dll_live_tim": 102, "dll_pd_dly_sel": 102, "dll_period_lock_by1": 102, "dll_period_lock_by1dcm": 102, "dll_phase_detector_auto_reset": 102, "dll_phase_detector_auto_resetdcm": 102, "dll_phase_detector_mod": 102, "dll_phase_detector_modedcm": 102, "dll_phase_shift_calibr": 102, "dll_phase_shift_hfc": 102, "dll_phase_shift_lfc": 102, "dll_phase_shift_lock_by1": 102, "dll_phase_shift_lock_by1dcm": 102, "dll_settle_tim": 102, "dll_spare": 102, "dll_test_mux_sel": 102, "dll_wait_bl": 75, "dll_wait_br": 75, "dll_wait_tl": 75, "dll_wait_tr": 75, "dllc": [51, 86], "dllp": 78, "dma0_control": 124, "dma0_rxchannelctrl": 124, "dma0_rxirqtim": 124, "dma0_txchannelctrl": 124, "dma0_txirqtim": 124, "dma1_control": 124, "dma1_rxchannelctrl": 124, "dma1_rxirqtim": 124, "dma1_txchannelctrl": 124, "dma1_txirqtim": 124, "dma2_control": 124, "dma2_rxchannelctrl": 124, "dma2_rxirqtim": 124, "dma2_txchannelctrl": 124, "dma2_txirqtim": 124, "dma3_control": 124, "dma3_rxchannelctrl": 124, "dma3_rxirqtim": 124, "dma3_txchannelctrl": 124, "dma3_txirqtim": 124, "dma_test": 124, "dmux": 148, "dna_opt": 63, "dna_port": [56, 63, 126], "dnstream_link_num": [138, 146, 147], "do": [35, 46, 81, 82, 91, 96, 145], "do1": 148, "do11000": 148, "do11001": 148, "do11010": 148, "do11011": 148, "doa": [81, 96], "doa0": [72, 96], "doa0int": 72, "doa1": 72, "doa10": 72, "doa10int": 72, "doa11": 72, "doa11int": 72, "doa12": 72, "doa12int": 72, "doa13": 72, "doa13int": 72, "doa14": 72, "doa14int": 72, "doa15": 72, "doa15int": 72, "doa1int": 72, "doa2": 72, "doa3": 72, "doa31": 96, "doa4": 72, "doa4int": 72, "doa5": 72, "doa6": 72, "doa6int": 72, "doa7": 72, "doa8": 72, "doa8int": 72, "doa9": 72, "doa9int": 72, "doa_reg": [45, 59, 96], "doa_reg_l": [110, 125, 139], "doa_reg_u": [110, 125, 139], "dob": [81, 96], "dob0": 72, "dob0int": 72, "dob1": 72, "dob10": [72, 96], "dob10int": 72, "dob11": [72, 96], "dob11int": 72, "dob12": 72, "dob12int": 72, "dob13": 72, "dob13int": 72, "dob14": 72, "dob14int": 72, "dob15": 72, "dob15int": 72, "dob1int": 72, "dob2": 72, "dob3": 72, "dob4": [72, 96], "dob4int": 72, "dob5": [72, 96], "dob6": [72, 96], "dob6int": 72, "dob7": [72, 96], "dob8": [72, 96], "dob8int": 72, "dob9": [72, 96], "dob9int": 72, "dob_reg": [45, 59, 96], "dob_reg_l": [110, 125, 139], "dob_reg_u": [110, 125, 139], "document": [15, 16, 38, 39, 40, 41, 43, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 57, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 88, 89, 93, 94, 95, 98, 99, 101, 104, 105, 106, 107, 108, 111, 112, 114, 117, 118, 119, 120, 121, 122, 126, 127, 129, 132, 133, 134, 135, 136, 137, 140, 142, 143, 144, 150], "doe": [34, 142], "doesn": [16, 36, 46, 55, 58, 81, 91, 142, 165], "domux": 148, "domuxlc2": 148, "don": [35, 36, 46, 55, 58, 142, 165], "done": [2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 34, 35, 36, 96, 108, 122, 137, 145], "done110": [39, 48, 75, 84, 101, 114, 129], "done111": [49, 62], "done_act": 149, "done_cycl": [39, 48, 49, 62, 75, 84, 101, 114, 129], "done_in00": 149, "done_pip": [39, 48, 49, 62, 75, 84, 101, 114, 129], "done_signals_powerdown": 129, "donein": 149, "donepin": [50, 63, 76, 85, 98, 111, 126, 149], "donepinint": 149, "donepinmisc": 76, "dont_set1": 115, "dop": [81, 96], "dopa": 96, "doubl": [55, 91], "dout": 145, "dout0": 72, "dout000": 72, "dout0000": 72, "dout001": 72, "dout0int": 72, "dout1": 72, "dout10": 72, "dout100": 72, "dout1000": 72, "dout1001": 72, "dout10010": 72, "dout101": 72, "dout10int": 72, "dout11": 72, "dout1100": 72, "dout1101": 72, "dout11010": 72, "dout11int": 72, "dout12": 72, "dout1200": 72, "dout1201": 72, "dout12011": 72, "dout12int": 72, "dout13": 72, "dout1300": 72, "dout1301": 72, "dout13011": 72, "dout13int": 72, "dout14": 72, "dout1400": 72, "dout1401": 72, "dout14011": 72, "dout14int": 72, "dout15": 72, "dout1500": 72, "dout1501": 72, "dout15011": 72, "dout15int": 72, "dout16": 72, "dout1610": 72, "dout16100": 72, "dout1611": 72, "dout16int": 72, "dout17": 72, "dout1710": 72, "dout17100": 72, "dout1711": 72, "dout17int": 72, "dout18": 72, "dout1810": 72, "dout18100": 72, "dout1811": 72, "dout18int": 72, "dout19": 72, "dout1910": 72, "dout19100": 72, "dout1911": 72, "dout19int": 72, "dout1int": 72, "dout2": 72, "dout20": 72, "dout200": 72, "dout2000": 72, "dout201": 72, "dout2010": 72, "dout20101": 72, "dout2011": 72, "dout20int": 72, "dout21": 72, "dout2110": 72, "dout21101": 72, "dout2111": 72, "dout21int": 72, "dout22": 72, "dout2210": 72, "dout22101": 72, "dout2211": 72, "dout22int": 72, "dout23": 72, "dout2310": 72, "dout23101": 72, "dout2311": 72, "dout23int": 72, "dout24": 72, "dout2410": 72, "dout2411": 72, "dout24110": 72, "dout24int": 72, "dout25": 72, "dout2510": 72, "dout2511": 72, "dout25110": 72, "dout25int": 72, "dout26": 72, "dout2610": 72, "dout2611": 72, "dout26110": 72, "dout26int": 72, "dout27": 72, "dout2710": 72, "dout2711": 72, "dout27110": 72, "dout27int": 72, "dout28": 72, "dout2810": 72, "dout2811": 72, "dout28111": 72, "dout28int": 72, "dout29": 72, "dout2910": 72, "dout2911": 72, "dout29111": 72, "dout29int": 72, "dout2int": 72, "dout3": 72, "dout30": 72, "dout300": 72, "dout3000": 72, "dout301": 72, "dout3010": 72, "dout3011": 72, "dout30111": 72, "dout30int": 72, "dout31": 72, "dout3110": 72, "dout3111": 72, "dout31111": 72, "dout31int": 72, "dout3int": 72, "dout4": 72, "dout400": 72, "dout4001": 72, "dout401": 72, "dout4int": 72, "dout5": 72, "dout500": 72, "dout5001": 72, "dout501": 72, "dout5int": 72, "dout6": 72, "dout600": 72, "dout6001": 72, "dout601": 72, "dout6int": 72, "dout7": 72, "dout700": 72, "dout7001": 72, "dout701": 72, "dout7int": 72, "dout8": 72, "dout800": 72, "dout801": 72, "dout8010": 72, "dout8int": 72, "dout9": 72, "dout900": 72, "dout901": 72, "dout9010": 72, "dout9int": 72, "dout_busi": [108, 137], "doutmux": [60, 112, 127, 140], "doutmuxslice1": 60, "down": [36, 55, 56, 58, 104, 165], "down0": 15, "down1": [16, 153], "downward": [36, 122], "dpm": 97, "dpm_oscout10001000100": 97, "dpm_oscout20001000010": 97, "dpm_refclkout0001010000": 97, "dq": 145, "dqs0011": 61, "dqs2110": 61, "dr": [13, 153], "drain": 14, "drammod": [60, 112, 127, 140], "drck": 149, "drck100": 76, "drck200": 76, "dreg": [53, 65, 130, 141], "dregdsp": [53, 65], "dregdsp0": 130, "dregdsp1": 130, "drive": [12, 14, 17, 34, 35, 36, 55, 56, 58, 72, 73, 74, 76, 79, 82, 91, 108, 122, 137, 145, 163, 165], "drive_awak": [49, 62], "drive_both111": 105, "drive_don": [39, 48, 49, 62, 75, 84, 101, 114, 129], "drive_down110": 105, "drive_last_value0001": 57, "drive_pd_statu": 76, "drive_pd_statusmisc": 76, "drive_up101": 105, "driven": [14, 36, 55, 58, 87, 91, 165], "driver": [12, 34, 55, 91], "drp00": [66, 71, 118, 119, 134], "drp000": 133, "drp001": 133, "drp002": 133, "drp003": 133, "drp004": 133, "drp005": 133, "drp006": 133, "drp007": 133, "drp008": 133, "drp009": 133, "drp00a": 133, "drp00b": 133, "drp00c": 133, "drp00d": 133, "drp00e": 133, "drp00f": 133, "drp01": [66, 71, 118, 119, 134], "drp010": 133, "drp011": 133, "drp012": 133, "drp013": 133, "drp014": 133, "drp015": 133, "drp016": 133, "drp017": 133, "drp018": 133, "drp019": 133, "drp01a": 133, "drp01b": 133, "drp01c": 133, "drp01d": 133, "drp01e": 133, "drp01f": 133, "drp02": [66, 71, 118, 119, 134], "drp020": 133, "drp021": 133, "drp022": 133, "drp023": 133, "drp024": 133, "drp025": 133, "drp026": 133, "drp027": 133, "drp028": 133, "drp029": 133, "drp02a": 133, "drp02b": 133, "drp02c": 133, "drp02d": 133, "drp02e": 133, "drp02f": 133, "drp03": [66, 71, 118, 119, 134], "drp030": 133, "drp031": 133, "drp032": 133, "drp033": 133, "drp034": 133, "drp035": 133, "drp036": 133, "drp037": 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"drp071": 133, "drp072": 133, "drp073": 133, "drp074": 133, "drp075": 133, "drp076": 133, "drp077": 133, "drp078": 133, "drp079": 133, "drp07a": 133, "drp07b": 133, "drp07c": 133, "drp07d": 133, "drp07e": 133, "drp07f": 133, "drp08": [66, 71, 118, 119, 134], "drp080": 133, "drp081": 133, "drp082": 133, "drp083": 133, "drp084": 133, "drp085": 133, "drp086": 133, "drp087": 133, "drp088": 133, "drp089": 133, "drp08a": 133, "drp08b": 133, "drp08c": 133, "drp08d": 133, "drp08e": 133, "drp08f": 133, "drp09": [66, 71, 118, 119, 134], "drp090": 133, "drp091": 133, "drp092": 133, "drp093": 133, "drp094": 133, "drp095": 133, "drp096": 133, "drp097": 133, "drp098": 133, "drp099": 133, "drp09a": 133, "drp09b": 133, "drp09c": 133, "drp09d": 133, "drp09e": 133, "drp09f": 133, "drp0a": [66, 71, 118, 119, 134], "drp0a0": 133, "drp0a1": 133, "drp0a2": 133, "drp0a3": 133, "drp0a4": 133, "drp0a5": 133, "drp0a6": 133, "drp0a7": 133, "drp0a8": 133, "drp0a9": 133, "drp0aa": 133, "drp0ab": 133, "drp0ac": 133, "drp0ad": 133, "drp0ae": 133, "drp0af": 133, "drp0b": [66, 71, 118, 119, 134], "drp0b0": 133, "drp0b1": 133, "drp0b2": 133, "drp0b3": 133, "drp0b4": 133, "drp0b5": 133, "drp0b6": 133, "drp0b7": 133, "drp0b8": 133, "drp0b9": 133, "drp0ba": 133, "drp0bb": 133, "drp0bc": 133, "drp0bd": 133, "drp0be": 133, "drp0bf": 133, "drp0c": [66, 71, 118, 119, 134], "drp0c0": 133, "drp0c1": 133, "drp0c2": 133, "drp0c3": 133, "drp0c4": 133, "drp0c5": 133, "drp0c6": 133, "drp0c7": 133, "drp0c8": 133, "drp0c9": 133, "drp0ca": 133, "drp0cb": 133, "drp0cc": 133, "drp0cd": 133, "drp0ce": 133, "drp0cf": 133, "drp0d": [66, 71, 118, 119, 134], "drp0d0": 133, "drp0d1": 133, "drp0d2": 133, "drp0d3": 133, "drp0d4": 133, "drp0d5": 133, "drp0d6": 133, "drp0d7": 133, "drp0d8": 133, "drp0d9": 133, "drp0da": 133, "drp0db": 133, "drp0dc": 133, "drp0dd": 133, "drp0de": 133, "drp0df": 133, "drp0e": [66, 71, 118, 119, 134], "drp0e0": 133, "drp0e1": 133, "drp0e2": 133, "drp0e3": 133, "drp0e4": 133, "drp0e5": 133, "drp0e6": 133, "drp0e7": 133, "drp0e8": 133, "drp0e9": 133, "drp0ea": 133, "drp0eb": 133, "drp0ec": 133, "drp0ed": 133, "drp0ee": 133, "drp0ef": 133, "drp0f": [66, 71, 118, 119, 134], "drp0f0": 133, "drp0f1": 133, "drp0f2": 133, "drp0f3": 133, "drp0f4": 133, "drp0f5": 133, "drp0f6": 133, "drp0f7": 133, "drp0f8": 133, "drp0f9": 133, "drp0fa": 133, "drp0fb": 133, "drp0fc": 133, "drp0fd": 133, "drp0fe": 133, "drp0ff": 133, "drp10": [66, 71, 118, 119, 134], "drp100": 133, "drp101": 133, "drp102": 133, "drp103": 133, "drp104": 133, "drp105": 133, "drp106": 133, "drp107": 133, "drp108": 133, "drp109": 133, "drp10a": 133, "drp10b": 133, "drp10c": 133, "drp10d": 133, "drp10e": 133, "drp10f": 133, "drp11": [66, 71, 118, 119, 134], "drp110": 133, "drp111": 133, "drp112": 133, "drp113": 133, "drp114": 133, "drp115": 133, "drp116": 133, "drp117": 133, "drp118": 133, "drp119": 133, "drp11a": 133, "drp11b": 133, "drp11c": 133, "drp11d": 133, "drp11e": 133, "drp11f": 133, "drp12": [66, 71, 118, 119, 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151, 152, 157, 158, 159, 160], "h20": [6, 7, 24, 159, 160], "h21": [6, 7, 159, 160], "h2110": 149, "h211010": 149, "h22": [6, 7, 159, 160], "h23": [22, 23], "h24": [22, 23], "h25": [22, 23], "h26": [22, 23], "h2int": 151, "h3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 76, 77, 79, 148, 149, 151, 152, 156, 157, 158, 159, 160], "h3100": 149, "h311100": 149, "h4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 76, 79, 148, 149, 151, 152, 156, 157, 158, 159, 160], "h4000": 149, "h41101": 149, "h4111101111": 149, "h4int": 151, "h5": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 72, 76, 79, 148, 149, 151, 152, 156, 158, 159, 160], "h5010": 149, "h5111110111": 149, "h5int": 151, "h6": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 148, 149, 151, 152, 156, 158, 159, 160], "h6100": 149, "h6111111011": 149, "h7": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 148, 149, 151, 152, 156, 158, 159, 160], "h7110": 149, "h7111111101": 149, "h8": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 156, 158, 159, 160], "h9": [2, 3, 6, 7, 24, 25, 158, 159, 160], "ha": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 142, 145, 153, 163, 164, 165], "had": 104, "half": [55, 58, 87, 91, 104, 107, 117, 132, 137], "half0": [51, 52, 55, 64, 77, 86, 102], "half01": 69, "half010": 69, "half1": [55, 69], "half10": 91, "half1001": 69, "half11": 91, "half12": 91, "half13": 91, "half14": 91, "half15": 91, "half16": 91, "half17": 91, "half2": 55, "half2101": 69, "half3": 55, "half8": 91, "half9": 91, "halv": 104, "handl": [55, 91], "happen": [35, 36, 165], "hard": [44, 55, 56, 58, 87, 90, 92, 104, 117, 132, 142], "hardwar": [81, 96], "hardwir": [14, 36, 46, 82], "hasn": 35, "have": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 55, 56, 58, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 142, 145, 153, 154, 163, 165], "hc_cycl": [49, 62], "hc_opt": [54, 67], "hclk": [67, 104, 106, 108, 117, 120, 122, 132, 135, 137, 142, 145], "hclk0": [64, 71, 97, 100, 102, 113, 128], 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"iff_latch": [57, 79, 93, 108, 122], "iff_latchiob1": 79, "iff_latchiob2": 79, "iff_latchiob3": 79, "iff_rev_en": [57, 93], "iff_rev_enableioi1": 57, "iff_rev_us": 122, "iff_rev_usedilogic0": 122, "iff_rev_usedilogic1": 122, "iff_sr_en": [57, 79, 93], "iff_sr_enableiob1": 79, "iff_sr_enableiob2": 79, "iff_sr_enableiob3": 79, "iff_sr_enableioi0": 57, "iff_sr_enableioi1": 57, "iff_sr_enableioi2": 57, "iff_sr_us": 122, "iff_sr_usedologic0": 122, "iff_sr_usedologic1": 122, "iff_sync": [57, 79, 93, 108, 122], "iff_synciob1": 79, "iff_synciob2": 79, "iff_synciob3": 79, "iff_syncioi0": 57, "iff_syncioi2": 57, "iff_syncologic0": 122, "iff_syncologic1": 122, "iff_tsbypass_en": [57, 93, 108, 122], "iff_tsbypass_enableilogic0": 122, "iff_tsbypass_enableilogic1": 122, "iffdmux001": 57, "ignor": [35, 46, 82], "ignore0": [98, 111, 128], "ignore1": [98, 111, 128], "ii": [0, 12, 14], "iint": [73, 79, 151], "iiob1": 151, "ilogic0": [108, 122], "ilogic1": [108, 122], "im": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 36, 153, 155, 156, 157, 158, 159, 160, 165], "immateri": 164, "immedi": [35, 55, 58, 81, 91, 96, 104, 117, 122], "imped": 92, "implement": [35, 36, 46, 58, 81, 82, 87, 96, 165], "import_": 36, "import_chain_down": 36, "import_chain_up": 36, "import_down_alloc": 36, "import_down_alloc24": [15, 16], "import_sum_down": 36, "import_sum_up": 36, "import_up_alloc": 36, "import_up_alloc23": [15, 16], "improv": [56, 96], "imux": [10, 17, 32, 38, 42, 47, 55, 61, 68, 72, 73, 74, 76, 77, 79, 80, 83, 91, 107, 121, 136, 144, 148, 149, 151, 154, 161, 162], "imux0": [61, 107, 121, 136, 144], "imux001": [121, 136, 144], "imux1": [61, 107, 121, 136, 144], "imux10": [61, 107, 121, 136, 144], "imux100": 107, "imux101": [121, 136, 144], "imux1010": [121, 136, 144], "imux11": [61, 107, 121, 136, 144], "imux110": 107, "imux1110": [121, 136, 144], "imux12": [61, 107, 121, 136, 144], "imux121": 121, "imux1210": 144, "imux121000": 136, "imux13": [61, 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107, 121, 136, 144], "imux60": 107, "imux60010": 136, "imux601": 144, "imux610": 121, "imux7": [61, 107, 121, 136, 144], "imux70": 107, "imux70010": 136, "imux701": 144, "imux710": 121, "imux8": [61, 107, 121, 136, 144], "imux80": 107, "imux810": [121, 136, 144], "imux9": [61, 107, 121, 136, 144], "imux90": 107, "imux910": [121, 136, 144], "imux_bit": [17, 154], "imux_col": [153, 154], "imux_en": 98, "imux_width": [153, 154], "in_b00": [47, 83], "in_b10": [47, 83], "in_b20": [47, 83], "in_b30": [47, 83], "in_b40": 83, "in_b50": 83, "in_b60": 83, "in_b70": 83, "in_core010": 47, "in_core110": 47, "in_core210": 47, "in_core310": 47, "in_core410": 47, "in_core510": 47, "in_core610": 47, "in_core710": 47, "in_l01": 47, "in_l11": 47, "in_l21": 47, "in_l31": 47, "in_l41": 47, "in_l51": 47, "in_l61": 47, "in_l71": 47, "in_lr001": 47, "in_lr101": 47, "in_lr201": 47, "in_lr301": 47, "in_lr401": 47, "in_lr501": 47, "in_lr601": 47, "in_lr701": 47, "in_r01": 47, "in_r11": 47, "in_r21": 47, "in_r31": 47, "in_r41": 47, "in_r51": 47, "in_r61": 47, "in_r71": 47, "in_t00": 47, "in_t01": 83, "in_t10": 47, "in_t11": 83, "in_t20": 47, "in_t21": 83, "in_t30": 47, "in_t31": 83, "in_t41": 83, "in_t51": 83, "in_t61": 83, "in_t71": 83, "inapplic": 145, "includ": [12, 14, 15, 17, 35, 36, 55, 56, 58, 91, 104, 117, 153, 154, 163, 165], "incom": 91, "increas": [122, 165], "increment": 35, "independ": [14, 96, 104, 117, 132, 142, 165], "indetermin": [36, 46, 82], "index": [15, 16, 17, 35, 36, 91, 96, 154], "indic": [35, 154], "individu": [14, 36], "infer_ei": [138, 146], "infiniband10": 88, "infiniband11": 89, "infinitecomplet": 123, "infinitecompletionspci": 123, "inform": 164, "init": [108, 122], "init_": [81, 96], "init_4": [109, 111, 126], "init_40": [109, 111, 126], "init_41": [109, 111, 126], "init_42": [109, 111, 126], "init_43": [109, 111, 126], "init_44": [109, 111, 126], "init_45": [109, 111, 126], "init_46": [109, 111, 126], "init_47": [109, 111, 126], "init_48": [109, 111, 126], "init_49": [109, 111, 126], "init_4a": [109, 111, 126], "init_4b": [109, 111, 126], "init_4c": [109, 111, 126], "init_4d": [109, 111, 126], "init_4f": [109, 111, 126], "init_5": 109, "init_50": [109, 111, 126], "init_51": [109, 111, 126], "init_52": [109, 111, 126], "init_53": [109, 111, 126], "init_54": [109, 111, 126], "init_55": [109, 111, 126], "init_56": [109, 111, 126], "init_57": [109, 111, 126], "init_58": 109, "init_59": 109, "init_5a": 109, "init_5b": 109, "init_5c": 109, "init_5d": 109, "init_5f": 109, "init_6": 109, "init_60": 109, "init_61": 109, "init_62": 109, "init_63": 109, "init_64": 109, "init_65": 109, "init_66": 109, "init_67": 109, "init_68": 109, "init_69": 109, "init_6a": 109, "init_6b": 109, "init_6c": 109, "init_6d": 109, "init_6f": 109, "init_a": [45, 59, 81, 96], "init_a_l": [110, 125, 139], "init_a_u": [110, 125, 139], "init_b": [45, 59, 81, 96, 137, 145], "init_b_l": [110, 125, 139], "init_b_u": [110, 125, 139], "init_bitslipcnt": [108, 122], "init_c": [108, 122], "init_loadcnt": [108, 122], "init_out": [98, 111, 128], "init_outbufgctrl0": 98, "init_outbufgctrl1": 98, "init_outbufgctrl10": 98, "init_outbufgctrl11": 98, "init_outbufgctrl12": 98, "init_outbufgctrl13": 98, "init_outbufgctrl14": 98, "init_outbufgctrl15": 98, "init_outbufgctrl16": 98, "init_outbufgctrl17": 98, "init_outbufgctrl18": 98, "init_outbufgctrl19": 98, "init_outbufgctrl2": 98, "init_outbufgctrl20": 98, "init_outbufgctrl21": 98, "init_outbufgctrl22": 98, "init_outbufgctrl23": 98, "init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_rank1_parti": [108, 122], "init_rank2": [108, 122], "init_rank3": [108, 122], "init_signals_error": 129, "init_skip": 62, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 165], "initp_xx": [81, 96], "initpin": [98, 111, 126], "initpinmisc": 111, "initx": 73, "initxint": 73, "initxslice1": 73, "inityint": 73, "inmode0": [130, 141], "inmode1": [130, 141], "inmode2": [130, 141], "inmode3": [130, 141], "inmode4": [130, 141], "inmodereg": [130, 141], "inner": [58, 87, 104, 117, 132, 137], "input": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 33, 34, 35, 41, 44, 46, 54, 56, 78, 81, 82, 90, 92, 96, 104, 106, 117, 120, 132, 135, 142, 143, 149, 150, 153, 154, 162, 163, 164], "inputtest": 55, "insan": 82, "insert": 142, "insid": [55, 91], "instanc": 87, "instanti": [55, 91], "instead": [12, 14, 16, 34, 35, 36, 42, 56, 58, 81, 91, 108, 142, 145, 163, 165], "instruct": [11, 33, 36, 56, 92, 162], "int": [17, 37, 38, 45, 46, 47, 53, 58, 61, 65, 68, 72, 73, 74, 76, 77, 79, 80, 81, 82, 83, 87, 96, 99, 104, 107, 117, 121, 132, 136, 142, 144, 148, 149, 151, 152, 154], "int0": 45, "int00": [130, 141], "int000": 139, "int00001": 47, "int0001": [47, 83, 151], "int001": 47, "int01": 38, "int1": [51, 52, 64, 77, 86, 102], "int_clk00001": 109, "int_imux00000": 109, "integ": [17, 154], "interconnect": [14, 36, 37, 41, 44, 45, 46, 54, 56, 58, 67, 78, 81, 82, 87, 90, 92, 96, 104, 106, 117, 120, 132, 135, 137, 142, 143, 165], "interconnect_imask": 124, "interconnect_tmpl_sel": 124, "intereconnect": 142, "interfac": [11, 33, 41, 52, 54, 58, 64, 67, 87, 90, 106, 162], "interface_typ": [108, 122], "interface_typeilogic0": 108, "interface_typeilogic1": 108, "interfer": [46, 82], "interleav": 16, "intern": [36, 56, 92, 96, 142, 164], "internal1": 129, "internal_vref": [113, 137], "internalclk0": [49, 62], "interpos": 142, "interpret": 17, "interrupt": [35, 91], "interrupt_pin": [138, 146], "interrupt_stat_auto": 146, "interrupt_stat_autopci": 146, "interruptpin": 123, "intersect": [38, 47, 55, 58, 87, 104, 117, 132, 142], "intest": [13, 35, 164], "intf": [104, 107, 117, 120, 132, 135, 142, 143], "intosc00": 76, "intro": [41, 54, 67, 78, 106, 120, 135, 143, 150], "introduc": [58, 96, 142], "introduct": [11, 33, 44, 54, 90, 162], "inv": [15, 36, 37, 42, 43, 46, 47, 51, 52, 55, 57, 59, 60, 61, 64, 65, 66, 69, 71, 72, 73, 74, 76, 77, 79, 80, 83, 86, 91, 93, 96, 97, 98, 99, 102, 103, 107, 108, 109, 110, 111, 112, 115, 116, 118, 119, 122, 123, 124, 125, 126, 127, 128, 130, 133, 134, 139, 140, 141, 148, 149, 151], "inv0010": 151, "inv1000": 151, "inv22": [15, 16], "invalid": [15, 16, 35], "invers": [17, 34, 36, 57, 59, 79, 82, 93, 108, 122, 137, 154, 165], "invert": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 17, 23, 36, 37, 38, 39, 40, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52, 55, 57, 59, 60, 61, 62, 63, 64, 65, 66, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 91, 93, 96, 97, 98, 99, 100, 101, 102, 103, 105, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 118, 119, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 133, 134, 136, 137, 138, 139, 140, 141, 144, 146, 147, 148, 149, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 165], "invert_clk_do": 96, "invert_clk_doa_reg": 96, "invert_clk_dob_reg": 96, "invert_zd1_custom": 51, "invert_zd1_customdcm": 51, "inverted0": 69, "involv": [15, 16, 36, 87, 104, 117, 165], "io": [17, 54, 55, 56, 78, 81, 90, 91, 92, 104, 106, 108, 117, 120, 122, 132, 135, 149, 150], "io0": [79, 151], "io0011": 122, "io1": [79, 151], "io2": [79, 151], "io3": [79, 151], "io_mc": [153, 154, 164], "io_speci": [17, 154], "io_special_overrid": 17, "iob": [10, 11, 17, 35, 36, 47, 58, 78, 83, 87, 91, 106, 108, 120, 122, 137, 145, 154, 162, 164], "iob0": [57, 93, 108, 122, 137, 145, 151], "iob1": [57, 79, 93, 108, 122, 137, 145, 151], "iob2": [57, 79, 93, 151], "iob3": [57, 79, 93, 151], "iob4": [57, 93], "iob5": [57, 93], "iob6": 57, "iob7": 57, "iob_": [17, 34, 36, 154, 165], "iob_0_0": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], 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[47, 83], "out_r0gclkc": 83, "out_r1": [47, 83], "out_r1gclkc": 83, "out_r2": [47, 83], "out_r2gclkc": 83, "out_r3": [47, 83], "out_r3gclkc": 83, "out_r4": [47, 83], "out_r4gclkc": 83, "out_r5": [47, 83], "out_r5gclkc": 83, "out_r6": [47, 83], "out_r6gclkc": 83, "out_r7": [47, 83], "out_r7gclkc": 83, "out_t0": [38, 47, 83], "out_t1": [38, 47, 83], "out_t1gclkh": [38, 47, 83], "out_t2": [38, 47, 83], "out_t2gclkh": [38, 47, 83], "out_t3": [38, 47, 83], "out_t3gclkh": [38, 47, 83], "out_t4": [38, 47, 83], "out_t4gclkh": [38, 47, 83], "out_t5": [38, 47, 83], "out_t5gclkh": [38, 47, 83], "out_t6": [38, 47, 83], "out_t6gclkh": [38, 47, 83], "out_t7": [38, 47, 83], "out_t7gclkh": [38, 47, 83], "out_u0": 128, "out_u1": 128, "out_u2": 128, "out_u3": 128, "out_u4": 128, "out_u5": 128, "out_u6": 128, "out_u7": 128, "out_uim": 36, "outbus0": 83, "outbus1": 83, "outbus2": 83, "outbus3": 83, "outbus4": 83, "outbus4dcmconn": 83, "outbus5": 83, "outbus5dcmconn": 83, "outbus6": 83, "outbus7": 83, "outd_clkout0": 61, "outd_clkout1": 61, "outd_lock": 61, "outer": [132, 137], "outgo": 91, "outl_clkout0": 61, "outl_clkout1": 61, "outl_locked0": 61, "outl_locked1": 61, "output": [11, 12, 33, 34, 35, 41, 44, 54, 56, 78, 81, 90, 92, 96, 104, 106, 117, 120, 132, 135, 142, 143, 150, 162, 164], "output0001": [57, 93], "output001": [108, 122, 137], "output_delai": [122, 137], "output_delayiob0": 122, "output_delayiob1": 122, "output_diff": [57, 93], "output_diff_group": 57, "output_en": [57, 93, 108, 122, 137], "output_half0010": [57, 93], "output_half010": [108, 122, 137], "output_ht_25101000000001100011": 122, "output_ht_25101100000011001110": 137, "output_ldt_2501100110": 108, "output_lvds_2501101010": 108, "output_lvds_25100000000001100011": 122, "output_lvds_25100100000000011110": 137, "output_lvds_25_dci01000000": 108, "output_lvdsext_25110000000001000101": 122, "output_lvdsext_25110100000000011110": 137, "output_lvdsext_2511100010": 108, "output_lvdsext_25_dci11000000": 108, "output_misc": [57, 79, 93, 108, 122, 137], "output_misciob0": 57, "output_misciob1": [57, 93], "output_misciob2": 57, "output_misciob3": 57, "output_misciob4": [57, 93], "output_rsds_2501101010": 108, "output_rsds_25100000000001100011": 122, "output_rsds_25100100000000011110": 137, "output_ulvds_2501100110": 108, "outputs_act": 149, "outr_clkout0": 61, "outr_clkout1": 61, "outr_locked0": 61, "outr_locked1": 61, "outsel0": 97, "outsel1": 97, "outsel2": 97, "outsid": [35, 91], "outu_clkout0": 61, "outu_clkout1": 61, "outu_lock": 61, "over": [15, 16, 35, 46, 81, 82, 132, 142], "over_temperatur": 109, "over_temperature_delai": 109, "over_temperature_off": 109, "overlap": [35, 37, 46], "overrid": [17, 35, 164], "overriden": [17, 35, 164, 165], "oversample_mod": [118, 119], "overtemp_powerdown": [114, 129], "overview": [11, 33, 162], "own": [17, 36, 91, 145, 165], "p": [15, 16, 36, 81, 142, 145, 153, 165], "p0": 96, "p0cmdclk": 69, "p0cmden": 69, "p0rdclk": 69, "p0rden": 69, "p0wrclk": 69, "p0wren": 69, "p1": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 155, 156, 157, 158, 159, 160], "p10": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p100": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p101": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p102": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p103": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p104": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p105": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p106": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p107": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p108": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p109": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p11": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p110": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p111": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p112": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p113": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p114": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p115": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p116": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p117": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], 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160], "p132": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p133": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p134": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p135": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p136": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p137": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p138": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p139": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p14": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p140": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p141": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p142": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], "p143": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 157, 158, 159, 160], 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160], "p159": [3, 6, 7, 18, 19, 22, 23, 24, 25, 158, 159, 160], "p16": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p160": [3, 6, 7, 18, 19, 22, 23, 24, 25, 158, 159, 160], "p161": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p162": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p163": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p164": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p165": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p166": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p167": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p168": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p169": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p17": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p170": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p171": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p172": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p173": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p174": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p175": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p176": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p177": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p178": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p179": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p18": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p180": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p181": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p182": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p183": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p184": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p185": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p186": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p187": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p188": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p189": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p19": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p190": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p191": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p192": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p193": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p194": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p195": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p196": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p197": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p198": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p199": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p1cmdclk": 69, "p1cmden": 69, "p1rdclk": 69, "p1rden": 69, "p1wrclk": 69, "p1wren": 69, "p2": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 155, 156, 157, 158, 159, 160], "p20": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p200": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p201": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p202": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p203": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p204": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p205": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p206": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p207": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p208": [3, 6, 7, 22, 23, 24, 25, 158, 159, 160], "p209": [3, 6, 7], "p21": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p210": [3, 6, 7], "p211": [3, 6, 7], "p212": [3, 6, 7], "p213": [3, 6, 7], "p214": [3, 6, 7], "p215": [3, 6, 7], "p216": [3, 6, 7], "p217": [3, 6, 7], "p218": [3, 6, 7], "p219": [3, 6, 7], "p22": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p220": [3, 6, 7], "p221": [3, 6, 7], "p222": [3, 6, 7], "p223": [6, 7], "p224": [6, 7], "p225": [6, 7], "p226": [6, 7], "p227": [6, 7], "p228": [6, 7], "p229": [6, 7], "p23": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p230": [6, 7], "p231": [6, 7], "p232": [6, 7], "p233": [6, 7], "p234": [6, 7], "p235": [6, 7], "p236": [6, 7], "p237": [6, 7], "p238": [6, 7], "p239": [6, 7], "p24": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p240": [6, 7], "p241": [6, 7], "p242": [6, 7], "p243": [6, 7], "p244": [6, 7], "p245": [6, 7], "p246": [6, 7], "p247": [6, 7], "p248": [6, 7], "p249": [6, 7], "p25": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p250": [6, 7], "p251": [6, 7], "p252": [6, 7], "p253": [6, 7], "p254": [6, 7], "p255": [6, 7], "p256": [6, 7], "p257": [6, 7], "p258": [6, 7], "p259": [6, 7], "p26": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p260": [6, 7], "p261": [6, 7], "p262": [6, 7], "p263": [6, 7], "p264": [6, 7], "p265": [6, 7], "p266": [6, 7], "p267": [6, 7], "p268": [6, 7], "p269": [6, 7], "p27": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p270": [6, 7], "p271": [6, 7], "p272": [6, 7], "p273": [6, 7], "p274": [6, 7], "p275": [6, 7], "p276": [6, 7], "p277": [6, 7], "p278": [6, 7], "p279": [6, 7], "p28": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p280": [6, 7], "p281": [6, 7], "p282": [6, 7], "p283": [6, 7], "p284": [6, 7], "p285": [6, 7], "p286": [6, 7], "p287": [6, 7], "p288": [6, 7], "p289": 7, "p29": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p290": 7, "p291": 7, "p292": 7, "p293": 7, "p294": 7, "p295": 7, "p296": 7, "p297": 7, "p298": 7, "p299": 7, "p2clk": 69, "p2cmdclk": 69, "p2cmden": 69, "p2en": 69, "p3": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 155, 156, 157, 158, 159, 160], "p30": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p300": 7, "p301": 7, "p302": 7, "p303": 7, "p304": 7, "p305": 7, "p306": 7, "p307": 7, "p308": 7, "p309": 7, "p31": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p310": 7, "p311": 7, "p312": 7, "p313": 7, "p314": 7, "p315": 7, "p316": 7, "p317": 7, "p318": 7, "p319": 7, "p32": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p3clk": 69, "p3cmdclk": 69, "p3cmden": 69, "p3en": 69, "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p4clk": 69, "p4cmdclk": 69, "p4cmden": 69, "p4en": 69, "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p5clk": 69, "p5cmdclk": 69, "p5cmden": 69, "p5en": 69, "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 156, 157, 158, 159, 160], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 156, 157, 158, 159, 160], "p_d": 81, "packag": [11, 17, 33, 36, 56, 142, 145, 154, 162, 164], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 122, 137, 145, 154, 163, 165], "pair": [17, 58, 82, 96, 104, 108, 122, 137, 142, 145, 154], "parallel": [16, 108, 122, 137, 145], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 154, 155, 156, 157, 158, 159, 160], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 122, 142, 155, 156, 157, 158, 159, 160, 162, 164], "partial": [34, 81, 96, 164], "particip": 36, "particular": [17, 154], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 132, 142, 148, 149, 151, 152], "pass0": [64, 71], "pass00000000": 102, "pass00000000001": 113, "pass00000001": 113, "pass00000001000000": 113, "pass00001000": 113, "pass10000000000000": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 115, "path": [36, 81], "pattern": [87, 115, 130, 141], "pattern0": [115, 130, 141], "pbbaseptr": 123, "pbcapabilitydw0basepow": 123, "pbcapabilitydw0datascal": 123, "pbcapabilitydw0pmst": 123, "pbcapabilitydw0pmsubst": 123, "pbcapabilitydw0powerrail": 123, "pbcapabilitydw0typ": 123, "pbcapabilitydw1basepow": 123, "pbcapabilitydw1datascal": 123, "pbcapabilitydw1pmst": 123, "pbcapabilitydw1pmsubst": 123, "pbcapabilitydw1powerrail": 123, "pbcapabilitydw1typ": 123, "pbcapabilitydw2basepow": 123, "pbcapabilitydw2datascal": 123, "pbcapabilitydw2pmst": 123, "pbcapabilitydw2pmsubst": 123, "pbcapabilitydw2powerrail": 123, "pbcapabilitydw2typ": 123, "pbcapabilitydw3basepow": 123, "pbcapabilitydw3datascal": 123, "pbcapabilitydw3pmst": 123, "pbcapabilitydw3pmsubst": 123, "pbcapabilitydw3powerrail": 123, "pbcapabilitydw3typ": 123, "pbcapabilitynextptr": 123, "pbcapabilitysystemalloc": 123, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 155, 156, 163], "pc84": [18, 29, 34], "pci": [44, 56, 58, 67, 78, 90, 91, 92, 120, 135, 143], "pci000": 91, "pci100": 91, "pci33_3": [57, 79], "pci33_30": [57, 93], "pci33_300": [57, 93], "pci33_30000": 93, "pci33_300000": [57, 93], "pci33_3000000": 122, "pci33_3000000000000": 122, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 122, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 122, "pci66_3000000000000": 122, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 122, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, "pci_clampiob0": 57, "pci_clampiob1": 57, "pci_clampiob3": 57, "pci_clampiob4": 57, "pci_delai": 80, "pci_express_mod": 134, "pci_express_mode_0": [66, 118, 119], "pci_express_mode_1": [66, 118, 119], "pci_express_mode_1gtp": 66, "pci_input": 57, "pci_inputiob1": 57, "pci_inputiob2": 57, "pci_inputiob3": 57, "pci_inputiob4": 57, "pci_inputiob5": 57, "pcice10": 57, "pcice_mux": 57, "pcie": [70, 117, 123, 132, 138, 142, 146], "pcie0": [66, 118, 119], "pcie2": 142, "pcie3": [142, 147], "pcie_base_ptr": [138, 146], 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"pcomma_10b_value_0": [66, 118, 119], "pcomma_10b_value_1": [66, 118, 119], "pcomma_detect": [88, 89, 105, 134], "pcomma_detect_0": [66, 118, 119], "pcomma_detect_1": [66, 118, 119], "pcomma_detect_1gtp": 66, "pcomma_detectgtx0": 134, "pcomma_detectgtx1": 134, "pcomma_detectgtx2": 134, "pcomma_detectgtx3": 134, "pcomma_valu": 105, "pcs0": [66, 118, 119], "pcs10": 134, "pcs_ability_lane0": 133, "pcs_ability_lane1": 133, "pcs_ability_lane2": 133, "pcs_ability_lane3": 133, "pcs_bit_slip": 105, "pcs_com_cfg": 118, "pcs_ctrl1_lane0": 133, "pcs_ctrl1_lane1": 133, "pcs_ctrl1_lane2": 133, "pcs_ctrl1_lane3": 133, "pcs_ctrl2_lane0": 133, "pcs_ctrl2_lane1": 133, "pcs_ctrl2_lane2": 133, "pcs_ctrl2_lane3": 133, "pcs_misc_cfg_0_lane0": 133, "pcs_misc_cfg_0_lane1": 133, "pcs_misc_cfg_0_lane2": 133, "pcs_misc_cfg_0_lane3": 133, "pcs_misc_cfg_1_lane0": 133, "pcs_misc_cfg_1_lane1": 133, "pcs_misc_cfg_1_lane2": 133, "pcs_misc_cfg_1_lane3": 133, "pcs_mode_lane0": 133, "pcs_mode_lane1": 133, "pcs_mode_lane2": 133, "pcs_mode_lane3": 133, "pcs_reset_1_lane0": 133, "pcs_reset_1_lane1": 133, "pcs_reset_1_lane2": 133, "pcs_reset_1_lane3": 133, "pcs_reset_lane0": 133, "pcs_reset_lane1": 133, "pcs_reset_lane2": 133, "pcs_reset_lane3": 133, "pcs_type_lane0": 133, "pcs_type_lane1": 133, "pcs_type_lane2": 133, "pcs_type_lane3": 133, "pdelidle_drp_en": 134, "pdelidle_drp_en_0": 66, "pdelidle_drp_en_1": 66, "pdelidle_drp_en_1gtp": 66, "pdrive": [57, 79, 93, 108, 122, 137], "pdriveiostd": [57, 79, 93, 108, 122, 137], "pdstatuspin": 76, "pdstatuspinmisc": 76, "pent": 121, "pent00010100": 121, "pent00011000": 121, "pent00100100": 121, "pent00101000": 121, "pent01000100": 121, "pent01001000": 121, "pent10000100": 121, "pent10001000": 121, "per": [12, 14, 17, 33, 34, 35, 36, 46, 55, 56, 58, 81, 91, 92, 96, 104, 108, 117, 122, 132, 137, 142, 145, 153, 154, 164, 165], "perf0001": 134, "perf1011": 134, "perf2101": 134, "perf3111": 134, "perfclk": 134, "perfclk1": 134, "perform": [35, 36, 145, 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"pf0_dpa_cap_sub_state_power_allocation0": 147, "pf0_dpa_cap_sub_state_power_allocation1": 147, "pf0_dpa_cap_sub_state_power_allocation2": 147, "pf0_dpa_cap_sub_state_power_allocation3": 147, "pf0_dpa_cap_sub_state_power_allocation4": 147, "pf0_dpa_cap_sub_state_power_allocation5": 147, "pf0_dpa_cap_sub_state_power_allocation6": 147, "pf0_dpa_cap_sub_state_power_allocation7": 147, "pf0_dpa_cap_v": 147, "pf0_dsn_cap_nextptr": 147, "pf0_expansion_rom_aperture_s": 147, "pf0_interrupt_lin": 147, "pf0_interrupt_pin": 147, "pf0_ltr_cap_max_nosnoop_lat": 147, "pf0_ltr_cap_max_snoop_lat": 147, "pf0_ltr_cap_nextptr": 147, "pf0_ltr_cap_ver": 147, "pf0_msi_cap_nextptr": 147, "pf0_msix_cap_nextptr": 147, "pf0_msix_cap_pba_offset": 147, "pf0_msix_cap_table_offset": 147, "pf0_msix_cap_table_s": 147, "pf0_pb_cap_nextptr": 147, "pf0_pb_cap_ver": 147, "pf0_pm_cap_id": 147, "pf0_pm_cap_nextptr": 147, "pf0_pm_cap_ver_id": 147, "pf0_rbar_cap_index0": 147, "pf0_rbar_cap_index1": 147, "pf0_rbar_cap_index2": 147, "pf0_rbar_cap_nextptr": 147, "pf0_rbar_cap_size0": 147, "pf0_rbar_cap_size1": 147, "pf0_rbar_cap_size2": 147, "pf0_rbar_cap_v": 147, "pf0_rbar_num": 147, "pf0_revision_id": 147, "pf0_sriov_bar0_aperture_s": 147, "pf0_sriov_bar0_control": 147, "pf0_sriov_bar1_aperture_s": 147, "pf0_sriov_bar1_control": 147, "pf0_sriov_bar2_aperture_s": 147, "pf0_sriov_bar2_control": 147, "pf0_sriov_bar3_aperture_s": 147, "pf0_sriov_bar3_control": 147, "pf0_sriov_bar4_aperture_s": 147, "pf0_sriov_bar4_control": 147, "pf0_sriov_bar5_aperture_s": 147, "pf0_sriov_bar5_control": 147, "pf0_sriov_cap_initial_vf": 147, "pf0_sriov_cap_nextptr": 147, "pf0_sriov_cap_total_vf": 147, "pf0_sriov_cap_v": 147, "pf0_sriov_first_vf_offset": 147, "pf0_sriov_func_dep_link": 147, "pf0_sriov_supported_page_s": 147, "pf0_sriov_vf_device_id": 147, "pf0_subsystem_id": 147, "pf0_tphr_cap_nextptr": 147, "pf0_tphr_cap_st_mode_sel": 147, "pf0_tphr_cap_st_table_loc": 147, "pf0_tphr_cap_st_table_s": 147, "pf0_tphr_cap_ver": 147, "pf0_vc_cap_nextptr": 147, "pf0_vc_cap_ver": 147, "pf1_aer_cap_nextptr": 147, "pf1_ari_cap_next_func": 147, "pf1_ari_cap_nextptr": 147, "pf1_bar0_aperture_s": 147, "pf1_bar0_control": 147, "pf1_bar1_aperture_s": 147, "pf1_bar1_control": 147, "pf1_bar2_aperture_s": 147, "pf1_bar2_control": 147, "pf1_bar3_aperture_s": 147, "pf1_bar3_control": 147, "pf1_bar4_aperture_s": 147, "pf1_bar4_control": 147, "pf1_bar5_aperture_s": 147, "pf1_bar5_control": 147, "pf1_bist_regist": 147, "pf1_capability_point": 147, "pf1_class_cod": 147, "pf1_dev_cap_max_payload_s": 147, "pf1_device_id": 147, "pf1_dpa_cap_nextptr": 147, "pf1_dpa_cap_sub_state_control": 147, "pf1_dpa_cap_sub_state_power_allocation0": 147, "pf1_dpa_cap_sub_state_power_allocation1": 147, "pf1_dpa_cap_sub_state_power_allocation2": 147, "pf1_dpa_cap_sub_state_power_allocation3": 147, "pf1_dpa_cap_sub_state_power_allocation4": 147, "pf1_dpa_cap_sub_state_power_allocation5": 147, "pf1_dpa_cap_sub_state_power_allocation6": 147, "pf1_dpa_cap_sub_state_power_allocation7": 147, "pf1_dpa_cap_v": 147, "pf1_dsn_cap_nextptr": 147, "pf1_expansion_rom_aperture_s": 147, "pf1_interrupt_lin": 147, "pf1_interrupt_pin": 147, "pf1_msi_cap_nextptr": 147, "pf1_msix_cap_nextptr": 147, "pf1_msix_cap_pba_offset": 147, "pf1_msix_cap_table_offset": 147, "pf1_msix_cap_table_s": 147, "pf1_pb_cap_nextptr": 147, "pf1_pb_cap_ver": 147, "pf1_pm_cap_id": 147, "pf1_pm_cap_nextptr": 147, "pf1_pm_cap_ver_id": 147, "pf1_rbar_cap_index0": 147, "pf1_rbar_cap_index1": 147, "pf1_rbar_cap_index2": 147, "pf1_rbar_cap_nextptr": 147, "pf1_rbar_cap_size0": 147, "pf1_rbar_cap_size1": 147, "pf1_rbar_cap_size2": 147, "pf1_rbar_cap_v": 147, "pf1_rbar_num": 147, "pf1_revision_id": 147, "pf1_sriov_bar0_aperture_s": 147, "pf1_sriov_bar0_control": 147, "pf1_sriov_bar1_aperture_s": 147, "pf1_sriov_bar1_control": 147, "pf1_sriov_bar2_aperture_s": 147, "pf1_sriov_bar2_control": 147, "pf1_sriov_bar3_aperture_s": 147, "pf1_sriov_bar3_control": 147, "pf1_sriov_bar4_aperture_s": 147, "pf1_sriov_bar4_control": 147, "pf1_sriov_bar5_aperture_s": 147, "pf1_sriov_bar5_control": 147, "pf1_sriov_cap_initial_vf": 147, "pf1_sriov_cap_nextptr": 147, "pf1_sriov_cap_total_vf": 147, "pf1_sriov_cap_v": 147, "pf1_sriov_first_vf_offset": 147, "pf1_sriov_func_dep_link": 147, "pf1_sriov_supported_page_s": 147, "pf1_sriov_vf_device_id": 147, "pf1_subsystem_id": 147, "pf1_tphr_cap_nextptr": 147, "pf1_tphr_cap_st_mode_sel": 147, "pf1_tphr_cap_st_table_loc": 147, "pf1_tphr_cap_st_table_s": 147, "pf1_tphr_cap_ver": 147, "pgate011": 50, "pgate0111": 50, "pgl0_lane": 138, "pgl1_lane": 138, "pgl2_lane": 138, "pgl3_lane": 138, "pgl4_lane": 138, "pgl5_lane": 138, "pgl6_lane": 138, "pgl7_lane": 138, "phase": [44, 67], "phase_freq_lock00": 102, "phase_shift": [51, 52, 64, 86, 102], "phase_shift_neg": [51, 52, 64, 86, 102], "phase_shift_negativedcm": [51, 102], "phasealign_drp_en": 134, "phasealign_drp_en_0": 66, "phasealign_drp_en_1": 66, "phasealign_drp_en_1gtp": 66, "phi": 35, "philip": [163, 164], "phyemac0gtxclk": 116, "phyemac0mclkin": 116, "phyemac0miitxclk": 116, "phyemac0rxclk": 116, "phyemac0txgmiimiiclkin": 116, "phyemac1gtxclk": 116, "phyemac1mclkin": 116, "phyemac1miitxclk": 116, "phyemac1rxclk": 116, "phyemac1txgmiimiiclkin": 116, "physic": [55, 153], "pick": [46, 82, 96], "picosecond": [17, 154], "pin": [10, 11, 14, 17, 32, 33, 36, 46, 63, 81, 82, 91, 96, 108, 122, 137, 145, 154, 161, 162, 164, 165], "pipe1": 134, "pipelin": [56, 81, 96], "pitch": [12, 34, 163], "pl_auto_config": [138, 146], "pl_center": [51, 86], "pl_eq_adapt_iter_count": 147, "pl_eq_adapt_reject_retry_count": 147, "pl_fast_train": [138, 146], "pl_fast_trainpci": [138, 146], "pl_lane0_eq_control": 147, "pl_lane1_eq_control": 147, "pl_lane2_eq_control": 147, "pl_lane3_eq_control": 147, "pl_lane4_eq_control": 147, "pl_lane5_eq_control": 147, "pl_lane6_eq_control": 147, "pl_lane7_eq_control": 147, "pl_link_cap_max_link_spe": 147, "pl_link_cap_max_link_width": 147, "pl_n_fts_comclk_gen1": 147, "pl_n_fts_comclk_gen2": 147, "pl_n_fts_comclk_gen3": 147, "pl_n_fts_gen1": 147, "pl_n_fts_gen2": 147, "pl_n_fts_gen3": 147, "pla": [153, 165], "place": [12, 35, 36, 55, 58, 91, 104, 145], "placement": 58, "plain": [12, 17, 34, 58, 87, 92, 96, 142, 154, 163], "plain0": [4, 5, 8, 9], "plain00": [2, 3, 6, 7], "plane": [81, 96, 153, 154], "plastic": [12, 34, 163], "platic": 34, "plb_test": 124, "plcc": [12, 34, 163], "pll": 71, "pll00": 66, "pll0_clkout0": 61, "pll0_clkout0_d": 61, "pll0_clkout0_u": 61, "pll0_clkout1": 61, "pll0_clkout1_d": 61, "pll0_clkout1_u": 61, "pll0d_clkout000": 61, "pll0d_clkout0111": 61, "pll0d_clkout101": 61, "pll0d_clkout1110": 61, "pll0d_locked00": 61, "pll0d_locked1": 61, "pll0u_clkout0000": 61, "pll0u_clkout001": 61, "pll0u_clkout100": 61, "pll0u_clkout1001": 61, "pll0u_locked1": 61, "pll0u_locked11": 61, "pll11": 66, "pll1_clkout0": 61, "pll1_clkout0_d": 61, "pll1_clkout0_u": 61, "pll1_clkout1": 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"pll_clkout4_pm": 71, "pll_clkout5100001": 71, "pll_clkout5_dt": 71, "pll_clkout5_edg": 71, "pll_clkout5_en": 71, "pll_clkout5_ht": 71, "pll_clkout5_lt": 71, "pll_clkout5_nocount": 71, "pll_clkout5_pm": 71, "pll_com_cfg": 119, "pll_com_cfg_0": 66, "pll_com_cfg_1": 66, "pll_cp": 71, "pll_cp_bias_trip_shift": 71, "pll_cp_cfg": 119, "pll_cp_cfg_0": 66, "pll_cp_cfg_1": 66, "pll_cp_re": 71, "pll_cp_repl": 71, "pll_cp_replpll": 71, "pll_cppll": 71, "pll_direct_path_cntrl": 71, "pll_divclk_edg": 71, "pll_divclk_en": 71, "pll_divclk_ht": 71, "pll_divclk_lt": 71, "pll_divclk_nocount": 71, "pll_divsel_fb": [118, 119], "pll_divsel_fb_0": 66, "pll_divsel_fb_1": 66, "pll_divsel_ref": [118, 119], "pll_divsel_ref_0": 66, "pll_divsel_ref_1": 66, "pll_drp_en": 134, "pll_drp_en_0": 66, "pll_drp_en_1": 66, "pll_drp_en_1gtp": 66, "pll_dvdd_comp_set": 71, "pll_en": 71, "pll_en_cntrl": 71, "pll_en_dli": 71, "pll_en_leakag": 71, "pll_en_tclk0": 71, "pll_en_tclk1": 71, "pll_en_tclk2": 71, "pll_en_tclk3": 71, "pll_en_vco0": 71, "pll_en_vco1": 71, "pll_en_vco2": 71, "pll_en_vco3": 71, "pll_en_vco4": 71, "pll_en_vco5": 71, "pll_en_vco6": 71, "pll_en_vco7": 71, "pll_en_vco_div1": 71, "pll_en_vco_div6": 71, "pll_fb_dccen": 119, "pll_fb_dccengtx_dual": 119, "pll_in_dly_mx_sel": 71, "pll_in_dly_set": 71, "pll_intfb": 71, "pll_lfhf": 71, "pll_lkdet_cfg": 119, "pll_lock_cnt": 71, "pll_lock_cntpll": 71, "pll_lock_fb_dli": 71, "pll_lock_fb_dlypl": 71, "pll_lock_ref_dli": 71, "pll_lock_ref_dlypl": 71, "pll_lock_sat_high": 71, "pll_lock_sat_highpl": 71, "pll_man_lf_en": 71, "pll_nbti_en": 71, "pll_pfd_cntrl": 71, "pll_pfd_dly": 71, "pll_pwrd_cfg": 71, "pll_re": 71, "pll_reg_input": 71, "pll_respll": 71, "pll_rxdivsel_out_0": [66, 118, 119], "pll_rxdivsel_out_1": [66, 118, 119], "pll_sata_0": [66, 118, 119], "pll_sata_0gtp": 66, "pll_sata_0gtp_du": 118, "pll_sata_0gtx_du": 119, "pll_sata_1": [66, 118, 119], "pll_sata_1gtp": 66, "pll_sata_1gtp_du": 118, "pll_sata_1gtx_du": 119, "pll_sel_slipd": 71, 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interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "FPGAcore", "General interconnect", "Input / Output", "Xilinx FPGAs", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers \u2014 Spartan 3, Spartan 3E", "Configuration registers \u2014 Spartan 3A and 3A DSP", "Corners", "Digital Clock Managers \u2014 Spartan 3", "Digital Clock Managers \u2014 Spartan 3E, 3A", "DSP", "Spartan 3", "General interconnect", "Introduction", "Input / Output", "Device geometry", "Block RAM", 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XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[112, "bitstream-clbll"], [127, "bitstream-clbll"], [140, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[112, "bitstream-clblm"], [127, "bitstream-clblm"], [140, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[60, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[60, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[61, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[61, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[61, "bitstream-hclk"]], "Bitstream \u2014 HCLK_IOI": [[137, "bitstream-hclk-ioi"]], "Bitstream \u2014 HCLK_ROW": [[61, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[121, "bitstream-intf"], [136, "bitstream-intf"], [146, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[146, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[121, "bitstream-intf-delay"], [136, "bitstream-intf-delay"], [146, "bitstream-intf-delay"]], "Bitstream \u2014 IO": [[137, "bitstream-io"]], "Bitstream \u2014 IOI tile": [[68, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[55, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[55, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[61, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[61, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[61, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[61, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[61, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PowerPC hole tiles": [[91, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[61, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[38, "bitstream-bottom-tiles"], [47, "bitstream-bottom-tiles"], [83, "bitstream-bottom-tiles"]], "Bitstream \u2014 column bottom": [[72, "bitstream-column-bottom"]], "Bitstream \u2014 column top": [[72, "bitstream-column-top"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [55, "bitstream-interconnect-tiles"], [91, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[107, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[55, "bitstream-interface-tiles"], [68, "bitstream-interface-tiles"], [91, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[72, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[61, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[47, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[72, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[68, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[72, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[61, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[47, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[91, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[61, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[38, "bitstream-top-tiles"], [47, "bitstream-top-tiles"], [83, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[45, "block-ram"], [59, "block-ram"], [72, "block-ram"], [96, "block-ram"], [110, "block-ram"], [125, "block-ram"], [139, "block-ram"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[81, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [156, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [166, "boundary-scan-register"]], "CCLK_FREQ": [[49, "cclk-freq"], [62, "cclk-freq"]], "CLKB": [[74, "clkb"], [154, "clkb"]], "CLKB.FC": [[38, "clkb-fc"]], "CLKB.S3": [[47, "clkb-s3"]], "CLKB.S3A": [[47, "clkb-s3a"]], "CLKB.S3E": [[47, "clkb-s3e"]], "CLKB.V2": [[83, "clkb-v2"]], "CLKB.V2P": [[83, "clkb-v2p"]], "CLKB.V2PX": [[83, "clkb-v2px"]], "CLKB_2DLL": [[74, "clkb-2dll"]], "CLKB_4DLL": [[74, "clkb-4dll"]], "CLKH": [[154, "clkh"]], "CLKL": [[80, "clkl"], [154, "clkl"]], "CLKL.S3A": [[47, "clkl-s3a"]], "CLKL.S3E": [[47, "clkl-s3e"]], "CLKR": [[80, "clkr"], [154, "clkr"]], "CLKR.S3A": [[47, "clkr-s3a"]], "CLKR.S3E": [[47, "clkr-s3e"]], "CLKT": [[74, "clkt"], [154, "clkt"]], "CLKT.FC": [[38, "clkt-fc"]], "CLKT.S3": [[47, "clkt-s3"]], "CLKT.S3A": [[47, "clkt-s3a"]], "CLKT.S3E": [[47, "clkt-s3e"]], "CLKT.V2": [[83, "clkt-v2"]], "CLKT.V2P": [[83, "clkt-v2p"]], "CLKT.V2PX": [[83, "clkt-v2px"]], "CLKT_2DLL": [[74, "clkt-2dll"]], "CLKT_4DLL": [[74, "clkt-4dll"]], "CLKV": [[154, "clkv"]], "CLKV.CLKV": [[74, "clkv-clkv"]], "CLKV.GCLKV": [[74, "clkv-gclkv"]], "CLKV_BRAM_BOT": [[74, "clkv-bram-bot"]], "CLKV_BRAM_TOP": [[74, "clkv-bram-top"]], "CLK_BALI_REBUF": [[141, "clk-bali-rebuf"]], "CLK_BUFG": [[141, "clk-bufg"]], "CLK_BUFG_REBUF": [[141, "clk-bufg-rebuf"]], "CLK_CMT_B": [[113, "clk-cmt-b"]], "CLK_CMT_T": [[113, "clk-cmt-t"]], "CLK_DCM_B": [[100, "clk-dcm-b"]], "CLK_DCM_T": [[100, "clk-dcm-t"]], "CLK_HROW": [[100, "clk-hrow"], [113, "clk-hrow"], [141, "clk-hrow"]], "CLK_IOB_B": [[100, "clk-iob-b"], [113, "clk-iob-b"]], "CLK_IOB_T": [[100, "clk-iob-t"], [113, "clk-iob-t"]], "CLK_MGT_B": [[113, "clk-mgt-b"]], "CLK_MGT_T": [[113, "clk-mgt-t"]], "CLK_TERM_B": [[100, "clk-term-b"]], "CLK_TERM_T": [[100, "clk-term-t"]], "CMT": [[142, "cmt"]], "CMT_BUFG_BOT": [[128, "cmt-bufg-bot"]], "CMT_BUFG_TOP": [[128, "cmt-bufg-top"]], "CMT_FIFO": [[142, "cmt-fifo"]], "CNR.BL": [[76, "cnr-bl"], [151, "cnr-bl"]], "CNR.BR": [[76, "cnr-br"], [151, "cnr-br"]], "CNR.TL": [[76, "cnr-tl"], [151, "cnr-tl"]], "CNR.TR": [[76, "cnr-tr"], [151, "cnr-tr"]], "COR": [[75, "cor"], [84, "cor"], [101, "cor"], [114, "cor"], [129, "cor"]], "COR.FC": [[39, "cor-fc"]], "COR.S3": [[48, "cor-s3"]], "COR.S3E": [[48, "cor-s3e"]], "COR1": [[62, "cor1"], [114, "cor1"], [129, "cor1"]], "COR1.S3A": [[49, "cor1-s3a"]], "COR2": [[62, "cor2"]], "COR2.S3A": [[49, "cor2-s3a"]], "CTL": [[62, "ctl"], [75, "ctl"], [84, "ctl"], [101, "ctl"], [114, "ctl"], [129, "ctl"]], "CTL.S3": [[39, "ctl-s3"], [48, "ctl-s3"]], "CTL.S3A": [[49, "ctl-s3a"]], "CTL1": [[129, "ctl1"]], "Carry logic": [[46, "carry-logic"], [82, "carry-logic"]], "Center column": [[104, "center-column"], [117, "center-column"], [132, "center-column"]], "Center column and configuration center": [[144, "center-column-and-configuration-center"]], "Clock Companion Modules": [[97, "clock-companion-modules"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[38, "clock-interconnect"], [47, "clock-interconnect"], [61, "clock-interconnect"], [74, "clock-interconnect"], [83, "clock-interconnect"], [100, "clock-interconnect"], [113, "clock-interconnect"], [128, "clock-interconnect"], [141, "clock-interconnect"]], "Clock management tile": [[142, "clock-management-tile"]], "Clock rows": [[58, "clock-rows"], [87, "clock-rows"]], "Clock source \u2014 left and right": [[47, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[38, "clock-source-spine-bottom-and-top"], [47, "clock-source-spine-bottom-and-top"], [83, "clock-source-spine-bottom-and-top"]], "Clock spine": [[87, "clock-spine"]], "Clock spine top and bottom": [[91, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[37, "configurable-logic-block"], [46, "configurable-logic-block"], [60, "configurable-logic-block"], [73, "configurable-logic-block"], [82, "configurable-logic-block"], [99, "configurable-logic-block"], [112, "configurable-logic-block"], [127, "configurable-logic-block"], [140, "configurable-logic-block"], [150, "configurable-logic-block"]], "Configuration Center": [[98, "configuration-center"], [111, "configuration-center"], [126, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[39, "configuration-registers"], [62, "configuration-registers"], [75, "configuration-registers"], [84, "configuration-registers"], [101, "configuration-registers"], [114, "configuration-registers"], [129, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[48, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[49, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [41, null], [44, null], [54, null], [67, null], [78, null], [90, null], [106, null], [120, null], [135, null], [145, null], [152, null], [163, null], [164, null]], "Corners": [[40, "corners"], [50, "corners"], [63, "corners"], [76, "corners"], [85, "corners"], [151, "corners"]], "DCM output bus": [[83, "dcm-output-bus"]], "DCM.S3": [[51, "dcm-s3"]], "DCM.S3E.BL": [[52, "dcm-s3e-bl"]], "DCM.S3E.BR": [[52, "dcm-s3e-br"]], "DCM.S3E.LB": [[52, "dcm-s3e-lb"]], "DCM.S3E.LT": [[52, "dcm-s3e-lt"]], "DCM.S3E.RB": [[52, "dcm-s3e-rb"]], "DCM.S3E.RT": [[52, "dcm-s3e-rt"]], "DCM.S3E.TL": [[52, "dcm-s3e-tl"]], "DCM.S3E.TR": [[52, "dcm-s3e-tr"]], "DCM.V2": [[86, "dcm-v2"]], "DCM.V2P": [[86, "dcm-v2p"]], "DCMCONN.BOT": [[83, "dcmconn-bot"]], "DCMCONN.TOP": [[83, "dcmconn-top"]], "DESKEW_ADJUST": [[51, "deskew-adjust"], [52, "deskew-adjust"], [86, "deskew-adjust"]], "DLL.BOT": [[77, "dll-bot"]], "DLL.TOP": [[77, "dll-top"]], "DLLP.BOT": [[77, "dllp-bot"]], "DLLP.TOP": [[77, "dllp-top"]], "DLLS.BOT": [[77, "dlls-bot"]], "DLLS.TOP": [[77, "dlls-top"]], "DSP": [[53, "dsp"], [65, "dsp"], [103, "dsp"], [115, "dsp"], [130, "dsp"], [143, "dsp"]], "Database schema": [[17, "database-schema"], [156, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [163, "database-devices"]], "Default option attributes": [[47, "default-option-attributes"]], "Default option values": [[45, "default-option-values"]], "Delay Locked Loop": [[77, "delay-locked-loop"]], "Device": [[17, "device"], [156, "device"]], "Device geometry": [[58, "device-geometry"], [87, "device-geometry"], [104, "device-geometry"], [117, "device-geometry"], [132, "device-geometry"], [144, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [165, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [167, "device-structure"]], "Device table": [[56, "device-table"], [92, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [165, "devices"]], "Digital Clock Managers": [[86, "digital-clock-managers"], [102, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[51, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[52, "digital-clock-managers-spartan-3e-3a"]], "Digital clock manager": [[64, "digital-clock-manager"]], "Dual-port 16\u00d7X RAM": [[46, "dual-port-16x-ram"], [82, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[82, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[82, "dual-port-641-ram"]], "ECC": [[104, "ecc"], [117, "ecc"], [132, "ecc"], [144, "ecc"]], "ECC mode": [[96, "ecc-mode"]], "EYE_MASK": [[62, "eye-mask"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[116, "ethernet-macs"], [131, "ethernet-macs"]], "FB columns and rows": [[167, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[167, "fclk-networks"]], "FIFO mode": [[96, "fifo-mode"]], "FPGAcore": [[41, "fpgacore"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[155, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[155, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[155, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [155, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[155, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[83, "gclkc"]], "GCLKC.B": [[83, "gclkc-b"]], "GCLKC.T": [[83, "gclkc-t"]], "GCLKH": [[38, "gclkh"], [47, "gclkh"], [83, "gclkh"]], "GCLKH.N": [[47, "gclkh-n"]], "GCLKH.S": [[47, "gclkh-s"]], "GCLKH.UNI": [[47, "gclkh-uni"]], "GCLKH.UNI.N": [[47, "gclkh-uni-n"]], "GCLKH.UNI.S": [[47, "gclkh-uni-s"]], "GCLKVM.S3": [[38, "gclkvm-s3"], [47, "gclkvm-s3"]], "GCLKVM.S3E": [[47, "gclkvm-s3e"]], "GENERAL5": [[62, "general5"]], "GENERAL[12]": [[49, "general-12"], [62, "general-12"]], "GENERAL[34]": [[62, "general-34"]], "GIGABIT.B": [[88, "gigabit-b"]], "GIGABIT.T": [[88, "gigabit-t"]], "GIGABIT10.B": [[89, "gigabit10-b"]], "GIGABIT10.T": [[89, "gigabit10-t"]], "GTH transceivers": [[133, "gth-transceivers"]], "GTP and GTX right column holes": [[144, "gtp-and-gtx-right-column-holes"]], "GTP transceivers": [[118, "gtp-transceivers"]], "GTX transceivers": [[119, "gtx-transceivers"], [134, "gtx-transceivers"]], "General Interconnect": [[107, "general-interconnect"]], "General interconnect": [[42, "general-interconnect"], [55, "general-interconnect"], [68, "general-interconnect"], [91, "general-interconnect"]], "General structure": [[58, "general-structure"], [87, "general-structure"], [104, "general-structure"], [117, "general-structure"], [132, "general-structure"], [144, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [157, "global-bits"], [158, "global-bits"], [159, "global-bits"], [160, "global-bits"], [161, "global-bits"], [162, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[100, "hclk"], [113, "hclk"], [128, "hclk"], [141, "hclk"]], "HCLK_CENTER": [[100, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[100, "hclk-center-above-cfg"]], "HCLK_CMT": [[113, "hclk-cmt"]], "HCLK_CMT_IOI": [[113, "hclk-cmt-ioi"]], "HCLK_DCM": [[100, "hclk-dcm"]], "HCLK_DCMIOB": [[100, "hclk-dcmiob"]], "HCLK_IOBDCM": [[100, "hclk-iobdcm"]], "HCLK_IOI": [[113, "hclk-ioi"]], "HCLK_IOIS_DCI": [[100, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[100, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[113, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[113, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[113, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[113, "hclk-ioi-topcen"]], "HCLK_MGT": [[100, "hclk-mgt"]], "HCLK_TERM_L": [[100, "hclk-term-l"]], "HCLK_TERM_R": [[100, "hclk-term-r"]], "HC_OPT": [[49, "hc-opt"], [62, "hc-opt"]], "Hard PCI logic": [[94, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[95, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[58, "horizontal-clock-spine"]], "I/O banks and special functions": [[108, "i-o-banks-and-special-functions"], [122, "i-o-banks-and-special-functions"], [137, "i-o-banks-and-special-functions"], [147, "i-o-banks-and-special-functions"]], "I/O buffer tiles": [[43, "i-o-buffer-tiles"]], "I/O buffers \u2014 Spartan 3": [[57, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[57, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[57, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex": [[79, "i-o-buffers-virtex"]], "I/O buffers \u2014 Virtex 2": [[93, "i-o-buffers-virtex-2"]], "I/O buffers \u2014 Virtex 2 Pro": [[93, "i-o-buffers-virtex-2-pro"]], "I/O buffers \u2014 Virtex E": [[79, "i-o-buffers-virtex-e"]], "I/O data \u2014 Spartan 3": [[50, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[50, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[50, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[85, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[85, "i-o-data-virtex-2-pro"]], "I/O interface": [[43, "i-o-interface"], [57, "i-o-interface"], [93, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [157, "i-o-pins"], [158, "i-o-pins"], [159, "i-o-pins"], [160, "i-o-pins"], [161, "i-o-pins"], [162, "i-o-pins"]], "I/O standard data": [[100, "i-o-standard-data"], [113, "i-o-standard-data"]], "IDCODE": [[35, "idcode"], [166, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [157, "imux-bits"], [158, "imux-bits"], [159, "imux-bits"], [160, "imux-bits"], [161, "imux-bits"], [162, "imux-bits"]], "INT.BRAM": [[91, "int-bram"]], "INT.BRAM.S3": [[55, "int-bram-s3"]], "INT.BRAM.S3A.03": [[55, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[55, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[55, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[55, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"], [91, "int-clb"]], "INT.CNR": [[91, "int-cnr"]], "INT.DCM": [[55, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[55, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[91, "int-dcm-v2"]], "INT.DCM.V2P": [[91, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[91, "int-gt-clkpad"]], "INT.IOI": [[91, "int-ioi"]], "INT.IOI.CLK_B": [[91, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[91, "int-ioi-clk-t"]], "INT.IOI.FC": [[42, "int-ioi-fc"]], "INT.IOI.S3": [[55, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[55, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[55, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[55, "int-ioi-s3e"]], "INT.PPC": [[91, "int-ppc"]], "INTF": [[68, "intf"]], "INTF.CMT": [[68, "intf-cmt"]], "INTF.CMT.IOI": [[68, "intf-cmt-ioi"]], "INTF.DSP": [[55, "intf-dsp"]], "INTF.GT.B0": [[91, "intf-gt-b0"]], "INTF.GT.B123": [[91, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[91, "intf-gt-bclkpad"]], "INTF.GT.T0": [[91, "intf-gt-t0"]], "INTF.GT.T123": [[91, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[91, "intf-gt-tclkpad"]], "INTF.IOI": [[68, "intf-ioi"]], "INTF.PPC": [[91, "intf-ppc"]], "IO and transceiver placement": [[144, "io-and-transceiver-placement"]], "IO banks and IO buffers": [[58, "io-banks-and-io-buffers"], [87, "io-banks-and-io-buffers"]], "IO clock nodes": [[100, "io-clock-nodes"], [113, "io-clock-nodes"]], "IO.B": [[79, "io-b"], [153, "io-b"]], "IO.L": [[79, "io-l"], [153, "io-l"]], "IO.R": [[79, "io-r"], [153, "io-r"]], "IO.T": [[79, "io-t"], [153, "io-t"]], "IOB.B.V": [[79, "iob-b-v"]], "IOB.B.VE": [[79, "iob-b-ve"]], "IOB.L.V": [[79, "iob-l-v"]], "IOB.L.VE": [[79, "iob-l-ve"]], "IOB.R.V": [[79, "iob-r-v"]], "IOB.R.VE": [[79, "iob-r-ve"]], "IOB.T.V": [[79, "iob-t-v"]], "IOB.T.VE": [[79, "iob-t-ve"]], "IOBS.FC.B": [[43, "iobs-fc-b"]], "IOBS.FC.L": [[43, "iobs-fc-l"]], "IOBS.FC.R": [[43, "iobs-fc-r"]], "IOBS.FC.T": [[43, "iobs-fc-t"]], "IOBS.S3.B2": [[57, "iobs-s3-b2"]], "IOBS.S3.L1": [[57, "iobs-s3-l1"]], "IOBS.S3.R1": [[57, "iobs-s3-r1"]], "IOBS.S3.T2": [[57, "iobs-s3-t2"]], "IOBS.S3A.B2": [[57, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[57, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[57, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[57, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[57, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[57, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[57, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[57, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[57, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[57, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[57, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[57, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[57, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[57, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[57, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[57, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[57, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[57, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[57, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[57, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[93, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[93, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[93, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[93, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[93, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[93, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[93, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[93, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[93, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[93, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[93, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[93, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[93, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[93, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[93, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[93, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[93, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[93, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[93, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[93, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[93, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[93, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[93, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[93, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[93, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[93, "iobs-v2p-t-r2-clk"]], "IOI": [[93, "ioi"]], "IOI.CLK_B": [[93, "ioi-clk-b"]], "IOI.CLK_T": [[93, "ioi-clk-t"]], "IOI.FC": [[43, "ioi-fc"]], "IOI.S3": [[57, "ioi-s3"]], "IOI.S3A.B": [[57, "ioi-s3a-b"]], "IOI.S3A.LR": [[57, "ioi-s3a-lr"]], "IOI.S3A.T": [[57, "ioi-s3a-t"]], "IOI.S3E": [[57, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [166, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [166, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[43, "input-output"], [57, "input-output"], [93, "input-output"]], "Input multiplexers": [[55, "input-multiplexers"], [91, "input-multiplexers"]], "Input/Output": [[79, "input-output"], [108, "input-output"], [122, "input-output"], [137, "input-output"], [147, "input-output"], [153, "input-output"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [167, "input-output-buffer"]], "Interconnect": [[121, "interconnect"], [136, "interconnect"], [146, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [56, "introduction"], [92, "introduction"], [165, "introduction"]], "JED bits": [[156, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [155, "jed-mapping"], [157, "jed-mapping"], [158, "jed-mapping"], [159, "jed-mapping"], [160, "jed-mapping"], [161, "jed-mapping"], [162, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[155, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[155, "jed-mapping-macrocells-without-iob"]], "JED structure": [[155, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [166, "jtag-interface"]], "LL.FC": [[40, "ll-fc"]], "LL.S3": [[50, "ll-s3"]], "LL.S3A": [[50, "ll-s3a"]], "LL.S3E": [[50, "ll-s3e"]], "LL.V2": [[85, "ll-v2"]], "LL.V2P": [[85, "ll-v2p"]], "LLH": [[55, "llh"]], "LLH.CLKB.S3A": [[55, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[55, "llh-clkt-s3a"]], "LLV.S3A": [[55, "llv-s3a"]], "LLV.S3E": [[55, "llv-s3e"]], "LR.FC": [[40, "lr-fc"]], "LR.S3": [[50, "lr-s3"]], "LR.S3A": [[50, "lr-s3a"]], "LR.S3E": [[50, "lr-s3e"]], "LR.V2": [[85, "lr-v2"]], "LR.V2P": [[85, "lr-v2p"]], "LUT RAM": [[46, "lut-ram"], [82, "lut-ram"]], "LUTs": [[46, "luts"], [82, "luts"]], "Local control terms": [[167, "local-control-terms"]], "Long line splitters": [[55, "long-line-splitters"]], "Lower left": [[40, "lower-left"], [50, "lower-left"], [63, "lower-left"], [85, "lower-left"]], "Lower right": [[40, "lower-right"], [50, "lower-right"], [63, "lower-right"], [85, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[100, "mgt-clock-repeater"], [113, "mgt-clock-repeater"]], "MODE": [[49, "mode"], [62, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [167, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Memory Controller Block": [[69, "memory-controller-block"]], "Middle GTP holes": [[144, "middle-gtp-holes"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [167, "misc-configuration"]], "Multi-gigabit transceivers": [[66, "multi-gigabit-transceivers"], [105, "multi-gigabit-transceivers"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[88, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[89, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[82, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[46, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[46, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [167, "overview"]], "PCI Express": [[70, "pci-express"]], "PCI Express Gen2 cores": [[148, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[149, "pci-express-gen3-cores"]], "PCI Express cores": [[123, "pci-express-cores"], [138, "pci-express-cores"]], "PCI Express holes": [[144, "pci-express-holes"]], "PCI Logic": [[80, "pci-logic"]], "PCI logic": [[87, "pci-logic"]], "PCIE_L": [[148, "pcie-l"]], "PCIE_R": [[148, "pcie-r"]], "PCI_CE_DELAY": [[61, "pci-ce-delay"]], "PMA_SPEED values": [[89, "pma-speed-values"]], "PMVIOB": [[128, "pmviob"]], "POWERDOWN": [[49, "powerdown"], [62, "powerdown"]], "PPC.E": [[91, "ppc-e"]], "PPC.N": [[91, "ppc-n"]], "PPC.S": [[91, "ppc-s"]], "PPC.W": [[91, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[49, "pu-gts"], [62, "pu-gts"]], "PU_GWE": [[49, "pu-gwe"], [62, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [165, "packages"]], "Part": [[17, "part"], [156, "part"]], "Phase-locked loop": [[71, "phase-locked-loop"]], "PowerPC cores": [[124, "powerpc-cores"]], "PowerPC holes": [[87, "powerpc-holes"], [91, "powerpc-holes"], [104, "powerpc-holes"], [117, "powerpc-holes"]], "Primary vertical clock spine": [[58, "primary-vertical-clock-spine"]], "Primitive outputs": [[55, "primitive-outputs"], [91, "primitive-outputs"]], "Processing system": [[144, "processing-system"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [167, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [166, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[37, "randor"], [46, "randor"]], "RANDOR_INIT": [[37, "randor-init"], [46, "randor-init"]], "RESERVED_ANDOR": [[37, "reserved-andor"], [46, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [167, "register"]], "Registers": [[46, "registers"], [82, "registers"]], "Row clock terminators": [[100, "row-clock-terminators"]], "SEU_OPT": [[49, "seu-opt"], [62, "seu-opt"]], "Secondary vertical clock spines": [[58, "secondary-vertical-clock-spines"]], "Shift registers": [[46, "shift-registers"], [82, "shift-registers"]], "Single-port 128\u00d71 RAM": [[82, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[46, "single-port-16x-ram"], [82, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[46, "single-port-32x-ram"], [82, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[46, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[82, "single-port-64x-ram"]], "Spartan 3": [[54, "spartan-3"]], "Spartan 3A DCMs": [[58, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[58, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[58, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[58, "spartan-3e-dcms"]], "Spartan 6": [[67, "spartan-6"]], "Speed": [[17, "speed"], [156, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [157, "speed-data"], [158, "speed-data"], [159, "speed-data"], [160, "speed-data"], [161, "speed-data"], [162, "speed-data"]], "Spine clock terminators": [[100, "spine-clock-terminators"]], "Spine column": [[104, "spine-column"], [117, "spine-column"]], "Spine muxes \u2014 CMT": [[113, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[100, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[100, "spine-muxes-iob"], [113, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[113, "spine-muxes-mgt"]], "Splitters": [[154, "splitters"]], "Sum of products": [[82, "sum-of-products"]], "Sum term, LUT2": [[167, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[109, "system-monitor"]], "TERM.E": [[91, "term-e"]], "TERM.N": [[91, "term-n"]], "TERM.S": [[91, "term-s"]], "TERM.W": [[91, "term-w"]], "TESTMODE": [[62, "testmode"], [129, "testmode"]], "TIMER": [[62, "timer"], [114, "timer"], [129, "timer"]], "TRIM": [[129, "trim"]], "Tables": [[71, "tables"]], "Terminators": [[55, "terminators"], [91, "terminators"]], "The BRAM bel": [[81, "the-bram-bel"]], "The CLKC clock center tile": [[38, "the-clkc-clock-center-tile"], [47, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[47, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[83, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[38, "the-gclkh-clock-row-distribution-tiles"], [47, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[38, "the-gclkvc-clock-spine-distribution-tiles"], [47, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[38, "the-gclkvm-secondary-clock-center-tiles"], [47, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[81, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[81, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[83, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [156, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [38, "id2"], [38, "id3"], [38, "id4"], [38, "id5"], [38, "id6"], [38, "id7"], [38, "id8"], [39, "id1"], [40, "id1"], [40, "id2"], [40, "id3"], [40, "id4"], [40, "id5"], [41, "id1"], [43, "id1"], [43, "id2"], [43, "id3"], [46, "id1"], [47, "id1"], [47, "id2"], [47, "id3"], [47, "id4"], [47, "id5"], [47, "id6"], [47, "id7"], [47, "id8"], [47, "id9"], [47, "id10"], [48, "id1"], [49, "id1"], [50, "id1"], [50, "id2"], [50, "id3"], [50, "id4"], [50, "id5"], [51, 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"9985": [45, 59, 81, 96, 110, 125, 139], "9986": [45, 59, 81, 96, 110, 125, 139], "9987": [45, 59, 81, 96, 110, 125, 139], "9988": [45, 59, 81, 96, 110, 125, 139], "9989": [45, 59, 81, 96, 110, 125, 139], "999": [45, 59, 72, 81, 96, 110, 125, 139], "9990": [45, 59, 81, 96, 110, 125, 139], "9991": [45, 59, 81, 96, 110, 125, 139], "9992": [45, 59, 81, 96, 110, 125, 139], "9993": [45, 59, 81, 96, 110, 125, 139], "9994": [45, 59, 81, 96, 110, 125, 139], "9995": [45, 59, 81, 96, 110, 125, 139], "9996": [45, 59, 81, 96, 110, 125, 139], "9997": [45, 59, 81, 96, 110, 125, 139], "9998": [45, 59, 81, 96, 110, 125, 139], "9999": [45, 59, 81, 96, 110, 125, 139], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 89, "9ce_mux": 155, "9fb_group": [157, 158, 159, 160, 161, 162], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": [55, 72, 79], "9lct5_inv": 155, "9reg_d_ireg": 155, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [98, 100, 123, 126, 142, 148, 149], "9rowcolumn012345678910111213141516171819": 105, "9rowcolumn012345678910111213141516171819202122": [69, 70], "9rowcolumn012345678910111213141516171819202122232425": 66, "9rowcolumn0123456789101112131415161718192021222324252627": [111, 116, 124, 131, 138, 141], "9rowcolumn01234567891011121314151617181920212223242526272829": [133, 134, 148], "9rowcolumn0123456789101112131415161718192021222324252627282930": [64, 71], "9rowcolumn012345678910111213141516171819202122232425262728293031": [118, 119], "A": [12, 14, 17, 35, 36, 46, 58, 81, 82, 87, 96, 104, 117, 122, 132, 137, 144, 147, 156, 167], "AED": [12, 165], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 37, 82, 167], "As": [35, 132, 167], "BY": [37, 46, 55, 73, 82, 91, 99], "For": [34, 35, 36, 55, 58, 87, 91, 104, 117, 132, 144, 167], "ISE": [35, 167], "IT": 91, "If": [35, 36, 81, 82, 96, 104, 117, 132, 137, 144, 167], "In": [15, 16, 36, 46, 55, 82, 91, 104, 108, 117, 122, 132, 137, 144, 147, 167], "It": [12, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 117, 132, 137, 144, 147, 156, 165, 167], "Its": [35, 81], "No": 144, "Not": [15, 16, 36, 55, 91, 167], "OR": [2, 6, 7, 36, 37], "On": [12, 15, 16, 36, 46, 47, 55, 58, 81, 87, 144, 167], "Such": [35, 55, 58, 87], "The": [12, 13, 15, 16, 17, 34, 35, 36, 37, 41, 42, 45, 46, 53, 54, 55, 56, 58, 65, 82, 87, 90, 91, 92, 96, 99, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 165, 166, 167], "Their": [46, 82], "There": [17, 35, 46, 55, 56, 81, 82, 91, 92, 104, 117, 132, 137, 144, 147], "These": [36, 91, 137, 144], "To": [35, 36, 96], "_": [17, 34, 36, 156, 167], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 155, 167], "_gclk": 167, "_init": [46, 82], "_inv": [36, 167], "_lct": 167, "_mc": [12, 165], "_mux": [36, 46, 82], "_none": 167, "_reg": [81, 96], "_srval": [46, 82], "_sum": 36, "a0": 45, "a0reg": [53, 65], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "a14": [2, 3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a15": [3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a16": [3, 6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a17": [6, 7, 22, 23, 24, 25, 45, 160, 161, 162], "a18": [6, 7, 22, 23, 24, 25, 160, 161, 162], "a19": [6, 7, 22, 23, 24, 25, 160, 161, 162], "a1reg": [53, 65], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a20": [6, 7, 22, 23, 24, 161, 162], "a21": [6, 7, 22, 23, 161, 162], "a22": [6, 7, 22, 23, 161, 162], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a5ffinit": [127, 140], "a5ffinitslice0": [127, 140], "a5ffmux": [127, 140], "a5ffsr": [127, 140], "a5ffsrinit": 60, "a5ffsrinitslice0": 60, "a5ffsrslice1": 127, "a5q0": 60, "a5q0100": [60, 127, 140], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a6lut": [60, 112, 127, 140], "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "a_dfeclkdlyadj": 134, "a_dfedlyovrd": 134, "a_dfedlyovrdgtx0": 134, "a_dfedlyovrdgtx1": 134, "a_dfedlyovrdgtx2": 134, "a_dfedlyovrdgtx3": 134, "a_dfetap1": 134, "a_dfetap2": 134, "a_dfetap3": 134, "a_dfetap4": 134, "a_dfetapovrd": 134, "a_dfetapovrdgtx0": 134, "a_dfetapovrdgtx1": 134, "a_dfetapovrdgtx2": 134, "a_dfetapovrdgtx3": 134, "a_fwdclk1001": 105, "a_fwdclk2001": 105, "a_fwdclk3001": 105, "a_fwdclk4001": 105, "a_gtpreset_0": 66, "a_gtpreset_0gtp": 66, "a_gtpreset_1": 66, "a_gtpreset_1gtp": 66, "a_gtxrxreset": 134, "a_gtxrxresetgtx0": 134, "a_gtxrxresetgtx1": 134, "a_gtxrxresetgtx2": 134, "a_gtxrxresetgtx3": 134, "a_gtxtxreset": 134, "a_gtxtxresetgtx0": 134, "a_gtxtxresetgtx1": 134, "a_gtxtxresetgtx2": 134, "a_gtxtxresetgtx3": 134, "a_input": [115, 130, 143], "a_loopback": 134, "a_loopback_0": 66, "a_loopback_1": 66, "a_pllclkrxreset": 134, "a_pllclkrxresetgtx0": 134, "a_pllclkrxresetgtx1": 134, "a_pllclkrxresetgtx2": 134, "a_pllclkrxresetgtx3": 134, "a_pllclktxreset": 134, "a_pllclktxresetgtx0": 134, "a_pllclktxresetgtx1": 134, "a_pllclktxresetgtx2": 134, "a_pllclktxresetgtx3": 134, "a_plllkdeten_0": 66, "a_plllkdeten_0gtp": 66, "a_plllkdeten_1": 66, "a_plllkdeten_1gtp": 66, "a_pllpowerdown_0": 66, "a_pllpowerdown_0gtp": 66, "a_pllpowerdown_1": 66, "a_pllpowerdown_1gtp": 66, "a_pllrxreset": 134, "a_pllrxresetgtx0": 134, "a_pllrxresetgtx1": 134, "a_pllrxresetgtx2": 134, "a_pllrxresetgtx3": 134, "a_plltxreset": 134, "a_plltxresetgtx0": 134, "a_plltxresetgtx1": 134, "a_plltxresetgtx2": 134, "a_plltxresetgtx3": 134, "a_prbscntreset": 134, "a_prbscntreset_0": 66, "a_prbscntreset_0gtp": 66, "a_prbscntreset_1": 66, "a_prbscntreset_1gtp": 66, "a_prbscntresetgtx0": 134, "a_prbscntresetgtx1": 134, "a_prbscntresetgtx2": 134, "a_prbscntresetgtx3": 134, "a_q": 81, "a_rxbufreset": 134, "a_rxbufreset_0": 66, "a_rxbufreset_0gtp": 66, "a_rxbufreset_1": 66, "a_rxbufreset_1gtp": 66, "a_rxbufresetgtx0": 134, "a_rxbufresetgtx1": 134, "a_rxbufresetgtx2": 134, "a_rxbufresetgtx3": 134, "a_rxcdrfreqreset": 134, "a_rxcdrfreqreset_0": 66, "a_rxcdrfreqreset_0gtp": 66, "a_rxcdrfreqreset_1": 66, "a_rxcdrfreqreset_1gtp": 66, "a_rxcdrfreqresetgtx0": 134, "a_rxcdrfreqresetgtx1": 134, "a_rxcdrfreqresetgtx2": 134, "a_rxcdrfreqresetgtx3": 134, "a_rxcdrhold": 134, "a_rxcdrhold_0": 66, "a_rxcdrhold_0gtp": 66, "a_rxcdrhold_1": 66, "a_rxcdrhold_1gtp": 66, "a_rxcdrholdgtx0": 134, "a_rxcdrholdgtx1": 134, "a_rxcdrholdgtx2": 134, "a_rxcdrholdgtx3": 134, "a_rxcdrphasereset": 134, "a_rxcdrphasereset_0": 66, "a_rxcdrphasereset_0gtp": 66, "a_rxcdrphasereset_1": 66, "a_rxcdrphasereset_1gtp": 66, "a_rxcdrphaseresetgtx0": 134, "a_rxcdrphaseresetgtx1": 134, "a_rxcdrphaseresetgtx2": 134, "a_rxcdrphaseresetgtx3": 134, "a_rxcdrreset": 134, "a_rxcdrreset_0": 66, "a_rxcdrreset_0gtp": 66, "a_rxcdrreset_1": 66, "a_rxcdrreset_1gtp": 66, "a_rxcdrresetgtx0": 134, "a_rxcdrresetgtx1": 134, "a_rxcdrresetgtx2": 134, "a_rxcdrresetgtx3": 134, "a_rxdfereset": 134, "a_rxdferesetgtx0": 134, "a_rxdferesetgtx1": 134, "a_rxdferesetgtx2": 134, "a_rxdferesetgtx3": 134, "a_rxenpmaphasealign": 134, "a_rxenpmaphasealign_0": 66, "a_rxenpmaphasealign_0gtp": 66, "a_rxenpmaphasealign_1": 66, "a_rxenpmaphasealign_1gtp": 66, "a_rxenpmaphasealigngtx0": 134, "a_rxenpmaphasealigngtx1": 134, "a_rxenpmaphasealigngtx2": 134, "a_rxenpmaphasealigngtx3": 134, "a_rxenprbstst": 134, "a_rxenprbstst_0": 66, "a_rxenprbstst_1": 66, "a_rxensamplealign": 134, "a_rxensamplealigngtx0": 134, "a_rxensamplealigngtx1": 134, "a_rxensamplealigngtx2": 134, "a_rxensamplealigngtx3": 134, "a_rxeqmix": 134, "a_rxeqmix_0": 66, "a_rxeqmix_1": 66, "a_rxplllkdeten": 134, "a_rxplllkdetengtx0": 134, "a_rxplllkdetengtx1": 134, "a_rxplllkdetengtx2": 134, "a_rxplllkdetengtx3": 134, "a_rxpllpowerdown": 134, "a_rxpllpowerdowngtx0": 134, "a_rxpllpowerdowngtx1": 134, "a_rxpllpowerdowngtx2": 134, "a_rxpllpowerdowngtx3": 134, "a_rxpmasetphas": 134, "a_rxpmasetphase_0": 66, "a_rxpmasetphase_0gtp": 66, "a_rxpmasetphase_1": 66, "a_rxpmasetphase_1gtp": 66, "a_rxpmasetphasegtx0": 134, "a_rxpmasetphasegtx1": 134, "a_rxpmasetphasegtx2": 134, "a_rxpmasetphasegtx3": 134, "a_rxpolar": 134, "a_rxpolarity_0": 66, "a_rxpolarity_0gtp": 66, "a_rxpolarity_1": 66, "a_rxpolarity_1gtp": 66, "a_rxpolaritygtx0": 134, "a_rxpolaritygtx1": 134, "a_rxpolaritygtx2": 134, "a_rxpolaritygtx3": 134, "a_rxpowerdown": 134, "a_rxpowerdown_0": 66, "a_rxpowerdown_1": 66, "a_rxreset": 134, "a_rxreset_0": 66, "a_rxreset_0gtp": 66, "a_rxreset_1": 66, "a_rxreset_1gtp": 66, "a_rxresetgtx0": 134, "a_rxresetgtx1": 134, "a_rxresetgtx2": 134, "a_rxresetgtx3": 134, "a_txbufdiffctrl": 134, "a_txbufdiffctrl_0": 66, "a_txbufdiffctrl_1": 66, "a_txdeemph": 134, "a_txdeemphgtx0": 134, "a_txdeemphgtx1": 134, "a_txdeemphgtx2": 134, "a_txdeemphgtx3": 134, "a_txdiffctrl": 134, "a_txdiffctrl_0": 66, "a_txdiffctrl_1": 66, "a_txelecidl": 134, "a_txelecidle_0": 66, "a_txelecidle_0gtp": 66, "a_txelecidle_1": 66, "a_txelecidle_1gtp": 66, "a_txelecidlegtx0": 134, "a_txelecidlegtx1": 134, "a_txelecidlegtx2": 134, "a_txelecidlegtx3": 134, "a_txenpmaphasealign": 134, "a_txenpmaphasealign_0": 66, "a_txenpmaphasealign_0gtp": 66, "a_txenpmaphasealign_1": 66, "a_txenpmaphasealign_1gtp": 66, "a_txenpmaphasealigngtx0": 134, "a_txenpmaphasealigngtx1": 134, "a_txenpmaphasealigngtx2": 134, "a_txenpmaphasealigngtx3": 134, "a_txenprbstst": 134, "a_txenprbstst_0": 66, "a_txenprbstst_1": 66, "a_txmargin": 134, "a_txplllkdeten": 134, "a_txplllkdetengtx0": 134, "a_txplllkdetengtx1": 134, "a_txplllkdetengtx2": 134, "a_txplllkdetengtx3": 134, "a_txpllpowerdown": 134, "a_txpllpowerdowngtx0": 134, "a_txpllpowerdowngtx1": 134, "a_txpllpowerdowngtx2": 134, "a_txpllpowerdowngtx3": 134, "a_txpmasetphas": 134, "a_txpmasetphase_0": 66, "a_txpmasetphase_0gtp": 66, "a_txpmasetphase_1": 66, "a_txpmasetphase_1gtp": 66, "a_txpmasetphasegtx0": 134, "a_txpmasetphasegtx1": 134, "a_txpmasetphasegtx2": 134, "a_txpmasetphasegtx3": 134, "a_txpolar": 134, "a_txpolarity_0": 66, "a_txpolarity_0gtp": 66, "a_txpolarity_1": 66, "a_txpolarity_1gtp": 66, "a_txpolaritygtx0": 134, "a_txpolaritygtx1": 134, "a_txpolaritygtx2": 134, "a_txpolaritygtx3": 134, "a_txpostemphasi": 134, "a_txpowerdown": 134, "a_txpowerdown_0": 66, "a_txpowerdown_1": 66, "a_txprbsforceerr": 134, "a_txprbsforceerr_0": 66, "a_txprbsforceerr_0gtp": 66, "a_txprbsforceerr_1": 66, "a_txprbsforceerr_1gtp": 66, "a_txprbsforceerrgtx0": 134, "a_txprbsforceerrgtx1": 134, "a_txprbsforceerrgtx2": 134, "a_txprbsforceerrgtx3": 134, "a_txpreemphasi": 134, "a_txpreemphasis_0": 66, "a_txpreemphasis_1": 66, "a_txreset": 134, "a_txreset_0": 66, "a_txreset_0gtp": 66, "a_txreset_1": 66, "a_txreset_1gtp": 66, "a_txresetgtx0": 134, "a_txresetgtx1": 134, "a_txresetgtx2": 134, "a_txresetgtx3": 134, "a_txsw": 134, "a_txswinggtx0": 134, "a_txswinggtx1": 134, "a_txswinggtx2": 134, "a_txswinggtx3": 134, "aa1": [6, 7, 22, 23, 161, 162], "aa10": [6, 7, 161, 162], "aa11": [6, 7, 161, 162], "aa12": [6, 7, 161, 162], "aa13": [6, 7, 161, 162], "aa14": [6, 7, 161, 162], "aa15": [6, 7, 161, 162], "aa16": [6, 7, 161, 162], "aa17": [6, 7, 161, 162], "aa18": [6, 7, 161, 162], "aa19": [6, 7, 161, 162], "aa2": [6, 7, 22, 23, 161, 162], "aa20": [6, 7, 161, 162], "aa21": [6, 7, 161, 162], "aa22": [6, 7, 161, 162], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 161, 162], "aa4": [6, 7, 22, 23, 161, 162], "aa5": [6, 7, 161, 162], "aa6": [6, 7, 161, 162], "aa7": [6, 7, 161, 162], "aa8": [6, 7, 161, 162], "aa9": [6, 7, 161, 162], "ab": [81, 91, 96], "ab1": [6, 7, 22, 23, 161, 162], "ab10": [6, 7, 161, 162], "ab11": [6, 7, 161, 162], "ab12": [6, 7, 161, 162], "ab13": [6, 7, 161, 162], "ab14": [6, 7, 161, 162], "ab15": [6, 7, 161, 162], "ab16": [6, 7, 161, 162], "ab17": [6, 7, 161, 162], "ab18": [6, 7, 161, 162], "ab19": [6, 7, 161, 162], "ab2": [6, 7, 22, 23, 161, 162], "ab20": [6, 7, 161, 162], "ab21": [6, 7, 161, 162], "ab22": [6, 7, 161, 162], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 161, 162], "ab4": [6, 7, 22, 23, 161, 162], "ab5": [6, 7, 161, 162], "ab6": [6, 7, 161, 162], "ab7": [6, 7, 161, 162], "ab8": [6, 7, 161, 162], "ab9": [6, 7, 161, 162], "abort": 35, "about": 35, "abov": [35, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 132, 144, 147, 167], "abp": 81, "abs_freq_ref11": 102, "abs_freq_snapshot10": 102, "absolut": 156, "abuff": 40, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "ac_cap_di": 134, "ac_cap_dis_0": [66, 118, 119], "ac_cap_dis_0gtp": 66, "ac_cap_dis_0gtp_du": 118, "ac_cap_dis_0gtx_du": 119, "ac_cap_dis_1": [66, 118, 119], "ac_cap_dis_1gtp": 66, "ac_cap_dis_1gtp_du": 118, "ac_cap_dis_1gtx_du": 119, "ac_cap_disgtx0": 134, "ac_cap_disgtx1": 134, "ac_cap_disgtx2": 134, "ac_cap_disgtx3": 134, "acb": [12, 34, 165], "accept": 91, "access": [35, 55, 56, 91, 92], "access_mod": 63, "accordingli": 36, "acd": 34, "acquir": 165, "across": [12, 34, 36, 45, 46, 53, 58, 65, 81, 82, 87, 91, 96, 104, 117, 132, 144, 147, 156, 165, 167], "activ": [35, 36, 46, 82, 166], "activelanesin": 123, "actual": [15, 16, 35, 55, 58, 81, 91, 104, 117, 132, 144, 167], "acy0": [60, 112, 127, 140], "acy0slice0": [112, 127, 140], "acy0slice1": [60, 127], "ad": [55, 56, 58, 81, 91, 92], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 109, "add": 92, "addit": [12, 14, 34, 36, 58, 81, 96, 104, 117, 132, 144, 167], "addition": [34, 35, 36, 46, 55, 82, 87, 91, 92, 104, 117, 132], "addr": [15, 16, 81, 96], "addr0": 72, "addr000000001": 72, "addr00000001": 72, "addr000001": 72, "addr000010000": 72, "addr0int": 72, "addr1": 72, "addr10": 72, "addr100000010": 72, "addr10000010": 72, "addr100010": 72, "addr1000100": 72, "addr100100000": 72, "addr10int": 72, "addr11": 72, "addr1101000": 72, "addr11int": 72, "addr12": 72, "addr1200001": 72, "addr1210001": 72, "addr12int": 72, "addr13": 72, "addr1300010": 72, "addr1310010": 72, "addr13int": 72, "addr14": 72, "addr1400100": 72, "addr1410100": 72, "addr14int": 72, "addr15": 72, "addr1501000": 72, "addr1511000": 72, "addr15int": 72, "addr16": 72, "addr1610001": 72, "addr16int": 72, "addr17": 72, "addr1710010": 72, "addr17int": 72, "addr18": 72, "addr1810100": 72, "addr18int": 72, "addr19": 72, "addr1911000": 72, "addr19int": 72, "addr1int": 72, "addr2": 72, "addr20": 72, "addr200000001": 72, "addr2000001": 72, "addr200000100": 72, "addr20000100": 72, "addr200100": 72, "addr20int": 72, "addr21": 72, "addr2100010": 72, "addr21int": 72, "addr22": 72, "addr2200100": 72, "addr22int": 72, "addr23": 72, "addr2301000": 72, "addr23int": 72, "addr24": 72, "addr240000001": 72, "addr2410001": 72, "addr24int": 72, "addr25": 72, "addr250000010": 72, "addr2510010": 72, "addr25int": 72, "addr26": 72, "addr260000100": 72, "addr2610100": 72, "addr26int": 72, "addr27": 72, "addr270001000": 72, "addr2711000": 72, "addr27int": 72, "addr28": 72, "addr2800000100": 72, "addr2800010000": 72, "addr280010000": 72, "addr28int": 72, "addr29": 72, "addr2900001000": 72, "addr2900100000": 72, "addr290100001": 72, "addr29int": 72, "addr2int": 72, "addr3": 72, "addr30": 72, "addr300000010": 72, "addr300001000": 72, "addr30001000": 72, "addr3001000001": 72, "addr300100010": 72, "addr3001010000": 72, "addr301000": 72, "addr30int": 72, "addr31": 72, "addr3101000010": 72, "addr310100100": 72, "addr3101100000": 72, "addr31int": 72, "addr3int": 72, "addr4": 72, "addr410001": 72, "addr4int": 72, "addr5": 72, "addr510010": 72, "addr5int": 72, "addr6": 72, "addr610100": 72, "addr6int": 72, "addr7": 72, "addr711000": 72, "addr7int": 72, "addr8": 72, "addr800001": 72, "addr8int": 72, "addr9": 72, "addr900010": 72, "addr9int": 72, "addr_cascade_out_a": 139, "addr_cascade_out_abram": 139, "addr_cascade_out_b": 139, "addr_cascade_out_bbram": 139, "addra0": 72, "addra1": 72, "addra10": 72, "addra11": 72, "addra2": 72, "addra3": 72, "addra4": 72, "addra5": 72, "addra6": 72, "addra7": 72, "addra8": 72, "addra9": 72, "addral0": 139, "addral1": 139, "addral10": 139, "addral11": 139, "addral12": 139, "addral13": 139, "addral14": 139, "addral2": 139, "addral3": 139, "addral4": 139, "addral5": 139, "addral6": 139, "addral7": 139, "addral8": 139, "addral9": 139, "addrau0": 139, "addrau1": 139, "addrau10": 139, "addrau11": 139, "addrau12": 139, "addrau13": 139, "addrau14": 139, "addrau2": 139, "addrau3": 139, "addrau4": 139, "addrau5": 139, "addrau6": 139, "addrau7": 139, "addrau8": 139, "addrau9": 139, "addrb0": 72, "addrb1": 72, "addrb10": 72, "addrb11": 72, "addrb2": 72, "addrb3": 72, "addrb4": 72, "addrb5": 72, "addrb6": 72, "addrb7": 72, "addrb8": 72, "addrb9": 72, "addrbl0": 139, "addrbl1": 139, "addrbl10": 139, "addrbl11": 139, "addrbl12": 139, "addrbl13": 139, "addrbl14": 139, "addrbl2": 139, "addrbl3": 139, "addrbl4": 139, "addrbl5": 139, "addrbl6": 139, "addrbl7": 139, "addrbl8": 139, "addrbl9": 139, "addrbu0": 139, "addrbu1": 139, "addrbu10": 139, "addrbu11": 139, "addrbu12": 139, "addrbu13": 139, "addrbu14": 139, "addrbu2": 139, "addrbu3": 139, "addrbu4": 139, "addrbu5": 139, "addrbu6": 139, "addrbu7": 139, "addrbu8": 139, "addrbu9": 139, "address": [15, 16, 35, 46, 81, 82, 91, 96], "adi1mux": [60, 112, 127, 140], "adi1muxslice0": [60, 112, 127], "adjac": [55, 91, 96, 144, 147], "adreg": [130, 143], "adregdsp0": 130, "adregdsp1": 130, "adv_b": 147, "advanc": 14, "ae1": [22, 23], "ae10": [22, 23], "ae11": [22, 23], "ae12": [22, 23], "ae13": [22, 23], "ae14": [22, 23], "ae15": [22, 23], "ae16": [22, 23], "ae17": [22, 23], "ae18": [22, 23], "ae19": [22, 23], "ae2": [22, 23], "ae20": [22, 23], "ae21": [22, 23], "ae22": [22, 23], "ae23": [22, 23], "ae24": [22, 23], "ae25": [22, 23], "ae26": [22, 23], "ae3": [22, 23], "ae4": [22, 23], "ae5": [22, 23], "ae6": [22, 23], "ae7": [22, 23], "ae8": [22, 23], "ae9": [22, 23], "aer_base_ptr": [138, 148], "aer_cap_ecrc_check_cap": [138, 148], "aer_cap_ecrc_check_capablepci": [138, 148], "aer_cap_ecrc_gen_cap": [138, 148], "aer_cap_id": [138, 148], "aer_cap_int_msg_num_msi": 138, "aer_cap_int_msg_num_msix": 138, "aer_cap_multihead": 148, "aer_cap_nextptr": [138, 148], "aer_cap_on": [138, 148], "aer_cap_optional_err_support": 148, "aer_cap_permit_rooterr_upd": [138, 148], "aer_cap_permit_rooterr_updatepci": [138, 148], "aer_cap_vers": [138, 148], "aerbaseptr": 123, "aercapabilityecrccheckcap": 123, "aercapabilityecrcgencap": 123, "aercapabilityecrcgencapablepci": 123, "aercapabilitynextptr": 123, "af1": [22, 23], "af10": [22, 23], "af11": [22, 23], "af12": [22, 23], "af13": [22, 23], "af14": [22, 23], "af15": [22, 23], "af16": [22, 23], "af17": [22, 23], "af18": [22, 23], "af19": [22, 23], "af2": [22, 23], "af20": [22, 23], "af21": [22, 23], "af22": [22, 23], "af23": [22, 23], "af24": [22, 23], "af25": [22, 23], "af26": [22, 23], "af3": [22, 23], "af4": [22, 23], "af5": [22, 23], "af6": [22, 23], "af7": [22, 23], "af8": [22, 23], "af9": [22, 23], "aff_latch": 127, "aff_latchslice0": 127, "affect": [36, 91, 144, 167], "affinit": [112, 127, 140], "affinitslice0": [112, 127, 140], "affinitslice1": 127, "affmux": [60, 112, 127, 140], "affmuxslice1": 60, "affsr": [112, 127, 140], "affsrinit": 60, "affsrinitslice0": 60, "affsrinitslice1": 60, "affsrslice0": 140, "affsrslice1": [127, 140], "after": [35, 36, 55, 91, 104, 117], "afterward": 167, "ag": 35, "again": [35, 91], "agp": 79, "agp0": 93, "agp00011": 79, "agp0100101011": 93, "agp0111": 79, "agp011101010": 79, "agp011101011": 79, "agp1111": 93, "ai1": [127, 140], "aim": 11, "align": [96, 144], "align_comma_msb": 88, "align_comma_word": [89, 105, 134], "align_comma_word_0": [66, 118, 119], "align_comma_word_0gtp": 66, "align_comma_word_0gtp_du": 118, "align_comma_word_0gtx_du": 119, "align_comma_word_1": [66, 118, 119], "align_comma_word_1gtp": 66, "align_comma_word_1gtp_du": 118, "align_comma_word_1gtx_du": 119, "align_comma_wordgtx0": 134, "align_comma_wordgtx1": 134, "align_comma_wordgtx2": 134, "align_comma_wordgtx3": 134, "all": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 55, 58, 81, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 166, 167], "alloc": [15, 16, 36, 58], "alloc1312": [15, 16], "alloc1514": [15, 16], "alloc1716": [15, 16], "alloc1918": [15, 16], "alloc2120": [15, 16], "allow": [36, 55, 56, 81, 82, 91, 92, 167], "allow_x8_gen2": [138, 148], "allow_x8_gen2pci": [138, 148], "almost": [58, 104, 144], "almost_empty_offset": [96, 110, 125, 139], "almost_empty_valu": 142, "almost_full_offset": [96, 110, 125, 139], "almost_full_valu": 142, "almostempti": 96, "almostful": 96, "alon": 82, "along": [144, 165], "alreadi": [35, 167], "also": [12, 14, 34, 36, 46, 55, 58, 81, 82, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 165, 167], "alt": [46, 82], "alt0": [37, 46, 60, 82, 99, 112, 127, 140], "alt00010001": 107, "alt0010001": 107, "altdig": [46, 82], "altern": [46, 82, 144], "alumode0": [115, 130, 143], "alumode0dsp0": 115, "alumode0dsp1": 115, "alumode1": [115, 130, 143], "alumode2": [115, 130, 143], "alumode2dsp0": 143, "alumode2dsp1": 143, "alumode3": [115, 130, 143], "alumode3dsp0": [115, 130], "alumode3dsp1": 130, "alumodereg": [115, 130, 143], "alwai": [12, 14, 17, 35, 36, 46, 55, 58, 81, 82, 87, 91, 104, 108, 117, 122, 132, 137, 144, 156, 167], "amount": [58, 87, 104], "an": [12, 14, 15, 17, 34, 35, 36, 46, 55, 56, 58, 81, 87, 91, 92, 96, 144, 147, 155, 156, 165, 166, 167], "analog": [55, 91, 108, 122, 137, 147], "analog_read111": 63, "and1": [37, 46], "ani": [35, 36, 46, 55, 58, 87, 91, 108, 122, 144, 167], "anoth": [46, 82, 91, 104, 117, 132, 144, 147], "anyth": [35, 82], "anywai": [55, 144], "anywher": 144, "aoutmux": [60, 112, 127, 140], "aoutmuxslice1": 60, "appear": [35, 46, 144], "appli": 144, "applic": [16, 36, 46, 144], "appropri": [36, 96], "apu_control": 124, "apu_test": 124, "apu_udi0": 124, "apu_udi1": 124, "apu_udi10": 124, "apu_udi11": 124, "apu_udi12": 124, "apu_udi13": 124, "apu_udi14": 124, "apu_udi15": 124, "apu_udi2": 124, "apu_udi3": 124, "apu_udi4": 124, "apu_udi5": 124, "apu_udi6": 124, "apu_udi7": 124, "apu_udi8": 124, "apu_udi9": 124, "ar": [12, 13, 15, 16, 17, 34, 35, 36, 38, 42, 45, 46, 47, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 132, 137, 144, 147, 155, 156, 166, 167], "arammod": [60, 112, 127, 140], "arb_num_time_slot": 69, "arb_time_slot_0": 69, "arb_time_slot_1": 69, "arb_time_slot_10": 69, "arb_time_slot_11": 69, "arb_time_slot_2": 69, "arb_time_slot_3": 69, "arb_time_slot_4": 69, "arb_time_slot_5": 69, "arb_time_slot_6": 69, "arb_time_slot_7": 69, "arb_time_slot_8": 69, "arb_time_slot_9": 69, "arbitrari": [14, 36, 144, 167], "arbitrarili": 12, "architectur": [104, 165], "area": [15, 16, 35, 45, 47, 55, 58, 81, 83, 87, 91, 96, 104, 117, 132, 144, 155, 156, 167], "areg": [45, 81, 103], "areg_acascreg": [115, 130, 143], "aren": [55, 58, 147], "ari_cap_en": 149, "ari_cap_enablepcie3": 149, "arm": 144, "around": [91, 104, 132], "arrai": [35, 155, 156, 167], "arrang": [147, 155], "array_mod": 142, "array_mode_4_x_40": 142, "array_mode_4_x_81": 142, "array_mode_8_x_41": 142, "array_modein_fifo": 142, "ascii": 167, "assembl": [46, 82], "assert": [15, 16], "assign": [13, 15, 16, 58, 87, 104, 117, 132, 144, 167], "associ": [12, 34, 36, 37, 42, 46, 55, 58, 82, 87, 91, 99, 104, 108, 117, 122, 132, 144, 156, 165, 166, 167], "async": [14, 36, 81, 167], "async1": [53, 61, 65, 141], "async11": [45, 59], "asynchron": [46, 56, 82, 167], "atbbumpen": 105, "atben": 105, "atbsel": 105, "attempt": 35, "attribut": [45, 46, 81, 82, 96], "auto": 35, "auto01": 134, "auto_c": 105, "auto_calgt11a": 105, "auto_calgt11b": 105, "auto_dps00": 102, "auto_zd211": 102, "autoincr": 35, "automot": [12, 34], "autoreset_over_under_flow": 115, "autoreset_patdet": [130, 143], "autoreset_pattern_detect": 115, "autoreset_pattern_detect_optinv": 115, "autoreset_pattern_detectdsp0": 115, "aux": [2, 3, 4, 5, 6, 7, 8, 9], "auxiliari": [108, 122, 137, 147], "avail": [17, 55, 91, 104, 117, 132, 144, 156], "ave_freq_lock10": 102, "awai": [104, 117, 144], "ax0": [60, 112, 127, 140], "ax01": [60, 112, 127, 140], "ax0100": [112, 127, 140], "ax1": [60, 112], "ax10": [127, 140], "ax1010": 60, "axisten_if_cc_alignment_mod": 149, "axisten_if_cc_alignment_modepcie3": 149, "axisten_if_cc_parity_chk": 149, "axisten_if_cq_alignment_mod": 149, "axisten_if_enable_client_tag": 149, "axisten_if_enable_msg_rout": 149, "axisten_if_enable_rx_msg_intfc": 149, "axisten_if_rc_alignment_mod": 149, "axisten_if_rc_alignment_modepcie3": 149, "axisten_if_rc_straddl": 149, "axisten_if_rq_alignment_mod": 149, "axisten_if_rq_parity_chk": 149, "axisten_if_rq_parity_chkpcie3": 149, "axisten_if_width": 149, "b": [2, 3, 4, 5, 6, 7, 8, 9, 36, 46, 55, 78, 81, 87, 91, 96, 150, 151, 152, 157, 158, 159, 160, 161, 162], "b0": [45, 81], "b0reg": [53, 65], "b1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 45, 157, 158, 159, 160, 161, 162], "b10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 45, 158, 159, 160, 161, 162], "b11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 162], "b11100": 150, "b12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 45, 159, 160, 161, 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8, 9, 36, 155, 167], "clk_mux3433": 16, "clk_mux3736": 15, "clk_out_gtp_sel_0": 66, "clk_out_gtp_sel_0gtp": 66, "clk_out_gtp_sel_1": 66, "clk_out_gtp_sel_1gtp": 66, "clk_rebuf": 141, "clk_sel_typ": 61, "clk_switch_opt": 49, "clk_term": 100, "clk_term_b": 104, "clk_term_t": 104, "clk_to_dcm0": 71, "clk_to_dcm1": 71, "clk_to_pll": 64, "clka": [72, 96, 97], "clka00": 97, "clka1d81010000010000": 97, "clka_en": 97, "clkaint": 72, "clkardclkl": [110, 125, 139], "clkardclklbram": 125, "clkardclku": [110, 125, 139], "clkardclkubram": 125, "clkawrclk": 59, "clkawrclkbram_h0": 59, "clkawrclkbram_h1": 59, "clkb": [58, 72, 78, 87, 96, 97, 122, 152], "clkb01": 97, "clkb_2dll": 78, "clkb_4dll": 78, "clkb_enabl": 97, "clkb_enablepmcd1": 97, "clkbint": 72, "clkbrdclk": 59, "clkbrdclkbram_h0": 59, "clkbrdclkbram_h1": 59, "clkbrst": 71, "clkbwrclkl": [110, 125, 139], "clkbwrclku": [110, 125, 139], "clkbwrclkubram": 125, "clkc": [41, 54, 58, 67, 87, 97], "clkc10": 97, "clkc_50a": [54, 58], "clkc_clkout0": 61, "clkc_clkout1": 61, "clkc_enabl": 97, "clkc_enablepmcd1": 97, "clkc_mux": 103, "clkcm_cfg": 134, "clkcm_cfggtx1": 134, "clkd": 97, "clkd11": 97, "clkd_enabl": 97, "clkd_enablepmcd1": 97, "clkdiv": 122, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkdivologic0": 122, "clkdivologic1": 122, "clkdsp0": 130, "clkdsp1": 130, "clkdv": [51, 52, 64, 86], "clkdv0010000": 74, "clkdv0010000010": 74, "clkdv00100000110": 74, "clkdv001011": 74, "clkdv01000000110": 74, "clkdv010100": 74, "clkdv0110": 64, "clkdv1000000010": 74, "clkdv10000010010": 74, "clkdv10000011": 102, "clkdv10100000011": 74, "clkdv101101": 74, "clkdv1100001": 74, "clkdv110100": 74, "clkdv1101000": 74, "clkdv1110000": 74, "clkdv_count_fal": [51, 52, 64, 77, 86, 102], "clkdv_count_fall_2": [51, 52, 64, 77, 86, 102], "clkdv_count_max": [51, 52, 64, 77, 86, 102], "clkdv_enabl": 102, "clkdv_enabledcm": 102, "clkdv_mode": [51, 52, 64, 77, 86, 102], "clkdv_modedcm": [51, 52, 86, 102], "clkdv_modedcm0": 64, "clkdv_modedcm1": 64, "clkdv_modedl": 77, "clkdv_phase_fal": [51, 52, 64, 77, 86, 102], "clkdv_phase_ris": [51, 52, 64, 77, 86, 102], "clkdvdcm": [51, 52, 86], "clkdvdcm0": 64, "clkdvdcm1": 64, "clkfb": [51, 64, 77, 86, 102], "clkfb0": [51, 86, 102], "clkfb011": 55, "clkfb_enabl": 102, "clkfb_enabledcm": 102, "clkfb_feedback": 102, "clkfb_feedbackdcm": 102, "clkfb_iob": [51, 52, 64, 86, 102], "clkfb_iobdcm": [51, 52, 86, 102], "clkfb_iobdcm0": 64, "clkfb_iobdcm1": 64, "clkfb_pad": 77, "clkfb_padint": 77, "clkfbdcm": [51, 86], "clkfbdcm10111": 71, "clkfbin": 71, "clkfbin110": 71, "clkfbout10100": 71, "clkfbout111": 71, "clkfx": [51, 52, 64, 86], "clkfx00110001": 102, "clkfx0111": 64, "clkfx180": [51, 86], "clkfx18000101001": 102, "clkfx1801000": 64, "clkfx180_enabl": 102, "clkfx180_enabledcm": 102, "clkfx180dcm": [51, 86], "clkfx_divid": [51, 52, 64, 86, 102], "clkfx_enabl": 102, "clkfx_enabledcm": 102, "clkfx_multipli": [51, 52, 64, 86, 102], "clkfxdcm": [51, 52, 86], "clkfxdcm0": 64, "clkfxdcm1": 64, "clkfxdv_divid": 64, "clkh": 152, "clkin": [64, 71, 77, 102, 118, 119], "clkin011": 55, "clkin1": [51, 86, 102], "clkin1100": 71, "clkin_clkfb_en": 64, "clkin_clkfb_enabledcm0": 64, "clkin_clkfb_enabledcm1": 64, "clkin_clkfbin_us": 71, "clkin_clkfbin_usedpl": 71, "clkin_divide_by_2": [51, 52, 64, 86, 102], "clkin_divide_by_2dcm": [51, 52, 86, 102], "clkin_divide_by_2dcm0": 64, "clkin_divide_by_2dcm1": 64, "clkin_en": 102, "clkin_enabledcm": 102, "clkin_iob": [51, 52, 64, 86, 102], "clkin_iobdcm": [51, 52, 86, 102], "clkin_iobdcm0": 64, "clkin_iobdcm1": 64, "clkin_pad": 77, "clkindc_b": [118, 119], "clkindc_b_0": 66, "clkindc_b_0gtp": 66, "clkindc_b_1": 66, "clkindc_b_1gtp": 66, "clkindc_bgtp_dual": 118, "clkindc_bgtx_dual": 119, "clkineast011": 66, "clkinsel": 71, "clkinsel_mod": 71, "clkinsel_modepl": 71, "clkinsel_stat": 71, "clkinsel_staticpl": 71, "clkint": [73, 79], "clkinwest111": 66, "clkiob1": 79, "clkiob111111110": 151, "clkiob2": 79, "clkiob3": 79, "clkl": [58, 78, 152], "clkout0000": 71, "clkout1001": 71, "clkout2010": 71, "clkout3011": 71, "clkout4100": 71, "clkout5101": 71, "clkout_east": 66, "clkout_eastgtp": 66, "clkout_north": [118, 119], "clkout_north_s0": [118, 119], "clkout_north_s101": [118, 119], "clkout_phase_shift": 64, "clkout_south": [118, 119], "clkout_south_n0": [118, 119], "clkout_south_n001": [118, 119], "clkout_west": 66, "clkout_westgtp": 66, "clkpad": [55, 87], "clkpad00000000000": 74, "clkpad000000000000": 74, "clkpad000000000001": 74, "clkpad000000000001000": 77, "clkpad00000000001": 74, "clkpad0000000001000": 77, "clkpad0000011": 74, "clkpad0000100000100": 91, "clkpad0001000000010000": 55, "clkpad00100010": 74, "clkpad01100100": 74, "clkpad10000000000": 74, "clkpad100000000000": 74, "clkpad100000000001": 74, "clkpad10000000001": 74, "clkpad100000000010000": 77, "clkpad1000000010000": 77, "clkpad10000100": 74, "clkpad1000100001000": 91, "clkpad1001000000100000": 55, "clkpad1100101": 74, "clkpad2001000000100": 91, "clkpad2001000001000000": 55, "clkpad3001000001000": 91, "clkpad3001000010000000": 55, "clkpad4010000000100": 91, "clkpad5010000001000": 91, "clkpad6100000000100": 91, "clkpad7100000001000": 91, "clkpin000": 61, "clkpin0000": 61, "clkpin01": 61, "clkpin1001": 61, "clkpin4100": 61, "clkpin5101": 61, "clkpn011": [118, 119], "clkpn1": [118, 119], "clkr": [58, 78, 152], "clkrcv_trst": [119, 134], "clkrcv_trst_0": 66, "clkrcv_trst_0gtp": 66, "clkrcv_trst_1": 66, "clkrcv_trst_1gtp": 66, "clkrcv_trstgtx1": 134, "clkrcv_trstgtx_dual": 119, "clkslice0": 112, "clkslice1": [60, 127], "clkt": [58, 78, 87, 152], "clkt_2dll": 78, "clkt_4dll": 78, "clktestsig0111": 134, "clktestsig1": 133, "clktestsig11": 134, "clktestsig1111": 134, "clktestsig_sel": 133, "clktestsig_selgth": 133, "clkv": [78, 152], "clkv_bram": 72, "clkv_bram_bot": 78, "clkv_bram_top": 78, "clock": [11, 12, 34, 35, 36, 41, 44, 46, 54, 55, 56, 67, 78, 81, 82, 90, 92, 96, 104, 106, 108, 117, 120, 122, 132, 135, 137, 144, 145, 147, 156, 165, 167], "clock_delai": 124, "clock_invert_m": 115, "clock_invert_p": 115, "clock_invert_pdsp1": 115, "clockwis": [58, 87], "close": [58, 81, 132, 144], "closest": 58, "clr0": 150, "clrmux": 150, "clrmuxlc0": 150, "clrmuxlc1": 150, "clrmuxlc2": 150, "clrmuxlc3": 150, "cm_trim": 134, "cm_trim_0": [66, 119], "cm_trim_1": [66, 119], "cmd_intx_impl": [138, 148], "cmd_intx_implementedpci": [138, 148], "cmo": 14, "cmos0": 151, "cmos00": [74, 79], "cmos00111": 137, "cmos01": 74, "cmos111": [57, 93, 108, 122], "cmos1200011": 137, "cmos_hv111": 57, "cmos_lv001": 57, "cmos_vccaux111": 57, "cmos_vccint011": 57, "cmos_vcco100": 57, "cmt": [64, 71, 117, 120, 122, 132, 144, 145], "cmt0": 61, "cmt10": 61, "cmt_bufg_": 132, "cmt_bufg_bot": [132, 135], "cmt_bufg_top": [132, 135], "cmt_clk010000000001000": 113, "cmt_clk100000010001000": 113, "cmt_clk1000001000010000": 113, "cmt_clk1100100000010000": 113, "cmt_clk1200000001010000": 113, "cmt_clk1300000100010000": 113, "cmt_clk1400010000010000": 113, "cmt_clk1501000000010000": 113, "cmt_clk1610000000100000": 113, "cmt_clk1700000010100000": 113, "cmt_clk1800001000100000": 113, "cmt_clk1900100000100000": 113, "cmt_clk2000000001100000": 113, "cmt_clk200001000001000": 113, "cmt_clk2100000100100000": 113, "cmt_clk2200010000100000": 113, "cmt_clk2301000000100000": 113, "cmt_clk2410000000000010": 113, "cmt_clk2500000010000010": 113, "cmt_clk2600001000000010": 113, "cmt_clk2700100000000010": 113, "cmt_clk300100000001000": 113, "cmt_clk400000001001000": 113, "cmt_clk500000100001000": 113, "cmt_clk600010000001000": 113, "cmt_clk701000000001000": 113, "cmt_clk810000000010000": 113, "cmt_clk900000010010000": 113, "cmt_d00100": 61, "cmt_d100100": 61, "cmt_d10100": 61, "cmt_d110100": 61, "cmt_d120100": 61, "cmt_d130100": 61, "cmt_d140100": 61, "cmt_d150100": 61, "cmt_d20100": 61, "cmt_d30100": 61, "cmt_d40100": 61, "cmt_d50100": 61, "cmt_d60100": 61, "cmt_d70100": 61, "cmt_d80100": 61, "cmt_d90100": 61, "cmt_dcm": 64, "cmt_enabl": 61, "cmt_fifo": 145, "cmt_pll": 71, "cmt_u01000": 61, "cmt_u101000": 61, "cmt_u11000": 61, "cmt_u111000": 61, "cmt_u121000": 61, "cmt_u131000": 61, "cmt_u141000": 61, "cmt_u151000": 61, "cmt_u21000": 61, "cmt_u31000": 61, "cmt_u41000": 61, "cmt_u51000": 61, "cmt_u61000": 61, "cmt_u71000": 61, "cmt_u81000": 61, "cmt_u91000": 61, "cmux": 151, "cmuxosc": 151, "cnr": [58, 78, 87, 152], "co01": 150, "co1": 150, "code": 35, "coin_window": [51, 86], "col": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [58, 81, 104, 117, 132, 144], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 46, 47, 55, 78, 81, 82, 83, 87, 91, 108, 122, 137, 147, 155, 156, 157, 158, 159, 160, 161, 162, 164, 166], "columnar": 104, "com": [51, 86], "com_burst_v": 134, "com_burst_val_0": [66, 118, 119], "com_burst_val_1": [66, 118, 119], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 46, 55, 81, 82, 91, 104, 167], "combination": 81, "combinatori": [14, 36, 167], "come": [12, 34, 36, 46, 58, 81, 87, 104, 108, 117, 122, 132, 144, 165, 167], "comma32": 105, "comma32gt11a": 105, "comma32gt11b": 105, "comma_10b_en": 134, "comma_10b_enable_0": [66, 118, 119], "comma_10b_enable_1": [66, 118, 119], "comma_10b_mask": [88, 89, 105], "comma_doubl": 134, "comma_double_0": [118, 119], "comma_double_0gtp_du": 118, "comma_double_0gtx_du": 119, "comma_double_1": [118, 119], "comma_double_1gtp_du": 118, "comma_double_1gtx_du": 119, "comma_doublegtx0": 134, "comma_doublegtx1": 134, "comma_doublegtx2": 134, "comma_doublegtx3": 134, "commerci": [17, 156], "common": [100, 147], "common_hclk_giob": 100, "common_mgt": 100, "common_mgtioclk": 100, "commonli": [144, 155], "companion": [44, 106], "compat": [12, 34, 165], "compens": 82, "complement": [108, 122, 137, 147], "complet": [12, 13, 16, 34, 35, 36, 104, 144, 155, 165], "complex": [15, 16, 144], "comput": [81, 155], "concaten": [15, 16, 81, 96], "conceptu": 58, "concur": [51, 52, 64, 86], "concur00100101": 102, "concur1001": 64, "concur_en": 102, "concur_enabledcm": 102, "concurdcm": [51, 52, 86], "concurdcm0": 64, "concurdcm1": 64, "config": [15, 16, 155], "config10": 102, "config_fallback": [114, 129], "config_r": [39, 48, 49, 75, 84, 101, 114, 129, 151], "configrout": 123, "configur": [11, 12, 15, 33, 34, 35, 41, 44, 47, 54, 55, 56, 67, 78, 87, 90, 91, 92, 104, 106, 108, 117, 120, 122, 132, 135, 137, 145, 147, 152, 155, 164], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 46, 58, 81, 82, 91, 92, 96, 108, 122, 137, 144, 166, 167], "consecut": 132, "consid": [35, 104, 108, 117, 122, 132, 137, 144, 147], "consist": [35, 36, 81, 104, 117, 122, 132, 137, 144], "const": [13, 14, 35, 36, 46, 82, 166, 167], "constant": [36, 46, 82, 108], "constraint": 12, "construct": 167, "consult": 15, "contain": [15, 17, 34, 42, 45, 46, 55, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 132, 137, 144, 147, 166, 167], "content": [35, 46, 82, 132], "contigu": [15, 16], "continu": [35, 147], "control": [12, 14, 35, 36, 44, 46, 56, 67, 82, 92, 96, 108], "convert": [15, 16], "convst": 109, "convstclk": [111, 126], "convstsysmon": 109, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 58, 87, 155, 156, 167], "cor": [41, 54, 78, 90, 106, 120, 135], "cor1": [54, 67, 120, 135], "cor2": [54, 67], "core": [12, 34, 36, 44, 55, 87, 90, 91, 92, 104, 117, 120, 135, 145, 165, 167], "corner": [41, 44, 54, 55, 56, 58, 67, 78, 87, 90, 91, 92, 144, 152], "correct": 96, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 46, 47, 53, 55, 58, 65, 81, 82, 83, 87, 91, 96, 104, 108, 117, 122, 132, 137, 144, 147, 156, 167], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 46, 58, 81, 87, 104, 117, 132, 144, 157, 158, 159, 160, 161, 162], "cout": [46, 82, 153], "coutmux": [60, 112, 127, 140], "coutmuxslice1": 60, "cover": [104, 117, 132, 144, 147, 167], "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 158, 165], "cpl_timeout_disable_support": [138, 148], "cpl_timeout_ranges_support": [138, 148], "cpld": [0, 12, 34, 36, 165, 167], "cpmc440clk": 124, "cpmc440timerclock": 124, "cpmdcrclk": 124, "cpmdma0llclk": 124, "cpmdma1llclk": 124, "cpmdma2llclk": 124, "cpmdma3llclk": 124, "cpmfcmclk": 124, "cpminterconnectclk": 124, "cpmmcclk": 124, "cpmppcmplbclk": 124, "cpmppcs0plbclk": 124, "cpmppcs1plbclk": 124, "crammod": [60, 112, 127, 140], "crc": [39, 48, 49, 62, 84, 101, 114, 151], "crc32_0": [118, 119], "crc32_1": [118, 119], "crc32_2": [118, 119], "crc32_3": [118, 119], "crc_end_of_pkt": [88, 89], "crc_format": [88, 89], "crc_init": [118, 119], "crc_start_of_pkt": [88, 89], "crcclk": [118, 119], "crcclkgtp_dual": 118, "crcclkgtx_dual": 119, "creat": [55, 87, 91, 104, 117], "create_edg": [98, 111, 128, 141], "create_edgebufgctrl0": 98, "create_edgebufgctrl1": 98, "create_edgebufgctrl10": 98, "create_edgebufgctrl11": 98, "create_edgebufgctrl12": 98, "create_edgebufgctrl13": 98, "create_edgebufgctrl14": 98, "create_edgebufgctrl15": 98, "create_edgebufgctrl16": 98, "create_edgebufgctrl17": 98, "create_edgebufgctrl18": 98, "create_edgebufgctrl19": 98, "create_edgebufgctrl2": 98, "create_edgebufgctrl20": 98, "create_edgebufgctrl21": 98, "create_edgebufgctrl22": 98, "create_edgebufgctrl23": 98, "create_edgebufgctrl24": 98, "create_edgebufgctrl25": 98, "create_edgebufgctrl26": 98, "create_edgebufgctrl27": 98, "create_edgebufgctrl28": 98, "create_edgebufgctrl29": 98, "create_edgebufgctrl3": 98, "create_edgebufgctrl30": 98, "create_edgebufgctrl31": 98, "create_edgebufgctrl4": 98, "create_edgebufgctrl5": 98, "create_edgebufgctrl6": 98, "create_edgebufgctrl7": 98, "create_edgebufgctrl8": 98, "create_edgebufgctrl9": 98, "creg": [53, 65, 103, 115, 130, 143], "cregdsp": [53, 65], "cregdsp0": [115, 130], "cregdsp1": 130, "crm_core_clk_freq_500": 149, "crm_core_clk_freq_500pcie3": 149, "crm_module_rst": [138, 148], "crm_user_clk_freq": 149, "crmcoreclk": 123, "crmcoreclkdlo": 123, "crmcoreclkpci": 123, "crmcoreclkrxo": 123, "crmcoreclkrxopci": 123, "crmcoreclktxo": 123, "crmcoreclktxopci": 123, "crmuserclk": 123, "crmuserclkrxo": 123, "crmuserclktxo": 123, "cross": [58, 91, 132, 144], "cs144": [20, 21, 34, 159, 165], "cs280": [24, 25, 34, 160, 165], "cs48": [26, 27, 28, 30, 31, 34, 157, 158, 165], "cs_b": [108, 122], "csi_b": [137, 147], "cso2pin": [50, 63], "cso_b": [122, 137, 147], "cspin": [98, 111, 126], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [41, 54, 67, 78, 90, 106, 120, 135], "ctl1": 135, "ctlgo": [51, 52, 64, 86, 102], "ctlgo001": 55, "ctlgodcm": 86, "ctlmode": [51, 52, 64, 86], "ctlmode011": 55, "ctlmodedcm": 86, "ctlosc1": [51, 52, 64, 86, 102], "ctlosc1001": 55, "ctlosc1dcm": [86, 102], "ctlosc2": [51, 52, 64, 86, 102], "ctlosc2001": 55, "ctlosc2dcm": [86, 102], "ctlsel0": [51, 52, 64, 86, 102], "ctlsel0011": 55, "ctlsel0dcm": 86, "ctlsel1": [51, 52, 64, 86, 102], "ctlsel1101": 55, "ctlsel1dcm": [86, 102], "ctlsel2": [51, 52, 64, 86, 102], "ctlsel2100": 55, "ctlsel2dcm": [86, 102], "ctr": 14, "ctrl0": [121, 136, 146], "ctrl00001": [136, 146], "ctrl1": [121, 136, 146], "ctrl10010": [136, 146], "ctrl2": 121, "ctrl3": 121, "ctt": 79, "ctt001100010": 79, "ctt01011": 79, "ctt0111": 79, "curious": [12, 34], "current": [35, 46, 82], "cut": [56, 58, 117, 144], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [60, 112, 127, 140], "cx0100": [112, 127, 140], "cx1": [60, 112], "cx10": [127, 140], "cx1010": 60, "cxt": 132, "cy0": 73, "cy0111": 60, "cy0f": [37, 46, 82, 99], "cy0g": [37, 46, 82, 99], "cy1010": [60, 112, 127, 140], "cy110": 112, "cycl": [35, 81, 96], "cycle_limit_sel": 105, "cyinit": [37, 46, 60, 73, 82, 99, 112, 127, 140], "cyinitslice0": [73, 99, 112, 127, 140], "cyinitslice1": [37, 46, 60, 73, 112, 127, 140], "cyinitslice2": 99, "cyinitslice3": [37, 46], "cyself": [37, 46, 73, 82], "cyselfslice0": 73, "cyselfslice1": [37, 46, 73], "cyselfslice3": [37, 46], "cyselg": [37, 46, 73, 82], "cyselgslice0": [73, 82], "cyselgslice1": [37, 46, 73, 82], "cyselgslice3": [37, 46], "d": [14, 36, 81, 96, 108, 122, 137, 147, 167], "d0": [130, 143], "d01": 108, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162, 167], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 143, 158, 159, 160, 161, 162], "d100001": 122, "d1001": 108, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d15": [3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d16": [3, 6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d17": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d18": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d19": [6, 7, 22, 23, 24, 25, 130, 143, 160, 161, 162], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d20": [6, 7, 22, 23, 24, 130, 143, 161, 162], "d21": [6, 7, 22, 23, 130, 143, 161, 162], "d22": [6, 7, 22, 23, 130, 143, 161, 162], "d23": [22, 23, 130, 143], "d24": [22, 23, 130, 143], "d25": [22, 23], "d26": [22, 23], "d2ologic0": 108, "d2ologic1": 108, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d3iob0": [108, 122], "d3iob1": [108, 122], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d4iob0": 108, "d4iob1": 108, "d4ologic0": 122, "d4ologic1": 122, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 108, 122, 130, 143, 159, 160, 161, 162], "d5ffinit": [127, 140], "d5ffinitslice0": [127, 140], "d5ffmux": [127, 140], "d5ffsr": [127, 140], "d5ffsrinit": 60, "d5ffsrinitslice0": 60, "d5ffsrslice1": 127, "d5ologic0": [108, 122], "d5ologic1": [108, 122], "d5q0": 60, "d5q0100": [60, 127, 140], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 108, 122, 130, 143, 157, 158, 159, 160, 161, 162], "d6iob0": 122, "d6iob1": 122, "d6lut": [60, 112, 127, 140], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 130, 143, 157, 158, 159, 160, 161, 162], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 130, 143, 158, 159, 160, 161, 162], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 130, 143, 159, 160, 161, 162], "d_in": [108, 122], "d_out_busi": 122, "daddr0": 102, "daddr1": 102, "daddr1dcm": 102, "daddr2": 102, "daddr2dcm": 102, "daddr3": 102, "daddr4": 102, "daddr4dcm": 102, "daddr5": 102, "daddr5dcm": 102, "daddr6": 102, "daddr6dcm": 102, "data": [10, 12, 14, 17, 32, 35, 37, 42, 45, 46, 53, 54, 55, 58, 59, 65, 72, 81, 82, 87, 90, 91, 96, 99, 104, 106, 108, 117, 120, 122, 132, 144, 151, 155, 156, 163, 167], "data0": [42, 55, 91], "data00001000001": 91, "data00001000100": 91, "data00mux": 55, "data1": [42, 55, 91], "data10": [42, 55], "data10001000010": 91, "data10001001000": 91, "data101mux": 55, "data10mux": 55, "data11": [42, 55], "data110mux": 55, "data11mux": 55, "data12": [42, 55], "data13": [42, 55], "data130mux": 55, "data131mux": 55, "data14": [42, 55], "data140mux": 55, "data15": [42, 55], "data16": [42, 55], "data160mux": 55, "data17": [42, 55], "data170mux": 55, "data171mux": 55, "data18": [42, 55], "data180mux": 55, "data181mux": 55, "data19": [42, 55], "data190mux": 55, "data2": [42, 55, 91], "data20": [42, 55], "data20001000100": 91, "data20001010000": 91, "data20mux": 55, "data21": [42, 55], "data210mux": 55, "data21mux": 55, "data22": [42, 55], "data220mux": 55, "data221mux": 55, "data23": [42, 55], "data24": [42, 55], "data240mux": 55, "data25": [42, 55], "data250mux": 55, "data251mux": 55, "data26": [42, 55], "data261mux": 55, "data27": [42, 55], "data270mux": 55, "data28": [42, 55], "data29": [42, 55], "data290mux": 55, "data3": [42, 55, 91], "data30": [42, 55], "data30001001000": 91, "data30001100000": 91, "data300mux": 55, "data301mux": 55, "data30mux": 55, "data31": [42, 55], "data4": [42, 55, 91], "data40001000001": 91, "data40001000010": 91, "data40001000100": 91, "data5": [42, 55, 91], "data50001000010": 91, "data50001000100": 91, "data50001001000": 91, "data50mux": 55, "data51mux": 55, "data6": [42, 55, 91], "data60001000100": 91, "data60001001000": 91, "data60001010000": 91, "data60mux": 55, "data7": [42, 55, 91], "data70001001000": 91, "data70001010000": 91, "data70001100000": 91, "data8": [42, 55], "data80mux": 55, "data9": [42, 55], "data90mux": 55, "data91mux": 55, "data_l": [110, 125, 139], "data_r": [61, 108, 122], "data_u": [110, 125, 139], "data_width": [108, 122], "data_width_": 81, "data_width_a": [45, 59, 81], "data_width_b": [45, 59, 81], "databas": [11, 15, 16, 33, 35, 36, 155, 164, 166, 167], "datain": 122, "datain1000": 122, "datainilogic0": 122, "datainilogic1": 122, "dataint": 151, "datap": [45, 59, 81, 96], "datap_l": [110, 125, 139], "datap_u": [110, 125, 139], "datareg": 13, "datastream": [17, 156], "dbl": [38, 42, 47, 55, 68, 83, 91, 107, 121, 136, 146, 150, 153], "dbl0001010000": 121, "dbl0001100000": 121, "dbl0010010000": 121, "dbl0010100000": 121, "dbl0100010000": 121, "dbl0100100000": 121, "dbl1000010000": 121, "dbl1000100000": 121, "dcdr_filter": 105, "dci": [56, 91, 92, 100, 108, 113, 122, 137, 147], "dci0": [50, 85], "dci00": 50, "dci1": [50, 85], "dci11": 50, "dci_altvr": 85, "dci_altvrmisc": 85, "dci_clk_en": [50, 85, 98, 111, 126], "dci_clk_enablemisc": 85, "dci_misc": [108, 122, 137], "dci_mod": [57, 93, 108, 122, 137], "dci_osc_sel": 50, "dci_t": [108, 122, 137], "dci_test_mux": 50, "dcireset": [98, 111, 126], "dcireset0": 50, "dcireset1": 50, "dciupdatemode_asrequir": [57, 93, 108, 122, 137], "dciupdatemode_asrequirediob0": [57, 93], "dciupdatemode_asrequirediob1": [57, 93], "dciupdatemode_asrequirediob2": 93, "dciupdatemode_asrequirediob3": [57, 93], "dciupdatemode_asrequirediob4": [57, 93], "dciupdatemode_asrequirediob5": 93, "dclk": [66, 111, 118, 119, 126, 133, 134], "dclk0": 102, "dclk_divid_2": 109, "dclk_miss": 109, "dclkgth": 133, "dclkgtp": 66, "dclkgtp_dual": 118, "dclkgtx_dual": 119, "dclksysmon": 111, "dcm": [54, 56, 81, 87, 90, 102, 104, 106, 108], "dcm0": 64, "dcm0000000000001": 64, "dcm000001000000111111": 100, "dcm0_clk00000000110": 64, "dcm0_clk1800000010110": 64, "dcm0_clk2700000011110": 64, "dcm0_clk2x0000100010": 64, "dcm0_clk2x1800000101010": 64, "dcm0_clk900000001110": 64, "dcm0_clkdv0000110010": 64, "dcm0_clkfb011": 71, "dcm0_clkfx0000111010": 64, "dcm0_clkfx1800000100110": 64, "dcm0_clkin010": 71, "dcm0_concur0000101110": 64, "dcm1": 64, "dcm100001000001011111": 100, "dcm1000010001000011111": 100, "dcm1100010010000011111": 100, "dcm1200100000000111111": 100, "dcm1300100000001011111": 100, "dcm1400100000010011111": 100, "dcm1500100000100011111": 100, "dcm1600100001000011111": 100, "dcm1700100010000011111": 100, "dcm1801000000000111111": 100, "dcm1901000000001011111": 100, "dcm1_clk00001000000": 64, "dcm1_clk1800101000000": 64, "dcm1_clk2700111000000": 64, "dcm1_clk2x1000000000": 64, "dcm1_clk2x1801010000000": 64, "dcm1_clk900011000000": 64, "dcm1_clkdv1100000000": 64, "dcm1_clkfb001": 71, "dcm1_clkfx1110000000": 64, "dcm1_clkfx1801001000000": 64, "dcm1_clkin000": 71, "dcm1_concur1011000000": 64, "dcm200001000010011111": 100, "dcm2001000000010011111": 100, "dcm2101000000100011111": 100, "dcm2201000001000011111": 100, "dcm2301000010000011111": 100, "dcm300001000100011111": 100, "dcm400001001000011111": 100, "dcm500001010000011111": 100, "dcm600010000000111111": 100, "dcm700010000001011111": 100, "dcm800010000010011111": 100, "dcm900010000100011111": 100, "dcm_bufpll": 67, "dcm_clkdv_clkfx_align": 102, "dcm_clkdv_clkfx_alignmentdcm": 102, "dcm_enabl": 50, "dcm_ext_fb_en": 102, "dcm_ext_fb_endcm": 102, "dcm_lock_high": 102, "dcm_lock_highdcm": 102, "dcm_out100": 47, "dcm_out_l0100": [47, 83], "dcm_out_l01000": 47, "dcm_out_r1000": [47, 83], "dcm_out_r10000": 47, "dcm_performance_mod": 102, "dcm_performance_modedcm": 102, "dcm_pulse_width_correction_high": 102, "dcm_pulse_width_correction_low": 102, "dcm_shutdown": [48, 84, 101], "dcm_unused_taps_powerdown": 102, "dcm_unused_taps_powerdowndcm": 102, "dcm_vbg_pd": 102, "dcm_vbg_sel": 102, "dcm_vref_sourc": 102, "dcm_vreg": 52, "dcm_vreg_en": 102, "dcm_vreg_enabledcm": 102, "dcm_vreg_phase_margin": 102, "dcmclk": 91, "dcmclk0": 91, "dcmclk00001000001": 91, "dcmclk0int": 91, "dcmclk1": 91, "dcmclk10001000010": 91, "dcmclk1int": 91, "dcmclk2": 91, "dcmclk20001000001": 91, "dcmclk2int": 91, "dcmclk3": 91, "dcmclk30001000010": 91, "dcmclk3int": 91, "dcr_autolock_en": 124, "dcr_test": 124, "dcremacclk": 116, "dcy0": [60, 112, 127, 140], "dcy0slice0": [112, 127, 140], "dcy0slice1": [60, 140], "dd1": 34, "ddel_a": [45, 59, 81], "ddel_a_default": 45, "ddel_b": [45, 59, 81], "ddel_b_default": 45, "ddr": [56, 92], "ddr0": [108, 122], "ddr00100": 122, "ddr01": 69, "ddr01100": 122, "ddr1": 61, "ddr210": 69, "ddr300": 69, "ddr_clk_edg": [108, 122], "deal": [58, 87, 91], "dec_mcomma_detect": [88, 89, 105, 134], "dec_mcomma_detect_0": [66, 118, 119], "dec_mcomma_detect_0gtp": 66, "dec_mcomma_detect_0gtp_du": 118, "dec_mcomma_detect_0gtx_du": 119, "dec_mcomma_detect_1": [66, 118, 119], "dec_mcomma_detect_1gtp": 66, "dec_mcomma_detect_1gtp_du": 118, "dec_mcomma_detect_1gtx_du": 119, "dec_mcomma_detectgt11a": 105, "dec_mcomma_detectgt11b": 105, "dec_mcomma_detectgtx0": 134, "dec_mcomma_detectgtx1": 134, "dec_mcomma_detectgtx2": 134, "dec_mcomma_detectgtx3": 134, "dec_pcomma_detect": [88, 89, 105, 134], "dec_pcomma_detect_0": [66, 118, 119], "dec_pcomma_detect_0gtp": 66, "dec_pcomma_detect_0gtp_du": 118, "dec_pcomma_detect_0gtx_du": 119, "dec_pcomma_detect_1": [66, 118, 119], "dec_pcomma_detect_1gtp": 66, "dec_pcomma_detect_1gtp_du": 118, "dec_pcomma_detect_1gtx_du": 119, "dec_pcomma_detectgt11a": 105, "dec_pcomma_detectgt11b": 105, "dec_pcomma_detectgtx0": 134, "dec_pcomma_detectgtx1": 134, "dec_pcomma_detectgtx2": 134, "dec_pcomma_detectgtx3": 134, "dec_valid_comma_onli": [88, 89, 105, 134], "dec_valid_comma_only_0": [66, 118, 119], "dec_valid_comma_only_0gtp": 66, "dec_valid_comma_only_0gtp_du": 118, "dec_valid_comma_only_0gtx_du": 119, "dec_valid_comma_only_1": [66, 118, 119], "dec_valid_comma_only_1gtp": 66, "dec_valid_comma_only_1gtp_du": 118, "dec_valid_comma_only_1gtx_du": 119, "dec_valid_comma_onlygt11a": 105, "dec_valid_comma_onlygt11b": 105, "dec_valid_comma_onlygtx0": 134, "dec_valid_comma_onlygtx1": 134, "dec_valid_comma_onlygtx2": 134, "dec_valid_comma_onlygtx3": 134, "decod": 96, "dedic": [12, 14, 34, 36, 45, 46, 56, 58, 81, 82, 87, 91, 92, 96, 104, 108, 117, 122, 137, 144, 147, 156, 165, 167], "def": [15, 16], "default": [17, 35, 54], "default00": 108, "default10": 122, "default_idelay_valu": 122, "default_only1011": 113, "defin": 167, "definit": 147, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [157, 158, 159, 160, 161, 162], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 157, 158, 159, 160, 161, 162], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_pt_ut": [157, 158, 159, 160, 161, 162], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "delai": [14, 44, 47, 74, 78, 117, 120, 132, 135, 144, 145], "delay0": 153, "delay_common": 57, "delay_commoniob0": 57, "delay_commoniob1": 57, "delay_commoniob2": 57, "delay_commoniob3": 57, "delay_commoniob4": 57, "delay_commoniob5": 57, "delay_commoniob6": 57, "delay_en": 43, "delay_src": 122, "delay_vari": 57, "delay_variableiob0": 57, "delay_variableiob1": 57, "delay_variableiob3": 57, "delay_variableiob4": 57, "delaychain_osc": 122, "delayed_write0": 139, "delayed_write00": 125, "delaymux": 153, "delaymuxint": 153, "delaymuxiob2": 153, "delaymuxiob3": 153, "depend": [17, 35, 36, 55, 58, 81, 91, 104, 108, 117, 132, 144, 147, 156, 166, 167], "deriv": [12, 34, 56, 92, 165, 167], "describ": [17, 35, 46, 47, 58, 81, 82, 83, 100, 113, 128, 141, 142, 156], "descript": [45, 99], "design": [12, 36, 58, 165, 167], "deskew_adjust": [54, 64, 90, 102], "despit": 144, "destin": 36, "detail": [35, 58, 87, 96, 166], "determin": [12, 34, 35, 46, 82, 167], "dev_cap2_ari_forwarding_support": 148, "dev_cap2_ari_forwarding_supportedpci": 148, "dev_cap2_atomicop32_completer_support": 148, "dev_cap2_atomicop32_completer_supportedpci": 148, "dev_cap2_atomicop64_completer_support": 148, "dev_cap2_atomicop_routing_support": 148, "dev_cap2_cas128_completer_support": 148, "dev_cap2_cas128_completer_supportedpci": 148, "dev_cap2_endend_tlp_prefix_support": 148, "dev_cap2_endend_tlp_prefix_supportedpci": 148, "dev_cap2_extended_fmt_field_support": 148, "dev_cap2_ltr_mechanism_support": 148, "dev_cap2_ltr_mechanism_supportedpci": 148, "dev_cap2_max_endend_tlp_prefix": 148, "dev_cap2_no_ro_enabled_prpr_pass": 148, "dev_cap2_tph_completer_support": 148, "dev_cap_enable_slot_pwr_limit_scal": [138, 148], "dev_cap_enable_slot_pwr_limit_scalepci": [138, 148], "dev_cap_enable_slot_pwr_limit_valu": [138, 148], "dev_cap_endpoint_l0s_lat": [70, 138, 148], "dev_cap_endpoint_l1_lat": [70, 138, 148], "dev_cap_ext_tag_support": [70, 138, 148], "dev_cap_ext_tag_supportedpci": [138, 148], "dev_cap_function_level_reset_cap": [138, 148], "dev_cap_max_payload_support": [70, 138, 148], "dev_cap_phantom_functions_support": [70, 138, 148], "dev_cap_role_based_error": [70, 138, 148], "dev_cap_rsvd_14_12": [138, 148], "dev_cap_rsvd_17_16": [138, 148], "dev_cap_rsvd_31_29": [138, 148], "dev_control_aux_power_support": [138, 148], "dev_control_aux_power_supportedpci": 148, "dev_control_ext_tag_default": 148, "devic": [11, 15, 16, 33, 35, 44, 45, 46, 47, 54, 55, 81, 82, 83, 90, 91, 106, 108, 120, 122, 135, 137, 145, 147, 155, 164, 166], "device_id": 138, "devicebram": 45, "devicecapabilityendpointl0slat": 123, "devicecapabilityendpointl1lat": 123, "devicedcm": [51, 52, 86], "deviceid": 123, "deviceiodelai": 122, "deviceserialnumb": 123, "devicevalu": [47, 61], "devoid": 144, "df": [51, 86], "dfb001": 61, "dfb010": 61, "dfe_cal_tim": [119, 134], "dfe_cfg": 134, "dfe_cfg_0": 119, "dfe_cfg_1": 119, "dfe_drp_en": 134, "dfe_drp_engtx0": 134, "dfe_drp_engtx1": 134, "dfe_drp_engtx2": 134, "dfe_drp_engtx3": 134, "dfe_train_ctrl_lane0": 133, "dfe_train_ctrl_lane1": 133, "dfe_train_ctrl_lane2": 133, "dfe_train_ctrl_lane3": 133, "dff": [14, 36, 167], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 155], "dff1": 15, "dff_latch": 127, "dff_latchslice0": 127, "dffce": 167, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 155], "dffinit": [112, 127, 140], "dffinitslice0": [112, 127, 140], "dffmux": [60, 112, 127, 140], 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125, 139], "init_b_u": [110, 125, 139], "init_bitslipcnt": [108, 122], "init_c": [108, 122], "init_loadcnt": [108, 122], "init_out": [98, 111, 128, 141], "init_outbufgctrl0": 98, "init_outbufgctrl1": 98, "init_outbufgctrl10": 98, "init_outbufgctrl11": 98, "init_outbufgctrl12": 98, "init_outbufgctrl13": 98, "init_outbufgctrl14": 98, "init_outbufgctrl15": 98, "init_outbufgctrl16": 98, "init_outbufgctrl17": 98, "init_outbufgctrl18": 98, "init_outbufgctrl19": 98, "init_outbufgctrl2": 98, "init_outbufgctrl20": 98, "init_outbufgctrl21": 98, "init_outbufgctrl22": 98, "init_outbufgctrl23": 98, "init_outbufgctrl24": 98, "init_outbufgctrl25": 98, "init_outbufgctrl26": 98, "init_outbufgctrl27": 98, "init_outbufgctrl28": 98, "init_outbufgctrl29": 98, "init_outbufgctrl3": 98, "init_outbufgctrl30": 98, "init_outbufgctrl31": 98, "init_outbufgctrl4": 98, "init_outbufgctrl5": 98, "init_outbufgctrl6": 98, "init_outbufgctrl7": 98, "init_outbufgctrl8": 98, "init_outbufgctrl9": 98, "init_rank1_parti": [108, 122], "init_rank2": [108, 122], "init_rank3": [108, 122], "init_signals_error": 129, "init_skip": 62, "init_xx": [81, 96], "initi": [14, 35, 36, 46, 73, 81, 82, 96, 167], "initp_xx": [81, 96], "initpin": [98, 111, 126], "initpinmisc": 111, "initx": 73, "initxint": 73, "initxslice1": 73, "inityint": 73, "inmode0": [130, 143], "inmode1": [130, 143], "inmode2": [130, 143], "inmode3": [130, 143], "inmode4": [130, 143], "inmodereg": [130, 143], "inner": [58, 87, 104, 117, 132, 137], "input": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 33, 34, 35, 41, 44, 46, 54, 56, 78, 81, 82, 90, 92, 96, 104, 106, 117, 120, 132, 135, 144, 145, 151, 152, 155, 156, 164, 165, 166], "inputtest": 55, "insan": 82, "insert": 144, "insid": [55, 91], "instanc": 87, "instanti": [55, 91], "instead": [12, 14, 16, 34, 35, 36, 42, 56, 58, 81, 91, 108, 144, 147, 165, 167], "instruct": [11, 33, 36, 56, 92, 164], "int": [17, 37, 38, 45, 46, 47, 53, 58, 61, 65, 68, 72, 73, 74, 76, 77, 79, 80, 81, 82, 83, 87, 96, 99, 104, 107, 117, 121, 132, 136, 144, 146, 150, 151, 153, 154, 156], "int0": [45, 142], "int00": [130, 143], "int000": 139, "int00001": 47, "int0001": [47, 83, 153], "int001": 47, "int01": 38, "int1": [51, 52, 64, 77, 86, 102], "int_clk00001": 109, "int_imux00000": 109, "integ": [17, 156], "interconnect": [14, 36, 37, 41, 44, 45, 46, 54, 56, 58, 67, 78, 81, 82, 87, 90, 92, 96, 104, 106, 117, 120, 132, 135, 137, 144, 145, 167], "interconnect_imask": 124, "interconnect_tmpl_sel": 124, "intereconnect": 144, "interfac": [11, 33, 41, 52, 54, 58, 64, 67, 87, 90, 106, 164], "interface_typ": [108, 122], "interface_typeilogic0": 108, "interface_typeilogic1": 108, "interfer": [46, 82], "interleav": 16, "intern": [36, 56, 92, 96, 144, 166], "internal1": 129, "internal_vref": [113, 137], "internalclk0": [49, 62], "interpos": 144, "interpret": 17, "interrupt": [35, 91], "interrupt_pin": [138, 148], "interrupt_stat_auto": 148, "interrupt_stat_autopci": 148, "interruptpin": 123, "intersect": [38, 47, 55, 58, 87, 104, 117, 132, 144], "intest": [13, 35, 166], "intf": [104, 107, 117, 120, 132, 135, 144, 145], "intosc00": 76, "intro": [41, 54, 67, 78, 106, 120, 135, 145, 152], "introduc": [58, 96, 144], "introduct": [11, 33, 44, 54, 90, 164], "inv": [15, 36, 37, 42, 43, 46, 47, 51, 52, 55, 57, 59, 60, 61, 64, 65, 66, 69, 71, 72, 73, 74, 76, 77, 79, 80, 83, 86, 91, 93, 96, 97, 98, 99, 102, 103, 107, 108, 109, 110, 111, 112, 115, 116, 118, 119, 122, 123, 124, 125, 126, 127, 128, 130, 133, 134, 139, 140, 141, 143, 150, 151, 153], "inv0010": 153, "inv1000": 153, "inv22": [15, 16], "invalid": [15, 16, 35], "invers": [17, 34, 36, 57, 59, 79, 82, 93, 108, 122, 137, 156, 167], "invert": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 17, 23, 36, 37, 38, 39, 40, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52, 55, 57, 59, 60, 61, 62, 63, 64, 65, 66, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 91, 93, 96, 97, 98, 99, 100, 101, 102, 103, 105, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 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"out_r7": [47, 83], "out_r7gclkc": 83, "out_t0": [38, 47, 83], "out_t1": [38, 47, 83], "out_t1gclkh": [38, 47, 83], "out_t2": [38, 47, 83], "out_t2gclkh": [38, 47, 83], "out_t3": [38, 47, 83], "out_t3gclkh": [38, 47, 83], "out_t4": [38, 47, 83], "out_t4gclkh": [38, 47, 83], "out_t5": [38, 47, 83], "out_t5gclkh": [38, 47, 83], "out_t6": [38, 47, 83], "out_t6gclkh": [38, 47, 83], "out_t7": [38, 47, 83], "out_t7gclkh": [38, 47, 83], "out_u0": [128, 141], "out_u1": [128, 141], "out_u10": 141, "out_u11": 141, "out_u2": [128, 141], "out_u3": [128, 141], "out_u4": [128, 141], "out_u5": [128, 141], "out_u6": [128, 141], "out_u7": [128, 141], "out_u8": 141, "out_u9": 141, "out_uim": 36, "outbus0": 83, "outbus1": 83, "outbus2": 83, "outbus3": 83, "outbus4": 83, "outbus4dcmconn": 83, "outbus5": 83, "outbus5dcmconn": 83, "outbus6": 83, "outbus7": 83, "outd_clkout0": 61, "outd_clkout1": 61, "outd_lock": 61, "outer": [132, 137], "outgo": 91, "outl_clkout0": 61, "outl_clkout1": 61, "outl_locked0": 61, "outl_locked1": 61, "output": [11, 12, 33, 34, 35, 41, 44, 54, 56, 78, 81, 90, 92, 96, 104, 106, 117, 120, 132, 135, 144, 145, 152, 164, 166], "output0001": [57, 93], "output001": [108, 122, 137], "output_delai": [122, 137], "output_delayiob0": 122, "output_delayiob1": 122, "output_diff": [57, 93], "output_diff_group": 57, "output_dis": 142, "output_disableout_fifo": 142, "output_en": [57, 93, 108, 122, 137], "output_half0010": [57, 93], "output_half010": [108, 122, 137], "output_ht_25101000000001100011": 122, "output_ht_25101100000011001110": 137, "output_ldt_2501100110": 108, "output_lvds_2501101010": 108, "output_lvds_25100000000001100011": 122, "output_lvds_25100100000000011110": 137, "output_lvds_25_dci01000000": 108, "output_lvdsext_25110000000001000101": 122, "output_lvdsext_25110100000000011110": 137, "output_lvdsext_2511100010": 108, "output_lvdsext_25_dci11000000": 108, "output_misc": [57, 79, 93, 108, 122, 137], "output_misciob0": 57, "output_misciob1": [57, 93], "output_misciob2": 57, "output_misciob3": 57, "output_misciob4": [57, 93], "output_rsds_2501101010": 108, "output_rsds_25100000000001100011": 122, "output_rsds_25100100000000011110": 137, "output_ulvds_2501100110": 108, "outputs_act": 151, "outr_clkout0": 61, "outr_clkout1": 61, "outr_locked0": 61, "outr_locked1": 61, "outsel0": 97, "outsel1": 97, "outsel2": 97, "outsid": [35, 91], "outu_clkout0": 61, "outu_clkout1": 61, "outu_lock": 61, "over": [15, 16, 35, 46, 81, 82, 132, 144], "over_temperatur": 109, "over_temperature_delai": 109, "over_temperature_off": 109, "overlap": [35, 37, 46], "overrid": [17, 35, 166], "overriden": [17, 35, 166, 167], "oversample_mod": [118, 119], "overtemp_powerdown": [114, 129], "overview": [11, 33, 164], "own": [17, 36, 91, 147, 167], "p": [15, 16, 36, 81, 144, 147, 155, 167], "p0": 96, "p0cmdclk": 69, "p0cmden": 69, "p0rdclk": 69, "p0rden": 69, "p0wrclk": 69, "p0wren": 69, "p1": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p10": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p100": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p101": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p102": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p103": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p104": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p105": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p106": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p107": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p108": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p109": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p11": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p110": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p111": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p112": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p113": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p114": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p115": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p116": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p117": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p120": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p121": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p122": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p123": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p124": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p125": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p126": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p127": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p128": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p129": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p13": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p130": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p131": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p132": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p133": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p134": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p135": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p136": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p137": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p138": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p139": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p14": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p140": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p141": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p142": [3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p143": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p144": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 159, 160, 161, 162], "p145": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p146": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p147": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p148": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p149": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p15": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p150": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p151": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p152": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p153": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p154": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p155": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p156": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p157": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p158": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p159": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p16": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p160": [3, 6, 7, 18, 19, 22, 23, 24, 25, 160, 161, 162], "p161": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p162": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p163": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p164": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p165": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p166": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p167": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p168": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p169": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p17": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p170": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p171": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p172": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p173": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p174": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p175": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p176": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p177": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p178": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p179": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p18": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p180": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p181": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p182": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p183": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p184": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p185": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p186": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p187": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p188": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p189": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p19": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p190": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p191": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p192": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p193": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p194": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p195": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p196": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p197": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p198": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p199": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p1cmdclk": 69, "p1cmden": 69, "p1rdclk": 69, "p1rden": 69, "p1wrclk": 69, "p1wren": 69, "p2": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p20": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p200": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p201": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p202": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p203": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p204": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p205": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p206": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p207": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p208": [3, 6, 7, 22, 23, 24, 25, 160, 161, 162], "p209": [3, 6, 7], "p21": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p210": [3, 6, 7], "p211": [3, 6, 7], "p212": [3, 6, 7], "p213": [3, 6, 7], "p214": [3, 6, 7], "p215": [3, 6, 7], "p216": [3, 6, 7], "p217": [3, 6, 7], "p218": [3, 6, 7], "p219": [3, 6, 7], "p22": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p220": [3, 6, 7], "p221": [3, 6, 7], "p222": [3, 6, 7], "p223": [6, 7], "p224": [6, 7], "p225": [6, 7], "p226": [6, 7], "p227": [6, 7], "p228": [6, 7], "p229": [6, 7], "p23": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p230": [6, 7], "p231": [6, 7], "p232": [6, 7], "p233": [6, 7], "p234": [6, 7], "p235": [6, 7], "p236": [6, 7], "p237": [6, 7], "p238": [6, 7], "p239": [6, 7], "p24": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p240": [6, 7], "p241": [6, 7], "p242": [6, 7], "p243": [6, 7], "p244": [6, 7], "p245": [6, 7], "p246": [6, 7], "p247": [6, 7], "p248": [6, 7], "p249": [6, 7], "p25": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p250": [6, 7], "p251": [6, 7], "p252": [6, 7], "p253": [6, 7], "p254": [6, 7], "p255": [6, 7], "p256": [6, 7], "p257": [6, 7], "p258": [6, 7], "p259": [6, 7], "p26": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p260": [6, 7], "p261": [6, 7], "p262": [6, 7], "p263": [6, 7], "p264": [6, 7], "p265": [6, 7], "p266": [6, 7], "p267": [6, 7], "p268": [6, 7], "p269": [6, 7], "p27": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p270": [6, 7], "p271": [6, 7], "p272": [6, 7], "p273": [6, 7], "p274": [6, 7], "p275": [6, 7], "p276": [6, 7], "p277": [6, 7], "p278": [6, 7], "p279": [6, 7], "p28": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p280": [6, 7], "p281": [6, 7], "p282": [6, 7], "p283": [6, 7], "p284": [6, 7], "p285": [6, 7], "p286": [6, 7], "p287": [6, 7], "p288": [6, 7], "p289": 7, "p29": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p290": 7, "p291": 7, "p292": 7, "p293": 7, "p294": 7, "p295": 7, "p296": 7, "p297": 7, "p298": 7, "p299": 7, "p2clk": 69, "p2cmdclk": 69, "p2cmden": 69, "p2en": 69, "p3": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 96, 157, 158, 159, 160, 161, 162], "p30": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p300": 7, "p301": 7, "p302": 7, "p303": 7, "p304": 7, "p305": 7, "p306": 7, "p307": 7, "p308": 7, "p309": 7, "p31": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p310": 7, "p311": 7, "p312": 7, "p313": 7, "p314": 7, "p315": 7, "p316": 7, "p317": 7, "p318": 7, "p319": 7, "p32": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p3clk": 69, "p3cmdclk": 69, "p3cmden": 69, "p3en": 69, "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p4clk": 69, "p4cmdclk": 69, "p4cmden": 69, "p4en": 69, "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p5clk": 69, "p5cmdclk": 69, "p5cmden": 69, "p5en": 69, "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 158, 159, 160, 161, 162], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 157, 158, 159, 160, 161, 162], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 158, 159, 160, 161, 162], "p_d": 81, "packag": [11, 17, 33, 36, 56, 144, 147, 156, 164, 166], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 55, 91, 108, 122, 137, 147, 156, 165, 167], "pair": [17, 58, 82, 96, 104, 108, 122, 137, 144, 147, 156], "parallel": [16, 108, 122, 137, 147], "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 156, 157, 158, 159, 160, 161, 162], "pariti": [81, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 46, 58, 82, 96, 108, 122, 144, 157, 158, 159, 160, 161, 162, 164, 166], "partial": [34, 81, 96, 166], "particip": 36, "particular": [17, 156], "particularli": 46, "pass": [35, 55, 58, 72, 73, 79, 91, 132, 144, 150, 151, 153, 154], "pass0": [64, 71], "pass00000000": 102, "pass00000000000001": 113, "pass00000000001": 113, "pass00000001": 113, "pass10000100000011111": 100, "pass100001000011111": 100, "passthrough": 91, "patdet1": 115, "path": [36, 81], "pattern": [87, 115, 130, 143], "pattern0": [115, 130, 143], "pbbaseptr": 123, "pbcapabilitydw0basepow": 123, "pbcapabilitydw0datascal": 123, "pbcapabilitydw0pmst": 123, "pbcapabilitydw0pmsubst": 123, "pbcapabilitydw0powerrail": 123, "pbcapabilitydw0typ": 123, "pbcapabilitydw1basepow": 123, "pbcapabilitydw1datascal": 123, "pbcapabilitydw1pmst": 123, "pbcapabilitydw1pmsubst": 123, "pbcapabilitydw1powerrail": 123, "pbcapabilitydw1typ": 123, "pbcapabilitydw2basepow": 123, "pbcapabilitydw2datascal": 123, "pbcapabilitydw2pmst": 123, "pbcapabilitydw2pmsubst": 123, "pbcapabilitydw2powerrail": 123, "pbcapabilitydw2typ": 123, "pbcapabilitydw3basepow": 123, "pbcapabilitydw3datascal": 123, "pbcapabilitydw3pmst": 123, "pbcapabilitydw3pmsubst": 123, "pbcapabilitydw3powerrail": 123, "pbcapabilitydw3typ": 123, "pbcapabilitynextptr": 123, "pbcapabilitysystemalloc": 123, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 157, 158, 165], "pc84": [18, 29, 34], "pci": [44, 56, 58, 67, 78, 90, 91, 92, 120, 135, 145], "pci000": 91, "pci100": 91, "pci33_3": [57, 79], "pci33_30": [57, 93], "pci33_300": [57, 93], "pci33_30000": 93, "pci33_300000": [57, 93], "pci33_3000000": 122, "pci33_3000000000000": 122, "pci33_3000001": 57, "pci33_300010011": 108, "pci33_300111": 79, "pci33_30100101011": 93, "pci33_30100101101": 108, "pci33_30101001101": 122, "pci33_3010101110": 93, "pci33_30111": 79, "pci33_301111100": 57, "pci33_310": 108, "pci33_3100001101": 79, "pci33_3100010010": 79, "pci33_3100110": 57, "pci33_311001001": 57, "pci33_3111110": 57, "pci33_5": 79, "pci33_501111": 79, "pci33_5101011001": 79, "pci66_3": [57, 79], "pci66_30": [57, 93], "pci66_300": [57, 93], "pci66_300000": [57, 93], "pci66_3000000": 122, "pci66_3000000000000": 122, "pci66_3000001": 57, "pci66_300010011": 108, "pci66_30011": 93, "pci66_300111": 79, "pci66_30100101011": 93, "pci66_30100101101": 108, "pci66_30101001101": 122, "pci66_3010101110": 93, "pci66_30111": 79, "pci66_301111100": 57, "pci66_310": 108, "pci66_3100001101": 79, "pci66_3100001110": 79, "pci66_3100110": 57, "pci66_311001001": 57, "pci66_3111110": 57, "pci_c": 76, "pci_ce010001": 79, "pci_ce_delai": 67, "pci_cemisc": 76, "pci_clamp": 57, "pci_clampiob0": 57, "pci_clampiob1": 57, "pci_clampiob3": 57, "pci_clampiob4": 57, "pci_delai": 80, "pci_express_mod": 134, "pci_express_mode_0": [66, 118, 119], "pci_express_mode_1": [66, 118, 119], "pci_express_mode_1gtp": 66, "pci_input": 57, "pci_inputiob1": 57, "pci_inputiob2": 57, "pci_inputiob3": 57, "pci_inputiob4": 57, "pci_inputiob5": 57, "pcice10": 57, "pcice_mux": 57, "pcie": [70, 117, 123, 132, 138, 144, 148], "pcie0": [66, 118, 119], "pcie2": 144, "pcie3": [144, 149], "pcie_base_ptr": [138, 148], "pcie_cap_capability_id": [138, 148], "pcie_cap_capability_vers": [70, 138, 148], "pcie_cap_device_port_typ": [70, 138, 148], "pcie_cap_int_msg_num": [70, 138], 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"yes0": 69, "ymux": 46, "you": [35, 147], "your": 35, "yq": [46, 55, 82, 91], "yq0011110": 73, "yq0111111": 73, "z": 35, "zclk_div2": 85, "zd1_by1": [51, 86], "zd1_by1dcm": 51, "zd2_by1": [51, 86], "zd2_by1dcm": 51, "zero": 167, "zia": [14, 164, 166], "zia_gclk": [155, 167], "zia_gclk0_en": [157, 158, 159, 160, 161, 162], "zia_gclk1_en": [157, 158, 159, 160, 161, 162], "zia_gclk2_en": [157, 158, 159, 160, 161, 162], "zia_gclk3_en": [157, 158, 159, 160, 161, 162], "zynq": 144, "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "FPGAcore", "General interconnect", "Input / Output", "Xilinx FPGAs", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers \u2014 Spartan 3, Spartan 3E", "Configuration registers \u2014 Spartan 3A and 3A DSP", "Corners", "Digital Clock Managers \u2014 Spartan 3", "Digital Clock Managers \u2014 Spartan 3E, 3A", "DSP", "Spartan 3", "General interconnect", "Introduction", "Input / Output", "Device geometry", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Digital clock manager", "DSP", "Multi-gigabit transceivers", "Spartan 6", "General interconnect", "Memory Controller Block", "PCI Express", "Phase-locked loop", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Delay Locked Loop", "Virtex", "Input/Output", "PCI Logic", "Block RAM \u2014 Virtex 2, Spartan 3", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Digital Clock Managers", "Device geometry", "Multi-gigabit transceivers \u2014 Virtex 2 Pro", "Multi-gigabit transceivers \u2014 Virtex 2 Pro X", "Virtex 2", "General interconnect", "Introduction", "Input / Output", "Hard PCI logic", "Hard PowerPC 405 cores", "Block RAM", "Clock Companion Modules", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Digital Clock Managers", "DSP", "Device geometry", "Multi-gigabit transceivers", "Virtex 4", "General Interconnect", "Input/Output", "System monitor", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "DSP", "Ethernet MACs", "Device geometry", "GTP transceivers", "GTX transceivers", "Virtex 5", "Interconnect", "Input/Output", "PCI Express cores", "PowerPC cores", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "DSP", "Ethernet MACs", "Device geometry", "GTH transceivers", "GTX transceivers", "Virtex 6", "Interconnect", "Input/Output", "PCI Express cores", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Clock management tile", "DSP", "Device geometry", "Virtex 7", "Interconnect", "Input/Output", "PCI Express Gen2 cores", "PCI Express Gen3 cores", "Configurable Logic Block", "Corners", "XC5200", "Input/Output", "Splitters", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [47, 91], "03": 55, "1": [46, 82], "12": [49, 55, 62], "128": 82, "16": [46, 82], "2": [81, 85, 88, 89, 90, 93], "3": [46, 48, 50, 51, 54, 57, 81], "32": [46, 82], "34": 62, "3a": [49, 50, 52, 57, 58, 81], "3e": [48, 50, 52, 57, 58, 81], "4": [46, 106], "405": 95, "5": 120, "6": [67, 135], "64": [46, 82], "7": 145, "AND": 15, "The": [38, 47, 81, 83], "aim": 14, "alt": 93, "attribut": 47, "b": [43, 57, 79, 83, 88, 89, 93, 153], "b0": 91, "b1": 57, "b123": 91, "b2": [57, 93], "b3": 57, "b4": 57, "backbon": [55, 91], "bank": [14, 58, 87, 108, 122, 137, 147], "bclkpad": 91, "bel": 81, "bit": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 156, 157, 158, 159, 160, 161, 162], "bitstream": [1, 15, 16, 37, 38, 42, 45, 46, 47, 53, 55, 58, 59, 60, 61, 64, 65, 66, 68, 69, 70, 71, 72, 73, 81, 82, 83, 87, 88, 89, 91, 96, 97, 98, 99, 102, 103, 104, 105, 107, 108, 109, 110, 111, 112, 115, 116, 117, 118, 119, 121, 122, 123, 124, 125, 126, 127, 130, 131, 132, 133, 134, 136, 137, 138, 139, 140, 143, 144, 146, 149, 150, 155], "bl": [52, 76, 151], "blank": 35, "block": [37, 45, 46, 59, 60, 69, 72, 73, 81, 82, 96, 99, 110, 112, 125, 127, 139, 140, 150], "bond": [17, 156], "bot": [77, 83], "bottom": [38, 47, 61, 72, 83, 91], "boundari": [13, 35, 166], "br": [52, 76, 151], "bram": [45, 55, 58, 81, 91, 146], "bu": [36, 83], "buffer": [14, 15, 36, 43, 57, 58, 79, 87, 93, 167], "buse": 82, "carri": [46, 82], "cclk_freq": [49, 62], "center": [38, 47, 98, 104, 111, 117, 126, 132, 144], "check": 35, "clb": [42, 55, 91], "clbll": [112, 127, 140], "clblm": [112, 127, 140], "clexl": 60, "clexm": 60, "clk": 93, "clk_b": [91, 93], "clk_bali_rebuf": 141, "clk_bufg": 141, "clk_bufg_rebuf": 141, "clk_cmt_b": 113, "clk_cmt_t": 113, "clk_dcm_b": 100, "clk_dcm_t": 100, "clk_hrow": [100, 113, 141], "clk_iob_b": [100, 113], "clk_iob_t": [100, 113], "clk_mgt_b": 113, "clk_mgt_t": 113, "clk_t": [91, 93], "clk_term_b": 100, "clk_term_t": 100, "clkb": [38, 47, 55, 74, 83, 154], "clkb_2dll": 74, "clkb_4dll": 74, "clkc": [38, 47, 61], "clkc_50a": 47, "clkh": 154, "clkl": [47, 80, 154], "clkpad": 91, "clkr": [47, 80, 154], "clkt": [38, 47, 55, 74, 83, 154], "clkt_2dll": 74, "clkt_4dll": 74, "clkv": [74, 154], "clkv_bram_bot": 74, "clkv_bram_top": 74, "clock": [14, 38, 47, 51, 52, 58, 61, 64, 74, 83, 86, 87, 91, 97, 100, 102, 113, 128, 141, 142], "cmt": [68, 113, 142], "cmt_bufg_bot": 128, "cmt_bufg_top": 128, "cmt_fifo": 142, "cnr": [76, 91, 151], "column": [58, 72, 104, 117, 132, 144, 167], "combin": 0, "companion": 97, "configur": [14, 36, 37, 39, 46, 48, 49, 60, 62, 73, 75, 82, 84, 98, 99, 101, 111, 112, 114, 126, 127, 129, 140, 144, 150, 167], "content": [0, 10, 11, 32, 33, 41, 44, 54, 67, 78, 90, 106, 120, 135, 145, 152, 163, 164], "control": [69, 167], "coolrunn": 11, "cor": [39, 48, 75, 84, 101, 114, 129], "cor1": [49, 62, 114, 129], "cor2": [49, 62], "core": [95, 123, 124, 138, 148, 149], "corner": [40, 50, 63, 76, 85, 151], "cpld": [11, 33, 164], "ctl": [39, 48, 49, 62, 75, 84, 101, 114, 129], "ctl1": 129, "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 50, 85, 100, 113, 157, 158, 159, 160, 161, 162], "databas": [10, 17, 32, 156, 163], "dcm": [51, 52, 55, 58, 83, 86, 91, 100], "dcm_bufpll": 61, "dcmconn": 83, "default": [45, 47], "delai": [77, 121, 136, 146], "deskew_adjust": [51, 52, 86], "devic": [10, 12, 14, 17, 32, 34, 36, 56, 58, 87, 92, 104, 117, 132, 144, 156, 163, 165, 167], "digit": [51, 52, 64, 86, 102], "distribut": [38, 47, 83], "divid": 14, "dll": 77, "dllp": 77, "dr": 35, "dsp": [49, 53, 55, 58, 65, 103, 115, 130, 143], "dual": [46, 82], "dummi": 55, "e": [79, 91], "ecc": [96, 104, 117, 132, 144], "enabl": 15, "enter": 35, "eras": 35, "ethernet": [116, 131], "exit": 35, "export": 36, "express": [70, 123, 138, 144, 148, 149], "eye_mask": 62, "fb": [14, 15, 16, 36, 155, 167], "fc": [38, 39, 40, 42, 43], "fclk": 167, "fifo": 96, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 44, "fpgacor": 41, "frequenc": 35, "function": [108, 122, 137, 147], "fuse": [15, 16, 35, 36, 155], "gate": [14, 36], "gclkc": 83, "gclkh": [38, 47, 83], "gclkv": 74, "gclkvc": [38, 47], "gclkvm": [38, 47], "gen2": 148, "gen3": 149, "gener": [42, 49, 55, 58, 62, 68, 87, 91, 104, 107, 117, 132, 144], "general5": 62, "geometri": [58, 87, 104, 117, 132, 144], "gigabit": [66, 88, 89, 105], "gigabit10": 89, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 155, 157, 158, 159, 160, 161, 162], "gt": 91, "gth": 133, "gtp": [118, 144], "gtx": [119, 134, 144], "hard": [94, 95], "hc_opt": [49, 62], "hclk": [61, 100, 113, 128, 141], "hclk_center": 100, "hclk_center_above_cfg": 100, "hclk_cmt": 113, "hclk_cmt_ioi": 113, "hclk_dcm": 100, "hclk_dcmiob": 100, "hclk_iobdcm": 100, "hclk_ioi": [113, 137], "hclk_ioi_botcen": 113, "hclk_ioi_cent": 113, "hclk_ioi_cmt": 113, "hclk_ioi_topcen": 113, "hclk_iois_dci": 100, "hclk_iois_lvd": 100, "hclk_mgt": 100, "hclk_row": 61, "hclk_term_l": 100, "hclk_term_r": 100, "hole": [87, 91, 104, 117, 144], "horizont": 58, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 122, 137, 147, 157, 158, 159, 160, 161, 162], "ibuf": 23, "idcod": [35, 166], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 155, 157, 158, 159, 160, 161, 162], "input": [14, 15, 16, 36, 43, 55, 57, 79, 91, 93, 108, 122, 137, 147, 153, 167], "instruct": [13, 35, 166], "int": [42, 55, 91], "interconnect": [38, 42, 47, 55, 61, 68, 74, 83, 91, 100, 107, 113, 121, 128, 136, 141, 146], "interfac": [13, 35, 43, 55, 57, 68, 91, 93, 107, 166], "intf": [55, 68, 91, 121, 136, 146], "introduct": [12, 34, 56, 92, 165], "io": [58, 79, 87, 100, 113, 137, 144, 153], "iob": [2, 3, 6, 7, 14, 43, 57, 79, 93, 100, 113, 155, 167], "ioi": [42, 43, 55, 57, 68, 91, 93], "ir": [13, 35, 166], "isp": [13, 35, 166], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 155, 156, 157, 158, 159, 160, 161, 162], "jtag": [13, 35, 166], "keeper": 36, "l": [43, 79, 93, 153], "l1": [57, 93], "l2": [57, 93], "l3": 57, "l4": 57, "lb": 52, "left": [40, 47, 50, 61, 63, 72, 85], "level": [17, 156], "line": 55, "ll": [40, 50, 85], "llh": 55, "llv": 55, "local": 167, "lock": [71, 77], "logic": [37, 46, 60, 73, 80, 82, 87, 94, 99, 112, 127, 140, 150], "long": 55, "loop": [71, 77], "lower": [40, 50, 63, 85], "lr": [40, 50, 55, 57, 85], "lt": 52, "lut": [46, 82], "lut2": 167, "mac": [116, 131], "macrocel": [14, 15, 16, 36, 155, 167], "manag": [51, 52, 64, 86, 102, 142], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 155, 157, 158, 159, 160, 161, 162], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "memori": 69, "mgt": [100, 113], "middl": [72, 144], "misc": [14, 36, 167], "mode": [35, 49, 62, 96], "modul": 97, "monitor": 109, "mult": 81, "multi": [66, 88, 89, 105], "multiplex": [46, 55, 82, 91], "mux": [100, 113], "n": [47, 91], "network": [14, 36, 167], "node": [100, 113], "normal": 68, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 57, 79, 85, 93, 100, 108, 113, 122, 137, 147, 157, 158, 159, 160, 161, 162], "option": [45, 47], "output": [14, 36, 43, 46, 55, 57, 79, 82, 83, 91, 93, 108, 122, 137, 147, 153, 167], "overview": [14, 36, 167], "packag": [12, 34, 165], "part": [17, 156], "pci": [70, 80, 87, 94, 123, 138, 144, 148, 149], "pci_ce_delai": 61, "pcie_l": 148, "pcie_r": 148, "pcilogics": 61, "per": [15, 16], "phase": 71, "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 157, 158, 159, 160, 161, 162, 165], "placement": 144, "pll_bufpll_b": 61, "pll_bufpll_out0": 61, "pll_bufpll_out1": 61, "pll_bufpll_t": 61, "pma_spe": 89, "pmviob": 128, "port": [46, 82], "powerdown": [49, 62], "powerpc": [87, 91, 95, 104, 117, 124], "ppc": 91, "primari": 58, "primit": [55, 91], "pro": [85, 88, 89, 93], "process": 144, "product": [14, 15, 16, 36, 82, 155, 167], "program": [13, 35, 166], "project": 0, "protect": 35, "pt": 36, "pu_gt": [49, 62], "pu_gw": [49, 62], "pull": 36, "r": [43, 79, 93, 153], "r1": [57, 93], "r2": [57, 93], "r3": 57, "r4": 57, "ram": [45, 46, 59, 72, 81, 82, 96, 110, 125, 139], "randor": [37, 46], "randor_init": [37, 46], "rb": 52, "read": 35, "regist": [13, 14, 35, 39, 46, 48, 49, 62, 75, 82, 84, 101, 114, 129, 166, 167], "repeat": [100, 113], "reserved_andor": [37, 46], "right": [40, 47, 50, 61, 63, 72, 85, 144], "row": [38, 47, 58, 83, 87, 100, 167], "rt": 52, "s3": [38, 39, 45, 47, 48, 50, 51, 55, 57], "s3a": [45, 47, 49, 50, 55, 57], "s3adsp": [45, 55], "s3e": [45, 47, 48, 50, 52, 55, 57], "scan": [13, 35, 166], "schema": [17, 156], "secondari": [38, 47, 58], "sequenc": [13, 35, 166], "seu_opt": [49, 62], "shift": [46, 82], "side": 72, "singl": [46, 82], "sourc": [38, 47, 83], "spartan": [46, 48, 49, 50, 51, 52, 54, 57, 58, 67, 81], "special": [108, 122, 137, 147], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 156, 157, 158, 159, 160, 161, 162], "spine": [38, 47, 58, 83, 87, 91, 100, 104, 113, 117], "splitter": [55, 154], "standard": [100, 113], "structur": [1, 14, 15, 16, 36, 58, 87, 104, 117, 132, 144, 155, 167], "sum": [14, 36, 82, 155, 167], "system": [109, 144], "t": [43, 57, 79, 83, 88, 89, 93, 153], "t0": 91, "t1": 57, "t123": 91, "t2": [57, 93], "t3": 57, "t4": 57, "tabl": [56, 71, 92], "tb": 55, "tbuf": 82, "tclkpad": 91, "term": [14, 15, 16, 36, 91, 155, 167], "termin": [55, 91, 100], "testmod": [62, 129], "tile": [17, 38, 42, 43, 47, 55, 61, 68, 83, 91, 107, 142, 156], "timer": [62, 114, 129], "tl": [52, 76, 151], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 46, 47, 48, 49, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 69, 71, 75, 78, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 98, 100, 101, 104, 105, 106, 107, 111, 112, 113, 114, 117, 118, 119, 120, 121, 126, 127, 128, 129, 132, 133, 134, 135, 136, 140, 141, 142, 144, 145, 146, 147, 152, 166, 167], "top": [17, 38, 47, 61, 72, 77, 83, 91, 156], "tr": [52, 76, 151], "transceiv": [66, 88, 89, 105, 118, 119, 133, 134, 144], "trim": 129, "tristat": 82, "uim": [15, 23, 36], "ul": [40, 50, 85], "uni": 47, "univers": 167, "unk1c": 129, "up": 36, "upper": [40, 50, 63, 85], "ur": [40, 50, 85], "v": 79, "v2": [83, 85, 86, 91, 93], "v2p": [83, 85, 86, 91, 93], "v2px": 83, "valu": [45, 89], "ve": 79, "vertic": 58, "virtex": [46, 78, 79, 81, 85, 88, 89, 90, 93, 106, 120, 135, 145], "w": 91, "wide": [46, 82], "wire": 15, "without": [2, 3, 6, 7, 155], "write": 35, "x": [46, 82, 89], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc5200": 152, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 157, "xcr3064xl": 158, "xcr3128xl": 159, "xcr3256xl": 160, "xcr3384xl": 161, "xcr3512xl": 162, "xilinx": [11, 33, 44, 164], "xor": [14, 36], "xpla3": 164, "xv": [16, 35, 36], "zia": 167}}) \ No newline at end of file diff --git a/xilinx/index.html b/xilinx/index.html index 5df5fca2..9c1c7327 100644 --- a/xilinx/index.html +++ b/xilinx/index.html @@ -222,6 +222,8 @@

Xilinx FPGAsBlock RAM
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • diff --git a/xilinx/spartan6/clock.html b/xilinx/spartan6/clock.html index bbc3ca21..54198644 100644 --- a/xilinx/spartan6/clock.html +++ b/xilinx/spartan6/clock.html @@ -5774,9 +5774,43 @@

    Bitstream — P

    PCI_CE_DELAY

    +
    DeviceValue
    xa6slx100TAP9 +
    xa6slx16TAP6 +
    xa6slx25TAP6 +
    xa6slx25tTAP6 +
    xa6slx4TAP6 +
    xa6slx45TAP6 +
    xa6slx45tTAP6 +
    xa6slx75TAP9 +
    xa6slx75tTAP9 +
    xa6slx9TAP6 +
    xc6slx100TAP9 +
    xc6slx100lTAP9 +
    xc6slx100tTAP9 +
    xc6slx150TAP9 +
    xc6slx150lTAP9 +
    xc6slx150tTAP9 +
    xc6slx16TAP6 +
    xc6slx16lTAP6 +
    xc6slx25TAP6 +
    xc6slx25lTAP6
    xc6slx25tTAP6 +
    xc6slx4TAP6 +
    xc6slx45TAP6 +
    xc6slx45lTAP6 +
    xc6slx45tTAP6 +
    xc6slx4lTAP6 +
    xc6slx75TAP9 +
    xc6slx75lTAP9
    xc6slx75tTAP9
    xc6slx9TAP6 +
    xc6slx9lTAP6 +
    xq6slx150TAP9 +
    xq6slx150lTAP9 +
    xq6slx150tTAP9 +
    xq6slx75TAP9 +
    xq6slx75lTAP9 +
    xq6slx75tTAP9
    diff --git a/xilinx/virtex5/clock.html b/xilinx/virtex5/clock.html index eb7bcf7a..2a668b2e 100644 --- a/xilinx/virtex5/clock.html +++ b/xilinx/virtex5/clock.html @@ -2196,31 +2196,31 @@

    CLK_CMT_B0 ---- 1 -CLK_CMT:MUX.MUXBUS0[0]-CLK_CMT:MUX.MUXBUS1[0]- +CLK_CMT:MUX.MUXBUS0[12]-CLK_CMT:MUX.MUXBUS1[12]- 2 --CLK_CMT:MUX.MUXBUS0[6]-CLK_CMT:MUX.MUXBUS1[6] +-CLK_CMT:MUX.MUXBUS0[10]-CLK_CMT:MUX.MUXBUS1[10] 3 -CLK_CMT:MUX.MUXBUS0[1]-CLK_CMT:MUX.MUXBUS1[1]- +CLK_CMT:MUX.MUXBUS0[8]-CLK_CMT:MUX.MUXBUS1[8]- 4 --CLK_CMT:MUX.MUXBUS0[7]-CLK_CMT:MUX.MUXBUS1[7] +-CLK_CMT:MUX.MUXBUS0[6]-CLK_CMT:MUX.MUXBUS1[6] 5 -CLK_CMT:MUX.MUXBUS0[2]-CLK_CMT:MUX.MUXBUS1[2]- +CLK_CMT:MUX.MUXBUS0[11]-CLK_CMT:MUX.MUXBUS1[11]- 6 --CLK_CMT:MUX.MUXBUS0[8]-CLK_CMT:MUX.MUXBUS1[8] +-CLK_CMT:MUX.MUXBUS0[9]-CLK_CMT:MUX.MUXBUS1[9] 7 -CLK_CMT:MUX.MUXBUS0[3]CLK_CMT:MUX.MUXBUS0[9]CLK_CMT:MUX.MUXBUS1[3]CLK_CMT:MUX.MUXBUS1[9] +CLK_CMT:MUX.MUXBUS0[7]CLK_CMT:MUX.MUXBUS0[13]CLK_CMT:MUX.MUXBUS1[7]CLK_CMT:MUX.MUXBUS1[13] 8 -CLK_CMT:MUX.MUXBUS0[4]CLK_CMT:MUX.MUXBUS0[10]CLK_CMT:MUX.MUXBUS1[4]CLK_CMT:MUX.MUXBUS1[10] +CLK_CMT:MUX.MUXBUS0[3]CLK_CMT:MUX.MUXBUS0[4]CLK_CMT:MUX.MUXBUS1[3]CLK_CMT:MUX.MUXBUS1[4] 9 --CLK_CMT:MUX.MUXBUS0[11]-CLK_CMT:MUX.MUXBUS1[11] +-CLK_CMT:MUX.MUXBUS0[5]-CLK_CMT:MUX.MUXBUS1[5] 10 -CLK_CMT:MUX.MUXBUS0[5]CLK_CMT:MUX.MUXBUS0[12]CLK_CMT:MUX.MUXBUS1[5]CLK_CMT:MUX.MUXBUS1[12] +CLK_CMT:MUX.MUXBUS0[2]CLK_CMT:MUX.MUXBUS0[1]CLK_CMT:MUX.MUXBUS1[2]CLK_CMT:MUX.MUXBUS1[1] 11 ---- 12 ---- 13 --CLK_CMT:MUX.MUXBUS0[13]-CLK_CMT:MUX.MUXBUS1[13] +-CLK_CMT:MUX.MUXBUS0[0]-CLK_CMT:MUX.MUXBUS1[0] 14 ---- 15 @@ -2228,31 +2228,31 @@

    CLK_CMT_B16 ---- 17 -CLK_CMT:MUX.MUXBUS2[0]-CLK_CMT:MUX.MUXBUS3[0]- +CLK_CMT:MUX.MUXBUS2[12]-CLK_CMT:MUX.MUXBUS3[12]- 18 --CLK_CMT:MUX.MUXBUS2[6]-CLK_CMT:MUX.MUXBUS3[6] +-CLK_CMT:MUX.MUXBUS2[10]-CLK_CMT:MUX.MUXBUS3[10] 19 -CLK_CMT:MUX.MUXBUS2[1]-CLK_CMT:MUX.MUXBUS3[1]- +CLK_CMT:MUX.MUXBUS2[8]-CLK_CMT:MUX.MUXBUS3[8]- 20 --CLK_CMT:MUX.MUXBUS2[7]-CLK_CMT:MUX.MUXBUS3[7] +-CLK_CMT:MUX.MUXBUS2[6]-CLK_CMT:MUX.MUXBUS3[6] 21 -CLK_CMT:MUX.MUXBUS2[2]-CLK_CMT:MUX.MUXBUS3[2]- +CLK_CMT:MUX.MUXBUS2[11]-CLK_CMT:MUX.MUXBUS3[11]- 22 --CLK_CMT:MUX.MUXBUS2[8]-CLK_CMT:MUX.MUXBUS3[8] +-CLK_CMT:MUX.MUXBUS2[9]-CLK_CMT:MUX.MUXBUS3[9] 23 -CLK_CMT:MUX.MUXBUS2[3]CLK_CMT:MUX.MUXBUS2[9]CLK_CMT:MUX.MUXBUS3[3]CLK_CMT:MUX.MUXBUS3[9] +CLK_CMT:MUX.MUXBUS2[7]CLK_CMT:MUX.MUXBUS2[13]CLK_CMT:MUX.MUXBUS3[7]CLK_CMT:MUX.MUXBUS3[13] 24 -CLK_CMT:MUX.MUXBUS2[4]CLK_CMT:MUX.MUXBUS2[10]CLK_CMT:MUX.MUXBUS3[4]CLK_CMT:MUX.MUXBUS3[10] +CLK_CMT:MUX.MUXBUS2[3]CLK_CMT:MUX.MUXBUS2[4]CLK_CMT:MUX.MUXBUS3[3]CLK_CMT:MUX.MUXBUS3[4] 25 --CLK_CMT:MUX.MUXBUS2[11]-CLK_CMT:MUX.MUXBUS3[11] +-CLK_CMT:MUX.MUXBUS2[5]-CLK_CMT:MUX.MUXBUS3[5] 26 -CLK_CMT:MUX.MUXBUS2[5]CLK_CMT:MUX.MUXBUS2[12]CLK_CMT:MUX.MUXBUS3[5]CLK_CMT:MUX.MUXBUS3[12] +CLK_CMT:MUX.MUXBUS2[2]CLK_CMT:MUX.MUXBUS2[1]CLK_CMT:MUX.MUXBUS3[2]CLK_CMT:MUX.MUXBUS3[1] 27 ---- 28 ---- 29 --CLK_CMT:MUX.MUXBUS2[13]-CLK_CMT:MUX.MUXBUS3[13] +-CLK_CMT:MUX.MUXBUS2[0]-CLK_CMT:MUX.MUXBUS3[0] 30 ---- 31 @@ -2260,31 +2260,31 @@

    CLK_CMT_B32 ---- 33 -CLK_CMT:MUX.MUXBUS4[0]-CLK_CMT:MUX.MUXBUS5[0]- +CLK_CMT:MUX.MUXBUS4[12]-CLK_CMT:MUX.MUXBUS5[12]- 34 --CLK_CMT:MUX.MUXBUS4[6]-CLK_CMT:MUX.MUXBUS5[6] +-CLK_CMT:MUX.MUXBUS4[10]-CLK_CMT:MUX.MUXBUS5[10] 35 -CLK_CMT:MUX.MUXBUS4[1]-CLK_CMT:MUX.MUXBUS5[1]- +CLK_CMT:MUX.MUXBUS4[8]-CLK_CMT:MUX.MUXBUS5[8]- 36 --CLK_CMT:MUX.MUXBUS4[7]-CLK_CMT:MUX.MUXBUS5[7] +-CLK_CMT:MUX.MUXBUS4[6]-CLK_CMT:MUX.MUXBUS5[6] 37 -CLK_CMT:MUX.MUXBUS4[2]-CLK_CMT:MUX.MUXBUS5[2]- +CLK_CMT:MUX.MUXBUS4[11]-CLK_CMT:MUX.MUXBUS5[11]- 38 --CLK_CMT:MUX.MUXBUS4[8]-CLK_CMT:MUX.MUXBUS5[8] +-CLK_CMT:MUX.MUXBUS4[9]-CLK_CMT:MUX.MUXBUS5[9] 39 -CLK_CMT:MUX.MUXBUS4[3]CLK_CMT:MUX.MUXBUS4[9]CLK_CMT:MUX.MUXBUS5[3]CLK_CMT:MUX.MUXBUS5[9] +CLK_CMT:MUX.MUXBUS4[7]CLK_CMT:MUX.MUXBUS4[13]CLK_CMT:MUX.MUXBUS5[7]CLK_CMT:MUX.MUXBUS5[13] 40 -CLK_CMT:MUX.MUXBUS4[4]CLK_CMT:MUX.MUXBUS4[10]CLK_CMT:MUX.MUXBUS5[4]CLK_CMT:MUX.MUXBUS5[10] +CLK_CMT:MUX.MUXBUS4[3]CLK_CMT:MUX.MUXBUS4[4]CLK_CMT:MUX.MUXBUS5[3]CLK_CMT:MUX.MUXBUS5[4] 41 --CLK_CMT:MUX.MUXBUS4[11]-CLK_CMT:MUX.MUXBUS5[11] +-CLK_CMT:MUX.MUXBUS4[5]-CLK_CMT:MUX.MUXBUS5[5] 42 -CLK_CMT:MUX.MUXBUS4[5]CLK_CMT:MUX.MUXBUS4[12]CLK_CMT:MUX.MUXBUS5[5]CLK_CMT:MUX.MUXBUS5[12] +CLK_CMT:MUX.MUXBUS4[2]CLK_CMT:MUX.MUXBUS4[1]CLK_CMT:MUX.MUXBUS5[2]CLK_CMT:MUX.MUXBUS5[1] 43 ---- 44 ---- 45 --CLK_CMT:MUX.MUXBUS4[13]-CLK_CMT:MUX.MUXBUS5[13] +-CLK_CMT:MUX.MUXBUS4[0]-CLK_CMT:MUX.MUXBUS5[0] 46 ---- 47 @@ -2292,62 +2292,62 @@

    CLK_CMT_B48 ---- 49 -CLK_CMT:MUX.MUXBUS6[0]-CLK_CMT:MUX.MUXBUS7[0]- +CLK_CMT:MUX.MUXBUS6[12]-CLK_CMT:MUX.MUXBUS7[12]- 50 --CLK_CMT:MUX.MUXBUS6[6]-CLK_CMT:MUX.MUXBUS7[6] +-CLK_CMT:MUX.MUXBUS6[10]-CLK_CMT:MUX.MUXBUS7[10] 51 -CLK_CMT:MUX.MUXBUS6[1]-CLK_CMT:MUX.MUXBUS7[1]- +CLK_CMT:MUX.MUXBUS6[8]-CLK_CMT:MUX.MUXBUS7[8]- 52 --CLK_CMT:MUX.MUXBUS6[7]-CLK_CMT:MUX.MUXBUS7[7] +-CLK_CMT:MUX.MUXBUS6[6]-CLK_CMT:MUX.MUXBUS7[6] 53 -CLK_CMT:MUX.MUXBUS6[2]-CLK_CMT:MUX.MUXBUS7[2]- +CLK_CMT:MUX.MUXBUS6[11]-CLK_CMT:MUX.MUXBUS7[11]- 54 --CLK_CMT:MUX.MUXBUS6[8]-CLK_CMT:MUX.MUXBUS7[8] +-CLK_CMT:MUX.MUXBUS6[9]-CLK_CMT:MUX.MUXBUS7[9] 55 -CLK_CMT:MUX.MUXBUS6[3]CLK_CMT:MUX.MUXBUS6[9]CLK_CMT:MUX.MUXBUS7[3]CLK_CMT:MUX.MUXBUS7[9] +CLK_CMT:MUX.MUXBUS6[7]CLK_CMT:MUX.MUXBUS6[13]CLK_CMT:MUX.MUXBUS7[7]CLK_CMT:MUX.MUXBUS7[13] 56 -CLK_CMT:MUX.MUXBUS6[4]CLK_CMT:MUX.MUXBUS6[10]CLK_CMT:MUX.MUXBUS7[4]CLK_CMT:MUX.MUXBUS7[10] +CLK_CMT:MUX.MUXBUS6[3]CLK_CMT:MUX.MUXBUS6[4]CLK_CMT:MUX.MUXBUS7[3]CLK_CMT:MUX.MUXBUS7[4] 57 --CLK_CMT:MUX.MUXBUS6[11]-CLK_CMT:MUX.MUXBUS7[11] +-CLK_CMT:MUX.MUXBUS6[5]-CLK_CMT:MUX.MUXBUS7[5] 58 -CLK_CMT:MUX.MUXBUS6[5]CLK_CMT:MUX.MUXBUS6[12]CLK_CMT:MUX.MUXBUS7[5]CLK_CMT:MUX.MUXBUS7[12] +CLK_CMT:MUX.MUXBUS6[2]CLK_CMT:MUX.MUXBUS6[1]CLK_CMT:MUX.MUXBUS7[2]CLK_CMT:MUX.MUXBUS7[1] 59 ---- 60 ---- 61 --CLK_CMT:MUX.MUXBUS6[13]-CLK_CMT:MUX.MUXBUS7[13] +-CLK_CMT:MUX.MUXBUS6[0]-CLK_CMT:MUX.MUXBUS7[0] - + - + - + - + - + - + - + - + - + - + - + @@ -2355,31 +2355,31 @@

    CLK_CMT_B

    - + - + - + - + - + - + - + - + - + - + - + @@ -2387,31 +2387,31 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - + @@ -2419,62 +2419,62 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_B bittile 6
    RowColumn
    0123
    0 ----
    1CLK_CMT:MUX.MUXBUS8[0]-CLK_CMT:MUX.MUXBUS9[0]-
    CLK_CMT:MUX.MUXBUS8[12]-CLK_CMT:MUX.MUXBUS9[12]-
    2-CLK_CMT:MUX.MUXBUS8[6]-CLK_CMT:MUX.MUXBUS9[6]
    -CLK_CMT:MUX.MUXBUS8[10]-CLK_CMT:MUX.MUXBUS9[10]
    3CLK_CMT:MUX.MUXBUS8[1]-CLK_CMT:MUX.MUXBUS9[1]-
    CLK_CMT:MUX.MUXBUS8[8]-CLK_CMT:MUX.MUXBUS9[8]-
    4-CLK_CMT:MUX.MUXBUS8[7]-CLK_CMT:MUX.MUXBUS9[7]
    -CLK_CMT:MUX.MUXBUS8[6]-CLK_CMT:MUX.MUXBUS9[6]
    5CLK_CMT:MUX.MUXBUS8[2]-CLK_CMT:MUX.MUXBUS9[2]-
    CLK_CMT:MUX.MUXBUS8[11]-CLK_CMT:MUX.MUXBUS9[11]-
    6-CLK_CMT:MUX.MUXBUS8[8]-CLK_CMT:MUX.MUXBUS9[8]
    -CLK_CMT:MUX.MUXBUS8[9]-CLK_CMT:MUX.MUXBUS9[9]
    7CLK_CMT:MUX.MUXBUS8[3]CLK_CMT:MUX.MUXBUS8[9]CLK_CMT:MUX.MUXBUS9[3]CLK_CMT:MUX.MUXBUS9[9]
    CLK_CMT:MUX.MUXBUS8[7]CLK_CMT:MUX.MUXBUS8[13]CLK_CMT:MUX.MUXBUS9[7]CLK_CMT:MUX.MUXBUS9[13]
    8CLK_CMT:MUX.MUXBUS8[4]CLK_CMT:MUX.MUXBUS8[10]CLK_CMT:MUX.MUXBUS9[4]CLK_CMT:MUX.MUXBUS9[10]
    CLK_CMT:MUX.MUXBUS8[3]CLK_CMT:MUX.MUXBUS8[4]CLK_CMT:MUX.MUXBUS9[3]CLK_CMT:MUX.MUXBUS9[4]
    9-CLK_CMT:MUX.MUXBUS8[11]-CLK_CMT:MUX.MUXBUS9[11]
    -CLK_CMT:MUX.MUXBUS8[5]-CLK_CMT:MUX.MUXBUS9[5]
    10CLK_CMT:MUX.MUXBUS8[5]CLK_CMT:MUX.MUXBUS8[12]CLK_CMT:MUX.MUXBUS9[5]CLK_CMT:MUX.MUXBUS9[12]
    CLK_CMT:MUX.MUXBUS8[2]CLK_CMT:MUX.MUXBUS8[1]CLK_CMT:MUX.MUXBUS9[2]CLK_CMT:MUX.MUXBUS9[1]
    11 ----
    12 ----
    13-CLK_CMT:MUX.MUXBUS8[13]-CLK_CMT:MUX.MUXBUS9[13]
    -CLK_CMT:MUX.MUXBUS8[0]-CLK_CMT:MUX.MUXBUS9[0]
    14 ----
    1516 ----
    17CLK_CMT:MUX.MUXBUS10[0]-CLK_CMT:MUX.MUXBUS11[0]-
    CLK_CMT:MUX.MUXBUS10[12]-CLK_CMT:MUX.MUXBUS11[12]-
    18-CLK_CMT:MUX.MUXBUS10[6]-CLK_CMT:MUX.MUXBUS11[6]
    -CLK_CMT:MUX.MUXBUS10[10]-CLK_CMT:MUX.MUXBUS11[10]
    19CLK_CMT:MUX.MUXBUS10[1]-CLK_CMT:MUX.MUXBUS11[1]-
    CLK_CMT:MUX.MUXBUS10[8]-CLK_CMT:MUX.MUXBUS11[8]-
    20-CLK_CMT:MUX.MUXBUS10[7]-CLK_CMT:MUX.MUXBUS11[7]
    -CLK_CMT:MUX.MUXBUS10[6]-CLK_CMT:MUX.MUXBUS11[6]
    21CLK_CMT:MUX.MUXBUS10[2]-CLK_CMT:MUX.MUXBUS11[2]-
    CLK_CMT:MUX.MUXBUS10[11]-CLK_CMT:MUX.MUXBUS11[11]-
    22-CLK_CMT:MUX.MUXBUS10[8]-CLK_CMT:MUX.MUXBUS11[8]
    -CLK_CMT:MUX.MUXBUS10[9]-CLK_CMT:MUX.MUXBUS11[9]
    23CLK_CMT:MUX.MUXBUS10[3]CLK_CMT:MUX.MUXBUS10[9]CLK_CMT:MUX.MUXBUS11[3]CLK_CMT:MUX.MUXBUS11[9]
    CLK_CMT:MUX.MUXBUS10[7]CLK_CMT:MUX.MUXBUS10[13]CLK_CMT:MUX.MUXBUS11[7]CLK_CMT:MUX.MUXBUS11[13]
    24CLK_CMT:MUX.MUXBUS10[4]CLK_CMT:MUX.MUXBUS10[10]CLK_CMT:MUX.MUXBUS11[4]CLK_CMT:MUX.MUXBUS11[10]
    CLK_CMT:MUX.MUXBUS10[3]CLK_CMT:MUX.MUXBUS10[4]CLK_CMT:MUX.MUXBUS11[3]CLK_CMT:MUX.MUXBUS11[4]
    25-CLK_CMT:MUX.MUXBUS10[11]-CLK_CMT:MUX.MUXBUS11[11]
    -CLK_CMT:MUX.MUXBUS10[5]-CLK_CMT:MUX.MUXBUS11[5]
    26CLK_CMT:MUX.MUXBUS10[5]CLK_CMT:MUX.MUXBUS10[12]CLK_CMT:MUX.MUXBUS11[5]CLK_CMT:MUX.MUXBUS11[12]
    CLK_CMT:MUX.MUXBUS10[2]CLK_CMT:MUX.MUXBUS10[1]CLK_CMT:MUX.MUXBUS11[2]CLK_CMT:MUX.MUXBUS11[1]
    27 ----
    28 ----
    29-CLK_CMT:MUX.MUXBUS10[13]-CLK_CMT:MUX.MUXBUS11[13]
    -CLK_CMT:MUX.MUXBUS10[0]-CLK_CMT:MUX.MUXBUS11[0]
    30 ----
    3132 ----
    33CLK_CMT:MUX.MUXBUS12[0]-CLK_CMT:MUX.MUXBUS13[0]-
    CLK_CMT:MUX.MUXBUS12[12]-CLK_CMT:MUX.MUXBUS13[12]-
    34-CLK_CMT:MUX.MUXBUS12[6]-CLK_CMT:MUX.MUXBUS13[6]
    -CLK_CMT:MUX.MUXBUS12[10]-CLK_CMT:MUX.MUXBUS13[10]
    35CLK_CMT:MUX.MUXBUS12[1]-CLK_CMT:MUX.MUXBUS13[1]-
    CLK_CMT:MUX.MUXBUS12[8]-CLK_CMT:MUX.MUXBUS13[8]-
    36-CLK_CMT:MUX.MUXBUS12[7]-CLK_CMT:MUX.MUXBUS13[7]
    -CLK_CMT:MUX.MUXBUS12[6]-CLK_CMT:MUX.MUXBUS13[6]
    37CLK_CMT:MUX.MUXBUS12[2]-CLK_CMT:MUX.MUXBUS13[2]-
    CLK_CMT:MUX.MUXBUS12[11]-CLK_CMT:MUX.MUXBUS13[11]-
    38-CLK_CMT:MUX.MUXBUS12[8]-CLK_CMT:MUX.MUXBUS13[8]
    -CLK_CMT:MUX.MUXBUS12[9]-CLK_CMT:MUX.MUXBUS13[9]
    39CLK_CMT:MUX.MUXBUS12[3]CLK_CMT:MUX.MUXBUS12[9]CLK_CMT:MUX.MUXBUS13[3]CLK_CMT:MUX.MUXBUS13[9]
    CLK_CMT:MUX.MUXBUS12[7]CLK_CMT:MUX.MUXBUS12[13]CLK_CMT:MUX.MUXBUS13[7]CLK_CMT:MUX.MUXBUS13[13]
    40CLK_CMT:MUX.MUXBUS12[4]CLK_CMT:MUX.MUXBUS12[10]CLK_CMT:MUX.MUXBUS13[4]CLK_CMT:MUX.MUXBUS13[10]
    CLK_CMT:MUX.MUXBUS12[3]CLK_CMT:MUX.MUXBUS12[4]CLK_CMT:MUX.MUXBUS13[3]CLK_CMT:MUX.MUXBUS13[4]
    41-CLK_CMT:MUX.MUXBUS12[11]-CLK_CMT:MUX.MUXBUS13[11]
    -CLK_CMT:MUX.MUXBUS12[5]-CLK_CMT:MUX.MUXBUS13[5]
    42CLK_CMT:MUX.MUXBUS12[5]CLK_CMT:MUX.MUXBUS12[12]CLK_CMT:MUX.MUXBUS13[5]CLK_CMT:MUX.MUXBUS13[12]
    CLK_CMT:MUX.MUXBUS12[2]CLK_CMT:MUX.MUXBUS12[1]CLK_CMT:MUX.MUXBUS13[2]CLK_CMT:MUX.MUXBUS13[1]
    43 ----
    44 ----
    45-CLK_CMT:MUX.MUXBUS12[13]-CLK_CMT:MUX.MUXBUS13[13]
    -CLK_CMT:MUX.MUXBUS12[0]-CLK_CMT:MUX.MUXBUS13[0]
    46 ----
    4748 ----
    49CLK_CMT:MUX.MUXBUS14[0]-CLK_CMT:MUX.MUXBUS15[0]-
    CLK_CMT:MUX.MUXBUS14[12]-CLK_CMT:MUX.MUXBUS15[12]-
    50-CLK_CMT:MUX.MUXBUS14[6]-CLK_CMT:MUX.MUXBUS15[6]
    -CLK_CMT:MUX.MUXBUS14[10]-CLK_CMT:MUX.MUXBUS15[10]
    51CLK_CMT:MUX.MUXBUS14[1]-CLK_CMT:MUX.MUXBUS15[1]-
    CLK_CMT:MUX.MUXBUS14[8]-CLK_CMT:MUX.MUXBUS15[8]-
    52-CLK_CMT:MUX.MUXBUS14[7]-CLK_CMT:MUX.MUXBUS15[7]
    -CLK_CMT:MUX.MUXBUS14[6]-CLK_CMT:MUX.MUXBUS15[6]
    53CLK_CMT:MUX.MUXBUS14[2]-CLK_CMT:MUX.MUXBUS15[2]-
    CLK_CMT:MUX.MUXBUS14[11]-CLK_CMT:MUX.MUXBUS15[11]-
    54-CLK_CMT:MUX.MUXBUS14[8]-CLK_CMT:MUX.MUXBUS15[8]
    -CLK_CMT:MUX.MUXBUS14[9]-CLK_CMT:MUX.MUXBUS15[9]
    55CLK_CMT:MUX.MUXBUS14[3]CLK_CMT:MUX.MUXBUS14[9]CLK_CMT:MUX.MUXBUS15[3]CLK_CMT:MUX.MUXBUS15[9]
    CLK_CMT:MUX.MUXBUS14[7]CLK_CMT:MUX.MUXBUS14[13]CLK_CMT:MUX.MUXBUS15[7]CLK_CMT:MUX.MUXBUS15[13]
    56CLK_CMT:MUX.MUXBUS14[4]CLK_CMT:MUX.MUXBUS14[10]CLK_CMT:MUX.MUXBUS15[4]CLK_CMT:MUX.MUXBUS15[10]
    CLK_CMT:MUX.MUXBUS14[3]CLK_CMT:MUX.MUXBUS14[4]CLK_CMT:MUX.MUXBUS15[3]CLK_CMT:MUX.MUXBUS15[4]
    57-CLK_CMT:MUX.MUXBUS14[11]-CLK_CMT:MUX.MUXBUS15[11]
    -CLK_CMT:MUX.MUXBUS14[5]-CLK_CMT:MUX.MUXBUS15[5]
    58CLK_CMT:MUX.MUXBUS14[5]CLK_CMT:MUX.MUXBUS14[12]CLK_CMT:MUX.MUXBUS15[5]CLK_CMT:MUX.MUXBUS15[12]
    CLK_CMT:MUX.MUXBUS14[2]CLK_CMT:MUX.MUXBUS14[1]CLK_CMT:MUX.MUXBUS15[2]CLK_CMT:MUX.MUXBUS15[1]
    59 ----
    60 ----
    61-CLK_CMT:MUX.MUXBUS14[13]-CLK_CMT:MUX.MUXBUS15[13]
    -CLK_CMT:MUX.MUXBUS14[0]-CLK_CMT:MUX.MUXBUS15[0]
    - + - + - + - + - + - + - + - + - + - + - + @@ -2482,31 +2482,31 @@

    CLK_CMT_B

    - + - + - + - + - + - + - + - + - + - + - + @@ -2514,31 +2514,31 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - + @@ -2546,62 +2546,62 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_B bittile 7
    RowColumn
    0123
    0 ----
    1CLK_CMT:MUX.MUXBUS16[0]-CLK_CMT:MUX.MUXBUS17[0]-
    CLK_CMT:MUX.MUXBUS16[12]-CLK_CMT:MUX.MUXBUS17[12]-
    2-CLK_CMT:MUX.MUXBUS16[6]-CLK_CMT:MUX.MUXBUS17[6]
    -CLK_CMT:MUX.MUXBUS16[10]-CLK_CMT:MUX.MUXBUS17[10]
    3CLK_CMT:MUX.MUXBUS16[1]-CLK_CMT:MUX.MUXBUS17[1]-
    CLK_CMT:MUX.MUXBUS16[8]-CLK_CMT:MUX.MUXBUS17[8]-
    4-CLK_CMT:MUX.MUXBUS16[7]-CLK_CMT:MUX.MUXBUS17[7]
    -CLK_CMT:MUX.MUXBUS16[6]-CLK_CMT:MUX.MUXBUS17[6]
    5CLK_CMT:MUX.MUXBUS16[2]-CLK_CMT:MUX.MUXBUS17[2]-
    CLK_CMT:MUX.MUXBUS16[11]-CLK_CMT:MUX.MUXBUS17[11]-
    6-CLK_CMT:MUX.MUXBUS16[8]-CLK_CMT:MUX.MUXBUS17[8]
    -CLK_CMT:MUX.MUXBUS16[9]-CLK_CMT:MUX.MUXBUS17[9]
    7CLK_CMT:MUX.MUXBUS16[3]CLK_CMT:MUX.MUXBUS16[9]CLK_CMT:MUX.MUXBUS17[3]CLK_CMT:MUX.MUXBUS17[9]
    CLK_CMT:MUX.MUXBUS16[7]CLK_CMT:MUX.MUXBUS16[13]CLK_CMT:MUX.MUXBUS17[7]CLK_CMT:MUX.MUXBUS17[13]
    8CLK_CMT:MUX.MUXBUS16[4]CLK_CMT:MUX.MUXBUS16[10]CLK_CMT:MUX.MUXBUS17[4]CLK_CMT:MUX.MUXBUS17[10]
    CLK_CMT:MUX.MUXBUS16[3]CLK_CMT:MUX.MUXBUS16[4]CLK_CMT:MUX.MUXBUS17[3]CLK_CMT:MUX.MUXBUS17[4]
    9-CLK_CMT:MUX.MUXBUS16[11]-CLK_CMT:MUX.MUXBUS17[11]
    -CLK_CMT:MUX.MUXBUS16[5]-CLK_CMT:MUX.MUXBUS17[5]
    10CLK_CMT:MUX.MUXBUS16[5]CLK_CMT:MUX.MUXBUS16[12]CLK_CMT:MUX.MUXBUS17[5]CLK_CMT:MUX.MUXBUS17[12]
    CLK_CMT:MUX.MUXBUS16[2]CLK_CMT:MUX.MUXBUS16[1]CLK_CMT:MUX.MUXBUS17[2]CLK_CMT:MUX.MUXBUS17[1]
    11 ----
    12 ----
    13-CLK_CMT:MUX.MUXBUS16[13]-CLK_CMT:MUX.MUXBUS17[13]
    -CLK_CMT:MUX.MUXBUS16[0]-CLK_CMT:MUX.MUXBUS17[0]
    14 ----
    1516 ----
    17CLK_CMT:MUX.MUXBUS18[0]-CLK_CMT:MUX.MUXBUS19[0]-
    CLK_CMT:MUX.MUXBUS18[12]-CLK_CMT:MUX.MUXBUS19[12]-
    18-CLK_CMT:MUX.MUXBUS18[6]-CLK_CMT:MUX.MUXBUS19[6]
    -CLK_CMT:MUX.MUXBUS18[10]-CLK_CMT:MUX.MUXBUS19[10]
    19CLK_CMT:MUX.MUXBUS18[1]-CLK_CMT:MUX.MUXBUS19[1]-
    CLK_CMT:MUX.MUXBUS18[8]-CLK_CMT:MUX.MUXBUS19[8]-
    20-CLK_CMT:MUX.MUXBUS18[7]-CLK_CMT:MUX.MUXBUS19[7]
    -CLK_CMT:MUX.MUXBUS18[6]-CLK_CMT:MUX.MUXBUS19[6]
    21CLK_CMT:MUX.MUXBUS18[2]-CLK_CMT:MUX.MUXBUS19[2]-
    CLK_CMT:MUX.MUXBUS18[11]-CLK_CMT:MUX.MUXBUS19[11]-
    22-CLK_CMT:MUX.MUXBUS18[8]-CLK_CMT:MUX.MUXBUS19[8]
    -CLK_CMT:MUX.MUXBUS18[9]-CLK_CMT:MUX.MUXBUS19[9]
    23CLK_CMT:MUX.MUXBUS18[3]CLK_CMT:MUX.MUXBUS18[9]CLK_CMT:MUX.MUXBUS19[3]CLK_CMT:MUX.MUXBUS19[9]
    CLK_CMT:MUX.MUXBUS18[7]CLK_CMT:MUX.MUXBUS18[13]CLK_CMT:MUX.MUXBUS19[7]CLK_CMT:MUX.MUXBUS19[13]
    24CLK_CMT:MUX.MUXBUS18[4]CLK_CMT:MUX.MUXBUS18[10]CLK_CMT:MUX.MUXBUS19[4]CLK_CMT:MUX.MUXBUS19[10]
    CLK_CMT:MUX.MUXBUS18[3]CLK_CMT:MUX.MUXBUS18[4]CLK_CMT:MUX.MUXBUS19[3]CLK_CMT:MUX.MUXBUS19[4]
    25-CLK_CMT:MUX.MUXBUS18[11]-CLK_CMT:MUX.MUXBUS19[11]
    -CLK_CMT:MUX.MUXBUS18[5]-CLK_CMT:MUX.MUXBUS19[5]
    26CLK_CMT:MUX.MUXBUS18[5]CLK_CMT:MUX.MUXBUS18[12]CLK_CMT:MUX.MUXBUS19[5]CLK_CMT:MUX.MUXBUS19[12]
    CLK_CMT:MUX.MUXBUS18[2]CLK_CMT:MUX.MUXBUS18[1]CLK_CMT:MUX.MUXBUS19[2]CLK_CMT:MUX.MUXBUS19[1]
    27 ----
    28 ----
    29-CLK_CMT:MUX.MUXBUS18[13]-CLK_CMT:MUX.MUXBUS19[13]
    -CLK_CMT:MUX.MUXBUS18[0]-CLK_CMT:MUX.MUXBUS19[0]
    30 ----
    3132 ----
    33CLK_CMT:MUX.MUXBUS20[0]-CLK_CMT:MUX.MUXBUS21[0]-
    CLK_CMT:MUX.MUXBUS20[12]-CLK_CMT:MUX.MUXBUS21[12]-
    34-CLK_CMT:MUX.MUXBUS20[6]-CLK_CMT:MUX.MUXBUS21[6]
    -CLK_CMT:MUX.MUXBUS20[10]-CLK_CMT:MUX.MUXBUS21[10]
    35CLK_CMT:MUX.MUXBUS20[1]-CLK_CMT:MUX.MUXBUS21[1]-
    CLK_CMT:MUX.MUXBUS20[8]-CLK_CMT:MUX.MUXBUS21[8]-
    36-CLK_CMT:MUX.MUXBUS20[7]-CLK_CMT:MUX.MUXBUS21[7]
    -CLK_CMT:MUX.MUXBUS20[6]-CLK_CMT:MUX.MUXBUS21[6]
    37CLK_CMT:MUX.MUXBUS20[2]-CLK_CMT:MUX.MUXBUS21[2]-
    CLK_CMT:MUX.MUXBUS20[11]-CLK_CMT:MUX.MUXBUS21[11]-
    38-CLK_CMT:MUX.MUXBUS20[8]-CLK_CMT:MUX.MUXBUS21[8]
    -CLK_CMT:MUX.MUXBUS20[9]-CLK_CMT:MUX.MUXBUS21[9]
    39CLK_CMT:MUX.MUXBUS20[3]CLK_CMT:MUX.MUXBUS20[9]CLK_CMT:MUX.MUXBUS21[3]CLK_CMT:MUX.MUXBUS21[9]
    CLK_CMT:MUX.MUXBUS20[7]CLK_CMT:MUX.MUXBUS20[13]CLK_CMT:MUX.MUXBUS21[7]CLK_CMT:MUX.MUXBUS21[13]
    40CLK_CMT:MUX.MUXBUS20[4]CLK_CMT:MUX.MUXBUS20[10]CLK_CMT:MUX.MUXBUS21[4]CLK_CMT:MUX.MUXBUS21[10]
    CLK_CMT:MUX.MUXBUS20[3]CLK_CMT:MUX.MUXBUS20[4]CLK_CMT:MUX.MUXBUS21[3]CLK_CMT:MUX.MUXBUS21[4]
    41-CLK_CMT:MUX.MUXBUS20[11]-CLK_CMT:MUX.MUXBUS21[11]
    -CLK_CMT:MUX.MUXBUS20[5]-CLK_CMT:MUX.MUXBUS21[5]
    42CLK_CMT:MUX.MUXBUS20[5]CLK_CMT:MUX.MUXBUS20[12]CLK_CMT:MUX.MUXBUS21[5]CLK_CMT:MUX.MUXBUS21[12]
    CLK_CMT:MUX.MUXBUS20[2]CLK_CMT:MUX.MUXBUS20[1]CLK_CMT:MUX.MUXBUS21[2]CLK_CMT:MUX.MUXBUS21[1]
    43 ----
    44 ----
    45-CLK_CMT:MUX.MUXBUS20[13]-CLK_CMT:MUX.MUXBUS21[13]
    -CLK_CMT:MUX.MUXBUS20[0]-CLK_CMT:MUX.MUXBUS21[0]
    46 ----
    4748 ----
    49CLK_CMT:MUX.MUXBUS22[0]-CLK_CMT:MUX.MUXBUS23[0]-
    CLK_CMT:MUX.MUXBUS22[12]-CLK_CMT:MUX.MUXBUS23[12]-
    50-CLK_CMT:MUX.MUXBUS22[6]-CLK_CMT:MUX.MUXBUS23[6]
    -CLK_CMT:MUX.MUXBUS22[10]-CLK_CMT:MUX.MUXBUS23[10]
    51CLK_CMT:MUX.MUXBUS22[1]-CLK_CMT:MUX.MUXBUS23[1]-
    CLK_CMT:MUX.MUXBUS22[8]-CLK_CMT:MUX.MUXBUS23[8]-
    52-CLK_CMT:MUX.MUXBUS22[7]-CLK_CMT:MUX.MUXBUS23[7]
    -CLK_CMT:MUX.MUXBUS22[6]-CLK_CMT:MUX.MUXBUS23[6]
    53CLK_CMT:MUX.MUXBUS22[2]-CLK_CMT:MUX.MUXBUS23[2]-
    CLK_CMT:MUX.MUXBUS22[11]-CLK_CMT:MUX.MUXBUS23[11]-
    54-CLK_CMT:MUX.MUXBUS22[8]-CLK_CMT:MUX.MUXBUS23[8]
    -CLK_CMT:MUX.MUXBUS22[9]-CLK_CMT:MUX.MUXBUS23[9]
    55CLK_CMT:MUX.MUXBUS22[3]CLK_CMT:MUX.MUXBUS22[9]CLK_CMT:MUX.MUXBUS23[3]CLK_CMT:MUX.MUXBUS23[9]
    CLK_CMT:MUX.MUXBUS22[7]CLK_CMT:MUX.MUXBUS22[13]CLK_CMT:MUX.MUXBUS23[7]CLK_CMT:MUX.MUXBUS23[13]
    56CLK_CMT:MUX.MUXBUS22[4]CLK_CMT:MUX.MUXBUS22[10]CLK_CMT:MUX.MUXBUS23[4]CLK_CMT:MUX.MUXBUS23[10]
    CLK_CMT:MUX.MUXBUS22[3]CLK_CMT:MUX.MUXBUS22[4]CLK_CMT:MUX.MUXBUS23[3]CLK_CMT:MUX.MUXBUS23[4]
    57-CLK_CMT:MUX.MUXBUS22[11]-CLK_CMT:MUX.MUXBUS23[11]
    -CLK_CMT:MUX.MUXBUS22[5]-CLK_CMT:MUX.MUXBUS23[5]
    58CLK_CMT:MUX.MUXBUS22[5]CLK_CMT:MUX.MUXBUS22[12]CLK_CMT:MUX.MUXBUS23[5]CLK_CMT:MUX.MUXBUS23[12]
    CLK_CMT:MUX.MUXBUS22[2]CLK_CMT:MUX.MUXBUS22[1]CLK_CMT:MUX.MUXBUS23[2]CLK_CMT:MUX.MUXBUS23[1]
    59 ----
    60 ----
    61-CLK_CMT:MUX.MUXBUS22[13]-CLK_CMT:MUX.MUXBUS23[13]
    -CLK_CMT:MUX.MUXBUS22[0]-CLK_CMT:MUX.MUXBUS23[0]
    - + - + - + - + - + - + - + - + - + - + - + @@ -2609,31 +2609,31 @@

    CLK_CMT_B

    - + - + - + - + - + - + - + - + - + - + - + @@ -2641,31 +2641,31 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - + @@ -2673,31 +2673,31 @@

    CLK_CMT_B

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_B bittile 8
    RowColumn
    0123
    0 ----
    1CLK_CMT:MUX.MUXBUS24[0]-CLK_CMT:MUX.MUXBUS25[0]-
    CLK_CMT:MUX.MUXBUS24[12]-CLK_CMT:MUX.MUXBUS25[12]-
    2-CLK_CMT:MUX.MUXBUS24[6]-CLK_CMT:MUX.MUXBUS25[6]
    -CLK_CMT:MUX.MUXBUS24[10]-CLK_CMT:MUX.MUXBUS25[10]
    3CLK_CMT:MUX.MUXBUS24[1]-CLK_CMT:MUX.MUXBUS25[1]-
    CLK_CMT:MUX.MUXBUS24[8]-CLK_CMT:MUX.MUXBUS25[8]-
    4-CLK_CMT:MUX.MUXBUS24[7]-CLK_CMT:MUX.MUXBUS25[7]
    -CLK_CMT:MUX.MUXBUS24[6]-CLK_CMT:MUX.MUXBUS25[6]
    5CLK_CMT:MUX.MUXBUS24[2]-CLK_CMT:MUX.MUXBUS25[2]-
    CLK_CMT:MUX.MUXBUS24[11]-CLK_CMT:MUX.MUXBUS25[11]-
    6-CLK_CMT:MUX.MUXBUS24[8]-CLK_CMT:MUX.MUXBUS25[8]
    -CLK_CMT:MUX.MUXBUS24[9]-CLK_CMT:MUX.MUXBUS25[9]
    7CLK_CMT:MUX.MUXBUS24[3]CLK_CMT:MUX.MUXBUS24[9]CLK_CMT:MUX.MUXBUS25[3]CLK_CMT:MUX.MUXBUS25[9]
    CLK_CMT:MUX.MUXBUS24[7]CLK_CMT:MUX.MUXBUS24[13]CLK_CMT:MUX.MUXBUS25[7]CLK_CMT:MUX.MUXBUS25[13]
    8CLK_CMT:MUX.MUXBUS24[4]CLK_CMT:MUX.MUXBUS24[10]CLK_CMT:MUX.MUXBUS25[4]CLK_CMT:MUX.MUXBUS25[10]
    CLK_CMT:MUX.MUXBUS24[3]CLK_CMT:MUX.MUXBUS24[4]CLK_CMT:MUX.MUXBUS25[3]CLK_CMT:MUX.MUXBUS25[4]
    9-CLK_CMT:MUX.MUXBUS24[11]-CLK_CMT:MUX.MUXBUS25[11]
    -CLK_CMT:MUX.MUXBUS24[5]-CLK_CMT:MUX.MUXBUS25[5]
    10CLK_CMT:MUX.MUXBUS24[5]CLK_CMT:MUX.MUXBUS24[12]CLK_CMT:MUX.MUXBUS25[5]CLK_CMT:MUX.MUXBUS25[12]
    CLK_CMT:MUX.MUXBUS24[2]CLK_CMT:MUX.MUXBUS24[1]CLK_CMT:MUX.MUXBUS25[2]CLK_CMT:MUX.MUXBUS25[1]
    11 ----
    12 ----
    13-CLK_CMT:MUX.MUXBUS24[13]-CLK_CMT:MUX.MUXBUS25[13]
    -CLK_CMT:MUX.MUXBUS24[0]-CLK_CMT:MUX.MUXBUS25[0]
    14 ----
    1516 ----
    17CLK_CMT:MUX.MUXBUS26[0]-CLK_CMT:MUX.MUXBUS27[0]-
    CLK_CMT:MUX.MUXBUS26[12]-CLK_CMT:MUX.MUXBUS27[12]-
    18-CLK_CMT:MUX.MUXBUS26[6]-CLK_CMT:MUX.MUXBUS27[6]
    -CLK_CMT:MUX.MUXBUS26[10]-CLK_CMT:MUX.MUXBUS27[10]
    19CLK_CMT:MUX.MUXBUS26[1]-CLK_CMT:MUX.MUXBUS27[1]-
    CLK_CMT:MUX.MUXBUS26[8]-CLK_CMT:MUX.MUXBUS27[8]-
    20-CLK_CMT:MUX.MUXBUS26[7]-CLK_CMT:MUX.MUXBUS27[7]
    -CLK_CMT:MUX.MUXBUS26[6]-CLK_CMT:MUX.MUXBUS27[6]
    21CLK_CMT:MUX.MUXBUS26[2]-CLK_CMT:MUX.MUXBUS27[2]-
    CLK_CMT:MUX.MUXBUS26[11]-CLK_CMT:MUX.MUXBUS27[11]-
    22-CLK_CMT:MUX.MUXBUS26[8]-CLK_CMT:MUX.MUXBUS27[8]
    -CLK_CMT:MUX.MUXBUS26[9]-CLK_CMT:MUX.MUXBUS27[9]
    23CLK_CMT:MUX.MUXBUS26[3]CLK_CMT:MUX.MUXBUS26[9]CLK_CMT:MUX.MUXBUS27[3]CLK_CMT:MUX.MUXBUS27[9]
    CLK_CMT:MUX.MUXBUS26[7]CLK_CMT:MUX.MUXBUS26[13]CLK_CMT:MUX.MUXBUS27[7]CLK_CMT:MUX.MUXBUS27[13]
    24CLK_CMT:MUX.MUXBUS26[4]CLK_CMT:MUX.MUXBUS26[10]CLK_CMT:MUX.MUXBUS27[4]CLK_CMT:MUX.MUXBUS27[10]
    CLK_CMT:MUX.MUXBUS26[3]CLK_CMT:MUX.MUXBUS26[4]CLK_CMT:MUX.MUXBUS27[3]CLK_CMT:MUX.MUXBUS27[4]
    25-CLK_CMT:MUX.MUXBUS26[11]-CLK_CMT:MUX.MUXBUS27[11]
    -CLK_CMT:MUX.MUXBUS26[5]-CLK_CMT:MUX.MUXBUS27[5]
    26CLK_CMT:MUX.MUXBUS26[5]CLK_CMT:MUX.MUXBUS26[12]CLK_CMT:MUX.MUXBUS27[5]CLK_CMT:MUX.MUXBUS27[12]
    CLK_CMT:MUX.MUXBUS26[2]CLK_CMT:MUX.MUXBUS26[1]CLK_CMT:MUX.MUXBUS27[2]CLK_CMT:MUX.MUXBUS27[1]
    27 ----
    28 ----
    29-CLK_CMT:MUX.MUXBUS26[13]-CLK_CMT:MUX.MUXBUS27[13]
    -CLK_CMT:MUX.MUXBUS26[0]-CLK_CMT:MUX.MUXBUS27[0]
    30 ----
    3132 ----
    33CLK_CMT:MUX.MUXBUS28[0]-CLK_CMT:MUX.MUXBUS29[0]-
    CLK_CMT:MUX.MUXBUS28[12]-CLK_CMT:MUX.MUXBUS29[12]-
    34-CLK_CMT:MUX.MUXBUS28[6]-CLK_CMT:MUX.MUXBUS29[6]
    -CLK_CMT:MUX.MUXBUS28[10]-CLK_CMT:MUX.MUXBUS29[10]
    35CLK_CMT:MUX.MUXBUS28[1]-CLK_CMT:MUX.MUXBUS29[1]-
    CLK_CMT:MUX.MUXBUS28[8]-CLK_CMT:MUX.MUXBUS29[8]-
    36-CLK_CMT:MUX.MUXBUS28[7]-CLK_CMT:MUX.MUXBUS29[7]
    -CLK_CMT:MUX.MUXBUS28[6]-CLK_CMT:MUX.MUXBUS29[6]
    37CLK_CMT:MUX.MUXBUS28[2]-CLK_CMT:MUX.MUXBUS29[2]-
    CLK_CMT:MUX.MUXBUS28[11]-CLK_CMT:MUX.MUXBUS29[11]-
    38-CLK_CMT:MUX.MUXBUS28[8]-CLK_CMT:MUX.MUXBUS29[8]
    -CLK_CMT:MUX.MUXBUS28[9]-CLK_CMT:MUX.MUXBUS29[9]
    39CLK_CMT:MUX.MUXBUS28[3]CLK_CMT:MUX.MUXBUS28[9]CLK_CMT:MUX.MUXBUS29[3]CLK_CMT:MUX.MUXBUS29[9]
    CLK_CMT:MUX.MUXBUS28[7]CLK_CMT:MUX.MUXBUS28[13]CLK_CMT:MUX.MUXBUS29[7]CLK_CMT:MUX.MUXBUS29[13]
    40CLK_CMT:MUX.MUXBUS28[4]CLK_CMT:MUX.MUXBUS28[10]CLK_CMT:MUX.MUXBUS29[4]CLK_CMT:MUX.MUXBUS29[10]
    CLK_CMT:MUX.MUXBUS28[3]CLK_CMT:MUX.MUXBUS28[4]CLK_CMT:MUX.MUXBUS29[3]CLK_CMT:MUX.MUXBUS29[4]
    41-CLK_CMT:MUX.MUXBUS28[11]-CLK_CMT:MUX.MUXBUS29[11]
    -CLK_CMT:MUX.MUXBUS28[5]-CLK_CMT:MUX.MUXBUS29[5]
    42CLK_CMT:MUX.MUXBUS28[5]CLK_CMT:MUX.MUXBUS28[12]CLK_CMT:MUX.MUXBUS29[5]CLK_CMT:MUX.MUXBUS29[12]
    CLK_CMT:MUX.MUXBUS28[2]CLK_CMT:MUX.MUXBUS28[1]CLK_CMT:MUX.MUXBUS29[2]CLK_CMT:MUX.MUXBUS29[1]
    43 ----
    44 ----
    45-CLK_CMT:MUX.MUXBUS28[13]-CLK_CMT:MUX.MUXBUS29[13]
    -CLK_CMT:MUX.MUXBUS28[0]-CLK_CMT:MUX.MUXBUS29[0]
    46 ----
    4748 ----
    49CLK_CMT:MUX.MUXBUS30[0]-CLK_CMT:MUX.MUXBUS31[0]-
    CLK_CMT:MUX.MUXBUS30[12]-CLK_CMT:MUX.MUXBUS31[12]-
    50-CLK_CMT:MUX.MUXBUS30[6]-CLK_CMT:MUX.MUXBUS31[6]
    -CLK_CMT:MUX.MUXBUS30[10]-CLK_CMT:MUX.MUXBUS31[10]
    51CLK_CMT:MUX.MUXBUS30[1]-CLK_CMT:MUX.MUXBUS31[1]-
    CLK_CMT:MUX.MUXBUS30[8]-CLK_CMT:MUX.MUXBUS31[8]-
    52-CLK_CMT:MUX.MUXBUS30[7]-CLK_CMT:MUX.MUXBUS31[7]
    -CLK_CMT:MUX.MUXBUS30[6]-CLK_CMT:MUX.MUXBUS31[6]
    53CLK_CMT:MUX.MUXBUS30[2]-CLK_CMT:MUX.MUXBUS31[2]-
    CLK_CMT:MUX.MUXBUS30[11]-CLK_CMT:MUX.MUXBUS31[11]-
    54-CLK_CMT:MUX.MUXBUS30[8]-CLK_CMT:MUX.MUXBUS31[8]
    -CLK_CMT:MUX.MUXBUS30[9]-CLK_CMT:MUX.MUXBUS31[9]
    55CLK_CMT:MUX.MUXBUS30[3]CLK_CMT:MUX.MUXBUS30[9]CLK_CMT:MUX.MUXBUS31[3]CLK_CMT:MUX.MUXBUS31[9]
    CLK_CMT:MUX.MUXBUS30[7]CLK_CMT:MUX.MUXBUS30[13]CLK_CMT:MUX.MUXBUS31[7]CLK_CMT:MUX.MUXBUS31[13]
    56CLK_CMT:MUX.MUXBUS30[4]CLK_CMT:MUX.MUXBUS30[10]CLK_CMT:MUX.MUXBUS31[4]CLK_CMT:MUX.MUXBUS31[10]
    CLK_CMT:MUX.MUXBUS30[3]CLK_CMT:MUX.MUXBUS30[4]CLK_CMT:MUX.MUXBUS31[3]CLK_CMT:MUX.MUXBUS31[4]
    57-CLK_CMT:MUX.MUXBUS30[11]-CLK_CMT:MUX.MUXBUS31[11]
    -CLK_CMT:MUX.MUXBUS30[5]-CLK_CMT:MUX.MUXBUS31[5]
    58CLK_CMT:MUX.MUXBUS30[5]CLK_CMT:MUX.MUXBUS30[12]CLK_CMT:MUX.MUXBUS31[5]CLK_CMT:MUX.MUXBUS31[12]
    CLK_CMT:MUX.MUXBUS30[2]CLK_CMT:MUX.MUXBUS30[1]CLK_CMT:MUX.MUXBUS31[2]CLK_CMT:MUX.MUXBUS31[1]
    59 ----
    60 ----
    61-CLK_CMT:MUX.MUXBUS30[13]-CLK_CMT:MUX.MUXBUS31[13]
    -CLK_CMT:MUX.MUXBUS30[0]-CLK_CMT:MUX.MUXBUS31[0]
    @@ -2755,78 +2755,78 @@

    CLK_CMT_B
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_CMT:MUX.MUXBUS0[5, 1, 13][5, 1, 10][5, 1, 9][5, 1, 8][5, 1, 7][5, 1, 6][5, 1, 4][5, 1, 2][5, 0, 10][5, 0, 8][5, 0, 7][5, 0, 5][5, 0, 3][5, 0, 1]
    CLK_CMT:MUX.MUXBUS1[5, 3, 13][5, 3, 10][5, 3, 9][5, 3, 8][5, 3, 7][5, 3, 6][5, 3, 4][5, 3, 2][5, 2, 10][5, 2, 8][5, 2, 7][5, 2, 5][5, 2, 3][5, 2, 1]
    CLK_CMT:MUX.MUXBUS10[6, 1, 29][6, 1, 26][6, 1, 25][6, 1, 24][6, 1, 23][6, 1, 22][6, 1, 20][6, 1, 18][6, 0, 26][6, 0, 24][6, 0, 23][6, 0, 21][6, 0, 19][6, 0, 17]
    CLK_CMT:MUX.MUXBUS11[6, 3, 29][6, 3, 26][6, 3, 25][6, 3, 24][6, 3, 23][6, 3, 22][6, 3, 20][6, 3, 18][6, 2, 26][6, 2, 24][6, 2, 23][6, 2, 21][6, 2, 19][6, 2, 17]
    CLK_CMT:MUX.MUXBUS12[6, 1, 45][6, 1, 42][6, 1, 41][6, 1, 40][6, 1, 39][6, 1, 38][6, 1, 36][6, 1, 34][6, 0, 42][6, 0, 40][6, 0, 39][6, 0, 37][6, 0, 35][6, 0, 33]
    CLK_CMT:MUX.MUXBUS13[6, 3, 45][6, 3, 42][6, 3, 41][6, 3, 40][6, 3, 39][6, 3, 38][6, 3, 36][6, 3, 34][6, 2, 42][6, 2, 40][6, 2, 39][6, 2, 37][6, 2, 35][6, 2, 33]
    CLK_CMT:MUX.MUXBUS14[6, 1, 61][6, 1, 58][6, 1, 57][6, 1, 56][6, 1, 55][6, 1, 54][6, 1, 52][6, 1, 50][6, 0, 58][6, 0, 56][6, 0, 55][6, 0, 53][6, 0, 51][6, 0, 49]
    CLK_CMT:MUX.MUXBUS15[6, 3, 61][6, 3, 58][6, 3, 57][6, 3, 56][6, 3, 55][6, 3, 54][6, 3, 52][6, 3, 50][6, 2, 58][6, 2, 56][6, 2, 55][6, 2, 53][6, 2, 51][6, 2, 49]
    CLK_CMT:MUX.MUXBUS16[7, 1, 13][7, 1, 10][7, 1, 9][7, 1, 8][7, 1, 7][7, 1, 6][7, 1, 4][7, 1, 2][7, 0, 10][7, 0, 8][7, 0, 7][7, 0, 5][7, 0, 3][7, 0, 1]
    CLK_CMT:MUX.MUXBUS17[7, 3, 13][7, 3, 10][7, 3, 9][7, 3, 8][7, 3, 7][7, 3, 6][7, 3, 4][7, 3, 2][7, 2, 10][7, 2, 8][7, 2, 7][7, 2, 5][7, 2, 3][7, 2, 1]
    CLK_CMT:MUX.MUXBUS18[7, 1, 29][7, 1, 26][7, 1, 25][7, 1, 24][7, 1, 23][7, 1, 22][7, 1, 20][7, 1, 18][7, 0, 26][7, 0, 24][7, 0, 23][7, 0, 21][7, 0, 19][7, 0, 17]
    CLK_CMT:MUX.MUXBUS19[7, 3, 29][7, 3, 26][7, 3, 25][7, 3, 24][7, 3, 23][7, 3, 22][7, 3, 20][7, 3, 18][7, 2, 26][7, 2, 24][7, 2, 23][7, 2, 21][7, 2, 19][7, 2, 17]
    CLK_CMT:MUX.MUXBUS2[5, 1, 29][5, 1, 26][5, 1, 25][5, 1, 24][5, 1, 23][5, 1, 22][5, 1, 20][5, 1, 18][5, 0, 26][5, 0, 24][5, 0, 23][5, 0, 21][5, 0, 19][5, 0, 17]
    CLK_CMT:MUX.MUXBUS20[7, 1, 45][7, 1, 42][7, 1, 41][7, 1, 40][7, 1, 39][7, 1, 38][7, 1, 36][7, 1, 34][7, 0, 42][7, 0, 40][7, 0, 39][7, 0, 37][7, 0, 35][7, 0, 33]
    CLK_CMT:MUX.MUXBUS21[7, 3, 45][7, 3, 42][7, 3, 41][7, 3, 40][7, 3, 39][7, 3, 38][7, 3, 36][7, 3, 34][7, 2, 42][7, 2, 40][7, 2, 39][7, 2, 37][7, 2, 35][7, 2, 33]
    CLK_CMT:MUX.MUXBUS22[7, 1, 61][7, 1, 58][7, 1, 57][7, 1, 56][7, 1, 55][7, 1, 54][7, 1, 52][7, 1, 50][7, 0, 58][7, 0, 56][7, 0, 55][7, 0, 53][7, 0, 51][7, 0, 49]
    CLK_CMT:MUX.MUXBUS23[7, 3, 61][7, 3, 58][7, 3, 57][7, 3, 56][7, 3, 55][7, 3, 54][7, 3, 52][7, 3, 50][7, 2, 58][7, 2, 56][7, 2, 55][7, 2, 53][7, 2, 51][7, 2, 49]
    CLK_CMT:MUX.MUXBUS24[8, 1, 13][8, 1, 10][8, 1, 9][8, 1, 8][8, 1, 7][8, 1, 6][8, 1, 4][8, 1, 2][8, 0, 10][8, 0, 8][8, 0, 7][8, 0, 5][8, 0, 3][8, 0, 1]
    CLK_CMT:MUX.MUXBUS25[8, 3, 13][8, 3, 10][8, 3, 9][8, 3, 8][8, 3, 7][8, 3, 6][8, 3, 4][8, 3, 2][8, 2, 10][8, 2, 8][8, 2, 7][8, 2, 5][8, 2, 3][8, 2, 1]
    CLK_CMT:MUX.MUXBUS26[8, 1, 29][8, 1, 26][8, 1, 25][8, 1, 24][8, 1, 23][8, 1, 22][8, 1, 20][8, 1, 18][8, 0, 26][8, 0, 24][8, 0, 23][8, 0, 21][8, 0, 19][8, 0, 17]
    CLK_CMT:MUX.MUXBUS27[8, 3, 29][8, 3, 26][8, 3, 25][8, 3, 24][8, 3, 23][8, 3, 22][8, 3, 20][8, 3, 18][8, 2, 26][8, 2, 24][8, 2, 23][8, 2, 21][8, 2, 19][8, 2, 17]
    CLK_CMT:MUX.MUXBUS28[8, 1, 45][8, 1, 42][8, 1, 41][8, 1, 40][8, 1, 39][8, 1, 38][8, 1, 36][8, 1, 34][8, 0, 42][8, 0, 40][8, 0, 39][8, 0, 37][8, 0, 35][8, 0, 33]
    CLK_CMT:MUX.MUXBUS29[8, 3, 45][8, 3, 42][8, 3, 41][8, 3, 40][8, 3, 39][8, 3, 38][8, 3, 36][8, 3, 34][8, 2, 42][8, 2, 40][8, 2, 39][8, 2, 37][8, 2, 35][8, 2, 33]
    CLK_CMT:MUX.MUXBUS3[5, 3, 29][5, 3, 26][5, 3, 25][5, 3, 24][5, 3, 23][5, 3, 22][5, 3, 20][5, 3, 18][5, 2, 26][5, 2, 24][5, 2, 23][5, 2, 21][5, 2, 19][5, 2, 17]
    CLK_CMT:MUX.MUXBUS30[8, 1, 61][8, 1, 58][8, 1, 57][8, 1, 56][8, 1, 55][8, 1, 54][8, 1, 52][8, 1, 50][8, 0, 58][8, 0, 56][8, 0, 55][8, 0, 53][8, 0, 51][8, 0, 49]
    CLK_CMT:MUX.MUXBUS31[8, 3, 61][8, 3, 58][8, 3, 57][8, 3, 56][8, 3, 55][8, 3, 54][8, 3, 52][8, 3, 50][8, 2, 58][8, 2, 56][8, 2, 55][8, 2, 53][8, 2, 51][8, 2, 49]
    CLK_CMT:MUX.MUXBUS4[5, 1, 45][5, 1, 42][5, 1, 41][5, 1, 40][5, 1, 39][5, 1, 38][5, 1, 36][5, 1, 34][5, 0, 42][5, 0, 40][5, 0, 39][5, 0, 37][5, 0, 35][5, 0, 33]
    CLK_CMT:MUX.MUXBUS5[5, 3, 45][5, 3, 42][5, 3, 41][5, 3, 40][5, 3, 39][5, 3, 38][5, 3, 36][5, 3, 34][5, 2, 42][5, 2, 40][5, 2, 39][5, 2, 37][5, 2, 35][5, 2, 33]
    CLK_CMT:MUX.MUXBUS6[5, 1, 61][5, 1, 58][5, 1, 57][5, 1, 56][5, 1, 55][5, 1, 54][5, 1, 52][5, 1, 50][5, 0, 58][5, 0, 56][5, 0, 55][5, 0, 53][5, 0, 51][5, 0, 49]
    CLK_CMT:MUX.MUXBUS7[5, 3, 61][5, 3, 58][5, 3, 57][5, 3, 56][5, 3, 55][5, 3, 54][5, 3, 52][5, 3, 50][5, 2, 58][5, 2, 56][5, 2, 55][5, 2, 53][5, 2, 51][5, 2, 49]
    CLK_CMT:MUX.MUXBUS8[6, 1, 13][6, 1, 10][6, 1, 9][6, 1, 8][6, 1, 7][6, 1, 6][6, 1, 4][6, 1, 2][6, 0, 10][6, 0, 8][6, 0, 7][6, 0, 5][6, 0, 3][6, 0, 1]
    CLK_CMT:MUX.MUXBUS9[6, 3, 13][6, 3, 10][6, 3, 9][6, 3, 8][6, 3, 7][6, 3, 6][6, 3, 4][6, 3, 2][6, 2, 10][6, 2, 8][6, 2, 7][6, 2, 5][6, 2, 3][6, 2, 1]
    CLK_CMT:MUX.MUXBUS0[5, 1, 7][5, 0, 1][5, 0, 5][5, 1, 2][5, 1, 6][5, 0, 3][5, 0, 7][5, 1, 4][5, 1, 9][5, 1, 8][5, 0, 8][5, 0, 10][5, 1, 10][5, 1, 13]
    CLK_CMT:MUX.MUXBUS1[5, 3, 7][5, 2, 1][5, 2, 5][5, 3, 2][5, 3, 6][5, 2, 3][5, 2, 7][5, 3, 4][5, 3, 9][5, 3, 8][5, 2, 8][5, 2, 10][5, 3, 10][5, 3, 13]
    CLK_CMT:MUX.MUXBUS10[6, 1, 23][6, 0, 17][6, 0, 21][6, 1, 18][6, 1, 22][6, 0, 19][6, 0, 23][6, 1, 20][6, 1, 25][6, 1, 24][6, 0, 24][6, 0, 26][6, 1, 26][6, 1, 29]
    CLK_CMT:MUX.MUXBUS11[6, 3, 23][6, 2, 17][6, 2, 21][6, 3, 18][6, 3, 22][6, 2, 19][6, 2, 23][6, 3, 20][6, 3, 25][6, 3, 24][6, 2, 24][6, 2, 26][6, 3, 26][6, 3, 29]
    CLK_CMT:MUX.MUXBUS12[6, 1, 39][6, 0, 33][6, 0, 37][6, 1, 34][6, 1, 38][6, 0, 35][6, 0, 39][6, 1, 36][6, 1, 41][6, 1, 40][6, 0, 40][6, 0, 42][6, 1, 42][6, 1, 45]
    CLK_CMT:MUX.MUXBUS13[6, 3, 39][6, 2, 33][6, 2, 37][6, 3, 34][6, 3, 38][6, 2, 35][6, 2, 39][6, 3, 36][6, 3, 41][6, 3, 40][6, 2, 40][6, 2, 42][6, 3, 42][6, 3, 45]
    CLK_CMT:MUX.MUXBUS14[6, 1, 55][6, 0, 49][6, 0, 53][6, 1, 50][6, 1, 54][6, 0, 51][6, 0, 55][6, 1, 52][6, 1, 57][6, 1, 56][6, 0, 56][6, 0, 58][6, 1, 58][6, 1, 61]
    CLK_CMT:MUX.MUXBUS15[6, 3, 55][6, 2, 49][6, 2, 53][6, 3, 50][6, 3, 54][6, 2, 51][6, 2, 55][6, 3, 52][6, 3, 57][6, 3, 56][6, 2, 56][6, 2, 58][6, 3, 58][6, 3, 61]
    CLK_CMT:MUX.MUXBUS16[7, 1, 7][7, 0, 1][7, 0, 5][7, 1, 2][7, 1, 6][7, 0, 3][7, 0, 7][7, 1, 4][7, 1, 9][7, 1, 8][7, 0, 8][7, 0, 10][7, 1, 10][7, 1, 13]
    CLK_CMT:MUX.MUXBUS17[7, 3, 7][7, 2, 1][7, 2, 5][7, 3, 2][7, 3, 6][7, 2, 3][7, 2, 7][7, 3, 4][7, 3, 9][7, 3, 8][7, 2, 8][7, 2, 10][7, 3, 10][7, 3, 13]
    CLK_CMT:MUX.MUXBUS18[7, 1, 23][7, 0, 17][7, 0, 21][7, 1, 18][7, 1, 22][7, 0, 19][7, 0, 23][7, 1, 20][7, 1, 25][7, 1, 24][7, 0, 24][7, 0, 26][7, 1, 26][7, 1, 29]
    CLK_CMT:MUX.MUXBUS19[7, 3, 23][7, 2, 17][7, 2, 21][7, 3, 18][7, 3, 22][7, 2, 19][7, 2, 23][7, 3, 20][7, 3, 25][7, 3, 24][7, 2, 24][7, 2, 26][7, 3, 26][7, 3, 29]
    CLK_CMT:MUX.MUXBUS2[5, 1, 23][5, 0, 17][5, 0, 21][5, 1, 18][5, 1, 22][5, 0, 19][5, 0, 23][5, 1, 20][5, 1, 25][5, 1, 24][5, 0, 24][5, 0, 26][5, 1, 26][5, 1, 29]
    CLK_CMT:MUX.MUXBUS20[7, 1, 39][7, 0, 33][7, 0, 37][7, 1, 34][7, 1, 38][7, 0, 35][7, 0, 39][7, 1, 36][7, 1, 41][7, 1, 40][7, 0, 40][7, 0, 42][7, 1, 42][7, 1, 45]
    CLK_CMT:MUX.MUXBUS21[7, 3, 39][7, 2, 33][7, 2, 37][7, 3, 34][7, 3, 38][7, 2, 35][7, 2, 39][7, 3, 36][7, 3, 41][7, 3, 40][7, 2, 40][7, 2, 42][7, 3, 42][7, 3, 45]
    CLK_CMT:MUX.MUXBUS22[7, 1, 55][7, 0, 49][7, 0, 53][7, 1, 50][7, 1, 54][7, 0, 51][7, 0, 55][7, 1, 52][7, 1, 57][7, 1, 56][7, 0, 56][7, 0, 58][7, 1, 58][7, 1, 61]
    CLK_CMT:MUX.MUXBUS23[7, 3, 55][7, 2, 49][7, 2, 53][7, 3, 50][7, 3, 54][7, 2, 51][7, 2, 55][7, 3, 52][7, 3, 57][7, 3, 56][7, 2, 56][7, 2, 58][7, 3, 58][7, 3, 61]
    CLK_CMT:MUX.MUXBUS24[8, 1, 7][8, 0, 1][8, 0, 5][8, 1, 2][8, 1, 6][8, 0, 3][8, 0, 7][8, 1, 4][8, 1, 9][8, 1, 8][8, 0, 8][8, 0, 10][8, 1, 10][8, 1, 13]
    CLK_CMT:MUX.MUXBUS25[8, 3, 7][8, 2, 1][8, 2, 5][8, 3, 2][8, 3, 6][8, 2, 3][8, 2, 7][8, 3, 4][8, 3, 9][8, 3, 8][8, 2, 8][8, 2, 10][8, 3, 10][8, 3, 13]
    CLK_CMT:MUX.MUXBUS26[8, 1, 23][8, 0, 17][8, 0, 21][8, 1, 18][8, 1, 22][8, 0, 19][8, 0, 23][8, 1, 20][8, 1, 25][8, 1, 24][8, 0, 24][8, 0, 26][8, 1, 26][8, 1, 29]
    CLK_CMT:MUX.MUXBUS27[8, 3, 23][8, 2, 17][8, 2, 21][8, 3, 18][8, 3, 22][8, 2, 19][8, 2, 23][8, 3, 20][8, 3, 25][8, 3, 24][8, 2, 24][8, 2, 26][8, 3, 26][8, 3, 29]
    CLK_CMT:MUX.MUXBUS28[8, 1, 39][8, 0, 33][8, 0, 37][8, 1, 34][8, 1, 38][8, 0, 35][8, 0, 39][8, 1, 36][8, 1, 41][8, 1, 40][8, 0, 40][8, 0, 42][8, 1, 42][8, 1, 45]
    CLK_CMT:MUX.MUXBUS29[8, 3, 39][8, 2, 33][8, 2, 37][8, 3, 34][8, 3, 38][8, 2, 35][8, 2, 39][8, 3, 36][8, 3, 41][8, 3, 40][8, 2, 40][8, 2, 42][8, 3, 42][8, 3, 45]
    CLK_CMT:MUX.MUXBUS3[5, 3, 23][5, 2, 17][5, 2, 21][5, 3, 18][5, 3, 22][5, 2, 19][5, 2, 23][5, 3, 20][5, 3, 25][5, 3, 24][5, 2, 24][5, 2, 26][5, 3, 26][5, 3, 29]
    CLK_CMT:MUX.MUXBUS30[8, 1, 55][8, 0, 49][8, 0, 53][8, 1, 50][8, 1, 54][8, 0, 51][8, 0, 55][8, 1, 52][8, 1, 57][8, 1, 56][8, 0, 56][8, 0, 58][8, 1, 58][8, 1, 61]
    CLK_CMT:MUX.MUXBUS31[8, 3, 55][8, 2, 49][8, 2, 53][8, 3, 50][8, 3, 54][8, 2, 51][8, 2, 55][8, 3, 52][8, 3, 57][8, 3, 56][8, 2, 56][8, 2, 58][8, 3, 58][8, 3, 61]
    CLK_CMT:MUX.MUXBUS4[5, 1, 39][5, 0, 33][5, 0, 37][5, 1, 34][5, 1, 38][5, 0, 35][5, 0, 39][5, 1, 36][5, 1, 41][5, 1, 40][5, 0, 40][5, 0, 42][5, 1, 42][5, 1, 45]
    CLK_CMT:MUX.MUXBUS5[5, 3, 39][5, 2, 33][5, 2, 37][5, 3, 34][5, 3, 38][5, 2, 35][5, 2, 39][5, 3, 36][5, 3, 41][5, 3, 40][5, 2, 40][5, 2, 42][5, 3, 42][5, 3, 45]
    CLK_CMT:MUX.MUXBUS6[5, 1, 55][5, 0, 49][5, 0, 53][5, 1, 50][5, 1, 54][5, 0, 51][5, 0, 55][5, 1, 52][5, 1, 57][5, 1, 56][5, 0, 56][5, 0, 58][5, 1, 58][5, 1, 61]
    CLK_CMT:MUX.MUXBUS7[5, 3, 55][5, 2, 49][5, 2, 53][5, 3, 50][5, 3, 54][5, 2, 51][5, 2, 55][5, 3, 52][5, 3, 57][5, 3, 56][5, 2, 56][5, 2, 58][5, 3, 58][5, 3, 61]
    CLK_CMT:MUX.MUXBUS8[6, 1, 7][6, 0, 1][6, 0, 5][6, 1, 2][6, 1, 6][6, 0, 3][6, 0, 7][6, 1, 4][6, 1, 9][6, 1, 8][6, 0, 8][6, 0, 10][6, 1, 10][6, 1, 13]
    CLK_CMT:MUX.MUXBUS9[6, 3, 7][6, 2, 1][6, 2, 5][6, 3, 2][6, 3, 6][6, 2, 3][6, 2, 7][6, 3, 4][6, 3, 9][6, 3, 8][6, 2, 8][6, 2, 10][6, 3, 10][6, 3, 13]
    NONE00000000000000
    CMT_CLK700000000010001
    CMT_CLK500000000010010
    CMT_CLK300000000010100
    CMT_CLK100000000011000
    MGT_R400000000100010
    MGT_R200000000100100
    MGT_R000000000101000
    CMT_CLK600000001010000
    CMT_CLK400000010010000
    MGT_R300000010100000
    CMT_CLK200000100010000
    MGT_R100000100100000
    CMT_CLK000001000010000
    MGT_L400001000100000
    CMT_CLK1500010000000001
    CMT_CLK1300010000000010
    CMT_CLK1100010000000100
    CMT_CLK900010000001000
    CMT_CLK1400010001000000
    CMT_CLK1200010010000000
    CMT_CLK1000010100000000
    CMT_CLK800011000000000
    CMT_CLK2300100000000001
    CMT_CLK2100100000000010
    CMT_CLK1900100000000100
    CMT_CLK1700100000001000
    CMT_CLK2200100001000000
    CMT_CLK2000100010000000
    CMT_CLK1800100100000000
    CMT_CLK1600101000000000
    MGT_L301000000000001
    MGT_L101000000000010
    CMT_CLK2701000000000100
    CMT_CLK2501000000001000
    MGT_L201000001000000
    MGT_L001000010000000
    CMT_CLK2601000100000000
    CMT_CLK2401001000000000
    PASS10000000000000
    PASS00000000000001
    MGT_L000000001000010
    MGT_R300000001000100
    CMT_CLK400000001001000
    CMT_CLK1200000001010000
    CMT_CLK2000000001100000
    CMT_CLK2500000010000010
    MGT_R000000010000100
    CMT_CLK100000010001000
    CMT_CLK900000010010000
    CMT_CLK1700000010100000
    MGT_L100000100000010
    MGT_R400000100000100
    CMT_CLK500000100001000
    CMT_CLK1300000100010000
    CMT_CLK2100000100100000
    CMT_CLK2600001000000010
    MGT_R100001000000100
    CMT_CLK200001000001000
    CMT_CLK1000001000010000
    CMT_CLK1800001000100000
    MGT_L200010000000010
    CMT_CLK600010000001000
    CMT_CLK1400010000010000
    CMT_CLK2200010000100000
    CMT_CLK2700100000000010
    MGT_R200100000000100
    CMT_CLK300100000001000
    CMT_CLK1100100000010000
    CMT_CLK1900100000100000
    MGT_L301000000000010
    CMT_CLK701000000001000
    CMT_CLK1501000000010000
    CMT_CLK2301000000100000
    CMT_CLK2410000000000010
    MGT_L410000000000100
    CMT_CLK010000000001000
    CMT_CLK810000000010000
    CMT_CLK1610000000100000
    @@ -2841,31 +2841,31 @@

    CLK_CMT_T1 ---- 2 --CLK_CMT:MUX.MUXBUS30[6]-CLK_CMT:MUX.MUXBUS31[6] +-CLK_CMT:MUX.MUXBUS30[0]-CLK_CMT:MUX.MUXBUS31[0] 3 ---- 4 ---- 5 -CLK_CMT:MUX.MUXBUS30[0]CLK_CMT:MUX.MUXBUS30[7]CLK_CMT:MUX.MUXBUS31[0]CLK_CMT:MUX.MUXBUS31[7] +CLK_CMT:MUX.MUXBUS30[2]CLK_CMT:MUX.MUXBUS30[1]CLK_CMT:MUX.MUXBUS31[2]CLK_CMT:MUX.MUXBUS31[1] 6 --CLK_CMT:MUX.MUXBUS30[8]-CLK_CMT:MUX.MUXBUS31[8] +-CLK_CMT:MUX.MUXBUS30[5]-CLK_CMT:MUX.MUXBUS31[5] 7 -CLK_CMT:MUX.MUXBUS30[1]CLK_CMT:MUX.MUXBUS30[9]CLK_CMT:MUX.MUXBUS31[1]CLK_CMT:MUX.MUXBUS31[9] +CLK_CMT:MUX.MUXBUS30[3]CLK_CMT:MUX.MUXBUS30[4]CLK_CMT:MUX.MUXBUS31[3]CLK_CMT:MUX.MUXBUS31[4] 8 -CLK_CMT:MUX.MUXBUS30[2]CLK_CMT:MUX.MUXBUS30[10]CLK_CMT:MUX.MUXBUS31[2]CLK_CMT:MUX.MUXBUS31[10] +CLK_CMT:MUX.MUXBUS30[7]CLK_CMT:MUX.MUXBUS30[13]CLK_CMT:MUX.MUXBUS31[7]CLK_CMT:MUX.MUXBUS31[13] 9 --CLK_CMT:MUX.MUXBUS30[11]-CLK_CMT:MUX.MUXBUS31[11] +-CLK_CMT:MUX.MUXBUS30[9]-CLK_CMT:MUX.MUXBUS31[9] 10 -CLK_CMT:MUX.MUXBUS30[3]-CLK_CMT:MUX.MUXBUS31[3]- +CLK_CMT:MUX.MUXBUS30[11]-CLK_CMT:MUX.MUXBUS31[11]- 11 --CLK_CMT:MUX.MUXBUS30[12]-CLK_CMT:MUX.MUXBUS31[12] +-CLK_CMT:MUX.MUXBUS30[6]-CLK_CMT:MUX.MUXBUS31[6] 12 -CLK_CMT:MUX.MUXBUS30[4]-CLK_CMT:MUX.MUXBUS31[4]- +CLK_CMT:MUX.MUXBUS30[8]-CLK_CMT:MUX.MUXBUS31[8]- 13 --CLK_CMT:MUX.MUXBUS30[13]-CLK_CMT:MUX.MUXBUS31[13] +-CLK_CMT:MUX.MUXBUS30[10]-CLK_CMT:MUX.MUXBUS31[10] 14 -CLK_CMT:MUX.MUXBUS30[5]-CLK_CMT:MUX.MUXBUS31[5]- +CLK_CMT:MUX.MUXBUS30[12]-CLK_CMT:MUX.MUXBUS31[12]- 15 ---- 16 @@ -2873,31 +2873,31 @@

    CLK_CMT_T17 ---- 18 --CLK_CMT:MUX.MUXBUS28[6]-CLK_CMT:MUX.MUXBUS29[6] +-CLK_CMT:MUX.MUXBUS28[0]-CLK_CMT:MUX.MUXBUS29[0] 19 ---- 20 ---- 21 -CLK_CMT:MUX.MUXBUS28[0]CLK_CMT:MUX.MUXBUS28[7]CLK_CMT:MUX.MUXBUS29[0]CLK_CMT:MUX.MUXBUS29[7] +CLK_CMT:MUX.MUXBUS28[2]CLK_CMT:MUX.MUXBUS28[1]CLK_CMT:MUX.MUXBUS29[2]CLK_CMT:MUX.MUXBUS29[1] 22 --CLK_CMT:MUX.MUXBUS28[8]-CLK_CMT:MUX.MUXBUS29[8] +-CLK_CMT:MUX.MUXBUS28[5]-CLK_CMT:MUX.MUXBUS29[5] 23 -CLK_CMT:MUX.MUXBUS28[1]CLK_CMT:MUX.MUXBUS28[9]CLK_CMT:MUX.MUXBUS29[1]CLK_CMT:MUX.MUXBUS29[9] +CLK_CMT:MUX.MUXBUS28[3]CLK_CMT:MUX.MUXBUS28[4]CLK_CMT:MUX.MUXBUS29[3]CLK_CMT:MUX.MUXBUS29[4] 24 -CLK_CMT:MUX.MUXBUS28[2]CLK_CMT:MUX.MUXBUS28[10]CLK_CMT:MUX.MUXBUS29[2]CLK_CMT:MUX.MUXBUS29[10] +CLK_CMT:MUX.MUXBUS28[7]CLK_CMT:MUX.MUXBUS28[13]CLK_CMT:MUX.MUXBUS29[7]CLK_CMT:MUX.MUXBUS29[13] 25 --CLK_CMT:MUX.MUXBUS28[11]-CLK_CMT:MUX.MUXBUS29[11] +-CLK_CMT:MUX.MUXBUS28[9]-CLK_CMT:MUX.MUXBUS29[9] 26 -CLK_CMT:MUX.MUXBUS28[3]-CLK_CMT:MUX.MUXBUS29[3]- +CLK_CMT:MUX.MUXBUS28[11]-CLK_CMT:MUX.MUXBUS29[11]- 27 --CLK_CMT:MUX.MUXBUS28[12]-CLK_CMT:MUX.MUXBUS29[12] +-CLK_CMT:MUX.MUXBUS28[6]-CLK_CMT:MUX.MUXBUS29[6] 28 -CLK_CMT:MUX.MUXBUS28[4]-CLK_CMT:MUX.MUXBUS29[4]- +CLK_CMT:MUX.MUXBUS28[8]-CLK_CMT:MUX.MUXBUS29[8]- 29 --CLK_CMT:MUX.MUXBUS28[13]-CLK_CMT:MUX.MUXBUS29[13] +-CLK_CMT:MUX.MUXBUS28[10]-CLK_CMT:MUX.MUXBUS29[10] 30 -CLK_CMT:MUX.MUXBUS28[5]-CLK_CMT:MUX.MUXBUS29[5]- +CLK_CMT:MUX.MUXBUS28[12]-CLK_CMT:MUX.MUXBUS29[12]- 31 ---- 32 @@ -2905,31 +2905,31 @@

    CLK_CMT_T33 ---- 34 --CLK_CMT:MUX.MUXBUS26[6]-CLK_CMT:MUX.MUXBUS27[6] +-CLK_CMT:MUX.MUXBUS26[0]-CLK_CMT:MUX.MUXBUS27[0] 35 ---- 36 ---- 37 -CLK_CMT:MUX.MUXBUS26[0]CLK_CMT:MUX.MUXBUS26[7]CLK_CMT:MUX.MUXBUS27[0]CLK_CMT:MUX.MUXBUS27[7] +CLK_CMT:MUX.MUXBUS26[2]CLK_CMT:MUX.MUXBUS26[1]CLK_CMT:MUX.MUXBUS27[2]CLK_CMT:MUX.MUXBUS27[1] 38 --CLK_CMT:MUX.MUXBUS26[8]-CLK_CMT:MUX.MUXBUS27[8] +-CLK_CMT:MUX.MUXBUS26[5]-CLK_CMT:MUX.MUXBUS27[5] 39 -CLK_CMT:MUX.MUXBUS26[1]CLK_CMT:MUX.MUXBUS26[9]CLK_CMT:MUX.MUXBUS27[1]CLK_CMT:MUX.MUXBUS27[9] +CLK_CMT:MUX.MUXBUS26[3]CLK_CMT:MUX.MUXBUS26[4]CLK_CMT:MUX.MUXBUS27[3]CLK_CMT:MUX.MUXBUS27[4] 40 -CLK_CMT:MUX.MUXBUS26[2]CLK_CMT:MUX.MUXBUS26[10]CLK_CMT:MUX.MUXBUS27[2]CLK_CMT:MUX.MUXBUS27[10] +CLK_CMT:MUX.MUXBUS26[7]CLK_CMT:MUX.MUXBUS26[13]CLK_CMT:MUX.MUXBUS27[7]CLK_CMT:MUX.MUXBUS27[13] 41 --CLK_CMT:MUX.MUXBUS26[11]-CLK_CMT:MUX.MUXBUS27[11] +-CLK_CMT:MUX.MUXBUS26[9]-CLK_CMT:MUX.MUXBUS27[9] 42 -CLK_CMT:MUX.MUXBUS26[3]-CLK_CMT:MUX.MUXBUS27[3]- +CLK_CMT:MUX.MUXBUS26[11]-CLK_CMT:MUX.MUXBUS27[11]- 43 --CLK_CMT:MUX.MUXBUS26[12]-CLK_CMT:MUX.MUXBUS27[12] +-CLK_CMT:MUX.MUXBUS26[6]-CLK_CMT:MUX.MUXBUS27[6] 44 -CLK_CMT:MUX.MUXBUS26[4]-CLK_CMT:MUX.MUXBUS27[4]- +CLK_CMT:MUX.MUXBUS26[8]-CLK_CMT:MUX.MUXBUS27[8]- 45 --CLK_CMT:MUX.MUXBUS26[13]-CLK_CMT:MUX.MUXBUS27[13] +-CLK_CMT:MUX.MUXBUS26[10]-CLK_CMT:MUX.MUXBUS27[10] 46 -CLK_CMT:MUX.MUXBUS26[5]-CLK_CMT:MUX.MUXBUS27[5]- +CLK_CMT:MUX.MUXBUS26[12]-CLK_CMT:MUX.MUXBUS27[12]- 47 ---- 48 @@ -2937,31 +2937,31 @@

    CLK_CMT_T49 ---- 50 --CLK_CMT:MUX.MUXBUS24[6]-CLK_CMT:MUX.MUXBUS25[6] +-CLK_CMT:MUX.MUXBUS24[0]-CLK_CMT:MUX.MUXBUS25[0] 51 ---- 52 ---- 53 -CLK_CMT:MUX.MUXBUS24[0]CLK_CMT:MUX.MUXBUS24[7]CLK_CMT:MUX.MUXBUS25[0]CLK_CMT:MUX.MUXBUS25[7] +CLK_CMT:MUX.MUXBUS24[2]CLK_CMT:MUX.MUXBUS24[1]CLK_CMT:MUX.MUXBUS25[2]CLK_CMT:MUX.MUXBUS25[1] 54 --CLK_CMT:MUX.MUXBUS24[8]-CLK_CMT:MUX.MUXBUS25[8] +-CLK_CMT:MUX.MUXBUS24[5]-CLK_CMT:MUX.MUXBUS25[5] 55 -CLK_CMT:MUX.MUXBUS24[1]CLK_CMT:MUX.MUXBUS24[9]CLK_CMT:MUX.MUXBUS25[1]CLK_CMT:MUX.MUXBUS25[9] +CLK_CMT:MUX.MUXBUS24[3]CLK_CMT:MUX.MUXBUS24[4]CLK_CMT:MUX.MUXBUS25[3]CLK_CMT:MUX.MUXBUS25[4] 56 -CLK_CMT:MUX.MUXBUS24[2]CLK_CMT:MUX.MUXBUS24[10]CLK_CMT:MUX.MUXBUS25[2]CLK_CMT:MUX.MUXBUS25[10] +CLK_CMT:MUX.MUXBUS24[7]CLK_CMT:MUX.MUXBUS24[13]CLK_CMT:MUX.MUXBUS25[7]CLK_CMT:MUX.MUXBUS25[13] 57 --CLK_CMT:MUX.MUXBUS24[11]-CLK_CMT:MUX.MUXBUS25[11] +-CLK_CMT:MUX.MUXBUS24[9]-CLK_CMT:MUX.MUXBUS25[9] 58 -CLK_CMT:MUX.MUXBUS24[3]-CLK_CMT:MUX.MUXBUS25[3]- +CLK_CMT:MUX.MUXBUS24[11]-CLK_CMT:MUX.MUXBUS25[11]- 59 --CLK_CMT:MUX.MUXBUS24[12]-CLK_CMT:MUX.MUXBUS25[12] +-CLK_CMT:MUX.MUXBUS24[6]-CLK_CMT:MUX.MUXBUS25[6] 60 -CLK_CMT:MUX.MUXBUS24[4]-CLK_CMT:MUX.MUXBUS25[4]- +CLK_CMT:MUX.MUXBUS24[8]-CLK_CMT:MUX.MUXBUS25[8]- 61 --CLK_CMT:MUX.MUXBUS24[13]-CLK_CMT:MUX.MUXBUS25[13] +-CLK_CMT:MUX.MUXBUS24[10]-CLK_CMT:MUX.MUXBUS25[10] 62 -CLK_CMT:MUX.MUXBUS24[5]-CLK_CMT:MUX.MUXBUS25[5]- +CLK_CMT:MUX.MUXBUS24[12]-CLK_CMT:MUX.MUXBUS25[12]- @@ -2970,31 +2970,31 @@

    CLK_CMT_T

    - + - + - + - + - + - + - + - + - + - + - + @@ -3002,31 +3002,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3034,31 +3034,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3066,31 +3066,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_T bittile 2
    RowColumn
    0123
    1 ----
    2-CLK_CMT:MUX.MUXBUS22[6]-CLK_CMT:MUX.MUXBUS23[6]
    -CLK_CMT:MUX.MUXBUS22[0]-CLK_CMT:MUX.MUXBUS23[0]
    3 ----
    4 ----
    5CLK_CMT:MUX.MUXBUS22[0]CLK_CMT:MUX.MUXBUS22[7]CLK_CMT:MUX.MUXBUS23[0]CLK_CMT:MUX.MUXBUS23[7]
    CLK_CMT:MUX.MUXBUS22[2]CLK_CMT:MUX.MUXBUS22[1]CLK_CMT:MUX.MUXBUS23[2]CLK_CMT:MUX.MUXBUS23[1]
    6-CLK_CMT:MUX.MUXBUS22[8]-CLK_CMT:MUX.MUXBUS23[8]
    -CLK_CMT:MUX.MUXBUS22[5]-CLK_CMT:MUX.MUXBUS23[5]
    7CLK_CMT:MUX.MUXBUS22[1]CLK_CMT:MUX.MUXBUS22[9]CLK_CMT:MUX.MUXBUS23[1]CLK_CMT:MUX.MUXBUS23[9]
    CLK_CMT:MUX.MUXBUS22[3]CLK_CMT:MUX.MUXBUS22[4]CLK_CMT:MUX.MUXBUS23[3]CLK_CMT:MUX.MUXBUS23[4]
    8CLK_CMT:MUX.MUXBUS22[2]CLK_CMT:MUX.MUXBUS22[10]CLK_CMT:MUX.MUXBUS23[2]CLK_CMT:MUX.MUXBUS23[10]
    CLK_CMT:MUX.MUXBUS22[7]CLK_CMT:MUX.MUXBUS22[13]CLK_CMT:MUX.MUXBUS23[7]CLK_CMT:MUX.MUXBUS23[13]
    9-CLK_CMT:MUX.MUXBUS22[11]-CLK_CMT:MUX.MUXBUS23[11]
    -CLK_CMT:MUX.MUXBUS22[9]-CLK_CMT:MUX.MUXBUS23[9]
    10CLK_CMT:MUX.MUXBUS22[3]-CLK_CMT:MUX.MUXBUS23[3]-
    CLK_CMT:MUX.MUXBUS22[11]-CLK_CMT:MUX.MUXBUS23[11]-
    11-CLK_CMT:MUX.MUXBUS22[12]-CLK_CMT:MUX.MUXBUS23[12]
    -CLK_CMT:MUX.MUXBUS22[6]-CLK_CMT:MUX.MUXBUS23[6]
    12CLK_CMT:MUX.MUXBUS22[4]-CLK_CMT:MUX.MUXBUS23[4]-
    CLK_CMT:MUX.MUXBUS22[8]-CLK_CMT:MUX.MUXBUS23[8]-
    13-CLK_CMT:MUX.MUXBUS22[13]-CLK_CMT:MUX.MUXBUS23[13]
    -CLK_CMT:MUX.MUXBUS22[10]-CLK_CMT:MUX.MUXBUS23[10]
    14CLK_CMT:MUX.MUXBUS22[5]-CLK_CMT:MUX.MUXBUS23[5]-
    CLK_CMT:MUX.MUXBUS22[12]-CLK_CMT:MUX.MUXBUS23[12]-
    15 ----
    1617 ----
    18-CLK_CMT:MUX.MUXBUS20[6]-CLK_CMT:MUX.MUXBUS21[6]
    -CLK_CMT:MUX.MUXBUS20[0]-CLK_CMT:MUX.MUXBUS21[0]
    19 ----
    20 ----
    21CLK_CMT:MUX.MUXBUS20[0]CLK_CMT:MUX.MUXBUS20[7]CLK_CMT:MUX.MUXBUS21[0]CLK_CMT:MUX.MUXBUS21[7]
    CLK_CMT:MUX.MUXBUS20[2]CLK_CMT:MUX.MUXBUS20[1]CLK_CMT:MUX.MUXBUS21[2]CLK_CMT:MUX.MUXBUS21[1]
    22-CLK_CMT:MUX.MUXBUS20[8]-CLK_CMT:MUX.MUXBUS21[8]
    -CLK_CMT:MUX.MUXBUS20[5]-CLK_CMT:MUX.MUXBUS21[5]
    23CLK_CMT:MUX.MUXBUS20[1]CLK_CMT:MUX.MUXBUS20[9]CLK_CMT:MUX.MUXBUS21[1]CLK_CMT:MUX.MUXBUS21[9]
    CLK_CMT:MUX.MUXBUS20[3]CLK_CMT:MUX.MUXBUS20[4]CLK_CMT:MUX.MUXBUS21[3]CLK_CMT:MUX.MUXBUS21[4]
    24CLK_CMT:MUX.MUXBUS20[2]CLK_CMT:MUX.MUXBUS20[10]CLK_CMT:MUX.MUXBUS21[2]CLK_CMT:MUX.MUXBUS21[10]
    CLK_CMT:MUX.MUXBUS20[7]CLK_CMT:MUX.MUXBUS20[13]CLK_CMT:MUX.MUXBUS21[7]CLK_CMT:MUX.MUXBUS21[13]
    25-CLK_CMT:MUX.MUXBUS20[11]-CLK_CMT:MUX.MUXBUS21[11]
    -CLK_CMT:MUX.MUXBUS20[9]-CLK_CMT:MUX.MUXBUS21[9]
    26CLK_CMT:MUX.MUXBUS20[3]-CLK_CMT:MUX.MUXBUS21[3]-
    CLK_CMT:MUX.MUXBUS20[11]-CLK_CMT:MUX.MUXBUS21[11]-
    27-CLK_CMT:MUX.MUXBUS20[12]-CLK_CMT:MUX.MUXBUS21[12]
    -CLK_CMT:MUX.MUXBUS20[6]-CLK_CMT:MUX.MUXBUS21[6]
    28CLK_CMT:MUX.MUXBUS20[4]-CLK_CMT:MUX.MUXBUS21[4]-
    CLK_CMT:MUX.MUXBUS20[8]-CLK_CMT:MUX.MUXBUS21[8]-
    29-CLK_CMT:MUX.MUXBUS20[13]-CLK_CMT:MUX.MUXBUS21[13]
    -CLK_CMT:MUX.MUXBUS20[10]-CLK_CMT:MUX.MUXBUS21[10]
    30CLK_CMT:MUX.MUXBUS20[5]-CLK_CMT:MUX.MUXBUS21[5]-
    CLK_CMT:MUX.MUXBUS20[12]-CLK_CMT:MUX.MUXBUS21[12]-
    31 ----
    3233 ----
    34-CLK_CMT:MUX.MUXBUS18[6]-CLK_CMT:MUX.MUXBUS19[6]
    -CLK_CMT:MUX.MUXBUS18[0]-CLK_CMT:MUX.MUXBUS19[0]
    35 ----
    36 ----
    37CLK_CMT:MUX.MUXBUS18[0]CLK_CMT:MUX.MUXBUS18[7]CLK_CMT:MUX.MUXBUS19[0]CLK_CMT:MUX.MUXBUS19[7]
    CLK_CMT:MUX.MUXBUS18[2]CLK_CMT:MUX.MUXBUS18[1]CLK_CMT:MUX.MUXBUS19[2]CLK_CMT:MUX.MUXBUS19[1]
    38-CLK_CMT:MUX.MUXBUS18[8]-CLK_CMT:MUX.MUXBUS19[8]
    -CLK_CMT:MUX.MUXBUS18[5]-CLK_CMT:MUX.MUXBUS19[5]
    39CLK_CMT:MUX.MUXBUS18[1]CLK_CMT:MUX.MUXBUS18[9]CLK_CMT:MUX.MUXBUS19[1]CLK_CMT:MUX.MUXBUS19[9]
    CLK_CMT:MUX.MUXBUS18[3]CLK_CMT:MUX.MUXBUS18[4]CLK_CMT:MUX.MUXBUS19[3]CLK_CMT:MUX.MUXBUS19[4]
    40CLK_CMT:MUX.MUXBUS18[2]CLK_CMT:MUX.MUXBUS18[10]CLK_CMT:MUX.MUXBUS19[2]CLK_CMT:MUX.MUXBUS19[10]
    CLK_CMT:MUX.MUXBUS18[7]CLK_CMT:MUX.MUXBUS18[13]CLK_CMT:MUX.MUXBUS19[7]CLK_CMT:MUX.MUXBUS19[13]
    41-CLK_CMT:MUX.MUXBUS18[11]-CLK_CMT:MUX.MUXBUS19[11]
    -CLK_CMT:MUX.MUXBUS18[9]-CLK_CMT:MUX.MUXBUS19[9]
    42CLK_CMT:MUX.MUXBUS18[3]-CLK_CMT:MUX.MUXBUS19[3]-
    CLK_CMT:MUX.MUXBUS18[11]-CLK_CMT:MUX.MUXBUS19[11]-
    43-CLK_CMT:MUX.MUXBUS18[12]-CLK_CMT:MUX.MUXBUS19[12]
    -CLK_CMT:MUX.MUXBUS18[6]-CLK_CMT:MUX.MUXBUS19[6]
    44CLK_CMT:MUX.MUXBUS18[4]-CLK_CMT:MUX.MUXBUS19[4]-
    CLK_CMT:MUX.MUXBUS18[8]-CLK_CMT:MUX.MUXBUS19[8]-
    45-CLK_CMT:MUX.MUXBUS18[13]-CLK_CMT:MUX.MUXBUS19[13]
    -CLK_CMT:MUX.MUXBUS18[10]-CLK_CMT:MUX.MUXBUS19[10]
    46CLK_CMT:MUX.MUXBUS18[5]-CLK_CMT:MUX.MUXBUS19[5]-
    CLK_CMT:MUX.MUXBUS18[12]-CLK_CMT:MUX.MUXBUS19[12]-
    47 ----
    4849 ----
    50-CLK_CMT:MUX.MUXBUS16[6]-CLK_CMT:MUX.MUXBUS17[6]
    -CLK_CMT:MUX.MUXBUS16[0]-CLK_CMT:MUX.MUXBUS17[0]
    51 ----
    52 ----
    53CLK_CMT:MUX.MUXBUS16[0]CLK_CMT:MUX.MUXBUS16[7]CLK_CMT:MUX.MUXBUS17[0]CLK_CMT:MUX.MUXBUS17[7]
    CLK_CMT:MUX.MUXBUS16[2]CLK_CMT:MUX.MUXBUS16[1]CLK_CMT:MUX.MUXBUS17[2]CLK_CMT:MUX.MUXBUS17[1]
    54-CLK_CMT:MUX.MUXBUS16[8]-CLK_CMT:MUX.MUXBUS17[8]
    -CLK_CMT:MUX.MUXBUS16[5]-CLK_CMT:MUX.MUXBUS17[5]
    55CLK_CMT:MUX.MUXBUS16[1]CLK_CMT:MUX.MUXBUS16[9]CLK_CMT:MUX.MUXBUS17[1]CLK_CMT:MUX.MUXBUS17[9]
    CLK_CMT:MUX.MUXBUS16[3]CLK_CMT:MUX.MUXBUS16[4]CLK_CMT:MUX.MUXBUS17[3]CLK_CMT:MUX.MUXBUS17[4]
    56CLK_CMT:MUX.MUXBUS16[2]CLK_CMT:MUX.MUXBUS16[10]CLK_CMT:MUX.MUXBUS17[2]CLK_CMT:MUX.MUXBUS17[10]
    CLK_CMT:MUX.MUXBUS16[7]CLK_CMT:MUX.MUXBUS16[13]CLK_CMT:MUX.MUXBUS17[7]CLK_CMT:MUX.MUXBUS17[13]
    57-CLK_CMT:MUX.MUXBUS16[11]-CLK_CMT:MUX.MUXBUS17[11]
    -CLK_CMT:MUX.MUXBUS16[9]-CLK_CMT:MUX.MUXBUS17[9]
    58CLK_CMT:MUX.MUXBUS16[3]-CLK_CMT:MUX.MUXBUS17[3]-
    CLK_CMT:MUX.MUXBUS16[11]-CLK_CMT:MUX.MUXBUS17[11]-
    59-CLK_CMT:MUX.MUXBUS16[12]-CLK_CMT:MUX.MUXBUS17[12]
    -CLK_CMT:MUX.MUXBUS16[6]-CLK_CMT:MUX.MUXBUS17[6]
    60CLK_CMT:MUX.MUXBUS16[4]-CLK_CMT:MUX.MUXBUS17[4]-
    CLK_CMT:MUX.MUXBUS16[8]-CLK_CMT:MUX.MUXBUS17[8]-
    61-CLK_CMT:MUX.MUXBUS16[13]-CLK_CMT:MUX.MUXBUS17[13]
    -CLK_CMT:MUX.MUXBUS16[10]-CLK_CMT:MUX.MUXBUS17[10]
    62CLK_CMT:MUX.MUXBUS16[5]-CLK_CMT:MUX.MUXBUS17[5]-
    CLK_CMT:MUX.MUXBUS16[12]-CLK_CMT:MUX.MUXBUS17[12]-
    @@ -3099,31 +3099,31 @@

    CLK_CMT_T

    - + - + - + - + - + - + - + - + - + - + - + @@ -3131,31 +3131,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3163,31 +3163,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3195,31 +3195,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_T bittile 3
    RowColumn
    0123
    1 ----
    2-CLK_CMT:MUX.MUXBUS14[6]-CLK_CMT:MUX.MUXBUS15[6]
    -CLK_CMT:MUX.MUXBUS14[0]-CLK_CMT:MUX.MUXBUS15[0]
    3 ----
    4 ----
    5CLK_CMT:MUX.MUXBUS14[0]CLK_CMT:MUX.MUXBUS14[7]CLK_CMT:MUX.MUXBUS15[0]CLK_CMT:MUX.MUXBUS15[7]
    CLK_CMT:MUX.MUXBUS14[2]CLK_CMT:MUX.MUXBUS14[1]CLK_CMT:MUX.MUXBUS15[2]CLK_CMT:MUX.MUXBUS15[1]
    6-CLK_CMT:MUX.MUXBUS14[8]-CLK_CMT:MUX.MUXBUS15[8]
    -CLK_CMT:MUX.MUXBUS14[5]-CLK_CMT:MUX.MUXBUS15[5]
    7CLK_CMT:MUX.MUXBUS14[1]CLK_CMT:MUX.MUXBUS14[9]CLK_CMT:MUX.MUXBUS15[1]CLK_CMT:MUX.MUXBUS15[9]
    CLK_CMT:MUX.MUXBUS14[3]CLK_CMT:MUX.MUXBUS14[4]CLK_CMT:MUX.MUXBUS15[3]CLK_CMT:MUX.MUXBUS15[4]
    8CLK_CMT:MUX.MUXBUS14[2]CLK_CMT:MUX.MUXBUS14[10]CLK_CMT:MUX.MUXBUS15[2]CLK_CMT:MUX.MUXBUS15[10]
    CLK_CMT:MUX.MUXBUS14[7]CLK_CMT:MUX.MUXBUS14[13]CLK_CMT:MUX.MUXBUS15[7]CLK_CMT:MUX.MUXBUS15[13]
    9-CLK_CMT:MUX.MUXBUS14[11]-CLK_CMT:MUX.MUXBUS15[11]
    -CLK_CMT:MUX.MUXBUS14[9]-CLK_CMT:MUX.MUXBUS15[9]
    10CLK_CMT:MUX.MUXBUS14[3]-CLK_CMT:MUX.MUXBUS15[3]-
    CLK_CMT:MUX.MUXBUS14[11]-CLK_CMT:MUX.MUXBUS15[11]-
    11-CLK_CMT:MUX.MUXBUS14[12]-CLK_CMT:MUX.MUXBUS15[12]
    -CLK_CMT:MUX.MUXBUS14[6]-CLK_CMT:MUX.MUXBUS15[6]
    12CLK_CMT:MUX.MUXBUS14[4]-CLK_CMT:MUX.MUXBUS15[4]-
    CLK_CMT:MUX.MUXBUS14[8]-CLK_CMT:MUX.MUXBUS15[8]-
    13-CLK_CMT:MUX.MUXBUS14[13]-CLK_CMT:MUX.MUXBUS15[13]
    -CLK_CMT:MUX.MUXBUS14[10]-CLK_CMT:MUX.MUXBUS15[10]
    14CLK_CMT:MUX.MUXBUS14[5]-CLK_CMT:MUX.MUXBUS15[5]-
    CLK_CMT:MUX.MUXBUS14[12]-CLK_CMT:MUX.MUXBUS15[12]-
    15 ----
    1617 ----
    18-CLK_CMT:MUX.MUXBUS12[6]-CLK_CMT:MUX.MUXBUS13[6]
    -CLK_CMT:MUX.MUXBUS12[0]-CLK_CMT:MUX.MUXBUS13[0]
    19 ----
    20 ----
    21CLK_CMT:MUX.MUXBUS12[0]CLK_CMT:MUX.MUXBUS12[7]CLK_CMT:MUX.MUXBUS13[0]CLK_CMT:MUX.MUXBUS13[7]
    CLK_CMT:MUX.MUXBUS12[2]CLK_CMT:MUX.MUXBUS12[1]CLK_CMT:MUX.MUXBUS13[2]CLK_CMT:MUX.MUXBUS13[1]
    22-CLK_CMT:MUX.MUXBUS12[8]-CLK_CMT:MUX.MUXBUS13[8]
    -CLK_CMT:MUX.MUXBUS12[5]-CLK_CMT:MUX.MUXBUS13[5]
    23CLK_CMT:MUX.MUXBUS12[1]CLK_CMT:MUX.MUXBUS12[9]CLK_CMT:MUX.MUXBUS13[1]CLK_CMT:MUX.MUXBUS13[9]
    CLK_CMT:MUX.MUXBUS12[3]CLK_CMT:MUX.MUXBUS12[4]CLK_CMT:MUX.MUXBUS13[3]CLK_CMT:MUX.MUXBUS13[4]
    24CLK_CMT:MUX.MUXBUS12[2]CLK_CMT:MUX.MUXBUS12[10]CLK_CMT:MUX.MUXBUS13[2]CLK_CMT:MUX.MUXBUS13[10]
    CLK_CMT:MUX.MUXBUS12[7]CLK_CMT:MUX.MUXBUS12[13]CLK_CMT:MUX.MUXBUS13[7]CLK_CMT:MUX.MUXBUS13[13]
    25-CLK_CMT:MUX.MUXBUS12[11]-CLK_CMT:MUX.MUXBUS13[11]
    -CLK_CMT:MUX.MUXBUS12[9]-CLK_CMT:MUX.MUXBUS13[9]
    26CLK_CMT:MUX.MUXBUS12[3]-CLK_CMT:MUX.MUXBUS13[3]-
    CLK_CMT:MUX.MUXBUS12[11]-CLK_CMT:MUX.MUXBUS13[11]-
    27-CLK_CMT:MUX.MUXBUS12[12]-CLK_CMT:MUX.MUXBUS13[12]
    -CLK_CMT:MUX.MUXBUS12[6]-CLK_CMT:MUX.MUXBUS13[6]
    28CLK_CMT:MUX.MUXBUS12[4]-CLK_CMT:MUX.MUXBUS13[4]-
    CLK_CMT:MUX.MUXBUS12[8]-CLK_CMT:MUX.MUXBUS13[8]-
    29-CLK_CMT:MUX.MUXBUS12[13]-CLK_CMT:MUX.MUXBUS13[13]
    -CLK_CMT:MUX.MUXBUS12[10]-CLK_CMT:MUX.MUXBUS13[10]
    30CLK_CMT:MUX.MUXBUS12[5]-CLK_CMT:MUX.MUXBUS13[5]-
    CLK_CMT:MUX.MUXBUS12[12]-CLK_CMT:MUX.MUXBUS13[12]-
    31 ----
    3233 ----
    34-CLK_CMT:MUX.MUXBUS10[6]-CLK_CMT:MUX.MUXBUS11[6]
    -CLK_CMT:MUX.MUXBUS10[0]-CLK_CMT:MUX.MUXBUS11[0]
    35 ----
    36 ----
    37CLK_CMT:MUX.MUXBUS10[0]CLK_CMT:MUX.MUXBUS10[7]CLK_CMT:MUX.MUXBUS11[0]CLK_CMT:MUX.MUXBUS11[7]
    CLK_CMT:MUX.MUXBUS10[2]CLK_CMT:MUX.MUXBUS10[1]CLK_CMT:MUX.MUXBUS11[2]CLK_CMT:MUX.MUXBUS11[1]
    38-CLK_CMT:MUX.MUXBUS10[8]-CLK_CMT:MUX.MUXBUS11[8]
    -CLK_CMT:MUX.MUXBUS10[5]-CLK_CMT:MUX.MUXBUS11[5]
    39CLK_CMT:MUX.MUXBUS10[1]CLK_CMT:MUX.MUXBUS10[9]CLK_CMT:MUX.MUXBUS11[1]CLK_CMT:MUX.MUXBUS11[9]
    CLK_CMT:MUX.MUXBUS10[3]CLK_CMT:MUX.MUXBUS10[4]CLK_CMT:MUX.MUXBUS11[3]CLK_CMT:MUX.MUXBUS11[4]
    40CLK_CMT:MUX.MUXBUS10[2]CLK_CMT:MUX.MUXBUS10[10]CLK_CMT:MUX.MUXBUS11[2]CLK_CMT:MUX.MUXBUS11[10]
    CLK_CMT:MUX.MUXBUS10[7]CLK_CMT:MUX.MUXBUS10[13]CLK_CMT:MUX.MUXBUS11[7]CLK_CMT:MUX.MUXBUS11[13]
    41-CLK_CMT:MUX.MUXBUS10[11]-CLK_CMT:MUX.MUXBUS11[11]
    -CLK_CMT:MUX.MUXBUS10[9]-CLK_CMT:MUX.MUXBUS11[9]
    42CLK_CMT:MUX.MUXBUS10[3]-CLK_CMT:MUX.MUXBUS11[3]-
    CLK_CMT:MUX.MUXBUS10[11]-CLK_CMT:MUX.MUXBUS11[11]-
    43-CLK_CMT:MUX.MUXBUS10[12]-CLK_CMT:MUX.MUXBUS11[12]
    -CLK_CMT:MUX.MUXBUS10[6]-CLK_CMT:MUX.MUXBUS11[6]
    44CLK_CMT:MUX.MUXBUS10[4]-CLK_CMT:MUX.MUXBUS11[4]-
    CLK_CMT:MUX.MUXBUS10[8]-CLK_CMT:MUX.MUXBUS11[8]-
    45-CLK_CMT:MUX.MUXBUS10[13]-CLK_CMT:MUX.MUXBUS11[13]
    -CLK_CMT:MUX.MUXBUS10[10]-CLK_CMT:MUX.MUXBUS11[10]
    46CLK_CMT:MUX.MUXBUS10[5]-CLK_CMT:MUX.MUXBUS11[5]-
    CLK_CMT:MUX.MUXBUS10[12]-CLK_CMT:MUX.MUXBUS11[12]-
    47 ----
    4849 ----
    50-CLK_CMT:MUX.MUXBUS8[6]-CLK_CMT:MUX.MUXBUS9[6]
    -CLK_CMT:MUX.MUXBUS8[0]-CLK_CMT:MUX.MUXBUS9[0]
    51 ----
    52 ----
    53CLK_CMT:MUX.MUXBUS8[0]CLK_CMT:MUX.MUXBUS8[7]CLK_CMT:MUX.MUXBUS9[0]CLK_CMT:MUX.MUXBUS9[7]
    CLK_CMT:MUX.MUXBUS8[2]CLK_CMT:MUX.MUXBUS8[1]CLK_CMT:MUX.MUXBUS9[2]CLK_CMT:MUX.MUXBUS9[1]
    54-CLK_CMT:MUX.MUXBUS8[8]-CLK_CMT:MUX.MUXBUS9[8]
    -CLK_CMT:MUX.MUXBUS8[5]-CLK_CMT:MUX.MUXBUS9[5]
    55CLK_CMT:MUX.MUXBUS8[1]CLK_CMT:MUX.MUXBUS8[9]CLK_CMT:MUX.MUXBUS9[1]CLK_CMT:MUX.MUXBUS9[9]
    CLK_CMT:MUX.MUXBUS8[3]CLK_CMT:MUX.MUXBUS8[4]CLK_CMT:MUX.MUXBUS9[3]CLK_CMT:MUX.MUXBUS9[4]
    56CLK_CMT:MUX.MUXBUS8[2]CLK_CMT:MUX.MUXBUS8[10]CLK_CMT:MUX.MUXBUS9[2]CLK_CMT:MUX.MUXBUS9[10]
    CLK_CMT:MUX.MUXBUS8[7]CLK_CMT:MUX.MUXBUS8[13]CLK_CMT:MUX.MUXBUS9[7]CLK_CMT:MUX.MUXBUS9[13]
    57-CLK_CMT:MUX.MUXBUS8[11]-CLK_CMT:MUX.MUXBUS9[11]
    -CLK_CMT:MUX.MUXBUS8[9]-CLK_CMT:MUX.MUXBUS9[9]
    58CLK_CMT:MUX.MUXBUS8[3]-CLK_CMT:MUX.MUXBUS9[3]-
    CLK_CMT:MUX.MUXBUS8[11]-CLK_CMT:MUX.MUXBUS9[11]-
    59-CLK_CMT:MUX.MUXBUS8[12]-CLK_CMT:MUX.MUXBUS9[12]
    -CLK_CMT:MUX.MUXBUS8[6]-CLK_CMT:MUX.MUXBUS9[6]
    60CLK_CMT:MUX.MUXBUS8[4]-CLK_CMT:MUX.MUXBUS9[4]-
    CLK_CMT:MUX.MUXBUS8[8]-CLK_CMT:MUX.MUXBUS9[8]-
    61-CLK_CMT:MUX.MUXBUS8[13]-CLK_CMT:MUX.MUXBUS9[13]
    -CLK_CMT:MUX.MUXBUS8[10]-CLK_CMT:MUX.MUXBUS9[10]
    62CLK_CMT:MUX.MUXBUS8[5]-CLK_CMT:MUX.MUXBUS9[5]-
    CLK_CMT:MUX.MUXBUS8[12]-CLK_CMT:MUX.MUXBUS9[12]-
    @@ -3228,31 +3228,31 @@

    CLK_CMT_T

    - + - + - + - + - + - + - + - + - + - + - + @@ -3260,31 +3260,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3292,31 +3292,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - + @@ -3324,31 +3324,31 @@

    CLK_CMT_T

     - + - + - + - + - + - + - + - + - + - + - +
    CLK_CMT_T bittile 4
    RowColumn
    0123
    1 ----
    2-CLK_CMT:MUX.MUXBUS6[6]-CLK_CMT:MUX.MUXBUS7[6]
    -CLK_CMT:MUX.MUXBUS6[0]-CLK_CMT:MUX.MUXBUS7[0]
    3 ----
    4 ----
    5CLK_CMT:MUX.MUXBUS6[0]CLK_CMT:MUX.MUXBUS6[7]CLK_CMT:MUX.MUXBUS7[0]CLK_CMT:MUX.MUXBUS7[7]
    CLK_CMT:MUX.MUXBUS6[2]CLK_CMT:MUX.MUXBUS6[1]CLK_CMT:MUX.MUXBUS7[2]CLK_CMT:MUX.MUXBUS7[1]
    6-CLK_CMT:MUX.MUXBUS6[8]-CLK_CMT:MUX.MUXBUS7[8]
    -CLK_CMT:MUX.MUXBUS6[5]-CLK_CMT:MUX.MUXBUS7[5]
    7CLK_CMT:MUX.MUXBUS6[1]CLK_CMT:MUX.MUXBUS6[9]CLK_CMT:MUX.MUXBUS7[1]CLK_CMT:MUX.MUXBUS7[9]
    CLK_CMT:MUX.MUXBUS6[3]CLK_CMT:MUX.MUXBUS6[4]CLK_CMT:MUX.MUXBUS7[3]CLK_CMT:MUX.MUXBUS7[4]
    8CLK_CMT:MUX.MUXBUS6[2]CLK_CMT:MUX.MUXBUS6[10]CLK_CMT:MUX.MUXBUS7[2]CLK_CMT:MUX.MUXBUS7[10]
    CLK_CMT:MUX.MUXBUS6[7]CLK_CMT:MUX.MUXBUS6[13]CLK_CMT:MUX.MUXBUS7[7]CLK_CMT:MUX.MUXBUS7[13]
    9-CLK_CMT:MUX.MUXBUS6[11]-CLK_CMT:MUX.MUXBUS7[11]
    -CLK_CMT:MUX.MUXBUS6[9]-CLK_CMT:MUX.MUXBUS7[9]
    10CLK_CMT:MUX.MUXBUS6[3]-CLK_CMT:MUX.MUXBUS7[3]-
    CLK_CMT:MUX.MUXBUS6[11]-CLK_CMT:MUX.MUXBUS7[11]-
    11-CLK_CMT:MUX.MUXBUS6[12]-CLK_CMT:MUX.MUXBUS7[12]
    -CLK_CMT:MUX.MUXBUS6[6]-CLK_CMT:MUX.MUXBUS7[6]
    12CLK_CMT:MUX.MUXBUS6[4]-CLK_CMT:MUX.MUXBUS7[4]-
    CLK_CMT:MUX.MUXBUS6[8]-CLK_CMT:MUX.MUXBUS7[8]-
    13-CLK_CMT:MUX.MUXBUS6[13]-CLK_CMT:MUX.MUXBUS7[13]
    -CLK_CMT:MUX.MUXBUS6[10]-CLK_CMT:MUX.MUXBUS7[10]
    14CLK_CMT:MUX.MUXBUS6[5]-CLK_CMT:MUX.MUXBUS7[5]-
    CLK_CMT:MUX.MUXBUS6[12]-CLK_CMT:MUX.MUXBUS7[12]-
    15 ----
    1617 ----
    18-CLK_CMT:MUX.MUXBUS4[6]-CLK_CMT:MUX.MUXBUS5[6]
    -CLK_CMT:MUX.MUXBUS4[0]-CLK_CMT:MUX.MUXBUS5[0]
    19 ----
    20 ----
    21CLK_CMT:MUX.MUXBUS4[0]CLK_CMT:MUX.MUXBUS4[7]CLK_CMT:MUX.MUXBUS5[0]CLK_CMT:MUX.MUXBUS5[7]
    CLK_CMT:MUX.MUXBUS4[2]CLK_CMT:MUX.MUXBUS4[1]CLK_CMT:MUX.MUXBUS5[2]CLK_CMT:MUX.MUXBUS5[1]
    22-CLK_CMT:MUX.MUXBUS4[8]-CLK_CMT:MUX.MUXBUS5[8]
    -CLK_CMT:MUX.MUXBUS4[5]-CLK_CMT:MUX.MUXBUS5[5]
    23CLK_CMT:MUX.MUXBUS4[1]CLK_CMT:MUX.MUXBUS4[9]CLK_CMT:MUX.MUXBUS5[1]CLK_CMT:MUX.MUXBUS5[9]
    CLK_CMT:MUX.MUXBUS4[3]CLK_CMT:MUX.MUXBUS4[4]CLK_CMT:MUX.MUXBUS5[3]CLK_CMT:MUX.MUXBUS5[4]
    24CLK_CMT:MUX.MUXBUS4[2]CLK_CMT:MUX.MUXBUS4[10]CLK_CMT:MUX.MUXBUS5[2]CLK_CMT:MUX.MUXBUS5[10]
    CLK_CMT:MUX.MUXBUS4[7]CLK_CMT:MUX.MUXBUS4[13]CLK_CMT:MUX.MUXBUS5[7]CLK_CMT:MUX.MUXBUS5[13]
    25-CLK_CMT:MUX.MUXBUS4[11]-CLK_CMT:MUX.MUXBUS5[11]
    -CLK_CMT:MUX.MUXBUS4[9]-CLK_CMT:MUX.MUXBUS5[9]
    26CLK_CMT:MUX.MUXBUS4[3]-CLK_CMT:MUX.MUXBUS5[3]-
    CLK_CMT:MUX.MUXBUS4[11]-CLK_CMT:MUX.MUXBUS5[11]-
    27-CLK_CMT:MUX.MUXBUS4[12]-CLK_CMT:MUX.MUXBUS5[12]
    -CLK_CMT:MUX.MUXBUS4[6]-CLK_CMT:MUX.MUXBUS5[6]
    28CLK_CMT:MUX.MUXBUS4[4]-CLK_CMT:MUX.MUXBUS5[4]-
    CLK_CMT:MUX.MUXBUS4[8]-CLK_CMT:MUX.MUXBUS5[8]-
    29-CLK_CMT:MUX.MUXBUS4[13]-CLK_CMT:MUX.MUXBUS5[13]
    -CLK_CMT:MUX.MUXBUS4[10]-CLK_CMT:MUX.MUXBUS5[10]
    30CLK_CMT:MUX.MUXBUS4[5]-CLK_CMT:MUX.MUXBUS5[5]-
    CLK_CMT:MUX.MUXBUS4[12]-CLK_CMT:MUX.MUXBUS5[12]-
    31 ----
    3233 ----
    34-CLK_CMT:MUX.MUXBUS2[6]-CLK_CMT:MUX.MUXBUS3[6]
    -CLK_CMT:MUX.MUXBUS2[0]-CLK_CMT:MUX.MUXBUS3[0]
    35 ----
    36 ----
    37CLK_CMT:MUX.MUXBUS2[0]CLK_CMT:MUX.MUXBUS2[7]CLK_CMT:MUX.MUXBUS3[0]CLK_CMT:MUX.MUXBUS3[7]
    CLK_CMT:MUX.MUXBUS2[2]CLK_CMT:MUX.MUXBUS2[1]CLK_CMT:MUX.MUXBUS3[2]CLK_CMT:MUX.MUXBUS3[1]
    38-CLK_CMT:MUX.MUXBUS2[8]-CLK_CMT:MUX.MUXBUS3[8]
    -CLK_CMT:MUX.MUXBUS2[5]-CLK_CMT:MUX.MUXBUS3[5]
    39CLK_CMT:MUX.MUXBUS2[1]CLK_CMT:MUX.MUXBUS2[9]CLK_CMT:MUX.MUXBUS3[1]CLK_CMT:MUX.MUXBUS3[9]
    CLK_CMT:MUX.MUXBUS2[3]CLK_CMT:MUX.MUXBUS2[4]CLK_CMT:MUX.MUXBUS3[3]CLK_CMT:MUX.MUXBUS3[4]
    40CLK_CMT:MUX.MUXBUS2[2]CLK_CMT:MUX.MUXBUS2[10]CLK_CMT:MUX.MUXBUS3[2]CLK_CMT:MUX.MUXBUS3[10]
    CLK_CMT:MUX.MUXBUS2[7]CLK_CMT:MUX.MUXBUS2[13]CLK_CMT:MUX.MUXBUS3[7]CLK_CMT:MUX.MUXBUS3[13]
    41-CLK_CMT:MUX.MUXBUS2[11]-CLK_CMT:MUX.MUXBUS3[11]
    -CLK_CMT:MUX.MUXBUS2[9]-CLK_CMT:MUX.MUXBUS3[9]
    42CLK_CMT:MUX.MUXBUS2[3]-CLK_CMT:MUX.MUXBUS3[3]-
    CLK_CMT:MUX.MUXBUS2[11]-CLK_CMT:MUX.MUXBUS3[11]-
    43-CLK_CMT:MUX.MUXBUS2[12]-CLK_CMT:MUX.MUXBUS3[12]
    -CLK_CMT:MUX.MUXBUS2[6]-CLK_CMT:MUX.MUXBUS3[6]
    44CLK_CMT:MUX.MUXBUS2[4]-CLK_CMT:MUX.MUXBUS3[4]-
    CLK_CMT:MUX.MUXBUS2[8]-CLK_CMT:MUX.MUXBUS3[8]-
    45-CLK_CMT:MUX.MUXBUS2[13]-CLK_CMT:MUX.MUXBUS3[13]
    -CLK_CMT:MUX.MUXBUS2[10]-CLK_CMT:MUX.MUXBUS3[10]
    46CLK_CMT:MUX.MUXBUS2[5]-CLK_CMT:MUX.MUXBUS3[5]-
    CLK_CMT:MUX.MUXBUS2[12]-CLK_CMT:MUX.MUXBUS3[12]-
    47 ----
    4849 ----
    50-CLK_CMT:MUX.MUXBUS0[6]-CLK_CMT:MUX.MUXBUS1[6]
    -CLK_CMT:MUX.MUXBUS0[0]-CLK_CMT:MUX.MUXBUS1[0]
    51 ----
    52 ----
    53CLK_CMT:MUX.MUXBUS0[0]CLK_CMT:MUX.MUXBUS0[7]CLK_CMT:MUX.MUXBUS1[0]CLK_CMT:MUX.MUXBUS1[7]
    CLK_CMT:MUX.MUXBUS0[2]CLK_CMT:MUX.MUXBUS0[1]CLK_CMT:MUX.MUXBUS1[2]CLK_CMT:MUX.MUXBUS1[1]
    54-CLK_CMT:MUX.MUXBUS0[8]-CLK_CMT:MUX.MUXBUS1[8]
    -CLK_CMT:MUX.MUXBUS0[5]-CLK_CMT:MUX.MUXBUS1[5]
    55CLK_CMT:MUX.MUXBUS0[1]CLK_CMT:MUX.MUXBUS0[9]CLK_CMT:MUX.MUXBUS1[1]CLK_CMT:MUX.MUXBUS1[9]
    CLK_CMT:MUX.MUXBUS0[3]CLK_CMT:MUX.MUXBUS0[4]CLK_CMT:MUX.MUXBUS1[3]CLK_CMT:MUX.MUXBUS1[4]
    56CLK_CMT:MUX.MUXBUS0[2]CLK_CMT:MUX.MUXBUS0[10]CLK_CMT:MUX.MUXBUS1[2]CLK_CMT:MUX.MUXBUS1[10]
    CLK_CMT:MUX.MUXBUS0[7]CLK_CMT:MUX.MUXBUS0[13]CLK_CMT:MUX.MUXBUS1[7]CLK_CMT:MUX.MUXBUS1[13]
    57-CLK_CMT:MUX.MUXBUS0[11]-CLK_CMT:MUX.MUXBUS1[11]
    -CLK_CMT:MUX.MUXBUS0[9]-CLK_CMT:MUX.MUXBUS1[9]
    58CLK_CMT:MUX.MUXBUS0[3]-CLK_CMT:MUX.MUXBUS1[3]-
    CLK_CMT:MUX.MUXBUS0[11]-CLK_CMT:MUX.MUXBUS1[11]-
    59-CLK_CMT:MUX.MUXBUS0[12]-CLK_CMT:MUX.MUXBUS1[12]
    -CLK_CMT:MUX.MUXBUS0[6]-CLK_CMT:MUX.MUXBUS1[6]
    60CLK_CMT:MUX.MUXBUS0[4]-CLK_CMT:MUX.MUXBUS1[4]-
    CLK_CMT:MUX.MUXBUS0[8]-CLK_CMT:MUX.MUXBUS1[8]-
    61-CLK_CMT:MUX.MUXBUS0[13]-CLK_CMT:MUX.MUXBUS1[13]
    -CLK_CMT:MUX.MUXBUS0[10]-CLK_CMT:MUX.MUXBUS1[10]
    62CLK_CMT:MUX.MUXBUS0[5]-CLK_CMT:MUX.MUXBUS1[5]-
    CLK_CMT:MUX.MUXBUS0[12]-CLK_CMT:MUX.MUXBUS1[12]-
    @@ -3523,78 +3523,78 @@

    CLK_CMT_T

    CLK_CMT_T bittile 5
    RowColumn
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_CMT:MUX.MUXBUS0[4, 1, 61][4, 1, 59][4, 1, 57][4, 1, 56][4, 1, 55][4, 1, 54][4, 1, 53][4, 1, 50][4, 0, 62][4, 0, 60][4, 0, 58][4, 0, 56][4, 0, 55][4, 0, 53]
    CLK_CMT:MUX.MUXBUS1[4, 3, 61][4, 3, 59][4, 3, 57][4, 3, 56][4, 3, 55][4, 3, 54][4, 3, 53][4, 3, 50][4, 2, 62][4, 2, 60][4, 2, 58][4, 2, 56][4, 2, 55][4, 2, 53]
    CLK_CMT:MUX.MUXBUS10[3, 1, 45][3, 1, 43][3, 1, 41][3, 1, 40][3, 1, 39][3, 1, 38][3, 1, 37][3, 1, 34][3, 0, 46][3, 0, 44][3, 0, 42][3, 0, 40][3, 0, 39][3, 0, 37]
    CLK_CMT:MUX.MUXBUS11[3, 3, 45][3, 3, 43][3, 3, 41][3, 3, 40][3, 3, 39][3, 3, 38][3, 3, 37][3, 3, 34][3, 2, 46][3, 2, 44][3, 2, 42][3, 2, 40][3, 2, 39][3, 2, 37]
    CLK_CMT:MUX.MUXBUS12[3, 1, 29][3, 1, 27][3, 1, 25][3, 1, 24][3, 1, 23][3, 1, 22][3, 1, 21][3, 1, 18][3, 0, 30][3, 0, 28][3, 0, 26][3, 0, 24][3, 0, 23][3, 0, 21]
    CLK_CMT:MUX.MUXBUS13[3, 3, 29][3, 3, 27][3, 3, 25][3, 3, 24][3, 3, 23][3, 3, 22][3, 3, 21][3, 3, 18][3, 2, 30][3, 2, 28][3, 2, 26][3, 2, 24][3, 2, 23][3, 2, 21]
    CLK_CMT:MUX.MUXBUS14[3, 1, 13][3, 1, 11][3, 1, 9][3, 1, 8][3, 1, 7][3, 1, 6][3, 1, 5][3, 1, 2][3, 0, 14][3, 0, 12][3, 0, 10][3, 0, 8][3, 0, 7][3, 0, 5]
    CLK_CMT:MUX.MUXBUS15[3, 3, 13][3, 3, 11][3, 3, 9][3, 3, 8][3, 3, 7][3, 3, 6][3, 3, 5][3, 3, 2][3, 2, 14][3, 2, 12][3, 2, 10][3, 2, 8][3, 2, 7][3, 2, 5]
    CLK_CMT:MUX.MUXBUS16[2, 1, 61][2, 1, 59][2, 1, 57][2, 1, 56][2, 1, 55][2, 1, 54][2, 1, 53][2, 1, 50][2, 0, 62][2, 0, 60][2, 0, 58][2, 0, 56][2, 0, 55][2, 0, 53]
    CLK_CMT:MUX.MUXBUS17[2, 3, 61][2, 3, 59][2, 3, 57][2, 3, 56][2, 3, 55][2, 3, 54][2, 3, 53][2, 3, 50][2, 2, 62][2, 2, 60][2, 2, 58][2, 2, 56][2, 2, 55][2, 2, 53]
    CLK_CMT:MUX.MUXBUS18[2, 1, 45][2, 1, 43][2, 1, 41][2, 1, 40][2, 1, 39][2, 1, 38][2, 1, 37][2, 1, 34][2, 0, 46][2, 0, 44][2, 0, 42][2, 0, 40][2, 0, 39][2, 0, 37]
    CLK_CMT:MUX.MUXBUS19[2, 3, 45][2, 3, 43][2, 3, 41][2, 3, 40][2, 3, 39][2, 3, 38][2, 3, 37][2, 3, 34][2, 2, 46][2, 2, 44][2, 2, 42][2, 2, 40][2, 2, 39][2, 2, 37]
    CLK_CMT:MUX.MUXBUS2[4, 1, 45][4, 1, 43][4, 1, 41][4, 1, 40][4, 1, 39][4, 1, 38][4, 1, 37][4, 1, 34][4, 0, 46][4, 0, 44][4, 0, 42][4, 0, 40][4, 0, 39][4, 0, 37]
    CLK_CMT:MUX.MUXBUS20[2, 1, 29][2, 1, 27][2, 1, 25][2, 1, 24][2, 1, 23][2, 1, 22][2, 1, 21][2, 1, 18][2, 0, 30][2, 0, 28][2, 0, 26][2, 0, 24][2, 0, 23][2, 0, 21]
    CLK_CMT:MUX.MUXBUS21[2, 3, 29][2, 3, 27][2, 3, 25][2, 3, 24][2, 3, 23][2, 3, 22][2, 3, 21][2, 3, 18][2, 2, 30][2, 2, 28][2, 2, 26][2, 2, 24][2, 2, 23][2, 2, 21]
    CLK_CMT:MUX.MUXBUS22[2, 1, 13][2, 1, 11][2, 1, 9][2, 1, 8][2, 1, 7][2, 1, 6][2, 1, 5][2, 1, 2][2, 0, 14][2, 0, 12][2, 0, 10][2, 0, 8][2, 0, 7][2, 0, 5]
    CLK_CMT:MUX.MUXBUS23[2, 3, 13][2, 3, 11][2, 3, 9][2, 3, 8][2, 3, 7][2, 3, 6][2, 3, 5][2, 3, 2][2, 2, 14][2, 2, 12][2, 2, 10][2, 2, 8][2, 2, 7][2, 2, 5]
    CLK_CMT:MUX.MUXBUS24[1, 1, 61][1, 1, 59][1, 1, 57][1, 1, 56][1, 1, 55][1, 1, 54][1, 1, 53][1, 1, 50][1, 0, 62][1, 0, 60][1, 0, 58][1, 0, 56][1, 0, 55][1, 0, 53]
    CLK_CMT:MUX.MUXBUS25[1, 3, 61][1, 3, 59][1, 3, 57][1, 3, 56][1, 3, 55][1, 3, 54][1, 3, 53][1, 3, 50][1, 2, 62][1, 2, 60][1, 2, 58][1, 2, 56][1, 2, 55][1, 2, 53]
    CLK_CMT:MUX.MUXBUS26[1, 1, 45][1, 1, 43][1, 1, 41][1, 1, 40][1, 1, 39][1, 1, 38][1, 1, 37][1, 1, 34][1, 0, 46][1, 0, 44][1, 0, 42][1, 0, 40][1, 0, 39][1, 0, 37]
    CLK_CMT:MUX.MUXBUS27[1, 3, 45][1, 3, 43][1, 3, 41][1, 3, 40][1, 3, 39][1, 3, 38][1, 3, 37][1, 3, 34][1, 2, 46][1, 2, 44][1, 2, 42][1, 2, 40][1, 2, 39][1, 2, 37]
    CLK_CMT:MUX.MUXBUS28[1, 1, 29][1, 1, 27][1, 1, 25][1, 1, 24][1, 1, 23][1, 1, 22][1, 1, 21][1, 1, 18][1, 0, 30][1, 0, 28][1, 0, 26][1, 0, 24][1, 0, 23][1, 0, 21]
    CLK_CMT:MUX.MUXBUS29[1, 3, 29][1, 3, 27][1, 3, 25][1, 3, 24][1, 3, 23][1, 3, 22][1, 3, 21][1, 3, 18][1, 2, 30][1, 2, 28][1, 2, 26][1, 2, 24][1, 2, 23][1, 2, 21]
    CLK_CMT:MUX.MUXBUS3[4, 3, 45][4, 3, 43][4, 3, 41][4, 3, 40][4, 3, 39][4, 3, 38][4, 3, 37][4, 3, 34][4, 2, 46][4, 2, 44][4, 2, 42][4, 2, 40][4, 2, 39][4, 2, 37]
    CLK_CMT:MUX.MUXBUS30[1, 1, 13][1, 1, 11][1, 1, 9][1, 1, 8][1, 1, 7][1, 1, 6][1, 1, 5][1, 1, 2][1, 0, 14][1, 0, 12][1, 0, 10][1, 0, 8][1, 0, 7][1, 0, 5]
    CLK_CMT:MUX.MUXBUS31[1, 3, 13][1, 3, 11][1, 3, 9][1, 3, 8][1, 3, 7][1, 3, 6][1, 3, 5][1, 3, 2][1, 2, 14][1, 2, 12][1, 2, 10][1, 2, 8][1, 2, 7][1, 2, 5]
    CLK_CMT:MUX.MUXBUS4[4, 1, 29][4, 1, 27][4, 1, 25][4, 1, 24][4, 1, 23][4, 1, 22][4, 1, 21][4, 1, 18][4, 0, 30][4, 0, 28][4, 0, 26][4, 0, 24][4, 0, 23][4, 0, 21]
    CLK_CMT:MUX.MUXBUS5[4, 3, 29][4, 3, 27][4, 3, 25][4, 3, 24][4, 3, 23][4, 3, 22][4, 3, 21][4, 3, 18][4, 2, 30][4, 2, 28][4, 2, 26][4, 2, 24][4, 2, 23][4, 2, 21]
    CLK_CMT:MUX.MUXBUS6[4, 1, 13][4, 1, 11][4, 1, 9][4, 1, 8][4, 1, 7][4, 1, 6][4, 1, 5][4, 1, 2][4, 0, 14][4, 0, 12][4, 0, 10][4, 0, 8][4, 0, 7][4, 0, 5]
    CLK_CMT:MUX.MUXBUS7[4, 3, 13][4, 3, 11][4, 3, 9][4, 3, 8][4, 3, 7][4, 3, 6][4, 3, 5][4, 3, 2][4, 2, 14][4, 2, 12][4, 2, 10][4, 2, 8][4, 2, 7][4, 2, 5]
    CLK_CMT:MUX.MUXBUS8[3, 1, 61][3, 1, 59][3, 1, 57][3, 1, 56][3, 1, 55][3, 1, 54][3, 1, 53][3, 1, 50][3, 0, 62][3, 0, 60][3, 0, 58][3, 0, 56][3, 0, 55][3, 0, 53]
    CLK_CMT:MUX.MUXBUS9[3, 3, 61][3, 3, 59][3, 3, 57][3, 3, 56][3, 3, 55][3, 3, 54][3, 3, 53][3, 3, 50][3, 2, 62][3, 2, 60][3, 2, 58][3, 2, 56][3, 2, 55][3, 2, 53]
    CLK_CMT:MUX.MUXBUS0[4, 1, 56][4, 0, 62][4, 0, 58][4, 1, 61][4, 1, 57][4, 0, 60][4, 0, 56][4, 1, 59][4, 1, 54][4, 1, 55][4, 0, 55][4, 0, 53][4, 1, 53][4, 1, 50]
    CLK_CMT:MUX.MUXBUS1[4, 3, 56][4, 2, 62][4, 2, 58][4, 3, 61][4, 3, 57][4, 2, 60][4, 2, 56][4, 3, 59][4, 3, 54][4, 3, 55][4, 2, 55][4, 2, 53][4, 3, 53][4, 3, 50]
    CLK_CMT:MUX.MUXBUS10[3, 1, 40][3, 0, 46][3, 0, 42][3, 1, 45][3, 1, 41][3, 0, 44][3, 0, 40][3, 1, 43][3, 1, 38][3, 1, 39][3, 0, 39][3, 0, 37][3, 1, 37][3, 1, 34]
    CLK_CMT:MUX.MUXBUS11[3, 3, 40][3, 2, 46][3, 2, 42][3, 3, 45][3, 3, 41][3, 2, 44][3, 2, 40][3, 3, 43][3, 3, 38][3, 3, 39][3, 2, 39][3, 2, 37][3, 3, 37][3, 3, 34]
    CLK_CMT:MUX.MUXBUS12[3, 1, 24][3, 0, 30][3, 0, 26][3, 1, 29][3, 1, 25][3, 0, 28][3, 0, 24][3, 1, 27][3, 1, 22][3, 1, 23][3, 0, 23][3, 0, 21][3, 1, 21][3, 1, 18]
    CLK_CMT:MUX.MUXBUS13[3, 3, 24][3, 2, 30][3, 2, 26][3, 3, 29][3, 3, 25][3, 2, 28][3, 2, 24][3, 3, 27][3, 3, 22][3, 3, 23][3, 2, 23][3, 2, 21][3, 3, 21][3, 3, 18]
    CLK_CMT:MUX.MUXBUS14[3, 1, 8][3, 0, 14][3, 0, 10][3, 1, 13][3, 1, 9][3, 0, 12][3, 0, 8][3, 1, 11][3, 1, 6][3, 1, 7][3, 0, 7][3, 0, 5][3, 1, 5][3, 1, 2]
    CLK_CMT:MUX.MUXBUS15[3, 3, 8][3, 2, 14][3, 2, 10][3, 3, 13][3, 3, 9][3, 2, 12][3, 2, 8][3, 3, 11][3, 3, 6][3, 3, 7][3, 2, 7][3, 2, 5][3, 3, 5][3, 3, 2]
    CLK_CMT:MUX.MUXBUS16[2, 1, 56][2, 0, 62][2, 0, 58][2, 1, 61][2, 1, 57][2, 0, 60][2, 0, 56][2, 1, 59][2, 1, 54][2, 1, 55][2, 0, 55][2, 0, 53][2, 1, 53][2, 1, 50]
    CLK_CMT:MUX.MUXBUS17[2, 3, 56][2, 2, 62][2, 2, 58][2, 3, 61][2, 3, 57][2, 2, 60][2, 2, 56][2, 3, 59][2, 3, 54][2, 3, 55][2, 2, 55][2, 2, 53][2, 3, 53][2, 3, 50]
    CLK_CMT:MUX.MUXBUS18[2, 1, 40][2, 0, 46][2, 0, 42][2, 1, 45][2, 1, 41][2, 0, 44][2, 0, 40][2, 1, 43][2, 1, 38][2, 1, 39][2, 0, 39][2, 0, 37][2, 1, 37][2, 1, 34]
    CLK_CMT:MUX.MUXBUS19[2, 3, 40][2, 2, 46][2, 2, 42][2, 3, 45][2, 3, 41][2, 2, 44][2, 2, 40][2, 3, 43][2, 3, 38][2, 3, 39][2, 2, 39][2, 2, 37][2, 3, 37][2, 3, 34]
    CLK_CMT:MUX.MUXBUS2[4, 1, 40][4, 0, 46][4, 0, 42][4, 1, 45][4, 1, 41][4, 0, 44][4, 0, 40][4, 1, 43][4, 1, 38][4, 1, 39][4, 0, 39][4, 0, 37][4, 1, 37][4, 1, 34]
    CLK_CMT:MUX.MUXBUS20[2, 1, 24][2, 0, 30][2, 0, 26][2, 1, 29][2, 1, 25][2, 0, 28][2, 0, 24][2, 1, 27][2, 1, 22][2, 1, 23][2, 0, 23][2, 0, 21][2, 1, 21][2, 1, 18]
    CLK_CMT:MUX.MUXBUS21[2, 3, 24][2, 2, 30][2, 2, 26][2, 3, 29][2, 3, 25][2, 2, 28][2, 2, 24][2, 3, 27][2, 3, 22][2, 3, 23][2, 2, 23][2, 2, 21][2, 3, 21][2, 3, 18]
    CLK_CMT:MUX.MUXBUS22[2, 1, 8][2, 0, 14][2, 0, 10][2, 1, 13][2, 1, 9][2, 0, 12][2, 0, 8][2, 1, 11][2, 1, 6][2, 1, 7][2, 0, 7][2, 0, 5][2, 1, 5][2, 1, 2]
    CLK_CMT:MUX.MUXBUS23[2, 3, 8][2, 2, 14][2, 2, 10][2, 3, 13][2, 3, 9][2, 2, 12][2, 2, 8][2, 3, 11][2, 3, 6][2, 3, 7][2, 2, 7][2, 2, 5][2, 3, 5][2, 3, 2]
    CLK_CMT:MUX.MUXBUS24[1, 1, 56][1, 0, 62][1, 0, 58][1, 1, 61][1, 1, 57][1, 0, 60][1, 0, 56][1, 1, 59][1, 1, 54][1, 1, 55][1, 0, 55][1, 0, 53][1, 1, 53][1, 1, 50]
    CLK_CMT:MUX.MUXBUS25[1, 3, 56][1, 2, 62][1, 2, 58][1, 3, 61][1, 3, 57][1, 2, 60][1, 2, 56][1, 3, 59][1, 3, 54][1, 3, 55][1, 2, 55][1, 2, 53][1, 3, 53][1, 3, 50]
    CLK_CMT:MUX.MUXBUS26[1, 1, 40][1, 0, 46][1, 0, 42][1, 1, 45][1, 1, 41][1, 0, 44][1, 0, 40][1, 1, 43][1, 1, 38][1, 1, 39][1, 0, 39][1, 0, 37][1, 1, 37][1, 1, 34]
    CLK_CMT:MUX.MUXBUS27[1, 3, 40][1, 2, 46][1, 2, 42][1, 3, 45][1, 3, 41][1, 2, 44][1, 2, 40][1, 3, 43][1, 3, 38][1, 3, 39][1, 2, 39][1, 2, 37][1, 3, 37][1, 3, 34]
    CLK_CMT:MUX.MUXBUS28[1, 1, 24][1, 0, 30][1, 0, 26][1, 1, 29][1, 1, 25][1, 0, 28][1, 0, 24][1, 1, 27][1, 1, 22][1, 1, 23][1, 0, 23][1, 0, 21][1, 1, 21][1, 1, 18]
    CLK_CMT:MUX.MUXBUS29[1, 3, 24][1, 2, 30][1, 2, 26][1, 3, 29][1, 3, 25][1, 2, 28][1, 2, 24][1, 3, 27][1, 3, 22][1, 3, 23][1, 2, 23][1, 2, 21][1, 3, 21][1, 3, 18]
    CLK_CMT:MUX.MUXBUS3[4, 3, 40][4, 2, 46][4, 2, 42][4, 3, 45][4, 3, 41][4, 2, 44][4, 2, 40][4, 3, 43][4, 3, 38][4, 3, 39][4, 2, 39][4, 2, 37][4, 3, 37][4, 3, 34]
    CLK_CMT:MUX.MUXBUS30[1, 1, 8][1, 0, 14][1, 0, 10][1, 1, 13][1, 1, 9][1, 0, 12][1, 0, 8][1, 1, 11][1, 1, 6][1, 1, 7][1, 0, 7][1, 0, 5][1, 1, 5][1, 1, 2]
    CLK_CMT:MUX.MUXBUS31[1, 3, 8][1, 2, 14][1, 2, 10][1, 3, 13][1, 3, 9][1, 2, 12][1, 2, 8][1, 3, 11][1, 3, 6][1, 3, 7][1, 2, 7][1, 2, 5][1, 3, 5][1, 3, 2]
    CLK_CMT:MUX.MUXBUS4[4, 1, 24][4, 0, 30][4, 0, 26][4, 1, 29][4, 1, 25][4, 0, 28][4, 0, 24][4, 1, 27][4, 1, 22][4, 1, 23][4, 0, 23][4, 0, 21][4, 1, 21][4, 1, 18]
    CLK_CMT:MUX.MUXBUS5[4, 3, 24][4, 2, 30][4, 2, 26][4, 3, 29][4, 3, 25][4, 2, 28][4, 2, 24][4, 3, 27][4, 3, 22][4, 3, 23][4, 2, 23][4, 2, 21][4, 3, 21][4, 3, 18]
    CLK_CMT:MUX.MUXBUS6[4, 1, 8][4, 0, 14][4, 0, 10][4, 1, 13][4, 1, 9][4, 0, 12][4, 0, 8][4, 1, 11][4, 1, 6][4, 1, 7][4, 0, 7][4, 0, 5][4, 1, 5][4, 1, 2]
    CLK_CMT:MUX.MUXBUS7[4, 3, 8][4, 2, 14][4, 2, 10][4, 3, 13][4, 3, 9][4, 2, 12][4, 2, 8][4, 3, 11][4, 3, 6][4, 3, 7][4, 2, 7][4, 2, 5][4, 3, 5][4, 3, 2]
    CLK_CMT:MUX.MUXBUS8[3, 1, 56][3, 0, 62][3, 0, 58][3, 1, 61][3, 1, 57][3, 0, 60][3, 0, 56][3, 1, 59][3, 1, 54][3, 1, 55][3, 0, 55][3, 0, 53][3, 1, 53][3, 1, 50]
    CLK_CMT:MUX.MUXBUS9[3, 3, 56][3, 2, 62][3, 2, 58][3, 3, 61][3, 3, 57][3, 2, 60][3, 2, 56][3, 3, 59][3, 3, 54][3, 3, 55][3, 2, 55][3, 2, 53][3, 3, 53][3, 3, 50]
    NONE00000000000000
    MGT_R000000000000101
    CMT_CLK100000000000110
    MGT_R200000000001001
    CMT_CLK300000000001010
    MGT_R400000000010001
    CMT_CLK500000000010010
    CMT_CLK700000000100010
    PASS00000001000000
    CMT_CLK2500000010000100
    CMT_CLK2700000010001000
    MGT_L100000010010000
    MGT_L300000010100000
    CMT_CLK1700000100000100
    CMT_CLK1900000100001000
    CMT_CLK2100000100010000
    CMT_CLK2300000100100000
    CMT_CLK900001000000100
    CMT_CLK1100001000001000
    CMT_CLK1300001000010000
    CMT_CLK1500001000100000
    MGT_L400010000000001
    CMT_CLK000010000000010
    CMT_CLK2400010010000000
    CMT_CLK1600010100000000
    CMT_CLK800011000000000
    MGT_R100100000000001
    CMT_CLK200100000000010
    CMT_CLK2600100010000000
    CMT_CLK1800100100000000
    CMT_CLK1000101000000000
    MGT_R301000000000001
    CMT_CLK401000000000010
    MGT_L001000010000000
    CMT_CLK2001000100000000
    CMT_CLK1201001000000000
    CMT_CLK610000000000010
    MGT_L210000010000000
    CMT_CLK2210000100000000
    CMT_CLK1410001000000000
    PASS00000000000001
    MGT_L000000001000010
    MGT_R300000001000100
    CMT_CLK400000001001000
    CMT_CLK1200000001010000
    CMT_CLK2000000001100000
    CMT_CLK2500000010000010
    MGT_R000000010000100
    CMT_CLK100000010001000
    CMT_CLK900000010010000
    CMT_CLK1700000010100000
    MGT_L100000100000010
    MGT_R400000100000100
    CMT_CLK500000100001000
    CMT_CLK1300000100010000
    CMT_CLK2100000100100000
    CMT_CLK2600001000000010
    MGT_R100001000000100
    CMT_CLK200001000001000
    CMT_CLK1000001000010000
    CMT_CLK1800001000100000
    MGT_L200010000000010
    CMT_CLK600010000001000
    CMT_CLK1400010000010000
    CMT_CLK2200010000100000
    CMT_CLK2700100000000010
    MGT_R200100000000100
    CMT_CLK300100000001000
    CMT_CLK1100100000010000
    CMT_CLK1900100000100000
    MGT_L301000000000010
    CMT_CLK701000000001000
    CMT_CLK1501000000010000
    CMT_CLK2301000000100000
    CMT_CLK2410000000000010
    MGT_L410000000000100
    CMT_CLK010000000001000
    CMT_CLK810000000010000
    CMT_CLK1610000000100000
    @@ -3659,17 +3659,17 @@

    CLK_MGT_B2 ---- 3 --CLK_MGT:MUX.MUXBUS0[4]-CLK_MGT:MUX.MUXBUS1[4] +-CLK_MGT:MUX.MUXBUS0[7]-CLK_MGT:MUX.MUXBUS1[7] 4 -CLK_MGT:MUX.MUXBUS0[0]-CLK_MGT:MUX.MUXBUS1[0]- +CLK_MGT:MUX.MUXBUS0[6]-CLK_MGT:MUX.MUXBUS1[6]- 5 -CLK_MGT:MUX.MUXBUS0[5]-CLK_MGT:MUX.MUXBUS1[5] 6 -CLK_MGT:MUX.MUXBUS0[1]-CLK_MGT:MUX.MUXBUS1[1]- +CLK_MGT:MUX.MUXBUS0[4]-CLK_MGT:MUX.MUXBUS1[4]- 7 -CLK_MGT:MUX.MUXBUS0[2]CLK_MGT:MUX.MUXBUS0[6]CLK_MGT:MUX.MUXBUS1[2]CLK_MGT:MUX.MUXBUS1[6] +CLK_MGT:MUX.MUXBUS0[1]CLK_MGT:MUX.MUXBUS0[2]CLK_MGT:MUX.MUXBUS1[1]CLK_MGT:MUX.MUXBUS1[2] 8 --CLK_MGT:MUX.MUXBUS0[7]-CLK_MGT:MUX.MUXBUS1[7] +-CLK_MGT:MUX.MUXBUS0[3]-CLK_MGT:MUX.MUXBUS1[3] 9 ---- 10 @@ -3677,7 +3677,7 @@

    CLK_MGT_B11 ---- 12 -CLK_MGT:MUX.MUXBUS0[3]-CLK_MGT:MUX.MUXBUS1[3]- +CLK_MGT:MUX.MUXBUS0[0]-CLK_MGT:MUX.MUXBUS1[0]- 13 ---- 14 @@ -3691,17 +3691,17 @@

    CLK_MGT_B18 ---- 19 --CLK_MGT:MUX.MUXBUS2[4]-CLK_MGT:MUX.MUXBUS3[4] +-CLK_MGT:MUX.MUXBUS2[7]-CLK_MGT:MUX.MUXBUS3[7] 20 -CLK_MGT:MUX.MUXBUS2[0]-CLK_MGT:MUX.MUXBUS3[0]- +CLK_MGT:MUX.MUXBUS2[6]-CLK_MGT:MUX.MUXBUS3[6]- 21 -CLK_MGT:MUX.MUXBUS2[5]-CLK_MGT:MUX.MUXBUS3[5] 22 -CLK_MGT:MUX.MUXBUS2[1]-CLK_MGT:MUX.MUXBUS3[1]- +CLK_MGT:MUX.MUXBUS2[4]-CLK_MGT:MUX.MUXBUS3[4]- 23 -CLK_MGT:MUX.MUXBUS2[2]CLK_MGT:MUX.MUXBUS2[6]CLK_MGT:MUX.MUXBUS3[2]CLK_MGT:MUX.MUXBUS3[6] +CLK_MGT:MUX.MUXBUS2[1]CLK_MGT:MUX.MUXBUS2[2]CLK_MGT:MUX.MUXBUS3[1]CLK_MGT:MUX.MUXBUS3[2] 24 --CLK_MGT:MUX.MUXBUS2[7]-CLK_MGT:MUX.MUXBUS3[7] +-CLK_MGT:MUX.MUXBUS2[3]-CLK_MGT:MUX.MUXBUS3[3] 25 ---- 26 @@ -3709,7 +3709,7 @@

    CLK_MGT_B27 ---- 28 -CLK_MGT:MUX.MUXBUS2[3]-CLK_MGT:MUX.MUXBUS3[3]- +CLK_MGT:MUX.MUXBUS2[0]-CLK_MGT:MUX.MUXBUS3[0]- 29 ---- 30 @@ -3723,17 +3723,17 @@

    CLK_MGT_B34 ---- 35 --CLK_MGT:MUX.MUXBUS4[4]-CLK_MGT:MUX.MUXBUS5[4] +-CLK_MGT:MUX.MUXBUS4[7]-CLK_MGT:MUX.MUXBUS5[7] 36 -CLK_MGT:MUX.MUXBUS4[0]-CLK_MGT:MUX.MUXBUS5[0]- +CLK_MGT:MUX.MUXBUS4[6]-CLK_MGT:MUX.MUXBUS5[6]- 37 -CLK_MGT:MUX.MUXBUS4[5]-CLK_MGT:MUX.MUXBUS5[5] 38 -CLK_MGT:MUX.MUXBUS4[1]-CLK_MGT:MUX.MUXBUS5[1]- +CLK_MGT:MUX.MUXBUS4[4]-CLK_MGT:MUX.MUXBUS5[4]- 39 -CLK_MGT:MUX.MUXBUS4[2]CLK_MGT:MUX.MUXBUS4[6]CLK_MGT:MUX.MUXBUS5[2]CLK_MGT:MUX.MUXBUS5[6] +CLK_MGT:MUX.MUXBUS4[1]CLK_MGT:MUX.MUXBUS4[2]CLK_MGT:MUX.MUXBUS5[1]CLK_MGT:MUX.MUXBUS5[2] 40 --CLK_MGT:MUX.MUXBUS4[7]-CLK_MGT:MUX.MUXBUS5[7] +-CLK_MGT:MUX.MUXBUS4[3]-CLK_MGT:MUX.MUXBUS5[3] 41 ---- 42 @@ -3741,7 +3741,7 @@

    CLK_MGT_B43 ---- 44 -CLK_MGT:MUX.MUXBUS4[3]-CLK_MGT:MUX.MUXBUS5[3]- +CLK_MGT:MUX.MUXBUS4[0]-CLK_MGT:MUX.MUXBUS5[0]- 45 ---- 46 @@ -3755,17 +3755,17 @@

    CLK_MGT_B50 ---- 51 --CLK_MGT:MUX.MUXBUS6[4]-CLK_MGT:MUX.MUXBUS7[4] +-CLK_MGT:MUX.MUXBUS6[7]-CLK_MGT:MUX.MUXBUS7[7] 52 -CLK_MGT:MUX.MUXBUS6[0]-CLK_MGT:MUX.MUXBUS7[0]- +CLK_MGT:MUX.MUXBUS6[6]-CLK_MGT:MUX.MUXBUS7[6]- 53 -CLK_MGT:MUX.MUXBUS6[5]-CLK_MGT:MUX.MUXBUS7[5] 54 -CLK_MGT:MUX.MUXBUS6[1]-CLK_MGT:MUX.MUXBUS7[1]- +CLK_MGT:MUX.MUXBUS6[4]-CLK_MGT:MUX.MUXBUS7[4]- 55 -CLK_MGT:MUX.MUXBUS6[2]CLK_MGT:MUX.MUXBUS6[6]CLK_MGT:MUX.MUXBUS7[2]CLK_MGT:MUX.MUXBUS7[6] +CLK_MGT:MUX.MUXBUS6[1]CLK_MGT:MUX.MUXBUS6[2]CLK_MGT:MUX.MUXBUS7[1]CLK_MGT:MUX.MUXBUS7[2] 56 --CLK_MGT:MUX.MUXBUS6[7]-CLK_MGT:MUX.MUXBUS7[7] +-CLK_MGT:MUX.MUXBUS6[3]-CLK_MGT:MUX.MUXBUS7[3] 57 ---- 58 @@ -3773,7 +3773,7 @@

    CLK_MGT_B59 ---- 60 -CLK_MGT:MUX.MUXBUS6[3]-CLK_MGT:MUX.MUXBUS7[3]- +CLK_MGT:MUX.MUXBUS6[0]-CLK_MGT:MUX.MUXBUS7[0]- @@ -3784,17 +3784,17 @@

    CLK_MGT_B

    - + - + - + - + - + @@ -3802,7 +3802,7 @@

    CLK_MGT_B

     - + @@ -3816,17 +3816,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -3834,7 +3834,7 @@

    CLK_MGT_B

     - + @@ -3848,17 +3848,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -3866,7 +3866,7 @@

    CLK_MGT_B

     - + @@ -3880,17 +3880,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -3898,7 +3898,7 @@

    CLK_MGT_B

     - +
    CLK_MGT_B bittile 6
    RowColumn
    0123
    2 ----
    3-CLK_MGT:MUX.MUXBUS8[4]-CLK_MGT:MUX.MUXBUS9[4]
    -CLK_MGT:MUX.MUXBUS8[7]-CLK_MGT:MUX.MUXBUS9[7]
    4CLK_MGT:MUX.MUXBUS8[0]-CLK_MGT:MUX.MUXBUS9[0]-
    CLK_MGT:MUX.MUXBUS8[6]-CLK_MGT:MUX.MUXBUS9[6]-
    5 -CLK_MGT:MUX.MUXBUS8[5]-CLK_MGT:MUX.MUXBUS9[5]
    6CLK_MGT:MUX.MUXBUS8[1]-CLK_MGT:MUX.MUXBUS9[1]-
    CLK_MGT:MUX.MUXBUS8[4]-CLK_MGT:MUX.MUXBUS9[4]-
    7CLK_MGT:MUX.MUXBUS8[2]CLK_MGT:MUX.MUXBUS8[6]CLK_MGT:MUX.MUXBUS9[2]CLK_MGT:MUX.MUXBUS9[6]
    CLK_MGT:MUX.MUXBUS8[1]CLK_MGT:MUX.MUXBUS8[2]CLK_MGT:MUX.MUXBUS9[1]CLK_MGT:MUX.MUXBUS9[2]
    8-CLK_MGT:MUX.MUXBUS8[7]-CLK_MGT:MUX.MUXBUS9[7]
    -CLK_MGT:MUX.MUXBUS8[3]-CLK_MGT:MUX.MUXBUS9[3]
    9 ----
    1011 ----
    12CLK_MGT:MUX.MUXBUS8[3]-CLK_MGT:MUX.MUXBUS9[3]-
    CLK_MGT:MUX.MUXBUS8[0]-CLK_MGT:MUX.MUXBUS9[0]-
    13 ----
    1418 ----
    19-CLK_MGT:MUX.MUXBUS10[4]-CLK_MGT:MUX.MUXBUS11[4]
    -CLK_MGT:MUX.MUXBUS10[7]-CLK_MGT:MUX.MUXBUS11[7]
    20CLK_MGT:MUX.MUXBUS10[0]-CLK_MGT:MUX.MUXBUS11[0]-
    CLK_MGT:MUX.MUXBUS10[6]-CLK_MGT:MUX.MUXBUS11[6]-
    21 -CLK_MGT:MUX.MUXBUS10[5]-CLK_MGT:MUX.MUXBUS11[5]
    22CLK_MGT:MUX.MUXBUS10[1]-CLK_MGT:MUX.MUXBUS11[1]-
    CLK_MGT:MUX.MUXBUS10[4]-CLK_MGT:MUX.MUXBUS11[4]-
    23CLK_MGT:MUX.MUXBUS10[2]CLK_MGT:MUX.MUXBUS10[6]CLK_MGT:MUX.MUXBUS11[2]CLK_MGT:MUX.MUXBUS11[6]
    CLK_MGT:MUX.MUXBUS10[1]CLK_MGT:MUX.MUXBUS10[2]CLK_MGT:MUX.MUXBUS11[1]CLK_MGT:MUX.MUXBUS11[2]
    24-CLK_MGT:MUX.MUXBUS10[7]-CLK_MGT:MUX.MUXBUS11[7]
    -CLK_MGT:MUX.MUXBUS10[3]-CLK_MGT:MUX.MUXBUS11[3]
    25 ----
    2627 ----
    28CLK_MGT:MUX.MUXBUS10[3]-CLK_MGT:MUX.MUXBUS11[3]-
    CLK_MGT:MUX.MUXBUS10[0]-CLK_MGT:MUX.MUXBUS11[0]-
    29 ----
    3034 ----
    35-CLK_MGT:MUX.MUXBUS12[4]-CLK_MGT:MUX.MUXBUS13[4]
    -CLK_MGT:MUX.MUXBUS12[7]-CLK_MGT:MUX.MUXBUS13[7]
    36CLK_MGT:MUX.MUXBUS12[0]-CLK_MGT:MUX.MUXBUS13[0]-
    CLK_MGT:MUX.MUXBUS12[6]-CLK_MGT:MUX.MUXBUS13[6]-
    37 -CLK_MGT:MUX.MUXBUS12[5]-CLK_MGT:MUX.MUXBUS13[5]
    38CLK_MGT:MUX.MUXBUS12[1]-CLK_MGT:MUX.MUXBUS13[1]-
    CLK_MGT:MUX.MUXBUS12[4]-CLK_MGT:MUX.MUXBUS13[4]-
    39CLK_MGT:MUX.MUXBUS12[2]CLK_MGT:MUX.MUXBUS12[6]CLK_MGT:MUX.MUXBUS13[2]CLK_MGT:MUX.MUXBUS13[6]
    CLK_MGT:MUX.MUXBUS12[1]CLK_MGT:MUX.MUXBUS12[2]CLK_MGT:MUX.MUXBUS13[1]CLK_MGT:MUX.MUXBUS13[2]
    40-CLK_MGT:MUX.MUXBUS12[7]-CLK_MGT:MUX.MUXBUS13[7]
    -CLK_MGT:MUX.MUXBUS12[3]-CLK_MGT:MUX.MUXBUS13[3]
    41 ----
    4243 ----
    44CLK_MGT:MUX.MUXBUS12[3]-CLK_MGT:MUX.MUXBUS13[3]-
    CLK_MGT:MUX.MUXBUS12[0]-CLK_MGT:MUX.MUXBUS13[0]-
    45 ----
    4650 ----
    51-CLK_MGT:MUX.MUXBUS14[4]-CLK_MGT:MUX.MUXBUS15[4]
    -CLK_MGT:MUX.MUXBUS14[7]-CLK_MGT:MUX.MUXBUS15[7]
    52CLK_MGT:MUX.MUXBUS14[0]-CLK_MGT:MUX.MUXBUS15[0]-
    CLK_MGT:MUX.MUXBUS14[6]-CLK_MGT:MUX.MUXBUS15[6]-
    53 -CLK_MGT:MUX.MUXBUS14[5]-CLK_MGT:MUX.MUXBUS15[5]
    54CLK_MGT:MUX.MUXBUS14[1]-CLK_MGT:MUX.MUXBUS15[1]-
    CLK_MGT:MUX.MUXBUS14[4]-CLK_MGT:MUX.MUXBUS15[4]-
    55CLK_MGT:MUX.MUXBUS14[2]CLK_MGT:MUX.MUXBUS14[6]CLK_MGT:MUX.MUXBUS15[2]CLK_MGT:MUX.MUXBUS15[6]
    CLK_MGT:MUX.MUXBUS14[1]CLK_MGT:MUX.MUXBUS14[2]CLK_MGT:MUX.MUXBUS15[1]CLK_MGT:MUX.MUXBUS15[2]
    56-CLK_MGT:MUX.MUXBUS14[7]-CLK_MGT:MUX.MUXBUS15[7]
    -CLK_MGT:MUX.MUXBUS14[3]-CLK_MGT:MUX.MUXBUS15[3]
    57 ----
    5859 ----
    60CLK_MGT:MUX.MUXBUS14[3]-CLK_MGT:MUX.MUXBUS15[3]-
    CLK_MGT:MUX.MUXBUS14[0]-CLK_MGT:MUX.MUXBUS15[0]-
    @@ -3909,17 +3909,17 @@

    CLK_MGT_B

    - + - + - + - + - + @@ -3927,7 +3927,7 @@

    CLK_MGT_B

     - + @@ -3941,17 +3941,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -3959,7 +3959,7 @@

    CLK_MGT_B

     - + @@ -3973,17 +3973,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -3991,7 +3991,7 @@

    CLK_MGT_B

     - + @@ -4005,17 +4005,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -4023,7 +4023,7 @@

    CLK_MGT_B

     - +
    CLK_MGT_B bittile 7
    RowColumn
    0123
    2 ----
    3-CLK_MGT:MUX.MUXBUS16[4]-CLK_MGT:MUX.MUXBUS17[4]
    -CLK_MGT:MUX.MUXBUS16[7]-CLK_MGT:MUX.MUXBUS17[7]
    4CLK_MGT:MUX.MUXBUS16[0]-CLK_MGT:MUX.MUXBUS17[0]-
    CLK_MGT:MUX.MUXBUS16[6]-CLK_MGT:MUX.MUXBUS17[6]-
    5 -CLK_MGT:MUX.MUXBUS16[5]-CLK_MGT:MUX.MUXBUS17[5]
    6CLK_MGT:MUX.MUXBUS16[1]-CLK_MGT:MUX.MUXBUS17[1]-
    CLK_MGT:MUX.MUXBUS16[4]-CLK_MGT:MUX.MUXBUS17[4]-
    7CLK_MGT:MUX.MUXBUS16[2]CLK_MGT:MUX.MUXBUS16[6]CLK_MGT:MUX.MUXBUS17[2]CLK_MGT:MUX.MUXBUS17[6]
    CLK_MGT:MUX.MUXBUS16[1]CLK_MGT:MUX.MUXBUS16[2]CLK_MGT:MUX.MUXBUS17[1]CLK_MGT:MUX.MUXBUS17[2]
    8-CLK_MGT:MUX.MUXBUS16[7]-CLK_MGT:MUX.MUXBUS17[7]
    -CLK_MGT:MUX.MUXBUS16[3]-CLK_MGT:MUX.MUXBUS17[3]
    9 ----
    1011 ----
    12CLK_MGT:MUX.MUXBUS16[3]-CLK_MGT:MUX.MUXBUS17[3]-
    CLK_MGT:MUX.MUXBUS16[0]-CLK_MGT:MUX.MUXBUS17[0]-
    13 ----
    1418 ----
    19-CLK_MGT:MUX.MUXBUS18[4]-CLK_MGT:MUX.MUXBUS19[4]
    -CLK_MGT:MUX.MUXBUS18[7]-CLK_MGT:MUX.MUXBUS19[7]
    20CLK_MGT:MUX.MUXBUS18[0]-CLK_MGT:MUX.MUXBUS19[0]-
    CLK_MGT:MUX.MUXBUS18[6]-CLK_MGT:MUX.MUXBUS19[6]-
    21 -CLK_MGT:MUX.MUXBUS18[5]-CLK_MGT:MUX.MUXBUS19[5]
    22CLK_MGT:MUX.MUXBUS18[1]-CLK_MGT:MUX.MUXBUS19[1]-
    CLK_MGT:MUX.MUXBUS18[4]-CLK_MGT:MUX.MUXBUS19[4]-
    23CLK_MGT:MUX.MUXBUS18[2]CLK_MGT:MUX.MUXBUS18[6]CLK_MGT:MUX.MUXBUS19[2]CLK_MGT:MUX.MUXBUS19[6]
    CLK_MGT:MUX.MUXBUS18[1]CLK_MGT:MUX.MUXBUS18[2]CLK_MGT:MUX.MUXBUS19[1]CLK_MGT:MUX.MUXBUS19[2]
    24-CLK_MGT:MUX.MUXBUS18[7]-CLK_MGT:MUX.MUXBUS19[7]
    -CLK_MGT:MUX.MUXBUS18[3]-CLK_MGT:MUX.MUXBUS19[3]
    25 ----
    2627 ----
    28CLK_MGT:MUX.MUXBUS18[3]-CLK_MGT:MUX.MUXBUS19[3]-
    CLK_MGT:MUX.MUXBUS18[0]-CLK_MGT:MUX.MUXBUS19[0]-
    29 ----
    3034 ----
    35-CLK_MGT:MUX.MUXBUS20[4]-CLK_MGT:MUX.MUXBUS21[4]
    -CLK_MGT:MUX.MUXBUS20[7]-CLK_MGT:MUX.MUXBUS21[7]
    36CLK_MGT:MUX.MUXBUS20[0]-CLK_MGT:MUX.MUXBUS21[0]-
    CLK_MGT:MUX.MUXBUS20[6]-CLK_MGT:MUX.MUXBUS21[6]-
    37 -CLK_MGT:MUX.MUXBUS20[5]-CLK_MGT:MUX.MUXBUS21[5]
    38CLK_MGT:MUX.MUXBUS20[1]-CLK_MGT:MUX.MUXBUS21[1]-
    CLK_MGT:MUX.MUXBUS20[4]-CLK_MGT:MUX.MUXBUS21[4]-
    39CLK_MGT:MUX.MUXBUS20[2]CLK_MGT:MUX.MUXBUS20[6]CLK_MGT:MUX.MUXBUS21[2]CLK_MGT:MUX.MUXBUS21[6]
    CLK_MGT:MUX.MUXBUS20[1]CLK_MGT:MUX.MUXBUS20[2]CLK_MGT:MUX.MUXBUS21[1]CLK_MGT:MUX.MUXBUS21[2]
    40-CLK_MGT:MUX.MUXBUS20[7]-CLK_MGT:MUX.MUXBUS21[7]
    -CLK_MGT:MUX.MUXBUS20[3]-CLK_MGT:MUX.MUXBUS21[3]
    41 ----
    4243 ----
    44CLK_MGT:MUX.MUXBUS20[3]-CLK_MGT:MUX.MUXBUS21[3]-
    CLK_MGT:MUX.MUXBUS20[0]-CLK_MGT:MUX.MUXBUS21[0]-
    45 ----
    4650 ----
    51-CLK_MGT:MUX.MUXBUS22[4]-CLK_MGT:MUX.MUXBUS23[4]
    -CLK_MGT:MUX.MUXBUS22[7]-CLK_MGT:MUX.MUXBUS23[7]
    52CLK_MGT:MUX.MUXBUS22[0]-CLK_MGT:MUX.MUXBUS23[0]-
    CLK_MGT:MUX.MUXBUS22[6]-CLK_MGT:MUX.MUXBUS23[6]-
    53 -CLK_MGT:MUX.MUXBUS22[5]-CLK_MGT:MUX.MUXBUS23[5]
    54CLK_MGT:MUX.MUXBUS22[1]-CLK_MGT:MUX.MUXBUS23[1]-
    CLK_MGT:MUX.MUXBUS22[4]-CLK_MGT:MUX.MUXBUS23[4]-
    55CLK_MGT:MUX.MUXBUS22[2]CLK_MGT:MUX.MUXBUS22[6]CLK_MGT:MUX.MUXBUS23[2]CLK_MGT:MUX.MUXBUS23[6]
    CLK_MGT:MUX.MUXBUS22[1]CLK_MGT:MUX.MUXBUS22[2]CLK_MGT:MUX.MUXBUS23[1]CLK_MGT:MUX.MUXBUS23[2]
    56-CLK_MGT:MUX.MUXBUS22[7]-CLK_MGT:MUX.MUXBUS23[7]
    -CLK_MGT:MUX.MUXBUS22[3]-CLK_MGT:MUX.MUXBUS23[3]
    57 ----
    5859 ----
    60CLK_MGT:MUX.MUXBUS22[3]-CLK_MGT:MUX.MUXBUS23[3]-
    CLK_MGT:MUX.MUXBUS22[0]-CLK_MGT:MUX.MUXBUS23[0]-
    @@ -4034,17 +4034,17 @@

    CLK_MGT_B

    - + - + - + - + - + @@ -4052,7 +4052,7 @@

    CLK_MGT_B

     - + @@ -4066,17 +4066,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -4084,7 +4084,7 @@

    CLK_MGT_B

     - + @@ -4098,17 +4098,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -4116,7 +4116,7 @@

    CLK_MGT_B

     - + @@ -4130,17 +4130,17 @@

    CLK_MGT_B

     - + - + - + - + - + @@ -4148,7 +4148,7 @@

    CLK_MGT_B

     - +
    CLK_MGT_B bittile 8
    RowColumn
    0123
    2 ----
    3-CLK_MGT:MUX.MUXBUS24[4]-CLK_MGT:MUX.MUXBUS25[4]
    -CLK_MGT:MUX.MUXBUS24[7]-CLK_MGT:MUX.MUXBUS25[7]
    4CLK_MGT:MUX.MUXBUS24[0]-CLK_MGT:MUX.MUXBUS25[0]-
    CLK_MGT:MUX.MUXBUS24[6]-CLK_MGT:MUX.MUXBUS25[6]-
    5 -CLK_MGT:MUX.MUXBUS24[5]-CLK_MGT:MUX.MUXBUS25[5]
    6CLK_MGT:MUX.MUXBUS24[1]-CLK_MGT:MUX.MUXBUS25[1]-
    CLK_MGT:MUX.MUXBUS24[4]-CLK_MGT:MUX.MUXBUS25[4]-
    7CLK_MGT:MUX.MUXBUS24[2]CLK_MGT:MUX.MUXBUS24[6]CLK_MGT:MUX.MUXBUS25[2]CLK_MGT:MUX.MUXBUS25[6]
    CLK_MGT:MUX.MUXBUS24[1]CLK_MGT:MUX.MUXBUS24[2]CLK_MGT:MUX.MUXBUS25[1]CLK_MGT:MUX.MUXBUS25[2]
    8-CLK_MGT:MUX.MUXBUS24[7]-CLK_MGT:MUX.MUXBUS25[7]
    -CLK_MGT:MUX.MUXBUS24[3]-CLK_MGT:MUX.MUXBUS25[3]
    9 ----
    1011 ----
    12CLK_MGT:MUX.MUXBUS24[3]-CLK_MGT:MUX.MUXBUS25[3]-
    CLK_MGT:MUX.MUXBUS24[0]-CLK_MGT:MUX.MUXBUS25[0]-
    13 ----
    1418 ----
    19-CLK_MGT:MUX.MUXBUS26[4]-CLK_MGT:MUX.MUXBUS27[4]
    -CLK_MGT:MUX.MUXBUS26[7]-CLK_MGT:MUX.MUXBUS27[7]
    20CLK_MGT:MUX.MUXBUS26[0]-CLK_MGT:MUX.MUXBUS27[0]-
    CLK_MGT:MUX.MUXBUS26[6]-CLK_MGT:MUX.MUXBUS27[6]-
    21 -CLK_MGT:MUX.MUXBUS26[5]-CLK_MGT:MUX.MUXBUS27[5]
    22CLK_MGT:MUX.MUXBUS26[1]-CLK_MGT:MUX.MUXBUS27[1]-
    CLK_MGT:MUX.MUXBUS26[4]-CLK_MGT:MUX.MUXBUS27[4]-
    23CLK_MGT:MUX.MUXBUS26[2]CLK_MGT:MUX.MUXBUS26[6]CLK_MGT:MUX.MUXBUS27[2]CLK_MGT:MUX.MUXBUS27[6]
    CLK_MGT:MUX.MUXBUS26[1]CLK_MGT:MUX.MUXBUS26[2]CLK_MGT:MUX.MUXBUS27[1]CLK_MGT:MUX.MUXBUS27[2]
    24-CLK_MGT:MUX.MUXBUS26[7]-CLK_MGT:MUX.MUXBUS27[7]
    -CLK_MGT:MUX.MUXBUS26[3]-CLK_MGT:MUX.MUXBUS27[3]
    25 ----
    2627 ----
    28CLK_MGT:MUX.MUXBUS26[3]-CLK_MGT:MUX.MUXBUS27[3]-
    CLK_MGT:MUX.MUXBUS26[0]-CLK_MGT:MUX.MUXBUS27[0]-
    29 ----
    3034 ----
    35-CLK_MGT:MUX.MUXBUS28[4]-CLK_MGT:MUX.MUXBUS29[4]
    -CLK_MGT:MUX.MUXBUS28[7]-CLK_MGT:MUX.MUXBUS29[7]
    36CLK_MGT:MUX.MUXBUS28[0]-CLK_MGT:MUX.MUXBUS29[0]-
    CLK_MGT:MUX.MUXBUS28[6]-CLK_MGT:MUX.MUXBUS29[6]-
    37 -CLK_MGT:MUX.MUXBUS28[5]-CLK_MGT:MUX.MUXBUS29[5]
    38CLK_MGT:MUX.MUXBUS28[1]-CLK_MGT:MUX.MUXBUS29[1]-
    CLK_MGT:MUX.MUXBUS28[4]-CLK_MGT:MUX.MUXBUS29[4]-
    39CLK_MGT:MUX.MUXBUS28[2]CLK_MGT:MUX.MUXBUS28[6]CLK_MGT:MUX.MUXBUS29[2]CLK_MGT:MUX.MUXBUS29[6]
    CLK_MGT:MUX.MUXBUS28[1]CLK_MGT:MUX.MUXBUS28[2]CLK_MGT:MUX.MUXBUS29[1]CLK_MGT:MUX.MUXBUS29[2]
    40-CLK_MGT:MUX.MUXBUS28[7]-CLK_MGT:MUX.MUXBUS29[7]
    -CLK_MGT:MUX.MUXBUS28[3]-CLK_MGT:MUX.MUXBUS29[3]
    41 ----
    4243 ----
    44CLK_MGT:MUX.MUXBUS28[3]-CLK_MGT:MUX.MUXBUS29[3]-
    CLK_MGT:MUX.MUXBUS28[0]-CLK_MGT:MUX.MUXBUS29[0]-
    45 ----
    4650 ----
    51-CLK_MGT:MUX.MUXBUS30[4]-CLK_MGT:MUX.MUXBUS31[4]
    -CLK_MGT:MUX.MUXBUS30[7]-CLK_MGT:MUX.MUXBUS31[7]
    52CLK_MGT:MUX.MUXBUS30[0]-CLK_MGT:MUX.MUXBUS31[0]-
    CLK_MGT:MUX.MUXBUS30[6]-CLK_MGT:MUX.MUXBUS31[6]-
    53 -CLK_MGT:MUX.MUXBUS30[5]-CLK_MGT:MUX.MUXBUS31[5]
    54CLK_MGT:MUX.MUXBUS30[1]-CLK_MGT:MUX.MUXBUS31[1]-
    CLK_MGT:MUX.MUXBUS30[4]-CLK_MGT:MUX.MUXBUS31[4]-
    55CLK_MGT:MUX.MUXBUS30[2]CLK_MGT:MUX.MUXBUS30[6]CLK_MGT:MUX.MUXBUS31[2]CLK_MGT:MUX.MUXBUS31[6]
    CLK_MGT:MUX.MUXBUS30[1]CLK_MGT:MUX.MUXBUS30[2]CLK_MGT:MUX.MUXBUS31[1]CLK_MGT:MUX.MUXBUS31[2]
    56-CLK_MGT:MUX.MUXBUS30[7]-CLK_MGT:MUX.MUXBUS31[7]
    -CLK_MGT:MUX.MUXBUS30[3]-CLK_MGT:MUX.MUXBUS31[3]
    57 ----
    5859 ----
    60CLK_MGT:MUX.MUXBUS30[3]-CLK_MGT:MUX.MUXBUS31[3]-
    CLK_MGT:MUX.MUXBUS30[0]-CLK_MGT:MUX.MUXBUS31[0]-
    @@ -4206,50 +4206,50 @@

    CLK_MGT_B
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + +
    CLK_MGT:MUX.MUXBUS0[5, 1, 8][5, 1, 7][5, 1, 5][5, 1, 3][5, 0, 12][5, 0, 7][5, 0, 6][5, 0, 4]
    CLK_MGT:MUX.MUXBUS1[5, 3, 8][5, 3, 7][5, 3, 5][5, 3, 3][5, 2, 12][5, 2, 7][5, 2, 6][5, 2, 4]
    CLK_MGT:MUX.MUXBUS10[6, 1, 24][6, 1, 23][6, 1, 21][6, 1, 19][6, 0, 28][6, 0, 23][6, 0, 22][6, 0, 20]
    CLK_MGT:MUX.MUXBUS11[6, 3, 24][6, 3, 23][6, 3, 21][6, 3, 19][6, 2, 28][6, 2, 23][6, 2, 22][6, 2, 20]
    CLK_MGT:MUX.MUXBUS12[6, 1, 40][6, 1, 39][6, 1, 37][6, 1, 35][6, 0, 44][6, 0, 39][6, 0, 38][6, 0, 36]
    CLK_MGT:MUX.MUXBUS13[6, 3, 40][6, 3, 39][6, 3, 37][6, 3, 35][6, 2, 44][6, 2, 39][6, 2, 38][6, 2, 36]
    CLK_MGT:MUX.MUXBUS14[6, 1, 56][6, 1, 55][6, 1, 53][6, 1, 51][6, 0, 60][6, 0, 55][6, 0, 54][6, 0, 52]
    CLK_MGT:MUX.MUXBUS15[6, 3, 56][6, 3, 55][6, 3, 53][6, 3, 51][6, 2, 60][6, 2, 55][6, 2, 54][6, 2, 52]
    CLK_MGT:MUX.MUXBUS16[7, 1, 8][7, 1, 7][7, 1, 5][7, 1, 3][7, 0, 12][7, 0, 7][7, 0, 6][7, 0, 4]
    CLK_MGT:MUX.MUXBUS17[7, 3, 8][7, 3, 7][7, 3, 5][7, 3, 3][7, 2, 12][7, 2, 7][7, 2, 6][7, 2, 4]
    CLK_MGT:MUX.MUXBUS18[7, 1, 24][7, 1, 23][7, 1, 21][7, 1, 19][7, 0, 28][7, 0, 23][7, 0, 22][7, 0, 20]
    CLK_MGT:MUX.MUXBUS19[7, 3, 24][7, 3, 23][7, 3, 21][7, 3, 19][7, 2, 28][7, 2, 23][7, 2, 22][7, 2, 20]
    CLK_MGT:MUX.MUXBUS2[5, 1, 24][5, 1, 23][5, 1, 21][5, 1, 19][5, 0, 28][5, 0, 23][5, 0, 22][5, 0, 20]
    CLK_MGT:MUX.MUXBUS20[7, 1, 40][7, 1, 39][7, 1, 37][7, 1, 35][7, 0, 44][7, 0, 39][7, 0, 38][7, 0, 36]
    CLK_MGT:MUX.MUXBUS21[7, 3, 40][7, 3, 39][7, 3, 37][7, 3, 35][7, 2, 44][7, 2, 39][7, 2, 38][7, 2, 36]
    CLK_MGT:MUX.MUXBUS22[7, 1, 56][7, 1, 55][7, 1, 53][7, 1, 51][7, 0, 60][7, 0, 55][7, 0, 54][7, 0, 52]
    CLK_MGT:MUX.MUXBUS23[7, 3, 56][7, 3, 55][7, 3, 53][7, 3, 51][7, 2, 60][7, 2, 55][7, 2, 54][7, 2, 52]
    CLK_MGT:MUX.MUXBUS24[8, 1, 8][8, 1, 7][8, 1, 5][8, 1, 3][8, 0, 12][8, 0, 7][8, 0, 6][8, 0, 4]
    CLK_MGT:MUX.MUXBUS25[8, 3, 8][8, 3, 7][8, 3, 5][8, 3, 3][8, 2, 12][8, 2, 7][8, 2, 6][8, 2, 4]
    CLK_MGT:MUX.MUXBUS26[8, 1, 24][8, 1, 23][8, 1, 21][8, 1, 19][8, 0, 28][8, 0, 23][8, 0, 22][8, 0, 20]
    CLK_MGT:MUX.MUXBUS27[8, 3, 24][8, 3, 23][8, 3, 21][8, 3, 19][8, 2, 28][8, 2, 23][8, 2, 22][8, 2, 20]
    CLK_MGT:MUX.MUXBUS28[8, 1, 40][8, 1, 39][8, 1, 37][8, 1, 35][8, 0, 44][8, 0, 39][8, 0, 38][8, 0, 36]
    CLK_MGT:MUX.MUXBUS29[8, 3, 40][8, 3, 39][8, 3, 37][8, 3, 35][8, 2, 44][8, 2, 39][8, 2, 38][8, 2, 36]
    CLK_MGT:MUX.MUXBUS3[5, 3, 24][5, 3, 23][5, 3, 21][5, 3, 19][5, 2, 28][5, 2, 23][5, 2, 22][5, 2, 20]
    CLK_MGT:MUX.MUXBUS30[8, 1, 56][8, 1, 55][8, 1, 53][8, 1, 51][8, 0, 60][8, 0, 55][8, 0, 54][8, 0, 52]
    CLK_MGT:MUX.MUXBUS31[8, 3, 56][8, 3, 55][8, 3, 53][8, 3, 51][8, 2, 60][8, 2, 55][8, 2, 54][8, 2, 52]
    CLK_MGT:MUX.MUXBUS4[5, 1, 40][5, 1, 39][5, 1, 37][5, 1, 35][5, 0, 44][5, 0, 39][5, 0, 38][5, 0, 36]
    CLK_MGT:MUX.MUXBUS5[5, 3, 40][5, 3, 39][5, 3, 37][5, 3, 35][5, 2, 44][5, 2, 39][5, 2, 38][5, 2, 36]
    CLK_MGT:MUX.MUXBUS6[5, 1, 56][5, 1, 55][5, 1, 53][5, 1, 51][5, 0, 60][5, 0, 55][5, 0, 54][5, 0, 52]
    CLK_MGT:MUX.MUXBUS7[5, 3, 56][5, 3, 55][5, 3, 53][5, 3, 51][5, 2, 60][5, 2, 55][5, 2, 54][5, 2, 52]
    CLK_MGT:MUX.MUXBUS8[6, 1, 8][6, 1, 7][6, 1, 5][6, 1, 3][6, 0, 12][6, 0, 7][6, 0, 6][6, 0, 4]
    CLK_MGT:MUX.MUXBUS9[6, 3, 8][6, 3, 7][6, 3, 5][6, 3, 3][6, 2, 12][6, 2, 7][6, 2, 6][6, 2, 4]
    CLK_MGT:MUX.MUXBUS0[5, 1, 3][5, 0, 4][5, 1, 5][5, 0, 6][5, 1, 8][5, 1, 7][5, 0, 7][5, 0, 12]
    CLK_MGT:MUX.MUXBUS1[5, 3, 3][5, 2, 4][5, 3, 5][5, 2, 6][5, 3, 8][5, 3, 7][5, 2, 7][5, 2, 12]
    CLK_MGT:MUX.MUXBUS10[6, 1, 19][6, 0, 20][6, 1, 21][6, 0, 22][6, 1, 24][6, 1, 23][6, 0, 23][6, 0, 28]
    CLK_MGT:MUX.MUXBUS11[6, 3, 19][6, 2, 20][6, 3, 21][6, 2, 22][6, 3, 24][6, 3, 23][6, 2, 23][6, 2, 28]
    CLK_MGT:MUX.MUXBUS12[6, 1, 35][6, 0, 36][6, 1, 37][6, 0, 38][6, 1, 40][6, 1, 39][6, 0, 39][6, 0, 44]
    CLK_MGT:MUX.MUXBUS13[6, 3, 35][6, 2, 36][6, 3, 37][6, 2, 38][6, 3, 40][6, 3, 39][6, 2, 39][6, 2, 44]
    CLK_MGT:MUX.MUXBUS14[6, 1, 51][6, 0, 52][6, 1, 53][6, 0, 54][6, 1, 56][6, 1, 55][6, 0, 55][6, 0, 60]
    CLK_MGT:MUX.MUXBUS15[6, 3, 51][6, 2, 52][6, 3, 53][6, 2, 54][6, 3, 56][6, 3, 55][6, 2, 55][6, 2, 60]
    CLK_MGT:MUX.MUXBUS16[7, 1, 3][7, 0, 4][7, 1, 5][7, 0, 6][7, 1, 8][7, 1, 7][7, 0, 7][7, 0, 12]
    CLK_MGT:MUX.MUXBUS17[7, 3, 3][7, 2, 4][7, 3, 5][7, 2, 6][7, 3, 8][7, 3, 7][7, 2, 7][7, 2, 12]
    CLK_MGT:MUX.MUXBUS18[7, 1, 19][7, 0, 20][7, 1, 21][7, 0, 22][7, 1, 24][7, 1, 23][7, 0, 23][7, 0, 28]
    CLK_MGT:MUX.MUXBUS19[7, 3, 19][7, 2, 20][7, 3, 21][7, 2, 22][7, 3, 24][7, 3, 23][7, 2, 23][7, 2, 28]
    CLK_MGT:MUX.MUXBUS2[5, 1, 19][5, 0, 20][5, 1, 21][5, 0, 22][5, 1, 24][5, 1, 23][5, 0, 23][5, 0, 28]
    CLK_MGT:MUX.MUXBUS20[7, 1, 35][7, 0, 36][7, 1, 37][7, 0, 38][7, 1, 40][7, 1, 39][7, 0, 39][7, 0, 44]
    CLK_MGT:MUX.MUXBUS21[7, 3, 35][7, 2, 36][7, 3, 37][7, 2, 38][7, 3, 40][7, 3, 39][7, 2, 39][7, 2, 44]
    CLK_MGT:MUX.MUXBUS22[7, 1, 51][7, 0, 52][7, 1, 53][7, 0, 54][7, 1, 56][7, 1, 55][7, 0, 55][7, 0, 60]
    CLK_MGT:MUX.MUXBUS23[7, 3, 51][7, 2, 52][7, 3, 53][7, 2, 54][7, 3, 56][7, 3, 55][7, 2, 55][7, 2, 60]
    CLK_MGT:MUX.MUXBUS24[8, 1, 3][8, 0, 4][8, 1, 5][8, 0, 6][8, 1, 8][8, 1, 7][8, 0, 7][8, 0, 12]
    CLK_MGT:MUX.MUXBUS25[8, 3, 3][8, 2, 4][8, 3, 5][8, 2, 6][8, 3, 8][8, 3, 7][8, 2, 7][8, 2, 12]
    CLK_MGT:MUX.MUXBUS26[8, 1, 19][8, 0, 20][8, 1, 21][8, 0, 22][8, 1, 24][8, 1, 23][8, 0, 23][8, 0, 28]
    CLK_MGT:MUX.MUXBUS27[8, 3, 19][8, 2, 20][8, 3, 21][8, 2, 22][8, 3, 24][8, 3, 23][8, 2, 23][8, 2, 28]
    CLK_MGT:MUX.MUXBUS28[8, 1, 35][8, 0, 36][8, 1, 37][8, 0, 38][8, 1, 40][8, 1, 39][8, 0, 39][8, 0, 44]
    CLK_MGT:MUX.MUXBUS29[8, 3, 35][8, 2, 36][8, 3, 37][8, 2, 38][8, 3, 40][8, 3, 39][8, 2, 39][8, 2, 44]
    CLK_MGT:MUX.MUXBUS3[5, 3, 19][5, 2, 20][5, 3, 21][5, 2, 22][5, 3, 24][5, 3, 23][5, 2, 23][5, 2, 28]
    CLK_MGT:MUX.MUXBUS30[8, 1, 51][8, 0, 52][8, 1, 53][8, 0, 54][8, 1, 56][8, 1, 55][8, 0, 55][8, 0, 60]
    CLK_MGT:MUX.MUXBUS31[8, 3, 51][8, 2, 52][8, 3, 53][8, 2, 54][8, 3, 56][8, 3, 55][8, 2, 55][8, 2, 60]
    CLK_MGT:MUX.MUXBUS4[5, 1, 35][5, 0, 36][5, 1, 37][5, 0, 38][5, 1, 40][5, 1, 39][5, 0, 39][5, 0, 44]
    CLK_MGT:MUX.MUXBUS5[5, 3, 35][5, 2, 36][5, 3, 37][5, 2, 38][5, 3, 40][5, 3, 39][5, 2, 39][5, 2, 44]
    CLK_MGT:MUX.MUXBUS6[5, 1, 51][5, 0, 52][5, 1, 53][5, 0, 54][5, 1, 56][5, 1, 55][5, 0, 55][5, 0, 60]
    CLK_MGT:MUX.MUXBUS7[5, 3, 51][5, 2, 52][5, 3, 53][5, 2, 54][5, 3, 56][5, 3, 55][5, 2, 55][5, 2, 60]
    CLK_MGT:MUX.MUXBUS8[6, 1, 3][6, 0, 4][6, 1, 5][6, 0, 6][6, 1, 8][6, 1, 7][6, 0, 7][6, 0, 12]
    CLK_MGT:MUX.MUXBUS9[6, 3, 3][6, 2, 4][6, 3, 5][6, 2, 6][6, 3, 8][6, 3, 7][6, 2, 7][6, 2, 12]
    NONE00000000
    MGT_L200000101
    MGT_L000000110
    PASS00001000
    MGT_L300010100
    MGT_L100100100
    MGT_R101000001
    MGT_L401000010
    MGT_R201010000
    MGT_R001100000
    MGT_R310000010
    MGT_R410100000
    PASS00000001
    MGT_L000010010
    MGT_L400010100
    MGT_R300011000
    MGT_L100100010
    MGT_R000100100
    MGT_R400101000
    MGT_L201000010
    MGT_R101000100
    MGT_L310000010
    MGT_R210000100

    @@ -4274,15 +4274,15 @@

    CLK_MGT_T6 ---- 7 --CLK_MGT:MUX.MUXBUS30[4]-CLK_MGT:MUX.MUXBUS31[4] +-CLK_MGT:MUX.MUXBUS30[3]-CLK_MGT:MUX.MUXBUS31[3] 8 -CLK_MGT:MUX.MUXBUS30[1]CLK_MGT:MUX.MUXBUS30[5]CLK_MGT:MUX.MUXBUS31[1]CLK_MGT:MUX.MUXBUS31[5] +CLK_MGT:MUX.MUXBUS30[1]CLK_MGT:MUX.MUXBUS30[2]CLK_MGT:MUX.MUXBUS31[1]CLK_MGT:MUX.MUXBUS31[2] 9 -CLK_MGT:MUX.MUXBUS30[2]-CLK_MGT:MUX.MUXBUS31[2]- +CLK_MGT:MUX.MUXBUS30[4]-CLK_MGT:MUX.MUXBUS31[4]- 10 --CLK_MGT:MUX.MUXBUS30[6]-CLK_MGT:MUX.MUXBUS31[6] +-CLK_MGT:MUX.MUXBUS30[5]-CLK_MGT:MUX.MUXBUS31[5] 11 -CLK_MGT:MUX.MUXBUS30[3]-CLK_MGT:MUX.MUXBUS31[3]- +CLK_MGT:MUX.MUXBUS30[6]-CLK_MGT:MUX.MUXBUS31[6]- 12 -CLK_MGT:MUX.MUXBUS30[7]-CLK_MGT:MUX.MUXBUS31[7] 13 @@ -4306,15 +4306,15 @@

    CLK_MGT_T22 ---- 23 --CLK_MGT:MUX.MUXBUS28[4]-CLK_MGT:MUX.MUXBUS29[4] +-CLK_MGT:MUX.MUXBUS28[3]-CLK_MGT:MUX.MUXBUS29[3] 24 -CLK_MGT:MUX.MUXBUS28[1]CLK_MGT:MUX.MUXBUS28[5]CLK_MGT:MUX.MUXBUS29[1]CLK_MGT:MUX.MUXBUS29[5] +CLK_MGT:MUX.MUXBUS28[1]CLK_MGT:MUX.MUXBUS28[2]CLK_MGT:MUX.MUXBUS29[1]CLK_MGT:MUX.MUXBUS29[2] 25 -CLK_MGT:MUX.MUXBUS28[2]-CLK_MGT:MUX.MUXBUS29[2]- +CLK_MGT:MUX.MUXBUS28[4]-CLK_MGT:MUX.MUXBUS29[4]- 26 --CLK_MGT:MUX.MUXBUS28[6]-CLK_MGT:MUX.MUXBUS29[6] +-CLK_MGT:MUX.MUXBUS28[5]-CLK_MGT:MUX.MUXBUS29[5] 27 -CLK_MGT:MUX.MUXBUS28[3]-CLK_MGT:MUX.MUXBUS29[3]- +CLK_MGT:MUX.MUXBUS28[6]-CLK_MGT:MUX.MUXBUS29[6]- 28 -CLK_MGT:MUX.MUXBUS28[7]-CLK_MGT:MUX.MUXBUS29[7] 29 @@ -4338,15 +4338,15 @@

    CLK_MGT_T38 ---- 39 --CLK_MGT:MUX.MUXBUS26[4]-CLK_MGT:MUX.MUXBUS27[4] +-CLK_MGT:MUX.MUXBUS26[3]-CLK_MGT:MUX.MUXBUS27[3] 40 -CLK_MGT:MUX.MUXBUS26[1]CLK_MGT:MUX.MUXBUS26[5]CLK_MGT:MUX.MUXBUS27[1]CLK_MGT:MUX.MUXBUS27[5] +CLK_MGT:MUX.MUXBUS26[1]CLK_MGT:MUX.MUXBUS26[2]CLK_MGT:MUX.MUXBUS27[1]CLK_MGT:MUX.MUXBUS27[2] 41 -CLK_MGT:MUX.MUXBUS26[2]-CLK_MGT:MUX.MUXBUS27[2]- +CLK_MGT:MUX.MUXBUS26[4]-CLK_MGT:MUX.MUXBUS27[4]- 42 --CLK_MGT:MUX.MUXBUS26[6]-CLK_MGT:MUX.MUXBUS27[6] +-CLK_MGT:MUX.MUXBUS26[5]-CLK_MGT:MUX.MUXBUS27[5] 43 -CLK_MGT:MUX.MUXBUS26[3]-CLK_MGT:MUX.MUXBUS27[3]- +CLK_MGT:MUX.MUXBUS26[6]-CLK_MGT:MUX.MUXBUS27[6]- 44 -CLK_MGT:MUX.MUXBUS26[7]-CLK_MGT:MUX.MUXBUS27[7] 45 @@ -4370,15 +4370,15 @@

    CLK_MGT_T54 ---- 55 --CLK_MGT:MUX.MUXBUS24[4]-CLK_MGT:MUX.MUXBUS25[4] +-CLK_MGT:MUX.MUXBUS24[3]-CLK_MGT:MUX.MUXBUS25[3] 56 -CLK_MGT:MUX.MUXBUS24[1]CLK_MGT:MUX.MUXBUS24[5]CLK_MGT:MUX.MUXBUS25[1]CLK_MGT:MUX.MUXBUS25[5] +CLK_MGT:MUX.MUXBUS24[1]CLK_MGT:MUX.MUXBUS24[2]CLK_MGT:MUX.MUXBUS25[1]CLK_MGT:MUX.MUXBUS25[2] 57 -CLK_MGT:MUX.MUXBUS24[2]-CLK_MGT:MUX.MUXBUS25[2]- +CLK_MGT:MUX.MUXBUS24[4]-CLK_MGT:MUX.MUXBUS25[4]- 58 --CLK_MGT:MUX.MUXBUS24[6]-CLK_MGT:MUX.MUXBUS25[6] +-CLK_MGT:MUX.MUXBUS24[5]-CLK_MGT:MUX.MUXBUS25[5] 59 -CLK_MGT:MUX.MUXBUS24[3]-CLK_MGT:MUX.MUXBUS25[3]- +CLK_MGT:MUX.MUXBUS24[6]-CLK_MGT:MUX.MUXBUS25[6]- 60 -CLK_MGT:MUX.MUXBUS24[7]-CLK_MGT:MUX.MUXBUS25[7] @@ -4399,15 +4399,15 @@

    CLK_MGT_T6 ---- 7 --CLK_MGT:MUX.MUXBUS22[4]-CLK_MGT:MUX.MUXBUS23[4] +-CLK_MGT:MUX.MUXBUS22[3]-CLK_MGT:MUX.MUXBUS23[3] 8 -CLK_MGT:MUX.MUXBUS22[1]CLK_MGT:MUX.MUXBUS22[5]CLK_MGT:MUX.MUXBUS23[1]CLK_MGT:MUX.MUXBUS23[5] +CLK_MGT:MUX.MUXBUS22[1]CLK_MGT:MUX.MUXBUS22[2]CLK_MGT:MUX.MUXBUS23[1]CLK_MGT:MUX.MUXBUS23[2] 9 -CLK_MGT:MUX.MUXBUS22[2]-CLK_MGT:MUX.MUXBUS23[2]- +CLK_MGT:MUX.MUXBUS22[4]-CLK_MGT:MUX.MUXBUS23[4]- 10 --CLK_MGT:MUX.MUXBUS22[6]-CLK_MGT:MUX.MUXBUS23[6] +-CLK_MGT:MUX.MUXBUS22[5]-CLK_MGT:MUX.MUXBUS23[5] 11 -CLK_MGT:MUX.MUXBUS22[3]-CLK_MGT:MUX.MUXBUS23[3]- +CLK_MGT:MUX.MUXBUS22[6]-CLK_MGT:MUX.MUXBUS23[6]- 12 -CLK_MGT:MUX.MUXBUS22[7]-CLK_MGT:MUX.MUXBUS23[7] 13 @@ -4431,15 +4431,15 @@

    CLK_MGT_T22 ---- 23 --CLK_MGT:MUX.MUXBUS20[4]-CLK_MGT:MUX.MUXBUS21[4] +-CLK_MGT:MUX.MUXBUS20[3]-CLK_MGT:MUX.MUXBUS21[3] 24 -CLK_MGT:MUX.MUXBUS20[1]CLK_MGT:MUX.MUXBUS20[5]CLK_MGT:MUX.MUXBUS21[1]CLK_MGT:MUX.MUXBUS21[5] +CLK_MGT:MUX.MUXBUS20[1]CLK_MGT:MUX.MUXBUS20[2]CLK_MGT:MUX.MUXBUS21[1]CLK_MGT:MUX.MUXBUS21[2] 25 -CLK_MGT:MUX.MUXBUS20[2]-CLK_MGT:MUX.MUXBUS21[2]- +CLK_MGT:MUX.MUXBUS20[4]-CLK_MGT:MUX.MUXBUS21[4]- 26 --CLK_MGT:MUX.MUXBUS20[6]-CLK_MGT:MUX.MUXBUS21[6] +-CLK_MGT:MUX.MUXBUS20[5]-CLK_MGT:MUX.MUXBUS21[5] 27 -CLK_MGT:MUX.MUXBUS20[3]-CLK_MGT:MUX.MUXBUS21[3]- +CLK_MGT:MUX.MUXBUS20[6]-CLK_MGT:MUX.MUXBUS21[6]- 28 -CLK_MGT:MUX.MUXBUS20[7]-CLK_MGT:MUX.MUXBUS21[7] 29 @@ -4463,15 +4463,15 @@

    CLK_MGT_T38 ---- 39 --CLK_MGT:MUX.MUXBUS18[4]-CLK_MGT:MUX.MUXBUS19[4] +-CLK_MGT:MUX.MUXBUS18[3]-CLK_MGT:MUX.MUXBUS19[3] 40 -CLK_MGT:MUX.MUXBUS18[1]CLK_MGT:MUX.MUXBUS18[5]CLK_MGT:MUX.MUXBUS19[1]CLK_MGT:MUX.MUXBUS19[5] +CLK_MGT:MUX.MUXBUS18[1]CLK_MGT:MUX.MUXBUS18[2]CLK_MGT:MUX.MUXBUS19[1]CLK_MGT:MUX.MUXBUS19[2] 41 -CLK_MGT:MUX.MUXBUS18[2]-CLK_MGT:MUX.MUXBUS19[2]- +CLK_MGT:MUX.MUXBUS18[4]-CLK_MGT:MUX.MUXBUS19[4]- 42 --CLK_MGT:MUX.MUXBUS18[6]-CLK_MGT:MUX.MUXBUS19[6] +-CLK_MGT:MUX.MUXBUS18[5]-CLK_MGT:MUX.MUXBUS19[5] 43 -CLK_MGT:MUX.MUXBUS18[3]-CLK_MGT:MUX.MUXBUS19[3]- +CLK_MGT:MUX.MUXBUS18[6]-CLK_MGT:MUX.MUXBUS19[6]- 44 -CLK_MGT:MUX.MUXBUS18[7]-CLK_MGT:MUX.MUXBUS19[7] 45 @@ -4495,15 +4495,15 @@

    CLK_MGT_T54 ---- 55 --CLK_MGT:MUX.MUXBUS16[4]-CLK_MGT:MUX.MUXBUS17[4] +-CLK_MGT:MUX.MUXBUS16[3]-CLK_MGT:MUX.MUXBUS17[3] 56 -CLK_MGT:MUX.MUXBUS16[1]CLK_MGT:MUX.MUXBUS16[5]CLK_MGT:MUX.MUXBUS17[1]CLK_MGT:MUX.MUXBUS17[5] +CLK_MGT:MUX.MUXBUS16[1]CLK_MGT:MUX.MUXBUS16[2]CLK_MGT:MUX.MUXBUS17[1]CLK_MGT:MUX.MUXBUS17[2] 57 -CLK_MGT:MUX.MUXBUS16[2]-CLK_MGT:MUX.MUXBUS17[2]- +CLK_MGT:MUX.MUXBUS16[4]-CLK_MGT:MUX.MUXBUS17[4]- 58 --CLK_MGT:MUX.MUXBUS16[6]-CLK_MGT:MUX.MUXBUS17[6] +-CLK_MGT:MUX.MUXBUS16[5]-CLK_MGT:MUX.MUXBUS17[5] 59 -CLK_MGT:MUX.MUXBUS16[3]-CLK_MGT:MUX.MUXBUS17[3]- +CLK_MGT:MUX.MUXBUS16[6]-CLK_MGT:MUX.MUXBUS17[6]- 60 -CLK_MGT:MUX.MUXBUS16[7]-CLK_MGT:MUX.MUXBUS17[7] @@ -4524,15 +4524,15 @@

    CLK_MGT_T6 ---- 7 --CLK_MGT:MUX.MUXBUS14[4]-CLK_MGT:MUX.MUXBUS15[4] +-CLK_MGT:MUX.MUXBUS14[3]-CLK_MGT:MUX.MUXBUS15[3] 8 -CLK_MGT:MUX.MUXBUS14[1]CLK_MGT:MUX.MUXBUS14[5]CLK_MGT:MUX.MUXBUS15[1]CLK_MGT:MUX.MUXBUS15[5] +CLK_MGT:MUX.MUXBUS14[1]CLK_MGT:MUX.MUXBUS14[2]CLK_MGT:MUX.MUXBUS15[1]CLK_MGT:MUX.MUXBUS15[2] 9 -CLK_MGT:MUX.MUXBUS14[2]-CLK_MGT:MUX.MUXBUS15[2]- +CLK_MGT:MUX.MUXBUS14[4]-CLK_MGT:MUX.MUXBUS15[4]- 10 --CLK_MGT:MUX.MUXBUS14[6]-CLK_MGT:MUX.MUXBUS15[6] +-CLK_MGT:MUX.MUXBUS14[5]-CLK_MGT:MUX.MUXBUS15[5] 11 -CLK_MGT:MUX.MUXBUS14[3]-CLK_MGT:MUX.MUXBUS15[3]- +CLK_MGT:MUX.MUXBUS14[6]-CLK_MGT:MUX.MUXBUS15[6]- 12 -CLK_MGT:MUX.MUXBUS14[7]-CLK_MGT:MUX.MUXBUS15[7] 13 @@ -4556,15 +4556,15 @@

    CLK_MGT_T22 ---- 23 --CLK_MGT:MUX.MUXBUS12[4]-CLK_MGT:MUX.MUXBUS13[4] +-CLK_MGT:MUX.MUXBUS12[3]-CLK_MGT:MUX.MUXBUS13[3] 24 -CLK_MGT:MUX.MUXBUS12[1]CLK_MGT:MUX.MUXBUS12[5]CLK_MGT:MUX.MUXBUS13[1]CLK_MGT:MUX.MUXBUS13[5] +CLK_MGT:MUX.MUXBUS12[1]CLK_MGT:MUX.MUXBUS12[2]CLK_MGT:MUX.MUXBUS13[1]CLK_MGT:MUX.MUXBUS13[2] 25 -CLK_MGT:MUX.MUXBUS12[2]-CLK_MGT:MUX.MUXBUS13[2]- +CLK_MGT:MUX.MUXBUS12[4]-CLK_MGT:MUX.MUXBUS13[4]- 26 --CLK_MGT:MUX.MUXBUS12[6]-CLK_MGT:MUX.MUXBUS13[6] +-CLK_MGT:MUX.MUXBUS12[5]-CLK_MGT:MUX.MUXBUS13[5] 27 -CLK_MGT:MUX.MUXBUS12[3]-CLK_MGT:MUX.MUXBUS13[3]- +CLK_MGT:MUX.MUXBUS12[6]-CLK_MGT:MUX.MUXBUS13[6]- 28 -CLK_MGT:MUX.MUXBUS12[7]-CLK_MGT:MUX.MUXBUS13[7] 29 @@ -4588,15 +4588,15 @@

    CLK_MGT_T38 ---- 39 --CLK_MGT:MUX.MUXBUS10[4]-CLK_MGT:MUX.MUXBUS11[4] +-CLK_MGT:MUX.MUXBUS10[3]-CLK_MGT:MUX.MUXBUS11[3] 40 -CLK_MGT:MUX.MUXBUS10[1]CLK_MGT:MUX.MUXBUS10[5]CLK_MGT:MUX.MUXBUS11[1]CLK_MGT:MUX.MUXBUS11[5] +CLK_MGT:MUX.MUXBUS10[1]CLK_MGT:MUX.MUXBUS10[2]CLK_MGT:MUX.MUXBUS11[1]CLK_MGT:MUX.MUXBUS11[2] 41 -CLK_MGT:MUX.MUXBUS10[2]-CLK_MGT:MUX.MUXBUS11[2]- +CLK_MGT:MUX.MUXBUS10[4]-CLK_MGT:MUX.MUXBUS11[4]- 42 --CLK_MGT:MUX.MUXBUS10[6]-CLK_MGT:MUX.MUXBUS11[6] +-CLK_MGT:MUX.MUXBUS10[5]-CLK_MGT:MUX.MUXBUS11[5] 43 -CLK_MGT:MUX.MUXBUS10[3]-CLK_MGT:MUX.MUXBUS11[3]- +CLK_MGT:MUX.MUXBUS10[6]-CLK_MGT:MUX.MUXBUS11[6]- 44 -CLK_MGT:MUX.MUXBUS10[7]-CLK_MGT:MUX.MUXBUS11[7] 45 @@ -4620,15 +4620,15 @@

    CLK_MGT_T54 ---- 55 --CLK_MGT:MUX.MUXBUS8[4]-CLK_MGT:MUX.MUXBUS9[4] +-CLK_MGT:MUX.MUXBUS8[3]-CLK_MGT:MUX.MUXBUS9[3] 56 -CLK_MGT:MUX.MUXBUS8[1]CLK_MGT:MUX.MUXBUS8[5]CLK_MGT:MUX.MUXBUS9[1]CLK_MGT:MUX.MUXBUS9[5] +CLK_MGT:MUX.MUXBUS8[1]CLK_MGT:MUX.MUXBUS8[2]CLK_MGT:MUX.MUXBUS9[1]CLK_MGT:MUX.MUXBUS9[2] 57 -CLK_MGT:MUX.MUXBUS8[2]-CLK_MGT:MUX.MUXBUS9[2]- +CLK_MGT:MUX.MUXBUS8[4]-CLK_MGT:MUX.MUXBUS9[4]- 58 --CLK_MGT:MUX.MUXBUS8[6]-CLK_MGT:MUX.MUXBUS9[6] +-CLK_MGT:MUX.MUXBUS8[5]-CLK_MGT:MUX.MUXBUS9[5] 59 -CLK_MGT:MUX.MUXBUS8[3]-CLK_MGT:MUX.MUXBUS9[3]- +CLK_MGT:MUX.MUXBUS8[6]-CLK_MGT:MUX.MUXBUS9[6]- 60 -CLK_MGT:MUX.MUXBUS8[7]-CLK_MGT:MUX.MUXBUS9[7] @@ -4649,15 +4649,15 @@

    CLK_MGT_T6 ---- 7 --CLK_MGT:MUX.MUXBUS6[4]-CLK_MGT:MUX.MUXBUS7[4] +-CLK_MGT:MUX.MUXBUS6[3]-CLK_MGT:MUX.MUXBUS7[3] 8 -CLK_MGT:MUX.MUXBUS6[1]CLK_MGT:MUX.MUXBUS6[5]CLK_MGT:MUX.MUXBUS7[1]CLK_MGT:MUX.MUXBUS7[5] +CLK_MGT:MUX.MUXBUS6[1]CLK_MGT:MUX.MUXBUS6[2]CLK_MGT:MUX.MUXBUS7[1]CLK_MGT:MUX.MUXBUS7[2] 9 -CLK_MGT:MUX.MUXBUS6[2]-CLK_MGT:MUX.MUXBUS7[2]- +CLK_MGT:MUX.MUXBUS6[4]-CLK_MGT:MUX.MUXBUS7[4]- 10 --CLK_MGT:MUX.MUXBUS6[6]-CLK_MGT:MUX.MUXBUS7[6] +-CLK_MGT:MUX.MUXBUS6[5]-CLK_MGT:MUX.MUXBUS7[5] 11 -CLK_MGT:MUX.MUXBUS6[3]-CLK_MGT:MUX.MUXBUS7[3]- +CLK_MGT:MUX.MUXBUS6[6]-CLK_MGT:MUX.MUXBUS7[6]- 12 -CLK_MGT:MUX.MUXBUS6[7]-CLK_MGT:MUX.MUXBUS7[7] 13 @@ -4681,15 +4681,15 @@

    CLK_MGT_T22 ---- 23 --CLK_MGT:MUX.MUXBUS4[4]-CLK_MGT:MUX.MUXBUS5[4] +-CLK_MGT:MUX.MUXBUS4[3]-CLK_MGT:MUX.MUXBUS5[3] 24 -CLK_MGT:MUX.MUXBUS4[1]CLK_MGT:MUX.MUXBUS4[5]CLK_MGT:MUX.MUXBUS5[1]CLK_MGT:MUX.MUXBUS5[5] +CLK_MGT:MUX.MUXBUS4[1]CLK_MGT:MUX.MUXBUS4[2]CLK_MGT:MUX.MUXBUS5[1]CLK_MGT:MUX.MUXBUS5[2] 25 -CLK_MGT:MUX.MUXBUS4[2]-CLK_MGT:MUX.MUXBUS5[2]- +CLK_MGT:MUX.MUXBUS4[4]-CLK_MGT:MUX.MUXBUS5[4]- 26 --CLK_MGT:MUX.MUXBUS4[6]-CLK_MGT:MUX.MUXBUS5[6] +-CLK_MGT:MUX.MUXBUS4[5]-CLK_MGT:MUX.MUXBUS5[5] 27 -CLK_MGT:MUX.MUXBUS4[3]-CLK_MGT:MUX.MUXBUS5[3]- +CLK_MGT:MUX.MUXBUS4[6]-CLK_MGT:MUX.MUXBUS5[6]- 28 -CLK_MGT:MUX.MUXBUS4[7]-CLK_MGT:MUX.MUXBUS5[7] 29 @@ -4713,15 +4713,15 @@

    CLK_MGT_T38 ---- 39 --CLK_MGT:MUX.MUXBUS2[4]-CLK_MGT:MUX.MUXBUS3[4] +-CLK_MGT:MUX.MUXBUS2[3]-CLK_MGT:MUX.MUXBUS3[3] 40 -CLK_MGT:MUX.MUXBUS2[1]CLK_MGT:MUX.MUXBUS2[5]CLK_MGT:MUX.MUXBUS3[1]CLK_MGT:MUX.MUXBUS3[5] +CLK_MGT:MUX.MUXBUS2[1]CLK_MGT:MUX.MUXBUS2[2]CLK_MGT:MUX.MUXBUS3[1]CLK_MGT:MUX.MUXBUS3[2] 41 -CLK_MGT:MUX.MUXBUS2[2]-CLK_MGT:MUX.MUXBUS3[2]- +CLK_MGT:MUX.MUXBUS2[4]-CLK_MGT:MUX.MUXBUS3[4]- 42 --CLK_MGT:MUX.MUXBUS2[6]-CLK_MGT:MUX.MUXBUS3[6] +-CLK_MGT:MUX.MUXBUS2[5]-CLK_MGT:MUX.MUXBUS3[5] 43 -CLK_MGT:MUX.MUXBUS2[3]-CLK_MGT:MUX.MUXBUS3[3]- +CLK_MGT:MUX.MUXBUS2[6]-CLK_MGT:MUX.MUXBUS3[6]- 44 -CLK_MGT:MUX.MUXBUS2[7]-CLK_MGT:MUX.MUXBUS3[7] 45 @@ -4745,15 +4745,15 @@

    CLK_MGT_T54 ---- 55 --CLK_MGT:MUX.MUXBUS0[4]-CLK_MGT:MUX.MUXBUS1[4] +-CLK_MGT:MUX.MUXBUS0[3]-CLK_MGT:MUX.MUXBUS1[3] 56 -CLK_MGT:MUX.MUXBUS0[1]CLK_MGT:MUX.MUXBUS0[5]CLK_MGT:MUX.MUXBUS1[1]CLK_MGT:MUX.MUXBUS1[5] +CLK_MGT:MUX.MUXBUS0[1]CLK_MGT:MUX.MUXBUS0[2]CLK_MGT:MUX.MUXBUS1[1]CLK_MGT:MUX.MUXBUS1[2] 57 -CLK_MGT:MUX.MUXBUS0[2]-CLK_MGT:MUX.MUXBUS1[2]- +CLK_MGT:MUX.MUXBUS0[4]-CLK_MGT:MUX.MUXBUS1[4]- 58 --CLK_MGT:MUX.MUXBUS0[6]-CLK_MGT:MUX.MUXBUS1[6] +-CLK_MGT:MUX.MUXBUS0[5]-CLK_MGT:MUX.MUXBUS1[5] 59 -CLK_MGT:MUX.MUXBUS0[3]-CLK_MGT:MUX.MUXBUS1[3]- +CLK_MGT:MUX.MUXBUS0[6]-CLK_MGT:MUX.MUXBUS1[6]- 60 -CLK_MGT:MUX.MUXBUS0[7]-CLK_MGT:MUX.MUXBUS1[7] @@ -4930,50 +4930,50 @@

    CLK_MGT_T
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - + + + + + + + + - +
    CLK_MGT:MUX.MUXBUS0[4, 1, 60][4, 1, 58][4, 1, 56][4, 1, 55][4, 0, 59][4, 0, 57][4, 0, 56][4, 0, 51]
    CLK_MGT:MUX.MUXBUS1[4, 3, 60][4, 3, 58][4, 3, 56][4, 3, 55][4, 2, 59][4, 2, 57][4, 2, 56][4, 2, 51]
    CLK_MGT:MUX.MUXBUS10[3, 1, 44][3, 1, 42][3, 1, 40][3, 1, 39][3, 0, 43][3, 0, 41][3, 0, 40][3, 0, 35]
    CLK_MGT:MUX.MUXBUS11[3, 3, 44][3, 3, 42][3, 3, 40][3, 3, 39][3, 2, 43][3, 2, 41][3, 2, 40][3, 2, 35]
    CLK_MGT:MUX.MUXBUS12[3, 1, 28][3, 1, 26][3, 1, 24][3, 1, 23][3, 0, 27][3, 0, 25][3, 0, 24][3, 0, 19]
    CLK_MGT:MUX.MUXBUS13[3, 3, 28][3, 3, 26][3, 3, 24][3, 3, 23][3, 2, 27][3, 2, 25][3, 2, 24][3, 2, 19]
    CLK_MGT:MUX.MUXBUS14[3, 1, 12][3, 1, 10][3, 1, 8][3, 1, 7][3, 0, 11][3, 0, 9][3, 0, 8][3, 0, 3]
    CLK_MGT:MUX.MUXBUS15[3, 3, 12][3, 3, 10][3, 3, 8][3, 3, 7][3, 2, 11][3, 2, 9][3, 2, 8][3, 2, 3]
    CLK_MGT:MUX.MUXBUS16[2, 1, 60][2, 1, 58][2, 1, 56][2, 1, 55][2, 0, 59][2, 0, 57][2, 0, 56][2, 0, 51]
    CLK_MGT:MUX.MUXBUS17[2, 3, 60][2, 3, 58][2, 3, 56][2, 3, 55][2, 2, 59][2, 2, 57][2, 2, 56][2, 2, 51]
    CLK_MGT:MUX.MUXBUS18[2, 1, 44][2, 1, 42][2, 1, 40][2, 1, 39][2, 0, 43][2, 0, 41][2, 0, 40][2, 0, 35]
    CLK_MGT:MUX.MUXBUS19[2, 3, 44][2, 3, 42][2, 3, 40][2, 3, 39][2, 2, 43][2, 2, 41][2, 2, 40][2, 2, 35]
    CLK_MGT:MUX.MUXBUS2[4, 1, 44][4, 1, 42][4, 1, 40][4, 1, 39][4, 0, 43][4, 0, 41][4, 0, 40][4, 0, 35]
    CLK_MGT:MUX.MUXBUS20[2, 1, 28][2, 1, 26][2, 1, 24][2, 1, 23][2, 0, 27][2, 0, 25][2, 0, 24][2, 0, 19]
    CLK_MGT:MUX.MUXBUS21[2, 3, 28][2, 3, 26][2, 3, 24][2, 3, 23][2, 2, 27][2, 2, 25][2, 2, 24][2, 2, 19]
    CLK_MGT:MUX.MUXBUS22[2, 1, 12][2, 1, 10][2, 1, 8][2, 1, 7][2, 0, 11][2, 0, 9][2, 0, 8][2, 0, 3]
    CLK_MGT:MUX.MUXBUS23[2, 3, 12][2, 3, 10][2, 3, 8][2, 3, 7][2, 2, 11][2, 2, 9][2, 2, 8][2, 2, 3]
    CLK_MGT:MUX.MUXBUS24[1, 1, 60][1, 1, 58][1, 1, 56][1, 1, 55][1, 0, 59][1, 0, 57][1, 0, 56][1, 0, 51]
    CLK_MGT:MUX.MUXBUS25[1, 3, 60][1, 3, 58][1, 3, 56][1, 3, 55][1, 2, 59][1, 2, 57][1, 2, 56][1, 2, 51]
    CLK_MGT:MUX.MUXBUS26[1, 1, 44][1, 1, 42][1, 1, 40][1, 1, 39][1, 0, 43][1, 0, 41][1, 0, 40][1, 0, 35]
    CLK_MGT:MUX.MUXBUS27[1, 3, 44][1, 3, 42][1, 3, 40][1, 3, 39][1, 2, 43][1, 2, 41][1, 2, 40][1, 2, 35]
    CLK_MGT:MUX.MUXBUS28[1, 1, 28][1, 1, 26][1, 1, 24][1, 1, 23][1, 0, 27][1, 0, 25][1, 0, 24][1, 0, 19]
    CLK_MGT:MUX.MUXBUS29[1, 3, 28][1, 3, 26][1, 3, 24][1, 3, 23][1, 2, 27][1, 2, 25][1, 2, 24][1, 2, 19]
    CLK_MGT:MUX.MUXBUS3[4, 3, 44][4, 3, 42][4, 3, 40][4, 3, 39][4, 2, 43][4, 2, 41][4, 2, 40][4, 2, 35]
    CLK_MGT:MUX.MUXBUS30[1, 1, 12][1, 1, 10][1, 1, 8][1, 1, 7][1, 0, 11][1, 0, 9][1, 0, 8][1, 0, 3]
    CLK_MGT:MUX.MUXBUS31[1, 3, 12][1, 3, 10][1, 3, 8][1, 3, 7][1, 2, 11][1, 2, 9][1, 2, 8][1, 2, 3]
    CLK_MGT:MUX.MUXBUS4[4, 1, 28][4, 1, 26][4, 1, 24][4, 1, 23][4, 0, 27][4, 0, 25][4, 0, 24][4, 0, 19]
    CLK_MGT:MUX.MUXBUS5[4, 3, 28][4, 3, 26][4, 3, 24][4, 3, 23][4, 2, 27][4, 2, 25][4, 2, 24][4, 2, 19]
    CLK_MGT:MUX.MUXBUS6[4, 1, 12][4, 1, 10][4, 1, 8][4, 1, 7][4, 0, 11][4, 0, 9][4, 0, 8][4, 0, 3]
    CLK_MGT:MUX.MUXBUS7[4, 3, 12][4, 3, 10][4, 3, 8][4, 3, 7][4, 2, 11][4, 2, 9][4, 2, 8][4, 2, 3]
    CLK_MGT:MUX.MUXBUS8[3, 1, 60][3, 1, 58][3, 1, 56][3, 1, 55][3, 0, 59][3, 0, 57][3, 0, 56][3, 0, 51]
    CLK_MGT:MUX.MUXBUS9[3, 3, 60][3, 3, 58][3, 3, 56][3, 3, 55][3, 2, 59][3, 2, 57][3, 2, 56][3, 2, 51]
    CLK_MGT:MUX.MUXBUS0[4, 1, 60][4, 0, 59][4, 1, 58][4, 0, 57][4, 1, 55][4, 1, 56][4, 0, 56][4, 0, 51]
    CLK_MGT:MUX.MUXBUS1[4, 3, 60][4, 2, 59][4, 3, 58][4, 2, 57][4, 3, 55][4, 3, 56][4, 2, 56][4, 2, 51]
    CLK_MGT:MUX.MUXBUS10[3, 1, 44][3, 0, 43][3, 1, 42][3, 0, 41][3, 1, 39][3, 1, 40][3, 0, 40][3, 0, 35]
    CLK_MGT:MUX.MUXBUS11[3, 3, 44][3, 2, 43][3, 3, 42][3, 2, 41][3, 3, 39][3, 3, 40][3, 2, 40][3, 2, 35]
    CLK_MGT:MUX.MUXBUS12[3, 1, 28][3, 0, 27][3, 1, 26][3, 0, 25][3, 1, 23][3, 1, 24][3, 0, 24][3, 0, 19]
    CLK_MGT:MUX.MUXBUS13[3, 3, 28][3, 2, 27][3, 3, 26][3, 2, 25][3, 3, 23][3, 3, 24][3, 2, 24][3, 2, 19]
    CLK_MGT:MUX.MUXBUS14[3, 1, 12][3, 0, 11][3, 1, 10][3, 0, 9][3, 1, 7][3, 1, 8][3, 0, 8][3, 0, 3]
    CLK_MGT:MUX.MUXBUS15[3, 3, 12][3, 2, 11][3, 3, 10][3, 2, 9][3, 3, 7][3, 3, 8][3, 2, 8][3, 2, 3]
    CLK_MGT:MUX.MUXBUS16[2, 1, 60][2, 0, 59][2, 1, 58][2, 0, 57][2, 1, 55][2, 1, 56][2, 0, 56][2, 0, 51]
    CLK_MGT:MUX.MUXBUS17[2, 3, 60][2, 2, 59][2, 3, 58][2, 2, 57][2, 3, 55][2, 3, 56][2, 2, 56][2, 2, 51]
    CLK_MGT:MUX.MUXBUS18[2, 1, 44][2, 0, 43][2, 1, 42][2, 0, 41][2, 1, 39][2, 1, 40][2, 0, 40][2, 0, 35]
    CLK_MGT:MUX.MUXBUS19[2, 3, 44][2, 2, 43][2, 3, 42][2, 2, 41][2, 3, 39][2, 3, 40][2, 2, 40][2, 2, 35]
    CLK_MGT:MUX.MUXBUS2[4, 1, 44][4, 0, 43][4, 1, 42][4, 0, 41][4, 1, 39][4, 1, 40][4, 0, 40][4, 0, 35]
    CLK_MGT:MUX.MUXBUS20[2, 1, 28][2, 0, 27][2, 1, 26][2, 0, 25][2, 1, 23][2, 1, 24][2, 0, 24][2, 0, 19]
    CLK_MGT:MUX.MUXBUS21[2, 3, 28][2, 2, 27][2, 3, 26][2, 2, 25][2, 3, 23][2, 3, 24][2, 2, 24][2, 2, 19]
    CLK_MGT:MUX.MUXBUS22[2, 1, 12][2, 0, 11][2, 1, 10][2, 0, 9][2, 1, 7][2, 1, 8][2, 0, 8][2, 0, 3]
    CLK_MGT:MUX.MUXBUS23[2, 3, 12][2, 2, 11][2, 3, 10][2, 2, 9][2, 3, 7][2, 3, 8][2, 2, 8][2, 2, 3]
    CLK_MGT:MUX.MUXBUS24[1, 1, 60][1, 0, 59][1, 1, 58][1, 0, 57][1, 1, 55][1, 1, 56][1, 0, 56][1, 0, 51]
    CLK_MGT:MUX.MUXBUS25[1, 3, 60][1, 2, 59][1, 3, 58][1, 2, 57][1, 3, 55][1, 3, 56][1, 2, 56][1, 2, 51]
    CLK_MGT:MUX.MUXBUS26[1, 1, 44][1, 0, 43][1, 1, 42][1, 0, 41][1, 1, 39][1, 1, 40][1, 0, 40][1, 0, 35]
    CLK_MGT:MUX.MUXBUS27[1, 3, 44][1, 2, 43][1, 3, 42][1, 2, 41][1, 3, 39][1, 3, 40][1, 2, 40][1, 2, 35]
    CLK_MGT:MUX.MUXBUS28[1, 1, 28][1, 0, 27][1, 1, 26][1, 0, 25][1, 1, 23][1, 1, 24][1, 0, 24][1, 0, 19]
    CLK_MGT:MUX.MUXBUS29[1, 3, 28][1, 2, 27][1, 3, 26][1, 2, 25][1, 3, 23][1, 3, 24][1, 2, 24][1, 2, 19]
    CLK_MGT:MUX.MUXBUS3[4, 3, 44][4, 2, 43][4, 3, 42][4, 2, 41][4, 3, 39][4, 3, 40][4, 2, 40][4, 2, 35]
    CLK_MGT:MUX.MUXBUS30[1, 1, 12][1, 0, 11][1, 1, 10][1, 0, 9][1, 1, 7][1, 1, 8][1, 0, 8][1, 0, 3]
    CLK_MGT:MUX.MUXBUS31[1, 3, 12][1, 2, 11][1, 3, 10][1, 2, 9][1, 3, 7][1, 3, 8][1, 2, 8][1, 2, 3]
    CLK_MGT:MUX.MUXBUS4[4, 1, 28][4, 0, 27][4, 1, 26][4, 0, 25][4, 1, 23][4, 1, 24][4, 0, 24][4, 0, 19]
    CLK_MGT:MUX.MUXBUS5[4, 3, 28][4, 2, 27][4, 3, 26][4, 2, 25][4, 3, 23][4, 3, 24][4, 2, 24][4, 2, 19]
    CLK_MGT:MUX.MUXBUS6[4, 1, 12][4, 0, 11][4, 1, 10][4, 0, 9][4, 1, 7][4, 1, 8][4, 0, 8][4, 0, 3]
    CLK_MGT:MUX.MUXBUS7[4, 3, 12][4, 2, 11][4, 3, 10][4, 2, 9][4, 3, 7][4, 3, 8][4, 2, 8][4, 2, 3]
    CLK_MGT:MUX.MUXBUS8[3, 1, 60][3, 0, 59][3, 1, 58][3, 0, 57][3, 1, 55][3, 1, 56][3, 0, 56][3, 0, 51]
    CLK_MGT:MUX.MUXBUS9[3, 3, 60][3, 2, 59][3, 3, 58][3, 2, 57][3, 3, 55][3, 3, 56][3, 2, 56][3, 2, 51]
    NONE00000000
    PASS00000001
    MGT_L000000110
    MGT_L200001010
    MGT_R300010100
    MGT_L400100100
    MGT_R100101000
    MGT_L101000010
    MGT_R401010000
    MGT_R001100000
    MGT_L000010010
    MGT_L400010100
    MGT_R300011000
    MGT_L100100010
    MGT_R000100100
    MGT_R400101000
    MGT_L201000010
    MGT_R101000100
    MGT_L310000010
    MGT_R210100000
    MGT_R210000100
    diff --git a/xilinx/virtex5/io.html b/xilinx/virtex5/io.html index cce6c905..57bc89c1 100644 --- a/xilinx/virtex5/io.html +++ b/xilinx/virtex5/io.html @@ -541,9 +541,46 @@

    Bitstream DeviceIODELAY:DEFAULT_IDELAY_VALUE [5][4][3][2][1][0] +xc5vfx100t110010 +xc5vfx130t110111 +xc5vfx200t111000 xc5vfx30t100111 +xc5vfx70t101100 +xc5vlx110101100 +xc5vlx110t101100 +xc5vlx155110010 +xc5vlx155t110010 +xc5vlx20t100111 +xc5vlx220111000 +xc5vlx220t111000 +xc5vlx30100111 +xc5vlx30t100111 +xc5vlx330111000 xc5vlx330t111000 +xc5vlx50100111 +xc5vlx50t100111 +xc5vlx85101100 +xc5vlx85t101100 +xc5vsx240t111000 +xc5vsx35t100111 +xc5vsx50t101011 +xc5vsx95t110010 xc5vtx150t110111 +xc5vtx240t111000 +xq5vfx100t110010 +xq5vfx130t110111 +xq5vfx200t111000 +xq5vfx70t101100 +xq5vlx110101100 +xq5vlx110t101100 +xq5vlx155t110010 +xq5vlx220t111000 +xq5vlx30t100111 +xq5vlx330t111000 +xq5vlx85101100 +xq5vsx240t111000 +xq5vsx50t101011 +xq5vsx95t110010 diff --git a/xilinx/virtex7/bram.html b/xilinx/virtex7/bram.html index eb5f5810..6be720dd 100644 --- a/xilinx/virtex7/bram.html +++ b/xilinx/virtex7/bram.html @@ -67,6 +67,8 @@
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • diff --git a/xilinx/virtex7/clb.html b/xilinx/virtex7/clb.html index cd746ef1..743b3830 100644 --- a/xilinx/virtex7/clb.html +++ b/xilinx/virtex7/clb.html @@ -68,6 +68,8 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • diff --git a/xilinx/virtex7/clock.html b/xilinx/virtex7/clock.html new file mode 100644 index 00000000..51b7b8c8 --- /dev/null +++ b/xilinx/virtex7/clock.html @@ -0,0 +1,5675 @@ + + + + + + + Clock interconnect — Project Combine documentation + + + + + + + + + + + + + + + + + +
    + + +
    + +
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    + +
    +

    Clock interconnect

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    +

    Todo

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    describe this madness

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    +

    HCLK

    +
    IO bittile 0
    RowColumn
    012345678910111213141516171819202122232425262728293031323334353637
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    HCLK bittile 0
    RowColumn
    012345
    0------
    1------
    2------
    3------
    4------
    5------
    6------
    7------
    8------
    9------
    10------
    11------
    12------
    13------
    14HCLK:ENABLE.HCLK8HCLK:MUX.OUT_D6[0]HCLK:MUX.OUT_D7[4]HCLK:MUX.OUT_D6[5]HCLK:MUX.OUT_D6[4]HCLK:MUX.OUT_D7[5]
    15HCLK:MUX.OUT_D6[1]HCLK:MUX.OUT_D6[2]HCLK:MUX.OUT_D7[6]HCLK:MUX.OUT_D6[7]HCLK:MUX.OUT_D6[6]HCLK:MUX.OUT_D7[7]
    16HCLK:MUX.OUT_D6[3]HCLK:MUX.OUT_D8[3]HCLK:MUX.OUT_D7[3]HCLK:MUX.OUT_D7[0]HCLK:MUX.OUT_D7[2]HCLK:MUX.OUT_D7[1]
    17HCLK:MUX.OUT_D8[2]HCLK:MUX.OUT_D8[1]HCLK:MUX.OUT_D9[0]HCLK:MUX.OUT_D9[3]HCLK:MUX.OUT_D9[1]HCLK:MUX.OUT_D9[2]
    18HCLK:MUX.OUT_D8[0]-HCLK:MUX.OUT_D8[7]HCLK:MUX.OUT_D9[6]HCLK:MUX.OUT_D9[7]HCLK:MUX.OUT_D8[6]
    19-HCLK:ENABLE.HCLK9HCLK:MUX.OUT_D8[5]HCLK:MUX.OUT_D9[4]HCLK:MUX.OUT_D9[5]HCLK:MUX.OUT_D8[4]
    20HCLK:MUX.OUT_D10[0]HCLK:MUX.OUT_D10[1]HCLK:MUX.OUT_D11[4]HCLK:MUX.OUT_D10[5]HCLK:MUX.OUT_D10[4]HCLK:MUX.OUT_D11[5]
    21HCLK:MUX.OUT_D10[2]HCLK:MUX.OUT_D10[3]HCLK:MUX.OUT_D11[6]HCLK:MUX.OUT_D10[7]HCLK:MUX.OUT_D10[6]HCLK:MUX.OUT_D11[7]
    22HCLK:ENABLE.HCLK10HCLK:ENABLE.HCLK11HCLK:MUX.OUT_D11[3]HCLK:MUX.OUT_D11[0]HCLK:MUX.OUT_D11[2]HCLK:MUX.OUT_D11[1]
    23HCLK:ENABLE.RCLK0HCLK:ENABLE.RCLK1HCLK:MUX.OUT_U11[0]HCLK:MUX.OUT_U11[3]HCLK:MUX.OUT_U11[1]HCLK:MUX.OUT_U11[2]
    24HCLK:MUX.OUT_U10[3]HCLK:MUX.OUT_U10[2]HCLK:MUX.OUT_U10[7]HCLK:MUX.OUT_U11[6]HCLK:MUX.OUT_U11[7]HCLK:MUX.OUT_U10[6]
    25HCLK:MUX.OUT_U10[1]HCLK:MUX.OUT_U10[0]HCLK:MUX.OUT_U10[5]HCLK:MUX.OUT_U11[4]HCLK:MUX.OUT_U11[5]HCLK:MUX.OUT_U10[4]
    26HCLK:MUX.OUT_U8[0]HCLK:MUX.OUT_U8[1]HCLK:MUX.OUT_U9[4]HCLK:MUX.OUT_U8[5]HCLK:MUX.OUT_U8[4]HCLK:MUX.OUT_U9[5]
    27--HCLK:MUX.OUT_U9[6]HCLK:MUX.OUT_U8[7]HCLK:MUX.OUT_U8[6]HCLK:MUX.OUT_U9[7]
    28HCLK:MUX.OUT_U8[2]HCLK:MUX.OUT_U8[3]HCLK:MUX.OUT_U9[3]HCLK:MUX.OUT_U9[0]HCLK:MUX.OUT_U9[2]HCLK:MUX.OUT_U9[1]
    29HCLK:MUX.OUT_U6[3]HCLK:MUX.OUT_U6[2]HCLK:MUX.OUT_U7[0]HCLK:MUX.OUT_U7[3]HCLK:MUX.OUT_U7[1]HCLK:MUX.OUT_U7[2]
    30HCLK:MUX.OUT_U6[1]HCLK:MUX.OUT_U6[0]HCLK:MUX.OUT_U6[7]HCLK:MUX.OUT_U7[6]HCLK:MUX.OUT_U7[7]HCLK:MUX.OUT_U6[6]
    31HCLK:ENABLE.RCLK2HCLK:ENABLE.RCLK3HCLK:MUX.OUT_U6[5]HCLK:MUX.OUT_U7[4]HCLK:MUX.OUT_U7[5]HCLK:MUX.OUT_U6[4]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    HCLK bittile 1
    RowColumn
    0123456789101112131415161718192021222324
    0-------------------------
    1-------------------------
    2-------------------------
    3-------------------------
    4-------------------------
    5-------------------------
    6-------------------------
    7-------------------------
    8-------------------------
    9-------------------------
    10-------------------------
    11-------------------------
    12-------------------------
    13------------------------HCLK:DRP_MASK_BELOW_R
    14HCLK:ENABLE.HCLK0HCLK:MUX.OUT_D0[0]HCLK:MUX.OUT_D1[4]HCLK:MUX.OUT_D0[5]HCLK:MUX.OUT_D0[4]HCLK:MUX.OUT_D1[5]-------------------
    15HCLK:MUX.OUT_D0[1]HCLK:MUX.OUT_D0[2]HCLK:MUX.OUT_D1[6]HCLK:MUX.OUT_D0[7]HCLK:MUX.OUT_D0[6]HCLK:MUX.OUT_D1[7]-------------------
    16HCLK:MUX.OUT_D0[3]HCLK:MUX.OUT_D2[3]HCLK:MUX.OUT_D1[3]HCLK:MUX.OUT_D1[0]HCLK:MUX.OUT_D1[2]HCLK:MUX.OUT_D1[1]-------------------
    17HCLK:MUX.OUT_D2[2]HCLK:MUX.OUT_D2[1]HCLK:MUX.OUT_D3[0]HCLK:MUX.OUT_D3[3]HCLK:MUX.OUT_D3[1]HCLK:MUX.OUT_D3[2]-------------------
    18HCLK:MUX.OUT_D2[0]-HCLK:MUX.OUT_D2[7]HCLK:MUX.OUT_D3[6]HCLK:MUX.OUT_D3[7]HCLK:MUX.OUT_D2[6]-------------------
    19-HCLK:ENABLE.HCLK1HCLK:MUX.OUT_D2[5]HCLK:MUX.OUT_D3[4]HCLK:MUX.OUT_D3[5]HCLK:MUX.OUT_D2[4]-------------------
    20HCLK:MUX.OUT_D4[0]HCLK:MUX.OUT_D4[1]HCLK:MUX.OUT_D5[4]HCLK:MUX.OUT_D4[5]HCLK:MUX.OUT_D4[4]HCLK:MUX.OUT_D5[5]-------------------
    21HCLK:MUX.OUT_D4[2]HCLK:MUX.OUT_D4[3]HCLK:MUX.OUT_D5[6]HCLK:MUX.OUT_D4[7]HCLK:MUX.OUT_D4[6]HCLK:MUX.OUT_D5[7]-------------------
    22HCLK:ENABLE.HCLK2HCLK:ENABLE.HCLK3HCLK:MUX.OUT_D5[3]HCLK:MUX.OUT_D5[0]HCLK:MUX.OUT_D5[2]HCLK:MUX.OUT_D5[1]-------------------
    23HCLK:ENABLE.HCLK4HCLK:ENABLE.HCLK5HCLK:MUX.OUT_U5[0]HCLK:MUX.OUT_U5[3]HCLK:MUX.OUT_U5[1]HCLK:MUX.OUT_U5[2]-------------------
    24HCLK:MUX.OUT_U4[3]HCLK:MUX.OUT_U4[2]HCLK:MUX.OUT_U4[7]HCLK:MUX.OUT_U5[6]HCLK:MUX.OUT_U5[7]HCLK:MUX.OUT_U4[6]-------------------
    25HCLK:MUX.OUT_U4[1]HCLK:MUX.OUT_U4[0]HCLK:MUX.OUT_U4[5]HCLK:MUX.OUT_U5[4]HCLK:MUX.OUT_U5[5]HCLK:MUX.OUT_U4[4]-------------------
    26HCLK:MUX.OUT_U2[0]HCLK:MUX.OUT_U2[1]HCLK:MUX.OUT_U3[4]HCLK:MUX.OUT_U2[5]HCLK:MUX.OUT_U2[4]HCLK:MUX.OUT_U3[5]-------------------
    27--HCLK:MUX.OUT_U3[6]HCLK:MUX.OUT_U2[7]HCLK:MUX.OUT_U2[6]HCLK:MUX.OUT_U3[7]-------------------
    28HCLK:MUX.OUT_U2[2]HCLK:MUX.OUT_U2[3]HCLK:MUX.OUT_U3[3]HCLK:MUX.OUT_U3[0]HCLK:MUX.OUT_U3[2]HCLK:MUX.OUT_U3[1]-------------------
    29HCLK:MUX.OUT_U0[3]HCLK:MUX.OUT_U0[2]HCLK:MUX.OUT_U1[0]HCLK:MUX.OUT_U1[3]HCLK:MUX.OUT_U1[1]HCLK:MUX.OUT_U1[2]-------------------
    30HCLK:MUX.OUT_U0[1]HCLK:MUX.OUT_U0[0]HCLK:MUX.OUT_U0[7]HCLK:MUX.OUT_U1[6]HCLK:MUX.OUT_U1[7]HCLK:MUX.OUT_U0[6]-------------------
    31HCLK:ENABLE.HCLK6HCLK:ENABLE.HCLK7HCLK:MUX.OUT_U0[5]HCLK:MUX.OUT_U1[4]HCLK:MUX.OUT_U1[5]HCLK:MUX.OUT_U0[4]-------------------
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    HCLK:DRP_MASK_BELOW_R[1, 24, 13]
    HCLK:ENABLE.HCLK0[1, 0, 14]
    HCLK:ENABLE.HCLK1[1, 1, 19]
    HCLK:ENABLE.HCLK10[0, 0, 22]
    HCLK:ENABLE.HCLK11[0, 1, 22]
    HCLK:ENABLE.HCLK2[1, 0, 22]
    HCLK:ENABLE.HCLK3[1, 1, 22]
    HCLK:ENABLE.HCLK4[1, 0, 23]
    HCLK:ENABLE.HCLK5[1, 1, 23]
    HCLK:ENABLE.HCLK6[1, 0, 31]
    HCLK:ENABLE.HCLK7[1, 1, 31]
    HCLK:ENABLE.HCLK8[0, 0, 14]
    HCLK:ENABLE.HCLK9[0, 1, 19]
    HCLK:ENABLE.RCLK0[0, 0, 23]
    HCLK:ENABLE.RCLK1[0, 1, 23]
    HCLK:ENABLE.RCLK2[0, 0, 31]
    HCLK:ENABLE.RCLK3[0, 1, 31]
    Non-inverted[0]
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    HCLK:MUX.OUT_D0[1, 3, 15][1, 4, 15][1, 3, 14][1, 4, 14][1, 0, 16][1, 1, 15][1, 0, 15][1, 1, 14]
    HCLK:MUX.OUT_D1[1, 5, 15][1, 2, 15][1, 5, 14][1, 2, 14][1, 2, 16][1, 4, 16][1, 5, 16][1, 3, 16]
    HCLK:MUX.OUT_D10[0, 3, 21][0, 4, 21][0, 3, 20][0, 4, 20][0, 1, 21][0, 0, 21][0, 1, 20][0, 0, 20]
    HCLK:MUX.OUT_D11[0, 5, 21][0, 2, 21][0, 5, 20][0, 2, 20][0, 2, 22][0, 4, 22][0, 5, 22][0, 3, 22]
    HCLK:MUX.OUT_D2[1, 2, 18][1, 5, 18][1, 2, 19][1, 5, 19][1, 1, 16][1, 0, 17][1, 1, 17][1, 0, 18]
    HCLK:MUX.OUT_D3[1, 4, 18][1, 3, 18][1, 4, 19][1, 3, 19][1, 3, 17][1, 5, 17][1, 4, 17][1, 2, 17]
    HCLK:MUX.OUT_D4[1, 3, 21][1, 4, 21][1, 3, 20][1, 4, 20][1, 1, 21][1, 0, 21][1, 1, 20][1, 0, 20]
    HCLK:MUX.OUT_D5[1, 5, 21][1, 2, 21][1, 5, 20][1, 2, 20][1, 2, 22][1, 4, 22][1, 5, 22][1, 3, 22]
    HCLK:MUX.OUT_D6[0, 3, 15][0, 4, 15][0, 3, 14][0, 4, 14][0, 0, 16][0, 1, 15][0, 0, 15][0, 1, 14]
    HCLK:MUX.OUT_D7[0, 5, 15][0, 2, 15][0, 5, 14][0, 2, 14][0, 2, 16][0, 4, 16][0, 5, 16][0, 3, 16]
    HCLK:MUX.OUT_D8[0, 2, 18][0, 5, 18][0, 2, 19][0, 5, 19][0, 1, 16][0, 0, 17][0, 1, 17][0, 0, 18]
    HCLK:MUX.OUT_D9[0, 4, 18][0, 3, 18][0, 4, 19][0, 3, 19][0, 3, 17][0, 5, 17][0, 4, 17][0, 2, 17]
    HCLK:MUX.OUT_U0[1, 2, 30][1, 5, 30][1, 2, 31][1, 5, 31][1, 0, 29][1, 1, 29][1, 0, 30][1, 1, 30]
    HCLK:MUX.OUT_U1[1, 4, 30][1, 3, 30][1, 4, 31][1, 3, 31][1, 3, 29][1, 5, 29][1, 4, 29][1, 2, 29]
    HCLK:MUX.OUT_U10[0, 2, 24][0, 5, 24][0, 2, 25][0, 5, 25][0, 0, 24][0, 1, 24][0, 0, 25][0, 1, 25]
    HCLK:MUX.OUT_U11[0, 4, 24][0, 3, 24][0, 4, 25][0, 3, 25][0, 3, 23][0, 5, 23][0, 4, 23][0, 2, 23]
    HCLK:MUX.OUT_U2[1, 3, 27][1, 4, 27][1, 3, 26][1, 4, 26][1, 1, 28][1, 0, 28][1, 1, 26][1, 0, 26]
    HCLK:MUX.OUT_U3[1, 5, 27][1, 2, 27][1, 5, 26][1, 2, 26][1, 2, 28][1, 4, 28][1, 5, 28][1, 3, 28]
    HCLK:MUX.OUT_U4[1, 2, 24][1, 5, 24][1, 2, 25][1, 5, 25][1, 0, 24][1, 1, 24][1, 0, 25][1, 1, 25]
    HCLK:MUX.OUT_U5[1, 4, 24][1, 3, 24][1, 4, 25][1, 3, 25][1, 3, 23][1, 5, 23][1, 4, 23][1, 2, 23]
    HCLK:MUX.OUT_U6[0, 2, 30][0, 5, 30][0, 2, 31][0, 5, 31][0, 0, 29][0, 1, 29][0, 0, 30][0, 1, 30]
    HCLK:MUX.OUT_U7[0, 4, 30][0, 3, 30][0, 4, 31][0, 3, 31][0, 3, 29][0, 5, 29][0, 4, 29][0, 2, 29]
    HCLK:MUX.OUT_U8[0, 3, 27][0, 4, 27][0, 3, 26][0, 4, 26][0, 1, 28][0, 0, 28][0, 1, 26][0, 0, 26]
    HCLK:MUX.OUT_U9[0, 5, 27][0, 2, 27][0, 5, 26][0, 2, 26][0, 2, 28][0, 4, 28][0, 5, 28][0, 3, 28]
    NONE00000000
    HCLK000010001
    HCLK400010010
    HCLK800010100
    RCLK000011000
    HCLK100100001
    HCLK500100010
    HCLK900100100
    RCLK100101000
    HCLK201000001
    HCLK601000010
    HCLK1001000100
    RCLK201001000
    HCLK310000001
    HCLK710000010
    HCLK1110000100
    RCLK310001000
    +

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    CLK_BUFG

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG bittile 0
    RowColumn
    0123456789101112131415161718192021222324252627
    0---------------------------BUFGCTRL0:CREATE_EDGE
    1--------------------------~BUFGCTRL0:INV.IGNORE0-
    2--------------------------~BUFGCTRL0:PRESELECT_I0~BUFGCTRL0:INV.CE0
    3---------------------------~BUFGCTRL0:INV.S0
    4--------------------------BUFGCTRL0:MUX.I1[0]-
    5--------------------------BUFGCTRL0:MUX.I1[1]BUFGCTRL0:MUX.I1[2]
    6---------------------------BUFGCTRL0:MUX.I0[1]
    7--------------------------BUFGCTRL0:MUX.I0[2]-
    8--------------------------BUFGCTRL0:MUX.I0[0]-
    9---------------------------BUFGCTRL0:TEST_I0
    10--------------------------BUFGCTRL0:TEST_I1-
    11--------------------------~BUFGCTRL0:INV.S1~BUFGCTRL0:INV.CE1
    12--------------------------BUFGCTRL0:PRESELECT_I1~BUFGCTRL0:INV.IGNORE1
    13---------------------------BUFGCTRL0:INIT_OUT
    14--------------------------BUFGCTRL0:ENABLE.FBBUFGCTRL0:ENABLE.GCLK
    15---------------------------BUFGCTRL0:ENABLE
    16---------------------------BUFGCTRL1:CREATE_EDGE
    17--------------------------~BUFGCTRL1:INV.IGNORE0-
    18--------------------------~BUFGCTRL1:PRESELECT_I0~BUFGCTRL1:INV.CE0
    19---------------------------~BUFGCTRL1:INV.S0
    20--------------------------BUFGCTRL1:MUX.I1[0]-
    21--------------------------BUFGCTRL1:MUX.I1[1]BUFGCTRL1:MUX.I1[2]
    22---------------------------BUFGCTRL1:MUX.I0[1]
    23--------------------------BUFGCTRL1:MUX.I0[2]-
    24--------------------------BUFGCTRL1:MUX.I0[0]-
    25---------------------------BUFGCTRL1:TEST_I0
    26--------------------------BUFGCTRL1:TEST_I1-
    27--------------------------~BUFGCTRL1:INV.S1~BUFGCTRL1:INV.CE1
    28--------------------------BUFGCTRL1:PRESELECT_I1~BUFGCTRL1:INV.IGNORE1
    29---------------------------BUFGCTRL1:INIT_OUT
    30--------------------------BUFGCTRL1:ENABLE.FBBUFGCTRL1:ENABLE.GCLK
    31---------------------------BUFGCTRL1:ENABLE
    32---------------------------BUFGCTRL2:CREATE_EDGE
    33--------------------------~BUFGCTRL2:INV.IGNORE0-
    34--------------------------~BUFGCTRL2:PRESELECT_I0~BUFGCTRL2:INV.CE0
    35---------------------------~BUFGCTRL2:INV.S0
    36--------------------------BUFGCTRL2:MUX.I1[0]-
    37--------------------------BUFGCTRL2:MUX.I1[1]BUFGCTRL2:MUX.I1[2]
    38---------------------------BUFGCTRL2:MUX.I0[1]
    39--------------------------BUFGCTRL2:MUX.I0[2]-
    40--------------------------BUFGCTRL2:MUX.I0[0]-
    41---------------------------BUFGCTRL2:TEST_I0
    42--------------------------BUFGCTRL2:TEST_I1-
    43--------------------------~BUFGCTRL2:INV.S1~BUFGCTRL2:INV.CE1
    44--------------------------BUFGCTRL2:PRESELECT_I1~BUFGCTRL2:INV.IGNORE1
    45---------------------------BUFGCTRL2:INIT_OUT
    46--------------------------BUFGCTRL2:ENABLE.FBBUFGCTRL2:ENABLE.GCLK
    47---------------------------BUFGCTRL2:ENABLE
    48---------------------------BUFGCTRL3:CREATE_EDGE
    49--------------------------~BUFGCTRL3:INV.IGNORE0-
    50--------------------------~BUFGCTRL3:PRESELECT_I0~BUFGCTRL3:INV.CE0
    51---------------------------~BUFGCTRL3:INV.S0
    52--------------------------BUFGCTRL3:MUX.I1[0]-
    53--------------------------BUFGCTRL3:MUX.I1[1]BUFGCTRL3:MUX.I1[2]
    54---------------------------BUFGCTRL3:MUX.I0[1]
    55--------------------------BUFGCTRL3:MUX.I0[2]-
    56--------------------------BUFGCTRL3:MUX.I0[0]-
    57---------------------------BUFGCTRL3:TEST_I0
    58--------------------------BUFGCTRL3:TEST_I1-
    59--------------------------~BUFGCTRL3:INV.S1~BUFGCTRL3:INV.CE1
    60--------------------------BUFGCTRL3:PRESELECT_I1~BUFGCTRL3:INV.IGNORE1
    61---------------------------BUFGCTRL3:INIT_OUT
    62--------------------------BUFGCTRL3:ENABLE.FBBUFGCTRL3:ENABLE.GCLK
    63---------------------------BUFGCTRL3:ENABLE
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG bittile 1
    RowColumn
    0123456789101112131415161718192021222324252627
    0---------------------------BUFGCTRL4:CREATE_EDGE
    1--------------------------~BUFGCTRL4:INV.IGNORE0-
    2--------------------------~BUFGCTRL4:PRESELECT_I0~BUFGCTRL4:INV.CE0
    3---------------------------~BUFGCTRL4:INV.S0
    4--------------------------BUFGCTRL4:MUX.I1[0]-
    5--------------------------BUFGCTRL4:MUX.I1[1]BUFGCTRL4:MUX.I1[2]
    6---------------------------BUFGCTRL4:MUX.I0[1]
    7--------------------------BUFGCTRL4:MUX.I0[2]-
    8--------------------------BUFGCTRL4:MUX.I0[0]-
    9---------------------------BUFGCTRL4:TEST_I0
    10--------------------------BUFGCTRL4:TEST_I1-
    11--------------------------~BUFGCTRL4:INV.S1~BUFGCTRL4:INV.CE1
    12--------------------------BUFGCTRL4:PRESELECT_I1~BUFGCTRL4:INV.IGNORE1
    13---------------------------BUFGCTRL4:INIT_OUT
    14--------------------------BUFGCTRL4:ENABLE.FBBUFGCTRL4:ENABLE.GCLK
    15---------------------------BUFGCTRL4:ENABLE
    16---------------------------BUFGCTRL5:CREATE_EDGE
    17--------------------------~BUFGCTRL5:INV.IGNORE0-
    18--------------------------~BUFGCTRL5:PRESELECT_I0~BUFGCTRL5:INV.CE0
    19---------------------------~BUFGCTRL5:INV.S0
    20--------------------------BUFGCTRL5:MUX.I1[0]-
    21--------------------------BUFGCTRL5:MUX.I1[1]BUFGCTRL5:MUX.I1[2]
    22---------------------------BUFGCTRL5:MUX.I0[1]
    23--------------------------BUFGCTRL5:MUX.I0[2]-
    24--------------------------BUFGCTRL5:MUX.I0[0]-
    25---------------------------BUFGCTRL5:TEST_I0
    26--------------------------BUFGCTRL5:TEST_I1-
    27--------------------------~BUFGCTRL5:INV.S1~BUFGCTRL5:INV.CE1
    28--------------------------BUFGCTRL5:PRESELECT_I1~BUFGCTRL5:INV.IGNORE1
    29---------------------------BUFGCTRL5:INIT_OUT
    30--------------------------BUFGCTRL5:ENABLE.FBBUFGCTRL5:ENABLE.GCLK
    31---------------------------BUFGCTRL5:ENABLE
    32---------------------------BUFGCTRL6:CREATE_EDGE
    33--------------------------~BUFGCTRL6:INV.IGNORE0-
    34--------------------------~BUFGCTRL6:PRESELECT_I0~BUFGCTRL6:INV.CE0
    35---------------------------~BUFGCTRL6:INV.S0
    36--------------------------BUFGCTRL6:MUX.I1[0]-
    37--------------------------BUFGCTRL6:MUX.I1[1]BUFGCTRL6:MUX.I1[2]
    38---------------------------BUFGCTRL6:MUX.I0[1]
    39--------------------------BUFGCTRL6:MUX.I0[2]-
    40--------------------------BUFGCTRL6:MUX.I0[0]-
    41---------------------------BUFGCTRL6:TEST_I0
    42--------------------------BUFGCTRL6:TEST_I1-
    43--------------------------~BUFGCTRL6:INV.S1~BUFGCTRL6:INV.CE1
    44--------------------------BUFGCTRL6:PRESELECT_I1~BUFGCTRL6:INV.IGNORE1
    45---------------------------BUFGCTRL6:INIT_OUT
    46--------------------------BUFGCTRL6:ENABLE.FBBUFGCTRL6:ENABLE.GCLK
    47---------------------------BUFGCTRL6:ENABLE
    48---------------------------BUFGCTRL7:CREATE_EDGE
    49--------------------------~BUFGCTRL7:INV.IGNORE0-
    50--------------------------~BUFGCTRL7:PRESELECT_I0~BUFGCTRL7:INV.CE0
    51---------------------------~BUFGCTRL7:INV.S0
    52--------------------------BUFGCTRL7:MUX.I1[0]-
    53--------------------------BUFGCTRL7:MUX.I1[1]BUFGCTRL7:MUX.I1[2]
    54---------------------------BUFGCTRL7:MUX.I0[1]
    55--------------------------BUFGCTRL7:MUX.I0[2]-
    56--------------------------BUFGCTRL7:MUX.I0[0]-
    57---------------------------BUFGCTRL7:TEST_I0
    58--------------------------BUFGCTRL7:TEST_I1-
    59--------------------------~BUFGCTRL7:INV.S1~BUFGCTRL7:INV.CE1
    60--------------------------BUFGCTRL7:PRESELECT_I1~BUFGCTRL7:INV.IGNORE1
    61---------------------------BUFGCTRL7:INIT_OUT
    62--------------------------BUFGCTRL7:ENABLE.FBBUFGCTRL7:ENABLE.GCLK
    63---------------------------BUFGCTRL7:ENABLE
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG bittile 2
    RowColumn
    0123456789101112131415161718192021222324252627
    0---------------------------BUFGCTRL8:CREATE_EDGE
    1--------------------------~BUFGCTRL8:INV.IGNORE0-
    2--------------------------~BUFGCTRL8:PRESELECT_I0~BUFGCTRL8:INV.CE0
    3---------------------------~BUFGCTRL8:INV.S0
    4--------------------------BUFGCTRL8:MUX.I1[0]-
    5--------------------------BUFGCTRL8:MUX.I1[1]BUFGCTRL8:MUX.I1[2]
    6---------------------------BUFGCTRL8:MUX.I0[1]
    7--------------------------BUFGCTRL8:MUX.I0[2]-
    8--------------------------BUFGCTRL8:MUX.I0[0]-
    9---------------------------BUFGCTRL8:TEST_I0
    10--------------------------BUFGCTRL8:TEST_I1-
    11--------------------------~BUFGCTRL8:INV.S1~BUFGCTRL8:INV.CE1
    12--------------------------BUFGCTRL8:PRESELECT_I1~BUFGCTRL8:INV.IGNORE1
    13---------------------------BUFGCTRL8:INIT_OUT
    14--------------------------BUFGCTRL8:ENABLE.FBBUFGCTRL8:ENABLE.GCLK
    15---------------------------BUFGCTRL8:ENABLE
    16---------------------------BUFGCTRL9:CREATE_EDGE
    17--------------------------~BUFGCTRL9:INV.IGNORE0-
    18--------------------------~BUFGCTRL9:PRESELECT_I0~BUFGCTRL9:INV.CE0
    19---------------------------~BUFGCTRL9:INV.S0
    20--------------------------BUFGCTRL9:MUX.I1[0]-
    21--------------------------BUFGCTRL9:MUX.I1[1]BUFGCTRL9:MUX.I1[2]
    22---------------------------BUFGCTRL9:MUX.I0[1]
    23--------------------------BUFGCTRL9:MUX.I0[2]-
    24--------------------------BUFGCTRL9:MUX.I0[0]-
    25---------------------------BUFGCTRL9:TEST_I0
    26--------------------------BUFGCTRL9:TEST_I1-
    27--------------------------~BUFGCTRL9:INV.S1~BUFGCTRL9:INV.CE1
    28--------------------------BUFGCTRL9:PRESELECT_I1~BUFGCTRL9:INV.IGNORE1
    29---------------------------BUFGCTRL9:INIT_OUT
    30--------------------------BUFGCTRL9:ENABLE.FBBUFGCTRL9:ENABLE.GCLK
    31---------------------------BUFGCTRL9:ENABLE
    32---------------------------BUFGCTRL10:CREATE_EDGE
    33--------------------------~BUFGCTRL10:INV.IGNORE0-
    34--------------------------~BUFGCTRL10:PRESELECT_I0~BUFGCTRL10:INV.CE0
    35---------------------------~BUFGCTRL10:INV.S0
    36--------------------------BUFGCTRL10:MUX.I1[0]-
    37--------------------------BUFGCTRL10:MUX.I1[1]BUFGCTRL10:MUX.I1[2]
    38---------------------------BUFGCTRL10:MUX.I0[1]
    39--------------------------BUFGCTRL10:MUX.I0[2]-
    40--------------------------BUFGCTRL10:MUX.I0[0]-
    41---------------------------BUFGCTRL10:TEST_I0
    42--------------------------BUFGCTRL10:TEST_I1-
    43--------------------------~BUFGCTRL10:INV.S1~BUFGCTRL10:INV.CE1
    44--------------------------BUFGCTRL10:PRESELECT_I1~BUFGCTRL10:INV.IGNORE1
    45---------------------------BUFGCTRL10:INIT_OUT
    46--------------------------BUFGCTRL10:ENABLE.FBBUFGCTRL10:ENABLE.GCLK
    47---------------------------BUFGCTRL10:ENABLE
    48---------------------------BUFGCTRL11:CREATE_EDGE
    49--------------------------~BUFGCTRL11:INV.IGNORE0-
    50--------------------------~BUFGCTRL11:PRESELECT_I0~BUFGCTRL11:INV.CE0
    51---------------------------~BUFGCTRL11:INV.S0
    52--------------------------BUFGCTRL11:MUX.I1[0]-
    53--------------------------BUFGCTRL11:MUX.I1[1]BUFGCTRL11:MUX.I1[2]
    54---------------------------BUFGCTRL11:MUX.I0[1]
    55--------------------------BUFGCTRL11:MUX.I0[2]-
    56--------------------------BUFGCTRL11:MUX.I0[0]-
    57---------------------------BUFGCTRL11:TEST_I0
    58--------------------------BUFGCTRL11:TEST_I1-
    59--------------------------~BUFGCTRL11:INV.S1~BUFGCTRL11:INV.CE1
    60--------------------------BUFGCTRL11:PRESELECT_I1~BUFGCTRL11:INV.IGNORE1
    61---------------------------BUFGCTRL11:INIT_OUT
    62--------------------------BUFGCTRL11:ENABLE.FBBUFGCTRL11:ENABLE.GCLK
    63---------------------------BUFGCTRL11:ENABLE
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG bittile 3
    RowColumn
    0123456789101112131415161718192021222324252627
    0---------------------------BUFGCTRL12:CREATE_EDGE
    1--------------------------~BUFGCTRL12:INV.IGNORE0-
    2--------------------------~BUFGCTRL12:PRESELECT_I0~BUFGCTRL12:INV.CE0
    3---------------------------~BUFGCTRL12:INV.S0
    4--------------------------BUFGCTRL12:MUX.I1[0]-
    5--------------------------BUFGCTRL12:MUX.I1[1]BUFGCTRL12:MUX.I1[2]
    6---------------------------BUFGCTRL12:MUX.I0[1]
    7--------------------------BUFGCTRL12:MUX.I0[2]-
    8--------------------------BUFGCTRL12:MUX.I0[0]-
    9---------------------------BUFGCTRL12:TEST_I0
    10--------------------------BUFGCTRL12:TEST_I1-
    11--------------------------~BUFGCTRL12:INV.S1~BUFGCTRL12:INV.CE1
    12--------------------------BUFGCTRL12:PRESELECT_I1~BUFGCTRL12:INV.IGNORE1
    13---------------------------BUFGCTRL12:INIT_OUT
    14--------------------------BUFGCTRL12:ENABLE.FBBUFGCTRL12:ENABLE.GCLK
    15---------------------------BUFGCTRL12:ENABLE
    16---------------------------BUFGCTRL13:CREATE_EDGE
    17--------------------------~BUFGCTRL13:INV.IGNORE0-
    18--------------------------~BUFGCTRL13:PRESELECT_I0~BUFGCTRL13:INV.CE0
    19---------------------------~BUFGCTRL13:INV.S0
    20--------------------------BUFGCTRL13:MUX.I1[0]-
    21--------------------------BUFGCTRL13:MUX.I1[1]BUFGCTRL13:MUX.I1[2]
    22---------------------------BUFGCTRL13:MUX.I0[1]
    23--------------------------BUFGCTRL13:MUX.I0[2]-
    24--------------------------BUFGCTRL13:MUX.I0[0]-
    25---------------------------BUFGCTRL13:TEST_I0
    26--------------------------BUFGCTRL13:TEST_I1-
    27--------------------------~BUFGCTRL13:INV.S1~BUFGCTRL13:INV.CE1
    28--------------------------BUFGCTRL13:PRESELECT_I1~BUFGCTRL13:INV.IGNORE1
    29---------------------------BUFGCTRL13:INIT_OUT
    30--------------------------BUFGCTRL13:ENABLE.FBBUFGCTRL13:ENABLE.GCLK
    31---------------------------BUFGCTRL13:ENABLE
    32---------------------------BUFGCTRL14:CREATE_EDGE
    33--------------------------~BUFGCTRL14:INV.IGNORE0-
    34--------------------------~BUFGCTRL14:PRESELECT_I0~BUFGCTRL14:INV.CE0
    35---------------------------~BUFGCTRL14:INV.S0
    36--------------------------BUFGCTRL14:MUX.I1[0]-
    37--------------------------BUFGCTRL14:MUX.I1[1]BUFGCTRL14:MUX.I1[2]
    38---------------------------BUFGCTRL14:MUX.I0[1]
    39--------------------------BUFGCTRL14:MUX.I0[2]-
    40--------------------------BUFGCTRL14:MUX.I0[0]-
    41---------------------------BUFGCTRL14:TEST_I0
    42--------------------------BUFGCTRL14:TEST_I1-
    43--------------------------~BUFGCTRL14:INV.S1~BUFGCTRL14:INV.CE1
    44--------------------------BUFGCTRL14:PRESELECT_I1~BUFGCTRL14:INV.IGNORE1
    45---------------------------BUFGCTRL14:INIT_OUT
    46--------------------------BUFGCTRL14:ENABLE.FBBUFGCTRL14:ENABLE.GCLK
    47---------------------------BUFGCTRL14:ENABLE
    48---------------------------BUFGCTRL15:CREATE_EDGE
    49--------------------------~BUFGCTRL15:INV.IGNORE0-
    50--------------------------~BUFGCTRL15:PRESELECT_I0~BUFGCTRL15:INV.CE0
    51---------------------------~BUFGCTRL15:INV.S0
    52--------------------------BUFGCTRL15:MUX.I1[0]-
    53--------------------------BUFGCTRL15:MUX.I1[1]BUFGCTRL15:MUX.I1[2]
    54---------------------------BUFGCTRL15:MUX.I0[1]
    55--------------------------BUFGCTRL15:MUX.I0[2]-
    56--------------------------BUFGCTRL15:MUX.I0[0]-
    57---------------------------BUFGCTRL15:TEST_I0
    58--------------------------BUFGCTRL15:TEST_I1-
    59--------------------------~BUFGCTRL15:INV.S1~BUFGCTRL15:INV.CE1
    60--------------------------BUFGCTRL15:PRESELECT_I1~BUFGCTRL15:INV.IGNORE1
    61---------------------------BUFGCTRL15:INIT_OUT
    62--------------------------BUFGCTRL15:ENABLE.FBBUFGCTRL15:ENABLE.GCLK
    63---------------------------BUFGCTRL15:ENABLE
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFGCTRL0:INV.CE0[0, 27, 2]
    BUFGCTRL0:INV.CE1[0, 27, 11]
    BUFGCTRL0:INV.IGNORE0[0, 26, 1]
    BUFGCTRL0:INV.IGNORE1[0, 27, 12]
    BUFGCTRL0:INV.S0[0, 27, 3]
    BUFGCTRL0:INV.S1[0, 26, 11]
    BUFGCTRL0:PRESELECT_I0[0, 26, 2]
    BUFGCTRL10:INV.CE0[2, 27, 34]
    BUFGCTRL10:INV.CE1[2, 27, 43]
    BUFGCTRL10:INV.IGNORE0[2, 26, 33]
    BUFGCTRL10:INV.IGNORE1[2, 27, 44]
    BUFGCTRL10:INV.S0[2, 27, 35]
    BUFGCTRL10:INV.S1[2, 26, 43]
    BUFGCTRL10:PRESELECT_I0[2, 26, 34]
    BUFGCTRL11:INV.CE0[2, 27, 50]
    BUFGCTRL11:INV.CE1[2, 27, 59]
    BUFGCTRL11:INV.IGNORE0[2, 26, 49]
    BUFGCTRL11:INV.IGNORE1[2, 27, 60]
    BUFGCTRL11:INV.S0[2, 27, 51]
    BUFGCTRL11:INV.S1[2, 26, 59]
    BUFGCTRL11:PRESELECT_I0[2, 26, 50]
    BUFGCTRL12:INV.CE0[3, 27, 2]
    BUFGCTRL12:INV.CE1[3, 27, 11]
    BUFGCTRL12:INV.IGNORE0[3, 26, 1]
    BUFGCTRL12:INV.IGNORE1[3, 27, 12]
    BUFGCTRL12:INV.S0[3, 27, 3]
    BUFGCTRL12:INV.S1[3, 26, 11]
    BUFGCTRL12:PRESELECT_I0[3, 26, 2]
    BUFGCTRL13:INV.CE0[3, 27, 18]
    BUFGCTRL13:INV.CE1[3, 27, 27]
    BUFGCTRL13:INV.IGNORE0[3, 26, 17]
    BUFGCTRL13:INV.IGNORE1[3, 27, 28]
    BUFGCTRL13:INV.S0[3, 27, 19]
    BUFGCTRL13:INV.S1[3, 26, 27]
    BUFGCTRL13:PRESELECT_I0[3, 26, 18]
    BUFGCTRL14:INV.CE0[3, 27, 34]
    BUFGCTRL14:INV.CE1[3, 27, 43]
    BUFGCTRL14:INV.IGNORE0[3, 26, 33]
    BUFGCTRL14:INV.IGNORE1[3, 27, 44]
    BUFGCTRL14:INV.S0[3, 27, 35]
    BUFGCTRL14:INV.S1[3, 26, 43]
    BUFGCTRL14:PRESELECT_I0[3, 26, 34]
    BUFGCTRL15:INV.CE0[3, 27, 50]
    BUFGCTRL15:INV.CE1[3, 27, 59]
    BUFGCTRL15:INV.IGNORE0[3, 26, 49]
    BUFGCTRL15:INV.IGNORE1[3, 27, 60]
    BUFGCTRL15:INV.S0[3, 27, 51]
    BUFGCTRL15:INV.S1[3, 26, 59]
    BUFGCTRL15:PRESELECT_I0[3, 26, 50]
    BUFGCTRL1:INV.CE0[0, 27, 18]
    BUFGCTRL1:INV.CE1[0, 27, 27]
    BUFGCTRL1:INV.IGNORE0[0, 26, 17]
    BUFGCTRL1:INV.IGNORE1[0, 27, 28]
    BUFGCTRL1:INV.S0[0, 27, 19]
    BUFGCTRL1:INV.S1[0, 26, 27]
    BUFGCTRL1:PRESELECT_I0[0, 26, 18]
    BUFGCTRL2:INV.CE0[0, 27, 34]
    BUFGCTRL2:INV.CE1[0, 27, 43]
    BUFGCTRL2:INV.IGNORE0[0, 26, 33]
    BUFGCTRL2:INV.IGNORE1[0, 27, 44]
    BUFGCTRL2:INV.S0[0, 27, 35]
    BUFGCTRL2:INV.S1[0, 26, 43]
    BUFGCTRL2:PRESELECT_I0[0, 26, 34]
    BUFGCTRL3:INV.CE0[0, 27, 50]
    BUFGCTRL3:INV.CE1[0, 27, 59]
    BUFGCTRL3:INV.IGNORE0[0, 26, 49]
    BUFGCTRL3:INV.IGNORE1[0, 27, 60]
    BUFGCTRL3:INV.S0[0, 27, 51]
    BUFGCTRL3:INV.S1[0, 26, 59]
    BUFGCTRL3:PRESELECT_I0[0, 26, 50]
    BUFGCTRL4:INV.CE0[1, 27, 2]
    BUFGCTRL4:INV.CE1[1, 27, 11]
    BUFGCTRL4:INV.IGNORE0[1, 26, 1]
    BUFGCTRL4:INV.IGNORE1[1, 27, 12]
    BUFGCTRL4:INV.S0[1, 27, 3]
    BUFGCTRL4:INV.S1[1, 26, 11]
    BUFGCTRL4:PRESELECT_I0[1, 26, 2]
    BUFGCTRL5:INV.CE0[1, 27, 18]
    BUFGCTRL5:INV.CE1[1, 27, 27]
    BUFGCTRL5:INV.IGNORE0[1, 26, 17]
    BUFGCTRL5:INV.IGNORE1[1, 27, 28]
    BUFGCTRL5:INV.S0[1, 27, 19]
    BUFGCTRL5:INV.S1[1, 26, 27]
    BUFGCTRL5:PRESELECT_I0[1, 26, 18]
    BUFGCTRL6:INV.CE0[1, 27, 34]
    BUFGCTRL6:INV.CE1[1, 27, 43]
    BUFGCTRL6:INV.IGNORE0[1, 26, 33]
    BUFGCTRL6:INV.IGNORE1[1, 27, 44]
    BUFGCTRL6:INV.S0[1, 27, 35]
    BUFGCTRL6:INV.S1[1, 26, 43]
    BUFGCTRL6:PRESELECT_I0[1, 26, 34]
    BUFGCTRL7:INV.CE0[1, 27, 50]
    BUFGCTRL7:INV.CE1[1, 27, 59]
    BUFGCTRL7:INV.IGNORE0[1, 26, 49]
    BUFGCTRL7:INV.IGNORE1[1, 27, 60]
    BUFGCTRL7:INV.S0[1, 27, 51]
    BUFGCTRL7:INV.S1[1, 26, 59]
    BUFGCTRL7:PRESELECT_I0[1, 26, 50]
    BUFGCTRL8:INV.CE0[2, 27, 2]
    BUFGCTRL8:INV.CE1[2, 27, 11]
    BUFGCTRL8:INV.IGNORE0[2, 26, 1]
    BUFGCTRL8:INV.IGNORE1[2, 27, 12]
    BUFGCTRL8:INV.S0[2, 27, 3]
    BUFGCTRL8:INV.S1[2, 26, 11]
    BUFGCTRL8:PRESELECT_I0[2, 26, 2]
    BUFGCTRL9:INV.CE0[2, 27, 18]
    BUFGCTRL9:INV.CE1[2, 27, 27]
    BUFGCTRL9:INV.IGNORE0[2, 26, 17]
    BUFGCTRL9:INV.IGNORE1[2, 27, 28]
    BUFGCTRL9:INV.S0[2, 27, 19]
    BUFGCTRL9:INV.S1[2, 26, 27]
    BUFGCTRL9:PRESELECT_I0[2, 26, 18]
    Inverted~[0]
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    BUFGCTRL0:MUX.I0[0, 26, 7][0, 27, 6][0, 26, 8]
    BUFGCTRL0:MUX.I1[0, 27, 5][0, 26, 5][0, 26, 4]
    BUFGCTRL10:MUX.I0[2, 26, 39][2, 27, 38][2, 26, 40]
    BUFGCTRL10:MUX.I1[2, 27, 37][2, 26, 37][2, 26, 36]
    BUFGCTRL11:MUX.I0[2, 26, 55][2, 27, 54][2, 26, 56]
    BUFGCTRL11:MUX.I1[2, 27, 53][2, 26, 53][2, 26, 52]
    BUFGCTRL12:MUX.I0[3, 26, 7][3, 27, 6][3, 26, 8]
    BUFGCTRL12:MUX.I1[3, 27, 5][3, 26, 5][3, 26, 4]
    BUFGCTRL13:MUX.I0[3, 26, 23][3, 27, 22][3, 26, 24]
    BUFGCTRL13:MUX.I1[3, 27, 21][3, 26, 21][3, 26, 20]
    BUFGCTRL14:MUX.I0[3, 26, 39][3, 27, 38][3, 26, 40]
    BUFGCTRL14:MUX.I1[3, 27, 37][3, 26, 37][3, 26, 36]
    BUFGCTRL15:MUX.I0[3, 26, 55][3, 27, 54][3, 26, 56]
    BUFGCTRL15:MUX.I1[3, 27, 53][3, 26, 53][3, 26, 52]
    BUFGCTRL1:MUX.I0[0, 26, 23][0, 27, 22][0, 26, 24]
    BUFGCTRL1:MUX.I1[0, 27, 21][0, 26, 21][0, 26, 20]
    BUFGCTRL2:MUX.I0[0, 26, 39][0, 27, 38][0, 26, 40]
    BUFGCTRL2:MUX.I1[0, 27, 37][0, 26, 37][0, 26, 36]
    BUFGCTRL3:MUX.I0[0, 26, 55][0, 27, 54][0, 26, 56]
    BUFGCTRL3:MUX.I1[0, 27, 53][0, 26, 53][0, 26, 52]
    BUFGCTRL4:MUX.I0[1, 26, 7][1, 27, 6][1, 26, 8]
    BUFGCTRL4:MUX.I1[1, 27, 5][1, 26, 5][1, 26, 4]
    BUFGCTRL5:MUX.I0[1, 26, 23][1, 27, 22][1, 26, 24]
    BUFGCTRL5:MUX.I1[1, 27, 21][1, 26, 21][1, 26, 20]
    BUFGCTRL6:MUX.I0[1, 26, 39][1, 27, 38][1, 26, 40]
    BUFGCTRL6:MUX.I1[1, 27, 37][1, 26, 37][1, 26, 36]
    BUFGCTRL7:MUX.I0[1, 26, 55][1, 27, 54][1, 26, 56]
    BUFGCTRL7:MUX.I1[1, 27, 53][1, 26, 53][1, 26, 52]
    BUFGCTRL8:MUX.I0[2, 26, 7][2, 27, 6][2, 26, 8]
    BUFGCTRL8:MUX.I1[2, 27, 5][2, 26, 5][2, 26, 4]
    BUFGCTRL9:MUX.I0[2, 26, 23][2, 27, 22][2, 26, 24]
    BUFGCTRL9:MUX.I1[2, 27, 21][2, 26, 21][2, 26, 20]
    CKINT1000
    CASCI001
    CKINT0010
    FB_PREV100
    FB_NEXT110
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFGCTRL0:CREATE_EDGE[0, 27, 0]
    BUFGCTRL0:ENABLE[0, 27, 15]
    BUFGCTRL0:ENABLE.FB[0, 26, 14]
    BUFGCTRL0:ENABLE.GCLK[0, 27, 14]
    BUFGCTRL0:INIT_OUT[0, 27, 13]
    BUFGCTRL0:PRESELECT_I1[0, 26, 12]
    BUFGCTRL0:TEST_I0[0, 27, 9]
    BUFGCTRL0:TEST_I1[0, 26, 10]
    BUFGCTRL10:CREATE_EDGE[2, 27, 32]
    BUFGCTRL10:ENABLE[2, 27, 47]
    BUFGCTRL10:ENABLE.FB[2, 26, 46]
    BUFGCTRL10:ENABLE.GCLK[2, 27, 46]
    BUFGCTRL10:INIT_OUT[2, 27, 45]
    BUFGCTRL10:PRESELECT_I1[2, 26, 44]
    BUFGCTRL10:TEST_I0[2, 27, 41]
    BUFGCTRL10:TEST_I1[2, 26, 42]
    BUFGCTRL11:CREATE_EDGE[2, 27, 48]
    BUFGCTRL11:ENABLE[2, 27, 63]
    BUFGCTRL11:ENABLE.FB[2, 26, 62]
    BUFGCTRL11:ENABLE.GCLK[2, 27, 62]
    BUFGCTRL11:INIT_OUT[2, 27, 61]
    BUFGCTRL11:PRESELECT_I1[2, 26, 60]
    BUFGCTRL11:TEST_I0[2, 27, 57]
    BUFGCTRL11:TEST_I1[2, 26, 58]
    BUFGCTRL12:CREATE_EDGE[3, 27, 0]
    BUFGCTRL12:ENABLE[3, 27, 15]
    BUFGCTRL12:ENABLE.FB[3, 26, 14]
    BUFGCTRL12:ENABLE.GCLK[3, 27, 14]
    BUFGCTRL12:INIT_OUT[3, 27, 13]
    BUFGCTRL12:PRESELECT_I1[3, 26, 12]
    BUFGCTRL12:TEST_I0[3, 27, 9]
    BUFGCTRL12:TEST_I1[3, 26, 10]
    BUFGCTRL13:CREATE_EDGE[3, 27, 16]
    BUFGCTRL13:ENABLE[3, 27, 31]
    BUFGCTRL13:ENABLE.FB[3, 26, 30]
    BUFGCTRL13:ENABLE.GCLK[3, 27, 30]
    BUFGCTRL13:INIT_OUT[3, 27, 29]
    BUFGCTRL13:PRESELECT_I1[3, 26, 28]
    BUFGCTRL13:TEST_I0[3, 27, 25]
    BUFGCTRL13:TEST_I1[3, 26, 26]
    BUFGCTRL14:CREATE_EDGE[3, 27, 32]
    BUFGCTRL14:ENABLE[3, 27, 47]
    BUFGCTRL14:ENABLE.FB[3, 26, 46]
    BUFGCTRL14:ENABLE.GCLK[3, 27, 46]
    BUFGCTRL14:INIT_OUT[3, 27, 45]
    BUFGCTRL14:PRESELECT_I1[3, 26, 44]
    BUFGCTRL14:TEST_I0[3, 27, 41]
    BUFGCTRL14:TEST_I1[3, 26, 42]
    BUFGCTRL15:CREATE_EDGE[3, 27, 48]
    BUFGCTRL15:ENABLE[3, 27, 63]
    BUFGCTRL15:ENABLE.FB[3, 26, 62]
    BUFGCTRL15:ENABLE.GCLK[3, 27, 62]
    BUFGCTRL15:INIT_OUT[3, 27, 61]
    BUFGCTRL15:PRESELECT_I1[3, 26, 60]
    BUFGCTRL15:TEST_I0[3, 27, 57]
    BUFGCTRL15:TEST_I1[3, 26, 58]
    BUFGCTRL1:CREATE_EDGE[0, 27, 16]
    BUFGCTRL1:ENABLE[0, 27, 31]
    BUFGCTRL1:ENABLE.FB[0, 26, 30]
    BUFGCTRL1:ENABLE.GCLK[0, 27, 30]
    BUFGCTRL1:INIT_OUT[0, 27, 29]
    BUFGCTRL1:PRESELECT_I1[0, 26, 28]
    BUFGCTRL1:TEST_I0[0, 27, 25]
    BUFGCTRL1:TEST_I1[0, 26, 26]
    BUFGCTRL2:CREATE_EDGE[0, 27, 32]
    BUFGCTRL2:ENABLE[0, 27, 47]
    BUFGCTRL2:ENABLE.FB[0, 26, 46]
    BUFGCTRL2:ENABLE.GCLK[0, 27, 46]
    BUFGCTRL2:INIT_OUT[0, 27, 45]
    BUFGCTRL2:PRESELECT_I1[0, 26, 44]
    BUFGCTRL2:TEST_I0[0, 27, 41]
    BUFGCTRL2:TEST_I1[0, 26, 42]
    BUFGCTRL3:CREATE_EDGE[0, 27, 48]
    BUFGCTRL3:ENABLE[0, 27, 63]
    BUFGCTRL3:ENABLE.FB[0, 26, 62]
    BUFGCTRL3:ENABLE.GCLK[0, 27, 62]
    BUFGCTRL3:INIT_OUT[0, 27, 61]
    BUFGCTRL3:PRESELECT_I1[0, 26, 60]
    BUFGCTRL3:TEST_I0[0, 27, 57]
    BUFGCTRL3:TEST_I1[0, 26, 58]
    BUFGCTRL4:CREATE_EDGE[1, 27, 0]
    BUFGCTRL4:ENABLE[1, 27, 15]
    BUFGCTRL4:ENABLE.FB[1, 26, 14]
    BUFGCTRL4:ENABLE.GCLK[1, 27, 14]
    BUFGCTRL4:INIT_OUT[1, 27, 13]
    BUFGCTRL4:PRESELECT_I1[1, 26, 12]
    BUFGCTRL4:TEST_I0[1, 27, 9]
    BUFGCTRL4:TEST_I1[1, 26, 10]
    BUFGCTRL5:CREATE_EDGE[1, 27, 16]
    BUFGCTRL5:ENABLE[1, 27, 31]
    BUFGCTRL5:ENABLE.FB[1, 26, 30]
    BUFGCTRL5:ENABLE.GCLK[1, 27, 30]
    BUFGCTRL5:INIT_OUT[1, 27, 29]
    BUFGCTRL5:PRESELECT_I1[1, 26, 28]
    BUFGCTRL5:TEST_I0[1, 27, 25]
    BUFGCTRL5:TEST_I1[1, 26, 26]
    BUFGCTRL6:CREATE_EDGE[1, 27, 32]
    BUFGCTRL6:ENABLE[1, 27, 47]
    BUFGCTRL6:ENABLE.FB[1, 26, 46]
    BUFGCTRL6:ENABLE.GCLK[1, 27, 46]
    BUFGCTRL6:INIT_OUT[1, 27, 45]
    BUFGCTRL6:PRESELECT_I1[1, 26, 44]
    BUFGCTRL6:TEST_I0[1, 27, 41]
    BUFGCTRL6:TEST_I1[1, 26, 42]
    BUFGCTRL7:CREATE_EDGE[1, 27, 48]
    BUFGCTRL7:ENABLE[1, 27, 63]
    BUFGCTRL7:ENABLE.FB[1, 26, 62]
    BUFGCTRL7:ENABLE.GCLK[1, 27, 62]
    BUFGCTRL7:INIT_OUT[1, 27, 61]
    BUFGCTRL7:PRESELECT_I1[1, 26, 60]
    BUFGCTRL7:TEST_I0[1, 27, 57]
    BUFGCTRL7:TEST_I1[1, 26, 58]
    BUFGCTRL8:CREATE_EDGE[2, 27, 0]
    BUFGCTRL8:ENABLE[2, 27, 15]
    BUFGCTRL8:ENABLE.FB[2, 26, 14]
    BUFGCTRL8:ENABLE.GCLK[2, 27, 14]
    BUFGCTRL8:INIT_OUT[2, 27, 13]
    BUFGCTRL8:PRESELECT_I1[2, 26, 12]
    BUFGCTRL8:TEST_I0[2, 27, 9]
    BUFGCTRL8:TEST_I1[2, 26, 10]
    BUFGCTRL9:CREATE_EDGE[2, 27, 16]
    BUFGCTRL9:ENABLE[2, 27, 31]
    BUFGCTRL9:ENABLE.FB[2, 26, 30]
    BUFGCTRL9:ENABLE.GCLK[2, 27, 30]
    BUFGCTRL9:INIT_OUT[2, 27, 29]
    BUFGCTRL9:PRESELECT_I1[2, 26, 28]
    BUFGCTRL9:TEST_I0[2, 27, 25]
    BUFGCTRL9:TEST_I1[2, 26, 26]
    Non-inverted[0]
    +
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    CLK_HROW

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 0
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14------------------------------
    15------------------------------
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20--------------------------CLK_HROW:MUX.CASCO0[0]CLK_HROW:ENABLE.GCLK_TEST0CLK_HROW:MUX.CASCO1[0]CLK_HROW:ENABLE.GCLK_TEST1
    21--------------------------CLK_HROW:INV.GCLK_TEST0-CLK_HROW:INV.GCLK_TEST1-
    22------------------------------
    23------------------------------
    24--------------------------CLK_HROW:MUX.CASCO0[2]CLK_HROW:MUX.CASCO0[1]CLK_HROW:MUX.CASCO1[2]CLK_HROW:MUX.CASCO1[1]
    25--------------------------CLK_HROW:MUX.CASCO0[4]CLK_HROW:MUX.CASCO0[5]CLK_HROW:MUX.CASCO1[4]CLK_HROW:MUX.CASCO1[5]
    26--------------------------CLK_HROW:MUX.CASCO0[3]-CLK_HROW:MUX.CASCO1[3]-
    27------------------------------
    28--------------------------CLK_HROW:MUX.CASCO0[8]CLK_HROW:MUX.CASCO0[9]CLK_HROW:MUX.CASCO1[8]CLK_HROW:MUX.CASCO1[9]
    29--------------------------CLK_HROW:MUX.CASCO0[10]CLK_HROW:MUX.CASCO0[11]CLK_HROW:MUX.CASCO1[10]CLK_HROW:MUX.CASCO1[11]
    30--------------------------CLK_HROW:MUX.CASCO0[12]CLK_HROW:MUX.CASCO0[13]CLK_HROW:MUX.CASCO1[12]CLK_HROW:MUX.CASCO1[13]
    31--------------------------CLK_HROW:MUX.CASCO0[6]CLK_HROW:MUX.CASCO0[7]CLK_HROW:MUX.CASCO1[6]CLK_HROW:MUX.CASCO1[7]
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36--------------------------CLK_HROW:MUX.CASCO2[0]CLK_HROW:ENABLE.GCLK_TEST2CLK_HROW:MUX.CASCO3[0]CLK_HROW:ENABLE.GCLK_TEST3
    37--------------------------CLK_HROW:INV.GCLK_TEST2-CLK_HROW:INV.GCLK_TEST3-
    38------------------------------
    39------------------------------
    40--------------------------CLK_HROW:MUX.CASCO2[2]CLK_HROW:MUX.CASCO2[1]CLK_HROW:MUX.CASCO3[2]CLK_HROW:MUX.CASCO3[1]
    41--------------------------CLK_HROW:MUX.CASCO2[4]CLK_HROW:MUX.CASCO2[5]CLK_HROW:MUX.CASCO3[4]CLK_HROW:MUX.CASCO3[5]
    42--------------------------CLK_HROW:MUX.CASCO2[3]-CLK_HROW:MUX.CASCO3[3]-
    43------------------------------
    44--------------------------CLK_HROW:MUX.CASCO2[8]CLK_HROW:MUX.CASCO2[9]CLK_HROW:MUX.CASCO3[8]CLK_HROW:MUX.CASCO3[9]
    45--------------------------CLK_HROW:MUX.CASCO2[10]CLK_HROW:MUX.CASCO2[11]CLK_HROW:MUX.CASCO3[10]CLK_HROW:MUX.CASCO3[11]
    46--------------------------CLK_HROW:MUX.CASCO2[12]CLK_HROW:MUX.CASCO2[13]CLK_HROW:MUX.CASCO3[12]CLK_HROW:MUX.CASCO3[13]
    47--------------------------CLK_HROW:MUX.CASCO2[6]CLK_HROW:MUX.CASCO2[7]CLK_HROW:MUX.CASCO3[6]CLK_HROW:MUX.CASCO3[7]
    48------------------------------
    49------------------------------
    50------------------------------
    51------------------------------
    52--------------------------CLK_HROW:MUX.CASCO4[0]CLK_HROW:ENABLE.GCLK_TEST4CLK_HROW:MUX.CASCO5[0]CLK_HROW:ENABLE.GCLK_TEST5
    53--------------------------CLK_HROW:INV.GCLK_TEST4-CLK_HROW:INV.GCLK_TEST5-
    54------------------------------
    55------------------------------
    56--------------------------CLK_HROW:MUX.CASCO4[2]CLK_HROW:MUX.CASCO4[1]CLK_HROW:MUX.CASCO5[2]CLK_HROW:MUX.CASCO5[1]
    57--------------------------CLK_HROW:MUX.CASCO4[4]CLK_HROW:MUX.CASCO4[5]CLK_HROW:MUX.CASCO5[4]CLK_HROW:MUX.CASCO5[5]
    58--------------------------CLK_HROW:MUX.CASCO4[3]-CLK_HROW:MUX.CASCO5[3]-
    59------------------------------
    60--------------------------CLK_HROW:MUX.CASCO4[8]CLK_HROW:MUX.CASCO4[9]CLK_HROW:MUX.CASCO5[8]CLK_HROW:MUX.CASCO5[9]
    61--------------------------CLK_HROW:MUX.CASCO4[10]CLK_HROW:MUX.CASCO4[11]CLK_HROW:MUX.CASCO5[10]CLK_HROW:MUX.CASCO5[11]
    62--------------------------CLK_HROW:MUX.CASCO4[12]CLK_HROW:MUX.CASCO4[13]CLK_HROW:MUX.CASCO5[12]CLK_HROW:MUX.CASCO5[13]
    63--------------------------CLK_HROW:MUX.CASCO4[6]CLK_HROW:MUX.CASCO4[7]CLK_HROW:MUX.CASCO5[6]CLK_HROW:MUX.CASCO5[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 1
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4--------------------------CLK_HROW:MUX.CASCO6[0]CLK_HROW:ENABLE.GCLK_TEST6CLK_HROW:MUX.CASCO7[0]CLK_HROW:ENABLE.GCLK_TEST7
    5--------------------------CLK_HROW:INV.GCLK_TEST6-CLK_HROW:INV.GCLK_TEST7-
    6------------------------------
    7------------------------------
    8--------------------------CLK_HROW:MUX.CASCO6[2]CLK_HROW:MUX.CASCO6[1]CLK_HROW:MUX.CASCO7[2]CLK_HROW:MUX.CASCO7[1]
    9--------------------------CLK_HROW:MUX.CASCO6[4]CLK_HROW:MUX.CASCO6[5]CLK_HROW:MUX.CASCO7[4]CLK_HROW:MUX.CASCO7[5]
    10--------------------------CLK_HROW:MUX.CASCO6[3]-CLK_HROW:MUX.CASCO7[3]-
    11------------------------------
    12--------------------------CLK_HROW:MUX.CASCO6[8]CLK_HROW:MUX.CASCO6[9]CLK_HROW:MUX.CASCO7[8]CLK_HROW:MUX.CASCO7[9]
    13--------------------------CLK_HROW:MUX.CASCO6[10]CLK_HROW:MUX.CASCO6[11]CLK_HROW:MUX.CASCO7[10]CLK_HROW:MUX.CASCO7[11]
    14--------------------------CLK_HROW:MUX.CASCO6[12]CLK_HROW:MUX.CASCO6[13]CLK_HROW:MUX.CASCO7[12]CLK_HROW:MUX.CASCO7[13]
    15--------------------------CLK_HROW:MUX.CASCO6[6]CLK_HROW:MUX.CASCO6[7]CLK_HROW:MUX.CASCO7[6]CLK_HROW:MUX.CASCO7[7]
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20--------------------------CLK_HROW:MUX.CASCO8[0]CLK_HROW:ENABLE.GCLK_TEST8CLK_HROW:MUX.CASCO9[0]CLK_HROW:ENABLE.GCLK_TEST9
    21--------------------------CLK_HROW:INV.GCLK_TEST8-CLK_HROW:INV.GCLK_TEST9-
    22------------------------------
    23------------------------------
    24--------------------------CLK_HROW:MUX.CASCO8[2]CLK_HROW:MUX.CASCO8[1]CLK_HROW:MUX.CASCO9[2]CLK_HROW:MUX.CASCO9[1]
    25--------------------------CLK_HROW:MUX.CASCO8[4]CLK_HROW:MUX.CASCO8[5]CLK_HROW:MUX.CASCO9[4]CLK_HROW:MUX.CASCO9[5]
    26--------------------------CLK_HROW:MUX.CASCO8[3]-CLK_HROW:MUX.CASCO9[3]-
    27------------------------------
    28--------------------------CLK_HROW:MUX.CASCO8[8]CLK_HROW:MUX.CASCO8[9]CLK_HROW:MUX.CASCO9[8]CLK_HROW:MUX.CASCO9[9]
    29--------------------------CLK_HROW:MUX.CASCO8[10]CLK_HROW:MUX.CASCO8[11]CLK_HROW:MUX.CASCO9[10]CLK_HROW:MUX.CASCO9[11]
    30--------------------------CLK_HROW:MUX.CASCO8[12]CLK_HROW:MUX.CASCO8[13]CLK_HROW:MUX.CASCO9[12]CLK_HROW:MUX.CASCO9[13]
    31--------------------------CLK_HROW:MUX.CASCO8[6]CLK_HROW:MUX.CASCO8[7]CLK_HROW:MUX.CASCO9[6]CLK_HROW:MUX.CASCO9[7]
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36--------------------------CLK_HROW:MUX.CASCO10[0]CLK_HROW:ENABLE.GCLK_TEST10CLK_HROW:MUX.CASCO11[0]CLK_HROW:ENABLE.GCLK_TEST11
    37--------------------------CLK_HROW:INV.GCLK_TEST10-CLK_HROW:INV.GCLK_TEST11-
    38------------------------------
    39------------------------------
    40--------------------------CLK_HROW:MUX.CASCO10[2]CLK_HROW:MUX.CASCO10[1]CLK_HROW:MUX.CASCO11[2]CLK_HROW:MUX.CASCO11[1]
    41--------------------------CLK_HROW:MUX.CASCO10[4]CLK_HROW:MUX.CASCO10[5]CLK_HROW:MUX.CASCO11[4]CLK_HROW:MUX.CASCO11[5]
    42--------------------------CLK_HROW:MUX.CASCO10[3]-CLK_HROW:MUX.CASCO11[3]-
    43------------------------------
    44--------------------------CLK_HROW:MUX.CASCO10[8]CLK_HROW:MUX.CASCO10[9]CLK_HROW:MUX.CASCO11[8]CLK_HROW:MUX.CASCO11[9]
    45--------------------------CLK_HROW:MUX.CASCO10[10]CLK_HROW:MUX.CASCO10[11]CLK_HROW:MUX.CASCO11[10]CLK_HROW:MUX.CASCO11[11]
    46--------------------------CLK_HROW:MUX.CASCO10[12]CLK_HROW:MUX.CASCO10[13]CLK_HROW:MUX.CASCO11[12]CLK_HROW:MUX.CASCO11[13]
    47--------------------------CLK_HROW:MUX.CASCO10[6]CLK_HROW:MUX.CASCO10[7]CLK_HROW:MUX.CASCO11[6]CLK_HROW:MUX.CASCO11[7]
    48------------------------------
    49------------------------------
    50------------------------------
    51------------------------------
    52--------------------------CLK_HROW:MUX.CASCO12[0]CLK_HROW:ENABLE.GCLK_TEST12CLK_HROW:MUX.CASCO13[0]CLK_HROW:ENABLE.GCLK_TEST13
    53--------------------------CLK_HROW:INV.GCLK_TEST12-CLK_HROW:INV.GCLK_TEST13-
    54------------------------------
    55------------------------------
    56--------------------------CLK_HROW:MUX.CASCO12[2]CLK_HROW:MUX.CASCO12[1]CLK_HROW:MUX.CASCO13[2]CLK_HROW:MUX.CASCO13[1]
    57--------------------------CLK_HROW:MUX.CASCO12[4]CLK_HROW:MUX.CASCO12[5]CLK_HROW:MUX.CASCO13[4]CLK_HROW:MUX.CASCO13[5]
    58--------------------------CLK_HROW:MUX.CASCO12[3]-CLK_HROW:MUX.CASCO13[3]-
    59------------------------------
    60--------------------------CLK_HROW:MUX.CASCO12[8]CLK_HROW:MUX.CASCO12[9]CLK_HROW:MUX.CASCO13[8]CLK_HROW:MUX.CASCO13[9]
    61--------------------------CLK_HROW:MUX.CASCO12[10]CLK_HROW:MUX.CASCO12[11]CLK_HROW:MUX.CASCO13[10]CLK_HROW:MUX.CASCO13[11]
    62--------------------------CLK_HROW:MUX.CASCO12[12]CLK_HROW:MUX.CASCO12[13]CLK_HROW:MUX.CASCO13[12]CLK_HROW:MUX.CASCO13[13]
    63--------------------------CLK_HROW:MUX.CASCO12[6]CLK_HROW:MUX.CASCO12[7]CLK_HROW:MUX.CASCO13[6]CLK_HROW:MUX.CASCO13[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 2
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4--------------------------CLK_HROW:MUX.CASCO14[0]CLK_HROW:ENABLE.GCLK_TEST14CLK_HROW:MUX.CASCO15[0]CLK_HROW:ENABLE.GCLK_TEST15
    5--------------------------CLK_HROW:INV.GCLK_TEST14-CLK_HROW:INV.GCLK_TEST15-
    6------------------------------
    7------------------------------
    8--------------------------CLK_HROW:MUX.CASCO14[2]CLK_HROW:MUX.CASCO14[1]CLK_HROW:MUX.CASCO15[2]CLK_HROW:MUX.CASCO15[1]
    9--------------------------CLK_HROW:MUX.CASCO14[4]CLK_HROW:MUX.CASCO14[5]CLK_HROW:MUX.CASCO15[4]CLK_HROW:MUX.CASCO15[5]
    10--------------------------CLK_HROW:MUX.CASCO14[3]-CLK_HROW:MUX.CASCO15[3]-
    11------------------------------
    12--------------------------CLK_HROW:MUX.CASCO14[8]CLK_HROW:MUX.CASCO14[9]CLK_HROW:MUX.CASCO15[8]CLK_HROW:MUX.CASCO15[9]
    13--------------------------CLK_HROW:MUX.CASCO14[10]CLK_HROW:MUX.CASCO14[11]CLK_HROW:MUX.CASCO15[10]CLK_HROW:MUX.CASCO15[11]
    14--------------------------CLK_HROW:MUX.CASCO14[12]CLK_HROW:MUX.CASCO14[13]CLK_HROW:MUX.CASCO15[12]CLK_HROW:MUX.CASCO15[13]
    15--------------------------CLK_HROW:MUX.CASCO14[6]CLK_HROW:MUX.CASCO14[7]CLK_HROW:MUX.CASCO15[6]CLK_HROW:MUX.CASCO15[7]
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20------------------------------
    21------------------------------
    22------------------------------
    23------------------------------
    24------------------------------
    25------------------------------
    26------------------------------
    27------------------------------
    28------------------------------
    29------------------------------
    30------------------------------
    31------------------------------
    32------------------------------
    33------------------------------
    34------------------------------
    35--------------------------BUFHCE_R0:INIT_OUT~BUFHCE_R0:INV.CEBUFHCE_R1:INIT_OUT~BUFHCE_R1:INV.CE
    36------------------------------
    37------------------------------
    38---------------------------BUFHCE_R0:CE_TYPE-BUFHCE_R1:CE_TYPE
    39---------------------------BUFHCE_R0:ENABLE-BUFHCE_R1:ENABLE
    40--------------------------BUFHCE_R0:MUX.I[4]BUFHCE_R0:MUX.I[5]BUFHCE_R1:MUX.I[4]BUFHCE_R1:MUX.I[5]
    41--------------------------BUFHCE_R0:MUX.I[6]BUFHCE_R0:MUX.I[7]BUFHCE_R1:MUX.I[6]BUFHCE_R1:MUX.I[7]
    42--------------------------BUFHCE_R0:MUX.I[3]BUFHCE_R0:MUX.I[2]BUFHCE_R1:MUX.I[3]BUFHCE_R1:MUX.I[2]
    43--------------------------BUFHCE_R0:MUX.I[1]BUFHCE_R0:MUX.I[0]BUFHCE_R1:MUX.I[1]BUFHCE_R1:MUX.I[0]
    44--------------------------BUFHCE_R0:MUX.I[8]BUFHCE_R0:MUX.I[9]BUFHCE_R1:MUX.I[8]BUFHCE_R1:MUX.I[9]
    45--------------------------BUFHCE_R0:MUX.I[10]BUFHCE_R0:MUX.I[11]BUFHCE_R1:MUX.I[10]BUFHCE_R1:MUX.I[11]
    46--------------------------BUFHCE_R0:MUX.I[12]BUFHCE_R0:MUX.I[13]BUFHCE_R1:MUX.I[12]BUFHCE_R1:MUX.I[13]
    47--------------------------BUFHCE_R0:MUX.I[14]BUFHCE_R0:MUX.I[15]BUFHCE_R1:MUX.I[14]BUFHCE_R1:MUX.I[15]
    48------------------------------
    49------------------------------
    50------------------------------
    51--------------------------BUFHCE_R2:INIT_OUT~BUFHCE_R2:INV.CEBUFHCE_R3:INIT_OUT~BUFHCE_R3:INV.CE
    52------------------------------
    53------------------------------
    54---------------------------BUFHCE_R2:CE_TYPE-BUFHCE_R3:CE_TYPE
    55---------------------------BUFHCE_R2:ENABLE-BUFHCE_R3:ENABLE
    56--------------------------BUFHCE_R2:MUX.I[4]BUFHCE_R2:MUX.I[5]BUFHCE_R3:MUX.I[4]BUFHCE_R3:MUX.I[5]
    57--------------------------BUFHCE_R2:MUX.I[6]BUFHCE_R2:MUX.I[7]BUFHCE_R3:MUX.I[6]BUFHCE_R3:MUX.I[7]
    58--------------------------BUFHCE_R2:MUX.I[3]BUFHCE_R2:MUX.I[2]BUFHCE_R3:MUX.I[3]BUFHCE_R3:MUX.I[2]
    59--------------------------BUFHCE_R2:MUX.I[1]BUFHCE_R2:MUX.I[0]BUFHCE_R3:MUX.I[1]BUFHCE_R3:MUX.I[0]
    60--------------------------BUFHCE_R2:MUX.I[8]BUFHCE_R2:MUX.I[9]BUFHCE_R3:MUX.I[8]BUFHCE_R3:MUX.I[9]
    61--------------------------BUFHCE_R2:MUX.I[10]BUFHCE_R2:MUX.I[11]BUFHCE_R3:MUX.I[10]BUFHCE_R3:MUX.I[11]
    62--------------------------BUFHCE_R2:MUX.I[12]BUFHCE_R2:MUX.I[13]BUFHCE_R3:MUX.I[12]BUFHCE_R3:MUX.I[13]
    63--------------------------BUFHCE_R2:MUX.I[14]BUFHCE_R2:MUX.I[15]BUFHCE_R3:MUX.I[14]BUFHCE_R3:MUX.I[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 3
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3--------------------------BUFHCE_R4:INIT_OUT~BUFHCE_R4:INV.CEBUFHCE_R5:INIT_OUT~BUFHCE_R5:INV.CE
    4------------------------------
    5------------------------------
    6---------------------------BUFHCE_R4:CE_TYPE-BUFHCE_R5:CE_TYPE
    7---------------------------BUFHCE_R4:ENABLE-BUFHCE_R5:ENABLE
    8--------------------------BUFHCE_R4:MUX.I[4]BUFHCE_R4:MUX.I[5]BUFHCE_R5:MUX.I[4]BUFHCE_R5:MUX.I[5]
    9--------------------------BUFHCE_R4:MUX.I[6]BUFHCE_R4:MUX.I[7]BUFHCE_R5:MUX.I[6]BUFHCE_R5:MUX.I[7]
    10--------------------------BUFHCE_R4:MUX.I[3]BUFHCE_R4:MUX.I[2]BUFHCE_R5:MUX.I[3]BUFHCE_R5:MUX.I[2]
    11--------------------------BUFHCE_R4:MUX.I[1]BUFHCE_R4:MUX.I[0]BUFHCE_R5:MUX.I[1]BUFHCE_R5:MUX.I[0]
    12--------------------------BUFHCE_R4:MUX.I[8]BUFHCE_R4:MUX.I[9]BUFHCE_R5:MUX.I[8]BUFHCE_R5:MUX.I[9]
    13--------------------------BUFHCE_R4:MUX.I[10]BUFHCE_R4:MUX.I[11]BUFHCE_R5:MUX.I[10]BUFHCE_R5:MUX.I[11]
    14--------------------------BUFHCE_R4:MUX.I[12]BUFHCE_R4:MUX.I[13]BUFHCE_R5:MUX.I[12]BUFHCE_R5:MUX.I[13]
    15--------------------------BUFHCE_R4:MUX.I[14]BUFHCE_R4:MUX.I[15]BUFHCE_R5:MUX.I[14]BUFHCE_R5:MUX.I[15]
    16------------------------------
    17------------------------------
    18------------------------------
    19--------------------------BUFHCE_L0:INIT_OUT~BUFHCE_L0:INV.CEBUFHCE_L1:INIT_OUT~BUFHCE_L1:INV.CE
    20------------------------------
    21------------------------------
    22---------------------------BUFHCE_L0:CE_TYPE-BUFHCE_L1:CE_TYPE
    23---------------------------BUFHCE_L0:ENABLE-BUFHCE_L1:ENABLE
    24--------------------------BUFHCE_L0:MUX.I[4]BUFHCE_L0:MUX.I[5]BUFHCE_L1:MUX.I[4]BUFHCE_L1:MUX.I[5]
    25--------------------------BUFHCE_L0:MUX.I[6]BUFHCE_L0:MUX.I[7]BUFHCE_L1:MUX.I[6]BUFHCE_L1:MUX.I[7]
    26--------------------------BUFHCE_L0:MUX.I[3]BUFHCE_L0:MUX.I[2]BUFHCE_L1:MUX.I[3]BUFHCE_L1:MUX.I[2]
    27--------------------------BUFHCE_L0:MUX.I[1]BUFHCE_L0:MUX.I[0]BUFHCE_L1:MUX.I[1]BUFHCE_L1:MUX.I[0]
    28--------------------------BUFHCE_L0:MUX.I[8]BUFHCE_L0:MUX.I[9]BUFHCE_L1:MUX.I[8]BUFHCE_L1:MUX.I[9]
    29--------------------------BUFHCE_L0:MUX.I[10]BUFHCE_L0:MUX.I[11]BUFHCE_L1:MUX.I[10]BUFHCE_L1:MUX.I[11]
    30--------------------------BUFHCE_L0:MUX.I[12]BUFHCE_L0:MUX.I[13]BUFHCE_L1:MUX.I[12]BUFHCE_L1:MUX.I[13]
    31--------------------------BUFHCE_L0:MUX.I[14]BUFHCE_L0:MUX.I[15]BUFHCE_L1:MUX.I[14]BUFHCE_L1:MUX.I[15]
    32------------------------------
    33------------------------------
    34------------------------------
    35--------------------------BUFHCE_L2:INIT_OUT~BUFHCE_L2:INV.CEBUFHCE_L3:INIT_OUT~BUFHCE_L3:INV.CE
    36------------------------------
    37------------------------------
    38---------------------------BUFHCE_L2:CE_TYPE-BUFHCE_L3:CE_TYPE
    39---------------------------BUFHCE_L2:ENABLE-BUFHCE_L3:ENABLE
    40--------------------------BUFHCE_L2:MUX.I[4]BUFHCE_L2:MUX.I[5]BUFHCE_L3:MUX.I[4]BUFHCE_L3:MUX.I[5]
    41--------------------------BUFHCE_L2:MUX.I[6]BUFHCE_L2:MUX.I[7]BUFHCE_L3:MUX.I[6]BUFHCE_L3:MUX.I[7]
    42--------------------------BUFHCE_L2:MUX.I[3]BUFHCE_L2:MUX.I[2]BUFHCE_L3:MUX.I[3]BUFHCE_L3:MUX.I[2]
    43--------------------------BUFHCE_L2:MUX.I[1]BUFHCE_L2:MUX.I[0]BUFHCE_L3:MUX.I[1]BUFHCE_L3:MUX.I[0]
    44--------------------------BUFHCE_L2:MUX.I[8]BUFHCE_L2:MUX.I[9]BUFHCE_L3:MUX.I[8]BUFHCE_L3:MUX.I[9]
    45--------------------------BUFHCE_L2:MUX.I[10]BUFHCE_L2:MUX.I[11]BUFHCE_L3:MUX.I[10]BUFHCE_L3:MUX.I[11]
    46--------------------------BUFHCE_L2:MUX.I[12]BUFHCE_L2:MUX.I[13]BUFHCE_L3:MUX.I[12]BUFHCE_L3:MUX.I[13]
    47--------------------------BUFHCE_L2:MUX.I[14]BUFHCE_L2:MUX.I[15]BUFHCE_L3:MUX.I[14]BUFHCE_L3:MUX.I[15]
    48--------------------------CLK_HROW:ENABLE.HIN10_LCLK_HROW:ENABLE.HIN11_LCLK_HROW:ENABLE.HIN10_RCLK_HROW:ENABLE.HIN11_R
    49--------------------------CLK_HROW:ENABLE.HIN12_LCLK_HROW:ENABLE.HIN13_LCLK_HROW:ENABLE.HIN12_RCLK_HROW:ENABLE.HIN13_R
    50------------------------------
    51--------------------------BUFHCE_L4:INIT_OUT~BUFHCE_L4:INV.CEBUFHCE_L5:INIT_OUT~BUFHCE_L5:INV.CE
    52------------------------------
    53------------------------------
    54---------------------------BUFHCE_L4:CE_TYPE-BUFHCE_L5:CE_TYPE
    55---------------------------BUFHCE_L4:ENABLE-BUFHCE_L5:ENABLE
    56--------------------------BUFHCE_L4:MUX.I[4]BUFHCE_L4:MUX.I[5]BUFHCE_L5:MUX.I[4]BUFHCE_L5:MUX.I[5]
    57--------------------------BUFHCE_L4:MUX.I[6]BUFHCE_L4:MUX.I[7]BUFHCE_L5:MUX.I[6]BUFHCE_L5:MUX.I[7]
    58--------------------------BUFHCE_L4:MUX.I[3]BUFHCE_L4:MUX.I[2]BUFHCE_L5:MUX.I[3]BUFHCE_L5:MUX.I[2]
    59--------------------------BUFHCE_L4:MUX.I[1]BUFHCE_L4:MUX.I[0]BUFHCE_L5:MUX.I[1]BUFHCE_L5:MUX.I[0]
    60--------------------------BUFHCE_L4:MUX.I[8]BUFHCE_L4:MUX.I[9]BUFHCE_L5:MUX.I[8]BUFHCE_L5:MUX.I[9]
    61--------------------------BUFHCE_L4:MUX.I[10]BUFHCE_L4:MUX.I[11]BUFHCE_L5:MUX.I[10]BUFHCE_L5:MUX.I[11]
    62--------------------------BUFHCE_L4:MUX.I[12]BUFHCE_L4:MUX.I[13]BUFHCE_L5:MUX.I[12]BUFHCE_L5:MUX.I[13]
    63--------------------------BUFHCE_L4:MUX.I[14]BUFHCE_L4:MUX.I[15]BUFHCE_L5:MUX.I[14]BUFHCE_L5:MUX.I[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 4
    RowColumn
    01234567891011121314151617181920212223242526272829
    0--------------------------CLK_HROW:INV.HCLK_TEST_LCLK_HROW:MUX.HCLK_TEST_L[4]CLK_HROW:INV.HCLK_TEST_RCLK_HROW:MUX.HCLK_TEST_R[4]
    1--------------------------CLK_HROW:MUX.HCLK_TEST_L[5]CLK_HROW:MUX.HCLK_TEST_L[6]CLK_HROW:MUX.HCLK_TEST_R[5]CLK_HROW:MUX.HCLK_TEST_R[6]
    2--------------------------CLK_HROW:MUX.HCLK_TEST_L[7]-CLK_HROW:MUX.HCLK_TEST_R[7]-
    3--------------------------BUFHCE_L6:INIT_OUT~BUFHCE_L6:INV.CEBUFHCE_L7:INIT_OUT~BUFHCE_L7:INV.CE
    4------------------------------
    5------------------------------
    6---------------------------BUFHCE_L6:CE_TYPE-BUFHCE_L7:CE_TYPE
    7---------------------------BUFHCE_L6:ENABLE-BUFHCE_L7:ENABLE
    8--------------------------BUFHCE_L6:MUX.I[4]BUFHCE_L6:MUX.I[5]BUFHCE_L7:MUX.I[4]BUFHCE_L7:MUX.I[5]
    9--------------------------BUFHCE_L6:MUX.I[6]BUFHCE_L6:MUX.I[7]BUFHCE_L7:MUX.I[6]BUFHCE_L7:MUX.I[7]
    10--------------------------BUFHCE_L6:MUX.I[3]BUFHCE_L6:MUX.I[2]BUFHCE_L7:MUX.I[3]BUFHCE_L7:MUX.I[2]
    11--------------------------BUFHCE_L6:MUX.I[1]BUFHCE_L6:MUX.I[0]BUFHCE_L7:MUX.I[1]BUFHCE_L7:MUX.I[0]
    12--------------------------BUFHCE_L6:MUX.I[8]BUFHCE_L6:MUX.I[9]BUFHCE_L7:MUX.I[8]BUFHCE_L7:MUX.I[9]
    13--------------------------BUFHCE_L6:MUX.I[10]BUFHCE_L6:MUX.I[11]BUFHCE_L7:MUX.I[10]BUFHCE_L7:MUX.I[11]
    14--------------------------BUFHCE_L6:MUX.I[12]BUFHCE_L6:MUX.I[13]BUFHCE_L7:MUX.I[12]BUFHCE_L7:MUX.I[13]
    15--------------------------BUFHCE_L6:MUX.I[14]BUFHCE_L6:MUX.I[15]BUFHCE_L7:MUX.I[14]BUFHCE_L7:MUX.I[15]
    16------------------------------
    17------------------------------
    18------------------------------
    19--------------------------BUFHCE_L8:INIT_OUT~BUFHCE_L8:INV.CEBUFHCE_L9:INIT_OUT~BUFHCE_L9:INV.CE
    20------------------------------
    21------------------------------
    22---------------------------BUFHCE_L8:CE_TYPE-BUFHCE_L9:CE_TYPE
    23---------------------------BUFHCE_L8:ENABLE-BUFHCE_L9:ENABLE
    24--------------------------BUFHCE_L8:MUX.I[4]BUFHCE_L8:MUX.I[5]BUFHCE_L9:MUX.I[4]BUFHCE_L9:MUX.I[5]
    25--------------------------BUFHCE_L8:MUX.I[6]BUFHCE_L8:MUX.I[7]BUFHCE_L9:MUX.I[6]BUFHCE_L9:MUX.I[7]
    26--------------------------BUFHCE_L8:MUX.I[3]BUFHCE_L8:MUX.I[2]BUFHCE_L9:MUX.I[3]BUFHCE_L9:MUX.I[2]
    27--------------------------BUFHCE_L8:MUX.I[1]BUFHCE_L8:MUX.I[0]BUFHCE_L9:MUX.I[1]BUFHCE_L9:MUX.I[0]
    28--------------------------BUFHCE_L8:MUX.I[8]BUFHCE_L8:MUX.I[9]BUFHCE_L9:MUX.I[8]BUFHCE_L9:MUX.I[9]
    29--------------------------BUFHCE_L8:MUX.I[10]BUFHCE_L8:MUX.I[11]BUFHCE_L9:MUX.I[10]BUFHCE_L9:MUX.I[11]
    30--------------------------BUFHCE_L8:MUX.I[12]BUFHCE_L8:MUX.I[13]BUFHCE_L9:MUX.I[12]BUFHCE_L9:MUX.I[13]
    31--------------------------BUFHCE_L8:MUX.I[14]BUFHCE_L8:MUX.I[15]BUFHCE_L9:MUX.I[14]BUFHCE_L9:MUX.I[15]
    32------------------------------
    33------------------------------
    34------------------------------
    35--------------------------BUFHCE_L10:INIT_OUT~BUFHCE_L10:INV.CEBUFHCE_L11:INIT_OUT~BUFHCE_L11:INV.CE
    36------------------------------
    37------------------------------
    38---------------------------BUFHCE_L10:CE_TYPE-BUFHCE_L11:CE_TYPE
    39---------------------------BUFHCE_L10:ENABLE-BUFHCE_L11:ENABLE
    40--------------------------BUFHCE_L10:MUX.I[4]BUFHCE_L10:MUX.I[5]BUFHCE_L11:MUX.I[4]BUFHCE_L11:MUX.I[5]
    41--------------------------BUFHCE_L10:MUX.I[6]BUFHCE_L10:MUX.I[7]BUFHCE_L11:MUX.I[6]BUFHCE_L11:MUX.I[7]
    42--------------------------BUFHCE_L10:MUX.I[3]BUFHCE_L10:MUX.I[2]BUFHCE_L11:MUX.I[3]BUFHCE_L11:MUX.I[2]
    43--------------------------BUFHCE_L10:MUX.I[1]BUFHCE_L10:MUX.I[0]BUFHCE_L11:MUX.I[1]BUFHCE_L11:MUX.I[0]
    44--------------------------BUFHCE_L10:MUX.I[8]BUFHCE_L10:MUX.I[9]BUFHCE_L11:MUX.I[8]BUFHCE_L11:MUX.I[9]
    45--------------------------BUFHCE_L10:MUX.I[10]BUFHCE_L10:MUX.I[11]BUFHCE_L11:MUX.I[10]BUFHCE_L11:MUX.I[11]
    46--------------------------BUFHCE_L10:MUX.I[12]BUFHCE_L10:MUX.I[13]BUFHCE_L11:MUX.I[12]BUFHCE_L11:MUX.I[13]
    47--------------------------BUFHCE_L10:MUX.I[14]BUFHCE_L10:MUX.I[15]BUFHCE_L11:MUX.I[14]BUFHCE_L11:MUX.I[15]
    48------------------------------
    49------------------------------
    50------------------------------
    51--------------------------BUFHCE_R6:INIT_OUT~BUFHCE_R6:INV.CEBUFHCE_R7:INIT_OUT~BUFHCE_R7:INV.CE
    52------------------------------
    53------------------------------
    54---------------------------BUFHCE_R6:CE_TYPE-BUFHCE_R7:CE_TYPE
    55---------------------------BUFHCE_R6:ENABLE-BUFHCE_R7:ENABLE
    56--------------------------BUFHCE_R6:MUX.I[4]BUFHCE_R6:MUX.I[5]BUFHCE_R7:MUX.I[4]BUFHCE_R7:MUX.I[5]
    57--------------------------BUFHCE_R6:MUX.I[6]BUFHCE_R6:MUX.I[7]BUFHCE_R7:MUX.I[6]BUFHCE_R7:MUX.I[7]
    58--------------------------BUFHCE_R6:MUX.I[3]BUFHCE_R6:MUX.I[2]BUFHCE_R7:MUX.I[3]BUFHCE_R7:MUX.I[2]
    59--------------------------BUFHCE_R6:MUX.I[1]BUFHCE_R6:MUX.I[0]BUFHCE_R7:MUX.I[1]BUFHCE_R7:MUX.I[0]
    60--------------------------BUFHCE_R6:MUX.I[8]BUFHCE_R6:MUX.I[9]BUFHCE_R7:MUX.I[8]BUFHCE_R7:MUX.I[9]
    61--------------------------BUFHCE_R6:MUX.I[10]BUFHCE_R6:MUX.I[11]BUFHCE_R7:MUX.I[10]BUFHCE_R7:MUX.I[11]
    62--------------------------BUFHCE_R6:MUX.I[12]BUFHCE_R6:MUX.I[13]BUFHCE_R7:MUX.I[12]BUFHCE_R7:MUX.I[13]
    63--------------------------BUFHCE_R6:MUX.I[14]BUFHCE_R6:MUX.I[15]BUFHCE_R7:MUX.I[14]BUFHCE_R7:MUX.I[15]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 5
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3--------------------------BUFHCE_R8:INIT_OUT~BUFHCE_R8:INV.CEBUFHCE_R9:INIT_OUT~BUFHCE_R9:INV.CE
    4------------------------------
    5------------------------------
    6---------------------------BUFHCE_R8:CE_TYPE-BUFHCE_R9:CE_TYPE
    7---------------------------BUFHCE_R8:ENABLE-BUFHCE_R9:ENABLE
    8--------------------------BUFHCE_R8:MUX.I[4]BUFHCE_R8:MUX.I[5]BUFHCE_R9:MUX.I[4]BUFHCE_R9:MUX.I[5]
    9--------------------------BUFHCE_R8:MUX.I[6]BUFHCE_R8:MUX.I[7]BUFHCE_R9:MUX.I[6]BUFHCE_R9:MUX.I[7]
    10--------------------------BUFHCE_R8:MUX.I[3]BUFHCE_R8:MUX.I[2]BUFHCE_R9:MUX.I[3]BUFHCE_R9:MUX.I[2]
    11--------------------------BUFHCE_R8:MUX.I[1]BUFHCE_R8:MUX.I[0]BUFHCE_R9:MUX.I[1]BUFHCE_R9:MUX.I[0]
    12--------------------------BUFHCE_R8:MUX.I[8]BUFHCE_R8:MUX.I[9]BUFHCE_R9:MUX.I[8]BUFHCE_R9:MUX.I[9]
    13--------------------------BUFHCE_R8:MUX.I[10]BUFHCE_R8:MUX.I[11]BUFHCE_R9:MUX.I[10]BUFHCE_R9:MUX.I[11]
    14--------------------------BUFHCE_R8:MUX.I[12]BUFHCE_R8:MUX.I[13]BUFHCE_R9:MUX.I[12]BUFHCE_R9:MUX.I[13]
    15--------------------------BUFHCE_R8:MUX.I[14]BUFHCE_R8:MUX.I[15]BUFHCE_R9:MUX.I[14]BUFHCE_R9:MUX.I[15]
    16------------------------------
    17------------------------------
    18------------------------------
    19--------------------------BUFHCE_R10:INIT_OUT~BUFHCE_R10:INV.CEBUFHCE_R11:INIT_OUT~BUFHCE_R11:INV.CE
    20------------------------------
    21------------------------------
    22---------------------------BUFHCE_R10:CE_TYPE-BUFHCE_R11:CE_TYPE
    23---------------------------BUFHCE_R10:ENABLE-BUFHCE_R11:ENABLE
    24--------------------------BUFHCE_R10:MUX.I[4]BUFHCE_R10:MUX.I[5]BUFHCE_R11:MUX.I[4]BUFHCE_R11:MUX.I[5]
    25--------------------------BUFHCE_R10:MUX.I[6]BUFHCE_R10:MUX.I[7]BUFHCE_R11:MUX.I[6]BUFHCE_R11:MUX.I[7]
    26--------------------------BUFHCE_R10:MUX.I[3]BUFHCE_R10:MUX.I[2]BUFHCE_R11:MUX.I[3]BUFHCE_R11:MUX.I[2]
    27--------------------------BUFHCE_R10:MUX.I[1]BUFHCE_R10:MUX.I[0]BUFHCE_R11:MUX.I[1]BUFHCE_R11:MUX.I[0]
    28--------------------------BUFHCE_R10:MUX.I[8]BUFHCE_R10:MUX.I[9]BUFHCE_R11:MUX.I[8]BUFHCE_R11:MUX.I[9]
    29--------------------------BUFHCE_R10:MUX.I[10]BUFHCE_R10:MUX.I[11]BUFHCE_R11:MUX.I[10]BUFHCE_R11:MUX.I[11]
    30--------------------------BUFHCE_R10:MUX.I[12]BUFHCE_R10:MUX.I[13]BUFHCE_R11:MUX.I[12]BUFHCE_R11:MUX.I[13]
    31--------------------------BUFHCE_R10:MUX.I[14]BUFHCE_R10:MUX.I[15]BUFHCE_R11:MUX.I[14]BUFHCE_R11:MUX.I[15]
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36------------------------------
    37------------------------------
    38------------------------------
    39------------------------------
    40------------------------------
    41------------------------------
    42------------------------------
    43------------------------------
    44------------------------------
    45------------------------------
    46------------------------------
    47------------------------------
    48------------------------------
    49------------------------------
    50------------------------------
    51------------------------------
    52--------------------------CLK_HROW:MUX.CASCO16[0]CLK_HROW:ENABLE.GCLK_TEST16CLK_HROW:MUX.CASCO17[0]CLK_HROW:ENABLE.GCLK_TEST17
    53--------------------------CLK_HROW:INV.GCLK_TEST16-CLK_HROW:INV.GCLK_TEST17-
    54------------------------------
    55------------------------------
    56--------------------------CLK_HROW:MUX.CASCO16[2]CLK_HROW:MUX.CASCO16[1]CLK_HROW:MUX.CASCO17[2]CLK_HROW:MUX.CASCO17[1]
    57--------------------------CLK_HROW:MUX.CASCO16[4]CLK_HROW:MUX.CASCO16[5]CLK_HROW:MUX.CASCO17[4]CLK_HROW:MUX.CASCO17[5]
    58--------------------------CLK_HROW:MUX.CASCO16[3]-CLK_HROW:MUX.CASCO17[3]-
    59------------------------------
    60--------------------------CLK_HROW:MUX.CASCO16[8]CLK_HROW:MUX.CASCO16[9]CLK_HROW:MUX.CASCO17[8]CLK_HROW:MUX.CASCO17[9]
    61--------------------------CLK_HROW:MUX.CASCO16[10]CLK_HROW:MUX.CASCO16[11]CLK_HROW:MUX.CASCO17[10]CLK_HROW:MUX.CASCO17[11]
    62--------------------------CLK_HROW:MUX.CASCO16[12]CLK_HROW:MUX.CASCO16[13]CLK_HROW:MUX.CASCO17[12]CLK_HROW:MUX.CASCO17[13]
    63--------------------------CLK_HROW:MUX.CASCO16[6]CLK_HROW:MUX.CASCO16[7]CLK_HROW:MUX.CASCO17[6]CLK_HROW:MUX.CASCO17[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 6
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4--------------------------CLK_HROW:MUX.CASCO18[0]CLK_HROW:ENABLE.GCLK_TEST18CLK_HROW:MUX.CASCO19[0]CLK_HROW:ENABLE.GCLK_TEST19
    5--------------------------CLK_HROW:INV.GCLK_TEST18-CLK_HROW:INV.GCLK_TEST19-
    6------------------------------
    7------------------------------
    8--------------------------CLK_HROW:MUX.CASCO18[2]CLK_HROW:MUX.CASCO18[1]CLK_HROW:MUX.CASCO19[2]CLK_HROW:MUX.CASCO19[1]
    9--------------------------CLK_HROW:MUX.CASCO18[4]CLK_HROW:MUX.CASCO18[5]CLK_HROW:MUX.CASCO19[4]CLK_HROW:MUX.CASCO19[5]
    10--------------------------CLK_HROW:MUX.CASCO18[3]-CLK_HROW:MUX.CASCO19[3]-
    11------------------------------
    12--------------------------CLK_HROW:MUX.CASCO18[8]CLK_HROW:MUX.CASCO18[9]CLK_HROW:MUX.CASCO19[8]CLK_HROW:MUX.CASCO19[9]
    13--------------------------CLK_HROW:MUX.CASCO18[10]CLK_HROW:MUX.CASCO18[11]CLK_HROW:MUX.CASCO19[10]CLK_HROW:MUX.CASCO19[11]
    14--------------------------CLK_HROW:MUX.CASCO18[12]CLK_HROW:MUX.CASCO18[13]CLK_HROW:MUX.CASCO19[12]CLK_HROW:MUX.CASCO19[13]
    15--------------------------CLK_HROW:MUX.CASCO18[6]CLK_HROW:MUX.CASCO18[7]CLK_HROW:MUX.CASCO19[6]CLK_HROW:MUX.CASCO19[7]
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20--------------------------CLK_HROW:MUX.CASCO20[0]CLK_HROW:ENABLE.GCLK_TEST20CLK_HROW:MUX.CASCO21[0]CLK_HROW:ENABLE.GCLK_TEST21
    21--------------------------CLK_HROW:INV.GCLK_TEST20-CLK_HROW:INV.GCLK_TEST21-
    22------------------------------
    23------------------------------
    24--------------------------CLK_HROW:MUX.CASCO20[2]CLK_HROW:MUX.CASCO20[1]CLK_HROW:MUX.CASCO21[2]CLK_HROW:MUX.CASCO21[1]
    25--------------------------CLK_HROW:MUX.CASCO20[4]CLK_HROW:MUX.CASCO20[5]CLK_HROW:MUX.CASCO21[4]CLK_HROW:MUX.CASCO21[5]
    26--------------------------CLK_HROW:MUX.CASCO20[3]-CLK_HROW:MUX.CASCO21[3]-
    27------------------------------
    28--------------------------CLK_HROW:MUX.CASCO20[8]CLK_HROW:MUX.CASCO20[9]CLK_HROW:MUX.CASCO21[8]CLK_HROW:MUX.CASCO21[9]
    29--------------------------CLK_HROW:MUX.CASCO20[10]CLK_HROW:MUX.CASCO20[11]CLK_HROW:MUX.CASCO21[10]CLK_HROW:MUX.CASCO21[11]
    30--------------------------CLK_HROW:MUX.CASCO20[12]CLK_HROW:MUX.CASCO20[13]CLK_HROW:MUX.CASCO21[12]CLK_HROW:MUX.CASCO21[13]
    31--------------------------CLK_HROW:MUX.CASCO20[6]CLK_HROW:MUX.CASCO20[7]CLK_HROW:MUX.CASCO21[6]CLK_HROW:MUX.CASCO21[7]
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36--------------------------CLK_HROW:MUX.CASCO22[0]CLK_HROW:ENABLE.GCLK_TEST22CLK_HROW:MUX.CASCO23[0]CLK_HROW:ENABLE.GCLK_TEST23
    37--------------------------CLK_HROW:INV.GCLK_TEST22-CLK_HROW:INV.GCLK_TEST23-
    38------------------------------
    39------------------------------
    40--------------------------CLK_HROW:MUX.CASCO22[2]CLK_HROW:MUX.CASCO22[1]CLK_HROW:MUX.CASCO23[2]CLK_HROW:MUX.CASCO23[1]
    41--------------------------CLK_HROW:MUX.CASCO22[4]CLK_HROW:MUX.CASCO22[5]CLK_HROW:MUX.CASCO23[4]CLK_HROW:MUX.CASCO23[5]
    42--------------------------CLK_HROW:MUX.CASCO22[3]-CLK_HROW:MUX.CASCO23[3]-
    43------------------------------
    44--------------------------CLK_HROW:MUX.CASCO22[8]CLK_HROW:MUX.CASCO22[9]CLK_HROW:MUX.CASCO23[8]CLK_HROW:MUX.CASCO23[9]
    45--------------------------CLK_HROW:MUX.CASCO22[10]CLK_HROW:MUX.CASCO22[11]CLK_HROW:MUX.CASCO23[10]CLK_HROW:MUX.CASCO23[11]
    46--------------------------CLK_HROW:MUX.CASCO22[12]CLK_HROW:MUX.CASCO22[13]CLK_HROW:MUX.CASCO23[12]CLK_HROW:MUX.CASCO23[13]
    47--------------------------CLK_HROW:MUX.CASCO22[6]CLK_HROW:MUX.CASCO22[7]CLK_HROW:MUX.CASCO23[6]CLK_HROW:MUX.CASCO23[7]
    48------------------------------
    49------------------------------
    50------------------------------
    51------------------------------
    52--------------------------CLK_HROW:MUX.CASCO24[0]CLK_HROW:ENABLE.GCLK_TEST24CLK_HROW:MUX.CASCO25[0]CLK_HROW:ENABLE.GCLK_TEST25
    53--------------------------CLK_HROW:INV.GCLK_TEST24-CLK_HROW:INV.GCLK_TEST25-
    54------------------------------
    55------------------------------
    56--------------------------CLK_HROW:MUX.CASCO24[2]CLK_HROW:MUX.CASCO24[1]CLK_HROW:MUX.CASCO25[2]CLK_HROW:MUX.CASCO25[1]
    57--------------------------CLK_HROW:MUX.CASCO24[4]CLK_HROW:MUX.CASCO24[5]CLK_HROW:MUX.CASCO25[4]CLK_HROW:MUX.CASCO25[5]
    58--------------------------CLK_HROW:MUX.CASCO24[3]-CLK_HROW:MUX.CASCO25[3]-
    59------------------------------
    60--------------------------CLK_HROW:MUX.CASCO24[8]CLK_HROW:MUX.CASCO24[9]CLK_HROW:MUX.CASCO25[8]CLK_HROW:MUX.CASCO25[9]
    61--------------------------CLK_HROW:MUX.CASCO24[10]CLK_HROW:MUX.CASCO24[11]CLK_HROW:MUX.CASCO25[10]CLK_HROW:MUX.CASCO25[11]
    62--------------------------CLK_HROW:MUX.CASCO24[12]CLK_HROW:MUX.CASCO24[13]CLK_HROW:MUX.CASCO25[12]CLK_HROW:MUX.CASCO25[13]
    63--------------------------CLK_HROW:MUX.CASCO24[6]CLK_HROW:MUX.CASCO24[7]CLK_HROW:MUX.CASCO25[6]CLK_HROW:MUX.CASCO25[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 7
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4--------------------------CLK_HROW:MUX.CASCO26[0]CLK_HROW:ENABLE.GCLK_TEST26CLK_HROW:MUX.CASCO27[0]CLK_HROW:ENABLE.GCLK_TEST27
    5--------------------------CLK_HROW:INV.GCLK_TEST26-CLK_HROW:INV.GCLK_TEST27-
    6------------------------------
    7------------------------------
    8--------------------------CLK_HROW:MUX.CASCO26[2]CLK_HROW:MUX.CASCO26[1]CLK_HROW:MUX.CASCO27[2]CLK_HROW:MUX.CASCO27[1]
    9--------------------------CLK_HROW:MUX.CASCO26[4]CLK_HROW:MUX.CASCO26[5]CLK_HROW:MUX.CASCO27[4]CLK_HROW:MUX.CASCO27[5]
    10--------------------------CLK_HROW:MUX.CASCO26[3]-CLK_HROW:MUX.CASCO27[3]-
    11------------------------------
    12--------------------------CLK_HROW:MUX.CASCO26[8]CLK_HROW:MUX.CASCO26[9]CLK_HROW:MUX.CASCO27[8]CLK_HROW:MUX.CASCO27[9]
    13--------------------------CLK_HROW:MUX.CASCO26[10]CLK_HROW:MUX.CASCO26[11]CLK_HROW:MUX.CASCO27[10]CLK_HROW:MUX.CASCO27[11]
    14--------------------------CLK_HROW:MUX.CASCO26[12]CLK_HROW:MUX.CASCO26[13]CLK_HROW:MUX.CASCO27[12]CLK_HROW:MUX.CASCO27[13]
    15--------------------------CLK_HROW:MUX.CASCO26[6]CLK_HROW:MUX.CASCO26[7]CLK_HROW:MUX.CASCO27[6]CLK_HROW:MUX.CASCO27[7]
    16------------------------------
    17------------------------------
    18------------------------------
    19------------------------------
    20--------------------------CLK_HROW:MUX.CASCO28[0]CLK_HROW:ENABLE.GCLK_TEST28CLK_HROW:MUX.CASCO29[0]CLK_HROW:ENABLE.GCLK_TEST29
    21--------------------------CLK_HROW:INV.GCLK_TEST28-CLK_HROW:INV.GCLK_TEST29-
    22------------------------------
    23------------------------------
    24--------------------------CLK_HROW:MUX.CASCO28[2]CLK_HROW:MUX.CASCO28[1]CLK_HROW:MUX.CASCO29[2]CLK_HROW:MUX.CASCO29[1]
    25--------------------------CLK_HROW:MUX.CASCO28[4]CLK_HROW:MUX.CASCO28[5]CLK_HROW:MUX.CASCO29[4]CLK_HROW:MUX.CASCO29[5]
    26--------------------------CLK_HROW:MUX.CASCO28[3]-CLK_HROW:MUX.CASCO29[3]-
    27------------------------------
    28--------------------------CLK_HROW:MUX.CASCO28[8]CLK_HROW:MUX.CASCO28[9]CLK_HROW:MUX.CASCO29[8]CLK_HROW:MUX.CASCO29[9]
    29--------------------------CLK_HROW:MUX.CASCO28[10]CLK_HROW:MUX.CASCO28[11]CLK_HROW:MUX.CASCO29[10]CLK_HROW:MUX.CASCO29[11]
    30--------------------------CLK_HROW:MUX.CASCO28[12]CLK_HROW:MUX.CASCO28[13]CLK_HROW:MUX.CASCO29[12]CLK_HROW:MUX.CASCO29[13]
    31--------------------------CLK_HROW:MUX.CASCO28[6]CLK_HROW:MUX.CASCO28[7]CLK_HROW:MUX.CASCO29[6]CLK_HROW:MUX.CASCO29[7]
    32------------------------------
    33------------------------------
    34------------------------------
    35------------------------------
    36--------------------------CLK_HROW:MUX.CASCO30[0]CLK_HROW:ENABLE.GCLK_TEST30CLK_HROW:MUX.CASCO31[0]CLK_HROW:ENABLE.GCLK_TEST31
    37--------------------------CLK_HROW:INV.GCLK_TEST30-CLK_HROW:INV.GCLK_TEST31-
    38------------------------------
    39------------------------------
    40--------------------------CLK_HROW:MUX.CASCO30[2]CLK_HROW:MUX.CASCO30[1]CLK_HROW:MUX.CASCO31[2]CLK_HROW:MUX.CASCO31[1]
    41--------------------------CLK_HROW:MUX.CASCO30[4]CLK_HROW:MUX.CASCO30[5]CLK_HROW:MUX.CASCO31[4]CLK_HROW:MUX.CASCO31[5]
    42--------------------------CLK_HROW:MUX.CASCO30[3]-CLK_HROW:MUX.CASCO31[3]-
    43------------------------------
    44--------------------------CLK_HROW:MUX.CASCO30[8]CLK_HROW:MUX.CASCO30[9]CLK_HROW:MUX.CASCO31[8]CLK_HROW:MUX.CASCO31[9]
    45--------------------------CLK_HROW:MUX.CASCO30[10]CLK_HROW:MUX.CASCO30[11]CLK_HROW:MUX.CASCO31[10]CLK_HROW:MUX.CASCO31[11]
    46--------------------------CLK_HROW:MUX.CASCO30[12]CLK_HROW:MUX.CASCO30[13]CLK_HROW:MUX.CASCO31[12]CLK_HROW:MUX.CASCO31[13]
    47--------------------------CLK_HROW:MUX.CASCO30[6]CLK_HROW:MUX.CASCO30[7]CLK_HROW:MUX.CASCO31[6]CLK_HROW:MUX.CASCO31[7]
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW bittile 8
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14--------------------------CLK_HROW:ENABLE.RCLK0_LCLK_HROW:ENABLE.RCLK1_LCLK_HROW:ENABLE.RCLK0_RCLK_HROW:ENABLE.RCLK1_R
    15--------------------------CLK_HROW:ENABLE.RCLK2_LCLK_HROW:ENABLE.RCLK3_LCLK_HROW:ENABLE.RCLK2_RCLK_HROW:ENABLE.RCLK3_R
    16--------------------------CLK_HROW:MUX.HCLK_TEST_L[0]CLK_HROW:MUX.HCLK_TEST_L[1]CLK_HROW:MUX.HCLK_TEST_R[0]CLK_HROW:MUX.HCLK_TEST_R[1]
    17--------------------------CLK_HROW:MUX.HCLK_TEST_L[2]CLK_HROW:MUX.HCLK_TEST_L[3]CLK_HROW:MUX.HCLK_TEST_R[2]CLK_HROW:MUX.HCLK_TEST_R[3]
    18--------------------------CLK_HROW:ENABLE.HIN0_LCLK_HROW:ENABLE.HIN1_LCLK_HROW:ENABLE.HIN0_RCLK_HROW:ENABLE.HIN1_R
    19--------------------------CLK_HROW:ENABLE.HIN2_LCLK_HROW:ENABLE.HIN3_LCLK_HROW:ENABLE.HIN2_RCLK_HROW:ENABLE.HIN3_R
    20--------------------------CLK_HROW:ENABLE.HIN4_LCLK_HROW:ENABLE.HIN5_LCLK_HROW:ENABLE.HIN4_RCLK_HROW:ENABLE.HIN5_R
    21--------------------------CLK_HROW:ENABLE.HIN6_LCLK_HROW:ENABLE.HIN7_LCLK_HROW:ENABLE.HIN6_RCLK_HROW:ENABLE.HIN7_R
    22--------------------------CLK_HROW:ENABLE.HIN8_LCLK_HROW:ENABLE.HIN9_LCLK_HROW:ENABLE.HIN8_RCLK_HROW:ENABLE.HIN9_R
    23--------------------------CLK_HROW:ENABLE.GCLK16CLK_HROW:ENABLE.GCLK17CLK_HROW:ENABLE.GCLK0CLK_HROW:ENABLE.GCLK1
    24--------------------------CLK_HROW:ENABLE.GCLK18CLK_HROW:ENABLE.GCLK19CLK_HROW:ENABLE.GCLK2CLK_HROW:ENABLE.GCLK3
    25--------------------------CLK_HROW:ENABLE.GCLK20CLK_HROW:ENABLE.GCLK21CLK_HROW:ENABLE.GCLK4CLK_HROW:ENABLE.GCLK5
    26--------------------------CLK_HROW:ENABLE.GCLK22CLK_HROW:ENABLE.GCLK23CLK_HROW:ENABLE.GCLK6CLK_HROW:ENABLE.GCLK7
    27--------------------------CLK_HROW:ENABLE.GCLK24CLK_HROW:ENABLE.GCLK25CLK_HROW:ENABLE.GCLK8CLK_HROW:ENABLE.GCLK9
    28--------------------------CLK_HROW:ENABLE.GCLK26CLK_HROW:ENABLE.GCLK27CLK_HROW:ENABLE.GCLK10CLK_HROW:ENABLE.GCLK11
    29--------------------------CLK_HROW:ENABLE.GCLK28CLK_HROW:ENABLE.GCLK29CLK_HROW:ENABLE.GCLK12CLK_HROW:ENABLE.GCLK13
    30--------------------------CLK_HROW:ENABLE.GCLK30CLK_HROW:ENABLE.GCLK31CLK_HROW:ENABLE.GCLK14CLK_HROW:ENABLE.GCLK15
    31--------------------------CLK_HROW:ENABLE.CKINT0CLK_HROW:ENABLE.CKINT1CLK_HROW:ENABLE.CKINT2CLK_HROW:ENABLE.CKINT3
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO0[0, 27, 30][0, 26, 30][0, 27, 29][0, 26, 29][0, 27, 28][0, 26, 28][0, 27, 31][0, 26, 31][0, 27, 25][0, 26, 25][0, 26, 26][0, 26, 24][0, 27, 24][0, 26, 20]
    CLK_HROW:MUX.CASCO1[0, 29, 30][0, 28, 30][0, 29, 29][0, 28, 29][0, 29, 28][0, 28, 28][0, 29, 31][0, 28, 31][0, 29, 25][0, 28, 25][0, 28, 26][0, 28, 24][0, 29, 24][0, 28, 20]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST000000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST100000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
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    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:ENABLE[3, 27, 23]
    BUFHCE_L0:INIT_OUT[3, 26, 19]
    BUFHCE_L10:ENABLE[4, 27, 39]
    BUFHCE_L10:INIT_OUT[4, 26, 35]
    BUFHCE_L11:ENABLE[4, 29, 39]
    BUFHCE_L11:INIT_OUT[4, 28, 35]
    BUFHCE_L1:ENABLE[3, 29, 23]
    BUFHCE_L1:INIT_OUT[3, 28, 19]
    BUFHCE_L2:ENABLE[3, 27, 39]
    BUFHCE_L2:INIT_OUT[3, 26, 35]
    BUFHCE_L3:ENABLE[3, 29, 39]
    BUFHCE_L3:INIT_OUT[3, 28, 35]
    BUFHCE_L4:ENABLE[3, 27, 55]
    BUFHCE_L4:INIT_OUT[3, 26, 51]
    BUFHCE_L5:ENABLE[3, 29, 55]
    BUFHCE_L5:INIT_OUT[3, 28, 51]
    BUFHCE_L6:ENABLE[4, 27, 7]
    BUFHCE_L6:INIT_OUT[4, 26, 3]
    BUFHCE_L7:ENABLE[4, 29, 7]
    BUFHCE_L7:INIT_OUT[4, 28, 3]
    BUFHCE_L8:ENABLE[4, 27, 23]
    BUFHCE_L8:INIT_OUT[4, 26, 19]
    BUFHCE_L9:ENABLE[4, 29, 23]
    BUFHCE_L9:INIT_OUT[4, 28, 19]
    BUFHCE_R0:ENABLE[2, 27, 39]
    BUFHCE_R0:INIT_OUT[2, 26, 35]
    BUFHCE_R10:ENABLE[5, 27, 23]
    BUFHCE_R10:INIT_OUT[5, 26, 19]
    BUFHCE_R11:ENABLE[5, 29, 23]
    BUFHCE_R11:INIT_OUT[5, 28, 19]
    BUFHCE_R1:ENABLE[2, 29, 39]
    BUFHCE_R1:INIT_OUT[2, 28, 35]
    BUFHCE_R2:ENABLE[2, 27, 55]
    BUFHCE_R2:INIT_OUT[2, 26, 51]
    BUFHCE_R3:ENABLE[2, 29, 55]
    BUFHCE_R3:INIT_OUT[2, 28, 51]
    BUFHCE_R4:ENABLE[3, 27, 7]
    BUFHCE_R4:INIT_OUT[3, 26, 3]
    BUFHCE_R5:ENABLE[3, 29, 7]
    BUFHCE_R5:INIT_OUT[3, 28, 3]
    BUFHCE_R6:ENABLE[4, 27, 55]
    BUFHCE_R6:INIT_OUT[4, 26, 51]
    BUFHCE_R7:ENABLE[4, 29, 55]
    BUFHCE_R7:INIT_OUT[4, 28, 51]
    BUFHCE_R8:ENABLE[5, 27, 7]
    BUFHCE_R8:INIT_OUT[5, 26, 3]
    BUFHCE_R9:ENABLE[5, 29, 7]
    BUFHCE_R9:INIT_OUT[5, 28, 3]
    CLK_HROW:ENABLE.CKINT0[8, 26, 31]
    CLK_HROW:ENABLE.CKINT1[8, 27, 31]
    CLK_HROW:ENABLE.CKINT2[8, 28, 31]
    CLK_HROW:ENABLE.CKINT3[8, 29, 31]
    CLK_HROW:ENABLE.GCLK0[8, 28, 23]
    CLK_HROW:ENABLE.GCLK1[8, 29, 23]
    CLK_HROW:ENABLE.GCLK10[8, 28, 28]
    CLK_HROW:ENABLE.GCLK11[8, 29, 28]
    CLK_HROW:ENABLE.GCLK12[8, 28, 29]
    CLK_HROW:ENABLE.GCLK13[8, 29, 29]
    CLK_HROW:ENABLE.GCLK14[8, 28, 30]
    CLK_HROW:ENABLE.GCLK15[8, 29, 30]
    CLK_HROW:ENABLE.GCLK16[8, 26, 23]
    CLK_HROW:ENABLE.GCLK17[8, 27, 23]
    CLK_HROW:ENABLE.GCLK18[8, 26, 24]
    CLK_HROW:ENABLE.GCLK19[8, 27, 24]
    CLK_HROW:ENABLE.GCLK2[8, 28, 24]
    CLK_HROW:ENABLE.GCLK20[8, 26, 25]
    CLK_HROW:ENABLE.GCLK21[8, 27, 25]
    CLK_HROW:ENABLE.GCLK22[8, 26, 26]
    CLK_HROW:ENABLE.GCLK23[8, 27, 26]
    CLK_HROW:ENABLE.GCLK24[8, 26, 27]
    CLK_HROW:ENABLE.GCLK25[8, 27, 27]
    CLK_HROW:ENABLE.GCLK26[8, 26, 28]
    CLK_HROW:ENABLE.GCLK27[8, 27, 28]
    CLK_HROW:ENABLE.GCLK28[8, 26, 29]
    CLK_HROW:ENABLE.GCLK29[8, 27, 29]
    CLK_HROW:ENABLE.GCLK3[8, 29, 24]
    CLK_HROW:ENABLE.GCLK30[8, 26, 30]
    CLK_HROW:ENABLE.GCLK31[8, 27, 30]
    CLK_HROW:ENABLE.GCLK4[8, 28, 25]
    CLK_HROW:ENABLE.GCLK5[8, 29, 25]
    CLK_HROW:ENABLE.GCLK6[8, 28, 26]
    CLK_HROW:ENABLE.GCLK7[8, 29, 26]
    CLK_HROW:ENABLE.GCLK8[8, 28, 27]
    CLK_HROW:ENABLE.GCLK9[8, 29, 27]
    CLK_HROW:ENABLE.GCLK_TEST0[0, 27, 20]
    CLK_HROW:ENABLE.GCLK_TEST1[0, 29, 20]
    CLK_HROW:ENABLE.GCLK_TEST10[1, 27, 36]
    CLK_HROW:ENABLE.GCLK_TEST11[1, 29, 36]
    CLK_HROW:ENABLE.GCLK_TEST12[1, 27, 52]
    CLK_HROW:ENABLE.GCLK_TEST13[1, 29, 52]
    CLK_HROW:ENABLE.GCLK_TEST14[2, 27, 4]
    CLK_HROW:ENABLE.GCLK_TEST15[2, 29, 4]
    CLK_HROW:ENABLE.GCLK_TEST16[5, 27, 52]
    CLK_HROW:ENABLE.GCLK_TEST17[5, 29, 52]
    CLK_HROW:ENABLE.GCLK_TEST18[6, 27, 4]
    CLK_HROW:ENABLE.GCLK_TEST19[6, 29, 4]
    CLK_HROW:ENABLE.GCLK_TEST2[0, 27, 36]
    CLK_HROW:ENABLE.GCLK_TEST20[6, 27, 20]
    CLK_HROW:ENABLE.GCLK_TEST21[6, 29, 20]
    CLK_HROW:ENABLE.GCLK_TEST22[6, 27, 36]
    CLK_HROW:ENABLE.GCLK_TEST23[6, 29, 36]
    CLK_HROW:ENABLE.GCLK_TEST24[6, 27, 52]
    CLK_HROW:ENABLE.GCLK_TEST25[6, 29, 52]
    CLK_HROW:ENABLE.GCLK_TEST26[7, 27, 4]
    CLK_HROW:ENABLE.GCLK_TEST27[7, 29, 4]
    CLK_HROW:ENABLE.GCLK_TEST28[7, 27, 20]
    CLK_HROW:ENABLE.GCLK_TEST29[7, 29, 20]
    CLK_HROW:ENABLE.GCLK_TEST3[0, 29, 36]
    CLK_HROW:ENABLE.GCLK_TEST30[7, 27, 36]
    CLK_HROW:ENABLE.GCLK_TEST31[7, 29, 36]
    CLK_HROW:ENABLE.GCLK_TEST4[0, 27, 52]
    CLK_HROW:ENABLE.GCLK_TEST5[0, 29, 52]
    CLK_HROW:ENABLE.GCLK_TEST6[1, 27, 4]
    CLK_HROW:ENABLE.GCLK_TEST7[1, 29, 4]
    CLK_HROW:ENABLE.GCLK_TEST8[1, 27, 20]
    CLK_HROW:ENABLE.GCLK_TEST9[1, 29, 20]
    CLK_HROW:ENABLE.HIN0_L[8, 26, 18]
    CLK_HROW:ENABLE.HIN0_R[8, 28, 18]
    CLK_HROW:ENABLE.HIN10_L[3, 26, 48]
    CLK_HROW:ENABLE.HIN10_R[3, 28, 48]
    CLK_HROW:ENABLE.HIN11_L[3, 27, 48]
    CLK_HROW:ENABLE.HIN11_R[3, 29, 48]
    CLK_HROW:ENABLE.HIN12_L[3, 26, 49]
    CLK_HROW:ENABLE.HIN12_R[3, 28, 49]
    CLK_HROW:ENABLE.HIN13_L[3, 27, 49]
    CLK_HROW:ENABLE.HIN13_R[3, 29, 49]
    CLK_HROW:ENABLE.HIN1_L[8, 27, 18]
    CLK_HROW:ENABLE.HIN1_R[8, 29, 18]
    CLK_HROW:ENABLE.HIN2_L[8, 26, 19]
    CLK_HROW:ENABLE.HIN2_R[8, 28, 19]
    CLK_HROW:ENABLE.HIN3_L[8, 27, 19]
    CLK_HROW:ENABLE.HIN3_R[8, 29, 19]
    CLK_HROW:ENABLE.HIN4_L[8, 26, 20]
    CLK_HROW:ENABLE.HIN4_R[8, 28, 20]
    CLK_HROW:ENABLE.HIN5_L[8, 27, 20]
    CLK_HROW:ENABLE.HIN5_R[8, 29, 20]
    CLK_HROW:ENABLE.HIN6_L[8, 26, 21]
    CLK_HROW:ENABLE.HIN6_R[8, 28, 21]
    CLK_HROW:ENABLE.HIN7_L[8, 27, 21]
    CLK_HROW:ENABLE.HIN7_R[8, 29, 21]
    CLK_HROW:ENABLE.HIN8_L[8, 26, 22]
    CLK_HROW:ENABLE.HIN8_R[8, 28, 22]
    CLK_HROW:ENABLE.HIN9_L[8, 27, 22]
    CLK_HROW:ENABLE.HIN9_R[8, 29, 22]
    CLK_HROW:ENABLE.RCLK0_L[8, 26, 14]
    CLK_HROW:ENABLE.RCLK0_R[8, 28, 14]
    CLK_HROW:ENABLE.RCLK1_L[8, 27, 14]
    CLK_HROW:ENABLE.RCLK1_R[8, 29, 14]
    CLK_HROW:ENABLE.RCLK2_L[8, 26, 15]
    CLK_HROW:ENABLE.RCLK2_R[8, 28, 15]
    CLK_HROW:ENABLE.RCLK3_L[8, 27, 15]
    CLK_HROW:ENABLE.RCLK3_R[8, 29, 15]
    CLK_HROW:INV.GCLK_TEST0[0, 26, 21]
    CLK_HROW:INV.GCLK_TEST1[0, 28, 21]
    CLK_HROW:INV.GCLK_TEST10[1, 26, 37]
    CLK_HROW:INV.GCLK_TEST11[1, 28, 37]
    CLK_HROW:INV.GCLK_TEST12[1, 26, 53]
    CLK_HROW:INV.GCLK_TEST13[1, 28, 53]
    CLK_HROW:INV.GCLK_TEST14[2, 26, 5]
    CLK_HROW:INV.GCLK_TEST15[2, 28, 5]
    CLK_HROW:INV.GCLK_TEST16[5, 26, 53]
    CLK_HROW:INV.GCLK_TEST17[5, 28, 53]
    CLK_HROW:INV.GCLK_TEST18[6, 26, 5]
    CLK_HROW:INV.GCLK_TEST19[6, 28, 5]
    CLK_HROW:INV.GCLK_TEST2[0, 26, 37]
    CLK_HROW:INV.GCLK_TEST20[6, 26, 21]
    CLK_HROW:INV.GCLK_TEST21[6, 28, 21]
    CLK_HROW:INV.GCLK_TEST22[6, 26, 37]
    CLK_HROW:INV.GCLK_TEST23[6, 28, 37]
    CLK_HROW:INV.GCLK_TEST24[6, 26, 53]
    CLK_HROW:INV.GCLK_TEST25[6, 28, 53]
    CLK_HROW:INV.GCLK_TEST26[7, 26, 5]
    CLK_HROW:INV.GCLK_TEST27[7, 28, 5]
    CLK_HROW:INV.GCLK_TEST28[7, 26, 21]
    CLK_HROW:INV.GCLK_TEST29[7, 28, 21]
    CLK_HROW:INV.GCLK_TEST3[0, 28, 37]
    CLK_HROW:INV.GCLK_TEST30[7, 26, 37]
    CLK_HROW:INV.GCLK_TEST31[7, 28, 37]
    CLK_HROW:INV.GCLK_TEST4[0, 26, 53]
    CLK_HROW:INV.GCLK_TEST5[0, 28, 53]
    CLK_HROW:INV.GCLK_TEST6[1, 26, 5]
    CLK_HROW:INV.GCLK_TEST7[1, 28, 5]
    CLK_HROW:INV.GCLK_TEST8[1, 26, 21]
    CLK_HROW:INV.GCLK_TEST9[1, 28, 21]
    CLK_HROW:INV.HCLK_TEST_L[4, 26, 0]
    CLK_HROW:INV.HCLK_TEST_R[4, 28, 0]
    Non-inverted[0]
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO2[0, 27, 46][0, 26, 46][0, 27, 45][0, 26, 45][0, 27, 44][0, 26, 44][0, 27, 47][0, 26, 47][0, 27, 41][0, 26, 41][0, 26, 42][0, 26, 40][0, 27, 40][0, 26, 36]
    CLK_HROW:MUX.CASCO3[0, 29, 46][0, 28, 46][0, 29, 45][0, 28, 45][0, 29, 44][0, 28, 44][0, 29, 47][0, 28, 47][0, 29, 41][0, 28, 41][0, 28, 42][0, 28, 40][0, 29, 40][0, 28, 36]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST200000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST300000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO4[0, 27, 62][0, 26, 62][0, 27, 61][0, 26, 61][0, 27, 60][0, 26, 60][0, 27, 63][0, 26, 63][0, 27, 57][0, 26, 57][0, 26, 58][0, 26, 56][0, 27, 56][0, 26, 52]
    CLK_HROW:MUX.CASCO5[0, 29, 62][0, 28, 62][0, 29, 61][0, 28, 61][0, 29, 60][0, 28, 60][0, 29, 63][0, 28, 63][0, 29, 57][0, 28, 57][0, 28, 58][0, 28, 56][0, 29, 56][0, 28, 52]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST400000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST500000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO6[1, 27, 14][1, 26, 14][1, 27, 13][1, 26, 13][1, 27, 12][1, 26, 12][1, 27, 15][1, 26, 15][1, 27, 9][1, 26, 9][1, 26, 10][1, 26, 8][1, 27, 8][1, 26, 4]
    CLK_HROW:MUX.CASCO7[1, 29, 14][1, 28, 14][1, 29, 13][1, 28, 13][1, 29, 12][1, 28, 12][1, 29, 15][1, 28, 15][1, 29, 9][1, 28, 9][1, 28, 10][1, 28, 8][1, 29, 8][1, 28, 4]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST600000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST700000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO8[1, 27, 30][1, 26, 30][1, 27, 29][1, 26, 29][1, 27, 28][1, 26, 28][1, 27, 31][1, 26, 31][1, 27, 25][1, 26, 25][1, 26, 26][1, 26, 24][1, 27, 24][1, 26, 20]
    CLK_HROW:MUX.CASCO9[1, 29, 30][1, 28, 30][1, 29, 29][1, 28, 29][1, 29, 28][1, 28, 28][1, 29, 31][1, 28, 31][1, 29, 25][1, 28, 25][1, 28, 26][1, 28, 24][1, 29, 24][1, 28, 20]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST800000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST900000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO10[1, 27, 46][1, 26, 46][1, 27, 45][1, 26, 45][1, 27, 44][1, 26, 44][1, 27, 47][1, 26, 47][1, 27, 41][1, 26, 41][1, 26, 42][1, 26, 40][1, 27, 40][1, 26, 36]
    CLK_HROW:MUX.CASCO11[1, 29, 46][1, 28, 46][1, 29, 45][1, 28, 45][1, 29, 44][1, 28, 44][1, 29, 47][1, 28, 47][1, 29, 41][1, 28, 41][1, 28, 42][1, 28, 40][1, 29, 40][1, 28, 36]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST1000000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST1100000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO12[1, 27, 62][1, 26, 62][1, 27, 61][1, 26, 61][1, 27, 60][1, 26, 60][1, 27, 63][1, 26, 63][1, 27, 57][1, 26, 57][1, 26, 58][1, 26, 56][1, 27, 56][1, 26, 52]
    CLK_HROW:MUX.CASCO13[1, 29, 62][1, 28, 62][1, 29, 61][1, 28, 61][1, 29, 60][1, 28, 60][1, 29, 63][1, 28, 63][1, 29, 57][1, 28, 57][1, 28, 58][1, 28, 56][1, 29, 56][1, 28, 52]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST1200000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST1300000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO14[2, 27, 14][2, 26, 14][2, 27, 13][2, 26, 13][2, 27, 12][2, 26, 12][2, 27, 15][2, 26, 15][2, 27, 9][2, 26, 9][2, 26, 10][2, 26, 8][2, 27, 8][2, 26, 4]
    CLK_HROW:MUX.CASCO15[2, 29, 14][2, 28, 14][2, 29, 13][2, 28, 13][2, 29, 12][2, 28, 12][2, 29, 15][2, 28, 15][2, 29, 9][2, 28, 9][2, 28, 10][2, 28, 8][2, 29, 8][2, 28, 4]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST1400000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST1500000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:INV.CE[3, 27, 19]
    BUFHCE_L10:INV.CE[4, 27, 35]
    BUFHCE_L11:INV.CE[4, 29, 35]
    BUFHCE_L1:INV.CE[3, 29, 19]
    BUFHCE_L2:INV.CE[3, 27, 35]
    BUFHCE_L3:INV.CE[3, 29, 35]
    BUFHCE_L4:INV.CE[3, 27, 51]
    BUFHCE_L5:INV.CE[3, 29, 51]
    BUFHCE_L6:INV.CE[4, 27, 3]
    BUFHCE_L7:INV.CE[4, 29, 3]
    BUFHCE_L8:INV.CE[4, 27, 19]
    BUFHCE_L9:INV.CE[4, 29, 19]
    BUFHCE_R0:INV.CE[2, 27, 35]
    BUFHCE_R10:INV.CE[5, 27, 19]
    BUFHCE_R11:INV.CE[5, 29, 19]
    BUFHCE_R1:INV.CE[2, 29, 35]
    BUFHCE_R2:INV.CE[2, 27, 51]
    BUFHCE_R3:INV.CE[2, 29, 51]
    BUFHCE_R4:INV.CE[3, 27, 3]
    BUFHCE_R5:INV.CE[3, 29, 3]
    BUFHCE_R6:INV.CE[4, 27, 51]
    BUFHCE_R7:INV.CE[4, 29, 51]
    BUFHCE_R8:INV.CE[5, 27, 3]
    BUFHCE_R9:INV.CE[5, 29, 3]
    Inverted~[0]
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:CE_TYPE[3, 27, 22]
    BUFHCE_L10:CE_TYPE[4, 27, 38]
    BUFHCE_L11:CE_TYPE[4, 29, 38]
    BUFHCE_L1:CE_TYPE[3, 29, 22]
    BUFHCE_L2:CE_TYPE[3, 27, 38]
    BUFHCE_L3:CE_TYPE[3, 29, 38]
    BUFHCE_L4:CE_TYPE[3, 27, 54]
    BUFHCE_L5:CE_TYPE[3, 29, 54]
    BUFHCE_L6:CE_TYPE[4, 27, 6]
    BUFHCE_L7:CE_TYPE[4, 29, 6]
    BUFHCE_L8:CE_TYPE[4, 27, 22]
    BUFHCE_L9:CE_TYPE[4, 29, 22]
    BUFHCE_R0:CE_TYPE[2, 27, 38]
    BUFHCE_R10:CE_TYPE[5, 27, 22]
    BUFHCE_R11:CE_TYPE[5, 29, 22]
    BUFHCE_R1:CE_TYPE[2, 29, 38]
    BUFHCE_R2:CE_TYPE[2, 27, 54]
    BUFHCE_R3:CE_TYPE[2, 29, 54]
    BUFHCE_R4:CE_TYPE[3, 27, 6]
    BUFHCE_R5:CE_TYPE[3, 29, 6]
    BUFHCE_R6:CE_TYPE[4, 27, 54]
    BUFHCE_R7:CE_TYPE[4, 29, 54]
    BUFHCE_R8:CE_TYPE[5, 27, 6]
    BUFHCE_R9:CE_TYPE[5, 29, 6]
    SYNC0
    ASYNC1
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L10:MUX.I[4, 27, 47][4, 26, 47][4, 27, 46][4, 26, 46][4, 27, 45][4, 26, 45][4, 27, 44][4, 26, 44][4, 27, 41][4, 26, 41][4, 27, 40][4, 26, 40][4, 26, 42][4, 27, 42][4, 26, 43][4, 27, 43]
    BUFHCE_L11:MUX.I[4, 29, 47][4, 28, 47][4, 29, 46][4, 28, 46][4, 29, 45][4, 28, 45][4, 29, 44][4, 28, 44][4, 29, 41][4, 28, 41][4, 29, 40][4, 28, 40][4, 28, 42][4, 29, 42][4, 28, 43][4, 29, 43]
    BUFHCE_L6:MUX.I[4, 27, 15][4, 26, 15][4, 27, 14][4, 26, 14][4, 27, 13][4, 26, 13][4, 27, 12][4, 26, 12][4, 27, 9][4, 26, 9][4, 27, 8][4, 26, 8][4, 26, 10][4, 27, 10][4, 26, 11][4, 27, 11]
    BUFHCE_L7:MUX.I[4, 29, 15][4, 28, 15][4, 29, 14][4, 28, 14][4, 29, 13][4, 28, 13][4, 29, 12][4, 28, 12][4, 29, 9][4, 28, 9][4, 29, 8][4, 28, 8][4, 28, 10][4, 29, 10][4, 28, 11][4, 29, 11]
    BUFHCE_L8:MUX.I[4, 27, 31][4, 26, 31][4, 27, 30][4, 26, 30][4, 27, 29][4, 26, 29][4, 27, 28][4, 26, 28][4, 27, 25][4, 26, 25][4, 27, 24][4, 26, 24][4, 26, 26][4, 27, 26][4, 26, 27][4, 27, 27]
    BUFHCE_L9:MUX.I[4, 29, 31][4, 28, 31][4, 29, 30][4, 28, 30][4, 29, 29][4, 28, 29][4, 29, 28][4, 28, 28][4, 29, 25][4, 28, 25][4, 29, 24][4, 28, 24][4, 28, 26][4, 29, 26][4, 28, 27][4, 29, 27]
    BUFHCE_R0:MUX.I[2, 27, 47][2, 26, 47][2, 27, 46][2, 26, 46][2, 27, 45][2, 26, 45][2, 27, 44][2, 26, 44][2, 27, 41][2, 26, 41][2, 27, 40][2, 26, 40][2, 26, 42][2, 27, 42][2, 26, 43][2, 27, 43]
    BUFHCE_R1:MUX.I[2, 29, 47][2, 28, 47][2, 29, 46][2, 28, 46][2, 29, 45][2, 28, 45][2, 29, 44][2, 28, 44][2, 29, 41][2, 28, 41][2, 29, 40][2, 28, 40][2, 28, 42][2, 29, 42][2, 28, 43][2, 29, 43]
    BUFHCE_R2:MUX.I[2, 27, 63][2, 26, 63][2, 27, 62][2, 26, 62][2, 27, 61][2, 26, 61][2, 27, 60][2, 26, 60][2, 27, 57][2, 26, 57][2, 27, 56][2, 26, 56][2, 26, 58][2, 27, 58][2, 26, 59][2, 27, 59]
    BUFHCE_R3:MUX.I[2, 29, 63][2, 28, 63][2, 29, 62][2, 28, 62][2, 29, 61][2, 28, 61][2, 29, 60][2, 28, 60][2, 29, 57][2, 28, 57][2, 29, 56][2, 28, 56][2, 28, 58][2, 29, 58][2, 28, 59][2, 29, 59]
    BUFHCE_R4:MUX.I[3, 27, 15][3, 26, 15][3, 27, 14][3, 26, 14][3, 27, 13][3, 26, 13][3, 27, 12][3, 26, 12][3, 27, 9][3, 26, 9][3, 27, 8][3, 26, 8][3, 26, 10][3, 27, 10][3, 26, 11][3, 27, 11]
    BUFHCE_R5:MUX.I[3, 29, 15][3, 28, 15][3, 29, 14][3, 28, 14][3, 29, 13][3, 28, 13][3, 29, 12][3, 28, 12][3, 29, 9][3, 28, 9][3, 29, 8][3, 28, 8][3, 28, 10][3, 29, 10][3, 28, 11][3, 29, 11]
    NONE0000000000000000
    GCLK00000000100000001
    GCLK80000000100000010
    GCLK160000000100000100
    GCLK240000000100001000
    HIN0_L0000000100010000
    HIN8_L0000000100100000
    HIN0_R0000000101000000
    HIN8_R0000000110000000
    GCLK10000001000000001
    GCLK90000001000000010
    GCLK170000001000000100
    GCLK250000001000001000
    HIN1_L0000001000010000
    HIN9_L0000001000100000
    HIN1_R0000001001000000
    HIN9_R0000001010000000
    GCLK20000010000000001
    GCLK100000010000000010
    GCLK180000010000000100
    GCLK260000010000001000
    HIN2_L0000010000010000
    HIN10_L0000010000100000
    HIN2_R0000010001000000
    HIN10_R0000010010000000
    GCLK30000100000000001
    GCLK110000100000000010
    GCLK190000100000000100
    GCLK270000100000001000
    HIN3_L0000100000010000
    HIN11_L0000100000100000
    HIN3_R0000100001000000
    HIN11_R0000100010000000
    GCLK40001000000000001
    GCLK120001000000000010
    GCLK200001000000000100
    GCLK280001000000001000
    HIN4_L0001000000010000
    HIN12_L0001000000100000
    HIN4_R0001000001000000
    HIN12_R0001000010000000
    GCLK50010000000000001
    GCLK130010000000000010
    GCLK210010000000000100
    GCLK290010000000001000
    HIN5_L0010000000010000
    HIN13_L0010000000100000
    HIN5_R0010000001000000
    HIN13_R0010000010000000
    GCLK60100000000000001
    GCLK140100000000000010
    GCLK220100000000000100
    GCLK300100000000001000
    HIN6_L0100000000010000
    HCLK_TEST_L0100000000100000
    HIN6_R0100000001000000
    CKINT00100000010000000
    GCLK71000000000000001
    GCLK151000000000000010
    GCLK231000000000000100
    GCLK311000000000001000
    HIN7_L1000000000010000
    HCLK_TEST_R1000000000100000
    HIN7_R1000000001000000
    CKINT11000000010000000
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    BUFHCE_L0:MUX.I[3, 27, 31][3, 26, 31][3, 27, 30][3, 26, 30][3, 27, 29][3, 26, 29][3, 27, 28][3, 26, 28][3, 27, 25][3, 26, 25][3, 27, 24][3, 26, 24][3, 26, 26][3, 27, 26][3, 26, 27][3, 27, 27]
    BUFHCE_L1:MUX.I[3, 29, 31][3, 28, 31][3, 29, 30][3, 28, 30][3, 29, 29][3, 28, 29][3, 29, 28][3, 28, 28][3, 29, 25][3, 28, 25][3, 29, 24][3, 28, 24][3, 28, 26][3, 29, 26][3, 28, 27][3, 29, 27]
    BUFHCE_L2:MUX.I[3, 27, 47][3, 26, 47][3, 27, 46][3, 26, 46][3, 27, 45][3, 26, 45][3, 27, 44][3, 26, 44][3, 27, 41][3, 26, 41][3, 27, 40][3, 26, 40][3, 26, 42][3, 27, 42][3, 26, 43][3, 27, 43]
    BUFHCE_L3:MUX.I[3, 29, 47][3, 28, 47][3, 29, 46][3, 28, 46][3, 29, 45][3, 28, 45][3, 29, 44][3, 28, 44][3, 29, 41][3, 28, 41][3, 29, 40][3, 28, 40][3, 28, 42][3, 29, 42][3, 28, 43][3, 29, 43]
    BUFHCE_L4:MUX.I[3, 27, 63][3, 26, 63][3, 27, 62][3, 26, 62][3, 27, 61][3, 26, 61][3, 27, 60][3, 26, 60][3, 27, 57][3, 26, 57][3, 27, 56][3, 26, 56][3, 26, 58][3, 27, 58][3, 26, 59][3, 27, 59]
    BUFHCE_L5:MUX.I[3, 29, 63][3, 28, 63][3, 29, 62][3, 28, 62][3, 29, 61][3, 28, 61][3, 29, 60][3, 28, 60][3, 29, 57][3, 28, 57][3, 29, 56][3, 28, 56][3, 28, 58][3, 29, 58][3, 28, 59][3, 29, 59]
    BUFHCE_R10:MUX.I[5, 27, 31][5, 26, 31][5, 27, 30][5, 26, 30][5, 27, 29][5, 26, 29][5, 27, 28][5, 26, 28][5, 27, 25][5, 26, 25][5, 27, 24][5, 26, 24][5, 26, 26][5, 27, 26][5, 26, 27][5, 27, 27]
    BUFHCE_R11:MUX.I[5, 29, 31][5, 28, 31][5, 29, 30][5, 28, 30][5, 29, 29][5, 28, 29][5, 29, 28][5, 28, 28][5, 29, 25][5, 28, 25][5, 29, 24][5, 28, 24][5, 28, 26][5, 29, 26][5, 28, 27][5, 29, 27]
    BUFHCE_R6:MUX.I[4, 27, 63][4, 26, 63][4, 27, 62][4, 26, 62][4, 27, 61][4, 26, 61][4, 27, 60][4, 26, 60][4, 27, 57][4, 26, 57][4, 27, 56][4, 26, 56][4, 26, 58][4, 27, 58][4, 26, 59][4, 27, 59]
    BUFHCE_R7:MUX.I[4, 29, 63][4, 28, 63][4, 29, 62][4, 28, 62][4, 29, 61][4, 28, 61][4, 29, 60][4, 28, 60][4, 29, 57][4, 28, 57][4, 29, 56][4, 28, 56][4, 28, 58][4, 29, 58][4, 28, 59][4, 29, 59]
    BUFHCE_R8:MUX.I[5, 27, 15][5, 26, 15][5, 27, 14][5, 26, 14][5, 27, 13][5, 26, 13][5, 27, 12][5, 26, 12][5, 27, 9][5, 26, 9][5, 27, 8][5, 26, 8][5, 26, 10][5, 27, 10][5, 26, 11][5, 27, 11]
    BUFHCE_R9:MUX.I[5, 29, 15][5, 28, 15][5, 29, 14][5, 28, 14][5, 29, 13][5, 28, 13][5, 29, 12][5, 28, 12][5, 29, 9][5, 28, 9][5, 29, 8][5, 28, 8][5, 28, 10][5, 29, 10][5, 28, 11][5, 29, 11]
    NONE0000000000000000
    GCLK00000000100000001
    GCLK80000000100000010
    GCLK160000000100000100
    GCLK240000000100001000
    HIN0_L0000000100010000
    HIN8_L0000000100100000
    HIN0_R0000000101000000
    HIN8_R0000000110000000
    GCLK10000001000000001
    GCLK90000001000000010
    GCLK170000001000000100
    GCLK250000001000001000
    HIN1_L0000001000010000
    HIN9_L0000001000100000
    HIN1_R0000001001000000
    HIN9_R0000001010000000
    GCLK20000010000000001
    GCLK100000010000000010
    GCLK180000010000000100
    GCLK260000010000001000
    HIN2_L0000010000010000
    HIN10_L0000010000100000
    HIN2_R0000010001000000
    HIN10_R0000010010000000
    GCLK30000100000000001
    GCLK110000100000000010
    GCLK190000100000000100
    GCLK270000100000001000
    HIN3_L0000100000010000
    HIN11_L0000100000100000
    HIN3_R0000100001000000
    HIN11_R0000100010000000
    GCLK40001000000000001
    GCLK120001000000000010
    GCLK200001000000000100
    GCLK280001000000001000
    HIN4_L0001000000010000
    HIN12_L0001000000100000
    HIN4_R0001000001000000
    HIN12_R0001000010000000
    GCLK50010000000000001
    GCLK130010000000000010
    GCLK210010000000000100
    GCLK290010000000001000
    HIN5_L0010000000010000
    HIN13_L0010000000100000
    HIN5_R0010000001000000
    HIN13_R0010000010000000
    GCLK60100000000000001
    GCLK140100000000000010
    GCLK220100000000000100
    GCLK300100000000001000
    HIN6_L0100000000010000
    HCLK_TEST_L0100000000100000
    HIN6_R0100000001000000
    CKINT20100000010000000
    GCLK71000000000000001
    GCLK151000000000000010
    GCLK231000000000000100
    GCLK311000000000001000
    HIN7_L1000000000010000
    HCLK_TEST_R1000000000100000
    HIN7_R1000000001000000
    CKINT31000000010000000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO16[5, 27, 62][5, 26, 62][5, 27, 61][5, 26, 61][5, 27, 60][5, 26, 60][5, 27, 63][5, 26, 63][5, 27, 57][5, 26, 57][5, 26, 58][5, 26, 56][5, 27, 56][5, 26, 52]
    CLK_HROW:MUX.CASCO17[5, 29, 62][5, 28, 62][5, 29, 61][5, 28, 61][5, 29, 60][5, 28, 60][5, 29, 63][5, 28, 63][5, 29, 57][5, 28, 57][5, 28, 58][5, 28, 56][5, 29, 56][5, 28, 52]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST1600000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST1700000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO18[6, 27, 14][6, 26, 14][6, 27, 13][6, 26, 13][6, 27, 12][6, 26, 12][6, 27, 15][6, 26, 15][6, 27, 9][6, 26, 9][6, 26, 10][6, 26, 8][6, 27, 8][6, 26, 4]
    CLK_HROW:MUX.CASCO19[6, 29, 14][6, 28, 14][6, 29, 13][6, 28, 13][6, 29, 12][6, 28, 12][6, 29, 15][6, 28, 15][6, 29, 9][6, 28, 9][6, 28, 10][6, 28, 8][6, 29, 8][6, 28, 4]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST1800000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST1900000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO20[6, 27, 30][6, 26, 30][6, 27, 29][6, 26, 29][6, 27, 28][6, 26, 28][6, 27, 31][6, 26, 31][6, 27, 25][6, 26, 25][6, 26, 26][6, 26, 24][6, 27, 24][6, 26, 20]
    CLK_HROW:MUX.CASCO21[6, 29, 30][6, 28, 30][6, 29, 29][6, 28, 29][6, 29, 28][6, 28, 28][6, 29, 31][6, 28, 31][6, 29, 25][6, 28, 25][6, 28, 26][6, 28, 24][6, 29, 24][6, 28, 20]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST2000000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST2100000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO22[6, 27, 46][6, 26, 46][6, 27, 45][6, 26, 45][6, 27, 44][6, 26, 44][6, 27, 47][6, 26, 47][6, 27, 41][6, 26, 41][6, 26, 42][6, 26, 40][6, 27, 40][6, 26, 36]
    CLK_HROW:MUX.CASCO23[6, 29, 46][6, 28, 46][6, 29, 45][6, 28, 45][6, 29, 44][6, 28, 44][6, 29, 47][6, 28, 47][6, 29, 41][6, 28, 41][6, 28, 42][6, 28, 40][6, 29, 40][6, 28, 36]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST2200000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST2300000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO24[6, 27, 62][6, 26, 62][6, 27, 61][6, 26, 61][6, 27, 60][6, 26, 60][6, 27, 63][6, 26, 63][6, 27, 57][6, 26, 57][6, 26, 58][6, 26, 56][6, 27, 56][6, 26, 52]
    CLK_HROW:MUX.CASCO25[6, 29, 62][6, 28, 62][6, 29, 61][6, 28, 61][6, 29, 60][6, 28, 60][6, 29, 63][6, 28, 63][6, 29, 57][6, 28, 57][6, 28, 58][6, 28, 56][6, 29, 56][6, 28, 52]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST2400000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST2500000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO26[7, 27, 14][7, 26, 14][7, 27, 13][7, 26, 13][7, 27, 12][7, 26, 12][7, 27, 15][7, 26, 15][7, 27, 9][7, 26, 9][7, 26, 10][7, 26, 8][7, 27, 8][7, 26, 4]
    CLK_HROW:MUX.CASCO27[7, 29, 14][7, 28, 14][7, 29, 13][7, 28, 13][7, 29, 12][7, 28, 12][7, 29, 15][7, 28, 15][7, 29, 9][7, 28, 9][7, 28, 10][7, 28, 8][7, 29, 8][7, 28, 4]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST2600000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST2700000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO28[7, 27, 30][7, 26, 30][7, 27, 29][7, 26, 29][7, 27, 28][7, 26, 28][7, 27, 31][7, 26, 31][7, 27, 25][7, 26, 25][7, 26, 26][7, 26, 24][7, 27, 24][7, 26, 20]
    CLK_HROW:MUX.CASCO29[7, 29, 30][7, 28, 30][7, 29, 29][7, 28, 29][7, 29, 28][7, 28, 28][7, 29, 31][7, 28, 31][7, 29, 25][7, 28, 25][7, 28, 26][7, 28, 24][7, 29, 24][7, 28, 20]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST2800000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST2900000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.CASCO30[7, 27, 46][7, 26, 46][7, 27, 45][7, 26, 45][7, 27, 44][7, 26, 44][7, 27, 47][7, 26, 47][7, 27, 41][7, 26, 41][7, 26, 42][7, 26, 40][7, 27, 40][7, 26, 36]
    CLK_HROW:MUX.CASCO31[7, 29, 46][7, 28, 46][7, 29, 45][7, 28, 45][7, 29, 44][7, 28, 44][7, 29, 47][7, 28, 47][7, 29, 41][7, 28, 41][7, 28, 42][7, 28, 40][7, 29, 40][7, 28, 36]
    NONE00000000000000
    CASCI00000000000001
    HCLK_TEST_L00000001000010
    HIN6_L00000001000100
    RCLK2_R00000001001000
    HIN6_R00000001010000
    GCLK_TEST3000000001100000
    HCLK_TEST_R00000010000010
    HIN7_L00000010000100
    RCLK3_R00000010001000
    HIN7_R00000010010000
    GCLK_TEST3100000010100000
    HIN8_L00000100000010
    HIN0_L00000100000100
    RCLK0_L00000100001000
    HIN0_R00000100010000
    HIN8_R00000100100000
    HIN9_L00001000000010
    HIN1_L00001000000100
    RCLK1_L00001000001000
    HIN1_R00001000010000
    HIN9_R00001000100000
    HIN10_L00010000000010
    HIN2_L00010000000100
    RCLK2_L00010000001000
    HIN2_R00010000010000
    HIN10_R00010000100000
    HIN11_L00100000000010
    HIN3_L00100000000100
    RCLK3_L00100000001000
    HIN3_R00100000010000
    HIN11_R00100000100000
    HIN12_L01000000000010
    HIN4_L01000000000100
    RCLK0_R01000000001000
    HIN4_R01000000010000
    HIN12_R01000000100000
    HIN13_L10000000000010
    HIN5_L10000000000100
    RCLK1_R10000000001000
    HIN5_R10000000010000
    HIN13_R10000000100000
    +
    +
    + + + + + + + + + + + + + + + + + + +
    CLK_HROW:MUX.HCLK_TEST_L[4, 26, 2][4, 27, 1][4, 26, 1][4, 27, 0][8, 27, 17][8, 26, 17][8, 27, 16][8, 26, 16]
    CLK_HROW:MUX.HCLK_TEST_R[4, 28, 2][4, 29, 1][4, 28, 1][4, 29, 0][8, 29, 17][8, 28, 17][8, 29, 16][8, 28, 16]
    NONE00000000
    HIN000010001
    HIN400010010
    HIN800010100
    HIN1200011000
    HIN100100001
    HIN500100010
    HIN900100100
    HIN1300101000
    HIN201000001
    HIN601000010
    HIN1001000100
    HIN310000001
    HIN710000010
    HIN1110000100
    +
    +
    +

    CLK_BUFG_REBUF

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG_REBUF bittile 0
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK24_UCLK_REBUF:ENABLE.GCLK16_U
    1--------------------------CLK_REBUF:ENABLE.GCLK8_UCLK_REBUF:ENABLE.GCLK0_U
    2--------------------------CLK_REBUF:ENABLE.GCLK24_DCLK_REBUF:ENABLE.GCLK16_D
    3--------------------------CLK_REBUF:ENABLE.GCLK8_DCLK_REBUF:ENABLE.GCLK0_D
    4----------------------------
    5----------------------------
    6--------------------------CLK_REBUF:INV.GCLK1_D.GCLK0_DCLK_REBUF:INV.GCLK9_D.GCLK8_D
    7--------------------------CLK_REBUF:INV.GCLK17_D.GCLK16_DCLK_REBUF:INV.GCLK25_D.GCLK24_D
    8--------------------------CLK_REBUF:BUF.GCLK1_D.GCLK0_DCLK_REBUF:BUF.GCLK9_D.GCLK8_D
    9--------------------------CLK_REBUF:BUF.GCLK17_D.GCLK16_DCLK_REBUF:BUF.GCLK25_D.GCLK24_D
    10----------------------------
    11----------------------------
    12--------------------------CLK_REBUF:BUF.GCLK24_UCLK_REBUF:BUF.GCLK16_U
    13--------------------------CLK_REBUF:BUF.GCLK8_UCLK_REBUF:BUF.GCLK0_U
    14--------------------------CLK_REBUF:BUF.GCLK24_DCLK_REBUF:BUF.GCLK16_D
    15--------------------------CLK_REBUF:BUF.GCLK8_DCLK_REBUF:BUF.GCLK0_D
    16--------------------------CLK_REBUF:ENABLE.GCLK25_UCLK_REBUF:ENABLE.GCLK17_U
    17--------------------------CLK_REBUF:ENABLE.GCLK9_UCLK_REBUF:ENABLE.GCLK1_U
    18--------------------------CLK_REBUF:ENABLE.GCLK25_DCLK_REBUF:ENABLE.GCLK17_D
    19--------------------------CLK_REBUF:ENABLE.GCLK9_DCLK_REBUF:ENABLE.GCLK1_D
    20----------------------------
    21----------------------------
    22--------------------------CLK_REBUF:INV.GCLK0_U.GCLK1_UCLK_REBUF:INV.GCLK8_U.GCLK9_U
    23--------------------------CLK_REBUF:INV.GCLK16_U.GCLK17_UCLK_REBUF:INV.GCLK24_U.GCLK25_U
    24--------------------------CLK_REBUF:BUF.GCLK0_U.GCLK1_UCLK_REBUF:BUF.GCLK8_U.GCLK9_U
    25--------------------------CLK_REBUF:BUF.GCLK16_U.GCLK17_UCLK_REBUF:BUF.GCLK24_U.GCLK25_U
    26----------------------------
    27----------------------------
    28--------------------------CLK_REBUF:BUF.GCLK25_UCLK_REBUF:BUF.GCLK17_U
    29--------------------------CLK_REBUF:BUF.GCLK9_UCLK_REBUF:BUF.GCLK1_U
    30--------------------------CLK_REBUF:BUF.GCLK25_DCLK_REBUF:BUF.GCLK17_D
    31--------------------------CLK_REBUF:BUF.GCLK9_DCLK_REBUF:BUF.GCLK1_D
    32--------------------------CLK_REBUF:ENABLE.GCLK26_UCLK_REBUF:ENABLE.GCLK18_U
    33--------------------------CLK_REBUF:ENABLE.GCLK10_UCLK_REBUF:ENABLE.GCLK2_U
    34--------------------------CLK_REBUF:ENABLE.GCLK26_DCLK_REBUF:ENABLE.GCLK18_D
    35--------------------------CLK_REBUF:ENABLE.GCLK10_DCLK_REBUF:ENABLE.GCLK2_D
    36----------------------------
    37----------------------------
    38--------------------------CLK_REBUF:INV.GCLK3_D.GCLK2_DCLK_REBUF:INV.GCLK11_D.GCLK10_D
    39--------------------------CLK_REBUF:INV.GCLK19_D.GCLK18_DCLK_REBUF:INV.GCLK27_D.GCLK26_D
    40--------------------------CLK_REBUF:BUF.GCLK3_D.GCLK2_DCLK_REBUF:BUF.GCLK11_D.GCLK10_D
    41--------------------------CLK_REBUF:BUF.GCLK19_D.GCLK18_DCLK_REBUF:BUF.GCLK27_D.GCLK26_D
    42----------------------------
    43----------------------------
    44--------------------------CLK_REBUF:BUF.GCLK26_UCLK_REBUF:BUF.GCLK18_U
    45--------------------------CLK_REBUF:BUF.GCLK10_UCLK_REBUF:BUF.GCLK2_U
    46--------------------------CLK_REBUF:BUF.GCLK26_DCLK_REBUF:BUF.GCLK18_D
    47--------------------------CLK_REBUF:BUF.GCLK10_DCLK_REBUF:BUF.GCLK2_D
    48--------------------------CLK_REBUF:ENABLE.GCLK27_UCLK_REBUF:ENABLE.GCLK19_U
    49--------------------------CLK_REBUF:ENABLE.GCLK11_UCLK_REBUF:ENABLE.GCLK3_U
    50--------------------------CLK_REBUF:ENABLE.GCLK27_DCLK_REBUF:ENABLE.GCLK19_D
    51--------------------------CLK_REBUF:ENABLE.GCLK11_DCLK_REBUF:ENABLE.GCLK3_D
    52----------------------------
    53----------------------------
    54--------------------------CLK_REBUF:INV.GCLK2_U.GCLK3_UCLK_REBUF:INV.GCLK10_U.GCLK11_U
    55--------------------------CLK_REBUF:INV.GCLK18_U.GCLK19_UCLK_REBUF:INV.GCLK26_U.GCLK27_U
    56--------------------------CLK_REBUF:BUF.GCLK2_U.GCLK3_UCLK_REBUF:BUF.GCLK10_U.GCLK11_U
    57--------------------------CLK_REBUF:BUF.GCLK18_U.GCLK19_UCLK_REBUF:BUF.GCLK26_U.GCLK27_U
    58----------------------------
    59----------------------------
    60--------------------------CLK_REBUF:BUF.GCLK27_UCLK_REBUF:BUF.GCLK19_U
    61--------------------------CLK_REBUF:BUF.GCLK11_UCLK_REBUF:BUF.GCLK3_U
    62--------------------------CLK_REBUF:BUF.GCLK27_DCLK_REBUF:BUF.GCLK19_D
    63--------------------------CLK_REBUF:BUF.GCLK11_DCLK_REBUF:BUF.GCLK3_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BUFG_REBUF bittile 1
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK28_UCLK_REBUF:ENABLE.GCLK20_U
    1--------------------------CLK_REBUF:ENABLE.GCLK12_UCLK_REBUF:ENABLE.GCLK4_U
    2--------------------------CLK_REBUF:ENABLE.GCLK28_DCLK_REBUF:ENABLE.GCLK20_D
    3--------------------------CLK_REBUF:ENABLE.GCLK12_DCLK_REBUF:ENABLE.GCLK4_D
    4----------------------------
    5----------------------------
    6--------------------------CLK_REBUF:INV.GCLK5_D.GCLK4_DCLK_REBUF:INV.GCLK13_D.GCLK12_D
    7--------------------------CLK_REBUF:INV.GCLK21_D.GCLK20_DCLK_REBUF:INV.GCLK29_D.GCLK28_D
    8--------------------------CLK_REBUF:BUF.GCLK5_D.GCLK4_DCLK_REBUF:BUF.GCLK13_D.GCLK12_D
    9--------------------------CLK_REBUF:BUF.GCLK21_D.GCLK20_DCLK_REBUF:BUF.GCLK29_D.GCLK28_D
    10----------------------------
    11----------------------------
    12--------------------------CLK_REBUF:BUF.GCLK28_UCLK_REBUF:BUF.GCLK20_U
    13--------------------------CLK_REBUF:BUF.GCLK12_UCLK_REBUF:BUF.GCLK4_U
    14--------------------------CLK_REBUF:BUF.GCLK28_DCLK_REBUF:BUF.GCLK20_D
    15--------------------------CLK_REBUF:BUF.GCLK12_DCLK_REBUF:BUF.GCLK4_D
    16--------------------------CLK_REBUF:ENABLE.GCLK29_UCLK_REBUF:ENABLE.GCLK21_U
    17--------------------------CLK_REBUF:ENABLE.GCLK13_UCLK_REBUF:ENABLE.GCLK5_U
    18--------------------------CLK_REBUF:ENABLE.GCLK29_DCLK_REBUF:ENABLE.GCLK21_D
    19--------------------------CLK_REBUF:ENABLE.GCLK13_DCLK_REBUF:ENABLE.GCLK5_D
    20----------------------------
    21----------------------------
    22--------------------------CLK_REBUF:INV.GCLK4_U.GCLK5_UCLK_REBUF:INV.GCLK12_U.GCLK13_U
    23--------------------------CLK_REBUF:INV.GCLK20_U.GCLK21_UCLK_REBUF:INV.GCLK28_U.GCLK29_U
    24--------------------------CLK_REBUF:BUF.GCLK4_U.GCLK5_UCLK_REBUF:BUF.GCLK12_U.GCLK13_U
    25--------------------------CLK_REBUF:BUF.GCLK20_U.GCLK21_UCLK_REBUF:BUF.GCLK28_U.GCLK29_U
    26----------------------------
    27----------------------------
    28--------------------------CLK_REBUF:BUF.GCLK29_UCLK_REBUF:BUF.GCLK21_U
    29--------------------------CLK_REBUF:BUF.GCLK13_UCLK_REBUF:BUF.GCLK5_U
    30--------------------------CLK_REBUF:BUF.GCLK29_DCLK_REBUF:BUF.GCLK21_D
    31--------------------------CLK_REBUF:BUF.GCLK13_DCLK_REBUF:BUF.GCLK5_D
    32--------------------------CLK_REBUF:ENABLE.GCLK30_UCLK_REBUF:ENABLE.GCLK22_U
    33--------------------------CLK_REBUF:ENABLE.GCLK14_UCLK_REBUF:ENABLE.GCLK6_U
    34--------------------------CLK_REBUF:ENABLE.GCLK30_DCLK_REBUF:ENABLE.GCLK22_D
    35--------------------------CLK_REBUF:ENABLE.GCLK14_DCLK_REBUF:ENABLE.GCLK6_D
    36----------------------------
    37----------------------------
    38--------------------------CLK_REBUF:INV.GCLK7_D.GCLK6_DCLK_REBUF:INV.GCLK15_D.GCLK14_D
    39--------------------------CLK_REBUF:INV.GCLK23_D.GCLK22_DCLK_REBUF:INV.GCLK31_D.GCLK30_D
    40--------------------------CLK_REBUF:BUF.GCLK7_D.GCLK6_DCLK_REBUF:BUF.GCLK15_D.GCLK14_D
    41--------------------------CLK_REBUF:BUF.GCLK23_D.GCLK22_DCLK_REBUF:BUF.GCLK31_D.GCLK30_D
    42----------------------------
    43----------------------------
    44--------------------------CLK_REBUF:BUF.GCLK30_UCLK_REBUF:BUF.GCLK22_U
    45--------------------------CLK_REBUF:BUF.GCLK14_UCLK_REBUF:BUF.GCLK6_U
    46--------------------------CLK_REBUF:BUF.GCLK30_DCLK_REBUF:BUF.GCLK22_D
    47--------------------------CLK_REBUF:BUF.GCLK14_DCLK_REBUF:BUF.GCLK6_D
    48--------------------------CLK_REBUF:ENABLE.GCLK31_UCLK_REBUF:ENABLE.GCLK23_U
    49--------------------------CLK_REBUF:ENABLE.GCLK15_UCLK_REBUF:ENABLE.GCLK7_U
    50--------------------------CLK_REBUF:ENABLE.GCLK31_DCLK_REBUF:ENABLE.GCLK23_D
    51--------------------------CLK_REBUF:ENABLE.GCLK15_DCLK_REBUF:ENABLE.GCLK7_D
    52----------------------------
    53----------------------------
    54--------------------------CLK_REBUF:INV.GCLK6_U.GCLK7_UCLK_REBUF:INV.GCLK14_U.GCLK15_U
    55--------------------------CLK_REBUF:INV.GCLK22_U.GCLK23_UCLK_REBUF:INV.GCLK30_U.GCLK31_U
    56--------------------------CLK_REBUF:BUF.GCLK6_U.GCLK7_UCLK_REBUF:BUF.GCLK14_U.GCLK15_U
    57--------------------------CLK_REBUF:BUF.GCLK22_U.GCLK23_UCLK_REBUF:BUF.GCLK30_U.GCLK31_U
    58----------------------------
    59----------------------------
    60--------------------------CLK_REBUF:BUF.GCLK31_UCLK_REBUF:BUF.GCLK23_U
    61--------------------------CLK_REBUF:BUF.GCLK15_UCLK_REBUF:BUF.GCLK7_U
    62--------------------------CLK_REBUF:BUF.GCLK31_DCLK_REBUF:BUF.GCLK23_D
    63--------------------------CLK_REBUF:BUF.GCLK15_DCLK_REBUF:BUF.GCLK7_D
    +
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_REBUF:BUF.GCLK0_D[0, 27, 15]
    CLK_REBUF:BUF.GCLK0_U[0, 27, 13]
    CLK_REBUF:BUF.GCLK0_U.GCLK1_U[0, 26, 24]
    CLK_REBUF:BUF.GCLK10_D[0, 26, 47]
    CLK_REBUF:BUF.GCLK10_U[0, 26, 45]
    CLK_REBUF:BUF.GCLK10_U.GCLK11_U[0, 27, 56]
    CLK_REBUF:BUF.GCLK11_D[0, 26, 63]
    CLK_REBUF:BUF.GCLK11_D.GCLK10_D[0, 27, 40]
    CLK_REBUF:BUF.GCLK11_U[0, 26, 61]
    CLK_REBUF:BUF.GCLK12_D[1, 26, 15]
    CLK_REBUF:BUF.GCLK12_U[1, 26, 13]
    CLK_REBUF:BUF.GCLK12_U.GCLK13_U[1, 27, 24]
    CLK_REBUF:BUF.GCLK13_D[1, 26, 31]
    CLK_REBUF:BUF.GCLK13_D.GCLK12_D[1, 27, 8]
    CLK_REBUF:BUF.GCLK13_U[1, 26, 29]
    CLK_REBUF:BUF.GCLK14_D[1, 26, 47]
    CLK_REBUF:BUF.GCLK14_U[1, 26, 45]
    CLK_REBUF:BUF.GCLK14_U.GCLK15_U[1, 27, 56]
    CLK_REBUF:BUF.GCLK15_D[1, 26, 63]
    CLK_REBUF:BUF.GCLK15_D.GCLK14_D[1, 27, 40]
    CLK_REBUF:BUF.GCLK15_U[1, 26, 61]
    CLK_REBUF:BUF.GCLK16_D[0, 27, 14]
    CLK_REBUF:BUF.GCLK16_U[0, 27, 12]
    CLK_REBUF:BUF.GCLK16_U.GCLK17_U[0, 26, 25]
    CLK_REBUF:BUF.GCLK17_D[0, 27, 30]
    CLK_REBUF:BUF.GCLK17_D.GCLK16_D[0, 26, 9]
    CLK_REBUF:BUF.GCLK17_U[0, 27, 28]
    CLK_REBUF:BUF.GCLK18_D[0, 27, 46]
    CLK_REBUF:BUF.GCLK18_U[0, 27, 44]
    CLK_REBUF:BUF.GCLK18_U.GCLK19_U[0, 26, 57]
    CLK_REBUF:BUF.GCLK19_D[0, 27, 62]
    CLK_REBUF:BUF.GCLK19_D.GCLK18_D[0, 26, 41]
    CLK_REBUF:BUF.GCLK19_U[0, 27, 60]
    CLK_REBUF:BUF.GCLK1_D[0, 27, 31]
    CLK_REBUF:BUF.GCLK1_D.GCLK0_D[0, 26, 8]
    CLK_REBUF:BUF.GCLK1_U[0, 27, 29]
    CLK_REBUF:BUF.GCLK20_D[1, 27, 14]
    CLK_REBUF:BUF.GCLK20_U[1, 27, 12]
    CLK_REBUF:BUF.GCLK20_U.GCLK21_U[1, 26, 25]
    CLK_REBUF:BUF.GCLK21_D[1, 27, 30]
    CLK_REBUF:BUF.GCLK21_D.GCLK20_D[1, 26, 9]
    CLK_REBUF:BUF.GCLK21_U[1, 27, 28]
    CLK_REBUF:BUF.GCLK22_D[1, 27, 46]
    CLK_REBUF:BUF.GCLK22_U[1, 27, 44]
    CLK_REBUF:BUF.GCLK22_U.GCLK23_U[1, 26, 57]
    CLK_REBUF:BUF.GCLK23_D[1, 27, 62]
    CLK_REBUF:BUF.GCLK23_D.GCLK22_D[1, 26, 41]
    CLK_REBUF:BUF.GCLK23_U[1, 27, 60]
    CLK_REBUF:BUF.GCLK24_D[0, 26, 14]
    CLK_REBUF:BUF.GCLK24_U[0, 26, 12]
    CLK_REBUF:BUF.GCLK24_U.GCLK25_U[0, 27, 25]
    CLK_REBUF:BUF.GCLK25_D[0, 26, 30]
    CLK_REBUF:BUF.GCLK25_D.GCLK24_D[0, 27, 9]
    CLK_REBUF:BUF.GCLK25_U[0, 26, 28]
    CLK_REBUF:BUF.GCLK26_D[0, 26, 46]
    CLK_REBUF:BUF.GCLK26_U[0, 26, 44]
    CLK_REBUF:BUF.GCLK26_U.GCLK27_U[0, 27, 57]
    CLK_REBUF:BUF.GCLK27_D[0, 26, 62]
    CLK_REBUF:BUF.GCLK27_D.GCLK26_D[0, 27, 41]
    CLK_REBUF:BUF.GCLK27_U[0, 26, 60]
    CLK_REBUF:BUF.GCLK28_D[1, 26, 14]
    CLK_REBUF:BUF.GCLK28_U[1, 26, 12]
    CLK_REBUF:BUF.GCLK28_U.GCLK29_U[1, 27, 25]
    CLK_REBUF:BUF.GCLK29_D[1, 26, 30]
    CLK_REBUF:BUF.GCLK29_D.GCLK28_D[1, 27, 9]
    CLK_REBUF:BUF.GCLK29_U[1, 26, 28]
    CLK_REBUF:BUF.GCLK2_D[0, 27, 47]
    CLK_REBUF:BUF.GCLK2_U[0, 27, 45]
    CLK_REBUF:BUF.GCLK2_U.GCLK3_U[0, 26, 56]
    CLK_REBUF:BUF.GCLK30_D[1, 26, 46]
    CLK_REBUF:BUF.GCLK30_U[1, 26, 44]
    CLK_REBUF:BUF.GCLK30_U.GCLK31_U[1, 27, 57]
    CLK_REBUF:BUF.GCLK31_D[1, 26, 62]
    CLK_REBUF:BUF.GCLK31_D.GCLK30_D[1, 27, 41]
    CLK_REBUF:BUF.GCLK31_U[1, 26, 60]
    CLK_REBUF:BUF.GCLK3_D[0, 27, 63]
    CLK_REBUF:BUF.GCLK3_D.GCLK2_D[0, 26, 40]
    CLK_REBUF:BUF.GCLK3_U[0, 27, 61]
    CLK_REBUF:BUF.GCLK4_D[1, 27, 15]
    CLK_REBUF:BUF.GCLK4_U[1, 27, 13]
    CLK_REBUF:BUF.GCLK4_U.GCLK5_U[1, 26, 24]
    CLK_REBUF:BUF.GCLK5_D[1, 27, 31]
    CLK_REBUF:BUF.GCLK5_D.GCLK4_D[1, 26, 8]
    CLK_REBUF:BUF.GCLK5_U[1, 27, 29]
    CLK_REBUF:BUF.GCLK6_D[1, 27, 47]
    CLK_REBUF:BUF.GCLK6_U[1, 27, 45]
    CLK_REBUF:BUF.GCLK6_U.GCLK7_U[1, 26, 56]
    CLK_REBUF:BUF.GCLK7_D[1, 27, 63]
    CLK_REBUF:BUF.GCLK7_D.GCLK6_D[1, 26, 40]
    CLK_REBUF:BUF.GCLK7_U[1, 27, 61]
    CLK_REBUF:BUF.GCLK8_D[0, 26, 15]
    CLK_REBUF:BUF.GCLK8_U[0, 26, 13]
    CLK_REBUF:BUF.GCLK8_U.GCLK9_U[0, 27, 24]
    CLK_REBUF:BUF.GCLK9_D[0, 26, 31]
    CLK_REBUF:BUF.GCLK9_D.GCLK8_D[0, 27, 8]
    CLK_REBUF:BUF.GCLK9_U[0, 26, 29]
    CLK_REBUF:ENABLE.GCLK0_D[0, 27, 3]
    CLK_REBUF:ENABLE.GCLK0_U[0, 27, 1]
    CLK_REBUF:ENABLE.GCLK10_D[0, 26, 35]
    CLK_REBUF:ENABLE.GCLK10_U[0, 26, 33]
    CLK_REBUF:ENABLE.GCLK11_D[0, 26, 51]
    CLK_REBUF:ENABLE.GCLK11_U[0, 26, 49]
    CLK_REBUF:ENABLE.GCLK12_D[1, 26, 3]
    CLK_REBUF:ENABLE.GCLK12_U[1, 26, 1]
    CLK_REBUF:ENABLE.GCLK13_D[1, 26, 19]
    CLK_REBUF:ENABLE.GCLK13_U[1, 26, 17]
    CLK_REBUF:ENABLE.GCLK14_D[1, 26, 35]
    CLK_REBUF:ENABLE.GCLK14_U[1, 26, 33]
    CLK_REBUF:ENABLE.GCLK15_D[1, 26, 51]
    CLK_REBUF:ENABLE.GCLK15_U[1, 26, 49]
    CLK_REBUF:ENABLE.GCLK16_D[0, 27, 2]
    CLK_REBUF:ENABLE.GCLK16_U[0, 27, 0]
    CLK_REBUF:ENABLE.GCLK17_D[0, 27, 18]
    CLK_REBUF:ENABLE.GCLK17_U[0, 27, 16]
    CLK_REBUF:ENABLE.GCLK18_D[0, 27, 34]
    CLK_REBUF:ENABLE.GCLK18_U[0, 27, 32]
    CLK_REBUF:ENABLE.GCLK19_D[0, 27, 50]
    CLK_REBUF:ENABLE.GCLK19_U[0, 27, 48]
    CLK_REBUF:ENABLE.GCLK1_D[0, 27, 19]
    CLK_REBUF:ENABLE.GCLK1_U[0, 27, 17]
    CLK_REBUF:ENABLE.GCLK20_D[1, 27, 2]
    CLK_REBUF:ENABLE.GCLK20_U[1, 27, 0]
    CLK_REBUF:ENABLE.GCLK21_D[1, 27, 18]
    CLK_REBUF:ENABLE.GCLK21_U[1, 27, 16]
    CLK_REBUF:ENABLE.GCLK22_D[1, 27, 34]
    CLK_REBUF:ENABLE.GCLK22_U[1, 27, 32]
    CLK_REBUF:ENABLE.GCLK23_D[1, 27, 50]
    CLK_REBUF:ENABLE.GCLK23_U[1, 27, 48]
    CLK_REBUF:ENABLE.GCLK24_D[0, 26, 2]
    CLK_REBUF:ENABLE.GCLK24_U[0, 26, 0]
    CLK_REBUF:ENABLE.GCLK25_D[0, 26, 18]
    CLK_REBUF:ENABLE.GCLK25_U[0, 26, 16]
    CLK_REBUF:ENABLE.GCLK26_D[0, 26, 34]
    CLK_REBUF:ENABLE.GCLK26_U[0, 26, 32]
    CLK_REBUF:ENABLE.GCLK27_D[0, 26, 50]
    CLK_REBUF:ENABLE.GCLK27_U[0, 26, 48]
    CLK_REBUF:ENABLE.GCLK28_D[1, 26, 2]
    CLK_REBUF:ENABLE.GCLK28_U[1, 26, 0]
    CLK_REBUF:ENABLE.GCLK29_D[1, 26, 18]
    CLK_REBUF:ENABLE.GCLK29_U[1, 26, 16]
    CLK_REBUF:ENABLE.GCLK2_D[0, 27, 35]
    CLK_REBUF:ENABLE.GCLK2_U[0, 27, 33]
    CLK_REBUF:ENABLE.GCLK30_D[1, 26, 34]
    CLK_REBUF:ENABLE.GCLK30_U[1, 26, 32]
    CLK_REBUF:ENABLE.GCLK31_D[1, 26, 50]
    CLK_REBUF:ENABLE.GCLK31_U[1, 26, 48]
    CLK_REBUF:ENABLE.GCLK3_D[0, 27, 51]
    CLK_REBUF:ENABLE.GCLK3_U[0, 27, 49]
    CLK_REBUF:ENABLE.GCLK4_D[1, 27, 3]
    CLK_REBUF:ENABLE.GCLK4_U[1, 27, 1]
    CLK_REBUF:ENABLE.GCLK5_D[1, 27, 19]
    CLK_REBUF:ENABLE.GCLK5_U[1, 27, 17]
    CLK_REBUF:ENABLE.GCLK6_D[1, 27, 35]
    CLK_REBUF:ENABLE.GCLK6_U[1, 27, 33]
    CLK_REBUF:ENABLE.GCLK7_D[1, 27, 51]
    CLK_REBUF:ENABLE.GCLK7_U[1, 27, 49]
    CLK_REBUF:ENABLE.GCLK8_D[0, 26, 3]
    CLK_REBUF:ENABLE.GCLK8_U[0, 26, 1]
    CLK_REBUF:ENABLE.GCLK9_D[0, 26, 19]
    CLK_REBUF:ENABLE.GCLK9_U[0, 26, 17]
    CLK_REBUF:INV.GCLK0_U.GCLK1_U[0, 26, 22]
    CLK_REBUF:INV.GCLK10_U.GCLK11_U[0, 27, 54]
    CLK_REBUF:INV.GCLK11_D.GCLK10_D[0, 27, 38]
    CLK_REBUF:INV.GCLK12_U.GCLK13_U[1, 27, 22]
    CLK_REBUF:INV.GCLK13_D.GCLK12_D[1, 27, 6]
    CLK_REBUF:INV.GCLK14_U.GCLK15_U[1, 27, 54]
    CLK_REBUF:INV.GCLK15_D.GCLK14_D[1, 27, 38]
    CLK_REBUF:INV.GCLK16_U.GCLK17_U[0, 26, 23]
    CLK_REBUF:INV.GCLK17_D.GCLK16_D[0, 26, 7]
    CLK_REBUF:INV.GCLK18_U.GCLK19_U[0, 26, 55]
    CLK_REBUF:INV.GCLK19_D.GCLK18_D[0, 26, 39]
    CLK_REBUF:INV.GCLK1_D.GCLK0_D[0, 26, 6]
    CLK_REBUF:INV.GCLK20_U.GCLK21_U[1, 26, 23]
    CLK_REBUF:INV.GCLK21_D.GCLK20_D[1, 26, 7]
    CLK_REBUF:INV.GCLK22_U.GCLK23_U[1, 26, 55]
    CLK_REBUF:INV.GCLK23_D.GCLK22_D[1, 26, 39]
    CLK_REBUF:INV.GCLK24_U.GCLK25_U[0, 27, 23]
    CLK_REBUF:INV.GCLK25_D.GCLK24_D[0, 27, 7]
    CLK_REBUF:INV.GCLK26_U.GCLK27_U[0, 27, 55]
    CLK_REBUF:INV.GCLK27_D.GCLK26_D[0, 27, 39]
    CLK_REBUF:INV.GCLK28_U.GCLK29_U[1, 27, 23]
    CLK_REBUF:INV.GCLK29_D.GCLK28_D[1, 27, 7]
    CLK_REBUF:INV.GCLK2_U.GCLK3_U[0, 26, 54]
    CLK_REBUF:INV.GCLK30_U.GCLK31_U[1, 27, 55]
    CLK_REBUF:INV.GCLK31_D.GCLK30_D[1, 27, 39]
    CLK_REBUF:INV.GCLK3_D.GCLK2_D[0, 26, 38]
    CLK_REBUF:INV.GCLK4_U.GCLK5_U[1, 26, 22]
    CLK_REBUF:INV.GCLK5_D.GCLK4_D[1, 26, 6]
    CLK_REBUF:INV.GCLK6_U.GCLK7_U[1, 26, 54]
    CLK_REBUF:INV.GCLK7_D.GCLK6_D[1, 26, 38]
    CLK_REBUF:INV.GCLK8_U.GCLK9_U[0, 27, 22]
    CLK_REBUF:INV.GCLK9_D.GCLK8_D[0, 27, 6]
    Non-inverted[0]
    +
    +
    +

    CLK_BALI_REBUF

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 0
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK0_UCLK_REBUF:ENABLE.GCLK16_U
    1--------------------------CLK_REBUF:ENABLE.GCLK0_DCLK_REBUF:ENABLE.GCLK16_D
    2--------------------------CLK_REBUF:INV.GCLK1_D.GCLK0_DCLK_REBUF:INV.GCLK17_D.GCLK16_D
    3--------------------------CLK_REBUF:BUF.GCLK1_D.GCLK0_DCLK_REBUF:BUF.GCLK17_D.GCLK16_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK0_UCLK_REBUF:BUF.GCLK16_U
    17--------------------------CLK_REBUF:BUF.GCLK0_DCLK_REBUF:BUF.GCLK16_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 1
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK1_UCLK_REBUF:ENABLE.GCLK17_U
    1--------------------------CLK_REBUF:ENABLE.GCLK1_DCLK_REBUF:ENABLE.GCLK17_D
    2--------------------------CLK_REBUF:INV.GCLK0_U.GCLK1_UCLK_REBUF:INV.GCLK16_U.GCLK17_U
    3--------------------------CLK_REBUF:BUF.GCLK0_U.GCLK1_UCLK_REBUF:BUF.GCLK16_U.GCLK17_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK1_UCLK_REBUF:BUF.GCLK17_U
    17--------------------------CLK_REBUF:BUF.GCLK1_DCLK_REBUF:BUF.GCLK17_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 2
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK8_UCLK_REBUF:ENABLE.GCLK24_U
    1--------------------------CLK_REBUF:ENABLE.GCLK8_DCLK_REBUF:ENABLE.GCLK24_D
    2--------------------------CLK_REBUF:INV.GCLK9_D.GCLK8_DCLK_REBUF:INV.GCLK25_D.GCLK24_D
    3--------------------------CLK_REBUF:BUF.GCLK9_D.GCLK8_DCLK_REBUF:BUF.GCLK25_D.GCLK24_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK8_UCLK_REBUF:BUF.GCLK24_U
    17--------------------------CLK_REBUF:BUF.GCLK8_DCLK_REBUF:BUF.GCLK24_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 3
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK9_UCLK_REBUF:ENABLE.GCLK25_U
    1--------------------------CLK_REBUF:ENABLE.GCLK9_DCLK_REBUF:ENABLE.GCLK25_D
    2--------------------------CLK_REBUF:INV.GCLK8_U.GCLK9_UCLK_REBUF:INV.GCLK24_U.GCLK25_U
    3--------------------------CLK_REBUF:BUF.GCLK8_U.GCLK9_UCLK_REBUF:BUF.GCLK24_U.GCLK25_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK9_UCLK_REBUF:BUF.GCLK25_U
    17--------------------------CLK_REBUF:BUF.GCLK9_DCLK_REBUF:BUF.GCLK25_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 4
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK2_UCLK_REBUF:ENABLE.GCLK18_U
    1--------------------------CLK_REBUF:ENABLE.GCLK2_DCLK_REBUF:ENABLE.GCLK18_D
    2--------------------------CLK_REBUF:INV.GCLK3_D.GCLK2_DCLK_REBUF:INV.GCLK19_D.GCLK18_D
    3--------------------------CLK_REBUF:BUF.GCLK3_D.GCLK2_DCLK_REBUF:BUF.GCLK19_D.GCLK18_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK2_UCLK_REBUF:BUF.GCLK18_U
    17--------------------------CLK_REBUF:BUF.GCLK2_DCLK_REBUF:BUF.GCLK18_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 5
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK3_UCLK_REBUF:ENABLE.GCLK19_U
    1--------------------------CLK_REBUF:ENABLE.GCLK3_DCLK_REBUF:ENABLE.GCLK19_D
    2--------------------------CLK_REBUF:INV.GCLK2_U.GCLK3_UCLK_REBUF:INV.GCLK18_U.GCLK19_U
    3--------------------------CLK_REBUF:BUF.GCLK2_U.GCLK3_UCLK_REBUF:BUF.GCLK18_U.GCLK19_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK3_UCLK_REBUF:BUF.GCLK19_U
    17--------------------------CLK_REBUF:BUF.GCLK3_DCLK_REBUF:BUF.GCLK19_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 6
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK10_UCLK_REBUF:ENABLE.GCLK26_U
    1--------------------------CLK_REBUF:ENABLE.GCLK10_DCLK_REBUF:ENABLE.GCLK26_D
    2--------------------------CLK_REBUF:INV.GCLK11_D.GCLK10_DCLK_REBUF:INV.GCLK27_D.GCLK26_D
    3--------------------------CLK_REBUF:BUF.GCLK11_D.GCLK10_DCLK_REBUF:BUF.GCLK27_D.GCLK26_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK10_UCLK_REBUF:BUF.GCLK26_U
    17--------------------------CLK_REBUF:BUF.GCLK10_DCLK_REBUF:BUF.GCLK26_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 7
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK11_UCLK_REBUF:ENABLE.GCLK27_U
    1--------------------------CLK_REBUF:ENABLE.GCLK11_DCLK_REBUF:ENABLE.GCLK27_D
    2--------------------------CLK_REBUF:INV.GCLK10_U.GCLK11_UCLK_REBUF:INV.GCLK26_U.GCLK27_U
    3--------------------------CLK_REBUF:BUF.GCLK10_U.GCLK11_UCLK_REBUF:BUF.GCLK26_U.GCLK27_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK11_UCLK_REBUF:BUF.GCLK27_U
    17--------------------------CLK_REBUF:BUF.GCLK11_DCLK_REBUF:BUF.GCLK27_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 8
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK4_UCLK_REBUF:ENABLE.GCLK20_U
    1--------------------------CLK_REBUF:ENABLE.GCLK4_DCLK_REBUF:ENABLE.GCLK20_D
    2--------------------------CLK_REBUF:INV.GCLK5_D.GCLK4_DCLK_REBUF:INV.GCLK21_D.GCLK20_D
    3--------------------------CLK_REBUF:BUF.GCLK5_D.GCLK4_DCLK_REBUF:BUF.GCLK21_D.GCLK20_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK4_UCLK_REBUF:BUF.GCLK20_U
    17--------------------------CLK_REBUF:BUF.GCLK4_DCLK_REBUF:BUF.GCLK20_D
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    CLK_BALI_REBUF bittile 9
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK5_UCLK_REBUF:ENABLE.GCLK21_U
    1--------------------------CLK_REBUF:ENABLE.GCLK5_DCLK_REBUF:ENABLE.GCLK21_D
    2--------------------------CLK_REBUF:INV.GCLK4_U.GCLK5_UCLK_REBUF:INV.GCLK20_U.GCLK21_U
    3--------------------------CLK_REBUF:BUF.GCLK4_U.GCLK5_UCLK_REBUF:BUF.GCLK20_U.GCLK21_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK5_UCLK_REBUF:BUF.GCLK21_U
    17--------------------------CLK_REBUF:BUF.GCLK5_DCLK_REBUF:BUF.GCLK21_D
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    CLK_BALI_REBUF bittile 10
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK12_UCLK_REBUF:ENABLE.GCLK28_U
    1--------------------------CLK_REBUF:ENABLE.GCLK12_DCLK_REBUF:ENABLE.GCLK28_D
    2--------------------------CLK_REBUF:INV.GCLK13_D.GCLK12_DCLK_REBUF:INV.GCLK29_D.GCLK28_D
    3--------------------------CLK_REBUF:BUF.GCLK13_D.GCLK12_DCLK_REBUF:BUF.GCLK29_D.GCLK28_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK12_UCLK_REBUF:BUF.GCLK28_U
    17--------------------------CLK_REBUF:BUF.GCLK12_DCLK_REBUF:BUF.GCLK28_D
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    CLK_BALI_REBUF bittile 11
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK13_UCLK_REBUF:ENABLE.GCLK29_U
    1--------------------------CLK_REBUF:ENABLE.GCLK13_DCLK_REBUF:ENABLE.GCLK29_D
    2--------------------------CLK_REBUF:INV.GCLK12_U.GCLK13_UCLK_REBUF:INV.GCLK28_U.GCLK29_U
    3--------------------------CLK_REBUF:BUF.GCLK12_U.GCLK13_UCLK_REBUF:BUF.GCLK28_U.GCLK29_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK13_UCLK_REBUF:BUF.GCLK29_U
    17--------------------------CLK_REBUF:BUF.GCLK13_DCLK_REBUF:BUF.GCLK29_D
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    CLK_BALI_REBUF bittile 12
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK6_UCLK_REBUF:ENABLE.GCLK22_U
    1--------------------------CLK_REBUF:ENABLE.GCLK6_DCLK_REBUF:ENABLE.GCLK22_D
    2--------------------------CLK_REBUF:INV.GCLK7_D.GCLK6_DCLK_REBUF:INV.GCLK23_D.GCLK22_D
    3--------------------------CLK_REBUF:BUF.GCLK7_D.GCLK6_DCLK_REBUF:BUF.GCLK23_D.GCLK22_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK6_UCLK_REBUF:BUF.GCLK22_U
    17--------------------------CLK_REBUF:BUF.GCLK6_DCLK_REBUF:BUF.GCLK22_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 13
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK7_UCLK_REBUF:ENABLE.GCLK23_U
    1--------------------------CLK_REBUF:ENABLE.GCLK7_DCLK_REBUF:ENABLE.GCLK23_D
    2--------------------------CLK_REBUF:INV.GCLK6_U.GCLK7_UCLK_REBUF:INV.GCLK22_U.GCLK23_U
    3--------------------------CLK_REBUF:BUF.GCLK6_U.GCLK7_UCLK_REBUF:BUF.GCLK22_U.GCLK23_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK7_UCLK_REBUF:BUF.GCLK23_U
    17--------------------------CLK_REBUF:BUF.GCLK7_DCLK_REBUF:BUF.GCLK23_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 14
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK14_UCLK_REBUF:ENABLE.GCLK30_U
    1--------------------------CLK_REBUF:ENABLE.GCLK14_DCLK_REBUF:ENABLE.GCLK30_D
    2--------------------------CLK_REBUF:INV.GCLK15_D.GCLK14_DCLK_REBUF:INV.GCLK31_D.GCLK30_D
    3--------------------------CLK_REBUF:BUF.GCLK15_D.GCLK14_DCLK_REBUF:BUF.GCLK31_D.GCLK30_D
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK14_UCLK_REBUF:BUF.GCLK30_U
    17--------------------------CLK_REBUF:BUF.GCLK14_DCLK_REBUF:BUF.GCLK30_D
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CLK_BALI_REBUF bittile 15
    RowColumn
    0123456789101112131415161718192021222324252627
    0--------------------------CLK_REBUF:ENABLE.GCLK15_UCLK_REBUF:ENABLE.GCLK31_U
    1--------------------------CLK_REBUF:ENABLE.GCLK15_DCLK_REBUF:ENABLE.GCLK31_D
    2--------------------------CLK_REBUF:INV.GCLK14_U.GCLK15_UCLK_REBUF:INV.GCLK30_U.GCLK31_U
    3--------------------------CLK_REBUF:BUF.GCLK14_U.GCLK15_UCLK_REBUF:BUF.GCLK30_U.GCLK31_U
    4----------------------------
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16--------------------------CLK_REBUF:BUF.GCLK15_UCLK_REBUF:BUF.GCLK31_U
    17--------------------------CLK_REBUF:BUF.GCLK15_DCLK_REBUF:BUF.GCLK31_D
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    CLK_REBUF:BUF.GCLK0_D[0, 26, 17]
    CLK_REBUF:BUF.GCLK0_U[0, 26, 16]
    CLK_REBUF:BUF.GCLK0_U.GCLK1_U[1, 26, 3]
    CLK_REBUF:BUF.GCLK10_D[6, 26, 17]
    CLK_REBUF:BUF.GCLK10_U[6, 26, 16]
    CLK_REBUF:BUF.GCLK10_U.GCLK11_U[7, 26, 3]
    CLK_REBUF:BUF.GCLK11_D[7, 26, 17]
    CLK_REBUF:BUF.GCLK11_D.GCLK10_D[6, 26, 3]
    CLK_REBUF:BUF.GCLK11_U[7, 26, 16]
    CLK_REBUF:BUF.GCLK12_D[10, 26, 17]
    CLK_REBUF:BUF.GCLK12_U[10, 26, 16]
    CLK_REBUF:BUF.GCLK12_U.GCLK13_U[11, 26, 3]
    CLK_REBUF:BUF.GCLK13_D[11, 26, 17]
    CLK_REBUF:BUF.GCLK13_D.GCLK12_D[10, 26, 3]
    CLK_REBUF:BUF.GCLK13_U[11, 26, 16]
    CLK_REBUF:BUF.GCLK14_D[14, 26, 17]
    CLK_REBUF:BUF.GCLK14_U[14, 26, 16]
    CLK_REBUF:BUF.GCLK14_U.GCLK15_U[15, 26, 3]
    CLK_REBUF:BUF.GCLK15_D[15, 26, 17]
    CLK_REBUF:BUF.GCLK15_D.GCLK14_D[14, 26, 3]
    CLK_REBUF:BUF.GCLK15_U[15, 26, 16]
    CLK_REBUF:BUF.GCLK16_D[0, 27, 17]
    CLK_REBUF:BUF.GCLK16_U[0, 27, 16]
    CLK_REBUF:BUF.GCLK16_U.GCLK17_U[1, 27, 3]
    CLK_REBUF:BUF.GCLK17_D[1, 27, 17]
    CLK_REBUF:BUF.GCLK17_D.GCLK16_D[0, 27, 3]
    CLK_REBUF:BUF.GCLK17_U[1, 27, 16]
    CLK_REBUF:BUF.GCLK18_D[4, 27, 17]
    CLK_REBUF:BUF.GCLK18_U[4, 27, 16]
    CLK_REBUF:BUF.GCLK18_U.GCLK19_U[5, 27, 3]
    CLK_REBUF:BUF.GCLK19_D[5, 27, 17]
    CLK_REBUF:BUF.GCLK19_D.GCLK18_D[4, 27, 3]
    CLK_REBUF:BUF.GCLK19_U[5, 27, 16]
    CLK_REBUF:BUF.GCLK1_D[1, 26, 17]
    CLK_REBUF:BUF.GCLK1_D.GCLK0_D[0, 26, 3]
    CLK_REBUF:BUF.GCLK1_U[1, 26, 16]
    CLK_REBUF:BUF.GCLK20_D[8, 27, 17]
    CLK_REBUF:BUF.GCLK20_U[8, 27, 16]
    CLK_REBUF:BUF.GCLK20_U.GCLK21_U[9, 27, 3]
    CLK_REBUF:BUF.GCLK21_D[9, 27, 17]
    CLK_REBUF:BUF.GCLK21_D.GCLK20_D[8, 27, 3]
    CLK_REBUF:BUF.GCLK21_U[9, 27, 16]
    CLK_REBUF:BUF.GCLK22_D[12, 27, 17]
    CLK_REBUF:BUF.GCLK22_U[12, 27, 16]
    CLK_REBUF:BUF.GCLK22_U.GCLK23_U[13, 27, 3]
    CLK_REBUF:BUF.GCLK23_D[13, 27, 17]
    CLK_REBUF:BUF.GCLK23_D.GCLK22_D[12, 27, 3]
    CLK_REBUF:BUF.GCLK23_U[13, 27, 16]
    CLK_REBUF:BUF.GCLK24_D[2, 27, 17]
    CLK_REBUF:BUF.GCLK24_U[2, 27, 16]
    CLK_REBUF:BUF.GCLK24_U.GCLK25_U[3, 27, 3]
    CLK_REBUF:BUF.GCLK25_D[3, 27, 17]
    CLK_REBUF:BUF.GCLK25_D.GCLK24_D[2, 27, 3]
    CLK_REBUF:BUF.GCLK25_U[3, 27, 16]
    CLK_REBUF:BUF.GCLK26_D[6, 27, 17]
    CLK_REBUF:BUF.GCLK26_U[6, 27, 16]
    CLK_REBUF:BUF.GCLK26_U.GCLK27_U[7, 27, 3]
    CLK_REBUF:BUF.GCLK27_D[7, 27, 17]
    CLK_REBUF:BUF.GCLK27_D.GCLK26_D[6, 27, 3]
    CLK_REBUF:BUF.GCLK27_U[7, 27, 16]
    CLK_REBUF:BUF.GCLK28_D[10, 27, 17]
    CLK_REBUF:BUF.GCLK28_U[10, 27, 16]
    CLK_REBUF:BUF.GCLK28_U.GCLK29_U[11, 27, 3]
    CLK_REBUF:BUF.GCLK29_D[11, 27, 17]
    CLK_REBUF:BUF.GCLK29_D.GCLK28_D[10, 27, 3]
    CLK_REBUF:BUF.GCLK29_U[11, 27, 16]
    CLK_REBUF:BUF.GCLK2_D[4, 26, 17]
    CLK_REBUF:BUF.GCLK2_U[4, 26, 16]
    CLK_REBUF:BUF.GCLK2_U.GCLK3_U[5, 26, 3]
    CLK_REBUF:BUF.GCLK30_D[14, 27, 17]
    CLK_REBUF:BUF.GCLK30_U[14, 27, 16]
    CLK_REBUF:BUF.GCLK30_U.GCLK31_U[15, 27, 3]
    CLK_REBUF:BUF.GCLK31_D[15, 27, 17]
    CLK_REBUF:BUF.GCLK31_D.GCLK30_D[14, 27, 3]
    CLK_REBUF:BUF.GCLK31_U[15, 27, 16]
    CLK_REBUF:BUF.GCLK3_D[5, 26, 17]
    CLK_REBUF:BUF.GCLK3_D.GCLK2_D[4, 26, 3]
    CLK_REBUF:BUF.GCLK3_U[5, 26, 16]
    CLK_REBUF:BUF.GCLK4_D[8, 26, 17]
    CLK_REBUF:BUF.GCLK4_U[8, 26, 16]
    CLK_REBUF:BUF.GCLK4_U.GCLK5_U[9, 26, 3]
    CLK_REBUF:BUF.GCLK5_D[9, 26, 17]
    CLK_REBUF:BUF.GCLK5_D.GCLK4_D[8, 26, 3]
    CLK_REBUF:BUF.GCLK5_U[9, 26, 16]
    CLK_REBUF:BUF.GCLK6_D[12, 26, 17]
    CLK_REBUF:BUF.GCLK6_U[12, 26, 16]
    CLK_REBUF:BUF.GCLK6_U.GCLK7_U[13, 26, 3]
    CLK_REBUF:BUF.GCLK7_D[13, 26, 17]
    CLK_REBUF:BUF.GCLK7_D.GCLK6_D[12, 26, 3]
    CLK_REBUF:BUF.GCLK7_U[13, 26, 16]
    CLK_REBUF:BUF.GCLK8_D[2, 26, 17]
    CLK_REBUF:BUF.GCLK8_U[2, 26, 16]
    CLK_REBUF:BUF.GCLK8_U.GCLK9_U[3, 26, 3]
    CLK_REBUF:BUF.GCLK9_D[3, 26, 17]
    CLK_REBUF:BUF.GCLK9_D.GCLK8_D[2, 26, 3]
    CLK_REBUF:BUF.GCLK9_U[3, 26, 16]
    CLK_REBUF:ENABLE.GCLK0_D[0, 26, 1]
    CLK_REBUF:ENABLE.GCLK0_U[0, 26, 0]
    CLK_REBUF:ENABLE.GCLK10_D[6, 26, 1]
    CLK_REBUF:ENABLE.GCLK10_U[6, 26, 0]
    CLK_REBUF:ENABLE.GCLK11_D[7, 26, 1]
    CLK_REBUF:ENABLE.GCLK11_U[7, 26, 0]
    CLK_REBUF:ENABLE.GCLK12_D[10, 26, 1]
    CLK_REBUF:ENABLE.GCLK12_U[10, 26, 0]
    CLK_REBUF:ENABLE.GCLK13_D[11, 26, 1]
    CLK_REBUF:ENABLE.GCLK13_U[11, 26, 0]
    CLK_REBUF:ENABLE.GCLK14_D[14, 26, 1]
    CLK_REBUF:ENABLE.GCLK14_U[14, 26, 0]
    CLK_REBUF:ENABLE.GCLK15_D[15, 26, 1]
    CLK_REBUF:ENABLE.GCLK15_U[15, 26, 0]
    CLK_REBUF:ENABLE.GCLK16_D[0, 27, 1]
    CLK_REBUF:ENABLE.GCLK16_U[0, 27, 0]
    CLK_REBUF:ENABLE.GCLK17_D[1, 27, 1]
    CLK_REBUF:ENABLE.GCLK17_U[1, 27, 0]
    CLK_REBUF:ENABLE.GCLK18_D[4, 27, 1]
    CLK_REBUF:ENABLE.GCLK18_U[4, 27, 0]
    CLK_REBUF:ENABLE.GCLK19_D[5, 27, 1]
    CLK_REBUF:ENABLE.GCLK19_U[5, 27, 0]
    CLK_REBUF:ENABLE.GCLK1_D[1, 26, 1]
    CLK_REBUF:ENABLE.GCLK1_U[1, 26, 0]
    CLK_REBUF:ENABLE.GCLK20_D[8, 27, 1]
    CLK_REBUF:ENABLE.GCLK20_U[8, 27, 0]
    CLK_REBUF:ENABLE.GCLK21_D[9, 27, 1]
    CLK_REBUF:ENABLE.GCLK21_U[9, 27, 0]
    CLK_REBUF:ENABLE.GCLK22_D[12, 27, 1]
    CLK_REBUF:ENABLE.GCLK22_U[12, 27, 0]
    CLK_REBUF:ENABLE.GCLK23_D[13, 27, 1]
    CLK_REBUF:ENABLE.GCLK23_U[13, 27, 0]
    CLK_REBUF:ENABLE.GCLK24_D[2, 27, 1]
    CLK_REBUF:ENABLE.GCLK24_U[2, 27, 0]
    CLK_REBUF:ENABLE.GCLK25_D[3, 27, 1]
    CLK_REBUF:ENABLE.GCLK25_U[3, 27, 0]
    CLK_REBUF:ENABLE.GCLK26_D[6, 27, 1]
    CLK_REBUF:ENABLE.GCLK26_U[6, 27, 0]
    CLK_REBUF:ENABLE.GCLK27_D[7, 27, 1]
    CLK_REBUF:ENABLE.GCLK27_U[7, 27, 0]
    CLK_REBUF:ENABLE.GCLK28_D[10, 27, 1]
    CLK_REBUF:ENABLE.GCLK28_U[10, 27, 0]
    CLK_REBUF:ENABLE.GCLK29_D[11, 27, 1]
    CLK_REBUF:ENABLE.GCLK29_U[11, 27, 0]
    CLK_REBUF:ENABLE.GCLK2_D[4, 26, 1]
    CLK_REBUF:ENABLE.GCLK2_U[4, 26, 0]
    CLK_REBUF:ENABLE.GCLK30_D[14, 27, 1]
    CLK_REBUF:ENABLE.GCLK30_U[14, 27, 0]
    CLK_REBUF:ENABLE.GCLK31_D[15, 27, 1]
    CLK_REBUF:ENABLE.GCLK31_U[15, 27, 0]
    CLK_REBUF:ENABLE.GCLK3_D[5, 26, 1]
    CLK_REBUF:ENABLE.GCLK3_U[5, 26, 0]
    CLK_REBUF:ENABLE.GCLK4_D[8, 26, 1]
    CLK_REBUF:ENABLE.GCLK4_U[8, 26, 0]
    CLK_REBUF:ENABLE.GCLK5_D[9, 26, 1]
    CLK_REBUF:ENABLE.GCLK5_U[9, 26, 0]
    CLK_REBUF:ENABLE.GCLK6_D[12, 26, 1]
    CLK_REBUF:ENABLE.GCLK6_U[12, 26, 0]
    CLK_REBUF:ENABLE.GCLK7_D[13, 26, 1]
    CLK_REBUF:ENABLE.GCLK7_U[13, 26, 0]
    CLK_REBUF:ENABLE.GCLK8_D[2, 26, 1]
    CLK_REBUF:ENABLE.GCLK8_U[2, 26, 0]
    CLK_REBUF:ENABLE.GCLK9_D[3, 26, 1]
    CLK_REBUF:ENABLE.GCLK9_U[3, 26, 0]
    CLK_REBUF:INV.GCLK0_U.GCLK1_U[1, 26, 2]
    CLK_REBUF:INV.GCLK10_U.GCLK11_U[7, 26, 2]
    CLK_REBUF:INV.GCLK11_D.GCLK10_D[6, 26, 2]
    CLK_REBUF:INV.GCLK12_U.GCLK13_U[11, 26, 2]
    CLK_REBUF:INV.GCLK13_D.GCLK12_D[10, 26, 2]
    CLK_REBUF:INV.GCLK14_U.GCLK15_U[15, 26, 2]
    CLK_REBUF:INV.GCLK15_D.GCLK14_D[14, 26, 2]
    CLK_REBUF:INV.GCLK16_U.GCLK17_U[1, 27, 2]
    CLK_REBUF:INV.GCLK17_D.GCLK16_D[0, 27, 2]
    CLK_REBUF:INV.GCLK18_U.GCLK19_U[5, 27, 2]
    CLK_REBUF:INV.GCLK19_D.GCLK18_D[4, 27, 2]
    CLK_REBUF:INV.GCLK1_D.GCLK0_D[0, 26, 2]
    CLK_REBUF:INV.GCLK20_U.GCLK21_U[9, 27, 2]
    CLK_REBUF:INV.GCLK21_D.GCLK20_D[8, 27, 2]
    CLK_REBUF:INV.GCLK22_U.GCLK23_U[13, 27, 2]
    CLK_REBUF:INV.GCLK23_D.GCLK22_D[12, 27, 2]
    CLK_REBUF:INV.GCLK24_U.GCLK25_U[3, 27, 2]
    CLK_REBUF:INV.GCLK25_D.GCLK24_D[2, 27, 2]
    CLK_REBUF:INV.GCLK26_U.GCLK27_U[7, 27, 2]
    CLK_REBUF:INV.GCLK27_D.GCLK26_D[6, 27, 2]
    CLK_REBUF:INV.GCLK28_U.GCLK29_U[11, 27, 2]
    CLK_REBUF:INV.GCLK29_D.GCLK28_D[10, 27, 2]
    CLK_REBUF:INV.GCLK2_U.GCLK3_U[5, 26, 2]
    CLK_REBUF:INV.GCLK30_U.GCLK31_U[15, 27, 2]
    CLK_REBUF:INV.GCLK31_D.GCLK30_D[14, 27, 2]
    CLK_REBUF:INV.GCLK3_D.GCLK2_D[4, 26, 2]
    CLK_REBUF:INV.GCLK4_U.GCLK5_U[9, 26, 2]
    CLK_REBUF:INV.GCLK5_D.GCLK4_D[8, 26, 2]
    CLK_REBUF:INV.GCLK6_U.GCLK7_U[13, 26, 2]
    CLK_REBUF:INV.GCLK7_D.GCLK6_D[12, 26, 2]
    CLK_REBUF:INV.GCLK8_U.GCLK9_U[3, 26, 2]
    CLK_REBUF:INV.GCLK9_D.GCLK8_D[2, 26, 2]
    Non-inverted[0]
    +
    + + + + + + + + + + + + + + \ No newline at end of file diff --git a/xilinx/virtex7/cmt.html b/xilinx/virtex7/cmt.html new file mode 100644 index 00000000..c6dc9153 --- /dev/null +++ b/xilinx/virtex7/cmt.html @@ -0,0 +1,681 @@ + + + + + + + Clock management tile — Project Combine documentation + + + + + + + + + + + + + + + + + +
    + + +
    + +
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    + +
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    +
    + +
    +

    Clock management tile

    +
    +

    Todo

    +

    describe this madness

    +
    +
    +

    CMT

    + + +
    CMT bittile 0
    RowColumn
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    CMT bittile 1
    RowColumn
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    CMT bittile 2
    RowColumn
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    CMT bittile 3
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    CMT bittile 4
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    CMT bittile 5
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    CMT bittile 6
    RowColumn
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    CMT bittile 7
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    CMT bittile 8
    RowColumn
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    CMT bittile 9
    RowColumn
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    CMT bittile 10
    RowColumn
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    CMT bittile 11
    RowColumn
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    CMT bittile 12
    RowColumn
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    CMT bittile 13
    RowColumn
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    CMT bittile 14
    RowColumn
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    CMT bittile 15
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    CMT bittile 16
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    CMT bittile 17
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    CMT bittile 18
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    CMT bittile 19
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    CMT bittile 20
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    CMT bittile 21
    RowColumn
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    CMT bittile 22
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    CMT bittile 23
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    CMT bittile 24
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    CMT bittile 25
    RowColumn
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    CMT bittile 26
    RowColumn
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    CMT bittile 27
    RowColumn
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    CMT bittile 28
    RowColumn
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    CMT bittile 29
    RowColumn
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    CMT bittile 30
    RowColumn
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    CMT bittile 31
    RowColumn
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    CMT bittile 32
    RowColumn
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    CMT bittile 33
    RowColumn
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    CMT bittile 34
    RowColumn
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    CMT bittile 35
    RowColumn
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    CMT bittile 36
    RowColumn
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    CMT bittile 37
    RowColumn
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    CMT bittile 38
    RowColumn
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    CMT bittile 39
    RowColumn
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    CMT bittile 40
    RowColumn
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    CMT bittile 41
    RowColumn
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    CMT bittile 42
    RowColumn
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    CMT bittile 43
    RowColumn
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    CMT bittile 44
    RowColumn
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    CMT bittile 45
    RowColumn
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    CMT bittile 46
    RowColumn
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    CMT bittile 47
    RowColumn
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    CMT bittile 48
    RowColumn
    + + +
    CMT bittile 49
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT bittile 50
    RowColumn
    01234567891011121314151617181920212223242526272829
    0------------------------------
    1------------------------------
    2------------------------------
    3------------------------------
    4------------------------------
    5------------------------------
    6------------------------------
    7------------------------------
    8------------------------------
    9------------------------------
    10------------------------------
    11------------------------------
    12------------------------------
    13------------------------------
    14----------------------------CMT:ENABLE.RCLK0CMT:ENABLE.RCLK1
    15----------------------------CMT:ENABLE.RCLK2CMT:ENABLE.RCLK3
    +
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    + + + + + + +
    CMT:ENABLE.RCLK0[50, 28, 14]
    CMT:ENABLE.RCLK1[50, 29, 14]
    CMT:ENABLE.RCLK2[50, 28, 15]
    CMT:ENABLE.RCLK3[50, 29, 15]
    Non-inverted[0]
    +
    +
    +

    CMT_FIFO

    + + +
    CMT_FIFO bittile 0
    RowColumn
    + + +
    CMT_FIFO bittile 1
    RowColumn
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    CMT_FIFO bittile 2
    RowColumn
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    CMT_FIFO bittile 3
    RowColumn
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    CMT_FIFO bittile 4
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    CMT_FIFO bittile 5
    RowColumn
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT_FIFO bittile 6
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1--------------------------OUT_FIFO:OUTPUT_DISABLEOUT_FIFO:SPARE[0]
    2--------------------------OUT_FIFO:SPARE[1]OUT_FIFO:SPARE[2]
    3--------------------------OUT_FIFO:SLOW_WR_CLKOUT_FIFO:SYNCHRONOUS_MODE
    4--------------------------OUT_FIFO:SLOW_RD_CLKOUT_FIFO:ARRAY_MODE
    5--------------------------OUT_FIFO:SPARE[3]-
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16----------------------------
    17----------------------------
    18----------------------------
    19----------------------------
    20----------------------------
    21----------------------------
    22----------------------------
    23----------------------------
    24----------------------------
    25----------------------------
    26----------------------------
    27----------------------------
    28----------------------------
    29---------------------------OUT_FIFO:MUX.RDEN
    30--------------------------OUT_FIFO:ALMOST_FULL_VALUE[0]OUT_FIFO:ALMOST_FULL_VALUE[2]
    31----------------------------
    32---------------------------OUT_FIFO:ALMOST_FULL_VALUE[3]
    33--------------------------OUT_FIFO:ALMOST_FULL_VALUE[1]-
    34--------------------------OUT_FIFO:MUX.RDCLK-
    35----------------------------
    36----------------------------
    37----------------------------
    38----------------------------
    39----------------------------
    40----------------------------
    41----------------------------
    42----------------------------
    43----------------------------
    44----------------------------
    45----------------------------
    46----------------------------
    47----------------------------
    48----------------------------
    49----------------------------
    50----------------------------
    51----------------------------
    52----------------------------
    53----------------------------
    54----------------------------
    55----------------------------
    56----------------------------
    57----------------------------
    58--------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[0]OUT_FIFO:ALMOST_EMPTY_VALUE[2]
    59----------------------------
    60---------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[3]
    61--------------------------OUT_FIFO:ALMOST_EMPTY_VALUE[1]-
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    CMT_FIFO bittile 7
    RowColumn
    0123456789101112131415161718192021222324252627
    0----------------------------
    1--------------------------IN_FIFO:SPARE[0]IN_FIFO:SPARE[1]
    2--------------------------IN_FIFO:SPARE[2]IN_FIFO:SLOW_WR_CLK
    3--------------------------IN_FIFO:SYNCHRONOUS_MODEIN_FIFO:SLOW_RD_CLK
    4--------------------------IN_FIFO:ARRAY_MODEIN_FIFO:SPARE[3]
    5----------------------------
    6----------------------------
    7----------------------------
    8----------------------------
    9----------------------------
    10----------------------------
    11----------------------------
    12----------------------------
    13----------------------------
    14----------------------------
    15----------------------------
    16----------------------------
    17----------------------------
    18----------------------------
    19----------------------------
    20----------------------------
    21----------------------------
    22----------------------------
    23----------------------------
    24----------------------------
    25----------------------------
    26----------------------------
    27----------------------------
    28----------------------------
    29---------------------------IN_FIFO:MUX.WREN
    30--------------------------IN_FIFO:ALMOST_FULL_VALUE[0]IN_FIFO:ALMOST_FULL_VALUE[2]
    31----------------------------
    32---------------------------IN_FIFO:ALMOST_FULL_VALUE[3]
    33--------------------------IN_FIFO:ALMOST_FULL_VALUE[1]-
    34--------------------------IN_FIFO:MUX.WRCLK-
    35----------------------------
    36----------------------------
    37----------------------------
    38----------------------------
    39----------------------------
    40----------------------------
    41----------------------------
    42----------------------------
    43----------------------------
    44----------------------------
    45----------------------------
    46----------------------------
    47----------------------------
    48----------------------------
    49----------------------------
    50----------------------------
    51----------------------------
    52----------------------------
    53----------------------------
    54----------------------------
    55----------------------------
    56----------------------------
    57----------------------------
    58--------------------------IN_FIFO:ALMOST_EMPTY_VALUE[0]IN_FIFO:ALMOST_EMPTY_VALUE[2]
    59----------------------------
    60---------------------------IN_FIFO:ALMOST_EMPTY_VALUE[3]
    61--------------------------IN_FIFO:ALMOST_EMPTY_VALUE[1]-
    +
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    IN_FIFO:SLOW_RD_CLK[7, 27, 3]
    IN_FIFO:SLOW_WR_CLK[7, 27, 2]
    IN_FIFO:SYNCHRONOUS_MODE[7, 26, 3]
    OUT_FIFO:OUTPUT_DISABLE[6, 26, 1]
    OUT_FIFO:SLOW_RD_CLK[6, 26, 4]
    OUT_FIFO:SLOW_WR_CLK[6, 26, 3]
    OUT_FIFO:SYNCHRONOUS_MODE[6, 27, 3]
    Non-inverted[0]
    +
    +
    +
    +
    + + + + + + + + +
    IN_FIFO:ALMOST_EMPTY_VALUE[7, 27, 60][7, 27, 58][7, 26, 61][7, 26, 58]
    IN_FIFO:ALMOST_FULL_VALUE[7, 27, 32][7, 27, 30][7, 26, 33][7, 26, 30]
    OUT_FIFO:ALMOST_EMPTY_VALUE[6, 27, 60][6, 27, 58][6, 26, 61][6, 26, 58]
    OUT_FIFO:ALMOST_FULL_VALUE[6, 27, 32][6, 27, 30][6, 26, 33][6, 26, 30]
    NONE0000
    10011
    21111
    +
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    + + + + + + + +
    IN_FIFO:MUX.WRCLK[7, 26, 34]
    IN_FIFO:MUX.WREN[7, 27, 29]
    OUT_FIFO:MUX.RDCLK[6, 26, 34]
    OUT_FIFO:MUX.RDEN[6, 27, 29]
    INT0
    PHASER1
    +
    +
    + + + + +
    IN_FIFO:SPARE[7, 27, 4][7, 26, 2][7, 27, 1][7, 26, 1]
    OUT_FIFO:SPARE[6, 26, 5][6, 27, 2][6, 26, 2][6, 27, 1]
    Non-inverted[3][2][1][0]
    +
    + + + + +
    OUT_FIFO:ARRAY_MODE[6, 27, 4]
    ARRAY_MODE_4_X_40
    ARRAY_MODE_8_X_41
    +
    + + + + +
    IN_FIFO:ARRAY_MODE[7, 26, 4]
    ARRAY_MODE_4_X_40
    ARRAY_MODE_4_X_81
    +
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    + + + + \ No newline at end of file diff --git a/xilinx/virtex7/dsp.html b/xilinx/virtex7/dsp.html index 70cc4a77..4c722919 100644 --- a/xilinx/virtex7/dsp.html +++ b/xilinx/virtex7/dsp.html @@ -67,6 +67,8 @@
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • diff --git a/xilinx/virtex7/geometry.html b/xilinx/virtex7/geometry.html index ec8f0ed1..85e26d2e 100644 --- a/xilinx/virtex7/geometry.html +++ b/xilinx/virtex7/geometry.html @@ -68,6 +68,8 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • diff --git a/xilinx/virtex7/index.html b/xilinx/virtex7/index.html index fe6b3665..b8a1ce9a 100644 --- a/xilinx/virtex7/index.html +++ b/xilinx/virtex7/index.html @@ -64,6 +64,8 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • @@ -135,6 +137,19 @@

    Virtex 7
  • I/O banks and special functions
    • +
  • Clock interconnect +
    • +
  • Clock management tile +
  • PCI Express Gen2 cores diff --git a/xilinx/virtex7/io.html b/xilinx/virtex7/io.html index 1771ad51..00cdd671 100644 --- a/xilinx/virtex7/io.html +++ b/xilinx/virtex7/io.html @@ -19,7 +19,7 @@ - + @@ -67,6 +67,8 @@
  • I/O banks and special functions
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores
  • PCI Express Gen3 cores
    • @@ -283,7 +285,7 @@

    I/O banks and special functions - +
    diff --git a/xilinx/virtex7/pcie.html b/xilinx/virtex7/pcie.html index 06a0a1f7..d2b38c43 100644 --- a/xilinx/virtex7/pcie.html +++ b/xilinx/virtex7/pcie.html @@ -20,7 +20,7 @@ - + @@ -64,6 +64,8 @@
  • Block RAM
  • DSP
  • Input/Output
    • +
  • Clock interconnect
    • +
  • Clock management tile
  • PCI Express Gen2 cores