diff --git a/searchindex.js b/searchindex.js
index ec7822b0..54df0cd7 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[38, "bram-s3"]], "BRAM.S3A": [[38, "bram-s3a"]], "BRAM.S3ADSP": [[38, "bram-s3adsp"]], "BRAM.S3E": [[38, "bram-s3e"]], "Backbone": [[48, "backbone"], [71, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[57, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [39, "bitstream"], [46, "bitstream"], [52, "bitstream"], [55, "bitstream"], [58, "bitstream"], [60, "bitstream"], [62, "bitstream"], [63, "bitstream"], [68, "bitstream"], [69, "bitstream"], [77, "bitstream"], [78, "bitstream"], [79, "bitstream"], [80, "bitstream"], [83, "bitstream"], [84, "bitstream"], [86, "bitstream"], [87, "bitstream"], [88, "bitstream"], [89, "bitstream"], [93, "bitstream"], [94, "bitstream"], [96, "bitstream"], [97, "bitstream"], [98, "bitstream"], [99, "bitstream"], [100, "bitstream"], [103, "bitstream"], [104, "bitstream"], [106, "bitstream"], [107, "bitstream"], [108, "bitstream"], [110, "bitstream"], [112, "bitstream"], [114, "bitstream"]], "Bitstream geometry": [[51, "bitstream-geometry"], [76, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [115, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[90, "bitstream-clbll"], [101, "bitstream-clbll"], [109, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[90, "bitstream-clblm"], [101, "bitstream-clblm"], [109, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[53, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[53, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[54, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[54, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[54, "bitstream-hclk"]], "Bitstream \u2014 HCLK_ROW": [[54, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[96, "bitstream-intf"], [106, "bitstream-intf"], [112, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[112, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[96, "bitstream-intf-delay"], [106, "bitstream-intf-delay"], [112, "bitstream-intf-delay"]], "Bitstream \u2014 IOI tile": [[57, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[48, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[48, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[54, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[54, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[54, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[54, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[54, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PMVIOB": [[100, "bitstream-pmviob"]], "Bitstream \u2014 PowerPC hole tiles": [[71, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[54, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[40, "bitstream-bottom-tiles"], [64, "bitstream-bottom-tiles"]], "Bitstream \u2014 interconnect tiles": [[48, "bitstream-interconnect-tiles"], [71, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[86, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[48, "bitstream-interface-tiles"], [71, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[59, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[54, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[40, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[59, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[57, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[59, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[54, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[40, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[71, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[54, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[40, "bitstream-top-tiles"], [64, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[38, "block-ram"], [52, "block-ram"], [77, "block-ram"], [88, "block-ram"], [99, "block-ram"], [108, "block-ram"]], "Block RAM \u2014 Virtex": [[59, "block-ram-virtex"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[62, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [116, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [126, "boundary-scan-register"]], "CCM": [[78, "ccm"]], "CLKB.S3": [[40, "clkb-s3"]], "CLKB.S3A": [[40, "clkb-s3a"]], "CLKB.S3E": [[40, "clkb-s3e"]], "CLKB.V2": [[64, "clkb-v2"]], "CLKB.V2P": [[64, "clkb-v2p"]], "CLKB.V2PX": [[64, "clkb-v2px"]], "CLKL.S3A": [[40, "clkl-s3a"]], "CLKL.S3E": [[40, "clkl-s3e"]], "CLKR.S3A": [[40, "clkr-s3a"]], "CLKR.S3E": [[40, "clkr-s3e"]], "CLKT.S3": [[40, "clkt-s3"]], "CLKT.S3A": [[40, "clkt-s3a"]], "CLKT.S3E": [[40, "clkt-s3e"]], "CLKT.V2": [[64, "clkt-v2"]], "CLKT.V2P": [[64, "clkt-v2p"]], "CLKT.V2PX": [[64, "clkt-v2px"]], "CLK_CMT_B": [[91, "clk-cmt-b"]], "CLK_CMT_T": [[91, "clk-cmt-t"]], "CLK_DCM_B": [[81, "clk-dcm-b"]], "CLK_DCM_T": [[81, "clk-dcm-t"]], "CLK_HROW": [[81, "clk-hrow"], [91, "clk-hrow"]], "CLK_IOB_B": [[81, "clk-iob-b"], [91, "clk-iob-b"]], "CLK_IOB_T": [[81, "clk-iob-t"], [91, "clk-iob-t"]], "CLK_MGT_B": [[91, "clk-mgt-b"]], "CLK_MGT_T": [[91, "clk-mgt-t"]], "CLK_TERM_B": [[81, "clk-term-b"]], "CLK_TERM_T": [[81, "clk-term-t"]], "COR": [[65, "cor"], [82, "cor"], [92, "cor"], [102, "cor"]], "COR.S3": [[41, "cor-s3"]], "COR.S3E": [[41, "cor-s3e"]], "COR1": [[92, "cor1"], [102, "cor1"]], "COR1.S3A": [[42, "cor1-s3a"]], "COR2.S3A": [[42, "cor2-s3a"]], "CTL": [[65, "ctl"], [82, "ctl"], [92, "ctl"], [102, "ctl"]], "CTL.S3": [[41, "ctl-s3"]], "CTL.S3A": [[42, "ctl-s3a"]], "CTL1": [[102, "ctl1"]], "Carry logic": [[39, "carry-logic"], [63, "carry-logic"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[40, "clock-interconnect"], [54, "clock-interconnect"], [64, "clock-interconnect"], [81, "clock-interconnect"], [91, "clock-interconnect"]], "Clock rows": [[51, "clock-rows"], [76, "clock-rows"]], "Clock source \u2014 left and right": [[40, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[40, "clock-source-spine-bottom-and-top"], [64, "clock-source-spine-bottom-and-top"]], "Clock spine": [[76, "clock-spine"]], "Clock spine top and bottom": [[71, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[39, "configurable-logic-block"], [53, "configurable-logic-block"], [63, "configurable-logic-block"], [80, "configurable-logic-block"], [90, "configurable-logic-block"], [101, "configurable-logic-block"], [109, "configurable-logic-block"]], "Configurable Logic Block \u2014 Virtex": [[60, "configurable-logic-block-virtex"]], "Configuration Center": [[79, "configuration-center"], [89, "configuration-center"], [100, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[65, "configuration-registers"], [82, "configuration-registers"], [92, "configuration-registers"], [102, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[41, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[42, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [37, null], [47, null], [56, null], [61, null], [70, null], [85, null], [95, null], [105, null], [111, null], [123, null], [124, null]], "Corners": [[43, "corners"], [66, "corners"]], "DCM": [[83, "dcm"]], "DCM output bus": [[64, "dcm-output-bus"]], "DCM.S3": [[44, "dcm-s3"]], "DCM.S3E.BL": [[45, "dcm-s3e-bl"]], "DCM.S3E.BR": [[45, "dcm-s3e-br"]], "DCM.S3E.LB": [[45, "dcm-s3e-lb"]], "DCM.S3E.LT": [[45, "dcm-s3e-lt"]], "DCM.S3E.RB": [[45, "dcm-s3e-rb"]], "DCM.S3E.RT": [[45, "dcm-s3e-rt"]], "DCM.S3E.TL": [[45, "dcm-s3e-tl"]], "DCM.S3E.TR": [[45, "dcm-s3e-tr"]], "DCM.V2": [[67, "dcm-v2"]], "DCM.V2P": [[67, "dcm-v2p"]], "DCMCONN.BOT": [[64, "dcmconn-bot"]], "DCMCONN.TOP": [[64, "dcmconn-top"]], "DESKEW_ADJUST": [[44, "deskew-adjust"], [45, "deskew-adjust"], [67, "deskew-adjust"]], "DSP": [[46, "dsp"], [55, "dsp"], [84, "dsp"], [93, "dsp"], [103, "dsp"], [110, "dsp"]], "Database schema": [[17, "database-schema"], [116, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [123, "database-devices"]], "Default option attributes": [[40, "default-option-attributes"]], "Default option values": [[38, "default-option-values"]], "Device": [[17, "device"], [116, "device"]], "Device geometry": [[51, "device-geometry"], [76, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [125, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [127, "device-structure"]], "Device table": [[49, "device-table"], [72, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [125, "devices"]], "Digital Clock Managers": [[67, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[44, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[45, "digital-clock-managers-spartan-3e-3a"]], "Dual-port 16\u00d7X RAM": [[39, "dual-port-16x-ram"], [63, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[63, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[63, "dual-port-641-ram"]], "ECC mode": [[77, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[94, "ethernet-macs"], [104, "ethernet-macs"]], "FB columns and rows": [[127, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[127, "fclk-networks"]], "FIFO mode": [[77, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[115, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[115, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[115, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [115, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[115, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[64, "gclkc"]], "GCLKC.B": [[64, "gclkc-b"]], "GCLKC.T": [[64, "gclkc-t"]], "GCLKH": [[40, "gclkh"], [64, "gclkh"]], "GCLKH.N": [[40, "gclkh-n"]], "GCLKH.S": [[40, "gclkh-s"]], "GCLKH.UNI": [[40, "gclkh-uni"]], "GCLKH.UNI.N": [[40, "gclkh-uni-n"]], "GCLKH.UNI.S": [[40, "gclkh-uni-s"]], "GCLKVM.S3": [[40, "gclkvm-s3"]], "GCLKVM.S3E": [[40, "gclkvm-s3e"]], "GENERAL[12]": [[42, "general-12"]], "GIGABIT.B": [[68, "gigabit-b"]], "GIGABIT.T": [[68, "gigabit-t"]], "GIGABIT10.B": [[69, "gigabit10-b"]], "GIGABIT10.T": [[69, "gigabit10-t"]], "General Interconnect": [[86, "general-interconnect"]], "General interconnect": [[48, "general-interconnect"], [57, "general-interconnect"], [71, "general-interconnect"]], "General structure": [[51, "general-structure"], [76, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [117, "global-bits"], [118, "global-bits"], [119, "global-bits"], [120, "global-bits"], [121, "global-bits"], [122, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[81, "hclk"], [91, "hclk"]], "HCLK_CENTER": [[81, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[81, "hclk-center-above-cfg"]], "HCLK_CMT": [[91, "hclk-cmt"]], "HCLK_CMT_IOI": [[91, "hclk-cmt-ioi"]], "HCLK_DCM": [[81, "hclk-dcm"]], "HCLK_DCMIOB": [[81, "hclk-dcmiob"]], "HCLK_IOBDCM": [[81, "hclk-iobdcm"]], "HCLK_IOI": [[91, "hclk-ioi"]], "HCLK_IOIS_DCI": [[81, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[81, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[91, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[91, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[91, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[91, "hclk-ioi-topcen"]], "HCLK_TERM_L": [[81, "hclk-term-l"]], "HCLK_TERM_R": [[81, "hclk-term-r"]], "HC_OPT": [[42, "hc-opt"]], "Hard PCI logic": [[74, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[75, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[51, "horizontal-clock-spine"]], "I/O buffers": [[73, "i-o-buffers"]], "I/O buffers \u2014 Spartan 3": [[50, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[50, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[50, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex 2 Pro": [[73, "i-o-buffers-virtex-2-pro"]], "I/O data \u2014 Spartan 3": [[43, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[43, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[43, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[66, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[66, "i-o-data-virtex-2-pro"]], "I/O interface": [[50, "i-o-interface"], [73, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [117, "i-o-pins"], [118, "i-o-pins"], [119, "i-o-pins"], [120, "i-o-pins"], [121, "i-o-pins"], [122, "i-o-pins"]], "IDCODE": [[35, "idcode"], [126, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [117, "imux-bits"], [118, "imux-bits"], [119, "imux-bits"], [120, "imux-bits"], [121, "imux-bits"], [122, "imux-bits"]], "INT.BRAM": [[71, "int-bram"]], "INT.BRAM.S3": [[48, "int-bram-s3"]], "INT.BRAM.S3A.03": [[48, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[48, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[48, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[48, "int-bram-s3e"]], "INT.CLB": [[48, "int-clb"], [71, "int-clb"]], "INT.CNR": [[71, "int-cnr"]], "INT.DCM": [[48, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[48, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[71, "int-dcm-v2"]], "INT.DCM.V2P": [[71, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[71, "int-gt-clkpad"]], "INT.IOI": [[71, "int-ioi"]], "INT.IOI.CLK_B": [[71, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[71, "int-ioi-clk-t"]], "INT.IOI.S3": [[48, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[48, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[48, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[48, "int-ioi-s3e"]], "INT.PPC": [[71, "int-ppc"]], "INTF": [[57, "intf"]], "INTF.CMT": [[57, "intf-cmt"]], "INTF.CMT.IOI": [[57, "intf-cmt-ioi"]], "INTF.DSP": [[48, "intf-dsp"]], "INTF.GT.B0": [[71, "intf-gt-b0"]], "INTF.GT.B123": [[71, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[71, "intf-gt-bclkpad"]], "INTF.GT.T0": [[71, "intf-gt-t0"]], "INTF.GT.T123": [[71, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[71, "intf-gt-tclkpad"]], "INTF.IOI": [[57, "intf-ioi"]], "INTF.PPC": [[71, "intf-ppc"]], "IO banks and IO buffers": [[51, "io-banks-and-io-buffers"], [76, "io-banks-and-io-buffers"]], "IO clock nodes": [[81, "io-clock-nodes"], [91, "io-clock-nodes"]], "IOBS.S3.B2": [[50, "iobs-s3-b2"]], "IOBS.S3.L1": [[50, "iobs-s3-l1"]], "IOBS.S3.R1": [[50, "iobs-s3-r1"]], "IOBS.S3.T2": [[50, "iobs-s3-t2"]], "IOBS.S3A.B2": [[50, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[50, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[50, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[50, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[50, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[50, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[50, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[50, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[50, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[50, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[50, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[50, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[50, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[50, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[50, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[50, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[50, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[50, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[50, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[50, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[73, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[73, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[73, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[73, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[73, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[73, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[73, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[73, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[73, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[73, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[73, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[73, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[73, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[73, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[73, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[73, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[73, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[73, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[73, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[73, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[73, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[73, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[73, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[73, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[73, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[73, "iobs-v2p-t-r2-clk"]], "IOI": [[73, "ioi"]], "IOI.CLK_B": [[73, "ioi-clk-b"]], "IOI.CLK_T": [[73, "ioi-clk-t"]], "IOI.S3": [[50, "ioi-s3"]], "IOI.S3A.B": [[50, "ioi-s3a-b"]], "IOI.S3A.LR": [[50, "ioi-s3a-lr"]], "IOI.S3A.T": [[50, "ioi-s3a-t"]], "IOI.S3E": [[50, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [126, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [126, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[50, "input-output"], [73, "input-output"]], "Input multiplexers": [[48, "input-multiplexers"], [71, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [127, "input-output-buffer"]], "Interconnect": [[96, "interconnect"], [106, "interconnect"], [112, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [49, "introduction"], [72, "introduction"], [125, "introduction"]], "JED bits": [[116, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [115, "jed-mapping"], [117, "jed-mapping"], [118, "jed-mapping"], [119, "jed-mapping"], [120, "jed-mapping"], [121, "jed-mapping"], [122, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[115, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[115, "jed-mapping-macrocells-without-iob"]], "JED structure": [[115, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [126, "jtag-interface"]], "LL.S3": [[43, "ll-s3"]], "LL.S3A": [[43, "ll-s3a"]], "LL.S3E": [[43, "ll-s3e"]], "LL.V2": [[66, "ll-v2"]], "LL.V2P": [[66, "ll-v2p"]], "LLH": [[48, "llh"]], "LLH.CLKB.S3A": [[48, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[48, "llh-clkt-s3a"]], "LLV.S3A": [[48, "llv-s3a"]], "LLV.S3E": [[48, "llv-s3e"]], "LR.S3": [[43, "lr-s3"]], "LR.S3A": [[43, "lr-s3a"]], "LR.S3E": [[43, "lr-s3e"]], "LR.V2": [[66, "lr-v2"]], "LR.V2P": [[66, "lr-v2p"]], "LUT RAM": [[39, "lut-ram"], [63, "lut-ram"]], "LUTs": [[39, "luts"], [63, "luts"]], "Local control terms": [[127, "local-control-terms"]], "Long line splitters": [[48, "long-line-splitters"]], "Lower left": [[43, "lower-left"], [66, "lower-left"]], "Lower right": [[43, "lower-right"], [66, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[81, "mgt-clock-repeater"], [91, "mgt-clock-repeater"]], "MODE": [[42, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [127, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [127, "misc-configuration"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[68, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[69, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[63, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[39, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[39, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [127, "overview"]], "PCI Express": [[58, "pci-express"]], "PCI Express Gen2 cores": [[113, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[114, "pci-express-gen3-cores"]], "PCI Express cores": [[97, "pci-express-cores"], [107, "pci-express-cores"]], "PCI logic": [[76, "pci-logic"]], "PCIE_L": [[113, "pcie-l"]], "PCIE_R": [[113, "pcie-r"]], "PCI_CE_DELAY": [[54, "pci-ce-delay"]], "PMA_SPEED values": [[69, "pma-speed-values"]], "POWERDOWN": [[42, "powerdown"]], "PPC.E": [[71, "ppc-e"]], "PPC.N": [[71, "ppc-n"]], "PPC.S": [[71, "ppc-s"]], "PPC.W": [[71, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "PU_GTS": [[42, "pu-gts"]], "PU_GWE": [[42, "pu-gwe"]], "Packages": [[12, "packages"], [34, "packages"], [125, "packages"]], "Part": [[17, "part"], [116, "part"]], "PowerPC cores": [[98, "powerpc-cores"]], "PowerPC holes": [[71, "powerpc-holes"], [76, "powerpc-holes"]], "Primary vertical clock spine": [[51, "primary-vertical-clock-spine"]], "Primitive outputs": [[48, "primitive-outputs"], [71, "primitive-outputs"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [127, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [126, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "RANDOR": [[39, "randor"]], "RANDOR_INIT": [[39, "randor-init"]], "RESERVED_ANDOR": [[39, "reserved-andor"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [127, "register"]], "Registers": [[39, "registers"], [63, "registers"]], "Row clock terminators": [[81, "row-clock-terminators"]], "SEU_OPT": [[42, "seu-opt"]], "Secondary vertical clock spines": [[51, "secondary-vertical-clock-spines"]], "Shift registers": [[39, "shift-registers"], [63, "shift-registers"]], "Single-port 128\u00d71 RAM": [[63, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[39, "single-port-16x-ram"], [63, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[39, "single-port-32x-ram"], [63, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[39, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[63, "single-port-64x-ram"]], "Spartan 3": [[47, "spartan-3"]], "Spartan 3A DCMs": [[51, "spartan-3a-dcms"]], "Spartan 3A and 3A DSP BRAM columns": [[51, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[51, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[51, "spartan-3e-dcms"]], "Spartan 6": [[56, "spartan-6"]], "Speed": [[17, "speed"], [116, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [117, "speed-data"], [118, "speed-data"], [119, "speed-data"], [120, "speed-data"], [121, "speed-data"], [122, "speed-data"]], "Spine clock terminators": [[81, "spine-clock-terminators"]], "Spine muxes \u2014 CMT": [[91, "spine-muxes-cmt"]], "Spine muxes \u2014 DCM": [[81, "spine-muxes-dcm"]], "Spine muxes \u2014 IOB": [[81, "spine-muxes-iob"], [91, "spine-muxes-iob"]], "Spine muxes \u2014 MGT": [[91, "spine-muxes-mgt"]], "Sum of products": [[63, "sum-of-products"]], "Sum term, LUT2": [[127, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "System monitor": [[87, "system-monitor"]], "TERM.E": [[71, "term-e"]], "TERM.N": [[71, "term-n"]], "TERM.S": [[71, "term-s"]], "TERM.W": [[71, "term-w"]], "TESTMODE": [[102, "testmode"]], "TIMER": [[92, "timer"], [102, "timer"]], "TRIM": [[102, "trim"]], "Terminators": [[48, "terminators"], [71, "terminators"]], "The BRAM bel": [[62, "the-bram-bel"]], "The CLKC clock center tile": [[40, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[40, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[64, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[40, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[40, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[40, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[62, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[62, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[64, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [116, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [39, "id1"], [40, "id1"], [40, "id2"], [40, "id3"], [40, "id4"], [40, "id5"], [40, "id6"], [40, "id7"], [40, "id8"], [40, "id9"], [40, "id10"], [41, "id1"], [42, "id1"], [43, "id1"], [43, "id2"], [43, "id3"], [43, "id4"], [43, "id5"], [44, "id1"], [45, "id1"], [46, "id1"], [47, "id1"], [49, "id1"], [50, "id1"], [50, "id2"], [50, "id3"], [50, "id4"], [50, "id5"], [51, "id1"], [53, "id1"], [55, "id1"], [56, "id1"], [61, "id1"], [62, "id1"], [62, "id2"], [62, "id3"], [62, "id4"], [63, "id1"], [63, "id2"], [63, "id3"], [64, "id1"], [64, "id2"], [64, "id3"], [64, "id4"], [64, "id5"], [65, "id1"], [66, "id1"], [66, "id2"], [66, "id3"], [66, "id4"], [66, "id5"], [67, "id1"], [68, "id1"], [69, "id1"], [70, "id1"], [71, "id1"], [72, "id1"], [73, "id1"], [73, "id2"], [73, "id3"], [73, "id4"], [74, "id1"], [75, "id1"], [76, "id1"], [77, "id1"], [77, "id2"], [77, "id3"], [79, "id1"], [81, "id1"], [82, "id1"], [85, "id1"], [86, "id1"], [89, "id1"], [90, "id1"], [91, "id1"], [92, "id1"], [95, "id1"], [96, "id1"], [100, "id1"], [101, "id1"], [102, "id1"], [105, "id1"], [106, "id1"], [109, "id1"], [111, "id1"], [112, "id1"], [126, "id1"], [126, "id2"], [126, "id3"], [127, "id1"], [127, "id2"]], "Top level": [[17, "top-level"], [116, "top-level"]], "Tristate buses and TBUFs": [[63, "tristate-buses-and-tbufs"]], "UIM IBUF bits": [[23, "uim-ibuf-bits"]], "UIM and FB inputs \u2014 XC9500": [[36, "uim-and-fb-inputs-xc9500"]], "UIM and FB inputs \u2014 XC9500XL/XV": [[36, "uim-and-fb-inputs-xc9500xl-xv"]], "UL.S3": [[43, "ul-s3"]], "UL.S3A": [[43, "ul-s3a"]], "UL.S3E": [[43, "ul-s3e"]], "UL.V2": [[66, "ul-v2"]], "UL.V2P": [[66, "ul-v2p"]], "UNK1C": [[102, "unk1c"]], "UR.S3": [[43, "ur-s3"]], "UR.S3A": [[43, "ur-s3a"]], "UR.S3E": [[43, "ur-s3e"]], "UR.V2": [[66, "ur-v2"]], "UR.V2P": [[66, "ur-v2p"]], "Universal control terms": [[127, "universal-control-terms"]], "Upper left": [[43, "upper-left"], [66, "upper-left"]], "Upper right": [[43, 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108], "9883": [38, 52, 62, 77, 88, 99, 108], "9884": [38, 52, 62, 77, 88, 99, 108], "9885": [38, 52, 62, 77, 88, 99, 108], "9886": [38, 52, 62, 77, 88, 99, 108], "9887": [38, 52, 62, 77, 88, 99, 108], "9888": [38, 52, 62, 77, 88, 99, 108], "9889": [38, 52, 62, 77, 88, 99, 108], "989": [7, 38, 52, 59, 62, 77, 88, 99, 108], "9890": [38, 52, 62, 77, 88, 99, 108], "9891": [38, 52, 62, 77, 88, 99, 108], "9892": [38, 52, 62, 77, 88, 99, 108], "9893": [38, 52, 62, 77, 88, 99, 108], "9894": [38, 52, 62, 77, 88, 99, 108], "9895": [38, 52, 62, 77, 88, 99, 108], "9896": [38, 52, 62, 77, 88, 99, 108], "9897": [38, 52, 62, 77, 88, 99, 108], "9898": [38, 52, 62, 77, 88, 99, 108], "9899": [38, 52, 62, 77, 88, 99, 108], "99": [2, 3, 7, 38, 52, 54, 59, 62, 69, 77, 88, 99, 108, 117, 118, 119, 120, 121, 122], "990": [7, 38, 52, 59, 62, 77, 88, 99, 108], "9900": [7, 38, 52, 62, 77, 88, 99, 108], "9901": [38, 52, 62, 77, 88, 99, 108], "9902": [38, 52, 62, 77, 88, 99, 108], "9903": [38, 52, 62, 77, 88, 99, 108], "9904": [38, 52, 62, 77, 88, 99, 108], "9905": [38, 52, 62, 77, 88, 99, 108], "9906": [38, 52, 62, 77, 88, 99, 108], "9907": [38, 52, 62, 77, 88, 99, 108], "9908": [38, 52, 62, 77, 88, 99, 108], "9909": [38, 52, 62, 77, 88, 99, 108], "991": [7, 38, 52, 59, 62, 77, 88, 99, 108], "9910": [38, 52, 62, 77, 88, 99, 108], "9911": [38, 52, 62, 77, 88, 99, 108], "9912": [38, 52, 62, 77, 88, 99, 108], "9913": [38, 52, 62, 77, 88, 99, 108], "9914": [38, 52, 62, 77, 88, 99, 108], "9915": [38, 52, 62, 77, 88, 99, 108], "9916": [38, 52, 62, 77, 88, 99, 108], "9917": [38, 52, 62, 77, 88, 99, 108], "9918": [38, 52, 62, 77, 88, 99, 108], "9919": [38, 52, 62, 77, 88, 99, 108], "992": [7, 38, 52, 59, 62, 77, 88, 99, 108], "9920": [38, 52, 62, 77, 88, 99, 108], "9921": [38, 52, 62, 77, 88, 99, 108], "9922": [38, 52, 62, 77, 88, 99, 108], "9923": [38, 52, 62, 77, 88, 99, 108], "9924": [38, 52, 62, 77, 88, 99, 108], "9925": [38, 52, 62, 77, 88, 99, 108], "9926": [38, 52, 62, 77, 88, 99, 108], "9927": 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88, 99, 108], "9950": [38, 52, 62, 77, 88, 99, 108], "9951": [38, 52, 62, 77, 88, 99, 108], "9952": [38, 52, 62, 77, 88, 99, 108], "9953": [38, 52, 62, 77, 88, 99, 108], "9954": [38, 52, 62, 77, 88, 99, 108], "9955": [38, 52, 62, 77, 88, 99, 108], "9956": [38, 52, 62, 77, 88, 99, 108], "9957": [38, 52, 62, 77, 88, 99, 108], "9958": [38, 52, 62, 77, 88, 99, 108], "9959": [38, 52, 62, 77, 88, 99, 108], "996": [38, 52, 59, 62, 77, 88, 99, 108], "9960": [38, 52, 62, 77, 88, 99, 108], "9961": [38, 52, 62, 77, 88, 99, 108], "9962": [38, 52, 62, 77, 88, 99, 108], "9963": [38, 52, 62, 77, 88, 99, 108], "9964": [38, 52, 62, 77, 88, 99, 108], "9965": [38, 52, 62, 77, 88, 99, 108], "9966": [38, 52, 62, 77, 88, 99, 108], "9967": [38, 52, 62, 77, 88, 99, 108], "9968": [38, 52, 62, 77, 88, 99, 108], "9969": [38, 52, 62, 77, 88, 99, 108], "997": [38, 52, 59, 62, 77, 88, 99, 108], "9970": [38, 52, 62, 77, 88, 99, 108], "9971": [38, 52, 62, 77, 88, 99, 108], "9972": [38, 52, 62, 77, 88, 99, 108], "9973": [38, 52, 62, 77, 88, 99, 108], "9974": [38, 52, 62, 77, 88, 99, 108], "9975": [38, 52, 62, 77, 88, 99, 108], "9976": [38, 52, 62, 77, 88, 99, 108], "9977": [38, 52, 62, 77, 88, 99, 108], "9978": [38, 52, 62, 77, 88, 99, 108], "9979": [38, 52, 62, 77, 88, 99, 108], "998": [38, 52, 59, 62, 77, 88, 99, 108], "9980": [38, 52, 62, 77, 88, 99, 108], "9981": [38, 52, 62, 77, 88, 99, 108], "9982": [38, 52, 62, 77, 88, 99, 108], "9983": [38, 52, 62, 77, 88, 99, 108], "9984": [38, 52, 62, 77, 88, 99, 108], "9985": [38, 52, 62, 77, 88, 99, 108], "9986": [38, 52, 62, 77, 88, 99, 108], "9987": [38, 52, 62, 77, 88, 99, 108], "9988": [38, 52, 62, 77, 88, 99, 108], "9989": [38, 52, 62, 77, 88, 99, 108], "999": [38, 52, 59, 62, 77, 88, 99, 108], "9990": [38, 52, 62, 77, 88, 99, 108], "9991": [38, 52, 62, 77, 88, 99, 108], "9992": [38, 52, 62, 77, 88, 99, 108], "9993": [38, 52, 62, 77, 88, 99, 108], "9994": [38, 52, 62, 77, 88, 99, 108], "9995": [38, 52, 62, 77, 88, 99, 108], "9996": [38, 52, 62, 77, 88, 99, 108], "9997": [38, 52, 62, 77, 88, 99, 108], "9998": [38, 52, 62, 77, 88, 99, 108], "9999": [38, 52, 62, 77, 88, 99, 108], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 69, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 69, "9ce_mux": 115, "9fb_group": [117, 118, 119, 120, 121, 122], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": 48, "9lct5_inv": 115, "9reg_d_ireg": 115, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [79, 81, 89, 97, 100, 113, 114], "9rowcolumn012345678910111213141516171819202122": 58, "9rowcolumn0123456789101112131415161718192021222324252627": [94, 98, 104, 107], "9rowcolumn01234567891011121314151617181920212223242526272829": 113, "A": [12, 14, 17, 35, 36, 39, 51, 62, 63, 76, 77, 116, 127], "AED": [12, 125], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 63, 127], "As": [35, 127], "BY": [39, 48, 63, 71], "For": [34, 35, 36, 48, 51, 71, 76, 127], "ISE": [35, 127], "IT": 71, "If": [35, 36, 62, 63, 77, 127], "In": [15, 16, 36, 39, 48, 63, 71, 127], "It": [12, 34, 35, 36, 39, 40, 48, 51, 62, 63, 71, 76, 77, 116, 125, 127], "Its": [35, 62], "Not": [15, 16, 36, 48, 71, 127], "OR": [2, 6, 7, 36], "On": [12, 15, 16, 36, 39, 40, 48, 51, 62, 76, 127], "Such": [35, 48, 51, 76], "The": [12, 13, 15, 16, 17, 34, 35, 36, 38, 39, 46, 47, 48, 49, 51, 55, 63, 70, 71, 72, 76, 77, 80, 115, 116, 125, 126, 127], "Their": [39, 63], "There": [17, 35, 39, 48, 49, 62, 63, 71, 72], "These": [36, 71], "To": [35, 36, 77], "_": [17, 34, 36, 116, 127], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 115, 127], "_gclk": 127, "_init": [39, 63], "_inv": [36, 127], "_lct": 127, "_mc": [12, 125], "_mux": [36, 39, 63], "_none": 127, "_reg": [62, 77], "_srval": [39, 63], "_sum": 36, "a0mux": 38, "a0reg": [46, 55], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a10mux": 38, "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a11mux": 38, "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a12mux": 38, "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a13mux": 38, "a14": [2, 3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a14mux": 38, "a15": [3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a15mux": 38, "a16": [3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a16mux": 38, "a17": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a17mux": 38, "a18": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a19": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a1mux": 38, "a1reg": [46, 55], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a20": [6, 7, 22, 23, 24, 121, 122], "a21": [6, 7, 22, 23, 121, 122], "a22": [6, 7, 22, 23, 121, 122], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a2mux": 38, "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a3mux": 38, "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a4mux": 38, "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a5ffinit": [101, 109], "a5ffinitslice0": [101, 109], "a5ffmux": [101, 109], "a5ffsr": [101, 109], "a5ffsrinit": 53, "a5ffsrinitslice0": 53, "a5ffsrslice1": 101, "a5mux": 38, "a5q0": 53, "a5q0100": [53, 101, 109], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a6lut": [53, 90, 101, 109], "a6mux": 38, "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a7mux": 38, "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a8mux": 38, "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a9mux": 38, "a_input": [93, 103, 110], "a_q": 62, "aa1": [6, 7, 22, 23, 121, 122], "aa10": [6, 7, 121, 122], "aa11": [6, 7, 121, 122], "aa12": [6, 7, 121, 122], "aa13": [6, 7, 121, 122], "aa14": [6, 7, 121, 122], "aa15": [6, 7, 121, 122], "aa16": [6, 7, 121, 122], "aa17": [6, 7, 121, 122], "aa18": [6, 7, 121, 122], "aa19": [6, 7, 121, 122], "aa2": [6, 7, 22, 23, 121, 122], "aa20": [6, 7, 121, 122], "aa21": [6, 7, 121, 122], "aa22": [6, 7, 121, 122], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 121, 122], "aa4": [6, 7, 22, 23, 121, 122], "aa5": [6, 7, 121, 122], "aa6": [6, 7, 121, 122], "aa7": [6, 7, 121, 122], "aa8": [6, 7, 121, 122], "aa9": [6, 7, 121, 122], "ab": [62, 71, 77], "ab1": [6, 7, 22, 23, 121, 122], "ab10": [6, 7, 121, 122], "ab11": [6, 7, 121, 122], "ab12": [6, 7, 121, 122], "ab13": [6, 7, 121, 122], "ab14": [6, 7, 121, 122], "ab15": [6, 7, 121, 122], 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"clkawrclkinvbram_h1": 52, "clkb": [51, 76, 77, 78], "clkb01": 78, "clkb_enabl": 78, "clkb_enablepmcd1": 78, "clkbinv": 59, "clkbrdclkinv": 52, "clkbrdclkinvbram_h0": 52, "clkbrdclkinvbram_h1": 52, "clkbwrclklinv": 88, "clkbwrclkuinv": 88, "clkc": [47, 51, 56, 76, 78], "clkc10": 78, "clkc_50a": [47, 51], "clkc_clkout0": 54, "clkc_clkout1": 54, "clkc_enabl": 78, "clkc_enablepmcd1": 78, "clkc_mux": 84, "clkd": 78, "clkd11": 78, "clkd_enabl": 78, "clkd_enablepmcd1": 78, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkdv": [44, 45, 67], "clkdv10000011": 83, "clkdv_count_fal": [44, 45, 67, 83], "clkdv_count_fall_2": [44, 45, 67, 83], "clkdv_count_max": [44, 45, 67, 83], "clkdv_enabl": 83, "clkdv_enabledcm": 83, "clkdv_mode": [44, 45, 67, 83], "clkdv_modedcm": [44, 45, 67, 83], "clkdv_phase_fal": [44, 45, 67, 83], "clkdv_phase_ris": [44, 45, 67, 83], "clkdvdcm": [44, 45, 67], "clkfb": [44, 45, 67, 83], "clkfb0": [44, 67, 83], "clkfb011": 48, "clkfb_enabl": 83, "clkfb_enabledcm": 83, "clkfb_feedback": 83, "clkfb_feedbackdcm": 83, "clkfb_iob": [44, 45, 67, 83], "clkfb_iobdcm": [44, 45, 67, 83], "clkfbdcm": [44, 45, 67], "clkfx": [44, 45, 67], "clkfx00110001": 83, "clkfx180": [44, 67], "clkfx18000101001": 83, "clkfx180_enabl": 83, "clkfx180_enabledcm": 83, "clkfx180dcm": [44, 67], "clkfx_divid": [44, 45, 67, 83], "clkfx_enabl": 83, "clkfx_enabledcm": 83, "clkfx_multipli": [44, 45, 67, 83], "clkfxdcm": [44, 45, 67], "clkin": 83, "clkin011": 48, "clkin1": [44, 67, 83], "clkin_divide_by_2": [44, 45, 67, 83], "clkin_divide_by_2dcm": [44, 45, 67, 83], "clkin_en": 83, "clkin_enabledcm": 83, "clkin_iob": [44, 45, 67, 83], "clkin_iobdcm": [44, 45, 67, 83], "clkinv": [53, 55, 60, 90, 93, 101, 103, 109, 110], "clkinvdsp0": 103, "clkinvdsp1": 103, "clkinvslice0": [60, 90], "clkinvslice1": [53, 101], "clkl": 51, "clkmux": [40, 64], "clkpad": [48, 76], "clkpad0000100000100": 71, "clkpad0001000000010000": 48, "clkpad1000100001000": 71, "clkpad1001000000100000": 48, "clkpad2001000000100": 71, "clkpad2001000001000000": 48, "clkpad3001000001000": 71, "clkpad3001000010000000": 48, "clkpad4010000000100": 71, "clkpad5010000001000": 71, "clkpad6100000000100": 71, "clkpad7100000001000": 71, "clkpin000": 54, "clkpin0000": 54, "clkpin01": 54, "clkpin1001": 54, "clkpin4100": 54, "clkpin5101": 54, "clkr": 51, "clkt": [51, 76], "clock": [11, 12, 34, 35, 36, 37, 39, 47, 48, 49, 56, 62, 63, 70, 72, 77, 85, 95, 116, 125, 127], "clock_delai": 98, "clock_invert_m": 93, "clock_invert_p": 93, "clock_invert_pdsp1": 93, "clockwis": [51, 76], "close": [51, 62], "closest": 51, "cmd_intx_impl": [107, 113], "cmd_intx_implementedpci": [107, 113], "cmo": 14, "cmos111": [50, 73], "cmos_hv111": 50, "cmos_lv001": 50, "cmos_vccaux111": 50, "cmos_vccint011": 50, "cmos_vcco100": 50, "cmt": 95, "cmt0": 54, "cmt10": 54, "cmt_clk000001000010000": 91, "cmt_clk000010000000010": 91, "cmt_clk100000000000110": 91, "cmt_clk100000000011000": 91, "cmt_clk1000010100000000": 91, "cmt_clk1000101000000000": 91, "cmt_clk1100001000001000": 91, "cmt_clk1100010000000100": 91, "cmt_clk1200010010000000": 91, "cmt_clk1201001000000000": 91, "cmt_clk1300001000010000": 91, "cmt_clk1300010000000010": 91, "cmt_clk1400010001000000": 91, "cmt_clk1410001000000000": 91, "cmt_clk1500001000100000": 91, "cmt_clk1500010000000001": 91, "cmt_clk1600010100000000": 91, "cmt_clk1600101000000000": 91, "cmt_clk1700000100000100": 91, "cmt_clk1700100000001000": 91, "cmt_clk1800100100000000": 91, "cmt_clk1900000100001000": 91, "cmt_clk1900100000000100": 91, "cmt_clk200000100010000": 91, "cmt_clk2000100010000000": 91, "cmt_clk200100000000010": 91, "cmt_clk2001000100000000": 91, "cmt_clk2100000100010000": 91, "cmt_clk2100100000000010": 91, "cmt_clk2200100001000000": 91, "cmt_clk2210000100000000": 91, "cmt_clk2300000100100000": 91, "cmt_clk2300100000000001": 91, "cmt_clk2400010010000000": 91, "cmt_clk2401001000000000": 91, "cmt_clk2500000010000100": 91, "cmt_clk2501000000001000": 91, "cmt_clk2600100010000000": 91, "cmt_clk2601000100000000": 91, "cmt_clk2700000010001000": 91, "cmt_clk2701000000000100": 91, "cmt_clk300000000001010": 91, "cmt_clk300000000010100": 91, "cmt_clk400000010010000": 91, "cmt_clk401000000000010": 91, "cmt_clk500000000010010": 91, "cmt_clk600000001010000": 91, "cmt_clk610000000000010": 91, "cmt_clk700000000010001": 91, "cmt_clk700000000100010": 91, "cmt_clk800011000000000": 91, "cmt_clk900001000000100": 91, "cmt_clk900010000001000": 91, "cmt_d00100": 54, "cmt_d100100": 54, "cmt_d10100": 54, "cmt_d110100": 54, "cmt_d120100": 54, "cmt_d130100": 54, "cmt_d140100": 54, "cmt_d150100": 54, "cmt_d20100": 54, "cmt_d30100": 54, "cmt_d40100": 54, "cmt_d50100": 54, "cmt_d60100": 54, "cmt_d70100": 54, "cmt_d80100": 54, "cmt_d90100": 54, "cmt_enabl": 54, "cmt_u01000": 54, "cmt_u101000": 54, "cmt_u11000": 54, "cmt_u111000": 54, "cmt_u121000": 54, "cmt_u131000": 54, "cmt_u141000": 54, "cmt_u151000": 54, "cmt_u21000": 54, "cmt_u31000": 54, "cmt_u41000": 54, "cmt_u51000": 54, "cmt_u61000": 54, "cmt_u71000": 54, "cmt_u81000": 54, "cmt_u91000": 54, "cnr": [51, 76], "code": 35, "coin_window": [44, 67], "col": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [51, 62], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 39, 40, 48, 62, 63, 64, 71, 76, 115, 116, 117, 118, 119, 120, 121, 122, 124, 126], "com": [44, 67], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 39, 48, 62, 63, 71, 127], "combination": 62, "combinatori": [14, 36, 127], "come": [12, 34, 36, 39, 51, 62, 76, 125, 127], "comma_10b_mask": [68, 69], "commerci": [17, 116], "common": 81, "common_hclk_giob": 81, "common_mgt": 81, "common_mgtioclk": 81, "commonli": 115, "compat": [12, 34, 125], "compens": 63, "complet": [12, 13, 16, 34, 35, 36, 115, 125], "complex": [15, 16], "comput": [62, 115], "concaten": [15, 16, 62, 77], "conceptu": 51, "concur": [44, 45, 67], "concur00100101": 83, "concur_en": 83, "concur_enabledcm": 83, "concurdcm": [44, 45, 67], "config": [15, 16, 115], "config10": 83, "config_fallback": [92, 102], "config_r": [41, 42, 65, 82, 92, 102], "configrout": 97, "configur": [11, 12, 15, 33, 34, 35, 37, 40, 47, 48, 49, 56, 61, 70, 71, 72, 76, 85, 95, 105, 111, 115, 124], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 39, 51, 62, 63, 71, 72, 77, 126, 127], "consid": 35, "consist": [35, 36, 62], "const": [13, 14, 35, 36, 39, 63, 126, 127], "constant": [36, 39, 63], "constraint": 12, "construct": 127, "consult": 15, "contain": [15, 17, 34, 38, 39, 48, 49, 51, 62, 63, 71, 72, 76, 77, 126, 127], "content": [35, 39, 63], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 39, 49, 63, 72, 77], "convert": [15, 16], "convst_mux": 87, "convstclkinv": [89, 100], "convstinv": 87, "convstinvsysmon": 87, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 51, 76, 115, 116, 127], "cor": [47, 70, 85, 95, 105], "cor1": [47, 95, 105], "cor2": 47, "core": [12, 34, 36, 37, 48, 70, 71, 72, 76, 95, 105, 111, 125, 127], "corner": [37, 47, 48, 49, 51, 70, 71, 72, 76], "correct": 77, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 39, 40, 46, 48, 51, 55, 62, 63, 64, 71, 76, 77, 116, 127], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 39, 51, 62, 76, 117, 118, 119, 120, 121, 122], "cout": [39, 63], "coutmux": [53, 90, 101, 109], "coutmuxslice1": 53, "cover": 127, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 118, 125], "cpl_timeout_disable_support": [107, 113], "cpl_timeout_ranges_support": [107, 113], "cpld": [0, 12, 34, 36, 125, 127], "cpmc440clkinv": 98, "cpmc440timerclockinv": 98, "cpmdcrclkinv": 98, "cpmdma0llclkinv": 98, "cpmdma1llclkinv": 98, "cpmdma2llclkinv": 98, "cpmdma3llclkinv": 98, "cpmfcmclkinv": 98, "cpminterconnectclkinv": 98, "cpmmcclkinv": 98, "cpmppcmplbclkinv": 98, "cpmppcs0plbclkinv": 98, "cpmppcs1plbclkinv": 98, "crammod": [53, 90, 101, 109], "crc": [41, 42, 65, 82, 92], "crc_end_of_pkt": [68, 69], "crc_format": [68, 69], "crc_start_of_pkt": [68, 69], "creat": [48, 71, 76], "create_edg": [79, 89], "create_edgebufgctrl0": 79, "create_edgebufgctrl1": 79, "create_edgebufgctrl10": 79, "create_edgebufgctrl11": 79, "create_edgebufgctrl12": 79, "create_edgebufgctrl13": 79, "create_edgebufgctrl14": 79, "create_edgebufgctrl15": 79, "create_edgebufgctrl16": 79, "create_edgebufgctrl17": 79, "create_edgebufgctrl18": 79, "create_edgebufgctrl19": 79, "create_edgebufgctrl2": 79, "create_edgebufgctrl20": 79, "create_edgebufgctrl21": 79, "create_edgebufgctrl22": 79, "create_edgebufgctrl23": 79, "create_edgebufgctrl24": 79, "create_edgebufgctrl25": 79, "create_edgebufgctrl26": 79, "create_edgebufgctrl27": 79, "create_edgebufgctrl28": 79, "create_edgebufgctrl29": 79, "create_edgebufgctrl3": 79, "create_edgebufgctrl30": 79, "create_edgebufgctrl31": 79, "create_edgebufgctrl4": 79, "create_edgebufgctrl5": 79, "create_edgebufgctrl6": 79, "create_edgebufgctrl7": 79, "create_edgebufgctrl8": 79, "create_edgebufgctrl9": 79, "creg": [46, 55, 84, 93, 103, 110], "cregdsp": [46, 55], "cregdsp0": [93, 103], "cregdsp1": 103, "crm_core_clk_freq_500": 114, "crm_core_clk_freq_500pcie3": 114, "crm_module_rst": [107, 113], "crm_user_clk_freq": 114, "crmcoreclkdloinv": 97, "crmcoreclkinv": 97, "crmcoreclkinvpci": 97, "crmcoreclkrxoinv": 97, "crmcoreclkrxoinvpci": 97, "crmcoreclktxoinv": 97, "crmcoreclktxoinvpci": 97, "crmuserclkinv": 97, "crmuserclkrxoinv": 97, "crmuserclktxoinv": 97, "cross": [51, 71], "cs144": [20, 21, 34, 119, 125], "cs280": [24, 25, 34, 120, 125], "cs48": [26, 27, 28, 30, 31, 34, 117, 118, 125], "cso2pin": 43, "cspin": [79, 89, 100], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [47, 70, 85, 95, 105], "ctl1": 105, "ctlgo001": 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63, 80, 90, 101, 109], "cyinitslice0": [60, 80, 90, 101, 109], "cyinitslice1": [39, 53, 60, 90, 101, 109], "cyinitslice2": 80, "cyinitslice3": 39, "cyself": [39, 60, 63], "cyselfslice0": 60, "cyselfslice1": [39, 60], "cyselfslice3": 39, "cyselg": [39, 60, 63], "cyselgslice0": [60, 63], "cyselgslice1": [39, 60, 63], "cyselgslice3": 39, "d": [14, 36, 62, 77, 127], "d0": [103, 110], "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122, 127], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 103, 110, 118, 119, 120, 121, 122], "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d15": [3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d16": [3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d17": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d18": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d19": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d20": [6, 7, 22, 23, 24, 103, 110, 121, 122], "d21": [6, 7, 22, 23, 103, 110, 121, 122], "d22": [6, 7, 22, 23, 103, 110, 121, 122], "d23": [22, 23, 103, 110], "d24": [22, 23, 103, 110], "d25": [22, 23], "d26": [22, 23], "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d5ffinit": [101, 109], "d5ffinitslice0": [101, 109], "d5ffmux": [101, 109], "d5ffsr": [101, 109], "d5ffsrinit": 53, "d5ffsrinitslice0": 53, "d5ffsrslice1": 101, "d5q0": 53, "d5q0100": [53, 101, 109], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d6lut": [53, 90, 101, 109], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 103, 110, 118, 119, 120, 121, 122], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "daddr0inv": 83, "daddr1inv": 83, "daddr1invdcm": 83, "daddr2inv": 83, "daddr2invdcm": 83, "daddr3inv": 83, "daddr4inv": 83, "daddr4invdcm": 83, "daddr5inv": 83, "daddr5invdcm": 83, "daddr6inv": 83, "daddr6invdcm": 83, "data": [10, 12, 14, 17, 32, 35, 38, 39, 46, 47, 48, 51, 52, 55, 59, 62, 63, 70, 71, 76, 77, 80, 115, 116, 123, 127], "data0": [48, 71], "data00001000001": 71, "data00001000100": 71, "data00mux": 48, "data1": [48, 71], "data10": 48, "data10001000010": 71, "data10001001000": 71, "data101mux": 48, "data10mux": 48, "data11": 48, "data110mux": 48, "data11mux": 48, "data12": 48, "data13": 48, "data130mux": 48, "data131mux": 48, "data14": 48, "data140mux": 48, "data15": 48, "data16": 48, "data160mux": 48, "data17": 48, "data170mux": 48, "data171mux": 48, "data18": 48, "data180mux": 48, "data181mux": 48, "data19": 48, "data190mux": 48, "data2": [48, 71], "data20": 48, "data20001000100": 71, "data20001010000": 71, "data20mux": 48, "data21": 48, "data210mux": 48, "data21mux": 48, "data22": 48, "data220mux": 48, "data221mux": 48, "data23": 48, "data24": 48, "data240mux": 48, "data25": 48, "data250mux": 48, "data251mux": 48, "data26": 48, "data261mux": 48, "data27": 48, "data270mux": 48, "data28": 48, "data29": 48, "data290mux": 48, "data3": [48, 71], "data30": 48, "data30001001000": 71, "data30001100000": 71, "data300mux": 48, "data301mux": 48, "data30mux": 48, "data31": 48, "data4": [48, 71], "data40001000001": 71, "data40001000010": 71, "data40001000100": 71, "data5": [48, 71], "data50001000010": 71, "data50001000100": 71, "data50001001000": 71, "data50mux": 48, "data51mux": 48, "data6": [48, 71], "data60001000100": 71, "data60001001000": 71, "data60001010000": 71, "data60mux": 48, "data7": [48, 71], "data70001001000": 71, "data70001010000": 71, "data70001100000": 71, "data8": 48, "data80mux": 48, "data9": 48, "data90mux": 48, "data91mux": 48, "data_l": [88, 99, 108], "data_r": 54, "data_u": [88, 99, 108], "data_width_": 62, "data_width_a": [38, 52, 62], "data_width_b": [38, 52, 62], "databas": [11, 15, 16, 33, 35, 36, 115, 124, 126, 127], "datap": [38, 52, 62, 77], "datap_l": [88, 99, 108], "datap_u": [88, 99, 108], "datareg": 13, "datastream": [17, 116], "dbl": [40, 48, 57, 64, 71, 86, 96, 106, 112], "dbl0001010000": 96, "dbl0001100000": 96, "dbl0010010000": 96, "dbl0010100000": 96, "dbl0100010000": 96, "dbl0100100000": 96, "dbl1000010000": 96, "dbl1000100000": 96, "dci": [49, 71, 72], "dci0": [43, 66], "dci00": 43, "dci1": [43, 66], "dci11": 43, "dci_altvr": 66, "dci_altvrmisc": 66, "dci_clk_en": [43, 66], "dci_clk_enablemisc": 66, "dci_mod": [50, 73], "dci_osc_sel": 43, "dci_test_mux": 43, "dcireset": [79, 89, 100], "dcireset0": 43, "dcireset1": 43, "dciupdatemode_asrequir": [50, 73], "dciupdatemode_asrequirediob0": [50, 73], "dciupdatemode_asrequirediob1": [50, 73], "dciupdatemode_asrequirediob2": 73, "dciupdatemode_asrequirediob3": [50, 73], "dciupdatemode_asrequirediob4": [50, 73], "dciupdatemode_asrequirediob5": 73, "dclk0": 83, "dclk_divid_2": 87, "dclk_miss": 87, "dclkinv": [89, 100], "dclkinvsysmon": 89, "dcm": [37, 47, 49, 62, 70, 76, 85], "dcm000001000000111111": 81, "dcm100001000001011111": 81, "dcm1000010001000011111": 81, "dcm1100010010000011111": 81, "dcm1200100000000111111": 81, "dcm1300100000001011111": 81, "dcm1400100000010011111": 81, "dcm1500100000100011111": 81, "dcm1600100001000011111": 81, "dcm1700100010000011111": 81, "dcm1801000000000111111": 81, "dcm1901000000001011111": 81, "dcm200001000010011111": 81, "dcm2001000000010011111": 81, "dcm2101000000100011111": 81, "dcm2201000001000011111": 81, "dcm2301000010000011111": 81, "dcm300001000100011111": 81, "dcm400001001000011111": 81, "dcm500001010000011111": 81, "dcm600010000000111111": 81, "dcm700010000001011111": 81, "dcm800010000010011111": 81, "dcm900010000100011111": 81, "dcm_bufpll": 56, "dcm_clkdv_clkfx_align": 83, "dcm_clkdv_clkfx_alignmentdcm": 83, "dcm_enabl": 43, "dcm_ext_fb_en": 83, "dcm_ext_fb_endcm": 83, "dcm_lock_high": 83, "dcm_lock_highdcm": 83, "dcm_out100": 40, "dcm_out_l0100": [40, 64], "dcm_out_l01000": 40, "dcm_out_r1000": [40, 64], "dcm_out_r10000": 40, "dcm_performance_mod": 83, "dcm_performance_modedcm": 83, "dcm_pulse_width_correction_high": 83, "dcm_pulse_width_correction_low": 83, "dcm_shutdown": [41, 65, 82], "dcm_unused_taps_powerdown": 83, "dcm_unused_taps_powerdowndcm": 83, "dcm_vbg_pd": 83, "dcm_vbg_sel": 83, "dcm_vref_sourc": 83, "dcm_vreg": 45, "dcm_vreg_en": 83, "dcm_vreg_enabledcm": 83, "dcm_vreg_phase_margin": 83, "dcmclk": 71, "dcmclk0": 71, "dcmclk00001000001": 71, "dcmclk0int": 71, "dcmclk1": 71, "dcmclk10001000010": 71, "dcmclk1int": 71, "dcmclk2": 71, "dcmclk20001000001": 71, "dcmclk2int": 71, "dcmclk3": 71, "dcmclk30001000010": 71, "dcmclk3int": 71, "dcr_autolock_en": 98, "dcr_test": 98, "dcremacclkinv": 94, "dcy0": [53, 90, 101, 109], "dcy0slice0": [90, 101, 109], "dcy0slice1": [53, 109], "dd1": 34, "ddel_a": [38, 52, 62], "ddel_a_default": 38, "ddel_b": [38, 52, 62], "ddel_b_default": 38, "ddr": [49, 72], "ddr1": 54, "deal": [51, 71, 76], "dec_mcomma_detect": [68, 69], "dec_pcomma_detect": [68, 69], "dec_valid_comma_onli": [68, 69], "decod": 77, "decrypt": [65, 82, 92, 102], "dedic": [12, 14, 34, 36, 38, 39, 49, 51, 62, 63, 71, 72, 76, 77, 116, 125, 127], "def": [15, 16], "default": [17, 35, 47], "defin": 127, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [117, 118, 119, 120, 121, 122], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_pt_ut": [117, 118, 119, 120, 121, 122], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "delai": [14, 40, 95, 105, 111], "delay_common": 50, "delay_commoniob0": 50, "delay_commoniob1": 50, "delay_commoniob2": 50, "delay_commoniob3": 50, "delay_commoniob4": 50, "delay_commoniob5": 50, "delay_commoniob6": 50, "delay_vari": 50, "delay_variableiob0": 50, "delay_variableiob1": 50, "delay_variableiob3": 50, "delay_variableiob4": 50, "delayed_write0": 108, "delayed_write00": 99, "depend": [17, 35, 36, 48, 51, 62, 71, 116, 126, 127], "deriv": [12, 34, 49, 72, 125, 127], "describ": [17, 35, 39, 40, 51, 62, 63, 64, 81, 91, 116], "descript": [38, 80], "design": [12, 36, 51, 125, 127], "deskew_adjust": [47, 70, 83], "destin": 36, "detail": [35, 51, 76, 77, 126], "determin": [12, 34, 35, 39, 63, 127], "dev_cap2_ari_forwarding_support": 113, "dev_cap2_ari_forwarding_supportedpci": 113, "dev_cap2_atomicop32_completer_support": 113, "dev_cap2_atomicop32_completer_supportedpci": 113, "dev_cap2_atomicop64_completer_support": 113, "dev_cap2_atomicop_routing_support": 113, "dev_cap2_cas128_completer_support": 113, "dev_cap2_cas128_completer_supportedpci": 113, "dev_cap2_endend_tlp_prefix_support": 113, "dev_cap2_endend_tlp_prefix_supportedpci": 113, "dev_cap2_extended_fmt_field_support": 113, "dev_cap2_ltr_mechanism_support": 113, "dev_cap2_ltr_mechanism_supportedpci": 113, "dev_cap2_max_endend_tlp_prefix": 113, "dev_cap2_no_ro_enabled_prpr_pass": 113, "dev_cap2_tph_completer_support": 113, "dev_cap_enable_slot_pwr_limit_scal": [107, 113], "dev_cap_enable_slot_pwr_limit_scalepci": [107, 113], "dev_cap_enable_slot_pwr_limit_valu": [107, 113], "dev_cap_endpoint_l0s_lat": [58, 107, 113], "dev_cap_endpoint_l1_lat": [58, 107, 113], "dev_cap_ext_tag_support": [58, 107, 113], "dev_cap_ext_tag_supportedpci": [107, 113], "dev_cap_function_level_reset_cap": [107, 113], "dev_cap_max_payload_support": [58, 107, 113], "dev_cap_phantom_functions_support": [58, 107, 113], "dev_cap_role_based_error": [58, 107, 113], "dev_cap_rsvd_14_12": [107, 113], "dev_cap_rsvd_17_16": [107, 113], "dev_cap_rsvd_31_29": [107, 113], "dev_control_aux_power_support": [107, 113], "dev_control_aux_power_supportedpci": 113, "dev_control_ext_tag_default": 113, "devic": [11, 15, 16, 33, 35, 37, 38, 39, 40, 47, 48, 62, 63, 64, 70, 71, 115, 124, 126], "device_id": 107, "devicebram": 38, "devicecapabilityendpointl0slat": 97, "devicecapabilityendpointl1lat": 97, "devicedcm": [44, 45, 67], "deviceid": 97, "deviceserialnumb": 97, "devicevalu": [40, 54], "df": [44, 67], "dfb001": 54, "dfb010": 54, "dff": [14, 36, 127], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 115], "dff1": 15, "dff_latch": 101, "dff_latchslice0": 101, "dffce": 127, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 115], "dffinit": [90, 101, 109], "dffinitslice0": [90, 101, 109], "dffmux": [53, 90, 101, 109], "dffmuxslice1": 53, "dffsr": [90, 101, 109], "dffsrinit": 53, "dffsrinitslice1": 53, "dffsrslice0": 109, "dffsrslice1": 101, "dfs_": 45, "dfs_ave_freq_adj_interv": 83, "dfs_ave_freq_gain": 83, "dfs_ave_freq_sample_interv": 83, "dfs_c": 45, "dfs_coarse_sel": 83, "dfs_coarse_seldcm": 83, "dfs_coin_window": 83, "dfs_early_lock": 83, "dfs_early_lockdcm": 83, "dfs_en_relrst": 83, "dfs_en_relrstdcm": 83, "dfs_enabl": [44, 45, 67, 83], "dfs_enabledcm": [44, 45, 67, 83], "dfs_extend_flush_tim": 83, "dfs_extend_flush_timedcm": 83, "dfs_extend_halt_tim": 83, "dfs_extend_halt_timedcm": 83, "dfs_extend_run_tim": 83, "dfs_extend_run_timedcm": 83, "dfs_feedback": [44, 45, 67, 83], "dfs_feedbackdcm": [44, 45, 83], "dfs_fine_sel": 83, "dfs_fine_seldcm": 83, "dfs_frequency_mod": [44, 45, 67, 83], "dfs_frequency_modedcm": [44, 45, 83], "dfs_hardsync": 83, "dfs_non_stop": 83, "dfs_non_stopdcm": 83, "dfs_oscillator_mod": 83, "dfs_skip_fin": 83, "dfs_skip_finedcm": 83, "dfs_spare": 83, "dfs_tp_sel": 83, "dfs_tp_seldcm": 83, "dfs_trackmod": 83, "dfs_trackmodedcm": 83, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 39, 62, 63, 77], "di0inv": 83, "di10inv": 83, "di10invdcm": 83, "di11inv": 83, "di126": [2, 12], "di12inv": 83, "di12invdcm": 83, "di13inv": 83, "di13invdcm": 83, "di14inv": 83, "di14invdcm": 83, "di15inv": 83, "di1inv": 83, "di1invdcm": 83, "di222": [3, 12], "di288": [6, 12], "di2inv": 83, "di2invdcm": 83, "di324": [7, 12], "di3inv": 83, "di44": [4, 5, 12], "di4inv": 83, "di4invdcm": 83, "di5inv": 83, "di5invdcm": 83, "di6inv": 83, "di6invdcm": 83, "di7inv": 83, "di81": [8, 9, 12], "di8inv": 83, "di9inv": 83, "di9invdcm": 83, "dia": 77, "diagon": [48, 71], "dib": 77, "dib16": 62, "dib31": 62, "die": [12, 17, 49, 116], "dif": [39, 63], "dif_mux": [39, 63, 80], "dif_muxslice0": 80, "diff101": [50, 73], "diff110": 50, "differ": [16, 35, 36, 39, 48, 63, 71, 125, 127], "differenti": [14, 49], "dig": [39, 63], "dig_mux": [39, 63, 80], "dig_muxslice0": 80, "dig_muxslice2": 80, "digit": [37, 47, 48, 49, 70, 71, 72], "dimens": 51, "dimension": 115, "dinpin": [79, 89, 100], "dip": [62, 77], "dipa": 77, "dipb": 77, "direct": [36, 48, 62, 71], "direct0": [38, 46, 55, 84, 93, 103, 110], "directli": [14, 17, 35, 36, 39, 51, 62, 63, 71, 116, 127], "dis_tstblclamp": 108, "dis_tstfiforst": [99, 108], "dis_vgg_reg": 102, "disabl": [36, 127], "disable_aspm_l1_tim": [107, 113], "disable_aspm_l1_timerpci": [107, 113], "disable_attr": [40, 54, 64], "disable_attrbufgmux0": 40, "disable_attrbufgmux2": 40, "disable_attrbufgmux6": 40, "disable_attrbufgmux7": 40, "disable_bar_filt": [58, 107, 113], "disable_err_msg": 113, "disable_gt": [50, 73], "disable_gtsiob0": 50, "disable_gtsiob1": 73, "disable_gtsiob2": [50, 73], "disable_gtsiob3": 50, "disable_gtsiob4": [50, 73], "disable_id_check": [58, 107, 113], "disable_id_checkpci": [107, 113], "disable_jtag": 100, "disable_lane_revers": [107, 113], "disable_lane_reversalpci": 107, "disable_locked_filt": 113, "disable_ppm_filt": 113, "disable_ppm_filterpci": 113, "disable_rx_poisoned_resp": 113, "disable_rx_poisoned_resppci": 113, "disable_rx_tc_filt": [107, 113], "disable_scrambl": [58, 107, 113], "disable_scramblingpci": 113, "disablebandgap": 66, "disablebandgapmisc": 66, "disablevgggener": 66, "disablevgggenerationmisc": 66, "disconnect": [48, 127], "displac": 51, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 48, 51, 71], "distribut": [47, 48, 51, 70, 71, 76], "divclk11": 54, "divid": [11, 12, 51, 54, 115, 127], "divide_100": 54, "divide_1000": 54, "divide_2001": 54, "divide_201": 54, "divide_300": 54, "divide_3010": 54, "divide_400": 54, "divide_4011": 54, "divide_501": 54, "divide_5100": 54, "divide_601": 54, "divide_6101": 54, "divide_710": 54, "divide_7110": 54, "divide_810": 54, "divide_8111": 54, "divide_bypass": 54, "divis": [77, 125], "dll": [44, 67, 72], "dll_": 45, "dll_c": 45, "dll_control_clock_spe": 83, "dll_control_clock_speeddcm": 83, "dll_ctl_sel_clkin_div2": 83, "dll_ctl_sel_clkin_div2dcm": 83, "dll_dead_tim": 83, "dll_deskew_lock_by1": 83, "dll_deskew_lock_by1dcm": 83, "dll_deskew_maxtap": 83, "dll_deskew_mintap": 83, "dll_enabl": [44, 67, 83], "dll_enabledcm": [44, 83], "dll_frequency_mod": [44, 45, 67, 83], "dll_frequency_modedcm": 45, "dll_live_tim": 83, "dll_pd_dly_sel": 83, "dll_period_lock_by1": 83, "dll_period_lock_by1dcm": 83, "dll_phase_detector_auto_reset": 83, "dll_phase_detector_auto_resetdcm": 83, "dll_phase_detector_mod": 83, "dll_phase_detector_modedcm": 83, "dll_phase_shift_calibr": 83, "dll_phase_shift_hfc": 83, "dll_phase_shift_lfc": 83, "dll_phase_shift_lock_by1": 83, "dll_phase_shift_lock_by1dcm": 83, "dll_settle_tim": 83, "dll_spare": 83, "dll_test_mux_sel": 83, "dllc": [44, 67], "dma0_control": 98, "dma0_rxchannelctrl": 98, "dma0_rxirqtim": 98, "dma0_txchannelctrl": 98, "dma0_txirqtim": 98, "dma1_control": 98, "dma1_rxchannelctrl": 98, "dma1_rxirqtim": 98, "dma1_txchannelctrl": 98, "dma1_txirqtim": 98, "dma2_control": 98, "dma2_rxchannelctrl": 98, "dma2_rxirqtim": 98, "dma2_txchannelctrl": 98, "dma2_txirqtim": 98, "dma3_control": 98, "dma3_rxchannelctrl": 98, "dma3_rxirqtim": 98, "dma3_txchannelctrl": 98, "dma3_txirqtim": 98, "dma_test": 98, "dna_port": [49, 100], "dnstream_link_num": [107, 113, 114], "do": [35, 39, 62, 63, 71, 77], "doa": [62, 77], "doa0": 77, "doa31": 77, "doa_reg": [38, 52, 77], "doa_reg_l": [88, 99, 108], "doa_reg_u": [88, 99, 108], "dob": [62, 77], "dob10": 77, "dob11": 77, "dob4": 77, "dob5": 77, "dob6": 77, "dob7": 77, "dob8": 77, "dob9": 77, "dob_reg": [38, 52, 77], "dob_reg_l": [88, 99, 108], "dob_reg_u": [88, 99, 108], "document": [15, 16, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 50, 53, 55, 56, 61, 62, 63, 64, 65, 66, 67, 68, 69, 73, 74, 75, 79, 80, 82, 85, 86, 89, 90, 92, 95, 96, 100, 101, 102, 105, 106, 109, 111, 112], "doe": 34, "doesn": [16, 36, 39, 48, 51, 62, 71, 127], "don": [35, 36, 39, 48, 51, 127], "done": [2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 34, 35, 36, 77], "done110": [41, 65, 82, 92, 102], "done111": 42, "done_cycl": [41, 42, 65, 82, 92, 102], "done_pip": [41, 42, 65, 82, 92, 102], "done_signals_powerdown": 102, "donepin": [43, 66, 79, 89, 100], "dont_set1": 93, "dop": [62, 77], "dopa": 77, "doubl": [48, 71], "doutmux": [53, 90, 101, 109], "doutmuxslice1": 53, "down": [36, 48, 49, 51, 127], "down0": 15, "down1": [16, 115], "downward": 36, "dpm": 78, "dpm_oscout10001000100": 78, "dpm_oscout20001000010": 78, "dpm_refclkout0001010000": 78, "dqs0011": 54, "dqs2110": 54, "dr": [13, 115], "drain": 14, "drammod": [53, 90, 101, 109], "dreg": [46, 55, 103, 110], "dregdsp": [46, 55], "dregdsp0": 103, "dregdsp1": 103, "drive": [12, 14, 17, 34, 35, 36, 48, 49, 51, 63, 71, 125, 127], "drive_awak": 42, "drive_don": [41, 42, 65, 82, 92, 102], "drive_last_value0001": 50, "driven": [14, 36, 48, 51, 71, 76, 127], "driver": [12, 34, 48, 71], "drp40": 83, "drp40_mask": 83, "drp40_maskdcm": 83, "drp41": 83, "drp41_mask": 83, "drp41_maskdcm": 83, "drp42": 83, "drp42_mask": 83, "drp42_maskdcm": 83, "drp43": 83, "drp43_mask": 83, "drp44": 83, "drp44_mask": 83, "drp44_maskdcm": 83, "drp45": 83, "drp45_mask": 83, "drp45_maskdcm": 83, "drp46": 83, "drp46_mask": 83, "drp46_maskdcm": 83, "drp47": 83, "drp47_mask": 83, "drp48": 83, "drp48_mask": 83, "drp48_maskdcm": 83, "drp49": 83, "drp49_mask": 83, "drp49_maskdcm": 83, "drp4a": 83, "drp4a_mask": 83, "drp4b": 83, "drp4b_mask": 83, "drp4c": 83, "drp4c_mask": 83, "drp4c_maskdcm": 83, "drp4d": 83, "drp4d_mask": 83, "drp4d_maskdcm": 83, "drp4e": 83, "drp4e_mask": 83, "drp4f": 83, "drp4f_mask": 83, "drp50": 83, "drp50_mask": 83, "drp50_maskdcm": 83, "drp51": 83, "drp51_mask": 83, "drp51_maskdcm": 83, "drp52": 83, "drp52_mask": 83, "drp52_maskdcm": 83, "drp53": 83, "drp53_mask": 83, "drp53_maskdcm": 83, "drp54": 83, "drp54_mask": 83, "drp54_maskdcm": 83, "drp55": 83, "drp55_mask": 83, "drp55_maskdcm": 83, "drp56": 83, "drp56_mask": 83, "drp56_maskdcm": 83, "drp57": 83, "drp57_mask": 83, "drp57_maskdcm": 83, "drp58": 83, "drp58_mask": 83, "drp58_maskdcm": 83, "drp59": 83, "drp59_mask": 83, "drp59_maskdcm": 83, "drp5a": 83, "drp5a_mask": 83, "drp5a_maskdcm": 83, "drp5b": 83, "drp5b_mask": 83, "drp5b_maskdcm": 83, "drp5c": 83, "drp5c_mask": 83, "drp5c_maskdcm": 83, "drp5d": 83, "drp5d_mask": 83, "drp5d_maskdcm": 83, "drp5e": 83, "drp5e_mask": 83, "drp5e_maskdcm": 83, "drp5f": 83, "drp5f_mask": 83, "drp5f_maskdcm": 83, "dsn_base_ptr": [107, 113], "dsn_cap_id": [107, 113], "dsn_cap_nextptr": [107, 113], "dsn_cap_on": [107, 113], "dsn_cap_vers": [107, 113], "dsnbaseptr": 97, "dsncapabilitynextptr": 97, "dsp": [37, 38, 40, 47, 49, 56, 62, 85, 95, 105, 111], "dsp0": [84, 93, 103, 110], "dsp00": 84, "dsp1": [84, 93, 103, 110], "dsp11": 84, "dsp_common": 84, "dss_enabl": 67, "dss_mode": 67, "dssen001": 48, "dsseninv": 67, "dsseninvdcm": 67, "dual": [14, 125], "dualcoreen": 97, "dualcoreslav": 97, "dualrolecfgcntrlrootepn": 97, "dualrolecfgcntrlrootepnpci": 97, "due": [35, 36, 39], "dummi": 71, "duplic": 15, "durat": 35, "dure": [62, 77], "duty_cycle_correct": [44, 45, 67, 83], "dx0": [53, 90, 101, 109], "dx0100": [90, 101, 109], "dx1": 53, "dx10": [101, 109], "dx1010": 53, "dxmux": [39, 60, 63, 80], "dxmuxslice1": 39, "dxmuxslice3": 39, "dymux": [39, 60, 63, 80], "dymuxslice0": 60, "dymuxslice1": 39, "dymuxslice3": 39, "e": [48, 76], "e0": [40, 48, 64, 71, 86], "e00000010001": 86, "e000001": 48, "e00001": 48, "e0000101": 71, "e00010": 48, "e000100000001": 71, "e0001000000010": 71, "e000100000010": 71, "e000100000100": 71, "e000100001000": 71, "e0001000010000": 71, "e00010001": [71, 86], "e00011010": 48, "e0010000000010": 86, "e001000000010": 71, "e0010000000100": [71, 86], "e0010000001000": 86, "e00100001": [71, 86], "e0010001": [71, 86], "e0010010": 86, "e00110000": 48, "e0100000000010": 86, "e0100000000100": 71, "e0100000001000": 86, "e010001": 48, "e0100010": 71, "e01001": 48, "e01101000": 48, "e01110001": 48, "e1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 119, 120, 121, 122], "e10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 24, 25, 118, 119, 120, 121, 122], "e1000000000100": 86, "e10000010001": 86, "e10000100": 48, "e11": [3, 6, 7, 20, 21, 24, 25, 119, 120, 121, 122], "e11000100": 48, "e11100100": 48, "e12": [2, 3, 6, 7, 20, 21, 24, 25, 119, 120, 121, 122], "e13": [2, 3, 6, 7, 20, 21, 24, 25, 119, 120, 121, 122], "e14": [2, 3, 6, 7, 24, 25, 120, 121, 122], "e15": [3, 6, 7, 24, 25, 120, 121, 122], "e16": [3, 6, 7, 24, 25, 120, 121, 122], "e17": [24, 25, 120], "e18": [24, 25, 120], "e19": [6, 7, 24, 25, 120, 121, 122], "e2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 119, 120, 121, 122], "e20": [6, 7, 24, 121, 122], "e21": [6, 7, 121, 122], "e22": [6, 7, 121, 122], "e23": [22, 23], "e24": [22, 23], "e25": [22, 23], "e26": [22, 23], "e3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 119, 120, 121, 122], "e4": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 119, 120, 121, 122], "e5": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 120, 121, 122], "e6": [2, 3, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 120, 121, 122], "e7": [2, 3, 5, 6, 7, 9, 24, 25, 26, 27, 28, 30, 31, 40, 48, 64, 71, 86, 117, 118, 120, 121, 122], "e8": [2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 64, 71, 86, 118, 120, 121, 122], "e9": [2, 3, 6, 7, 24, 25, 64, 71, 86, 120, 121, 122], "each": [14, 15, 16, 34, 35, 36, 39, 48, 51, 62, 63, 71, 76, 115, 116, 127], "earlier": [34, 125], "easi": [48, 71], "ebai": 35, "ecc": 85, "edg": [14, 48, 51, 71, 76], "ee0": [57, 106, 112], "ee1": [57, 106, 112], "ee2": [57, 106, 112], "ee3": [57, 106, 112], "efar0": 102, "effect": [35, 36, 39, 62, 63, 71, 127], "efuse1": [92, 102], "eg": [12, 48, 51, 71], "eight": 71, "either": [14, 35, 36, 51, 62, 63, 116, 126, 127], "el0": [57, 96, 106, 112], "el1": [57, 96, 106, 112], "el2": [57, 96, 106, 112], "el3": [57, 106, 112], "electron": [115, 127], "element": [17, 116], "elimin": 51, "els": [15, 16, 36, 127], "emac": [94, 104], "emac0_1000basex_en": 94, "emac0_addrfilter_en": 94, "emac0_bytephi": 94, "emac0_configvec_79": 94, "emac0_dcrbaseaddr": 94, "emac0_funct": 94, "emac0_gtloopback": 94, "emac0_host_en": 94, "emac0_linktimerv": 94, "emac0_ltcheck_dis": 94, "emac0_mdio_en": 94, "emac0_pauseaddr": 94, "emac0_phyinitautoneg_en": 94, "emac0_phyisol": 94, "emac0_phyloopbackmsb": 94, "emac0_phypowerdown": 94, "emac0_phyreset": 94, "emac0_rgmii_en": 94, "emac0_rx16bitclient_en": 94, "emac0_rx_en": 94, "emac0_rxflowctrl_en": 94, "emac0_rxhalfduplex": 94, "emac0_rxinbandfcs_en": 94, "emac0_rxjumboframe_en": 94, "emac0_rxreset": 94, "emac0_rxvlan_en": 94, "emac0_sgmii_en": 94, "emac0_speed_lsb": 94, "emac0_speed_msb": 94, "emac0_tx16bitclient_en": 94, "emac0_tx_en": 94, "emac0_txflowctrl_en": 94, "emac0_txhalfduplex": 94, "emac0_txifgadjust_en": 94, "emac0_txinbandfcs_en": 94, "emac0_txjumboframe_en": 94, "emac0_txreset": 94, "emac0_txvlan_en": 94, "emac0_unicastaddr": 94, "emac0_unidirection_en": 94, "emac0_useclken": 94, "emac1_1000basex_en": 94, "emac1_addrfilter_en": 94, "emac1_bytephi": 94, "emac1_configvec_79": 94, "emac1_dcrbaseaddr": 94, "emac1_funct": 94, "emac1_gtloopback": 94, "emac1_host_en": 94, "emac1_linktimerv": 94, "emac1_ltcheck_dis": 94, "emac1_mdio_en": 94, "emac1_pauseaddr": 94, "emac1_phyinitautoneg_en": 94, "emac1_phyisol": 94, "emac1_phyloopbackmsb": 94, "emac1_phypowerdown": 94, "emac1_phyreset": 94, "emac1_rgmii_en": 94, "emac1_rx16bitclient_en": 94, "emac1_rx_en": 94, "emac1_rxflowctrl_en": 94, "emac1_rxhalfduplex": 94, "emac1_rxinbandfcs_en": 94, "emac1_rxjumboframe_en": 94, "emac1_rxreset": 94, "emac1_rxvlan_en": 94, "emac1_sgmii_en": 94, "emac1_speed_lsb": 94, "emac1_speed_msb": 94, "emac1_tx16bitclient_en": 94, "emac1_tx_en": 94, "emac1_txflowctrl_en": 94, "emac1_txhalfduplex": 94, "emac1_txifgadjust_en": 94, "emac1_txinbandfcs_en": 94, "emac1_txjumboframe_en": 94, "emac1_txreset": 94, "emac1_txvlan_en": 94, "emac1_unicastaddr": 94, "emac1_unidirection_en": 94, "emac1_useclken": 94, "emac_1000basex_en": 104, "emac_addrfilter_en": 104, "emac_bytephi": 104, "emac_configvec_79": 104, "emac_ctrllencheck_dis": 104, "emac_dcrbaseaddr": 104, "emac_funct": 104, "emac_gtloopback": 104, "emac_host_en": 104, "emac_linktimerv": 104, "emac_ltcheck_dis": 104, "emac_mdio_en": 104, "emac_pauseaddr": 104, "emac_phyinitautoneg_en": 104, "emac_phyisol": 104, "emac_phyloopbackmsb": 104, "emac_phypowerdown": 104, "emac_phyreset": 104, "emac_rgmii_en": 104, "emac_rx16bitclient_en": 104, "emac_rx_en": 104, "emac_rxflowctrl_en": 104, "emac_rxhalfduplex": 104, "emac_rxinbandfcs_en": 104, "emac_rxjumboframe_en": 104, "emac_rxreset": 104, "emac_rxvlan_en": 104, "emac_sgmii_en": 104, "emac_speed_lsb": 104, "emac_speed_msb": 104, "emac_tx16bitclient_en": 104, "emac_tx_en": 104, "emac_txflowctrl_en": 104, "emac_txhalfduplex": 104, "emac_txifgadjust_en": 104, "emac_txinbandfcs_en": 104, "emac_txjumboframe_en": 104, "emac_txreset": 104, "emac_txvlan_en": 104, "emac_unicastaddr": 104, "emac_unidirection_en": 104, "emac_useclken": 104, "empti": [17, 51, 71, 77], "emul": 36, "en": [48, 62, 71, 77], "en0": 96, "en000001": 48, "en00001": 48, "en000010": 48, "en00010": 48, "en0001000010000": 86, "en00010001": [71, 86], "en001000000100": 71, "en00100001": [71, 86], "en0010001": [71, 86], "en00100010": [71, 86], "en0010010": 86, "en00100100": 48, "en0100000001000": 71, "en0100000010000": 86, "en0100010": [71, 86], "en01001000": 48, "en1": 96, "en2": 96, "en_dummy_osc": [44, 67], "en_dummy_osc_or_non_stop": 67, "en_dummy_oscdcm": 44, "en_ecc_read": [77, 88, 99, 108], "en_ecc_readbram": 99, "en_ecc_scrub": 88, "en_ecc_writ": [77, 88, 99, 108], "en_ecc_write_no_read": [88, 99], "en_ecc_write_no_readbram": 99, "en_ecc_writebram": 99, "en_old_oscctl": 44, "en_old_oscctldcm": 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"link_cap_l0s_exit_lat": 58, "link_cap_l0s_exit_latency_comclk_gen1": [107, 113], "link_cap_l0s_exit_latency_comclk_gen2": [107, 113], "link_cap_l0s_exit_latency_gen1": [107, 113], "link_cap_l0s_exit_latency_gen2": [107, 113], "link_cap_l1_exit_lat": 58, "link_cap_l1_exit_latency_comclk_gen1": [107, 113], "link_cap_l1_exit_latency_comclk_gen2": [107, 113], "link_cap_l1_exit_latency_gen1": [107, 113], "link_cap_l1_exit_latency_gen2": [107, 113], "link_cap_link_bandwidth_notification_cap": [107, 113], "link_cap_max_link_spe": [107, 113], "link_cap_max_link_width": [107, 113], "link_cap_rsvd_23": 113, "link_cap_rsvd_23_22": 107, "link_cap_surprise_down_error_cap": [107, 113], "link_cap_surprise_down_error_capablepci": [107, 113], "link_control_rcb": [107, 113], "link_ctrl2_deemphasi": [107, 113], "link_ctrl2_deemphasispci": [107, 113], "link_ctrl2_hw_autonomous_speed_dis": [107, 113], "link_ctrl2_target_link_spe": [107, 113], "link_status_slot_clock_config": [58, 107, 113], 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34, 119, 120, 121, 125], "tr": 47, "transceiv": [37, 70, 71, 72], "transfer": [2, 3, 4, 5, 6, 7], "translat": 115, "transmit": [15, 16], "trd_dly_l": [88, 99, 108], "trd_dly_u": [88, 99, 108], "trenchcoat": 49, "tri": 36, "trigger": [14, 35, 39, 49, 63, 72], "trim": 105, "trim_lp_b": 44, "trim_lp_bdcm": 44, "tristat": [36, 70, 71], "trn_dw": 113, "trn_dwpcie": 113, "trn_np_fc": 113, "true": [2, 3, 6, 7, 15, 16, 17, 36, 116, 127], "truli": 127, "ts0": 71, "ts00001000001": 71, "ts0int": 71, "ts1": 71, "ts10": 71, "ts10001000010": 71, "ts11": 71, "ts12": 71, "ts13": 71, "ts1int": 71, "ts2": 71, "ts20": 71, "ts21": 71, "ts22": 71, "ts23": 71, "tsbypass_mux": [50, 73], "tsbypass_muxioi0": 73, "tsbypass_muxioi1": 73, "tsbypass_muxioi2": 73, "tscrub_dly_l": 88, "tscrub_dly_u": 88, "tst_pulsepu_sft": 108, "tst_rng_osc": 108, "tst_ssrlat_wf": 108, "tstrefbl_ctrl": 108, "tstrsr_rwctrl": 108, "turn": [15, 39, 63, 71], "twice": [15, 35], "two": [15, 17, 34, 35, 36, 39, 40, 48, 51, 62, 63, 64, 71, 76, 77, 116, 127], "two24001": [93, 103, 110], "two_round": 42, "twr_dly_a_l": 108, "twr_dly_a_u": 108, "twr_dly_b_l": 108, "twr_dly_b_u": 108, "twr_dly_l": [88, 99], "twr_dly_u": [88, 99], "tx_buffer_us": [68, 69], "tx_crc_force_valu": [68, 69], "tx_crc_use": [68, 69], "tx_data_width": 68, "tx_diff_ctrl": 68, "tx_preemphasi": 68, "txreadaddrpip": 97, "txreadaddrpipepci": 97, "txreaddatapip": 97, "txreaddatapipepci": 97, "txtsnft": 97, "txtsnftscomclk": 97, "txwritepip": 97, "type": [17, 35, 48, 51, 71, 76, 116, 126], "u": 71, "u1": [6, 7, 22, 23, 24, 25, 120, 121, 122], "u10": [24, 25, 120], "u11": [24, 25, 120], "u12": [24, 25, 120], "u13": [24, 25, 120], "u14": [24, 25, 120], "u15": [24, 25, 120], "u16": [24, 25, 120], "u17": [24, 25, 120], "u18": [24, 25, 120], "u19": [6, 7, 24, 25, 120, 121, 122], "u2": [6, 7, 22, 23, 24, 25, 120, 121, 122], "u20": [6, 7, 24, 121, 122], "u21": [6, 7, 121, 122], "u22": [6, 7, 121, 122], "u23": [22, 23], "u24": [22, 23], "u25": [22, 23], "u26": [22, 23], "u3": [6, 7, 22, 23, 24, 25, 120, 121, 122], "u4": [6, 7, 22, 23, 24, 25, 120, 121, 122], "u5": [24, 25, 120], "u6": [24, 25, 120], "u7": [24, 25, 120], "u8": [24, 25, 120], "u9": [24, 25, 120], "uct": [115, 127], "uct0": [117, 118, 119, 120, 121, 122, 127], "uct0101": 115, "uct1": [117, 118, 119, 120, 121, 122, 127], "uct1110": 115, "uct2": [117, 118, 119, 120, 121, 122, 127], "uct2110": 115, "uct3": [117, 118, 119, 120, 121, 122, 127], "uct3111": 115, "ue": [115, 117, 118, 119, 120, 121, 122, 127], "uim": [16, 17, 32, 33, 34, 35], "uim0": 26, "uim10": 26, "uim110": 29, "uim1110": [18, 19, 22, 29], "uim11110": [19, 22, 23], "uim_area_bit": 15, "uim_ibuf_bit": 17, "uim_o": 36, "uim_oe_mux": 36, "uim_oe_mux4544": 15, "uim_out_inv": [15, 36], "uim_out_inv46": 15, "uim_row_bit": 15, "uim_subarea_bit": 15, "ul": [51, 76], "ulvds_250010000000000": 43, "ulvds_25011": 66, "ulvds_25100001": 73, "ulvds_25101": 50, "ulvds_251010": 73, "ulvds_2511": 66, "unaffect": 51, "unchang": [16, 39, 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76, 77, 115, 116, 125, 126, 127], "usabl": [48, 51], "use_dport": [103, 110], "use_dportdsp0": 110, "use_dportdsp1": 110, "use_mult": [93, 103, 110], "use_multdsp0": 110, "use_multdsp1": 110, "use_pattern_detect": 93, "use_rid_pin": 113, "use_rid_pinspci": 113, "use_simd": [93, 103, 110], "use_vref01": [2, 3, 6, 7], "useless": 48, "user": [49, 72, 115, 127], "user_clk2_div2": 113, "user_clk2_div2pci": 113, "user_clk_freq": [107, 113], "user_mode00": [68, 69], "userclk01": [41, 42, 65, 82, 92, 102], "usercod": [2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 35, 36], "userid": [43, 66, 79, 89, 100], "usr_cfg": 58, "usr_ext_cfg": 58, "usrcclk_en": [79, 89, 100], "usual": [17, 35, 36, 71, 127], "v": 12, "v1": [6, 7, 22, 23, 24, 25, 120, 121, 122], "v10": [24, 25, 120], "v11": [24, 25, 120], "v12": [24, 25, 120], "v13": [24, 25, 120], "v14": [24, 25, 120], "v15": [24, 25, 120], "v16": [24, 25, 120], "v17": [24, 25, 120], "v18": [24, 25, 120], "v19": [6, 7, 24, 25, 120, 121, 122], "v2": [6, 7, 22, 23, 24, 25, 70, 120, 121, 122], "v20": [6, 7, 24, 121, 122], "v21": [6, 7, 121, 122], "v22": [6, 7, 121, 122], "v23": [22, 23], "v24": [22, 23], "v25": [22, 23], "v26": [22, 23], "v2p": 70, "v3": [6, 7, 22, 23, 24, 25, 120, 121, 122], "v4": [6, 7, 22, 23, 24, 25, 120, 121, 122], "v5": [24, 25, 120], "v6": [24, 25, 120], "v7": [24, 25, 120], "v8": [24, 25, 120], "v9": [24, 25, 120], "valid": [15, 16, 35], "valu": [14, 15, 16, 17, 35, 36, 39, 47, 62, 63, 70, 71, 77, 116, 126, 127], "vari": [34, 35, 36, 127], "variabl": 115, "variant": [12, 34, 36, 48, 51, 71, 76, 127], "variou": [39, 48, 49, 63, 71, 72, 127], "vbg_dll_sel": 92, "vbg_pd": [44, 67], "vbg_sel": [44, 45, 67, 92, 102], "vbg_vgg_flast_sel": 102, "vbg_vgg_neg_sel": 102, "vc0_cpl_infinit": [58, 107, 113], "vc0_rx_ram_limit": [58, 107, 113], "vc0_total_credits_cd": [58, 107, 113], "vc0_total_credits_ch": [58, 107, 113], "vc0_total_credits_npd": 113, "vc0_total_credits_nph": [58, 107, 113], "vc0_total_credits_pd": [58, 107, 113], "vc0_total_credits_ph": [58, 107, 113], "vc0_tx_lastpacket": [58, 107, 113], "vc0rxfifobasec": 97, "vc0rxfifobasenp": 97, "vc0rxfifobasep": 97, "vc0rxfifolimitc": 97, "vc0rxfifolimitnp": 97, "vc0rxfifolimitp": 97, "vc0totalcreditscd": 97, "vc0totalcreditsch": 97, "vc0totalcreditsnph": 97, "vc0totalcreditspd": 97, "vc0totalcreditsph": 97, "vc0txfifobasec": 97, "vc0txfifobasenp": 97, "vc0txfifobasep": 97, "vc0txfifolimitc": 97, "vc0txfifolimitnp": 97, "vc0txfifolimitp": 97, "vc1rxfifobasec": 97, "vc1rxfifobasenp": 97, "vc1rxfifobasep": 97, "vc1rxfifolimitc": 97, "vc1rxfifolimitnp": 97, "vc1rxfifolimitp": 97, "vc1totalcreditscd": 97, "vc1totalcreditsch": 97, "vc1totalcreditsnph": 97, "vc1totalcreditspd": 97, "vc1totalcreditsph": 97, "vc1txfifobasec": 97, "vc1txfifobasenp": 97, "vc1txfifobasep": 97, "vc1txfifolimitc": 97, "vc1txfifolimitnp": 97, "vc1txfifolimitp": 97, "vc_base_ptr": [107, 113], "vc_cap_id": [107, 113], "vc_cap_nextptr": [107, 113], "vc_cap_on": [107, 113], "vc_cap_reject_snoop_transact": [107, 113], "vc_cap_reject_snoop_transactionspci": 113, "vc_cap_vers": [107, 113], "vcbaseptr": 97, "vcc": [36, 116, 117, 118, 119, 120, 121, 122, 125, 127], "vcc00": 54, "vcc0000": [2, 3, 4, 5, 6, 7, 8, 9], "vcc0000000000": [106, 112], "vcc00000010": 57, "vcc00010001": 86, "vcc0010000001": 96, "vcc00100001": 86, "vcc01": 15, "vcc01000010": 57, "vcc10": [103, 110], "vcc11": [2, 3, 4, 5, 6, 7, 8, 9], "vcc110": 115, "vcc11000001": 57, "vcc11111111": [4, 5, 117], "vcc1111111111111111": [8, 9], "vcc11111111111111111": 118, "vcc111111111111111111111111111": 119, "vcc1111111111111111111111111111": 2, "vcc1111111111111111111111111111111111111111111111": 120, "vcc111111111111111111111111111111111111111111111111": 3, "vcc111111111111111111111111111111111111111111111111111111111111111": 121, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111": 6, "vcc11111111111111111111111111111111111111111111111111111111111111111111111111111111111": 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"XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Xilinx FPGAs", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers \u2014 Spartan 3, Spartan 3E", "Configuration registers \u2014 Spartan 3A and 3A DSP", "Corners", "Digital Clock Managers \u2014 Spartan 3", "Digital Clock Managers \u2014 Spartan 3E, 3A", "DSP", "Spartan 3", "General interconnect", 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"clk_cmt_b": 91, "clk_cmt_t": 91, "clk_dcm_b": 81, "clk_dcm_t": 81, "clk_hrow": [81, 91], "clk_iob_b": [81, 91], "clk_iob_t": [81, 91], "clk_mgt_b": 91, "clk_mgt_t": 91, "clk_t": [71, 73], "clk_term_b": 81, "clk_term_t": 81, "clkb": [40, 48, 64], "clkc": [40, 54], "clkc_50a": 40, "clkl": 40, "clkpad": 71, "clkr": 40, "clkt": [40, 48, 64], "clock": [14, 40, 44, 45, 51, 54, 64, 67, 71, 76, 81, 91], "cmt": [57, 91], "cnr": 71, "column": [51, 127], "combin": 0, "configur": [14, 36, 39, 41, 42, 53, 60, 63, 65, 79, 80, 82, 89, 90, 92, 100, 101, 102, 109, 127], "content": [0, 10, 11, 32, 33, 37, 47, 56, 61, 70, 85, 95, 105, 111, 123, 124], "control": 127, "coolrunn": 11, "cor": [41, 65, 82, 92, 102], "cor1": [42, 92, 102], "cor2": 42, "core": [75, 97, 98, 107, 113, 114], "corner": [43, 66], "cpld": [11, 33, 124], "ctl": [41, 42, 65, 82, 92, 102], "ctl1": 102, "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 66, 117, 118, 119, 120, 121, 122], "databas": [10, 17, 32, 116, 123], "dcm": [44, 45, 48, 51, 64, 67, 71, 81, 83], "dcm_bufpll": 54, "dcmconn": 64, "default": [38, 40], "delai": [96, 106, 112], "deskew_adjust": [44, 45, 67], "devic": [10, 12, 14, 17, 32, 34, 36, 49, 51, 72, 76, 116, 123, 125, 127], "digit": [44, 45, 67], "distribut": [40, 64], "divid": 14, "dr": 35, "dsp": [42, 46, 48, 51, 55, 84, 93, 103, 110], "dual": [39, 63], "dummi": 48, "e": 71, "ecc": 77, "enabl": 15, "enter": 35, "eras": 35, "ethernet": [94, 104], "exit": 35, "export": 36, "express": [58, 97, 107, 113, 114], "fb": [14, 15, 16, 36, 115, 127], "fclk": 127, "fifo": 77, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 37, "frequenc": 35, "fuse": [15, 16, 35, 36, 115], "gate": [14, 36], "gclkc": 64, "gclkh": [40, 64], "gclkvc": 40, "gclkvm": 40, "gen2": 113, "gen3": 114, "gener": [42, 48, 51, 57, 71, 76, 86], "geometri": [51, 76], "gigabit": [68, 69], "gigabit10": 69, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 115, 117, 118, 119, 120, 121, 122], "gt": 71, "hard": [74, 75], "hc_opt": 42, "hclk": [54, 81, 91], "hclk_center": 81, "hclk_center_above_cfg": 81, "hclk_cmt": 91, "hclk_cmt_ioi": 91, "hclk_dcm": 81, "hclk_dcmiob": 81, "hclk_iobdcm": 81, "hclk_ioi": 91, "hclk_ioi_botcen": 91, "hclk_ioi_cent": 91, "hclk_ioi_cmt": 91, "hclk_ioi_topcen": 91, "hclk_iois_dci": 81, "hclk_iois_lvd": 81, "hclk_row": 54, "hclk_term_l": 81, "hclk_term_r": 81, "hole": [71, 76], "horizont": 51, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 66, 73, 117, 118, 119, 120, 121, 122], "ibuf": 23, "idcod": [35, 126], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 115, 117, 118, 119, 120, 121, 122], "input": [14, 15, 16, 36, 48, 50, 71, 73, 127], "instruct": [13, 35, 126], "int": [48, 71], "interconnect": [40, 48, 54, 57, 64, 71, 81, 86, 91, 96, 106, 112], "interfac": [13, 35, 48, 50, 57, 71, 73, 86, 126], "intf": [48, 57, 71, 96, 106, 112], "introduct": [12, 34, 49, 72, 125], "io": [51, 76, 81, 91], "iob": [2, 3, 6, 7, 14, 50, 73, 81, 91, 115, 127], "ioi": [48, 50, 57, 71, 73], "ir": [13, 35, 126], "isp": [13, 35, 126], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 115, 116, 117, 118, 119, 120, 121, 122], "jtag": [13, 35, 126], "keeper": 36, "l": 73, "l1": [50, 73], "l2": [50, 73], "l3": 50, "l4": 50, "lb": 45, "left": [40, 43, 54, 59, 66], "level": [17, 116], "line": 48, "ll": [43, 66], "llh": 48, "llv": 48, "local": 127, "logic": [39, 53, 60, 63, 74, 76, 80, 90, 101, 109], "long": 48, "lower": [43, 66], "lr": [43, 48, 50, 66], "lt": 45, "lut": [39, 63], "lut2": 127, "mac": [94, 104], "macrocel": [14, 15, 16, 36, 115, 127], "manag": [44, 45, 67], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 115, 117, 118, 119, 120, 121, 122], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "mgt": [81, 91], "middl": 59, "misc": [14, 36, 127], "mode": [35, 42, 77], "monitor": 87, "mult": 62, "multi": [68, 69], "multiplex": [39, 48, 63, 71], "mux": [81, 91], "n": [40, 71], "network": [14, 36, 127], "node": [81, 91], "normal": 57, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 66, 73, 117, 118, 119, 120, 121, 122], "option": [38, 40], "output": [14, 36, 39, 48, 50, 63, 64, 71, 73, 127], "overview": [14, 36, 127], "packag": [12, 34, 125], "part": [17, 116], "pci": [58, 74, 76, 97, 107, 113, 114], "pci_ce_delai": 54, "pcie_l": 113, "pcie_r": 113, "pcilogics": 54, "per": [15, 16], "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 117, 118, 119, 120, 121, 122, 125], "pll_bufpll_b": 54, "pll_bufpll_out0": 54, "pll_bufpll_out1": 54, "pll_bufpll_t": 54, "pma_spe": 69, "pmviob": 100, "port": [39, 63], "powerdown": 42, "powerpc": [71, 75, 76, 98], "ppc": 71, "primari": 51, "primit": [48, 71], "pro": [66, 68, 69, 73], "product": [14, 15, 16, 36, 63, 115, 127], "program": [13, 35, 126], "project": 0, "protect": 35, "pt": 36, "pu_gt": 42, "pu_gw": 42, "pull": 36, "r": 73, "r1": [50, 73], "r2": [50, 73], "r3": 50, "r4": 50, "ram": [38, 39, 52, 59, 62, 63, 77, 88, 99, 108], "randor": 39, "randor_init": 39, "rb": 45, "read": 35, "regist": [13, 14, 35, 39, 41, 42, 63, 65, 82, 92, 102, 126, 127], "repeat": [81, 91], "reserved_andor": 39, "right": [40, 43, 54, 59, 66], "row": [40, 51, 64, 76, 81, 127], "rt": 45, "s3": [38, 40, 41, 43, 44, 48, 50], "s3a": [38, 40, 42, 43, 48, 50], "s3adsp": [38, 48], "s3e": [38, 40, 41, 43, 45, 48, 50], "scan": [13, 35, 126], "schema": [17, 116], "secondari": [40, 51], "sequenc": [13, 35, 126], "seu_opt": 42, "shift": [39, 63], "side": 59, "singl": [39, 63], "sourc": [40, 64], "spartan": [39, 41, 42, 43, 44, 45, 47, 50, 51, 56, 62], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 116, 117, 118, 119, 120, 121, 122], "spine": [40, 51, 64, 71, 76, 81, 91], "splitter": 48, "structur": [1, 14, 15, 16, 36, 51, 76, 115, 127], "sum": [14, 36, 63, 115, 127], "system": 87, "t": [50, 64, 68, 69, 73], "t0": 71, "t1": 50, "t123": 71, "t2": [50, 73], "t3": 50, "t4": 50, "tabl": [49, 72], "tb": 48, "tbuf": 63, "tclkpad": 71, "term": [14, 15, 16, 36, 71, 115, 127], "termin": [48, 71, 81], "testmod": 102, "tile": [17, 40, 48, 54, 57, 64, 71, 86, 116], "timer": [92, 102], "tl": 45, "todo": [1, 12, 13, 14, 35, 36, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49, 50, 51, 53, 55, 56, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 81, 82, 85, 86, 89, 90, 91, 92, 95, 96, 100, 101, 102, 105, 106, 109, 111, 112, 126, 127], "top": [17, 40, 54, 64, 71, 116], "tr": 45, "transceiv": [68, 69], "trim": 102, "tristat": 63, "uim": [15, 23, 36], "ul": [43, 66], "uni": 40, "univers": 127, "unk1c": 102, "up": 36, "upper": [43, 66], "ur": [43, 66], "v2": [64, 66, 67, 71, 73], "v2p": [64, 66, 67, 71, 73], "v2px": 64, "valu": [38, 69], "vertic": 51, "virtex": [39, 59, 60, 61, 62, 66, 68, 69, 70, 73, 85, 95, 105, 111], "w": 71, "wide": [39, 63], "wire": 15, "without": [2, 3, 6, 7, 115], "write": 35, "x": [39, 63, 69], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 117, "xcr3064xl": 118, "xcr3128xl": 119, "xcr3256xl": 120, "xcr3384xl": 121, "xcr3512xl": 122, "xilinx": [11, 33, 37, 124], "xor": [14, 36], "xpla3": 124, "xv": [16, 35, 36], "zia": 127}})
\ No newline at end of file
+Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM.S3": [[38, "bram-s3"]], "BRAM.S3A": [[38, "bram-s3a"]], "BRAM.S3ADSP": [[38, "bram-s3adsp"]], "BRAM.S3E": [[38, "bram-s3e"]], "Backbone": [[48, "backbone"], [71, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[57, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [39, "bitstream"], [46, "bitstream"], [52, "bitstream"], [55, "bitstream"], [58, "bitstream"], [60, "bitstream"], [62, "bitstream"], [63, "bitstream"], [68, "bitstream"], [69, "bitstream"], [77, "bitstream"], [78, "bitstream"], [79, "bitstream"], [80, "bitstream"], [83, "bitstream"], [84, "bitstream"], [86, "bitstream"], [87, "bitstream"], [88, "bitstream"], [89, "bitstream"], [93, "bitstream"], [94, "bitstream"], [96, "bitstream"], [97, "bitstream"], [98, "bitstream"], [99, "bitstream"], [100, "bitstream"], [103, "bitstream"], [104, "bitstream"], [106, "bitstream"], [107, "bitstream"], [108, "bitstream"], [110, "bitstream"], [112, "bitstream"], [114, "bitstream"]], "Bitstream geometry": [[51, "bitstream-geometry"], [76, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [115, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 CLBLL": [[90, "bitstream-clbll"], [101, "bitstream-clbll"], [109, "bitstream-clbll"]], "Bitstream \u2014 CLBLM": [[90, "bitstream-clblm"], [101, "bitstream-clblm"], [109, "bitstream-clblm"]], "Bitstream \u2014 CLEXL": [[53, "bitstream-clexl"]], "Bitstream \u2014 CLEXM": [[53, "bitstream-clexm"]], "Bitstream \u2014 CLKC": [[54, "bitstream-clkc"]], "Bitstream \u2014 DCM_BUFPLL": [[54, "bitstream-dcm-bufpll"]], "Bitstream \u2014 HCLK": [[54, "bitstream-hclk"]], "Bitstream \u2014 HCLK_ROW": [[54, "bitstream-hclk-row"]], "Bitstream \u2014 INTF": [[96, "bitstream-intf"], [106, "bitstream-intf"], [112, "bitstream-intf"]], "Bitstream \u2014 INTF.BRAM": [[112, "bitstream-intf-bram"]], "Bitstream \u2014 INTF.DELAY": [[96, "bitstream-intf-delay"], [106, "bitstream-intf-delay"], [112, "bitstream-intf-delay"]], "Bitstream \u2014 IOI tile": [[57, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[48, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[48, "bitstream-llv-tiles"]], "Bitstream \u2014 PCILOGICSE": [[54, "bitstream-pcilogicse"]], "Bitstream \u2014 PLL_BUFPLL_B": [[54, "bitstream-pll-bufpll-b"]], "Bitstream \u2014 PLL_BUFPLL_OUT0": [[54, "bitstream-pll-bufpll-out0"]], "Bitstream \u2014 PLL_BUFPLL_OUT1": [[54, "bitstream-pll-bufpll-out1"]], "Bitstream \u2014 PLL_BUFPLL_T": [[54, "bitstream-pll-bufpll-t"]], "Bitstream \u2014 PMVIOB": [[100, "bitstream-pmviob"]], "Bitstream \u2014 PowerPC hole tiles": [[71, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 bottom tile": [[54, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[40, "bitstream-bottom-tiles"], [64, "bitstream-bottom-tiles"]], "Bitstream \u2014 interconnect tiles": [[48, "bitstream-interconnect-tiles"], [71, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[86, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[48, "bitstream-interface-tiles"], [71, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[59, "bitstream-left-side"]], "Bitstream \u2014 left tile": [[54, "bitstream-left-tile"]], "Bitstream \u2014 left tiles": [[40, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[59, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[57, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[59, "bitstream-right-side"]], "Bitstream \u2014 right tile": [[54, "bitstream-right-tile"]], "Bitstream \u2014 right tiles": [[40, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[71, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[54, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[40, "bitstream-top-tiles"], [64, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[38, "block-ram"], [52, "block-ram"], [77, "block-ram"], [88, "block-ram"], [99, "block-ram"], [108, "block-ram"]], "Block RAM \u2014 Virtex": [[59, "block-ram-virtex"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[62, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [116, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [126, "boundary-scan-register"]], "CCM": [[78, "ccm"]], "CLKB.S3": [[40, "clkb-s3"]], "CLKB.S3A": [[40, "clkb-s3a"]], "CLKB.S3E": [[40, "clkb-s3e"]], "CLKB.V2": [[64, "clkb-v2"]], "CLKB.V2P": [[64, "clkb-v2p"]], "CLKB.V2PX": [[64, "clkb-v2px"]], "CLKL.S3A": [[40, "clkl-s3a"]], "CLKL.S3E": [[40, "clkl-s3e"]], "CLKR.S3A": [[40, "clkr-s3a"]], "CLKR.S3E": [[40, "clkr-s3e"]], "CLKT.S3": [[40, "clkt-s3"]], "CLKT.S3A": [[40, "clkt-s3a"]], "CLKT.S3E": [[40, "clkt-s3e"]], "CLKT.V2": [[64, "clkt-v2"]], "CLKT.V2P": [[64, "clkt-v2p"]], "CLKT.V2PX": [[64, "clkt-v2px"]], "CLK_CMT_B": [[91, "clk-cmt-b"]], "CLK_CMT_T": [[91, "clk-cmt-t"]], "CLK_DCM_B": [[81, "clk-dcm-b"]], "CLK_DCM_T": [[81, "clk-dcm-t"]], "CLK_HROW": [[81, "clk-hrow"], [91, "clk-hrow"]], "CLK_IOB_B": [[81, "clk-iob-b"], [91, "clk-iob-b"]], "CLK_IOB_T": [[81, "clk-iob-t"], [91, "clk-iob-t"]], "CLK_MGT_B": [[91, "clk-mgt-b"]], "CLK_MGT_T": [[91, "clk-mgt-t"]], "CLK_TERM_B": [[81, "clk-term-b"]], "CLK_TERM_T": [[81, "clk-term-t"]], "COR": [[65, "cor"], [82, "cor"], [92, "cor"], [102, "cor"]], "COR.S3": [[41, "cor-s3"]], "COR.S3E": [[41, "cor-s3e"]], "COR1": [[92, "cor1"], [102, "cor1"]], "COR1.S3A": [[42, "cor1-s3a"]], "COR2.S3A": [[42, "cor2-s3a"]], "CTL": [[65, "ctl"], [82, "ctl"], [92, "ctl"], [102, "ctl"]], "CTL.S3": [[41, "ctl-s3"]], "CTL.S3A": [[42, "ctl-s3a"]], "CTL1": [[102, "ctl1"]], "Carry logic": [[39, "carry-logic"], [63, "carry-logic"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[40, "clock-interconnect"], [54, "clock-interconnect"], [64, "clock-interconnect"], [81, "clock-interconnect"], [91, "clock-interconnect"]], "Clock rows": [[51, "clock-rows"], [76, "clock-rows"]], "Clock source \u2014 left and right": [[40, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[40, "clock-source-spine-bottom-and-top"], [64, "clock-source-spine-bottom-and-top"]], "Clock spine": [[76, "clock-spine"]], "Clock spine top and bottom": [[71, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[39, "configurable-logic-block"], [53, "configurable-logic-block"], [63, "configurable-logic-block"], [80, "configurable-logic-block"], [90, "configurable-logic-block"], [101, "configurable-logic-block"], [109, "configurable-logic-block"]], "Configurable Logic Block \u2014 Virtex": [[60, "configurable-logic-block-virtex"]], "Configuration Center": [[79, "configuration-center"], [89, "configuration-center"], [100, "configuration-center"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Configuration registers": [[65, "configuration-registers"], [82, "configuration-registers"], [92, "configuration-registers"], [102, "configuration-registers"]], "Configuration registers \u2014 Spartan 3, Spartan 3E": [[41, "configuration-registers-spartan-3-spartan-3e"]], "Configuration registers \u2014 Spartan 3A and 3A DSP": [[42, "configuration-registers-spartan-3a-and-3a-dsp"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [37, null], [47, null], [56, null], [61, null], [70, null], [85, null], [95, null], [105, null], [111, null], [123, null], [124, null]], "Corners": [[43, "corners"], [66, "corners"]], "DCM": [[83, "dcm"]], "DCM output bus": [[64, "dcm-output-bus"]], "DCM.S3": [[44, "dcm-s3"]], "DCM.S3E.BL": [[45, "dcm-s3e-bl"]], "DCM.S3E.BR": [[45, "dcm-s3e-br"]], "DCM.S3E.LB": [[45, "dcm-s3e-lb"]], "DCM.S3E.LT": [[45, "dcm-s3e-lt"]], "DCM.S3E.RB": [[45, "dcm-s3e-rb"]], "DCM.S3E.RT": [[45, "dcm-s3e-rt"]], "DCM.S3E.TL": [[45, "dcm-s3e-tl"]], "DCM.S3E.TR": [[45, "dcm-s3e-tr"]], "DCM.V2": [[67, "dcm-v2"]], "DCM.V2P": [[67, "dcm-v2p"]], "DCMCONN.BOT": [[64, "dcmconn-bot"]], "DCMCONN.TOP": [[64, "dcmconn-top"]], "DESKEW_ADJUST": [[44, "deskew-adjust"], [45, "deskew-adjust"], [67, "deskew-adjust"]], "DSP": [[46, "dsp"], [55, "dsp"], [84, "dsp"], [93, "dsp"], [103, "dsp"], [110, "dsp"]], "Database schema": [[17, "database-schema"], [116, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [123, "database-devices"]], "Default option attributes": [[40, "default-option-attributes"]], "Default option values": [[38, "default-option-values"]], "Device": [[17, "device"], [116, "device"]], "Device geometry": [[51, "device-geometry"], [76, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [125, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [127, "device-structure"]], "Device table": [[49, "device-table"], [72, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [125, "devices"]], "Digital Clock Managers": [[67, "digital-clock-managers"]], "Digital Clock Managers \u2014 Spartan 3": [[44, "digital-clock-managers-spartan-3"]], "Digital Clock Managers \u2014 Spartan 3E, 3A": [[45, "digital-clock-managers-spartan-3e-3a"]], "Dual-port 16\u00d7X RAM": [[39, "dual-port-16x-ram"], [63, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[63, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[63, "dual-port-641-ram"]], "ECC mode": [[77, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "Ethernet MACs": [[94, "ethernet-macs"], [104, "ethernet-macs"]], "FB columns and rows": [[127, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[127, "fclk-networks"]], "FIFO mode": [[77, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[115, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[115, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[115, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [115, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[115, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[64, "gclkc"]], "GCLKC.B": [[64, "gclkc-b"]], "GCLKC.T": [[64, "gclkc-t"]], "GCLKH": [[40, "gclkh"], [64, "gclkh"]], "GCLKH.N": [[40, "gclkh-n"]], "GCLKH.S": [[40, "gclkh-s"]], "GCLKH.UNI": [[40, "gclkh-uni"]], "GCLKH.UNI.N": [[40, "gclkh-uni-n"]], "GCLKH.UNI.S": [[40, "gclkh-uni-s"]], "GCLKVM.S3": [[40, "gclkvm-s3"]], "GCLKVM.S3E": [[40, "gclkvm-s3e"]], "GENERAL[12]": [[42, "general-12"]], "GIGABIT.B": [[68, "gigabit-b"]], "GIGABIT.T": [[68, "gigabit-t"]], "GIGABIT10.B": [[69, "gigabit10-b"]], "GIGABIT10.T": [[69, "gigabit10-t"]], "General Interconnect": [[86, "general-interconnect"]], "General interconnect": [[48, "general-interconnect"], [57, "general-interconnect"], [71, "general-interconnect"]], "General structure": [[51, "general-structure"], [76, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [117, "global-bits"], [118, "global-bits"], [119, "global-bits"], [120, "global-bits"], [121, "global-bits"], [122, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "HCLK": [[81, "hclk"], [91, "hclk"]], "HCLK_CENTER": [[81, "hclk-center"]], "HCLK_CENTER_ABOVE_CFG": [[81, "hclk-center-above-cfg"]], "HCLK_CMT": [[91, "hclk-cmt"]], "HCLK_CMT_IOI": [[91, "hclk-cmt-ioi"]], "HCLK_DCM": [[81, "hclk-dcm"]], "HCLK_DCMIOB": [[81, "hclk-dcmiob"]], "HCLK_IOBDCM": [[81, "hclk-iobdcm"]], "HCLK_IOI": [[91, "hclk-ioi"]], "HCLK_IOIS_DCI": [[81, "hclk-iois-dci"]], "HCLK_IOIS_LVDS": [[81, "hclk-iois-lvds"]], "HCLK_IOI_BOTCEN": [[91, "hclk-ioi-botcen"]], "HCLK_IOI_CENTER": [[91, "hclk-ioi-center"]], "HCLK_IOI_CMT": [[91, "hclk-ioi-cmt"]], "HCLK_IOI_TOPCEN": [[91, "hclk-ioi-topcen"]], "HCLK_TERM_L": [[81, "hclk-term-l"]], "HCLK_TERM_R": [[81, "hclk-term-r"]], "HC_OPT": [[42, "hc-opt"]], "Hard PCI logic": [[74, "hard-pci-logic"]], "Hard PowerPC 405 cores": [[75, "hard-powerpc-405-cores"]], "Horizontal clock spine": [[51, "horizontal-clock-spine"]], "I/O buffers": [[73, "i-o-buffers"]], "I/O buffers \u2014 Spartan 3": [[50, "i-o-buffers-spartan-3"]], "I/O buffers \u2014 Spartan 3A": [[50, "i-o-buffers-spartan-3a"]], "I/O buffers \u2014 Spartan 3E": [[50, "i-o-buffers-spartan-3e"]], "I/O buffers \u2014 Virtex 2 Pro": [[73, "i-o-buffers-virtex-2-pro"]], "I/O data \u2014 Spartan 3": [[43, "i-o-data-spartan-3"]], "I/O data \u2014 Spartan 3A": [[43, "i-o-data-spartan-3a"]], "I/O data \u2014 Spartan 3E": [[43, "i-o-data-spartan-3e"]], "I/O data \u2014 Virtex 2": [[66, "i-o-data-virtex-2"]], "I/O data \u2014 Virtex 2 Pro": [[66, "i-o-data-virtex-2-pro"]], "I/O interface": [[50, "i-o-interface"], [73, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [117, "i-o-pins"], [118, "i-o-pins"], [119, "i-o-pins"], [120, "i-o-pins"], [121, "i-o-pins"], [122, "i-o-pins"]], "IDCODE": [[35, "idcode"], [126, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [117, "imux-bits"], [118, "imux-bits"], [119, "imux-bits"], [120, "imux-bits"], [121, "imux-bits"], [122, "imux-bits"]], "INT.BRAM": [[71, "int-bram"]], "INT.BRAM.S3": [[48, "int-bram-s3"]], "INT.BRAM.S3A.03": [[48, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[48, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[48, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[48, "int-bram-s3e"]], "INT.CLB": [[48, "int-clb"], [71, "int-clb"]], "INT.CNR": [[71, "int-cnr"]], "INT.DCM": [[48, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[48, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[71, "int-dcm-v2"]], "INT.DCM.V2P": [[71, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[71, "int-gt-clkpad"]], "INT.IOI": [[71, "int-ioi"]], "INT.IOI.CLK_B": [[71, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[71, "int-ioi-clk-t"]], "INT.IOI.S3": [[48, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[48, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[48, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[48, "int-ioi-s3e"]], "INT.PPC": [[71, "int-ppc"]], "INTF": [[57, "intf"]], "INTF.CMT": [[57, "intf-cmt"]], "INTF.CMT.IOI": [[57, "intf-cmt-ioi"]], "INTF.DSP": [[48, "intf-dsp"]], "INTF.GT.B0": [[71, "intf-gt-b0"]], "INTF.GT.B123": [[71, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[71, "intf-gt-bclkpad"]], "INTF.GT.T0": [[71, "intf-gt-t0"]], "INTF.GT.T123": [[71, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[71, "intf-gt-tclkpad"]], "INTF.IOI": [[57, "intf-ioi"]], "INTF.PPC": [[71, "intf-ppc"]], "IO banks and IO buffers": [[51, "io-banks-and-io-buffers"], [76, "io-banks-and-io-buffers"]], "IO clock nodes": [[81, "io-clock-nodes"], [91, "io-clock-nodes"]], "IOBS.S3.B2": [[50, "iobs-s3-b2"]], "IOBS.S3.L1": [[50, "iobs-s3-l1"]], "IOBS.S3.R1": [[50, "iobs-s3-r1"]], "IOBS.S3.T2": [[50, "iobs-s3-t2"]], "IOBS.S3A.B2": [[50, "iobs-s3a-b2"]], "IOBS.S3A.L4": [[50, "iobs-s3a-l4"]], "IOBS.S3A.R4": [[50, "iobs-s3a-r4"]], "IOBS.S3A.T2": [[50, "iobs-s3a-t2"]], "IOBS.S3E.B1": [[50, "iobs-s3e-b1"]], "IOBS.S3E.B2": [[50, "iobs-s3e-b2"]], "IOBS.S3E.B3": [[50, "iobs-s3e-b3"]], "IOBS.S3E.B4": [[50, "iobs-s3e-b4"]], "IOBS.S3E.L1": [[50, "iobs-s3e-l1"]], "IOBS.S3E.L2": [[50, "iobs-s3e-l2"]], "IOBS.S3E.L3": [[50, "iobs-s3e-l3"]], "IOBS.S3E.L4": [[50, "iobs-s3e-l4"]], "IOBS.S3E.R1": [[50, "iobs-s3e-r1"]], "IOBS.S3E.R2": [[50, "iobs-s3e-r2"]], "IOBS.S3E.R3": [[50, "iobs-s3e-r3"]], "IOBS.S3E.R4": [[50, "iobs-s3e-r4"]], "IOBS.S3E.T1": [[50, "iobs-s3e-t1"]], "IOBS.S3E.T2": [[50, "iobs-s3e-t2"]], "IOBS.S3E.T3": [[50, "iobs-s3e-t3"]], "IOBS.S3E.T4": [[50, "iobs-s3e-t4"]], "IOBS.V2.B.L2": [[73, "iobs-v2-b-l2"]], "IOBS.V2.B.R2": [[73, "iobs-v2-b-r2"]], "IOBS.V2.L.B2": [[73, "iobs-v2-l-b2"]], "IOBS.V2.L.T2": [[73, "iobs-v2-l-t2"]], "IOBS.V2.R.B2": [[73, "iobs-v2-r-b2"]], "IOBS.V2.R.T2": [[73, "iobs-v2-r-t2"]], "IOBS.V2.T.L2": [[73, "iobs-v2-t-l2"]], "IOBS.V2.T.R2": [[73, "iobs-v2-t-r2"]], "IOBS.V2P.B.L1": [[73, "iobs-v2p-b-l1"]], "IOBS.V2P.B.L1.ALT": [[73, "iobs-v2p-b-l1-alt"]], "IOBS.V2P.B.L2": [[73, "iobs-v2p-b-l2"]], "IOBS.V2P.B.R1": [[73, "iobs-v2p-b-r1"]], "IOBS.V2P.B.R1.ALT": [[73, "iobs-v2p-b-r1-alt"]], "IOBS.V2P.B.R2": [[73, "iobs-v2p-b-r2"]], "IOBS.V2P.B.R2.CLK": [[73, "iobs-v2p-b-r2-clk"]], "IOBS.V2P.L.B2": [[73, "iobs-v2p-l-b2"]], "IOBS.V2P.L.T2": [[73, "iobs-v2p-l-t2"]], "IOBS.V2P.R.B2": [[73, "iobs-v2p-r-b2"]], "IOBS.V2P.R.T2": [[73, "iobs-v2p-r-t2"]], "IOBS.V2P.T.L1": [[73, "iobs-v2p-t-l1"]], "IOBS.V2P.T.L1.ALT": [[73, "iobs-v2p-t-l1-alt"]], "IOBS.V2P.T.L2": [[73, "iobs-v2p-t-l2"]], "IOBS.V2P.T.R1": [[73, "iobs-v2p-t-r1"]], "IOBS.V2P.T.R1.ALT": [[73, "iobs-v2p-t-r1-alt"]], "IOBS.V2P.T.R2": [[73, "iobs-v2p-t-r2"]], "IOBS.V2P.T.R2.CLK": [[73, "iobs-v2p-t-r2-clk"]], "IOI": [[73, "ioi"]], "IOI.CLK_B": [[73, "ioi-clk-b"]], "IOI.CLK_T": [[73, "ioi-clk-t"]], "IOI.S3": [[50, "ioi-s3"]], "IOI.S3A.B": [[50, "ioi-s3a-b"]], "IOI.S3A.LR": [[50, "ioi-s3a-lr"]], "IOI.S3A.T": [[50, "ioi-s3a-t"]], "IOI.S3E": [[50, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [126, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [126, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output": [[50, "input-output"], [73, "input-output"]], "Input multiplexers": [[48, "input-multiplexers"], [71, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [127, "input-output-buffer"]], "Interconnect": [[96, "interconnect"], [106, "interconnect"], [112, "interconnect"]], "Introduction": [[12, "introduction"], [34, "introduction"], [49, "introduction"], [72, "introduction"], [125, "introduction"]], "JED bits": [[116, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [115, "jed-mapping"], [117, "jed-mapping"], [118, "jed-mapping"], [119, "jed-mapping"], [120, "jed-mapping"], [121, "jed-mapping"], [122, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[115, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[115, "jed-mapping-macrocells-without-iob"]], "JED structure": [[115, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [126, "jtag-interface"]], "LL.S3": [[43, "ll-s3"]], "LL.S3A": [[43, "ll-s3a"]], "LL.S3E": [[43, "ll-s3e"]], "LL.V2": [[66, "ll-v2"]], "LL.V2P": [[66, "ll-v2p"]], "LLH": [[48, "llh"]], "LLH.CLKB.S3A": [[48, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[48, "llh-clkt-s3a"]], "LLV.S3A": [[48, "llv-s3a"]], "LLV.S3E": [[48, "llv-s3e"]], "LR.S3": [[43, "lr-s3"]], "LR.S3A": [[43, "lr-s3a"]], "LR.S3E": [[43, "lr-s3e"]], "LR.V2": [[66, "lr-v2"]], "LR.V2P": [[66, "lr-v2p"]], "LUT RAM": [[39, "lut-ram"], [63, "lut-ram"]], "LUTs": [[39, "luts"], [63, "luts"]], "Local control terms": [[127, "local-control-terms"]], "Long line splitters": [[48, "long-line-splitters"]], "Lower left": [[43, "lower-left"], [66, "lower-left"]], "Lower right": [[43, "lower-right"], [66, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "MGT clock repeater": [[81, "mgt-clock-repeater"], [91, "mgt-clock-repeater"]], "MODE": [[42, "mode"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [127, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [127, "misc-configuration"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro": [[68, "multi-gigabit-transceivers-virtex-2-pro"]], "Multi-gigabit transceivers \u2014 Virtex 2 Pro X": [[69, "multi-gigabit-transceivers-virtex-2-pro-x"]], "Output multiplexers": [[63, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[39, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[39, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [127, "overview"]], "PCI Express": [[58, "pci-express"]], "PCI Express Gen2 cores": [[113, "pci-express-gen2-cores"]], "PCI Express Gen3 cores": [[114, "pci-express-gen3-cores"]], "PCI Express cores": [[97, "pci-express-cores"], [107, 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88, 99, 108], "9950": [38, 52, 62, 77, 88, 99, 108], "9951": [38, 52, 62, 77, 88, 99, 108], "9952": [38, 52, 62, 77, 88, 99, 108], "9953": [38, 52, 62, 77, 88, 99, 108], "9954": [38, 52, 62, 77, 88, 99, 108], "9955": [38, 52, 62, 77, 88, 99, 108], "9956": [38, 52, 62, 77, 88, 99, 108], "9957": [38, 52, 62, 77, 88, 99, 108], "9958": [38, 52, 62, 77, 88, 99, 108], "9959": [38, 52, 62, 77, 88, 99, 108], "996": [38, 52, 59, 62, 77, 88, 99, 108], "9960": [38, 52, 62, 77, 88, 99, 108], "9961": [38, 52, 62, 77, 88, 99, 108], "9962": [38, 52, 62, 77, 88, 99, 108], "9963": [38, 52, 62, 77, 88, 99, 108], "9964": [38, 52, 62, 77, 88, 99, 108], "9965": [38, 52, 62, 77, 88, 99, 108], "9966": [38, 52, 62, 77, 88, 99, 108], "9967": [38, 52, 62, 77, 88, 99, 108], "9968": [38, 52, 62, 77, 88, 99, 108], "9969": [38, 52, 62, 77, 88, 99, 108], "997": [38, 52, 59, 62, 77, 88, 99, 108], "9970": [38, 52, 62, 77, 88, 99, 108], "9971": [38, 52, 62, 77, 88, 99, 108], "9972": [38, 52, 62, 77, 88, 99, 108], "9973": [38, 52, 62, 77, 88, 99, 108], "9974": [38, 52, 62, 77, 88, 99, 108], "9975": [38, 52, 62, 77, 88, 99, 108], "9976": [38, 52, 62, 77, 88, 99, 108], "9977": [38, 52, 62, 77, 88, 99, 108], "9978": [38, 52, 62, 77, 88, 99, 108], "9979": [38, 52, 62, 77, 88, 99, 108], "998": [38, 52, 59, 62, 77, 88, 99, 108], "9980": [38, 52, 62, 77, 88, 99, 108], "9981": [38, 52, 62, 77, 88, 99, 108], "9982": [38, 52, 62, 77, 88, 99, 108], "9983": [38, 52, 62, 77, 88, 99, 108], "9984": [38, 52, 62, 77, 88, 99, 108], "9985": [38, 52, 62, 77, 88, 99, 108], "9986": [38, 52, 62, 77, 88, 99, 108], "9987": [38, 52, 62, 77, 88, 99, 108], "9988": [38, 52, 62, 77, 88, 99, 108], "9989": [38, 52, 62, 77, 88, 99, 108], "999": [38, 52, 59, 62, 77, 88, 99, 108], "9990": [38, 52, 62, 77, 88, 99, 108], "9991": [38, 52, 62, 77, 88, 99, 108], "9992": [38, 52, 62, 77, 88, 99, 108], "9993": [38, 52, 62, 77, 88, 99, 108], "9994": [38, 52, 62, 77, 88, 99, 108], "9995": [38, 52, 62, 77, 88, 99, 108], "9996": [38, 52, 62, 77, 88, 99, 108], "9997": [38, 52, 62, 77, 88, 99, 108], "9998": [38, 52, 62, 77, 88, 99, 108], "9999": [38, 52, 62, 77, 88, 99, 108], "9_32000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 69, "9_64000000001111111111001101010101001100101000010101000001001101010100000010000010001100100100000101000011010100010101101000": 69, "9ce_mux": 115, "9fb_group": [117, 118, 119, 120, 121, 122], "9foe2_mux": [4, 5, 8, 9], "9fsr_enabl": [2, 3, 6, 7], "9ibuf_mod": [2, 3, 6, 7], "9int": 48, "9lct5_inv": 115, "9reg_d_ireg": 115, "9reg_init": [2, 3, 6, 7], "9reg_mod": [4, 5, 8, 9], "9rowcolumn": [79, 81, 89, 97, 100, 113, 114], "9rowcolumn012345678910111213141516171819202122": 58, "9rowcolumn0123456789101112131415161718192021222324252627": [94, 98, 104, 107], "9rowcolumn01234567891011121314151617181920212223242526272829": 113, "A": [12, 14, 17, 35, 36, 39, 51, 62, 63, 76, 77, 116, 127], "AED": [12, 125], "AND": [2, 6, 7, 16, 33, 34, 35, 36, 63, 127], "As": [35, 127], "BY": [39, 48, 63, 71], "For": [34, 35, 36, 48, 51, 71, 76, 127], "ISE": [35, 127], "IT": 71, "If": [35, 36, 62, 63, 77, 127], "In": [15, 16, 36, 39, 48, 63, 71, 127], "It": [12, 34, 35, 36, 39, 40, 48, 51, 62, 63, 71, 76, 77, 116, 125, 127], "Its": [35, 62], "Not": [15, 16, 36, 48, 71, 127], "OR": [2, 6, 7, 36], "On": [12, 15, 16, 36, 39, 40, 48, 51, 62, 76, 127], "Such": [35, 48, 51, 76], "The": [12, 13, 15, 16, 17, 34, 35, 36, 38, 39, 46, 47, 48, 49, 51, 55, 63, 70, 71, 72, 76, 77, 80, 115, 116, 125, 126, 127], "Their": [39, 63], "There": [17, 35, 39, 48, 49, 62, 63, 71, 72], "These": [36, 71], "To": [35, 36, 77], "_": [17, 34, 36, 116, 127], "_chain_down": 36, "_chain_up": 36, "_enabl": [36, 115, 127], "_gclk": 127, "_init": [39, 63], "_inv": [36, 127], "_lct": 127, "_mc": [12, 125], "_mux": [36, 39, 63], "_none": 127, "_reg": [62, 77], "_srval": [39, 63], "_sum": 36, "a0mux": 38, "a0reg": [46, 55], "a1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a10mux": 38, "a11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a11mux": 38, "a12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a12mux": 38, "a13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 119, 120, 121, 122], "a13mux": 38, "a14": [2, 3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a14mux": 38, "a15": [3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a15mux": 38, "a16": [3, 6, 7, 22, 23, 24, 25, 120, 121, 122], "a16mux": 38, "a17": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a17mux": 38, "a18": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a19": [6, 7, 22, 23, 24, 25, 120, 121, 122], "a1mux": 38, "a1reg": [46, 55], "a2": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a20": [6, 7, 22, 23, 24, 121, 122], "a21": [6, 7, 22, 23, 121, 122], "a22": [6, 7, 22, 23, 121, 122], "a23": [22, 23], "a24": [22, 23], "a25": [22, 23], "a26": [22, 23], "a2mux": 38, "a3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a3mux": 38, "a4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a4mux": 38, "a5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a5ffinit": [101, 109], "a5ffinitslice0": [101, 109], "a5ffmux": [101, 109], "a5ffsr": [101, 109], "a5ffsrinit": 53, "a5ffsrinitslice0": 53, "a5ffsrslice1": 101, "a5mux": 38, "a5q0": 53, "a5q0100": [53, 101, 109], "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a6lut": [53, 90, 101, 109], "a6mux": 38, "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 117, 118, 119, 120, 121, 122], "a7mux": 38, "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a8mux": 38, "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 118, 119, 120, 121, 122], "a9mux": 38, "a_input": [93, 103, 110], "a_q": 62, "aa1": [6, 7, 22, 23, 121, 122], "aa10": [6, 7, 121, 122], "aa11": [6, 7, 121, 122], "aa12": [6, 7, 121, 122], "aa13": [6, 7, 121, 122], "aa14": [6, 7, 121, 122], "aa15": [6, 7, 121, 122], "aa16": [6, 7, 121, 122], "aa17": [6, 7, 121, 122], "aa18": [6, 7, 121, 122], "aa19": [6, 7, 121, 122], "aa2": [6, 7, 22, 23, 121, 122], "aa20": [6, 7, 121, 122], "aa21": [6, 7, 121, 122], "aa22": [6, 7, 121, 122], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 121, 122], "aa4": [6, 7, 22, 23, 121, 122], "aa5": [6, 7, 121, 122], "aa6": [6, 7, 121, 122], "aa7": [6, 7, 121, 122], "aa8": [6, 7, 121, 122], "aa9": [6, 7, 121, 122], "ab": [62, 71, 77], "ab1": [6, 7, 22, 23, 121, 122], "ab10": [6, 7, 121, 122], "ab11": [6, 7, 121, 122], "ab12": [6, 7, 121, 122], "ab13": [6, 7, 121, 122], "ab14": [6, 7, 121, 122], "ab15": [6, 7, 121, 122], "ab16": [6, 7, 121, 122], "ab17": [6, 7, 121, 122], "ab18": [6, 7, 121, 122], "ab19": [6, 7, 121, 122], "ab2": [6, 7, 22, 23, 121, 122], "ab20": [6, 7, 121, 122], "ab21": [6, 7, 121, 122], "ab22": [6, 7, 121, 122], "ab23": [22, 23], "ab24": [22, 23], "ab25": [22, 23], "ab26": [22, 23], "ab3": [6, 7, 22, 23, 121, 122], "ab4": [6, 7, 22, 23, 121, 122], "ab5": [6, 7, 121, 122], "ab6": [6, 7, 121, 122], "ab7": [6, 7, 121, 122], "ab8": [6, 7, 121, 122], "ab9": [6, 7, 121, 122], "abort": 35, "about": 35, "abov": [35, 39, 48, 51, 62, 63, 71, 76, 127], "abp": 62, "abs_freq_ref11": 83, "abs_freq_snapshot10": 83, "absolut": 116, "ac1": [22, 23], "ac10": [22, 23], "ac11": [22, 23], "ac12": [22, 23], "ac13": [22, 23], "ac14": [22, 23], "ac15": [22, 23], "ac16": [22, 23], "ac17": [22, 23], "ac18": [22, 23], "ac19": [22, 23], "ac2": [22, 23], "ac20": [22, 23], "ac21": [22, 23], "ac22": [22, 23], "ac23": [22, 23], "ac24": [22, 23], "ac25": [22, 23], "ac26": [22, 23], "ac3": [22, 23], "ac4": [22, 23], "ac5": [22, 23], "ac6": [22, 23], "ac7": [22, 23], "ac8": [22, 23], "ac9": [22, 23], "acb": [12, 34, 125], "accept": 71, "access": [35, 48, 49, 71, 72], "accordingli": 36, "acd": 34, "acquir": 125, "across": [12, 34, 36, 38, 39, 46, 51, 55, 62, 63, 71, 76, 77, 116, 125, 127], "activ": [35, 36, 39, 63, 126], "activelanesin": 97, "actual": [15, 16, 35, 48, 51, 62, 71, 127], "acy0": [53, 90, 101, 109], "acy0slice0": [90, 101, 109], "acy0slice1": [53, 101], "ad": [48, 49, 51, 62, 71, 72], "ad1": [22, 23], "ad10": [22, 23], "ad11": [22, 23], "ad12": [22, 23], "ad13": [22, 23], "ad14": [22, 23], "ad15": [22, 23], "ad16": [22, 23], "ad17": [22, 23], "ad18": [22, 23], "ad19": [22, 23], "ad2": [22, 23], "ad20": [22, 23], "ad21": [22, 23], "ad22": [22, 23], "ad23": [22, 23], "ad24": [22, 23], "ad25": [22, 23], "ad26": [22, 23], "ad3": [22, 23], "ad4": [22, 23], "ad5": [22, 23], "ad6": [22, 23], "ad7": [22, 23], "ad8": [22, 23], "ad9": [22, 23], "adc10": 87, "add": 72, "addit": [12, 14, 34, 36, 51, 62, 77, 127], "addition": [34, 35, 36, 39, 48, 63, 71, 72, 76], "addr": [15, 16, 62, 77], "addr_cascade_out_a": 108, "addr_cascade_out_abram": 108, "addr_cascade_out_b": 108, "addr_cascade_out_bbram": 108, "addral0": 108, "addral1": 108, "addral10": 108, "addral11": 108, "addral12": 108, "addral13": 108, "addral14": 108, "addral2": 108, "addral3": 108, "addral4": 108, "addral5": 108, "addral6": 108, "addral7": 108, "addral8": 108, "addral9": 108, "addrau0": 108, "addrau1": 108, "addrau10": 108, "addrau11": 108, "addrau12": 108, "addrau13": 108, "addrau14": 108, "addrau2": 108, "addrau3": 108, "addrau4": 108, "addrau5": 108, "addrau6": 108, "addrau7": 108, "addrau8": 108, "addrau9": 108, "addrbl0": 108, "addrbl1": 108, "addrbl10": 108, "addrbl11": 108, "addrbl12": 108, "addrbl13": 108, "addrbl14": 108, "addrbl2": 108, "addrbl3": 108, "addrbl4": 108, "addrbl5": 108, "addrbl6": 108, "addrbl7": 108, "addrbl8": 108, "addrbl9": 108, "addrbu0": 108, "addrbu1": 108, "addrbu10": 108, "addrbu11": 108, "addrbu12": 108, "addrbu13": 108, "addrbu14": 108, "addrbu2": 108, "addrbu3": 108, "addrbu4": 108, "addrbu5": 108, "addrbu6": 108, "addrbu7": 108, "addrbu8": 108, "addrbu9": 108, "address": [15, 16, 35, 39, 62, 63, 71, 77], "adi1mux": [53, 90, 101, 109], "adi1muxslice0": [53, 90, 101], "adjac": [48, 71, 77], "adreg": [103, 110], "adregdsp0": 103, "adregdsp1": 103, "advanc": 14, "ae1": [22, 23], "ae10": [22, 23], "ae11": [22, 23], "ae12": [22, 23], "ae13": [22, 23], "ae14": [22, 23], "ae15": [22, 23], "ae16": [22, 23], "ae17": [22, 23], "ae18": [22, 23], "ae19": [22, 23], "ae2": [22, 23], "ae20": [22, 23], "ae21": [22, 23], "ae22": [22, 23], "ae23": [22, 23], "ae24": [22, 23], "ae25": [22, 23], "ae26": [22, 23], "ae3": [22, 23], "ae4": [22, 23], "ae5": [22, 23], "ae6": [22, 23], "ae7": [22, 23], "ae8": [22, 23], "ae9": [22, 23], "aer_base_ptr": [107, 113], "aer_cap_ecrc_check_cap": [107, 113], "aer_cap_ecrc_check_capablepci": [107, 113], "aer_cap_ecrc_gen_cap": [107, 113], "aer_cap_id": [107, 113], "aer_cap_int_msg_num_msi": 107, "aer_cap_int_msg_num_msix": 107, "aer_cap_multihead": 113, "aer_cap_nextptr": [107, 113], "aer_cap_on": [107, 113], "aer_cap_optional_err_support": 113, "aer_cap_permit_rooterr_upd": [107, 113], "aer_cap_permit_rooterr_updatepci": [107, 113], "aer_cap_vers": [107, 113], "aerbaseptr": 97, "aercapabilityecrccheckcap": 97, "aercapabilityecrcgencap": 97, "aercapabilityecrcgencapablepci": 97, "aercapabilitynextptr": 97, "af1": [22, 23], "af10": [22, 23], "af11": [22, 23], "af12": [22, 23], "af13": [22, 23], "af14": [22, 23], "af15": [22, 23], "af16": [22, 23], "af17": [22, 23], "af18": [22, 23], "af19": [22, 23], "af2": [22, 23], "af20": [22, 23], "af21": [22, 23], "af22": [22, 23], "af23": [22, 23], "af24": [22, 23], "af25": [22, 23], "af26": [22, 23], "af3": [22, 23], "af4": [22, 23], "af5": [22, 23], "af6": [22, 23], "af7": [22, 23], "af8": [22, 23], "af9": [22, 23], "aff_latch": 101, "aff_latchslice0": 101, "affect": [36, 71, 127], "affinit": [90, 101, 109], "affinitslice0": [90, 101, 109], "affinitslice1": 101, "affmux": [53, 90, 101, 109], "affmuxslice1": 53, "affsr": [90, 101, 109], "affsrinit": 53, "affsrinitslice0": 53, "affsrinitslice1": 53, "affsrslice0": 109, "affsrslice1": [101, 109], "after": [35, 36, 48, 71], "afterward": 127, "ag": 35, "again": [35, 71], "agp0": 73, "agp0100101011": 73, "agp1111": 73, "ai1": [101, 109], "aim": 11, "align": 77, "align_comma_msb": 68, "align_comma_word": 69, "all": [12, 14, 15, 16, 17, 34, 35, 36, 39, 40, 48, 51, 62, 63, 71, 76, 77, 115, 116, 126, 127], "alloc": [15, 16, 36, 51], "alloc1312": [15, 16], "alloc1514": [15, 16], "alloc1716": [15, 16], "alloc1918": [15, 16], "alloc2120": [15, 16], "allow": [36, 48, 49, 62, 63, 71, 72, 127], "allow_x8_gen2": [107, 113], "allow_x8_gen2pci": [107, 113], "almost": 51, "almost_empty_offset": [77, 88, 99, 108], "almost_full_offset": [77, 88, 99, 108], "almostempti": 77, "almostful": 77, "alon": 63, "along": 125, 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"clkpad1001000000100000": 48, "clkpad2001000000100": 71, "clkpad2001000001000000": 48, "clkpad3001000001000": 71, "clkpad3001000010000000": 48, "clkpad4010000000100": 71, "clkpad5010000001000": 71, "clkpad6100000000100": 71, "clkpad7100000001000": 71, "clkpin000": 54, "clkpin0000": 54, "clkpin01": 54, "clkpin1001": 54, "clkpin4100": 54, "clkpin5101": 54, "clkr": 51, "clkt": [51, 76], "clock": [11, 12, 34, 35, 36, 37, 39, 47, 48, 49, 56, 62, 63, 70, 72, 77, 85, 95, 116, 125, 127], "clock_delai": 98, "clock_invert_m": 93, "clock_invert_p": 93, "clock_invert_pdsp1": 93, "clockwis": [51, 76], "close": [51, 62], "closest": 51, "cmd_intx_impl": [107, 113], "cmd_intx_implementedpci": [107, 113], "cmo": 14, "cmos111": [50, 73], "cmos_hv111": 50, "cmos_lv001": 50, "cmos_vccaux111": 50, "cmos_vccint011": 50, "cmos_vcco100": 50, "cmt": 95, "cmt0": 54, "cmt10": 54, "cmt_clk000001000010000": 91, "cmt_clk000010000000010": 91, "cmt_clk100000000000110": 91, "cmt_clk100000000011000": 91, "cmt_clk1000010100000000": 91, "cmt_clk1000101000000000": 91, "cmt_clk1100001000001000": 91, "cmt_clk1100010000000100": 91, "cmt_clk1200010010000000": 91, "cmt_clk1201001000000000": 91, "cmt_clk1300001000010000": 91, "cmt_clk1300010000000010": 91, "cmt_clk1400010001000000": 91, "cmt_clk1410001000000000": 91, "cmt_clk1500001000100000": 91, "cmt_clk1500010000000001": 91, "cmt_clk1600010100000000": 91, "cmt_clk1600101000000000": 91, "cmt_clk1700000100000100": 91, "cmt_clk1700100000001000": 91, "cmt_clk1800100100000000": 91, "cmt_clk1900000100001000": 91, "cmt_clk1900100000000100": 91, "cmt_clk200000100010000": 91, "cmt_clk2000100010000000": 91, "cmt_clk200100000000010": 91, "cmt_clk2001000100000000": 91, "cmt_clk2100000100010000": 91, "cmt_clk2100100000000010": 91, "cmt_clk2200100001000000": 91, "cmt_clk2210000100000000": 91, "cmt_clk2300000100100000": 91, "cmt_clk2300100000000001": 91, "cmt_clk2400010010000000": 91, "cmt_clk2401001000000000": 91, "cmt_clk2500000010000100": 91, "cmt_clk2501000000001000": 91, "cmt_clk2600100010000000": 91, "cmt_clk2601000100000000": 91, "cmt_clk2700000010001000": 91, "cmt_clk2701000000000100": 91, "cmt_clk300000000001010": 91, "cmt_clk300000000010100": 91, "cmt_clk400000010010000": 91, "cmt_clk401000000000010": 91, "cmt_clk500000000010010": 91, "cmt_clk600000001010000": 91, "cmt_clk610000000000010": 91, "cmt_clk700000000010001": 91, "cmt_clk700000000100010": 91, "cmt_clk800011000000000": 91, "cmt_clk900001000000100": 91, "cmt_clk900010000001000": 91, "cmt_d00100": 54, "cmt_d100100": 54, "cmt_d10100": 54, "cmt_d110100": 54, "cmt_d120100": 54, "cmt_d130100": 54, "cmt_d140100": 54, "cmt_d150100": 54, "cmt_d20100": 54, "cmt_d30100": 54, "cmt_d40100": 54, "cmt_d50100": 54, "cmt_d60100": 54, "cmt_d70100": 54, "cmt_d80100": 54, "cmt_d90100": 54, "cmt_enabl": 54, "cmt_u01000": 54, "cmt_u101000": 54, "cmt_u11000": 54, "cmt_u111000": 54, "cmt_u121000": 54, "cmt_u131000": 54, "cmt_u141000": 54, "cmt_u151000": 54, "cmt_u21000": 54, "cmt_u31000": 54, "cmt_u41000": 54, "cmt_u51000": 54, "cmt_u61000": 54, "cmt_u71000": 54, "cmt_u81000": 54, "cmt_u91000": 54, "cnr": [51, 76], "code": 35, "coin_window": [44, 67], "col": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [51, 62], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 39, 40, 48, 62, 63, 64, 71, 76, 115, 116, 117, 118, 119, 120, 121, 122, 124, 126], "com": [44, 67], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 39, 48, 62, 63, 71, 127], "combination": 62, "combinatori": [14, 36, 127], "come": [12, 34, 36, 39, 51, 62, 76, 125, 127], "comma_10b_mask": [68, 69], "commerci": [17, 116], "common": 81, "common_hclk_giob": 81, "common_mgt": 81, "common_mgtioclk": 81, "commonli": 115, "compat": [12, 34, 125], "compens": 63, "complet": [12, 13, 16, 34, 35, 36, 115, 125], "complex": [15, 16], "comput": [62, 115], "concaten": [15, 16, 62, 77], "conceptu": 51, "concur": [44, 45, 67], "concur00100101": 83, "concur_en": 83, "concur_enabledcm": 83, "concurdcm": [44, 45, 67], "config": [15, 16, 115], "config10": 83, "config_fallback": [92, 102], "config_r": [41, 42, 65, 82, 92, 102], "configrout": 97, "configur": [11, 12, 15, 33, 34, 35, 37, 40, 47, 48, 49, 56, 61, 70, 71, 72, 76, 85, 95, 105, 111, 115, 124], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 39, 51, 62, 63, 71, 72, 77, 126, 127], "consid": 35, "consist": [35, 36, 62], "const": [13, 14, 35, 36, 39, 63, 126, 127], "constant": [36, 39, 63], "constraint": 12, "construct": 127, "consult": 15, "contain": [15, 17, 34, 38, 39, 48, 49, 51, 62, 63, 71, 72, 76, 77, 126, 127], "content": [35, 39, 63], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 39, 49, 63, 72, 77], "convert": [15, 16], "convst_mux": 87, "convstclkinv": [89, 100], "convstinv": 87, "convstinvsysmon": 87, "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 51, 76, 115, 116, 127], "cor": [47, 70, 85, 95, 105], "cor1": [47, 95, 105], "cor2": 47, "core": [12, 34, 36, 37, 48, 70, 71, 72, 76, 95, 105, 111, 125, 127], "corner": [37, 47, 48, 49, 51, 70, 71, 72, 76], "correct": 77, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 39, 40, 46, 48, 51, 55, 62, 63, 64, 71, 76, 77, 116, 127], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 39, 51, 62, 76, 117, 118, 119, 120, 121, 122], "cout": [39, 63], "coutmux": [53, 90, 101, 109], "coutmuxslice1": 53, "cover": 127, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 118, 125], "cpl_timeout_disable_support": [107, 113], "cpl_timeout_ranges_support": [107, 113], "cpld": [0, 12, 34, 36, 125, 127], "cpmc440clkinv": 98, "cpmc440timerclockinv": 98, "cpmdcrclkinv": 98, "cpmdma0llclkinv": 98, "cpmdma1llclkinv": 98, "cpmdma2llclkinv": 98, "cpmdma3llclkinv": 98, "cpmfcmclkinv": 98, "cpminterconnectclkinv": 98, "cpmmcclkinv": 98, "cpmppcmplbclkinv": 98, "cpmppcs0plbclkinv": 98, "cpmppcs1plbclkinv": 98, "crammod": [53, 90, 101, 109], "crc": [41, 42, 65, 82, 92], "crc_end_of_pkt": [68, 69], "crc_format": [68, 69], "crc_start_of_pkt": [68, 69], "creat": [48, 71, 76], "create_edg": [79, 89], "create_edgebufgctrl0": 79, "create_edgebufgctrl1": 79, "create_edgebufgctrl10": 79, "create_edgebufgctrl11": 79, "create_edgebufgctrl12": 79, "create_edgebufgctrl13": 79, "create_edgebufgctrl14": 79, "create_edgebufgctrl15": 79, "create_edgebufgctrl16": 79, "create_edgebufgctrl17": 79, "create_edgebufgctrl18": 79, "create_edgebufgctrl19": 79, "create_edgebufgctrl2": 79, "create_edgebufgctrl20": 79, "create_edgebufgctrl21": 79, "create_edgebufgctrl22": 79, "create_edgebufgctrl23": 79, "create_edgebufgctrl24": 79, "create_edgebufgctrl25": 79, "create_edgebufgctrl26": 79, "create_edgebufgctrl27": 79, "create_edgebufgctrl28": 79, "create_edgebufgctrl29": 79, "create_edgebufgctrl3": 79, "create_edgebufgctrl30": 79, "create_edgebufgctrl31": 79, "create_edgebufgctrl4": 79, "create_edgebufgctrl5": 79, "create_edgebufgctrl6": 79, "create_edgebufgctrl7": 79, "create_edgebufgctrl8": 79, "create_edgebufgctrl9": 79, "creg": [46, 55, 84, 93, 103, 110], "cregdsp": [46, 55], "cregdsp0": [93, 103], "cregdsp1": 103, "crm_core_clk_freq_500": 114, "crm_core_clk_freq_500pcie3": 114, "crm_module_rst": [107, 113], "crm_user_clk_freq": 114, "crmcoreclkdloinv": 97, "crmcoreclkinv": 97, "crmcoreclkinvpci": 97, "crmcoreclkrxoinv": 97, "crmcoreclkrxoinvpci": 97, "crmcoreclktxoinv": 97, "crmcoreclktxoinvpci": 97, "crmuserclkinv": 97, "crmuserclkrxoinv": 97, "crmuserclktxoinv": 97, "cross": [51, 71], "cs144": [20, 21, 34, 119, 125], "cs280": [24, 25, 34, 120, 125], "cs48": [26, 27, 28, 30, 31, 34, 117, 118, 125], "cso2pin": 43, "cspin": [79, 89, 100], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctl": [47, 70, 85, 95, 105], "ctl1": 105, "ctlgo001": 48, "ctlgoinv": [44, 45, 67, 83], "ctlgoinvdcm": 67, "ctlmode011": 48, "ctlmodeinv": [44, 45, 67], "ctlmodeinvdcm": 67, "ctlosc1001": 48, "ctlosc1inv": [44, 45, 67, 83], "ctlosc1invdcm": [67, 83], "ctlosc2001": 48, "ctlosc2inv": [44, 45, 67, 83], "ctlosc2invdcm": [67, 83], "ctlsel0011": 48, "ctlsel0inv": [44, 45, 67, 83], "ctlsel0invdcm": 67, "ctlsel1101": 48, "ctlsel1inv": [44, 45, 67, 83], "ctlsel1invdcm": [67, 83], "ctlsel2100": 48, "ctlsel2inv": [44, 45, 67, 83], "ctlsel2invdcm": [67, 83], "ctr": 14, "ctrl0": [96, 106, 112], "ctrl00001": [106, 112], "ctrl1": [96, 106, 112], "ctrl10010": [106, 112], "ctrl2": 96, "ctrl3": 96, "curious": [12, 34], "current": [35, 39, 63], "cut": [49, 51], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": [53, 90, 101, 109], "cx0100": [90, 101, 109], "cx1": [53, 90], "cx10": [101, 109], "cx1010": 53, "cy0": 60, "cy0111": 53, "cy0f": [39, 63, 80], "cy0g": [39, 63, 80], "cy1010": [53, 90, 101, 109], "cy110": 90, "cycl": [35, 62, 77], "cyinit": [39, 53, 60, 63, 80, 90, 101, 109], "cyinitslice0": [60, 80, 90, 101, 109], "cyinitslice1": [39, 53, 60, 90, 101, 109], "cyinitslice2": 80, "cyinitslice3": 39, "cyself": [39, 60, 63], "cyselfslice0": 60, "cyselfslice1": [39, 60], "cyselfslice3": 39, "cyselg": [39, 60, 63], "cyselgslice0": [60, 63], "cyselgslice1": [39, 60, 63], "cyselgslice3": 39, "d": [14, 36, 62, 77, 127], "d0": [103, 110], "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122, 127], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 103, 110, 118, 119, 120, 121, 122], "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d14": [2, 3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d15": [3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d16": [3, 6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d17": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d18": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d19": [6, 7, 22, 23, 24, 25, 103, 110, 120, 121, 122], "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d20": [6, 7, 22, 23, 24, 103, 110, 121, 122], "d21": [6, 7, 22, 23, 103, 110, 121, 122], "d22": [6, 7, 22, 23, 103, 110, 121, 122], "d23": [22, 23, 103, 110], "d24": [22, 23, 103, 110], "d25": [22, 23], "d26": [22, 23], "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "d5ffinit": [101, 109], "d5ffinitslice0": [101, 109], "d5ffmux": [101, 109], "d5ffsr": [101, 109], "d5ffsrinit": 53, "d5ffsrinitslice0": 53, "d5ffsrslice1": 101, "d5q0": 53, "d5q0100": [53, 101, 109], "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d6lut": [53, 90, 101, 109], "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 103, 110, 117, 118, 119, 120, 121, 122], "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 103, 110, 118, 119, 120, 121, 122], "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 103, 110, 119, 120, 121, 122], "daddr0inv": 83, "daddr1inv": 83, "daddr1invdcm": 83, "daddr2inv": 83, "daddr2invdcm": 83, "daddr3inv": 83, "daddr4inv": 83, "daddr4invdcm": 83, "daddr5inv": 83, "daddr5invdcm": 83, "daddr6inv": 83, "daddr6invdcm": 83, "data": [10, 12, 14, 17, 32, 35, 38, 39, 46, 47, 48, 51, 52, 55, 59, 62, 63, 70, 71, 76, 77, 80, 115, 116, 123, 127], "data0": [48, 71], "data00001000001": 71, "data00001000100": 71, "data00mux": 48, "data1": [48, 71], "data10": 48, "data10001000010": 71, "data10001001000": 71, "data101mux": 48, "data10mux": 48, "data11": 48, "data110mux": 48, "data11mux": 48, "data12": 48, "data13": 48, "data130mux": 48, "data131mux": 48, "data14": 48, "data140mux": 48, "data15": 48, "data16": 48, "data160mux": 48, "data17": 48, "data170mux": 48, "data171mux": 48, "data18": 48, "data180mux": 48, "data181mux": 48, "data19": 48, "data190mux": 48, "data2": [48, 71], "data20": 48, "data20001000100": 71, "data20001010000": 71, "data20mux": 48, "data21": 48, "data210mux": 48, "data21mux": 48, "data22": 48, "data220mux": 48, "data221mux": 48, "data23": 48, "data24": 48, "data240mux": 48, "data25": 48, "data250mux": 48, "data251mux": 48, "data26": 48, "data261mux": 48, "data27": 48, "data270mux": 48, "data28": 48, "data29": 48, "data290mux": 48, "data3": [48, 71], "data30": 48, "data30001001000": 71, "data30001100000": 71, "data300mux": 48, "data301mux": 48, "data30mux": 48, "data31": 48, "data4": [48, 71], "data40001000001": 71, "data40001000010": 71, "data40001000100": 71, "data5": [48, 71], "data50001000010": 71, "data50001000100": 71, "data50001001000": 71, "data50mux": 48, "data51mux": 48, "data6": [48, 71], "data60001000100": 71, "data60001001000": 71, "data60001010000": 71, "data60mux": 48, "data7": [48, 71], "data70001001000": 71, "data70001010000": 71, "data70001100000": 71, "data8": 48, "data80mux": 48, "data9": 48, "data90mux": 48, "data91mux": 48, "data_l": [88, 99, 108], "data_r": 54, "data_u": [88, 99, 108], "data_width_": 62, "data_width_a": [38, 52, 62], "data_width_b": [38, 52, 62], "databas": [11, 15, 16, 33, 35, 36, 115, 124, 126, 127], "datap": [38, 52, 62, 77], "datap_l": [88, 99, 108], "datap_u": [88, 99, 108], "datareg": 13, "datastream": [17, 116], "dbl": [40, 48, 57, 64, 71, 86, 96, 106, 112], "dbl0001010000": 96, "dbl0001100000": 96, "dbl0010010000": 96, "dbl0010100000": 96, "dbl0100010000": 96, "dbl0100100000": 96, "dbl1000010000": 96, "dbl1000100000": 96, "dci": [49, 71, 72], "dci0": [43, 66], "dci00": 43, "dci1": [43, 66], "dci11": 43, "dci_altvr": 66, "dci_altvrmisc": 66, "dci_clk_en": [43, 66], "dci_clk_enablemisc": 66, "dci_mod": [50, 73], "dci_osc_sel": 43, "dci_test_mux": 43, "dcireset": [79, 89, 100], "dcireset0": 43, "dcireset1": 43, "dciupdatemode_asrequir": [50, 73], "dciupdatemode_asrequirediob0": [50, 73], "dciupdatemode_asrequirediob1": [50, 73], "dciupdatemode_asrequirediob2": 73, "dciupdatemode_asrequirediob3": [50, 73], "dciupdatemode_asrequirediob4": [50, 73], "dciupdatemode_asrequirediob5": 73, "dclk0": 83, "dclk_divid_2": 87, "dclk_miss": 87, "dclkinv": [89, 100], "dclkinvsysmon": 89, "dcm": [37, 47, 49, 62, 70, 76, 85], "dcm000001000000111111": 81, "dcm100001000001011111": 81, "dcm1000010001000011111": 81, "dcm1100010010000011111": 81, "dcm1200100000000111111": 81, "dcm1300100000001011111": 81, "dcm1400100000010011111": 81, "dcm1500100000100011111": 81, "dcm1600100001000011111": 81, "dcm1700100010000011111": 81, "dcm1801000000000111111": 81, "dcm1901000000001011111": 81, "dcm200001000010011111": 81, "dcm2001000000010011111": 81, "dcm2101000000100011111": 81, "dcm2201000001000011111": 81, "dcm2301000010000011111": 81, "dcm300001000100011111": 81, "dcm400001001000011111": 81, "dcm500001010000011111": 81, "dcm600010000000111111": 81, "dcm700010000001011111": 81, "dcm800010000010011111": 81, "dcm900010000100011111": 81, "dcm_bufpll": 56, "dcm_clkdv_clkfx_align": 83, "dcm_clkdv_clkfx_alignmentdcm": 83, "dcm_enabl": 43, "dcm_ext_fb_en": 83, "dcm_ext_fb_endcm": 83, "dcm_lock_high": 83, "dcm_lock_highdcm": 83, "dcm_out100": 40, "dcm_out_l0100": [40, 64], "dcm_out_l01000": 40, "dcm_out_r1000": [40, 64], "dcm_out_r10000": 40, "dcm_performance_mod": 83, "dcm_performance_modedcm": 83, "dcm_pulse_width_correction_high": 83, "dcm_pulse_width_correction_low": 83, "dcm_shutdown": [41, 65, 82], "dcm_unused_taps_powerdown": 83, "dcm_unused_taps_powerdowndcm": 83, "dcm_vbg_pd": 83, "dcm_vbg_sel": 83, "dcm_vref_sourc": 83, "dcm_vreg": 45, "dcm_vreg_en": 83, "dcm_vreg_enabledcm": 83, "dcm_vreg_phase_margin": 83, "dcmclk": 71, "dcmclk0": 71, "dcmclk00001000001": 71, "dcmclk0int": 71, "dcmclk1": 71, "dcmclk10001000010": 71, "dcmclk1int": 71, "dcmclk2": 71, "dcmclk20001000001": 71, "dcmclk2int": 71, "dcmclk3": 71, "dcmclk30001000010": 71, "dcmclk3int": 71, "dcr_autolock_en": 98, "dcr_test": 98, "dcremacclkinv": 94, "dcy0": [53, 90, 101, 109], "dcy0slice0": [90, 101, 109], "dcy0slice1": [53, 109], "dd1": 34, "ddel_a": [38, 52, 62], "ddel_a_default": 38, "ddel_b": [38, 52, 62], "ddel_b_default": 38, "ddr": [49, 72], "ddr1": 54, "deal": [51, 71, 76], "dec_mcomma_detect": [68, 69], "dec_pcomma_detect": [68, 69], "dec_valid_comma_onli": [68, 69], "decod": 77, "decrypt": 102, "dedic": [12, 14, 34, 36, 38, 39, 49, 51, 62, 63, 71, 72, 76, 77, 116, 125, 127], "def": [15, 16], "default": [17, 35, 47], "defin": 127, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [117, 118, 119, 120, 121, 122], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 117, 118, 119, 120, 121, 122], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_pt_ut": [117, 118, 119, 120, 121, 122], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "delai": [14, 40, 95, 105, 111], "delay_common": 50, "delay_commoniob0": 50, "delay_commoniob1": 50, "delay_commoniob2": 50, "delay_commoniob3": 50, "delay_commoniob4": 50, "delay_commoniob5": 50, "delay_commoniob6": 50, "delay_vari": 50, "delay_variableiob0": 50, "delay_variableiob1": 50, "delay_variableiob3": 50, "delay_variableiob4": 50, "delayed_write0": 108, "delayed_write00": 99, "depend": [17, 35, 36, 48, 51, 62, 71, 116, 126, 127], "deriv": [12, 34, 49, 72, 125, 127], "describ": [17, 35, 39, 40, 51, 62, 63, 64, 81, 91, 116], "descript": [38, 80], "design": [12, 36, 51, 125, 127], "deskew_adjust": [47, 70, 83], "destin": 36, "detail": [35, 51, 76, 77, 126], "determin": [12, 34, 35, 39, 63, 127], "dev_cap2_ari_forwarding_support": 113, "dev_cap2_ari_forwarding_supportedpci": 113, "dev_cap2_atomicop32_completer_support": 113, "dev_cap2_atomicop32_completer_supportedpci": 113, "dev_cap2_atomicop64_completer_support": 113, "dev_cap2_atomicop_routing_support": 113, "dev_cap2_cas128_completer_support": 113, "dev_cap2_cas128_completer_supportedpci": 113, "dev_cap2_endend_tlp_prefix_support": 113, "dev_cap2_endend_tlp_prefix_supportedpci": 113, "dev_cap2_extended_fmt_field_support": 113, "dev_cap2_ltr_mechanism_support": 113, "dev_cap2_ltr_mechanism_supportedpci": 113, "dev_cap2_max_endend_tlp_prefix": 113, "dev_cap2_no_ro_enabled_prpr_pass": 113, "dev_cap2_tph_completer_support": 113, "dev_cap_enable_slot_pwr_limit_scal": [107, 113], "dev_cap_enable_slot_pwr_limit_scalepci": [107, 113], "dev_cap_enable_slot_pwr_limit_valu": [107, 113], "dev_cap_endpoint_l0s_lat": [58, 107, 113], "dev_cap_endpoint_l1_lat": [58, 107, 113], "dev_cap_ext_tag_support": [58, 107, 113], "dev_cap_ext_tag_supportedpci": [107, 113], "dev_cap_function_level_reset_cap": [107, 113], "dev_cap_max_payload_support": [58, 107, 113], "dev_cap_phantom_functions_support": [58, 107, 113], "dev_cap_role_based_error": [58, 107, 113], "dev_cap_rsvd_14_12": [107, 113], "dev_cap_rsvd_17_16": [107, 113], "dev_cap_rsvd_31_29": [107, 113], "dev_control_aux_power_support": [107, 113], "dev_control_aux_power_supportedpci": 113, "dev_control_ext_tag_default": 113, "devic": [11, 15, 16, 33, 35, 37, 38, 39, 40, 47, 48, 62, 63, 64, 70, 71, 115, 124, 126], "device_id": 107, "devicebram": 38, "devicecapabilityendpointl0slat": 97, "devicecapabilityendpointl1lat": 97, "devicedcm": [44, 45, 67], "deviceid": 97, "deviceserialnumb": 97, "devicevalu": [40, 54], "df": [44, 67], "dfb001": 54, "dfb010": 54, "dff": [14, 36, 127], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 115], "dff1": 15, "dff_latch": 101, "dff_latchslice0": 101, "dffce": 127, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 115], "dffinit": [90, 101, 109], "dffinitslice0": [90, 101, 109], "dffmux": [53, 90, 101, 109], "dffmuxslice1": 53, "dffsr": [90, 101, 109], "dffsrinit": 53, "dffsrinitslice1": 53, "dffsrslice0": 109, "dffsrslice1": 101, "dfs_": 45, "dfs_ave_freq_adj_interv": 83, "dfs_ave_freq_gain": 83, "dfs_ave_freq_sample_interv": 83, "dfs_c": 45, "dfs_coarse_sel": 83, "dfs_coarse_seldcm": 83, "dfs_coin_window": 83, "dfs_early_lock": 83, "dfs_early_lockdcm": 83, "dfs_en_relrst": 83, "dfs_en_relrstdcm": 83, "dfs_enabl": [44, 45, 67, 83], "dfs_enabledcm": [44, 45, 67, 83], "dfs_extend_flush_tim": 83, "dfs_extend_flush_timedcm": 83, "dfs_extend_halt_tim": 83, "dfs_extend_halt_timedcm": 83, "dfs_extend_run_tim": 83, "dfs_extend_run_timedcm": 83, "dfs_feedback": [44, 45, 67, 83], "dfs_feedbackdcm": [44, 45, 83], "dfs_fine_sel": 83, "dfs_fine_seldcm": 83, "dfs_frequency_mod": [44, 45, 67, 83], "dfs_frequency_modedcm": [44, 45, 83], "dfs_hardsync": 83, "dfs_non_stop": 83, "dfs_non_stopdcm": 83, "dfs_oscillator_mod": 83, "dfs_skip_fin": 83, "dfs_skip_finedcm": 83, "dfs_spare": 83, "dfs_tp_sel": 83, "dfs_tp_seldcm": 83, "dfs_trackmod": 83, "dfs_trackmodedcm": 83, "dge": [2, 3, 6, 7, 12, 14], "dge_en": [2, 3, 6, 7], "di": [12, 39, 62, 63, 77], "di0inv": 83, "di10inv": 83, "di10invdcm": 83, "di11inv": 83, "di126": [2, 12], "di12inv": 83, "di12invdcm": 83, "di13inv": 83, "di13invdcm": 83, "di14inv": 83, "di14invdcm": 83, "di15inv": 83, "di1inv": 83, "di1invdcm": 83, "di222": [3, 12], "di288": [6, 12], "di2inv": 83, "di2invdcm": 83, "di324": [7, 12], "di3inv": 83, "di44": [4, 5, 12], "di4inv": 83, "di4invdcm": 83, "di5inv": 83, "di5invdcm": 83, "di6inv": 83, "di6invdcm": 83, "di7inv": 83, "di81": [8, 9, 12], "di8inv": 83, "di9inv": 83, "di9invdcm": 83, "dia": 77, "diagon": [48, 71], "dib": 77, "dib16": 62, "dib31": 62, "die": [12, 17, 49, 116], "dif": [39, 63], "dif_mux": [39, 63, 80], "dif_muxslice0": 80, "diff101": [50, 73], "diff110": 50, "differ": [16, 35, 36, 39, 48, 63, 71, 125, 127], "differenti": [14, 49], "dig": [39, 63], "dig_mux": [39, 63, 80], "dig_muxslice0": 80, "dig_muxslice2": 80, "digit": [37, 47, 48, 49, 70, 71, 72], "dimens": 51, "dimension": 115, "dinpin": [79, 89, 100], "dip": [62, 77], "dipa": 77, "dipb": 77, "direct": [36, 48, 62, 71], "direct0": [38, 46, 55, 84, 93, 103, 110], "directli": [14, 17, 35, 36, 39, 51, 62, 63, 71, 116, 127], "dis_tstblclamp": 108, "dis_tstfiforst": [99, 108], "dis_vgg_reg": 102, "disabl": [36, 127], "disable_aspm_l1_tim": [107, 113], "disable_aspm_l1_timerpci": [107, 113], "disable_attr": [40, 54, 64], "disable_attrbufgmux0": 40, "disable_attrbufgmux2": 40, "disable_attrbufgmux6": 40, "disable_attrbufgmux7": 40, "disable_bar_filt": [58, 107, 113], "disable_err_msg": 113, "disable_gt": [50, 73], "disable_gtsiob0": 50, "disable_gtsiob1": 73, "disable_gtsiob2": [50, 73], "disable_gtsiob3": 50, "disable_gtsiob4": [50, 73], "disable_id_check": [58, 107, 113], "disable_id_checkpci": [107, 113], "disable_jtag": 100, "disable_lane_revers": [107, 113], "disable_lane_reversalpci": 107, "disable_locked_filt": 113, "disable_ppm_filt": 113, "disable_ppm_filterpci": 113, "disable_rx_poisoned_resp": 113, "disable_rx_poisoned_resppci": 113, "disable_rx_tc_filt": [107, 113], "disable_scrambl": [58, 107, 113], "disable_scramblingpci": 113, "disablebandgap": 66, "disablebandgapmisc": 66, "disablevgggener": 66, "disablevgggenerationmisc": 66, "disconnect": [48, 127], "displac": 51, "distanc": [2, 3, 4, 5, 6, 7, 8, 9, 48, 51, 71], "distribut": [47, 48, 51, 70, 71, 76], "divclk11": 54, "divid": [11, 12, 51, 54, 115, 127], "divide_100": 54, "divide_1000": 54, "divide_2001": 54, "divide_201": 54, "divide_300": 54, "divide_3010": 54, "divide_400": 54, "divide_4011": 54, "divide_501": 54, "divide_5100": 54, "divide_601": 54, "divide_6101": 54, "divide_710": 54, "divide_7110": 54, "divide_810": 54, "divide_8111": 54, "divide_bypass": 54, "divis": [77, 125], "dll": [44, 67, 72], "dll_": 45, "dll_c": 45, "dll_control_clock_spe": 83, "dll_control_clock_speeddcm": 83, "dll_ctl_sel_clkin_div2": 83, "dll_ctl_sel_clkin_div2dcm": 83, "dll_dead_tim": 83, "dll_deskew_lock_by1": 83, "dll_deskew_lock_by1dcm": 83, "dll_deskew_maxtap": 83, "dll_deskew_mintap": 83, "dll_enabl": [44, 67, 83], "dll_enabledcm": [44, 83], "dll_frequency_mod": [44, 45, 67, 83], "dll_frequency_modedcm": 45, "dll_live_tim": 83, "dll_pd_dly_sel": 83, "dll_period_lock_by1": 83, "dll_period_lock_by1dcm": 83, "dll_phase_detector_auto_reset": 83, "dll_phase_detector_auto_resetdcm": 83, "dll_phase_detector_mod": 83, "dll_phase_detector_modedcm": 83, "dll_phase_shift_calibr": 83, "dll_phase_shift_hfc": 83, "dll_phase_shift_lfc": 83, "dll_phase_shift_lock_by1": 83, "dll_phase_shift_lock_by1dcm": 83, "dll_settle_tim": 83, "dll_spare": 83, "dll_test_mux_sel": 83, "dllc": [44, 67], "dma0_control": 98, "dma0_rxchannelctrl": 98, "dma0_rxirqtim": 98, "dma0_txchannelctrl": 98, "dma0_txirqtim": 98, "dma1_control": 98, "dma1_rxchannelctrl": 98, "dma1_rxirqtim": 98, "dma1_txchannelctrl": 98, "dma1_txirqtim": 98, "dma2_control": 98, "dma2_rxchannelctrl": 98, "dma2_rxirqtim": 98, "dma2_txchannelctrl": 98, "dma2_txirqtim": 98, "dma3_control": 98, "dma3_rxchannelctrl": 98, "dma3_rxirqtim": 98, "dma3_txchannelctrl": 98, "dma3_txirqtim": 98, "dma_test": 98, "dna_port": [49, 100], "dnstream_link_num": [107, 113, 114], "do": [35, 39, 62, 63, 71, 77], "doa": [62, 77], "doa0": 77, "doa31": 77, "doa_reg": [38, 52, 77], "doa_reg_l": [88, 99, 108], "doa_reg_u": [88, 99, 108], "dob": [62, 77], "dob10": 77, "dob11": 77, "dob4": 77, "dob5": 77, "dob6": 77, "dob7": 77, "dob8": 77, "dob9": 77, "dob_reg": [38, 52, 77], "dob_reg_l": [88, 99, 108], "dob_reg_u": [88, 99, 108], "document": [15, 16, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 50, 53, 55, 56, 61, 62, 63, 64, 65, 66, 67, 68, 69, 73, 74, 75, 79, 80, 82, 85, 86, 89, 90, 92, 95, 96, 100, 101, 102, 105, 106, 109, 111, 112], "doe": 34, "doesn": [16, 36, 39, 48, 51, 62, 71, 127], "don": [35, 36, 39, 48, 51, 127], "done": [2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 34, 35, 36, 77], "done110": [41, 65, 82, 92, 102], "done111": 42, "done_cycl": [41, 42, 65, 82, 92, 102], "done_pip": [41, 42, 65, 82, 92, 102], "done_signals_powerdown": 102, "donepin": [43, 66, 79, 89, 100], "dont_set1": 93, "dop": [62, 77], "dopa": 77, "doubl": [48, 71], "doutmux": [53, 90, 101, 109], "doutmuxslice1": 53, "down": [36, 48, 49, 51, 127], "down0": 15, "down1": [16, 115], "downward": 36, "dpm": 78, "dpm_oscout10001000100": 78, "dpm_oscout20001000010": 78, "dpm_refclkout0001010000": 78, "dqs0011": 54, "dqs2110": 54, "dr": [13, 115], "drain": 14, "drammod": [53, 90, 101, 109], "dreg": [46, 55, 103, 110], "dregdsp": [46, 55], "dregdsp0": 103, "dregdsp1": 103, "drive": [12, 14, 17, 34, 35, 36, 48, 49, 51, 63, 71, 125, 127], "drive_awak": 42, "drive_don": [41, 42, 65, 82, 92, 102], "drive_last_value0001": 50, "driven": [14, 36, 48, 51, 71, 76, 127], "driver": [12, 34, 48, 71], "drp40": 83, "drp40_mask": 83, "drp40_maskdcm": 83, "drp41": 83, "drp41_mask": 83, "drp41_maskdcm": 83, "drp42": 83, "drp42_mask": 83, "drp42_maskdcm": 83, "drp43": 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28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p300": 7, "p301": 7, "p302": 7, "p303": 7, "p304": 7, "p305": 7, "p306": 7, "p307": 7, "p308": 7, "p309": 7, "p31": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p310": 7, "p311": 7, "p312": 7, "p313": 7, "p314": 7, "p315": 7, "p316": 7, "p317": 7, "p318": 7, "p319": 7, "p32": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p320": 7, "p321": 7, "p322": 7, "p323": 7, "p324": 7, "p33": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p34": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p35": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p36": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p37": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p38": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p39": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p4": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p40": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p41": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p42": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p43": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p44": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p45": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p46": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 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25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 118, 119, 120, 121, 122], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 117, 118, 119, 120, 121, 122], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 118, 119, 120, 121, 122], "p_d": 62, "packag": [11, 17, 33, 36, 49, 116, 124, 126], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 48, 71, 116, 125, 127], "pair": [17, 51, 63, 77, 116], "parallel": 16, "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 116, 117, 118, 119, 120, 121, 122], "pariti": [62, 77], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 39, 51, 63, 77, 117, 118, 119, 120, 121, 122, 124, 126], "partial": [34, 62, 77, 126], "particip": 36, "particular": [17, 116], "particularli": 39, "pass": [35, 48, 51, 71], "pass00000000": 83, "pass00000000001": 91, "pass00000001": 91, "pass00000001000000": 91, "pass00001000": 91, "pass10000000000000": 91, "pass10000100000011111": 81, "pass100001000011111": 81, "passthrough": 71, "patdet1": 93, "path": [36, 62], "pattern": [76, 93, 103, 110], "pattern0": [93, 103, 110], "pbbaseptr": 97, "pbcapabilitydw0basepow": 97, "pbcapabilitydw0datascal": 97, "pbcapabilitydw0pmst": 97, "pbcapabilitydw0pmsubst": 97, "pbcapabilitydw0powerrail": 97, "pbcapabilitydw0typ": 97, "pbcapabilitydw1basepow": 97, "pbcapabilitydw1datascal": 97, "pbcapabilitydw1pmst": 97, "pbcapabilitydw1pmsubst": 97, "pbcapabilitydw1powerrail": 97, "pbcapabilitydw1typ": 97, "pbcapabilitydw2basepow": 97, "pbcapabilitydw2datascal": 97, "pbcapabilitydw2pmst": 97, "pbcapabilitydw2pmsubst": 97, "pbcapabilitydw2powerrail": 97, "pbcapabilitydw2typ": 97, "pbcapabilitydw3basepow": 97, "pbcapabilitydw3datascal": 97, "pbcapabilitydw3pmst": 97, "pbcapabilitydw3pmsubst": 97, "pbcapabilitydw3powerrail": 97, "pbcapabilitydw3typ": 97, "pbcapabilitynextptr": 97, "pbcapabilitysystemalloc": 97, "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 117, 118, 125], "pc84": [18, 29, 34], "pci": [37, 49, 51, 56, 70, 71, 72, 95, 105, 111], "pci000": 71, "pci100": 71, "pci33_3": 50, "pci33_30": [50, 73], "pci33_300": [50, 73], "pci33_30000": 73, "pci33_300000": [50, 73], "pci33_3000001": 50, "pci33_30100101011": 73, "pci33_3010101110": 73, "pci33_301111100": 50, "pci33_3100110": 50, "pci33_311001001": 50, "pci33_3111110": 50, "pci66_3": 50, "pci66_30": [50, 73], "pci66_300": [50, 73], "pci66_300000": [50, 73], "pci66_3000001": 50, "pci66_30011": 73, "pci66_30100101011": 73, "pci66_3010101110": 73, "pci66_301111100": 50, "pci66_3100110": 50, "pci66_311001001": 50, "pci66_3111110": 50, "pci_ce_delai": 56, "pci_clamp": 50, "pci_clampiob0": 50, "pci_clampiob1": 50, "pci_clampiob3": 50, "pci_clampiob4": 50, "pci_input": 50, "pci_inputiob1": 50, "pci_inputiob2": 50, "pci_inputiob3": 50, "pci_inputiob4": 50, "pci_inputiob5": 50, "pcice10": 50, "pcice_mux": 50, "pcie": [58, 97, 107, 113], "pcie3": 114, "pcie_base_ptr": [107, 113], "pcie_cap_capability_id": [107, 113], "pcie_cap_capability_vers": [58, 107, 113], "pcie_cap_device_port_typ": [58, 107, 113], "pcie_cap_int_msg_num": [58, 107], "pcie_cap_nextptr": [107, 113], "pcie_cap_on": [107, 113], "pcie_cap_onpci": [107, 113], "pcie_cap_rsvd_15_14": [107, 113], "pcie_cap_slot_impl": [58, 107, 113], "pcie_gener": 58, "pcie_l": 111, "pcie_r": 111, "pcie_revis": [107, 113], "pciecapabilityintmsgnum": 97, "pciecapabilitynextptr": 97, "pciecapabilityslotimpl": 97, "pcierevis": 97, "pcierevisionpci": 97, "pcilog": [51, 70, 71, 76], "pcilogics": [40, 51, 56], "pcix": 50, "pcix0": [50, 73], "pcix00": 73, "pcix000001": 50, "pcix0011": 73, "pcix0100101011": 73, "pcix011001100": 73, "pcix01111": 73, "pcix100110": 50, "pcix111110": 50, "pcix11111111": 50, "pcomma_10b_valu": [68, 69], "pcomma_detect": [68, 69], "pdrive": [50, 73], "pdriveiostd": [50, 73], "pent": 96, "pent00010100": 96, "pent00011000": 96, "pent00100100": 96, "pent00101000": 96, "pent01000100": 96, "pent01001000": 96, "pent10000100": 96, "pent10001000": 96, "per": [12, 14, 17, 33, 34, 35, 36, 39, 48, 49, 51, 62, 71, 72, 77, 115, 116, 126, 127], "perform": [35, 36, 127], "performance1": 108, "performance11": 99, "period_lf": 45, "period_not_hf": 45, "perman": 40, "persist": [41, 42, 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121, 122], "xxxxxxxxxxxxxxxx": [7, 8, 9], "xxxxxxxxxxxxxxxxx": 118, "xxxxxxxxxxxxxxxxxx": 23, "xxxxxxxxxxxxxxxxxxxxxxxxxxx": 119, "xxxxxxxxxxxxxxxxxxxxxxxxxxxx": 2, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [2, 3, 4, 5, 6, 7, 8, 9], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 120, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [3, 117, 118], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 121, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 6, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 122, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 7, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 119, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 120, 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122], "y2": [6, 7, 22, 23, 24, 121, 122], "y20": [6, 7, 24, 121, 122], "y21": [6, 7, 121, 122], "y22": [6, 7, 121, 122], "y23": [22, 23], "y24": [22, 23], "y25": [22, 23], "y26": [22, 23], "y3": [6, 7, 22, 23, 24, 121, 122], "y4": [6, 7, 22, 23, 24, 121, 122], "y5": [6, 7, 24, 121, 122], "y6": [6, 7, 24, 121, 122], "y7": [6, 7, 24, 121, 122], "y8": [6, 7, 24, 121, 122], "y9": [6, 7, 24, 121, 122], "yb": [39, 48, 63, 71], "yb00101": 80, "ybmux": [39, 60, 63, 80], "ybmuxslice0": 60, "ybmuxslice1": 60, "ymux": 39, "you": 35, "your": 35, "yq": [39, 48, 63, 71], "z": 35, "zclk_div2": 66, "zd1_by1": [44, 67], "zd1_by1dcm": 44, "zd2_by1": [44, 67], "zd2_by1dcm": 44, "zero": 127, "zia": [14, 124, 126], "zia_gclk": [115, 127], "zia_gclk0_en": [117, 118, 119, 120, 121, 122], "zia_gclk1_en": [117, 118, 119, 120, 121, 122], "zia_gclk2_en": [117, 118, 119, 120, 121, 122], "zia_gclk3_en": [117, 118, 119, 120, 121, 122], "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Xilinx FPGAs", "Block RAM", "Configurable Logic Block", "Clock interconnect", "Configuration registers \u2014 Spartan 3, Spartan 3E", "Configuration registers \u2014 Spartan 3A and 3A DSP", "Corners", "Digital Clock Managers \u2014 Spartan 3", "Digital Clock Managers \u2014 Spartan 3E, 3A", "DSP", "Spartan 3", "General interconnect", "Introduction", "Input / Output", "Device geometry", "Block RAM", "Configurable Logic Block", "Clock interconnect", "DSP", "Spartan 6", "General interconnect", "PCI Express", "Block RAM \u2014 Virtex", "Configurable Logic Block \u2014 Virtex", "Virtex", "Block RAM \u2014 Virtex 2, Spartan 3", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "Corners", "Digital Clock Managers", "Multi-gigabit transceivers \u2014 Virtex 2 Pro", "Multi-gigabit transceivers \u2014 Virtex 2 Pro X", "Virtex 2", "General interconnect", "Introduction", "Input / Output", "Hard PCI logic", "Hard PowerPC 405 cores", "Device geometry", "Block RAM", "CCM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "DCM", "DSP", "Virtex 4", "General Interconnect", "System monitor", "Block RAM", "Configuration Center", "Configurable Logic Block", "Clock interconnect", "Configuration registers", "DSP", "Ethernet MACs", "Virtex 5", "Interconnect", "PCI Express cores", "PowerPC cores", "Block RAM", "Configuration Center", "Configurable Logic Block", "Configuration registers", "DSP", "Ethernet MACs", "Virtex 6", "Interconnect", "PCI Express cores", "Block RAM", "Configurable Logic Block", "DSP", "Virtex 7", "Interconnect", "PCI Express Gen2 cores", "PCI Express Gen3 cores", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [40, 71], "03": 48, "1": [39, 63], "12": [42, 48], "128": 63, "16": [39, 63], "2": [62, 66, 68, 69, 70, 73], "3": [39, 41, 43, 44, 47, 50, 62], "32": [39, 63], "3a": [42, 43, 45, 50, 51, 62], "3e": [41, 43, 45, 50, 51, 62], "4": [39, 85], "405": 75, "5": 95, "6": [56, 105], "64": [39, 63], "7": 111, "AND": 15, "The": [40, 62, 64], "aim": 14, "alt": 73, "attribut": 40, "b": [50, 64, 68, 69, 73], "b0": 71, "b1": 50, "b123": 71, "b2": [50, 73], "b3": 50, "b4": 50, "backbon": [48, 71], "bank": [14, 51, 76], "bclkpad": 71, "bel": 62, "bit": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 115, 116, 117, 118, 119, 120, 121, 122], "bitsteam": 57, "bitstream": [1, 15, 16, 38, 39, 40, 46, 48, 51, 52, 53, 54, 55, 57, 58, 59, 60, 62, 63, 64, 68, 69, 71, 76, 77, 78, 79, 80, 83, 84, 86, 87, 88, 89, 90, 93, 94, 96, 97, 98, 99, 100, 101, 103, 104, 106, 107, 108, 109, 110, 112, 114, 115], "bl": 45, "blank": 35, "block": [38, 39, 52, 53, 59, 60, 62, 63, 77, 80, 88, 90, 99, 101, 108, 109], "bond": [17, 116], "bot": 64, "bottom": [40, 54, 64, 71], "boundari": [13, 35, 126], "br": 45, "bram": [38, 48, 51, 62, 71, 112], "bu": [36, 64], "buffer": [14, 15, 36, 50, 51, 73, 76, 127], "buse": 63, "carri": [39, 63], "ccm": 78, "center": [40, 79, 89, 100], "check": 35, "clb": [48, 71], "clbll": [90, 101, 109], "clblm": [90, 101, 109], "clexl": 53, "clexm": 53, "clk": 73, "clk_b": [71, 73], "clk_cmt_b": 91, "clk_cmt_t": 91, "clk_dcm_b": 81, "clk_dcm_t": 81, "clk_hrow": [81, 91], "clk_iob_b": [81, 91], "clk_iob_t": [81, 91], "clk_mgt_b": 91, "clk_mgt_t": 91, "clk_t": [71, 73], "clk_term_b": 81, "clk_term_t": 81, "clkb": [40, 48, 64], "clkc": [40, 54], "clkc_50a": 40, "clkl": 40, "clkpad": 71, "clkr": 40, "clkt": [40, 48, 64], "clock": [14, 40, 44, 45, 51, 54, 64, 67, 71, 76, 81, 91], "cmt": [57, 91], "cnr": 71, "column": [51, 127], "combin": 0, "configur": [14, 36, 39, 41, 42, 53, 60, 63, 65, 79, 80, 82, 89, 90, 92, 100, 101, 102, 109, 127], "content": [0, 10, 11, 32, 33, 37, 47, 56, 61, 70, 85, 95, 105, 111, 123, 124], "control": 127, "coolrunn": 11, "cor": [41, 65, 82, 92, 102], "cor1": [42, 92, 102], "cor2": 42, "core": [75, 97, 98, 107, 113, 114], "corner": [43, 66], "cpld": [11, 33, 124], "ctl": [41, 42, 65, 82, 92, 102], "ctl1": 102, "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 66, 117, 118, 119, 120, 121, 122], "databas": [10, 17, 32, 116, 123], "dcm": [44, 45, 48, 51, 64, 67, 71, 81, 83], "dcm_bufpll": 54, "dcmconn": 64, "default": [38, 40], "delai": [96, 106, 112], "deskew_adjust": [44, 45, 67], "devic": [10, 12, 14, 17, 32, 34, 36, 49, 51, 72, 76, 116, 123, 125, 127], "digit": [44, 45, 67], "distribut": [40, 64], "divid": 14, "dr": 35, "dsp": [42, 46, 48, 51, 55, 84, 93, 103, 110], "dual": [39, 63], "dummi": 48, "e": 71, "ecc": 77, "enabl": 15, "enter": 35, "eras": 35, "ethernet": [94, 104], "exit": 35, "export": 36, "express": [58, 97, 107, 113, 114], "fb": [14, 15, 16, 36, 115, 127], "fclk": 127, "fifo": 77, "flip": 36, "flop": 36, "format": [15, 16], "fpga": 37, "frequenc": 35, "fuse": [15, 16, 35, 36, 115], "gate": [14, 36], "gclkc": 64, "gclkh": [40, 64], "gclkvc": 40, "gclkvm": 40, "gen2": 113, "gen3": 114, "gener": [42, 48, 51, 57, 71, 76, 86], "geometri": [51, 76], "gigabit": [68, 69], "gigabit10": 69, "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 115, 117, 118, 119, 120, 121, 122], "gt": 71, "hard": [74, 75], "hc_opt": 42, "hclk": [54, 81, 91], "hclk_center": 81, "hclk_center_above_cfg": 81, "hclk_cmt": 91, "hclk_cmt_ioi": 91, "hclk_dcm": 81, "hclk_dcmiob": 81, "hclk_iobdcm": 81, "hclk_ioi": 91, "hclk_ioi_botcen": 91, "hclk_ioi_cent": 91, "hclk_ioi_cmt": 91, "hclk_ioi_topcen": 91, "hclk_iois_dci": 81, "hclk_iois_lvd": 81, "hclk_row": 54, "hclk_term_l": 81, "hclk_term_r": 81, "hole": [71, 76], "horizont": 51, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 66, 73, 117, 118, 119, 120, 121, 122], "ibuf": 23, "idcod": [35, 126], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 115, 117, 118, 119, 120, 121, 122], "input": [14, 15, 16, 36, 48, 50, 71, 73, 127], "instruct": [13, 35, 126], "int": [48, 71], "interconnect": [40, 48, 54, 57, 64, 71, 81, 86, 91, 96, 106, 112], "interfac": [13, 35, 48, 50, 57, 71, 73, 86, 126], "intf": [48, 57, 71, 96, 106, 112], "introduct": [12, 34, 49, 72, 125], "io": [51, 76, 81, 91], "iob": [2, 3, 6, 7, 14, 50, 73, 81, 91, 115, 127], "ioi": [48, 50, 57, 71, 73], "ir": [13, 35, 126], "isp": [13, 35, 126], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 115, 116, 117, 118, 119, 120, 121, 122], "jtag": [13, 35, 126], "keeper": 36, "l": 73, "l1": [50, 73], "l2": [50, 73], "l3": 50, "l4": 50, "lb": 45, "left": [40, 43, 54, 59, 66], "level": [17, 116], "line": 48, "ll": [43, 66], "llh": 48, "llv": 48, "local": 127, "logic": [39, 53, 60, 63, 74, 76, 80, 90, 101, 109], "long": 48, "lower": [43, 66], "lr": [43, 48, 50, 66], "lt": 45, "lut": [39, 63], "lut2": 127, "mac": [94, 104], "macrocel": [14, 15, 16, 36, 115, 127], "manag": [44, 45, 67], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 115, 117, 118, 119, 120, 121, 122], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "mgt": [81, 91], "middl": 59, "misc": [14, 36, 127], "mode": [35, 42, 77], "monitor": 87, "mult": 62, "multi": [68, 69], "multiplex": [39, 48, 63, 71], "mux": [81, 91], "n": [40, 71], "network": [14, 36, 127], "node": [81, 91], "normal": 57, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 43, 50, 66, 73, 117, 118, 119, 120, 121, 122], "option": [38, 40], "output": [14, 36, 39, 48, 50, 63, 64, 71, 73, 127], "overview": [14, 36, 127], "packag": [12, 34, 125], "part": [17, 116], "pci": [58, 74, 76, 97, 107, 113, 114], "pci_ce_delai": 54, "pcie_l": 113, "pcie_r": 113, "pcilogics": 54, "per": [15, 16], "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 117, 118, 119, 120, 121, 122, 125], "pll_bufpll_b": 54, "pll_bufpll_out0": 54, "pll_bufpll_out1": 54, "pll_bufpll_t": 54, "pma_spe": 69, "pmviob": 100, "port": [39, 63], "powerdown": 42, "powerpc": [71, 75, 76, 98], "ppc": 71, "primari": 51, "primit": [48, 71], "pro": [66, 68, 69, 73], "product": [14, 15, 16, 36, 63, 115, 127], "program": [13, 35, 126], "project": 0, "protect": 35, "pt": 36, "pu_gt": 42, "pu_gw": 42, "pull": 36, "r": 73, "r1": [50, 73], "r2": [50, 73], "r3": 50, "r4": 50, "ram": [38, 39, 52, 59, 62, 63, 77, 88, 99, 108], "randor": 39, "randor_init": 39, "rb": 45, "read": 35, "regist": [13, 14, 35, 39, 41, 42, 63, 65, 82, 92, 102, 126, 127], "repeat": [81, 91], "reserved_andor": 39, "right": [40, 43, 54, 59, 66], "row": [40, 51, 64, 76, 81, 127], "rt": 45, "s3": [38, 40, 41, 43, 44, 48, 50], "s3a": [38, 40, 42, 43, 48, 50], "s3adsp": [38, 48], "s3e": [38, 40, 41, 43, 45, 48, 50], "scan": [13, 35, 126], "schema": [17, 116], "secondari": [40, 51], "sequenc": [13, 35, 126], "seu_opt": 42, "shift": [39, 63], "side": 59, "singl": [39, 63], "sourc": [40, 64], "spartan": [39, 41, 42, 43, 44, 45, 47, 50, 51, 56, 62], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 116, 117, 118, 119, 120, 121, 122], "spine": [40, 51, 64, 71, 76, 81, 91], "splitter": 48, "structur": [1, 14, 15, 16, 36, 51, 76, 115, 127], "sum": [14, 36, 63, 115, 127], "system": 87, "t": [50, 64, 68, 69, 73], "t0": 71, "t1": 50, "t123": 71, "t2": [50, 73], "t3": 50, "t4": 50, "tabl": [49, 72], "tb": 48, "tbuf": 63, "tclkpad": 71, "term": [14, 15, 16, 36, 71, 115, 127], "termin": [48, 71, 81], "testmod": 102, "tile": [17, 40, 48, 54, 57, 64, 71, 86, 116], "timer": [92, 102], "tl": 45, "todo": [1, 12, 13, 14, 35, 36, 39, 40, 41, 42, 43, 44, 45, 46, 47, 49, 50, 51, 53, 55, 56, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 81, 82, 85, 86, 89, 90, 91, 92, 95, 96, 100, 101, 102, 105, 106, 109, 111, 112, 126, 127], "top": [17, 40, 54, 64, 71, 116], "tr": 45, "transceiv": [68, 69], "trim": 102, "tristat": 63, "uim": [15, 23, 36], "ul": [43, 66], "uni": 40, "univers": 127, "unk1c": 102, "up": 36, "upper": [43, 66], "ur": [43, 66], "v2": [64, 66, 67, 71, 73], "v2p": [64, 66, 67, 71, 73], "v2px": 64, "valu": [38, 69], "vertic": 51, "virtex": [39, 59, 60, 61, 62, 66, 68, 69, 70, 73, 85, 95, 105, 111], "w": 71, "wide": [39, 63], "wire": 15, "without": [2, 3, 6, 7, 115], "write": 35, "x": [39, 63, 69], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 117, "xcr3064xl": 118, "xcr3128xl": 119, "xcr3256xl": 120, "xcr3384xl": 121, "xcr3512xl": 122, "xilinx": [11, 33, 37, 124], "xor": [14, 36], "xpla3": 124, "xv": [16, 35, 36], "zia": 127}})
\ No newline at end of file
diff --git a/xilinx/virtex2/config.html b/xilinx/virtex2/config.html
index da877021..e49a04b7 100644
--- a/xilinx/virtex2/config.html
+++ b/xilinx/virtex2/config.html
@@ -279,17 +279,13 @@ <h2><code class="docutils literal notranslate"><span class="pre">CTL</span></cod
 <td><a href="#bits-xc2v-REG.CTL-MISC:SECURITY" title="MISC:SECURITY[0]">MISC:SECURITY[0]</a></td></tr>
 <tr><td>5</td>
 <td><a href="#bits-xc2v-REG.CTL-MISC:SECURITY" title="MISC:SECURITY[1]">MISC:SECURITY[1]</a></td></tr>
-<tr><td>6</td>
-<td><a href="#bits-xc2v-REG.CTL-MISC:DECRYPT" title="MISC:DECRYPT">MISC:DECRYPT</a></td></tr>
 </table>
 <div id="bits-xc2v-REG.CTL-MISC:BCLK_TEST"></div>
-<div id="bits-xc2v-REG.CTL-MISC:DECRYPT"></div>
 <div id="bits-xc2v-REG.CTL-MISC:GTS_USR_B"></div>
 <div id="bits-xc2v-REG.CTL-MISC:PERSIST"></div>
 <div id="bits-xc2v-REG.CTL-MISC:VGG_TEST"></div>
 <table class="docutils align-default prjcombine-enum">
 <tr><th>MISC:BCLK_TEST</th><th>[0, 0, 2]</th></tr>
-<tr><th>MISC:DECRYPT</th><th>[0, 0, 6]</th></tr>
 <tr><th>MISC:GTS_USR_B</th><th>[0, 0, 0]</th></tr>
 <tr><th>MISC:PERSIST</th><th>[0, 0, 3]</th></tr>
 <tr><th>MISC:VGG_TEST</th><th>[0, 0, 1]</th></tr>
diff --git a/xilinx/virtex4/config.html b/xilinx/virtex4/config.html
index 4004a7cc..7d1f0eb3 100644
--- a/xilinx/virtex4/config.html
+++ b/xilinx/virtex4/config.html
@@ -274,7 +274,7 @@ <h2><code class="docutils literal notranslate"><span class="pre">CTL</span></cod
 <tr><td>5</td>
 <td><a href="#bits-xc4v-REG.CTL-MISC:SECURITY" title="MISC:SECURITY[1]">MISC:SECURITY[1]</a></td></tr>
 <tr><td>6</td>
-<td><a href="#bits-xc4v-REG.CTL-MISC:DECRYPT" title="MISC:DECRYPT">MISC:DECRYPT</a></td></tr>
+<td><a href="#bits-xc4v-REG.CTL-MISC:ENCRYPT" title="MISC:ENCRYPT">MISC:ENCRYPT</a></td></tr>
 <tr><td>7</td>
 <td>-</td></tr>
 <tr><td>8</td>
@@ -324,13 +324,13 @@ <h2><code class="docutils literal notranslate"><span class="pre">CTL</span></cod
 <tr><td>30</td>
 <td><a href="#bits-xc4v-REG.CTL-MISC:ICAP_SELECT" title="MISC:ICAP_SELECT">MISC:ICAP_SELECT</a></td></tr>
 </table>
-<div id="bits-xc4v-REG.CTL-MISC:DECRYPT"></div>
+<div id="bits-xc4v-REG.CTL-MISC:ENCRYPT"></div>
 <div id="bits-xc4v-REG.CTL-MISC:EN_VTEST"></div>
 <div id="bits-xc4v-REG.CTL-MISC:GTS_USR_B"></div>
 <div id="bits-xc4v-REG.CTL-MISC:PERSIST"></div>
 <div id="bits-xc4v-REG.CTL-MISC:VGG_TEST"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:DECRYPT</th><th>[0, 0, 6]</th></tr>
+<tr><th>MISC:ENCRYPT</th><th>[0, 0, 6]</th></tr>
 <tr><th>MISC:EN_VTEST</th><th>[0, 0, 1]</th></tr>
 <tr><th>MISC:GTS_USR_B</th><th>[0, 0, 0]</th></tr>
 <tr><th>MISC:PERSIST</th><th>[0, 0, 3]</th></tr>
diff --git a/xilinx/virtex5/config.html b/xilinx/virtex5/config.html
index 42134f82..1562624d 100644
--- a/xilinx/virtex5/config.html
+++ b/xilinx/virtex5/config.html
@@ -361,7 +361,7 @@ <h2><code class="docutils literal notranslate"><span class="pre">CTL</span></cod
 <tr><td>5</td>
 <td><a href="#bits-xc5v-REG.CTL-MISC:SECURITY" title="MISC:SECURITY[1]">MISC:SECURITY[1]</a></td></tr>
 <tr><td>6</td>
-<td><a href="#bits-xc5v-REG.CTL-MISC:DECRYPT" title="MISC:DECRYPT">MISC:DECRYPT</a></td></tr>
+<td><a href="#bits-xc5v-REG.CTL-MISC:ENCRYPT" title="MISC:ENCRYPT">MISC:ENCRYPT</a></td></tr>
 <tr><td>7</td>
 <td>-</td></tr>
 <tr><td>8</td>
@@ -413,12 +413,12 @@ <h2><code class="docutils literal notranslate"><span class="pre">CTL</span></cod
 <tr><td>31</td>
 <td><a href="#bits-xc5v-REG.CTL-MISC:ENCRYPT_KEY_SELECT" title="MISC:ENCRYPT_KEY_SELECT">MISC:ENCRYPT_KEY_SELECT</a></td></tr>
 </table>
-<div id="bits-xc5v-REG.CTL-MISC:DECRYPT"></div>
+<div id="bits-xc5v-REG.CTL-MISC:ENCRYPT"></div>
 <div id="bits-xc5v-REG.CTL-MISC:GTS_USR_B"></div>
 <div id="bits-xc5v-REG.CTL-MISC:OVERTEMP_POWERDOWN"></div>
 <div id="bits-xc5v-REG.CTL-MISC:PERSIST"></div>
 <table class="docutils align-default prjcombine-enum">
-<tr><th>MISC:DECRYPT</th><th>[0, 0, 6]</th></tr>
+<tr><th>MISC:ENCRYPT</th><th>[0, 0, 6]</th></tr>
 <tr><th>MISC:GTS_USR_B</th><th>[0, 0, 0]</th></tr>
 <tr><th>MISC:OVERTEMP_POWERDOWN</th><th>[0, 0, 12]</th></tr>
 <tr><th>MISC:PERSIST</th><th>[0, 0, 3]</th></tr>