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prjunnamed · Sep 14, 2024 · f1b36a0 · f1b36a0
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diff --git a/_sources/xilinx/spartan3/corner.rst.txt b/_sources/xilinx/spartan3/corner.rst.txt
@@ -155,10 +155,7 @@ I/O data — Spartan 3E
 =====================
 
 .. raw:: html
-   :file: ../gen/xc3se-iostd-lvdsbias-0.html
-
-.. raw:: html
-   :file: ../gen/xc3se-iostd-lvdsbias-1.html
+   :file: ../gen/xc3se-iostd-lvdsbias.html
 
 
 I/O data — Spartan 3A

diff --git a/_sources/xilinx/virtex5/clock.rst.txt b/_sources/xilinx/virtex5/clock.rst.txt
@@ -132,3 +132,19 @@ IO clock nodes
 
 .. raw:: html
    :file: ../gen/tile-xc5v-HCLK_CMT.html
+
+
+I/O standard data
+=================
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-lvdsbias.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-lvdiv2.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-mask-term-vcc.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-dci-mask-term-split.html
diff --git a/_sources/xilinx/virtex5/io.rst.txt b/_sources/xilinx/virtex5/io.rst.txt
@@ -148,5 +148,17 @@ The ``SYSMON`` present on the device can use up to 16 IOB pairs from the left I/
 Bitstream
 =========
 
+.. raw:: html
+   :file: ../gen/xc5v-iostd-drive.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-slew.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-misc.html
+
+.. raw:: html
+   :file: ../gen/xc5v-iostd-lvds.html
+
 .. raw:: html
    :file: ../gen/tile-xc5v-IO.html
diff --git a/_sources/xilinx/virtex6/gtx.rst.txt b/_sources/xilinx/virtex6/gtx.rst.txt
@@ -0,0 +1,13 @@
+.. _virtex6-gtx:
+
+GTX transceivers
+################
+
+.. todo:: document
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen/tile-xc6v-GTX.html
diff --git a/_sources/xilinx/virtex6/index.rst.txt b/_sources/xilinx/virtex6/index.rst.txt
@@ -16,4 +16,5 @@ Virtex 6
    center
    emac
    pcie
+   gtx
    config
diff --git a/objects.inv b/objects.inv
diff --git a/searchindex.js b/searchindex.js
diff --git a/xilinx/index.html b/xilinx/index.html
@@ -209,6 +209,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
 <li class="toctree-l2"><a class="reference internal" href="virtex6/center.html">Configuration Center</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/emac.html">Ethernet MACs</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/pcie.html">PCI Express cores</a></li>
+<li class="toctree-l2"><a class="reference internal" href="virtex6/gtx.html">GTX transceivers</a></li>
 <li class="toctree-l2"><a class="reference internal" href="virtex6/config.html">Configuration registers</a></li>
 </ul>
 </li>

diff --git a/xilinx/spartan3/corner.html b/xilinx/spartan3/corner.html
diff --git a/xilinx/virtex2/corner.html b/xilinx/virtex2/corner.html
diff --git a/xilinx/virtex4/io.html b/xilinx/virtex4/io.html
@@ -222,10 +222,6 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>GTLP</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>GTLP_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>GTL_DCI</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
-<tr><td>HSLVDCI_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>HSLVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>HSTL_I</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td></tr>
 <tr><td>HSTL_II</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>
 <tr><td>HSTL_III</td><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
@@ -271,13 +267,6 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>LVCMOS33.4</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
 <tr><td>LVCMOS33.6</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
 <tr><td>LVCMOS33.8</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_33</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_15</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_18</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
-<tr><td>LVDCI_DV2_25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
 <tr><td>LVPECL_25</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td></tr>
 <tr><td>LVTTL.12</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
 <tr><td>LVTTL.16</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td></tr>

diff --git a/xilinx/virtex5/center.html b/xilinx/virtex5/center.html
@@ -249,7 +249,13 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-JTAGPPC:NUM_PPC" title="JTAGPPC:NUM_PPC[2]">JTAGPPC:NUM_PPC[2]</a></td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
-<tr><th colspan="1">CFG bittile 9</th></tr><tr><th rowspan="2">Row</th><th colspan="0">Column</th></tr><tr></tr>
+<tr><th colspan="29">CFG bittile 9</th></tr><tr><th rowspan="2">Row</th><th colspan="28">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE[1]">MISC:DCI_CLK_ENABLE[1]</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc5v-CFG-MISC:DCI_CLK_ENABLE" title="MISC:DCI_CLK_ENABLE[0]">MISC:DCI_CLK_ENABLE[0]</a></td><td>-</td></tr>
 </table>
 <table class="docutils align-default prjcombine-tile">
 <tr><th colspan="29">CFG bittile 10</th></tr><tr><th rowspan="2">Row</th><th colspan="28">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th><th>20</th><th>21</th><th>22</th><th>23</th><th>24</th><th>25</th><th>26</th><th>27</th></tr>
@@ -2545,6 +2551,11 @@ <h2>Bitstream<a class="headerlink" href="#bitstream" title="Link to this heading
 <tr><td>3</td><td>0</td><td>1</td><td>1</td></tr>
 <tr><td>4</td><td>1</td><td>0</td><td>0</td></tr>
 </table>
+<div id="bits-xc5v-CFG-MISC:DCI_CLK_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DCI_CLK_ENABLE</th><th>[9, 27, 1]</th><th>[9, 26, 2]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
 <div id="bits-xc5v-CFG-MISC:CCLKPIN"></div>
 <div id="bits-xc5v-CFG-MISC:DONEPIN"></div>
 <div id="bits-xc5v-CFG-MISC:INITPIN"></div>
-Original file line number
+Diff line change
@@ Expand Up / @@ -16,4 +16,5 @@ Virtex 6 @@
        center
        emac
        pcie
+       gtx
        config